Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
ff37e337 S |
21 | static void ath_update_txpow(struct ath_softc *sc) |
22 | { | |
cbe61d8a | 23 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 | 24 | |
17d7904d S |
25 | if (sc->curtxpow != sc->config.txpowlimit) { |
26 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 | 27 | /* read back in case value is clamped */ |
9cc3271f | 28 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; |
ff37e337 S |
29 | } |
30 | } | |
31 | ||
32 | static u8 parse_mpdudensity(u8 mpdudensity) | |
33 | { | |
34 | /* | |
35 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
36 | * 0 for no restriction | |
37 | * 1 for 1/4 us | |
38 | * 2 for 1/2 us | |
39 | * 3 for 1 us | |
40 | * 4 for 2 us | |
41 | * 5 for 4 us | |
42 | * 6 for 8 us | |
43 | * 7 for 16 us | |
44 | */ | |
45 | switch (mpdudensity) { | |
46 | case 0: | |
47 | return 0; | |
48 | case 1: | |
49 | case 2: | |
50 | case 3: | |
51 | /* Our lower layer calculations limit our precision to | |
52 | 1 microsecond */ | |
53 | return 1; | |
54 | case 4: | |
55 | return 2; | |
56 | case 5: | |
57 | return 4; | |
58 | case 6: | |
59 | return 8; | |
60 | case 7: | |
61 | return 16; | |
62 | default: | |
63 | return 0; | |
64 | } | |
65 | } | |
66 | ||
82880a7c VT |
67 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
68 | struct ieee80211_hw *hw) | |
69 | { | |
70 | struct ieee80211_channel *curchan = hw->conf.channel; | |
71 | struct ath9k_channel *channel; | |
72 | u8 chan_idx; | |
73 | ||
74 | chan_idx = curchan->hw_value; | |
75 | channel = &sc->sc_ah->channels[chan_idx]; | |
76 | ath9k_update_ichannel(sc, hw, channel); | |
77 | return channel; | |
78 | } | |
79 | ||
55624204 | 80 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
81 | { |
82 | unsigned long flags; | |
83 | bool ret; | |
84 | ||
9ecdef4b LR |
85 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
86 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
87 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
88 | |
89 | return ret; | |
90 | } | |
91 | ||
a91d75ae LR |
92 | void ath9k_ps_wakeup(struct ath_softc *sc) |
93 | { | |
898c914a | 94 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 95 | unsigned long flags; |
fbb078fc | 96 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
97 | |
98 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
99 | if (++sc->ps_usecount != 1) | |
100 | goto unlock; | |
101 | ||
fbb078fc | 102 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 103 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 104 | |
898c914a FF |
105 | /* |
106 | * While the hardware is asleep, the cycle counters contain no | |
107 | * useful data. Better clear them now so that they don't mess up | |
108 | * survey data results. | |
109 | */ | |
fbb078fc FF |
110 | if (power_mode != ATH9K_PM_AWAKE) { |
111 | spin_lock(&common->cc_lock); | |
112 | ath_hw_cycle_counters_update(common); | |
113 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
114 | spin_unlock(&common->cc_lock); | |
115 | } | |
898c914a | 116 | |
a91d75ae LR |
117 | unlock: |
118 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
119 | } | |
120 | ||
121 | void ath9k_ps_restore(struct ath_softc *sc) | |
122 | { | |
898c914a | 123 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae LR |
124 | unsigned long flags; |
125 | ||
126 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
127 | if (--sc->ps_usecount != 0) | |
128 | goto unlock; | |
129 | ||
898c914a FF |
130 | spin_lock(&common->cc_lock); |
131 | ath_hw_cycle_counters_update(common); | |
132 | spin_unlock(&common->cc_lock); | |
133 | ||
1dbfd9d4 VN |
134 | if (sc->ps_idle) |
135 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
136 | else if (sc->ps_enabled && | |
137 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
138 | PS_WAIT_FOR_CAB | |
139 | PS_WAIT_FOR_PSPOLL_DATA | | |
140 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 141 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
142 | |
143 | unlock: | |
144 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
145 | } | |
146 | ||
5ee08656 FF |
147 | static void ath_start_ani(struct ath_common *common) |
148 | { | |
149 | struct ath_hw *ah = common->ah; | |
150 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
151 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
152 | ||
153 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
154 | return; | |
155 | ||
156 | if (sc->sc_flags & SC_OP_OFFCHANNEL) | |
157 | return; | |
158 | ||
159 | common->ani.longcal_timer = timestamp; | |
160 | common->ani.shortcal_timer = timestamp; | |
161 | common->ani.checkani_timer = timestamp; | |
162 | ||
163 | mod_timer(&common->ani.timer, | |
164 | jiffies + | |
165 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
166 | } | |
167 | ||
3430098a FF |
168 | static void ath_update_survey_nf(struct ath_softc *sc, int channel) |
169 | { | |
170 | struct ath_hw *ah = sc->sc_ah; | |
171 | struct ath9k_channel *chan = &ah->channels[channel]; | |
172 | struct survey_info *survey = &sc->survey[channel]; | |
173 | ||
174 | if (chan->noisefloor) { | |
175 | survey->filled |= SURVEY_INFO_NOISE_DBM; | |
176 | survey->noise = chan->noisefloor; | |
177 | } | |
178 | } | |
179 | ||
180 | static void ath_update_survey_stats(struct ath_softc *sc) | |
181 | { | |
182 | struct ath_hw *ah = sc->sc_ah; | |
183 | struct ath_common *common = ath9k_hw_common(ah); | |
184 | int pos = ah->curchan - &ah->channels[0]; | |
185 | struct survey_info *survey = &sc->survey[pos]; | |
186 | struct ath_cycle_counters *cc = &common->cc_survey; | |
187 | unsigned int div = common->clockrate * 1000; | |
188 | ||
0845735e FF |
189 | if (!ah->curchan) |
190 | return; | |
191 | ||
898c914a FF |
192 | if (ah->power_mode == ATH9K_PM_AWAKE) |
193 | ath_hw_cycle_counters_update(common); | |
3430098a FF |
194 | |
195 | if (cc->cycles > 0) { | |
196 | survey->filled |= SURVEY_INFO_CHANNEL_TIME | | |
197 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
198 | SURVEY_INFO_CHANNEL_TIME_RX | | |
199 | SURVEY_INFO_CHANNEL_TIME_TX; | |
200 | survey->channel_time += cc->cycles / div; | |
201 | survey->channel_time_busy += cc->rx_busy / div; | |
202 | survey->channel_time_rx += cc->rx_frame / div; | |
203 | survey->channel_time_tx += cc->tx_frame / div; | |
204 | } | |
205 | memset(cc, 0, sizeof(*cc)); | |
206 | ||
207 | ath_update_survey_nf(sc, pos); | |
208 | } | |
209 | ||
ff37e337 S |
210 | /* |
211 | * Set/change channels. If the channel is really being changed, it's done | |
212 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
213 | * DMA, then restart stuff. | |
214 | */ | |
0e2dedf9 JM |
215 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
216 | struct ath9k_channel *hchan) | |
ff37e337 | 217 | { |
20bd2a09 | 218 | struct ath_wiphy *aphy = hw->priv; |
cbe61d8a | 219 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 220 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 221 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 222 | bool fastcc = true, stopped; |
ae8d2858 | 223 | struct ieee80211_channel *channel = hw->conf.channel; |
20bd2a09 | 224 | struct ath9k_hw_cal_data *caldata = NULL; |
ae8d2858 | 225 | int r; |
ff37e337 S |
226 | |
227 | if (sc->sc_flags & SC_OP_INVALID) | |
228 | return -EIO; | |
229 | ||
5ee08656 FF |
230 | del_timer_sync(&common->ani.timer); |
231 | cancel_work_sync(&sc->paprd_work); | |
232 | cancel_work_sync(&sc->hw_check_work); | |
233 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
234 | ||
3cbb5dd7 VN |
235 | ath9k_ps_wakeup(sc); |
236 | ||
c0d7c7af LR |
237 | /* |
238 | * This is only performed if the channel settings have | |
239 | * actually changed. | |
240 | * | |
241 | * To switch channels clear any pending DMA operations; | |
242 | * wait long enough for the RX fifo to drain, reset the | |
243 | * hardware at the new frequency, and then re-enable | |
244 | * the relevant bits of the h/w. | |
245 | */ | |
246 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 247 | ath_drain_all_txq(sc, false); |
5e848f78 LR |
248 | |
249 | spin_lock_bh(&sc->rx.pcu_lock); | |
250 | ||
c0d7c7af | 251 | stopped = ath_stoprecv(sc); |
ff37e337 | 252 | |
c0d7c7af LR |
253 | /* XXX: do not flush receive queue here. We don't want |
254 | * to flush data frames already in queue because of | |
255 | * changing channel. */ | |
ff37e337 | 256 | |
5ee08656 | 257 | if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL)) |
c0d7c7af LR |
258 | fastcc = false; |
259 | ||
20bd2a09 FF |
260 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) |
261 | caldata = &aphy->caldata; | |
262 | ||
c46917bb | 263 | ath_print(common, ATH_DBG_CONFIG, |
1e51b2ff | 264 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", |
c46917bb | 265 | sc->sc_ah->curchan->channel, |
1e51b2ff LR |
266 | channel->center_freq, conf_is_ht40(conf), |
267 | fastcc); | |
ff37e337 | 268 | |
c0d7c7af LR |
269 | spin_lock_bh(&sc->sc_resetlock); |
270 | ||
20bd2a09 | 271 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); |
c0d7c7af | 272 | if (r) { |
c46917bb | 273 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 274 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
275 | "reset status %d\n", |
276 | channel->center_freq, r); | |
c0d7c7af | 277 | spin_unlock_bh(&sc->sc_resetlock); |
5e848f78 | 278 | spin_unlock_bh(&sc->rx.pcu_lock); |
3989279c | 279 | goto ps_restore; |
ff37e337 | 280 | } |
c0d7c7af LR |
281 | spin_unlock_bh(&sc->sc_resetlock); |
282 | ||
c0d7c7af | 283 | if (ath_startrecv(sc) != 0) { |
c46917bb LR |
284 | ath_print(common, ATH_DBG_FATAL, |
285 | "Unable to restart recv logic\n"); | |
3989279c | 286 | r = -EIO; |
5e848f78 | 287 | spin_unlock_bh(&sc->rx.pcu_lock); |
3989279c | 288 | goto ps_restore; |
c0d7c7af LR |
289 | } |
290 | ||
5e848f78 LR |
291 | spin_unlock_bh(&sc->rx.pcu_lock); |
292 | ||
c0d7c7af | 293 | ath_update_txpow(sc); |
3069168c | 294 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c | 295 | |
48a6a468 LR |
296 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) { |
297 | ath_beacon_config(sc, NULL); | |
5ee08656 | 298 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
48a6a468 | 299 | ath_start_ani(common); |
5ee08656 FF |
300 | } |
301 | ||
3989279c | 302 | ps_restore: |
3cbb5dd7 | 303 | ath9k_ps_restore(sc); |
3989279c | 304 | return r; |
ff37e337 S |
305 | } |
306 | ||
9f42c2b6 FF |
307 | static void ath_paprd_activate(struct ath_softc *sc) |
308 | { | |
309 | struct ath_hw *ah = sc->sc_ah; | |
20bd2a09 | 310 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 311 | struct ath_common *common = ath9k_hw_common(ah); |
9f42c2b6 FF |
312 | int chain; |
313 | ||
20bd2a09 | 314 | if (!caldata || !caldata->paprd_done) |
9f42c2b6 FF |
315 | return; |
316 | ||
317 | ath9k_ps_wakeup(sc); | |
ddfef792 | 318 | ar9003_paprd_enable(ah, false); |
9f42c2b6 | 319 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
9094537c | 320 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
321 | continue; |
322 | ||
20bd2a09 | 323 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
9f42c2b6 FF |
324 | } |
325 | ||
326 | ar9003_paprd_enable(ah, true); | |
327 | ath9k_ps_restore(sc); | |
328 | } | |
329 | ||
330 | void ath_paprd_calibrate(struct work_struct *work) | |
331 | { | |
332 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
333 | struct ieee80211_hw *hw = sc->hw; | |
334 | struct ath_hw *ah = sc->sc_ah; | |
335 | struct ieee80211_hdr *hdr; | |
336 | struct sk_buff *skb = NULL; | |
337 | struct ieee80211_tx_info *tx_info; | |
338 | int band = hw->conf.channel->band; | |
339 | struct ieee80211_supported_band *sband = &sc->sbands[band]; | |
340 | struct ath_tx_control txctl; | |
20bd2a09 | 341 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 342 | struct ath_common *common = ath9k_hw_common(ah); |
9f42c2b6 FF |
343 | int qnum, ftype; |
344 | int chain_ok = 0; | |
345 | int chain; | |
346 | int len = 1800; | |
347 | int time_left; | |
348 | int i; | |
349 | ||
20bd2a09 FF |
350 | if (!caldata) |
351 | return; | |
352 | ||
9f42c2b6 FF |
353 | skb = alloc_skb(len, GFP_KERNEL); |
354 | if (!skb) | |
355 | return; | |
356 | ||
357 | tx_info = IEEE80211_SKB_CB(skb); | |
358 | ||
359 | skb_put(skb, len); | |
360 | memset(skb->data, 0, len); | |
361 | hdr = (struct ieee80211_hdr *)skb->data; | |
362 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
363 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 364 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
365 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
366 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
367 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
368 | ||
369 | memset(&txctl, 0, sizeof(txctl)); | |
370 | qnum = sc->tx.hwq_map[WME_AC_BE]; | |
371 | txctl.txq = &sc->tx.txq[qnum]; | |
372 | ||
47399f1a | 373 | ath9k_ps_wakeup(sc); |
9f42c2b6 FF |
374 | ar9003_paprd_init_table(ah); |
375 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { | |
9094537c | 376 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
377 | continue; |
378 | ||
379 | chain_ok = 0; | |
380 | memset(tx_info, 0, sizeof(*tx_info)); | |
381 | tx_info->band = band; | |
382 | ||
383 | for (i = 0; i < 4; i++) { | |
384 | tx_info->control.rates[i].idx = sband->n_bitrates - 1; | |
385 | tx_info->control.rates[i].count = 6; | |
386 | } | |
387 | ||
388 | init_completion(&sc->paprd_complete); | |
389 | ar9003_paprd_setup_gain_table(ah, chain); | |
390 | txctl.paprd = BIT(chain); | |
391 | if (ath_tx_start(hw, skb, &txctl) != 0) | |
392 | break; | |
393 | ||
394 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
ca369eb4 | 395 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); |
9f42c2b6 FF |
396 | if (!time_left) { |
397 | ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | |
398 | "Timeout waiting for paprd training on " | |
399 | "TX chain %d\n", | |
400 | chain); | |
ca369eb4 | 401 | goto fail_paprd; |
9f42c2b6 FF |
402 | } |
403 | ||
404 | if (!ar9003_paprd_is_done(ah)) | |
405 | break; | |
406 | ||
20bd2a09 | 407 | if (ar9003_paprd_create_curve(ah, caldata, chain) != 0) |
9f42c2b6 FF |
408 | break; |
409 | ||
410 | chain_ok = 1; | |
411 | } | |
412 | kfree_skb(skb); | |
413 | ||
414 | if (chain_ok) { | |
20bd2a09 | 415 | caldata->paprd_done = true; |
9f42c2b6 FF |
416 | ath_paprd_activate(sc); |
417 | } | |
418 | ||
ca369eb4 | 419 | fail_paprd: |
9f42c2b6 FF |
420 | ath9k_ps_restore(sc); |
421 | } | |
422 | ||
ff37e337 S |
423 | /* |
424 | * This routine performs the periodic noise floor calibration function | |
425 | * that is used to adjust and optimize the chip performance. This | |
426 | * takes environmental changes (location, temperature) into account. | |
427 | * When the task is complete, it reschedules itself depending on the | |
428 | * appropriate interval that was calculated. | |
429 | */ | |
55624204 | 430 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 431 | { |
20977d3e S |
432 | struct ath_softc *sc = (struct ath_softc *)data; |
433 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 434 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
435 | bool longcal = false; |
436 | bool shortcal = false; | |
437 | bool aniflag = false; | |
438 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
6044474e | 439 | u32 cal_interval, short_cal_interval, long_cal_interval; |
b5bfc568 | 440 | unsigned long flags; |
6044474e FF |
441 | |
442 | if (ah->caldata && ah->caldata->nfcal_interference) | |
443 | long_cal_interval = ATH_LONG_CALINTERVAL_INT; | |
444 | else | |
445 | long_cal_interval = ATH_LONG_CALINTERVAL; | |
ff37e337 | 446 | |
20977d3e S |
447 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
448 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 449 | |
1ffc1c61 JM |
450 | /* Only calibrate if awake */ |
451 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
452 | goto set_timer; | |
453 | ||
454 | ath9k_ps_wakeup(sc); | |
455 | ||
ff37e337 | 456 | /* Long calibration runs independently of short calibration. */ |
6044474e | 457 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
ff37e337 | 458 | longcal = true; |
c46917bb | 459 | ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 460 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
461 | } |
462 | ||
17d7904d | 463 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
464 | if (!common->ani.caldone) { |
465 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 466 | shortcal = true; |
c46917bb LR |
467 | ath_print(common, ATH_DBG_ANI, |
468 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
469 | common->ani.shortcal_timer = timestamp; |
470 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
471 | } |
472 | } else { | |
3d536acf | 473 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 474 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
475 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
476 | if (common->ani.caldone) | |
477 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
478 | } |
479 | } | |
480 | ||
481 | /* Verify whether we must check ANI */ | |
e36b27af LR |
482 | if ((timestamp - common->ani.checkani_timer) >= |
483 | ah->config.ani_poll_interval) { | |
ff37e337 | 484 | aniflag = true; |
3d536acf | 485 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
486 | } |
487 | ||
488 | /* Skip all processing if there's nothing to do. */ | |
489 | if (longcal || shortcal || aniflag) { | |
490 | /* Call ANI routine if necessary */ | |
b5bfc568 FF |
491 | if (aniflag) { |
492 | spin_lock_irqsave(&common->cc_lock, flags); | |
22e66a4c | 493 | ath9k_hw_ani_monitor(ah, ah->curchan); |
3430098a | 494 | ath_update_survey_stats(sc); |
b5bfc568 FF |
495 | spin_unlock_irqrestore(&common->cc_lock, flags); |
496 | } | |
ff37e337 S |
497 | |
498 | /* Perform calibration if necessary */ | |
499 | if (longcal || shortcal) { | |
3d536acf | 500 | common->ani.caldone = |
43c27613 LR |
501 | ath9k_hw_calibrate(ah, |
502 | ah->curchan, | |
503 | common->rx_chainmask, | |
504 | longcal); | |
ff37e337 S |
505 | } |
506 | } | |
507 | ||
1ffc1c61 JM |
508 | ath9k_ps_restore(sc); |
509 | ||
20977d3e | 510 | set_timer: |
ff37e337 S |
511 | /* |
512 | * Set timer interval based on previous results. | |
513 | * The interval must be the shortest necessary to satisfy ANI, | |
514 | * short calibration and long calibration. | |
515 | */ | |
aac9207e | 516 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 517 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
518 | cal_interval = min(cal_interval, |
519 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 520 | if (!common->ani.caldone) |
20977d3e | 521 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 522 | |
3d536acf | 523 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
20bd2a09 FF |
524 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { |
525 | if (!ah->caldata->paprd_done) | |
9f42c2b6 FF |
526 | ieee80211_queue_work(sc->hw, &sc->paprd_work); |
527 | else | |
528 | ath_paprd_activate(sc); | |
529 | } | |
ff37e337 S |
530 | } |
531 | ||
532 | /* | |
533 | * Update tx/rx chainmask. For legacy association, | |
534 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
535 | * the chainmask configuration, for bt coexistence, use |
536 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 537 | */ |
0e2dedf9 | 538 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 539 | { |
af03abec | 540 | struct ath_hw *ah = sc->sc_ah; |
43c27613 | 541 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 542 | |
5ee08656 | 543 | if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht || |
766ec4a9 | 544 | (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { |
43c27613 LR |
545 | common->tx_chainmask = ah->caps.tx_chainmask; |
546 | common->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 | 547 | } else { |
43c27613 LR |
548 | common->tx_chainmask = 1; |
549 | common->rx_chainmask = 1; | |
ff37e337 S |
550 | } |
551 | ||
43c27613 | 552 | ath_print(common, ATH_DBG_CONFIG, |
c46917bb | 553 | "tx chmask: %d, rx chmask: %d\n", |
43c27613 LR |
554 | common->tx_chainmask, |
555 | common->rx_chainmask); | |
ff37e337 S |
556 | } |
557 | ||
558 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
559 | { | |
560 | struct ath_node *an; | |
561 | ||
562 | an = (struct ath_node *)sta->drv_priv; | |
563 | ||
87792efc | 564 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 565 | ath_tx_node_init(sc, an); |
9e98ac65 | 566 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
567 | sta->ht_cap.ampdu_factor); |
568 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
a59b5a5e | 569 | an->last_rssi = ATH_RSSI_DUMMY_MARKER; |
87792efc | 570 | } |
ff37e337 S |
571 | } |
572 | ||
573 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
574 | { | |
575 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
576 | ||
577 | if (sc->sc_flags & SC_OP_TXAGGR) | |
578 | ath_tx_node_cleanup(sc, an); | |
579 | } | |
580 | ||
347809fc FF |
581 | void ath_hw_check(struct work_struct *work) |
582 | { | |
583 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
584 | int i; | |
585 | ||
586 | ath9k_ps_wakeup(sc); | |
587 | ||
588 | for (i = 0; i < 3; i++) { | |
589 | if (ath9k_hw_check_alive(sc->sc_ah)) | |
590 | goto out; | |
591 | ||
592 | msleep(1); | |
593 | } | |
fac6b6a0 | 594 | ath_reset(sc, true); |
347809fc FF |
595 | |
596 | out: | |
597 | ath9k_ps_restore(sc); | |
598 | } | |
599 | ||
55624204 | 600 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
601 | { |
602 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 603 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 604 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 605 | |
17d7904d | 606 | u32 status = sc->intrstatus; |
b5c80475 | 607 | u32 rxmask; |
ff37e337 | 608 | |
153e080d VT |
609 | ath9k_ps_wakeup(sc); |
610 | ||
347809fc | 611 | if (status & ATH9K_INT_FATAL) { |
fac6b6a0 | 612 | ath_reset(sc, true); |
153e080d | 613 | ath9k_ps_restore(sc); |
ff37e337 | 614 | return; |
063d8be3 | 615 | } |
ff37e337 | 616 | |
347809fc FF |
617 | if (!ath9k_hw_check_alive(ah)) |
618 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); | |
619 | ||
b5c80475 FF |
620 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
621 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
622 | ATH9K_INT_RXORN); | |
623 | else | |
624 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
625 | ||
626 | if (status & rxmask) { | |
b79b33c4 | 627 | spin_lock_bh(&sc->rx.pcu_lock); |
b5c80475 FF |
628 | |
629 | /* Check for high priority Rx first */ | |
630 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
631 | (status & ATH9K_INT_RXHP)) | |
632 | ath_rx_tasklet(sc, 0, true); | |
633 | ||
634 | ath_rx_tasklet(sc, 0, false); | |
b79b33c4 | 635 | spin_unlock_bh(&sc->rx.pcu_lock); |
ff37e337 S |
636 | } |
637 | ||
e5003249 VT |
638 | if (status & ATH9K_INT_TX) { |
639 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
640 | ath_tx_edma_tasklet(sc); | |
641 | else | |
642 | ath_tx_tasklet(sc); | |
643 | } | |
063d8be3 | 644 | |
96148326 | 645 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
646 | /* |
647 | * TSF sync does not look correct; remain awake to sync with | |
648 | * the next Beacon. | |
649 | */ | |
c46917bb LR |
650 | ath_print(common, ATH_DBG_PS, |
651 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 652 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
653 | } |
654 | ||
766ec4a9 | 655 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
656 | if (status & ATH9K_INT_GENTIMER) |
657 | ath_gen_timer_isr(sc->sc_ah); | |
658 | ||
ff37e337 | 659 | /* re-enable hardware interrupt */ |
3069168c | 660 | ath9k_hw_set_interrupts(ah, ah->imask); |
153e080d | 661 | ath9k_ps_restore(sc); |
ff37e337 S |
662 | } |
663 | ||
6baff7f9 | 664 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 665 | { |
063d8be3 S |
666 | #define SCHED_INTR ( \ |
667 | ATH9K_INT_FATAL | \ | |
668 | ATH9K_INT_RXORN | \ | |
669 | ATH9K_INT_RXEOL | \ | |
670 | ATH9K_INT_RX | \ | |
b5c80475 FF |
671 | ATH9K_INT_RXLP | \ |
672 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
673 | ATH9K_INT_TX | \ |
674 | ATH9K_INT_BMISS | \ | |
675 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
676 | ATH9K_INT_TSFOOR | \ |
677 | ATH9K_INT_GENTIMER) | |
063d8be3 | 678 | |
ff37e337 | 679 | struct ath_softc *sc = dev; |
cbe61d8a | 680 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 681 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
682 | enum ath9k_int status; |
683 | bool sched = false; | |
684 | ||
063d8be3 S |
685 | /* |
686 | * The hardware is not ready/present, don't | |
687 | * touch anything. Note this can happen early | |
688 | * on if the IRQ is shared. | |
689 | */ | |
690 | if (sc->sc_flags & SC_OP_INVALID) | |
691 | return IRQ_NONE; | |
ff37e337 | 692 | |
063d8be3 S |
693 | |
694 | /* shared irq, not for us */ | |
695 | ||
153e080d | 696 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 697 | return IRQ_NONE; |
063d8be3 S |
698 | |
699 | /* | |
700 | * Figure out the reason(s) for the interrupt. Note | |
701 | * that the hal returns a pseudo-ISR that may include | |
702 | * bits we haven't explicitly enabled so we mask the | |
703 | * value to insure we only process bits we requested. | |
704 | */ | |
705 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 706 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 707 | |
063d8be3 S |
708 | /* |
709 | * If there are no status bits set, then this interrupt was not | |
710 | * for me (should have been caught above). | |
711 | */ | |
153e080d | 712 | if (!status) |
063d8be3 | 713 | return IRQ_NONE; |
ff37e337 | 714 | |
063d8be3 S |
715 | /* Cache the status */ |
716 | sc->intrstatus = status; | |
717 | ||
718 | if (status & SCHED_INTR) | |
719 | sched = true; | |
720 | ||
721 | /* | |
722 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
723 | * chip immediately. | |
724 | */ | |
b5c80475 FF |
725 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
726 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
727 | goto chip_reset; |
728 | ||
08578b8f LR |
729 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
730 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
731 | |
732 | spin_lock(&common->cc_lock); | |
733 | ath_hw_cycle_counters_update(common); | |
08578b8f | 734 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
735 | spin_unlock(&common->cc_lock); |
736 | ||
08578b8f LR |
737 | goto chip_reset; |
738 | } | |
739 | ||
063d8be3 S |
740 | if (status & ATH9K_INT_SWBA) |
741 | tasklet_schedule(&sc->bcon_tasklet); | |
742 | ||
743 | if (status & ATH9K_INT_TXURN) | |
744 | ath9k_hw_updatetxtriglevel(ah, true); | |
745 | ||
b5c80475 FF |
746 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
747 | if (status & ATH9K_INT_RXEOL) { | |
748 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
749 | ath9k_hw_set_interrupts(ah, ah->imask); | |
750 | } | |
751 | } | |
752 | ||
063d8be3 | 753 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 754 | /* |
063d8be3 S |
755 | * Disable interrupts until we service the MIB |
756 | * interrupt; otherwise it will continue to | |
757 | * fire. | |
ff37e337 | 758 | */ |
063d8be3 S |
759 | ath9k_hw_set_interrupts(ah, 0); |
760 | /* | |
761 | * Let the hal handle the event. We assume | |
762 | * it will clear whatever condition caused | |
763 | * the interrupt. | |
764 | */ | |
88eac2da | 765 | spin_lock(&common->cc_lock); |
bfc472bb | 766 | ath9k_hw_proc_mib_event(ah); |
88eac2da | 767 | spin_unlock(&common->cc_lock); |
3069168c | 768 | ath9k_hw_set_interrupts(ah, ah->imask); |
063d8be3 | 769 | } |
ff37e337 | 770 | |
153e080d VT |
771 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
772 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
773 | /* Clear RxAbort bit so that we can |
774 | * receive frames */ | |
9ecdef4b | 775 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 776 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 777 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 778 | } |
063d8be3 S |
779 | |
780 | chip_reset: | |
ff37e337 | 781 | |
817e11de S |
782 | ath_debug_stat_interrupt(sc, status); |
783 | ||
ff37e337 S |
784 | if (sched) { |
785 | /* turn off every interrupt except SWBA */ | |
3069168c | 786 | ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
787 | tasklet_schedule(&sc->intr_tq); |
788 | } | |
789 | ||
790 | return IRQ_HANDLED; | |
063d8be3 S |
791 | |
792 | #undef SCHED_INTR | |
ff37e337 S |
793 | } |
794 | ||
f078f209 | 795 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 796 | struct ieee80211_channel *chan, |
094d05dc | 797 | enum nl80211_channel_type channel_type) |
f078f209 LR |
798 | { |
799 | u32 chanmode = 0; | |
f078f209 LR |
800 | |
801 | switch (chan->band) { | |
802 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
803 | switch(channel_type) { |
804 | case NL80211_CHAN_NO_HT: | |
805 | case NL80211_CHAN_HT20: | |
f078f209 | 806 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
807 | break; |
808 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 809 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
810 | break; |
811 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 812 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
813 | break; |
814 | } | |
f078f209 LR |
815 | break; |
816 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
817 | switch(channel_type) { |
818 | case NL80211_CHAN_NO_HT: | |
819 | case NL80211_CHAN_HT20: | |
f078f209 | 820 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
821 | break; |
822 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 823 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
824 | break; |
825 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 826 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
827 | break; |
828 | } | |
f078f209 LR |
829 | break; |
830 | default: | |
831 | break; | |
832 | } | |
833 | ||
834 | return chanmode; | |
835 | } | |
836 | ||
8feceb67 | 837 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 838 | struct ieee80211_vif *vif, |
8feceb67 | 839 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 840 | { |
f2b2143e | 841 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 842 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 843 | |
8feceb67 | 844 | if (bss_conf->assoc) { |
c46917bb LR |
845 | ath_print(common, ATH_DBG_CONFIG, |
846 | "Bss Info ASSOC %d, bssid: %pM\n", | |
847 | bss_conf->aid, common->curbssid); | |
f078f209 | 848 | |
8feceb67 | 849 | /* New association, store aid */ |
1510718d | 850 | common->curaid = bss_conf->aid; |
f2b2143e | 851 | ath9k_hw_write_associd(ah); |
2664f201 SB |
852 | |
853 | /* | |
854 | * Request a re-configuration of Beacon related timers | |
855 | * on the receipt of the first Beacon frame (i.e., | |
856 | * after time sync with the AP). | |
857 | */ | |
1b04b930 | 858 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 859 | |
8feceb67 | 860 | /* Configure the beacon */ |
2c3db3d5 | 861 | ath_beacon_config(sc, vif); |
f078f209 | 862 | |
8feceb67 | 863 | /* Reset rssi stats */ |
22e66a4c | 864 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 865 | |
6c3118e2 | 866 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 867 | ath_start_ani(common); |
8feceb67 | 868 | } else { |
c46917bb | 869 | ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 870 | common->curaid = 0; |
f38faa31 | 871 | /* Stop ANI */ |
6c3118e2 | 872 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 873 | del_timer_sync(&common->ani.timer); |
f078f209 | 874 | } |
8feceb67 | 875 | } |
f078f209 | 876 | |
68a89116 | 877 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 878 | { |
cbe61d8a | 879 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 880 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 881 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 882 | int r; |
500c064d | 883 | |
3cbb5dd7 | 884 | ath9k_ps_wakeup(sc); |
93b1b37f | 885 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 886 | |
159cd468 VT |
887 | if (!ah->curchan) |
888 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
889 | ||
5e848f78 | 890 | spin_lock_bh(&sc->rx.pcu_lock); |
d2f5b3a6 | 891 | spin_lock_bh(&sc->sc_resetlock); |
20bd2a09 | 892 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 893 | if (r) { |
c46917bb | 894 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 895 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
896 | "reset status %d\n", |
897 | channel->center_freq, r); | |
500c064d VT |
898 | } |
899 | spin_unlock_bh(&sc->sc_resetlock); | |
900 | ||
901 | ath_update_txpow(sc); | |
902 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
903 | ath_print(common, ATH_DBG_FATAL, |
904 | "Unable to restart recv logic\n"); | |
5e848f78 | 905 | spin_unlock_bh(&sc->rx.pcu_lock); |
500c064d VT |
906 | return; |
907 | } | |
5e848f78 | 908 | spin_unlock_bh(&sc->rx.pcu_lock); |
500c064d VT |
909 | |
910 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 911 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
912 | |
913 | /* Re-Enable interrupts */ | |
3069168c | 914 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
915 | |
916 | /* Enable LED */ | |
08fc5c1b | 917 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 918 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 919 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 920 | |
68a89116 | 921 | ieee80211_wake_queues(hw); |
3cbb5dd7 | 922 | ath9k_ps_restore(sc); |
500c064d VT |
923 | } |
924 | ||
68a89116 | 925 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 926 | { |
cbe61d8a | 927 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 928 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 929 | int r; |
500c064d | 930 | |
3cbb5dd7 | 931 | ath9k_ps_wakeup(sc); |
68a89116 | 932 | ieee80211_stop_queues(hw); |
500c064d | 933 | |
982723df VN |
934 | /* |
935 | * Keep the LED on when the radio is disabled | |
936 | * during idle unassociated state. | |
937 | */ | |
938 | if (!sc->ps_idle) { | |
939 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
940 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
941 | } | |
500c064d VT |
942 | |
943 | /* Disable interrupts */ | |
944 | ath9k_hw_set_interrupts(ah, 0); | |
945 | ||
043a0405 | 946 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
5e848f78 LR |
947 | |
948 | spin_lock_bh(&sc->rx.pcu_lock); | |
949 | ||
500c064d VT |
950 | ath_stoprecv(sc); /* turn off frame recv */ |
951 | ath_flushrecv(sc); /* flush recv queue */ | |
952 | ||
159cd468 | 953 | if (!ah->curchan) |
68a89116 | 954 | ah->curchan = ath_get_curchannel(sc, hw); |
159cd468 | 955 | |
500c064d | 956 | spin_lock_bh(&sc->sc_resetlock); |
20bd2a09 | 957 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 958 | if (r) { |
c46917bb | 959 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
f643e51d | 960 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
961 | "reset status %d\n", |
962 | channel->center_freq, r); | |
500c064d VT |
963 | } |
964 | spin_unlock_bh(&sc->sc_resetlock); | |
965 | ||
966 | ath9k_hw_phy_disable(ah); | |
5e848f78 LR |
967 | |
968 | spin_unlock_bh(&sc->rx.pcu_lock); | |
969 | ||
93b1b37f | 970 | ath9k_hw_configpcipowersave(ah, 1, 1); |
3cbb5dd7 | 971 | ath9k_ps_restore(sc); |
9ecdef4b | 972 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
973 | } |
974 | ||
ff37e337 S |
975 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
976 | { | |
cbe61d8a | 977 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 978 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 979 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 980 | int r; |
ff37e337 | 981 | |
2ab81d4a S |
982 | /* Stop ANI */ |
983 | del_timer_sync(&common->ani.timer); | |
984 | ||
cc9c378a S |
985 | ieee80211_stop_queues(hw); |
986 | ||
ff37e337 | 987 | ath9k_hw_set_interrupts(ah, 0); |
043a0405 | 988 | ath_drain_all_txq(sc, retry_tx); |
5e848f78 LR |
989 | |
990 | spin_lock_bh(&sc->rx.pcu_lock); | |
991 | ||
ff37e337 S |
992 | ath_stoprecv(sc); |
993 | ath_flushrecv(sc); | |
994 | ||
995 | spin_lock_bh(&sc->sc_resetlock); | |
20bd2a09 | 996 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false); |
ae8d2858 | 997 | if (r) |
c46917bb LR |
998 | ath_print(common, ATH_DBG_FATAL, |
999 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
1000 | spin_unlock_bh(&sc->sc_resetlock); |
1001 | ||
1002 | if (ath_startrecv(sc) != 0) | |
c46917bb LR |
1003 | ath_print(common, ATH_DBG_FATAL, |
1004 | "Unable to start recv logic\n"); | |
ff37e337 | 1005 | |
5e848f78 LR |
1006 | spin_unlock_bh(&sc->rx.pcu_lock); |
1007 | ||
ff37e337 S |
1008 | /* |
1009 | * We may be doing a reset in response to a request | |
1010 | * that changes the channel so update any state that | |
1011 | * might change as a result. | |
1012 | */ | |
ff37e337 S |
1013 | ath_update_txpow(sc); |
1014 | ||
52b8ac92 | 1015 | if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL))) |
2c3db3d5 | 1016 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 1017 | |
3069168c | 1018 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
1019 | |
1020 | if (retry_tx) { | |
1021 | int i; | |
1022 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1023 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
1024 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
1025 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
1026 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
1027 | } |
1028 | } | |
1029 | } | |
1030 | ||
cc9c378a S |
1031 | ieee80211_wake_queues(hw); |
1032 | ||
2ab81d4a S |
1033 | /* Start ANI */ |
1034 | ath_start_ani(common); | |
1035 | ||
ae8d2858 | 1036 | return r; |
ff37e337 S |
1037 | } |
1038 | ||
ebe297c3 | 1039 | static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) |
ff37e337 S |
1040 | { |
1041 | int qnum; | |
1042 | ||
1043 | switch (queue) { | |
1044 | case 0: | |
1d2231e2 | 1045 | qnum = sc->tx.hwq_map[WME_AC_VO]; |
ff37e337 S |
1046 | break; |
1047 | case 1: | |
1d2231e2 | 1048 | qnum = sc->tx.hwq_map[WME_AC_VI]; |
ff37e337 S |
1049 | break; |
1050 | case 2: | |
1d2231e2 | 1051 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
1052 | break; |
1053 | case 3: | |
1d2231e2 | 1054 | qnum = sc->tx.hwq_map[WME_AC_BK]; |
ff37e337 S |
1055 | break; |
1056 | default: | |
1d2231e2 | 1057 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
1058 | break; |
1059 | } | |
1060 | ||
1061 | return qnum; | |
1062 | } | |
1063 | ||
1064 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
1065 | { | |
1066 | int qnum; | |
1067 | ||
1068 | switch (queue) { | |
1d2231e2 | 1069 | case WME_AC_VO: |
ff37e337 S |
1070 | qnum = 0; |
1071 | break; | |
1d2231e2 | 1072 | case WME_AC_VI: |
ff37e337 S |
1073 | qnum = 1; |
1074 | break; | |
1d2231e2 | 1075 | case WME_AC_BE: |
ff37e337 S |
1076 | qnum = 2; |
1077 | break; | |
1d2231e2 | 1078 | case WME_AC_BK: |
ff37e337 S |
1079 | qnum = 3; |
1080 | break; | |
1081 | default: | |
1082 | qnum = -1; | |
1083 | break; | |
1084 | } | |
1085 | ||
1086 | return qnum; | |
1087 | } | |
1088 | ||
5f8e077c LR |
1089 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
1090 | * this redundant data */ | |
0e2dedf9 JM |
1091 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
1092 | struct ath9k_channel *ichan) | |
5f8e077c | 1093 | { |
5f8e077c LR |
1094 | struct ieee80211_channel *chan = hw->conf.channel; |
1095 | struct ieee80211_conf *conf = &hw->conf; | |
1096 | ||
1097 | ichan->channel = chan->center_freq; | |
1098 | ichan->chan = chan; | |
1099 | ||
1100 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
1101 | ichan->chanmode = CHANNEL_G; | |
8813262e | 1102 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; |
5f8e077c LR |
1103 | } else { |
1104 | ichan->chanmode = CHANNEL_A; | |
1105 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
1106 | } | |
1107 | ||
25c56eec | 1108 | if (conf_is_ht(conf)) |
5f8e077c LR |
1109 | ichan->chanmode = ath_get_extchanmode(sc, chan, |
1110 | conf->channel_type); | |
5f8e077c LR |
1111 | } |
1112 | ||
ff37e337 S |
1113 | /**********************/ |
1114 | /* mac80211 callbacks */ | |
1115 | /**********************/ | |
1116 | ||
8feceb67 | 1117 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1118 | { |
bce048d7 JM |
1119 | struct ath_wiphy *aphy = hw->priv; |
1120 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1121 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1122 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1123 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1124 | struct ath9k_channel *init_channel; |
82880a7c | 1125 | int r; |
f078f209 | 1126 | |
c46917bb LR |
1127 | ath_print(common, ATH_DBG_CONFIG, |
1128 | "Starting driver with initial channel: %d MHz\n", | |
1129 | curchan->center_freq); | |
f078f209 | 1130 | |
141b38b6 S |
1131 | mutex_lock(&sc->mutex); |
1132 | ||
9580a222 JM |
1133 | if (ath9k_wiphy_started(sc)) { |
1134 | if (sc->chan_idx == curchan->hw_value) { | |
1135 | /* | |
1136 | * Already on the operational channel, the new wiphy | |
1137 | * can be marked active. | |
1138 | */ | |
1139 | aphy->state = ATH_WIPHY_ACTIVE; | |
1140 | ieee80211_wake_queues(hw); | |
1141 | } else { | |
1142 | /* | |
1143 | * Another wiphy is on another channel, start the new | |
1144 | * wiphy in paused state. | |
1145 | */ | |
1146 | aphy->state = ATH_WIPHY_PAUSED; | |
1147 | ieee80211_stop_queues(hw); | |
1148 | } | |
1149 | mutex_unlock(&sc->mutex); | |
1150 | return 0; | |
1151 | } | |
1152 | aphy->state = ATH_WIPHY_ACTIVE; | |
1153 | ||
8feceb67 | 1154 | /* setup initial channel */ |
f078f209 | 1155 | |
82880a7c | 1156 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1157 | |
82880a7c | 1158 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
1159 | |
1160 | /* Reset SERDES registers */ | |
af03abec | 1161 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
1162 | |
1163 | /* | |
1164 | * The basic interface to setting the hardware in a good | |
1165 | * state is ``reset''. On return the hardware is known to | |
1166 | * be powered up and with interrupts disabled. This must | |
1167 | * be followed by initialization of the appropriate bits | |
1168 | * and then setup of the interrupt mask. | |
1169 | */ | |
5e848f78 | 1170 | spin_lock_bh(&sc->rx.pcu_lock); |
ff37e337 | 1171 | spin_lock_bh(&sc->sc_resetlock); |
20bd2a09 | 1172 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 1173 | if (r) { |
c46917bb LR |
1174 | ath_print(common, ATH_DBG_FATAL, |
1175 | "Unable to reset hardware; reset status %d " | |
1176 | "(freq %u MHz)\n", r, | |
1177 | curchan->center_freq); | |
ff37e337 | 1178 | spin_unlock_bh(&sc->sc_resetlock); |
5e848f78 | 1179 | spin_unlock_bh(&sc->rx.pcu_lock); |
141b38b6 | 1180 | goto mutex_unlock; |
ff37e337 S |
1181 | } |
1182 | spin_unlock_bh(&sc->sc_resetlock); | |
1183 | ||
1184 | /* | |
1185 | * This is needed only to setup initial state | |
1186 | * but it's best done after a reset. | |
1187 | */ | |
1188 | ath_update_txpow(sc); | |
8feceb67 | 1189 | |
ff37e337 S |
1190 | /* |
1191 | * Setup the hardware after reset: | |
1192 | * The receive engine is set going. | |
1193 | * Frame transmit is handled entirely | |
1194 | * in the frame output path; there's nothing to do | |
1195 | * here except setup the interrupt mask. | |
1196 | */ | |
1197 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
1198 | ath_print(common, ATH_DBG_FATAL, |
1199 | "Unable to start recv logic\n"); | |
141b38b6 | 1200 | r = -EIO; |
5e848f78 | 1201 | spin_unlock_bh(&sc->rx.pcu_lock); |
141b38b6 | 1202 | goto mutex_unlock; |
f078f209 | 1203 | } |
5e848f78 | 1204 | spin_unlock_bh(&sc->rx.pcu_lock); |
8feceb67 | 1205 | |
ff37e337 | 1206 | /* Setup our intr mask. */ |
b5c80475 FF |
1207 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1208 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1209 | ATH9K_INT_GLOBAL; | |
1210 | ||
1211 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1212 | ah->imask |= ATH9K_INT_RXHP | |
1213 | ATH9K_INT_RXLP | | |
1214 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1215 | else |
1216 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1217 | |
364734fa | 1218 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1219 | |
af03abec | 1220 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1221 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1222 | |
ff37e337 | 1223 | sc->sc_flags &= ~SC_OP_INVALID; |
5f841b41 | 1224 | sc->sc_ah->is_monitoring = false; |
ff37e337 S |
1225 | |
1226 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
1227 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1228 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 1229 | |
bce048d7 | 1230 | ieee80211_wake_queues(hw); |
ff37e337 | 1231 | |
42935eca | 1232 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1233 | |
766ec4a9 LR |
1234 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1235 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1236 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1237 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1238 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1239 | |
5bb12791 LR |
1240 | if (common->bus_ops->bt_coex_prep) |
1241 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1242 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1243 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1244 | } |
1245 | ||
98c316e3 | 1246 | pm_qos_update_request(&sc->pm_qos_req, 55); |
10598c12 | 1247 | |
141b38b6 S |
1248 | mutex_unlock: |
1249 | mutex_unlock(&sc->mutex); | |
1250 | ||
ae8d2858 | 1251 | return r; |
f078f209 LR |
1252 | } |
1253 | ||
8feceb67 VT |
1254 | static int ath9k_tx(struct ieee80211_hw *hw, |
1255 | struct sk_buff *skb) | |
f078f209 | 1256 | { |
528f0c6b | 1257 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
1258 | struct ath_wiphy *aphy = hw->priv; |
1259 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1260 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1261 | struct ath_tx_control txctl; |
1bc14880 BP |
1262 | int padpos, padsize; |
1263 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
84642d6b | 1264 | int qnum; |
528f0c6b | 1265 | |
8089cc47 | 1266 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
c46917bb LR |
1267 | ath_print(common, ATH_DBG_XMIT, |
1268 | "ath9k: %s: TX in unexpected wiphy state " | |
1269 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
ee166a0e JM |
1270 | goto exit; |
1271 | } | |
1272 | ||
96148326 | 1273 | if (sc->ps_enabled) { |
dc8c4585 JM |
1274 | /* |
1275 | * mac80211 does not set PM field for normal data frames, so we | |
1276 | * need to update that based on the current PS mode. | |
1277 | */ | |
1278 | if (ieee80211_is_data(hdr->frame_control) && | |
1279 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1280 | !ieee80211_has_pm(hdr->frame_control)) { | |
c46917bb LR |
1281 | ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " |
1282 | "while in PS mode\n"); | |
dc8c4585 JM |
1283 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1284 | } | |
1285 | } | |
1286 | ||
9a23f9ca JM |
1287 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1288 | /* | |
1289 | * We are using PS-Poll and mac80211 can request TX while in | |
1290 | * power save mode. Need to wake up hardware for the TX to be | |
1291 | * completed and if needed, also for RX of buffered frames. | |
1292 | */ | |
9a23f9ca | 1293 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1294 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1295 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1296 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
c46917bb LR |
1297 | ath_print(common, ATH_DBG_PS, |
1298 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1299 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1300 | } else { |
c46917bb LR |
1301 | ath_print(common, ATH_DBG_PS, |
1302 | "Wake up to complete TX\n"); | |
1b04b930 | 1303 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1304 | } |
1305 | /* | |
1306 | * The actual restore operation will happen only after | |
1307 | * the sc_flags bit is cleared. We are just dropping | |
1308 | * the ps_usecount here. | |
1309 | */ | |
1310 | ath9k_ps_restore(sc); | |
1311 | } | |
1312 | ||
528f0c6b | 1313 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 1314 | |
8feceb67 VT |
1315 | /* |
1316 | * As a temporary workaround, assign seq# here; this will likely need | |
1317 | * to be cleaned up to work better with Beacon transmission and virtual | |
1318 | * BSSes. | |
1319 | */ | |
1320 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
8feceb67 | 1321 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
b77f483f | 1322 | sc->tx.seq_no += 0x10; |
8feceb67 | 1323 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 1324 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 1325 | } |
f078f209 | 1326 | |
8feceb67 | 1327 | /* Add the padding after the header if this is not already done */ |
1bc14880 BP |
1328 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1329 | padsize = padpos & 3; | |
1330 | if (padsize && skb->len>padpos) { | |
8feceb67 VT |
1331 | if (skb_headroom(skb) < padsize) |
1332 | return -1; | |
1333 | skb_push(skb, padsize); | |
1bc14880 | 1334 | memmove(skb->data, skb->data + padsize, padpos); |
8feceb67 VT |
1335 | } |
1336 | ||
84642d6b FF |
1337 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
1338 | txctl.txq = &sc->tx.txq[qnum]; | |
528f0c6b | 1339 | |
c46917bb | 1340 | ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1341 | |
c52f33d0 | 1342 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1343 | ath_print(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1344 | goto exit; |
8feceb67 VT |
1345 | } |
1346 | ||
528f0c6b S |
1347 | return 0; |
1348 | exit: | |
1349 | dev_kfree_skb_any(skb); | |
8feceb67 | 1350 | return 0; |
f078f209 LR |
1351 | } |
1352 | ||
8feceb67 | 1353 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1354 | { |
bce048d7 JM |
1355 | struct ath_wiphy *aphy = hw->priv; |
1356 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1357 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1358 | struct ath_common *common = ath9k_hw_common(ah); |
447a42c2 | 1359 | int i; |
f078f209 | 1360 | |
4c483817 S |
1361 | mutex_lock(&sc->mutex); |
1362 | ||
9580a222 JM |
1363 | aphy->state = ATH_WIPHY_INACTIVE; |
1364 | ||
9a75c2ff VN |
1365 | if (led_blink) |
1366 | cancel_delayed_work_sync(&sc->ath_led_blink_work); | |
1367 | ||
c94dbff7 | 1368 | cancel_delayed_work_sync(&sc->tx_complete_work); |
9f42c2b6 | 1369 | cancel_work_sync(&sc->paprd_work); |
347809fc | 1370 | cancel_work_sync(&sc->hw_check_work); |
c94dbff7 | 1371 | |
447a42c2 RM |
1372 | for (i = 0; i < sc->num_sec_wiphy; i++) { |
1373 | if (sc->sec_wiphy[i]) | |
1374 | break; | |
1375 | } | |
1376 | ||
1377 | if (i == sc->num_sec_wiphy) { | |
c94dbff7 LR |
1378 | cancel_delayed_work_sync(&sc->wiphy_work); |
1379 | cancel_work_sync(&sc->chan_work); | |
1380 | } | |
1381 | ||
9c84b797 | 1382 | if (sc->sc_flags & SC_OP_INVALID) { |
c46917bb | 1383 | ath_print(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1384 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1385 | return; |
1386 | } | |
8feceb67 | 1387 | |
9580a222 JM |
1388 | if (ath9k_wiphy_started(sc)) { |
1389 | mutex_unlock(&sc->mutex); | |
1390 | return; /* another wiphy still in use */ | |
1391 | } | |
1392 | ||
3867cf6a S |
1393 | /* Ensure HW is awake when we try to shut it down. */ |
1394 | ath9k_ps_wakeup(sc); | |
1395 | ||
766ec4a9 | 1396 | if (ah->btcoex_hw.enabled) { |
af03abec | 1397 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1398 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1399 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1400 | } |
1401 | ||
ff37e337 S |
1402 | /* make sure h/w will not generate any interrupt |
1403 | * before setting the invalid flag. */ | |
af03abec | 1404 | ath9k_hw_set_interrupts(ah, 0); |
ff37e337 | 1405 | |
5e848f78 | 1406 | spin_lock_bh(&sc->rx.pcu_lock); |
ff37e337 | 1407 | if (!(sc->sc_flags & SC_OP_INVALID)) { |
043a0405 | 1408 | ath_drain_all_txq(sc, false); |
ff37e337 | 1409 | ath_stoprecv(sc); |
af03abec | 1410 | ath9k_hw_phy_disable(ah); |
ff37e337 | 1411 | } else |
b77f483f | 1412 | sc->rx.rxlink = NULL; |
5e848f78 | 1413 | spin_unlock_bh(&sc->rx.pcu_lock); |
ff37e337 | 1414 | |
ff37e337 | 1415 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1416 | ath9k_hw_disable(ah); |
1417 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
3867cf6a S |
1418 | ath9k_ps_restore(sc); |
1419 | ||
1420 | /* Finally, put the chip in FULL SLEEP mode */ | |
9ecdef4b | 1421 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
ff37e337 S |
1422 | |
1423 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1424 | |
98c316e3 | 1425 | pm_qos_update_request(&sc->pm_qos_req, PM_QOS_DEFAULT_VALUE); |
10598c12 | 1426 | |
141b38b6 S |
1427 | mutex_unlock(&sc->mutex); |
1428 | ||
c46917bb | 1429 | ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1430 | } |
1431 | ||
8feceb67 | 1432 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1433 | struct ieee80211_vif *vif) |
f078f209 | 1434 | { |
bce048d7 JM |
1435 | struct ath_wiphy *aphy = hw->priv; |
1436 | struct ath_softc *sc = aphy->sc; | |
3069168c PR |
1437 | struct ath_hw *ah = sc->sc_ah; |
1438 | struct ath_common *common = ath9k_hw_common(ah); | |
1ed32e4f | 1439 | struct ath_vif *avp = (void *)vif->drv_priv; |
d97809db | 1440 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 1441 | int ret = 0; |
8feceb67 | 1442 | |
141b38b6 S |
1443 | mutex_lock(&sc->mutex); |
1444 | ||
1ed32e4f | 1445 | switch (vif->type) { |
05c914fe | 1446 | case NL80211_IFTYPE_STATION: |
d97809db | 1447 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 1448 | break; |
e51f3eff BJ |
1449 | case NL80211_IFTYPE_WDS: |
1450 | ic_opmode = NL80211_IFTYPE_WDS; | |
1451 | break; | |
05c914fe | 1452 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 1453 | case NL80211_IFTYPE_AP: |
9cb5412b | 1454 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
1455 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1456 | ret = -ENOBUFS; | |
1457 | goto out; | |
1458 | } | |
1ed32e4f | 1459 | ic_opmode = vif->type; |
f078f209 LR |
1460 | break; |
1461 | default: | |
c46917bb | 1462 | ath_print(common, ATH_DBG_FATAL, |
1ed32e4f | 1463 | "Interface type %d not yet supported\n", vif->type); |
2c3db3d5 JM |
1464 | ret = -EOPNOTSUPP; |
1465 | goto out; | |
f078f209 LR |
1466 | } |
1467 | ||
c46917bb LR |
1468 | ath_print(common, ATH_DBG_CONFIG, |
1469 | "Attach a VIF of type: %d\n", ic_opmode); | |
8feceb67 | 1470 | |
17d7904d | 1471 | /* Set the VIF opmode */ |
5640b08e S |
1472 | avp->av_opmode = ic_opmode; |
1473 | avp->av_bslot = -1; | |
1474 | ||
2c3db3d5 | 1475 | sc->nvifs++; |
8ca21f01 | 1476 | |
364734fa | 1477 | ath9k_set_bssid_mask(hw, vif); |
8ca21f01 | 1478 | |
2c3db3d5 JM |
1479 | if (sc->nvifs > 1) |
1480 | goto out; /* skip global settings for secondary vif */ | |
1481 | ||
b238e90e | 1482 | if (ic_opmode == NL80211_IFTYPE_AP) { |
3069168c | 1483 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e S |
1484 | sc->sc_flags |= SC_OP_TSF_RESET; |
1485 | } | |
5640b08e | 1486 | |
5640b08e | 1487 | /* Set the device opmode */ |
3069168c | 1488 | ah->opmode = ic_opmode; |
5640b08e | 1489 | |
4e30ffa2 VN |
1490 | /* |
1491 | * Enable MIB interrupts when there are hardware phy counters. | |
1492 | * Note we only do this (at the moment) for station mode. | |
1493 | */ | |
1ed32e4f JB |
1494 | if ((vif->type == NL80211_IFTYPE_STATION) || |
1495 | (vif->type == NL80211_IFTYPE_ADHOC) || | |
1496 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
3448f912 LR |
1497 | if (ah->config.enable_ani) |
1498 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1499 | ah->imask |= ATH9K_INT_TSFOOR; |
4af9cf4f S |
1500 | } |
1501 | ||
3069168c | 1502 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1503 | |
1ed32e4f | 1504 | if (vif->type == NL80211_IFTYPE_AP || |
5f841b41 | 1505 | vif->type == NL80211_IFTYPE_ADHOC) { |
6c3118e2 | 1506 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 1507 | ath_start_ani(common); |
6c3118e2 | 1508 | } |
6f255425 | 1509 | |
2c3db3d5 | 1510 | out: |
141b38b6 | 1511 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 1512 | return ret; |
f078f209 LR |
1513 | } |
1514 | ||
8feceb67 | 1515 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1516 | struct ieee80211_vif *vif) |
f078f209 | 1517 | { |
bce048d7 JM |
1518 | struct ath_wiphy *aphy = hw->priv; |
1519 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1520 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1ed32e4f | 1521 | struct ath_vif *avp = (void *)vif->drv_priv; |
2c3db3d5 | 1522 | int i; |
f078f209 | 1523 | |
c46917bb | 1524 | ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1525 | |
141b38b6 S |
1526 | mutex_lock(&sc->mutex); |
1527 | ||
6f255425 | 1528 | /* Stop ANI */ |
6c3118e2 | 1529 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 1530 | del_timer_sync(&common->ani.timer); |
580f0b8a | 1531 | |
8feceb67 | 1532 | /* Reclaim beacon resources */ |
9cb5412b PE |
1533 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
1534 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
1535 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
5f70a88f | 1536 | ath9k_ps_wakeup(sc); |
b77f483f | 1537 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
5f70a88f | 1538 | ath9k_ps_restore(sc); |
580f0b8a | 1539 | } |
f078f209 | 1540 | |
74401773 | 1541 | ath_beacon_return(sc, avp); |
8feceb67 | 1542 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 1543 | |
2c3db3d5 | 1544 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
1ed32e4f | 1545 | if (sc->beacon.bslot[i] == vif) { |
2c3db3d5 JM |
1546 | printk(KERN_DEBUG "%s: vif had allocated beacon " |
1547 | "slot\n", __func__); | |
1548 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 1549 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
1550 | } |
1551 | } | |
1552 | ||
17d7904d | 1553 | sc->nvifs--; |
141b38b6 S |
1554 | |
1555 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1556 | } |
1557 | ||
fbab7390 | 1558 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1559 | { |
3069168c PR |
1560 | struct ath_hw *ah = sc->sc_ah; |
1561 | ||
3f7c5c10 | 1562 | sc->ps_enabled = true; |
3069168c PR |
1563 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1564 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1565 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1566 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1567 | } |
fdf76622 | 1568 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1569 | } |
3f7c5c10 SB |
1570 | } |
1571 | ||
845d708e SB |
1572 | static void ath9k_disable_ps(struct ath_softc *sc) |
1573 | { | |
1574 | struct ath_hw *ah = sc->sc_ah; | |
1575 | ||
1576 | sc->ps_enabled = false; | |
1577 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1578 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1579 | ath9k_hw_setrxabort(ah, 0); | |
1580 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1581 | PS_WAIT_FOR_CAB | | |
1582 | PS_WAIT_FOR_PSPOLL_DATA | | |
1583 | PS_WAIT_FOR_TX_ACK); | |
1584 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1585 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
1586 | ath9k_hw_set_interrupts(ah, ah->imask); | |
1587 | } | |
1588 | } | |
1589 | ||
1590 | } | |
1591 | ||
e8975581 | 1592 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1593 | { |
bce048d7 JM |
1594 | struct ath_wiphy *aphy = hw->priv; |
1595 | struct ath_softc *sc = aphy->sc; | |
3430098a FF |
1596 | struct ath_hw *ah = sc->sc_ah; |
1597 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1598 | struct ieee80211_conf *conf = &hw->conf; |
194b7c13 | 1599 | bool disable_radio; |
f078f209 | 1600 | |
aa33de09 | 1601 | mutex_lock(&sc->mutex); |
141b38b6 | 1602 | |
194b7c13 LR |
1603 | /* |
1604 | * Leave this as the first check because we need to turn on the | |
1605 | * radio if it was disabled before prior to processing the rest | |
1606 | * of the changes. Likewise we must only disable the radio towards | |
1607 | * the end. | |
1608 | */ | |
64839170 | 1609 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
194b7c13 LR |
1610 | bool enable_radio; |
1611 | bool all_wiphys_idle; | |
1612 | bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); | |
64839170 LR |
1613 | |
1614 | spin_lock_bh(&sc->wiphy_lock); | |
1615 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
194b7c13 LR |
1616 | ath9k_set_wiphy_idle(aphy, idle); |
1617 | ||
11446011 | 1618 | enable_radio = (!idle && all_wiphys_idle); |
194b7c13 LR |
1619 | |
1620 | /* | |
1621 | * After we unlock here its possible another wiphy | |
1622 | * can be re-renabled so to account for that we will | |
1623 | * only disable the radio toward the end of this routine | |
1624 | * if by then all wiphys are still idle. | |
1625 | */ | |
64839170 LR |
1626 | spin_unlock_bh(&sc->wiphy_lock); |
1627 | ||
194b7c13 | 1628 | if (enable_radio) { |
1dbfd9d4 | 1629 | sc->ps_idle = false; |
68a89116 | 1630 | ath_radio_enable(sc, hw); |
c46917bb LR |
1631 | ath_print(common, ATH_DBG_CONFIG, |
1632 | "not-idle: enabling radio\n"); | |
64839170 LR |
1633 | } |
1634 | } | |
1635 | ||
e7824a50 LR |
1636 | /* |
1637 | * We just prepare to enable PS. We have to wait until our AP has | |
1638 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1639 | * those ACKs and end up retransmitting the same null data frames. | |
1640 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1641 | */ | |
3cbb5dd7 | 1642 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1643 | unsigned long flags; |
1644 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1645 | if (conf->flags & IEEE80211_CONF_PS) |
1646 | ath9k_enable_ps(sc); | |
845d708e SB |
1647 | else |
1648 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1649 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1650 | } |
1651 | ||
199afd9d S |
1652 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1653 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
1654 | ath_print(common, ATH_DBG_CONFIG, | |
5f841b41 RM |
1655 | "Monitor mode is enabled\n"); |
1656 | sc->sc_ah->is_monitoring = true; | |
1657 | } else { | |
1658 | ath_print(common, ATH_DBG_CONFIG, | |
1659 | "Monitor mode is disabled\n"); | |
1660 | sc->sc_ah->is_monitoring = false; | |
199afd9d S |
1661 | } |
1662 | } | |
1663 | ||
4797938c | 1664 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1665 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1666 | int pos = curchan->hw_value; |
3430098a FF |
1667 | int old_pos = -1; |
1668 | unsigned long flags; | |
1669 | ||
1670 | if (ah->curchan) | |
1671 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1672 | |
0e2dedf9 JM |
1673 | aphy->chan_idx = pos; |
1674 | aphy->chan_is_ht = conf_is_ht(conf); | |
5ee08656 FF |
1675 | if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
1676 | sc->sc_flags |= SC_OP_OFFCHANNEL; | |
1677 | else | |
1678 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | |
0e2dedf9 | 1679 | |
8089cc47 JM |
1680 | if (aphy->state == ATH_WIPHY_SCAN || |
1681 | aphy->state == ATH_WIPHY_ACTIVE) | |
1682 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
1683 | else { | |
1684 | /* | |
1685 | * Do not change operational channel based on a paused | |
1686 | * wiphy changes. | |
1687 | */ | |
1688 | goto skip_chan_change; | |
1689 | } | |
0e2dedf9 | 1690 | |
c46917bb LR |
1691 | ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1692 | curchan->center_freq); | |
f078f209 | 1693 | |
5f8e077c | 1694 | /* XXX: remove me eventualy */ |
0e2dedf9 | 1695 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 1696 | |
ecf70441 | 1697 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 1698 | |
3430098a FF |
1699 | /* update survey stats for the old channel before switching */ |
1700 | spin_lock_irqsave(&common->cc_lock, flags); | |
1701 | ath_update_survey_stats(sc); | |
1702 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1703 | ||
1704 | /* | |
1705 | * If the operating channel changes, change the survey in-use flags | |
1706 | * along with it. | |
1707 | * Reset the survey data for the new channel, unless we're switching | |
1708 | * back to the operating channel from an off-channel operation. | |
1709 | */ | |
1710 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1711 | sc->cur_survey != &sc->survey[pos]) { | |
1712 | ||
1713 | if (sc->cur_survey) | |
1714 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1715 | ||
1716 | sc->cur_survey = &sc->survey[pos]; | |
1717 | ||
1718 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1719 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1720 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1721 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1722 | } | |
1723 | ||
0e2dedf9 | 1724 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
c46917bb LR |
1725 | ath_print(common, ATH_DBG_FATAL, |
1726 | "Unable to set channel\n"); | |
aa33de09 | 1727 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1728 | return -EINVAL; |
1729 | } | |
3430098a FF |
1730 | |
1731 | /* | |
1732 | * The most recent snapshot of channel->noisefloor for the old | |
1733 | * channel is only available after the hardware reset. Copy it to | |
1734 | * the survey stats now. | |
1735 | */ | |
1736 | if (old_pos >= 0) | |
1737 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1738 | } |
f078f209 | 1739 | |
8089cc47 | 1740 | skip_chan_change: |
c9f6a656 | 1741 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
17d7904d | 1742 | sc->config.txpowlimit = 2 * conf->power_level; |
c9f6a656 LR |
1743 | ath_update_txpow(sc); |
1744 | } | |
f078f209 | 1745 | |
194b7c13 LR |
1746 | spin_lock_bh(&sc->wiphy_lock); |
1747 | disable_radio = ath9k_all_wiphys_idle(sc); | |
1748 | spin_unlock_bh(&sc->wiphy_lock); | |
1749 | ||
64839170 | 1750 | if (disable_radio) { |
c46917bb | 1751 | ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
1dbfd9d4 | 1752 | sc->ps_idle = true; |
68a89116 | 1753 | ath_radio_disable(sc, hw); |
64839170 LR |
1754 | } |
1755 | ||
aa33de09 | 1756 | mutex_unlock(&sc->mutex); |
141b38b6 | 1757 | |
f078f209 LR |
1758 | return 0; |
1759 | } | |
1760 | ||
8feceb67 VT |
1761 | #define SUPPORTED_FILTERS \ |
1762 | (FIF_PROMISC_IN_BSS | \ | |
1763 | FIF_ALLMULTI | \ | |
1764 | FIF_CONTROL | \ | |
af6a3fc7 | 1765 | FIF_PSPOLL | \ |
8feceb67 VT |
1766 | FIF_OTHER_BSS | \ |
1767 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1768 | FIF_PROBE_REQ | \ |
8feceb67 | 1769 | FIF_FCSFAIL) |
c83be688 | 1770 | |
8feceb67 VT |
1771 | /* FIXME: sc->sc_full_reset ? */ |
1772 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1773 | unsigned int changed_flags, | |
1774 | unsigned int *total_flags, | |
3ac64bee | 1775 | u64 multicast) |
8feceb67 | 1776 | { |
bce048d7 JM |
1777 | struct ath_wiphy *aphy = hw->priv; |
1778 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1779 | u32 rfilt; |
f078f209 | 1780 | |
8feceb67 VT |
1781 | changed_flags &= SUPPORTED_FILTERS; |
1782 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1783 | |
b77f483f | 1784 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1785 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1786 | rfilt = ath_calcrxfilter(sc); |
1787 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1788 | ath9k_ps_restore(sc); |
f078f209 | 1789 | |
c46917bb LR |
1790 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1791 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1792 | } |
f078f209 | 1793 | |
4ca77860 JB |
1794 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1795 | struct ieee80211_vif *vif, | |
1796 | struct ieee80211_sta *sta) | |
8feceb67 | 1797 | { |
bce048d7 JM |
1798 | struct ath_wiphy *aphy = hw->priv; |
1799 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1800 | |
4ca77860 JB |
1801 | ath_node_attach(sc, sta); |
1802 | ||
1803 | return 0; | |
1804 | } | |
1805 | ||
1806 | static int ath9k_sta_remove(struct ieee80211_hw *hw, | |
1807 | struct ieee80211_vif *vif, | |
1808 | struct ieee80211_sta *sta) | |
1809 | { | |
1810 | struct ath_wiphy *aphy = hw->priv; | |
1811 | struct ath_softc *sc = aphy->sc; | |
1812 | ||
1813 | ath_node_detach(sc, sta); | |
1814 | ||
1815 | return 0; | |
f078f209 LR |
1816 | } |
1817 | ||
141b38b6 | 1818 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1819 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1820 | { |
bce048d7 JM |
1821 | struct ath_wiphy *aphy = hw->priv; |
1822 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1823 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 VT |
1824 | struct ath9k_tx_queue_info qi; |
1825 | int ret = 0, qnum; | |
f078f209 | 1826 | |
8feceb67 VT |
1827 | if (queue >= WME_NUM_AC) |
1828 | return 0; | |
f078f209 | 1829 | |
141b38b6 S |
1830 | mutex_lock(&sc->mutex); |
1831 | ||
1ffb0610 S |
1832 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1833 | ||
8feceb67 VT |
1834 | qi.tqi_aifs = params->aifs; |
1835 | qi.tqi_cwmin = params->cw_min; | |
1836 | qi.tqi_cwmax = params->cw_max; | |
1837 | qi.tqi_burstTime = params->txop; | |
1838 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 1839 | |
c46917bb LR |
1840 | ath_print(common, ATH_DBG_CONFIG, |
1841 | "Configure tx [queue/halq] [%d/%d], " | |
1842 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1843 | queue, qnum, params->aifs, params->cw_min, | |
1844 | params->cw_max, params->txop); | |
f078f209 | 1845 | |
8feceb67 VT |
1846 | ret = ath_txq_update(sc, qnum, &qi); |
1847 | if (ret) | |
c46917bb | 1848 | ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 1849 | |
94db2936 | 1850 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
1d2231e2 | 1851 | if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret) |
94db2936 VN |
1852 | ath_beaconq_config(sc); |
1853 | ||
141b38b6 S |
1854 | mutex_unlock(&sc->mutex); |
1855 | ||
8feceb67 VT |
1856 | return ret; |
1857 | } | |
f078f209 | 1858 | |
8feceb67 VT |
1859 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1860 | enum set_key_cmd cmd, | |
dc822b5d JB |
1861 | struct ieee80211_vif *vif, |
1862 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1863 | struct ieee80211_key_conf *key) |
1864 | { | |
bce048d7 JM |
1865 | struct ath_wiphy *aphy = hw->priv; |
1866 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1867 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1868 | int ret = 0; |
f078f209 | 1869 | |
b3bd89ce JM |
1870 | if (modparam_nohwcrypt) |
1871 | return -ENOSPC; | |
1872 | ||
141b38b6 | 1873 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1874 | ath9k_ps_wakeup(sc); |
c46917bb | 1875 | ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1876 | |
8feceb67 VT |
1877 | switch (cmd) { |
1878 | case SET_KEY: | |
040e539e | 1879 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1880 | if (ret >= 0) { |
1881 | key->hw_key_idx = ret; | |
8feceb67 VT |
1882 | /* push IV and Michael MIC generation to stack */ |
1883 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1884 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1885 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1886 | if (sc->sc_ah->sw_mgmt_crypto && |
1887 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1888 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1889 | ret = 0; |
8feceb67 VT |
1890 | } |
1891 | break; | |
1892 | case DISABLE_KEY: | |
040e539e | 1893 | ath_key_delete(common, key); |
8feceb67 VT |
1894 | break; |
1895 | default: | |
1896 | ret = -EINVAL; | |
1897 | } | |
f078f209 | 1898 | |
3cbb5dd7 | 1899 | ath9k_ps_restore(sc); |
141b38b6 S |
1900 | mutex_unlock(&sc->mutex); |
1901 | ||
8feceb67 VT |
1902 | return ret; |
1903 | } | |
f078f209 | 1904 | |
8feceb67 VT |
1905 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1906 | struct ieee80211_vif *vif, | |
1907 | struct ieee80211_bss_conf *bss_conf, | |
1908 | u32 changed) | |
1909 | { | |
bce048d7 JM |
1910 | struct ath_wiphy *aphy = hw->priv; |
1911 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 | 1912 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1913 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1914 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1915 | int slottime; |
c6089ccc | 1916 | int error; |
f078f209 | 1917 | |
141b38b6 S |
1918 | mutex_lock(&sc->mutex); |
1919 | ||
c6089ccc S |
1920 | if (changed & BSS_CHANGED_BSSID) { |
1921 | /* Set BSSID */ | |
1922 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1923 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1924 | common->curaid = 0; |
f2b2143e | 1925 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1926 | |
c6089ccc S |
1927 | /* Set aggregation protection mode parameters */ |
1928 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1929 | |
c6089ccc S |
1930 | /* Only legacy IBSS for now */ |
1931 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
1932 | ath_update_chainmask(sc, 0); | |
2d0ddec5 | 1933 | |
c6089ccc S |
1934 | ath_print(common, ATH_DBG_CONFIG, |
1935 | "BSSID: %pM aid: 0x%x\n", | |
1936 | common->curbssid, common->curaid); | |
2d0ddec5 | 1937 | |
c6089ccc S |
1938 | /* need to reconfigure the beacon */ |
1939 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1940 | } | |
2d0ddec5 | 1941 | |
c6089ccc S |
1942 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1943 | if ((changed & BSS_CHANGED_BEACON) || | |
1944 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
1945 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1946 | error = ath_beacon_alloc(aphy, vif); | |
1947 | if (!error) | |
1948 | ath_beacon_config(sc, vif); | |
0005baf4 FF |
1949 | } |
1950 | ||
1951 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1952 | if (bss_conf->use_short_slot) | |
1953 | slottime = 9; | |
1954 | else | |
1955 | slottime = 20; | |
1956 | if (vif->type == NL80211_IFTYPE_AP) { | |
1957 | /* | |
1958 | * Defer update, so that connected stations can adjust | |
1959 | * their settings at the same time. | |
1960 | * See beacon.c for more details | |
1961 | */ | |
1962 | sc->beacon.slottime = slottime; | |
1963 | sc->beacon.updateslot = UPDATE; | |
1964 | } else { | |
1965 | ah->slottime = slottime; | |
1966 | ath9k_hw_init_global_settings(ah); | |
1967 | } | |
2d0ddec5 JB |
1968 | } |
1969 | ||
c6089ccc S |
1970 | /* Disable transmission of beacons */ |
1971 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) | |
1972 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 | 1973 | |
c6089ccc S |
1974 | if (changed & BSS_CHANGED_BEACON_INT) { |
1975 | sc->beacon_interval = bss_conf->beacon_int; | |
1976 | /* | |
1977 | * In case of AP mode, the HW TSF has to be reset | |
1978 | * when the beacon interval changes. | |
1979 | */ | |
1980 | if (vif->type == NL80211_IFTYPE_AP) { | |
1981 | sc->sc_flags |= SC_OP_TSF_RESET; | |
1982 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 JB |
1983 | error = ath_beacon_alloc(aphy, vif); |
1984 | if (!error) | |
1985 | ath_beacon_config(sc, vif); | |
c6089ccc S |
1986 | } else { |
1987 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1988 | } |
1989 | } | |
1990 | ||
8feceb67 | 1991 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
c46917bb LR |
1992 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1993 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1994 | if (bss_conf->use_short_preamble) |
1995 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1996 | else | |
1997 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1998 | } | |
f078f209 | 1999 | |
8feceb67 | 2000 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
c46917bb LR |
2001 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
2002 | bss_conf->use_cts_prot); | |
8feceb67 VT |
2003 | if (bss_conf->use_cts_prot && |
2004 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
2005 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
2006 | else | |
2007 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
2008 | } | |
f078f209 | 2009 | |
8feceb67 | 2010 | if (changed & BSS_CHANGED_ASSOC) { |
c46917bb | 2011 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 2012 | bss_conf->assoc); |
5640b08e | 2013 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 2014 | } |
141b38b6 S |
2015 | |
2016 | mutex_unlock(&sc->mutex); | |
8feceb67 | 2017 | } |
f078f209 | 2018 | |
8feceb67 VT |
2019 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
2020 | { | |
2021 | u64 tsf; | |
bce048d7 JM |
2022 | struct ath_wiphy *aphy = hw->priv; |
2023 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 2024 | |
141b38b6 S |
2025 | mutex_lock(&sc->mutex); |
2026 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
2027 | mutex_unlock(&sc->mutex); | |
f078f209 | 2028 | |
8feceb67 VT |
2029 | return tsf; |
2030 | } | |
f078f209 | 2031 | |
3b5d665b AF |
2032 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
2033 | { | |
bce048d7 JM |
2034 | struct ath_wiphy *aphy = hw->priv; |
2035 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 2036 | |
141b38b6 S |
2037 | mutex_lock(&sc->mutex); |
2038 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
2039 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
2040 | } |
2041 | ||
8feceb67 VT |
2042 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
2043 | { | |
bce048d7 JM |
2044 | struct ath_wiphy *aphy = hw->priv; |
2045 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 2046 | |
141b38b6 | 2047 | mutex_lock(&sc->mutex); |
21526d57 LR |
2048 | |
2049 | ath9k_ps_wakeup(sc); | |
141b38b6 | 2050 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
2051 | ath9k_ps_restore(sc); |
2052 | ||
141b38b6 | 2053 | mutex_unlock(&sc->mutex); |
8feceb67 | 2054 | } |
f078f209 | 2055 | |
8feceb67 | 2056 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 2057 | struct ieee80211_vif *vif, |
141b38b6 S |
2058 | enum ieee80211_ampdu_mlme_action action, |
2059 | struct ieee80211_sta *sta, | |
2060 | u16 tid, u16 *ssn) | |
8feceb67 | 2061 | { |
bce048d7 JM |
2062 | struct ath_wiphy *aphy = hw->priv; |
2063 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2064 | int ret = 0; |
f078f209 | 2065 | |
85ad181e JB |
2066 | local_bh_disable(); |
2067 | ||
8feceb67 VT |
2068 | switch (action) { |
2069 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2070 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2071 | ret = -ENOTSUPP; | |
8feceb67 VT |
2072 | break; |
2073 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2074 | break; |
2075 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 2076 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
2077 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
2078 | if (!ret) | |
2079 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 2080 | ath9k_ps_restore(sc); |
8feceb67 VT |
2081 | break; |
2082 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 2083 | ath9k_ps_wakeup(sc); |
f83da965 | 2084 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 2085 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 2086 | ath9k_ps_restore(sc); |
8feceb67 | 2087 | break; |
b1720231 | 2088 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 2089 | ath9k_ps_wakeup(sc); |
8469cdef | 2090 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 2091 | ath9k_ps_restore(sc); |
8469cdef | 2092 | break; |
8feceb67 | 2093 | default: |
c46917bb LR |
2094 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
2095 | "Unknown AMPDU action\n"); | |
8feceb67 VT |
2096 | } |
2097 | ||
85ad181e JB |
2098 | local_bh_enable(); |
2099 | ||
8feceb67 | 2100 | return ret; |
f078f209 LR |
2101 | } |
2102 | ||
62dad5b0 BP |
2103 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
2104 | struct survey_info *survey) | |
2105 | { | |
2106 | struct ath_wiphy *aphy = hw->priv; | |
2107 | struct ath_softc *sc = aphy->sc; | |
3430098a | 2108 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 2109 | struct ieee80211_supported_band *sband; |
3430098a FF |
2110 | struct ieee80211_channel *chan; |
2111 | unsigned long flags; | |
2112 | int pos; | |
2113 | ||
2114 | spin_lock_irqsave(&common->cc_lock, flags); | |
2115 | if (idx == 0) | |
2116 | ath_update_survey_stats(sc); | |
39162dbe FF |
2117 | |
2118 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
2119 | if (sband && idx >= sband->n_channels) { | |
2120 | idx -= sband->n_channels; | |
2121 | sband = NULL; | |
2122 | } | |
62dad5b0 | 2123 | |
39162dbe FF |
2124 | if (!sband) |
2125 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 2126 | |
3430098a FF |
2127 | if (!sband || idx >= sband->n_channels) { |
2128 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2129 | return -ENOENT; | |
4f1a5a4b | 2130 | } |
62dad5b0 | 2131 | |
3430098a FF |
2132 | chan = &sband->channels[idx]; |
2133 | pos = chan->hw_value; | |
2134 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
2135 | survey->channel = chan; | |
2136 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2137 | ||
62dad5b0 BP |
2138 | return 0; |
2139 | } | |
2140 | ||
0c98de65 S |
2141 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2142 | { | |
bce048d7 JM |
2143 | struct ath_wiphy *aphy = hw->priv; |
2144 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2145 | |
3d832611 | 2146 | mutex_lock(&sc->mutex); |
8089cc47 | 2147 | if (ath9k_wiphy_scanning(sc)) { |
8089cc47 | 2148 | /* |
30888338 LR |
2149 | * There is a race here in mac80211 but fixing it requires |
2150 | * we revisit how we handle the scan complete callback. | |
2151 | * After mac80211 fixes we will not have configured hardware | |
2152 | * to the home channel nor would we have configured the RX | |
2153 | * filter yet. | |
8089cc47 | 2154 | */ |
3d832611 | 2155 | mutex_unlock(&sc->mutex); |
8089cc47 JM |
2156 | return; |
2157 | } | |
2158 | ||
2159 | aphy->state = ATH_WIPHY_SCAN; | |
2160 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
3d832611 | 2161 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2162 | } |
2163 | ||
30888338 LR |
2164 | /* |
2165 | * XXX: this requires a revisit after the driver | |
2166 | * scan_complete gets moved to another place/removed in mac80211. | |
2167 | */ | |
0c98de65 S |
2168 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) |
2169 | { | |
bce048d7 JM |
2170 | struct ath_wiphy *aphy = hw->priv; |
2171 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2172 | |
3d832611 | 2173 | mutex_lock(&sc->mutex); |
8089cc47 | 2174 | aphy->state = ATH_WIPHY_ACTIVE; |
3d832611 | 2175 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2176 | } |
2177 | ||
e239d859 FF |
2178 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2179 | { | |
2180 | struct ath_wiphy *aphy = hw->priv; | |
2181 | struct ath_softc *sc = aphy->sc; | |
2182 | struct ath_hw *ah = sc->sc_ah; | |
2183 | ||
2184 | mutex_lock(&sc->mutex); | |
2185 | ah->coverage_class = coverage_class; | |
2186 | ath9k_hw_init_global_settings(ah); | |
2187 | mutex_unlock(&sc->mutex); | |
2188 | } | |
2189 | ||
6baff7f9 | 2190 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2191 | .tx = ath9k_tx, |
2192 | .start = ath9k_start, | |
2193 | .stop = ath9k_stop, | |
2194 | .add_interface = ath9k_add_interface, | |
2195 | .remove_interface = ath9k_remove_interface, | |
2196 | .config = ath9k_config, | |
8feceb67 | 2197 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2198 | .sta_add = ath9k_sta_add, |
2199 | .sta_remove = ath9k_sta_remove, | |
8feceb67 | 2200 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2201 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2202 | .set_key = ath9k_set_key, |
8feceb67 | 2203 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2204 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2205 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2206 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2207 | .get_survey = ath9k_get_survey, |
0c98de65 S |
2208 | .sw_scan_start = ath9k_sw_scan_start, |
2209 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 2210 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2211 | .set_coverage_class = ath9k_set_coverage_class, |
8feceb67 | 2212 | }; |