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mac80211/cfg80211: add station events
[linux-block.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
f078f209
LR		 21static char *dev_info = "ath9k";
22
23MODULE_AUTHOR("Atheros Communications");
24MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26MODULE_LICENSE("Dual BSD/GPL");
27
b3bd89ce
JM		 28static int modparam_nohwcrypt;
29module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
faa27fae
LR		 32static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
33module_param_named(debug, ath9k_debug, uint, 0);
af1fc67c 34MODULE_PARM_DESC(debug, "Debugging mask");
faa27fae 35
5f8e077c
LR		 36/* We use the hw_value as an index into our private channel structure */
37
38#define CHAN2G(_freq, _idx) { \
39 .center_freq = (_freq), \
40 .hw_value = (_idx), \
eeddfd9d 41 .max_power = 20, \
5f8e077c
LR		 42}
43
44#define CHAN5G(_freq, _idx) { \
45 .band = IEEE80211_BAND_5GHZ, \
46 .center_freq = (_freq), \
47 .hw_value = (_idx), \
eeddfd9d 48 .max_power = 20, \
5f8e077c
LR		 49}
50
51/* Some 2 GHz radios are actually tunable on 2312-2732
52 * on 5 MHz steps, we support the channels which we know
53 * we have calibration data for all cards though to make
54 * this static */
55static struct ieee80211_channel ath9k_2ghz_chantable[] = {
56 CHAN2G(2412, 0), /* Channel 1 */
57 CHAN2G(2417, 1), /* Channel 2 */
58 CHAN2G(2422, 2), /* Channel 3 */
59 CHAN2G(2427, 3), /* Channel 4 */
60 CHAN2G(2432, 4), /* Channel 5 */
61 CHAN2G(2437, 5), /* Channel 6 */
62 CHAN2G(2442, 6), /* Channel 7 */
63 CHAN2G(2447, 7), /* Channel 8 */
64 CHAN2G(2452, 8), /* Channel 9 */
65 CHAN2G(2457, 9), /* Channel 10 */
66 CHAN2G(2462, 10), /* Channel 11 */
67 CHAN2G(2467, 11), /* Channel 12 */
68 CHAN2G(2472, 12), /* Channel 13 */
69 CHAN2G(2484, 13), /* Channel 14 */
70};
71
72/* Some 5 GHz radios are actually tunable on XXXX-YYYY
73 * on 5 MHz steps, we support the channels which we know
74 * we have calibration data for all cards though to make
75 * this static */
76static struct ieee80211_channel ath9k_5ghz_chantable[] = {
77 /* _We_ call this UNII 1 */
78 CHAN5G(5180, 14), /* Channel 36 */
79 CHAN5G(5200, 15), /* Channel 40 */
80 CHAN5G(5220, 16), /* Channel 44 */
81 CHAN5G(5240, 17), /* Channel 48 */
82 /* _We_ call this UNII 2 */
83 CHAN5G(5260, 18), /* Channel 52 */
84 CHAN5G(5280, 19), /* Channel 56 */
85 CHAN5G(5300, 20), /* Channel 60 */
86 CHAN5G(5320, 21), /* Channel 64 */
87 /* _We_ call this "Middle band" */
88 CHAN5G(5500, 22), /* Channel 100 */
89 CHAN5G(5520, 23), /* Channel 104 */
90 CHAN5G(5540, 24), /* Channel 108 */
91 CHAN5G(5560, 25), /* Channel 112 */
92 CHAN5G(5580, 26), /* Channel 116 */
93 CHAN5G(5600, 27), /* Channel 120 */
94 CHAN5G(5620, 28), /* Channel 124 */
95 CHAN5G(5640, 29), /* Channel 128 */
96 CHAN5G(5660, 30), /* Channel 132 */
97 CHAN5G(5680, 31), /* Channel 136 */
98 CHAN5G(5700, 32), /* Channel 140 */
99 /* _We_ call this UNII 3 */
100 CHAN5G(5745, 33), /* Channel 149 */
101 CHAN5G(5765, 34), /* Channel 153 */
102 CHAN5G(5785, 35), /* Channel 157 */
103 CHAN5G(5805, 36), /* Channel 161 */
104 CHAN5G(5825, 37), /* Channel 165 */
105};
106
545750d3
FF		 107/* Atheros hardware rate code addition for short premble */
108#define SHPCHECK(__hw_rate, __flags) \
109 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
110
111#define RATE(_bitrate, _hw_rate, _flags) { \
112 .bitrate = (_bitrate), \
113 .flags = (_flags), \
114 .hw_value = (_hw_rate), \
115 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
116}
117
118static struct ieee80211_rate ath9k_legacy_rates[] = {
119 RATE(10, 0x1b, 0),
120 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
121 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
122 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATE(60, 0x0b, 0),
124 RATE(90, 0x0f, 0),
125 RATE(120, 0x0a, 0),
126 RATE(180, 0x0e, 0),
127 RATE(240, 0x09, 0),
128 RATE(360, 0x0d, 0),
129 RATE(480, 0x08, 0),
130 RATE(540, 0x0c, 0),
131};
132
ce111bad
LR		 133static void ath_cache_conf_rate(struct ath_softc *sc,
134 struct ieee80211_conf *conf)
ff37e337 135{
030bb495
LR		 136 switch (conf->channel->band) {
137 case IEEE80211_BAND_2GHZ:
138 if (conf_is_ht20(conf))
545750d3 139 sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
030bb495 140 else if (conf_is_ht40_minus(conf))
545750d3 141 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
030bb495 142 else if (conf_is_ht40_plus(conf))
545750d3 143 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
96742256 144 else
545750d3 145 sc->cur_rate_mode = ATH9K_MODE_11G;
030bb495
LR		 146 break;
147 case IEEE80211_BAND_5GHZ:
148 if (conf_is_ht20(conf))
545750d3 149 sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
030bb495 150 else if (conf_is_ht40_minus(conf))
545750d3 151 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
030bb495 152 else if (conf_is_ht40_plus(conf))
545750d3 153 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
030bb495 154 else
545750d3 155 sc->cur_rate_mode = ATH9K_MODE_11A;
030bb495
LR		 156 break;
157 default:
ce111bad 158 BUG_ON(1);
030bb495
LR		 159 break;
160 }
ff37e337
S		 161}
162
163static void ath_update_txpow(struct ath_softc *sc)
164{
cbe61d8a 165 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 166 u32 txpow;
167
17d7904d
S		 168 if (sc->curtxpow != sc->config.txpowlimit) {
169 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 170 /* read back in case value is clamped */
171 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 172 sc->curtxpow = txpow;
ff37e337
S		 173 }
174}
175
176static u8 parse_mpdudensity(u8 mpdudensity)
177{
178 /*
179 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
180 * 0 for no restriction
181 * 1 for 1/4 us
182 * 2 for 1/2 us
183 * 3 for 1 us
184 * 4 for 2 us
185 * 5 for 4 us
186 * 6 for 8 us
187 * 7 for 16 us
188 */
189 switch (mpdudensity) {
190 case 0:
191 return 0;
192 case 1:
193 case 2:
194 case 3:
195 /* Our lower layer calculations limit our precision to
196 1 microsecond */
197 return 1;
198 case 4:
199 return 2;
200 case 5:
201 return 4;
202 case 6:
203 return 8;
204 case 7:
205 return 16;
206 default:
207 return 0;
208 }
209}
210
82880a7c
VT		 211static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
212 struct ieee80211_hw *hw)
213{
214 struct ieee80211_channel *curchan = hw->conf.channel;
215 struct ath9k_channel *channel;
216 u8 chan_idx;
217
218 chan_idx = curchan->hw_value;
219 channel = &sc->sc_ah->channels[chan_idx];
220 ath9k_update_ichannel(sc, hw, channel);
221 return channel;
222}
223
9ecdef4b 224static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 225{
226 unsigned long flags;
227 bool ret;
228
9ecdef4b
LR		 229 spin_lock_irqsave(&sc->sc_pm_lock, flags);
230 ret = ath9k_hw_setpower(sc->sc_ah, mode);
231 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 232
233 return ret;
234}
235
a91d75ae
LR		 236void ath9k_ps_wakeup(struct ath_softc *sc)
237{
238 unsigned long flags;
239
240 spin_lock_irqsave(&sc->sc_pm_lock, flags);
241 if (++sc->ps_usecount != 1)
242 goto unlock;
243
9ecdef4b 244 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae
LR		 245
246 unlock:
247 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
248}
249
250void ath9k_ps_restore(struct ath_softc *sc)
251{
252 unsigned long flags;
253
254 spin_lock_irqsave(&sc->sc_pm_lock, flags);
255 if (--sc->ps_usecount != 0)
256 goto unlock;
257
258 if (sc->ps_enabled &&
259 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
260 SC_OP_WAIT_FOR_CAB |
261 SC_OP_WAIT_FOR_PSPOLL_DATA |
262 SC_OP_WAIT_FOR_TX_ACK)))
9ecdef4b 263 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR		 264
265 unlock:
266 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
267}
268
ff37e337
S		 269/*
270 * Set/change channels. If the channel is really being changed, it's done
271 * by reseting the chip. To accomplish this we must first cleanup any pending
272 * DMA, then restart stuff.
273*/
0e2dedf9
JM		 274int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
275 struct ath9k_channel *hchan)
ff37e337 276{
cbe61d8a 277 struct ath_hw *ah = sc->sc_ah;
c46917bb 278 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 279 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 280 bool fastcc = true, stopped;
ae8d2858
LR		 281 struct ieee80211_channel *channel = hw->conf.channel;
282 int r;
ff37e337
S		 283
284 if (sc->sc_flags & SC_OP_INVALID)
285 return -EIO;
286
3cbb5dd7
VN		 287 ath9k_ps_wakeup(sc);
288
c0d7c7af
LR		 289 /*
290 * This is only performed if the channel settings have
291 * actually changed.
292 *
293 * To switch channels clear any pending DMA operations;
294 * wait long enough for the RX fifo to drain, reset the
295 * hardware at the new frequency, and then re-enable
296 * the relevant bits of the h/w.
297 */
298 ath9k_hw_set_interrupts(ah, 0);
043a0405 299 ath_drain_all_txq(sc, false);
c0d7c7af 300 stopped = ath_stoprecv(sc);
ff37e337 301
c0d7c7af
LR		 302 /* XXX: do not flush receive queue here. We don't want
303 * to flush data frames already in queue because of
304 * changing channel. */
ff37e337 305
c0d7c7af
LR		 306 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
307 fastcc = false;
308
c46917bb 309 ath_print(common, ATH_DBG_CONFIG,
25c56eec 310 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
c46917bb 311 sc->sc_ah->curchan->channel,
25c56eec 312 channel->center_freq, conf_is_ht40(conf));
ff37e337 313
c0d7c7af
LR		 314 spin_lock_bh(&sc->sc_resetlock);
315
316 r = ath9k_hw_reset(ah, hchan, fastcc);
317 if (r) {
c46917bb
LR		 318 ath_print(common, ATH_DBG_FATAL,
319 "Unable to reset channel (%u Mhz) "
320 "reset status %d\n",
321 channel->center_freq, r);
c0d7c7af 322 spin_unlock_bh(&sc->sc_resetlock);
3989279c 323 goto ps_restore;
ff37e337 324 }
c0d7c7af
LR		 325 spin_unlock_bh(&sc->sc_resetlock);
326
c0d7c7af
LR		 327 sc->sc_flags &= ~SC_OP_FULL_RESET;
328
329 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 330 ath_print(common, ATH_DBG_FATAL,
331 "Unable to restart recv logic\n");
3989279c
GJ		 332 r = -EIO;
333 goto ps_restore;
c0d7c7af
LR		 334 }
335
336 ath_cache_conf_rate(sc, &hw->conf);
337 ath_update_txpow(sc);
17d7904d 338 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 339
340 ps_restore:
3cbb5dd7 341 ath9k_ps_restore(sc);
3989279c 342 return r;
ff37e337
S		 343}
344
345/*
346 * This routine performs the periodic noise floor calibration function
347 * that is used to adjust and optimize the chip performance. This
348 * takes environmental changes (location, temperature) into account.
349 * When the task is complete, it reschedules itself depending on the
350 * appropriate interval that was calculated.
351 */
352static void ath_ani_calibrate(unsigned long data)
353{
20977d3e
S		 354 struct ath_softc *sc = (struct ath_softc *)data;
355 struct ath_hw *ah = sc->sc_ah;
c46917bb 356 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 357 bool longcal = false;
358 bool shortcal = false;
359 bool aniflag = false;
360 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 361 u32 cal_interval, short_cal_interval;
ff37e337 362
20977d3e
S		 363 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
364 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 365
1ffc1c61
JM		 366 /* Only calibrate if awake */
367 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
368 goto set_timer;
369
370 ath9k_ps_wakeup(sc);
371
ff37e337 372 /* Long calibration runs independently of short calibration. */
3d536acf 373 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 374 longcal = true;
c46917bb 375 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 376 common->ani.longcal_timer = timestamp;
ff37e337
S		 377 }
378
17d7904d 379 /* Short calibration applies only while caldone is false */
3d536acf
LR		 380 if (!common->ani.caldone) {
381 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 382 shortcal = true;
c46917bb
LR		 383 ath_print(common, ATH_DBG_ANI,
384 "shortcal @%lu\n", jiffies);
3d536acf
LR		 385 common->ani.shortcal_timer = timestamp;
386 common->ani.resetcal_timer = timestamp;
ff37e337
S		 387 }
388 } else {
3d536acf 389 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 390 ATH_RESTART_CALINTERVAL) {
3d536acf
LR		 391 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
392 if (common->ani.caldone)
393 common->ani.resetcal_timer = timestamp;
ff37e337
S		 394 }
395 }
396
397 /* Verify whether we must check ANI */
3d536acf 398 if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 399 aniflag = true;
3d536acf 400 common->ani.checkani_timer = timestamp;
ff37e337
S		 401 }
402
403 /* Skip all processing if there's nothing to do. */
404 if (longcal || shortcal || aniflag) {
405 /* Call ANI routine if necessary */
406 if (aniflag)
22e66a4c 407 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S		 408
409 /* Perform calibration if necessary */
410 if (longcal || shortcal) {
3d536acf 411 common->ani.caldone =
43c27613
LR		 412 ath9k_hw_calibrate(ah,
413 ah->curchan,
414 common->rx_chainmask,
415 longcal);
379f0440
S		 416
417 if (longcal)
3d536acf 418 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
379f0440
S		 419 ah->curchan);
420
c46917bb
LR		 421 ath_print(common, ATH_DBG_ANI,
422 " calibrate chan %u/%x nf: %d\n",
423 ah->curchan->channel,
424 ah->curchan->channelFlags,
3d536acf 425 common->ani.noise_floor);
ff37e337
S		 426 }
427 }
428
1ffc1c61
JM		 429 ath9k_ps_restore(sc);
430
20977d3e 431set_timer:
ff37e337
S		 432 /*
433 * Set timer interval based on previous results.
434 * The interval must be the shortest necessary to satisfy ANI,
435 * short calibration and long calibration.
436 */
aac9207e 437 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 438 if (sc->sc_ah->config.enable_ani)
aac9207e 439 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
3d536acf 440 if (!common->ani.caldone)
20977d3e 441 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 442
3d536acf 443 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 444}
445
3d536acf 446static void ath_start_ani(struct ath_common *common)
415f738e
S		 447{
448 unsigned long timestamp = jiffies_to_msecs(jiffies);
449
3d536acf
LR		 450 common->ani.longcal_timer = timestamp;
451 common->ani.shortcal_timer = timestamp;
452 common->ani.checkani_timer = timestamp;
415f738e 453
3d536acf 454 mod_timer(&common->ani.timer,
415f738e
S		 455 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
456}
457
ff37e337
S		 458/*
459 * Update tx/rx chainmask. For legacy association,
460 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 461 * the chainmask configuration, for bt coexistence, use
462 * the chainmask configuration even in legacy mode.
ff37e337 463 */
0e2dedf9 464void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 465{
af03abec 466 struct ath_hw *ah = sc->sc_ah;
43c27613 467 struct ath_common *common = ath9k_hw_common(ah);
af03abec 468
3d832611 469 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
766ec4a9 470 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
43c27613
LR		 471 common->tx_chainmask = ah->caps.tx_chainmask;
472 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337 473 } else {
43c27613
LR		 474 common->tx_chainmask = 1;
475 common->rx_chainmask = 1;
ff37e337
S		 476 }
477
43c27613 478 ath_print(common, ATH_DBG_CONFIG,
c46917bb 479 "tx chmask: %d, rx chmask: %d\n",
43c27613
LR		 480 common->tx_chainmask,
481 common->rx_chainmask);
ff37e337
S		 482}
483
484static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
485{
486 struct ath_node *an;
487
488 an = (struct ath_node *)sta->drv_priv;
489
87792efc 490 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 491 ath_tx_node_init(sc, an);
9e98ac65 492 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 493 sta->ht_cap.ampdu_factor);
494 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 495 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 496 }
ff37e337
S		 497}
498
499static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
500{
501 struct ath_node *an = (struct ath_node *)sta->drv_priv;
502
503 if (sc->sc_flags & SC_OP_TXAGGR)
504 ath_tx_node_cleanup(sc, an);
505}
506
507static void ath9k_tasklet(unsigned long data)
508{
509 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 510 struct ath_hw *ah = sc->sc_ah;
c46917bb 511 struct ath_common *common = ath9k_hw_common(ah);
af03abec 512
17d7904d 513 u32 status = sc->intrstatus;
ff37e337 514
153e080d
VT		 515 ath9k_ps_wakeup(sc);
516
ff37e337 517 if (status & ATH9K_INT_FATAL) {
ff37e337 518 ath_reset(sc, false);
153e080d 519 ath9k_ps_restore(sc);
ff37e337 520 return;
063d8be3 521 }
ff37e337 522
063d8be3
S		 523 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
524 spin_lock_bh(&sc->rx.rxflushlock);
525 ath_rx_tasklet(sc, 0);
526 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 527 }
528
063d8be3
S		 529 if (status & ATH9K_INT_TX)
530 ath_tx_tasklet(sc);
531
96148326 532 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 533 /*
534 * TSF sync does not look correct; remain awake to sync with
535 * the next Beacon.
536 */
c46917bb
LR		 537 ath_print(common, ATH_DBG_PS,
538 "TSFOOR - Sync with next Beacon\n");
ccdfeab6 539 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 540 }
541
766ec4a9 542 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT		 543 if (status & ATH9K_INT_GENTIMER)
544 ath_gen_timer_isr(sc->sc_ah);
545
ff37e337 546 /* re-enable hardware interrupt */
af03abec 547 ath9k_hw_set_interrupts(ah, sc->imask);
153e080d 548 ath9k_ps_restore(sc);
ff37e337
S		 549}
550
6baff7f9 551irqreturn_t ath_isr(int irq, void *dev)
ff37e337 552{
063d8be3
S		 553#define SCHED_INTR ( \
554 ATH9K_INT_FATAL | \
555 ATH9K_INT_RXORN | \
556 ATH9K_INT_RXEOL | \
557 ATH9K_INT_RX | \
558 ATH9K_INT_TX | \
559 ATH9K_INT_BMISS | \
560 ATH9K_INT_CST | \
ebb8e1d7
VT		 561 ATH9K_INT_TSFOOR | \
562 ATH9K_INT_GENTIMER)
063d8be3 563
ff37e337 564 struct ath_softc *sc = dev;
cbe61d8a 565 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 566 enum ath9k_int status;
567 bool sched = false;
568
063d8be3
S		 569 /*
570 * The hardware is not ready/present, don't
571 * touch anything. Note this can happen early
572 * on if the IRQ is shared.
573 */
574 if (sc->sc_flags & SC_OP_INVALID)
575 return IRQ_NONE;
ff37e337 576
063d8be3
S		 577
578 /* shared irq, not for us */
579
153e080d 580 if (!ath9k_hw_intrpend(ah))
063d8be3 581 return IRQ_NONE;
063d8be3
S		 582
583 /*
584 * Figure out the reason(s) for the interrupt. Note
585 * that the hal returns a pseudo-ISR that may include
586 * bits we haven't explicitly enabled so we mask the
587 * value to insure we only process bits we requested.
588 */
589 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
590 status &= sc->imask; /* discard unasked-for bits */
ff37e337 591
063d8be3
S		 592 /*
593 * If there are no status bits set, then this interrupt was not
594 * for me (should have been caught above).
595 */
153e080d 596 if (!status)
063d8be3 597 return IRQ_NONE;
ff37e337 598
063d8be3
S		 599 /* Cache the status */
600 sc->intrstatus = status;
601
602 if (status & SCHED_INTR)
603 sched = true;
604
605 /*
606 * If a FATAL or RXORN interrupt is received, we have to reset the
607 * chip immediately.
608 */
609 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
610 goto chip_reset;
611
612 if (status & ATH9K_INT_SWBA)
613 tasklet_schedule(&sc->bcon_tasklet);
614
615 if (status & ATH9K_INT_TXURN)
616 ath9k_hw_updatetxtriglevel(ah, true);
617
618 if (status & ATH9K_INT_MIB) {
ff37e337 619 /*
063d8be3
S		 620 * Disable interrupts until we service the MIB
621 * interrupt; otherwise it will continue to
622 * fire.
ff37e337 623 */
063d8be3
S		 624 ath9k_hw_set_interrupts(ah, 0);
625 /*
626 * Let the hal handle the event. We assume
627 * it will clear whatever condition caused
628 * the interrupt.
629 */
22e66a4c 630 ath9k_hw_procmibevent(ah);
063d8be3
S		 631 ath9k_hw_set_interrupts(ah, sc->imask);
632 }
ff37e337 633
153e080d
VT		 634 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
635 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 636 /* Clear RxAbort bit so that we can
637 * receive frames */
9ecdef4b 638 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 639 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 640 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 641 }
063d8be3
S		 642
643chip_reset:
ff37e337 644
817e11de
S		 645 ath_debug_stat_interrupt(sc, status);
646
ff37e337
S		 647 if (sched) {
648 /* turn off every interrupt except SWBA */
17d7904d 649 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 650 tasklet_schedule(&sc->intr_tq);
651 }
652
653 return IRQ_HANDLED;
063d8be3
S		 654
655#undef SCHED_INTR
ff37e337
S		 656}
657
f078f209 658static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 659 struct ieee80211_channel *chan,
094d05dc 660 enum nl80211_channel_type channel_type)
f078f209
LR		 661{
662 u32 chanmode = 0;
f078f209
LR		 663
664 switch (chan->band) {
665 case IEEE80211_BAND_2GHZ:
094d05dc
S		 666 switch(channel_type) {
667 case NL80211_CHAN_NO_HT:
668 case NL80211_CHAN_HT20:
f078f209 669 chanmode = CHANNEL_G_HT20;
094d05dc
S		 670 break;
671 case NL80211_CHAN_HT40PLUS:
f078f209 672 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 673 break;
674 case NL80211_CHAN_HT40MINUS:
f078f209 675 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 676 break;
677 }
f078f209
LR		 678 break;
679 case IEEE80211_BAND_5GHZ:
094d05dc
S		 680 switch(channel_type) {
681 case NL80211_CHAN_NO_HT:
682 case NL80211_CHAN_HT20:
f078f209 683 chanmode = CHANNEL_A_HT20;
094d05dc
S		 684 break;
685 case NL80211_CHAN_HT40PLUS:
f078f209 686 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 687 break;
688 case NL80211_CHAN_HT40MINUS:
f078f209 689 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 690 break;
691 }
f078f209
LR		 692 break;
693 default:
694 break;
695 }
696
697 return chanmode;
698}
699
7e86c104 700static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
3f53dd64
JM		 701 struct ath9k_keyval *hk, const u8 *addr,
702 bool authenticator)
f078f209 703{
7e86c104 704 struct ath_hw *ah = common->ah;
6ace2891
JM		 705 const u8 *key_rxmic;
706 const u8 *key_txmic;
f078f209 707
6ace2891
JM		 708 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
709 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 710
711 if (addr == NULL) {
d216aaa6
JM		 712 /*
713 * Group key installation - only two key cache entries are used
714 * regardless of splitmic capability since group key is only
715 * used either for TX or RX.
716 */
3f53dd64
JM		 717 if (authenticator) {
718 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
719 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
720 } else {
721 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
722 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
723 }
7e86c104 724 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
f078f209 725 }
7e86c104 726 if (!common->splitmic) {
d216aaa6 727 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 728 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
729 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
7e86c104 730 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
f078f209 731 }
d216aaa6
JM		 732
733 /* Separate key cache entries for TX and RX */
734
735 /* TX key goes at first index, RX key at +32. */
f078f209 736 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
7e86c104 737 if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
d216aaa6 738 /* TX MIC entry failed. No need to proceed further */
7e86c104 739 ath_print(common, ATH_DBG_FATAL,
c46917bb 740 "Setting TX MIC Key Failed\n");
f078f209
LR		 741 return 0;
742 }
743
744 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
745 /* XXX delete tx key on failure? */
7e86c104 746 return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
6ace2891
JM		 747}
748
7e86c104 749static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
6ace2891
JM		 750{
751 int i;
752
7e86c104
LR		 753 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
754 if (test_bit(i, common->keymap) ||
755 test_bit(i + 64, common->keymap))
6ace2891 756 continue; /* At least one part of TKIP key allocated */
7e86c104
LR		 757 if (common->splitmic &&
758 (test_bit(i + 32, common->keymap) ||
759 test_bit(i + 64 + 32, common->keymap)))
6ace2891
JM		 760 continue; /* At least one part of TKIP key allocated */
761
762 /* Found a free slot for a TKIP key */
763 return i;
764 }
765 return -1;
766}
767
7e86c104 768static int ath_reserve_key_cache_slot(struct ath_common *common)
6ace2891
JM		 769{
770 int i;
771
772 /* First, try to find slots that would not be available for TKIP. */
7e86c104
LR		 773 if (common->splitmic) {
774 for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
775 if (!test_bit(i, common->keymap) &&
776 (test_bit(i + 32, common->keymap) ||
777 test_bit(i + 64, common->keymap) ||
778 test_bit(i + 64 + 32, common->keymap)))
6ace2891 779 return i;
7e86c104
LR		 780 if (!test_bit(i + 32, common->keymap) &&
781 (test_bit(i, common->keymap) ||
782 test_bit(i + 64, common->keymap) ||
783 test_bit(i + 64 + 32, common->keymap)))
6ace2891 784 return i + 32;
7e86c104
LR		 785 if (!test_bit(i + 64, common->keymap) &&
786 (test_bit(i , common->keymap) ||
787 test_bit(i + 32, common->keymap) ||
788 test_bit(i + 64 + 32, common->keymap)))
ea612132 789 return i + 64;
7e86c104
LR		 790 if (!test_bit(i + 64 + 32, common->keymap) &&
791 (test_bit(i, common->keymap) ||
792 test_bit(i + 32, common->keymap) ||
793 test_bit(i + 64, common->keymap)))
ea612132 794 return i + 64 + 32;
6ace2891
JM		 795 }
796 } else {
7e86c104
LR		 797 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
798 if (!test_bit(i, common->keymap) &&
799 test_bit(i + 64, common->keymap))
6ace2891 800 return i;
7e86c104
LR		 801 if (test_bit(i, common->keymap) &&
802 !test_bit(i + 64, common->keymap))
6ace2891
JM		 803 return i + 64;
804 }
805 }
806
807 /* No partially used TKIP slots, pick any available slot */
7e86c104 808 for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
be2864cf
JM		 809 /* Do not allow slots that could be needed for TKIP group keys
810 * to be used. This limitation could be removed if we know that
811 * TKIP will not be used. */
812 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
813 continue;
7e86c104 814 if (common->splitmic) {
be2864cf
JM		 815 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
816 continue;
817 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
818 continue;
819 }
820
7e86c104 821 if (!test_bit(i, common->keymap))
6ace2891
JM		 822 return i; /* Found a free slot for a key */
823 }
824
825 /* No free slot found */
826 return -1;
f078f209
LR		 827}
828
7e86c104 829static int ath_key_config(struct ath_common *common,
3f53dd64 830 struct ieee80211_vif *vif,
dc822b5d 831 struct ieee80211_sta *sta,
f078f209
LR		 832 struct ieee80211_key_conf *key)
833{
7e86c104 834 struct ath_hw *ah = common->ah;
f078f209
LR		 835 struct ath9k_keyval hk;
836 const u8 *mac = NULL;
837 int ret = 0;
6ace2891 838 int idx;
f078f209
LR		 839
840 memset(&hk, 0, sizeof(hk));
841
842 switch (key->alg) {
843 case ALG_WEP:
844 hk.kv_type = ATH9K_CIPHER_WEP;
845 break;
846 case ALG_TKIP:
847 hk.kv_type = ATH9K_CIPHER_TKIP;
848 break;
849 case ALG_CCMP:
850 hk.kv_type = ATH9K_CIPHER_AES_CCM;
851 break;
852 default:
ca470b29 853 return -EOPNOTSUPP;
f078f209
LR		 854 }
855
6ace2891 856 hk.kv_len = key->keylen;
f078f209
LR		 857 memcpy(hk.kv_val, key->key, key->keylen);
858
6ace2891
JM		 859 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
860 /* For now, use the default keys for broadcast keys. This may
861 * need to change with virtual interfaces. */
862 idx = key->keyidx;
863 } else if (key->keyidx) {
dc822b5d
JB		 864 if (WARN_ON(!sta))
865 return -EOPNOTSUPP;
866 mac = sta->addr;
867
6ace2891
JM		 868 if (vif->type != NL80211_IFTYPE_AP) {
869 /* Only keyidx 0 should be used with unicast key, but
870 * allow this for client mode for now. */
871 idx = key->keyidx;
872 } else
873 return -EIO;
f078f209 874 } else {
dc822b5d
JB		 875 if (WARN_ON(!sta))
876 return -EOPNOTSUPP;
877 mac = sta->addr;
878
6ace2891 879 if (key->alg == ALG_TKIP)
7e86c104 880 idx = ath_reserve_key_cache_slot_tkip(common);
6ace2891 881 else
7e86c104 882 idx = ath_reserve_key_cache_slot(common);
6ace2891 883 if (idx < 0)
ca470b29 884 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 885 }
886
887 if (key->alg == ALG_TKIP)
7e86c104 888 ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
3f53dd64 889 vif->type == NL80211_IFTYPE_AP);
f078f209 890 else
7e86c104 891 ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
f078f209
LR		 892
893 if (!ret)
894 return -EIO;
895
7e86c104 896 set_bit(idx, common->keymap);
6ace2891 897 if (key->alg == ALG_TKIP) {
7e86c104
LR		 898 set_bit(idx + 64, common->keymap);
899 if (common->splitmic) {
900 set_bit(idx + 32, common->keymap);
901 set_bit(idx + 64 + 32, common->keymap);
6ace2891
JM		 902 }
903 }
904
905 return idx;
f078f209
LR		 906}
907
7e86c104 908static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
f078f209 909{
7e86c104
LR		 910 struct ath_hw *ah = common->ah;
911
912 ath9k_hw_keyreset(ah, key->hw_key_idx);
6ace2891
JM		 913 if (key->hw_key_idx < IEEE80211_WEP_NKID)
914 return;
915
7e86c104 916 clear_bit(key->hw_key_idx, common->keymap);
6ace2891
JM		 917 if (key->alg != ALG_TKIP)
918 return;
f078f209 919
7e86c104
LR		 920 clear_bit(key->hw_key_idx + 64, common->keymap);
921 if (common->splitmic) {
922 clear_bit(key->hw_key_idx + 32, common->keymap);
923 clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
6ace2891 924 }
f078f209
LR		 925}
926
eb2599ca
S		 927static void setup_ht_cap(struct ath_softc *sc,
928 struct ieee80211_sta_ht_cap *ht_info)
f078f209 929{
43c27613 930 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
140add21 931 u8 tx_streams, rx_streams;
f078f209 932
d9fe60de
JB		 933 ht_info->ht_supported = true;
934 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
935 IEEE80211_HT_CAP_SM_PS |
936 IEEE80211_HT_CAP_SGI_40 |
937 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 938
9e98ac65
S		 939 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
940 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 941
d9fe60de
JB		 942 /* set up supported mcs set */
943 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
43c27613
LR		 944 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
945 1 : 2;
946 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
947 1 : 2;
140add21
SB		 948
949 if (tx_streams != rx_streams) {
43c27613 950 ath_print(common, ATH_DBG_CONFIG,
c46917bb
LR		 951 "TX streams %d, RX streams: %d\n",
952 tx_streams, rx_streams);
140add21
SB		 953 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
954 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
955 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
956 }
eb2599ca 957
140add21
SB		 958 ht_info->mcs.rx_mask[0] = 0xff;
959 if (rx_streams >= 2)
eb2599ca 960 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 961
140add21 962 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 963}
964
8feceb67 965static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 966 struct ieee80211_vif *vif,
8feceb67 967 struct ieee80211_bss_conf *bss_conf)
f078f209 968{
f2b2143e 969 struct ath_hw *ah = sc->sc_ah;
1510718d 970 struct ath_common *common = ath9k_hw_common(ah);
f078f209 971
8feceb67 972 if (bss_conf->assoc) {
c46917bb
LR		 973 ath_print(common, ATH_DBG_CONFIG,
974 "Bss Info ASSOC %d, bssid: %pM\n",
975 bss_conf->aid, common->curbssid);
f078f209 976
8feceb67 977 /* New association, store aid */
1510718d 978 common->curaid = bss_conf->aid;
f2b2143e 979 ath9k_hw_write_associd(ah);
2664f201
SB		 980
981 /*
982 * Request a re-configuration of Beacon related timers
983 * on the receipt of the first Beacon frame (i.e.,
984 * after time sync with the AP).
985 */
986 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 987
8feceb67 988 /* Configure the beacon */
2c3db3d5 989 ath_beacon_config(sc, vif);
f078f209 990
8feceb67 991 /* Reset rssi stats */
22e66a4c 992 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 993
3d536acf 994 ath_start_ani(common);
8feceb67 995 } else {
c46917bb 996 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 997 common->curaid = 0;
f38faa31 998 /* Stop ANI */
3d536acf 999 del_timer_sync(&common->ani.timer);
f078f209 1000 }
8feceb67 1001}
f078f209 1002
8feceb67
VT		 1003/********************************/
1004/* LED functions */
1005/********************************/
f078f209 1006
f2bffa7e
VT		 1007static void ath_led_blink_work(struct work_struct *work)
1008{
1009 struct ath_softc *sc = container_of(work, struct ath_softc,
1010 ath_led_blink_work.work);
1011
1012 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1013 return;
85067c06
VT		 1014
1015 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1016 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
08fc5c1b 1017 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
85067c06 1018 else
08fc5c1b 1019 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
85067c06 1020 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e 1021
42935eca
LR		 1022 ieee80211_queue_delayed_work(sc->hw,
1023 &sc->ath_led_blink_work,
1024 (sc->sc_flags & SC_OP_LED_ON) ?
1025 msecs_to_jiffies(sc->led_off_duration) :
1026 msecs_to_jiffies(sc->led_on_duration));
f2bffa7e 1027
85067c06
VT		 1028 sc->led_on_duration = sc->led_on_cnt ?
1029 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1030 ATH_LED_ON_DURATION_IDLE;
1031 sc->led_off_duration = sc->led_off_cnt ?
1032 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1033 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 1034 sc->led_on_cnt = sc->led_off_cnt = 0;
1035 if (sc->sc_flags & SC_OP_LED_ON)
1036 sc->sc_flags &= ~SC_OP_LED_ON;
1037 else
1038 sc->sc_flags |= SC_OP_LED_ON;
1039}
1040
8feceb67
VT		 1041static void ath_led_brightness(struct led_classdev *led_cdev,
1042 enum led_brightness brightness)
1043{
1044 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1045 struct ath_softc *sc = led->sc;
f078f209 1046
8feceb67
VT		 1047 switch (brightness) {
1048 case LED_OFF:
1049 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e 1050 led->led_type == ATH_LED_RADIO) {
08fc5c1b 1051 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
f2bffa7e 1052 (led->led_type == ATH_LED_RADIO));
8feceb67 1053 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1054 if (led->led_type == ATH_LED_RADIO)
1055 sc->sc_flags &= ~SC_OP_LED_ON;
1056 } else {
1057 sc->led_off_cnt++;
1058 }
8feceb67
VT		 1059 break;
1060 case LED_FULL:
f2bffa7e 1061 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1062 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
42935eca
LR		 1063 ieee80211_queue_delayed_work(sc->hw,
1064 &sc->ath_led_blink_work, 0);
f2bffa7e 1065 } else if (led->led_type == ATH_LED_RADIO) {
08fc5c1b 1066 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
f2bffa7e
VT		 1067 sc->sc_flags |= SC_OP_LED_ON;
1068 } else {
1069 sc->led_on_cnt++;
1070 }
8feceb67
VT		 1071 break;
1072 default:
1073 break;
f078f209 1074 }
8feceb67 1075}
f078f209 1076
8feceb67
VT		 1077static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1078 char *trigger)
1079{
1080 int ret;
f078f209 1081
8feceb67
VT		 1082 led->sc = sc;
1083 led->led_cdev.name = led->name;
1084 led->led_cdev.default_trigger = trigger;
1085 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1086
8feceb67
VT		 1087 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1088 if (ret)
c46917bb
LR		 1089 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1090 "Failed to register led:%s", led->name);
8feceb67
VT		 1091 else
1092 led->registered = 1;
1093 return ret;
1094}
f078f209 1095
8feceb67
VT		 1096static void ath_unregister_led(struct ath_led *led)
1097{
1098 if (led->registered) {
1099 led_classdev_unregister(&led->led_cdev);
1100 led->registered = 0;
f078f209 1101 }
f078f209
LR		 1102}
1103
8feceb67 1104static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1105{
8feceb67
VT		 1106 ath_unregister_led(&sc->assoc_led);
1107 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1108 ath_unregister_led(&sc->tx_led);
1109 ath_unregister_led(&sc->rx_led);
1110 ath_unregister_led(&sc->radio_led);
08fc5c1b 1111 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
8feceb67 1112}
f078f209 1113
8feceb67
VT		 1114static void ath_init_leds(struct ath_softc *sc)
1115{
1116 char *trigger;
1117 int ret;
f078f209 1118
08fc5c1b
VN		 1119 if (AR_SREV_9287(sc->sc_ah))
1120 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1121 else
1122 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1123
8feceb67 1124 /* Configure gpio 1 for output */
08fc5c1b 1125 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
8feceb67
VT		 1126 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1127 /* LED off, active low */
08fc5c1b 1128 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
7dcfdcd9 1129
f2bffa7e
VT		 1130 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1131
8feceb67
VT		 1132 trigger = ieee80211_get_radio_led_name(sc->hw);
1133 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1134 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1135 ret = ath_register_led(sc, &sc->radio_led, trigger);
1136 sc->radio_led.led_type = ATH_LED_RADIO;
1137 if (ret)
1138 goto fail;
7dcfdcd9 1139
8feceb67
VT		 1140 trigger = ieee80211_get_assoc_led_name(sc->hw);
1141 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1142 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1143 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1144 sc->assoc_led.led_type = ATH_LED_ASSOC;
1145 if (ret)
1146 goto fail;
f078f209 1147
8feceb67
VT		 1148 trigger = ieee80211_get_tx_led_name(sc->hw);
1149 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1150 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1151 ret = ath_register_led(sc, &sc->tx_led, trigger);
1152 sc->tx_led.led_type = ATH_LED_TX;
1153 if (ret)
1154 goto fail;
f078f209 1155
8feceb67
VT		 1156 trigger = ieee80211_get_rx_led_name(sc->hw);
1157 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1158 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1159 ret = ath_register_led(sc, &sc->rx_led, trigger);
1160 sc->rx_led.led_type = ATH_LED_RX;
1161 if (ret)
1162 goto fail;
f078f209 1163
8feceb67
VT		 1164 return;
1165
1166fail:
35c95ab9 1167 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67 1168 ath_deinit_leds(sc);
f078f209
LR		 1169}
1170
68a89116 1171void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 1172{
cbe61d8a 1173 struct ath_hw *ah = sc->sc_ah;
c46917bb 1174 struct ath_common *common = ath9k_hw_common(ah);
68a89116 1175 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 1176 int r;
500c064d 1177
3cbb5dd7 1178 ath9k_ps_wakeup(sc);
93b1b37f 1179 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 1180
159cd468
VT		 1181 if (!ah->curchan)
1182 ah->curchan = ath_get_curchannel(sc, sc->hw);
1183
d2f5b3a6 1184 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1185 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1186 if (r) {
c46917bb
LR		 1187 ath_print(common, ATH_DBG_FATAL,
1188 "Unable to reset channel %u (%uMhz) ",
1189 "reset status %d\n",
1190 channel->center_freq, r);
500c064d
VT		 1191 }
1192 spin_unlock_bh(&sc->sc_resetlock);
1193
1194 ath_update_txpow(sc);
1195 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 1196 ath_print(common, ATH_DBG_FATAL,
1197 "Unable to restart recv logic\n");
500c064d
VT		 1198 return;
1199 }
1200
1201 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1202 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1203
1204 /* Re-Enable interrupts */
17d7904d 1205 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1206
1207 /* Enable LED */
08fc5c1b 1208 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 1209 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 1210 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 1211
68a89116 1212 ieee80211_wake_queues(hw);
3cbb5dd7 1213 ath9k_ps_restore(sc);
500c064d
VT		 1214}
1215
68a89116 1216void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 1217{
cbe61d8a 1218 struct ath_hw *ah = sc->sc_ah;
68a89116 1219 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 1220 int r;
500c064d 1221
3cbb5dd7 1222 ath9k_ps_wakeup(sc);
68a89116 1223 ieee80211_stop_queues(hw);
500c064d
VT		 1224
1225 /* Disable LED */
08fc5c1b
VN		 1226 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1227 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT		 1228
1229 /* Disable interrupts */
1230 ath9k_hw_set_interrupts(ah, 0);
1231
043a0405 1232 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1233 ath_stoprecv(sc); /* turn off frame recv */
1234 ath_flushrecv(sc); /* flush recv queue */
1235
159cd468 1236 if (!ah->curchan)
68a89116 1237 ah->curchan = ath_get_curchannel(sc, hw);
159cd468 1238
500c064d 1239 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1240 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1241 if (r) {
c46917bb
LR		 1242 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1243 "Unable to reset channel %u (%uMhz) "
1244 "reset status %d\n",
1245 channel->center_freq, r);
500c064d
VT		 1246 }
1247 spin_unlock_bh(&sc->sc_resetlock);
1248
1249 ath9k_hw_phy_disable(ah);
93b1b37f 1250 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 1251 ath9k_ps_restore(sc);
9ecdef4b 1252 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1253}
1254
5077fd35
GJ		 1255/*******************/
1256/* Rfkill */
1257/*******************/
1258
500c064d
VT		 1259static bool ath_is_rfkill_set(struct ath_softc *sc)
1260{
cbe61d8a 1261 struct ath_hw *ah = sc->sc_ah;
500c064d 1262
2660b81a
S		 1263 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1264 ah->rfkill_polarity;
500c064d
VT		 1265}
1266
3b319aae 1267static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1268{
3b319aae
JB		 1269 struct ath_wiphy *aphy = hw->priv;
1270 struct ath_softc *sc = aphy->sc;
19d337df 1271 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1272
3b319aae 1273 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
500c064d
VT		 1274}
1275
3b319aae 1276static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1277{
3b319aae 1278 struct ath_hw *ah = sc->sc_ah;
9c84b797 1279
3b319aae
JB		 1280 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1281 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1282}
500c064d 1283
7fda1666
LR		 1284static void ath9k_uninit_hw(struct ath_softc *sc)
1285{
1286 struct ath_hw *ah = sc->sc_ah;
1287
1288 BUG_ON(!ah);
1289
1290 ath9k_exit_debug(ah);
1291 ath9k_hw_detach(ah);
1292 sc->sc_ah = NULL;
1293}
1294
2568835c 1295static void ath_clean_core(struct ath_softc *sc)
f078f209 1296{
8feceb67 1297 struct ieee80211_hw *hw = sc->hw;
4d6b228d 1298 struct ath_hw *ah = sc->sc_ah;
9c84b797 1299 int i = 0;
f078f209 1300
3cbb5dd7
VN		 1301 ath9k_ps_wakeup(sc);
1302
4d6b228d 1303 dev_dbg(sc->dev, "Detach ATH hw\n");
f078f209 1304
35c95ab9 1305 ath_deinit_leds(sc);
e31f7b96 1306 wiphy_rfkill_stop_polling(sc->hw->wiphy);
35c95ab9 1307
c52f33d0
JM		 1308 for (i = 0; i < sc->num_sec_wiphy; i++) {
1309 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1310 if (aphy == NULL)
1311 continue;
1312 sc->sec_wiphy[i] = NULL;
1313 ieee80211_unregister_hw(aphy->hw);
1314 ieee80211_free_hw(aphy->hw);
1315 }
3fcdfb4b 1316 ieee80211_unregister_hw(hw);
8feceb67
VT		 1317 ath_rx_cleanup(sc);
1318 ath_tx_cleanup(sc);
f078f209 1319
9c84b797
S		 1320 tasklet_kill(&sc->intr_tq);
1321 tasklet_kill(&sc->bcon_tasklet);
f078f209 1322
9c84b797 1323 if (!(sc->sc_flags & SC_OP_INVALID))
9ecdef4b 1324 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8feceb67 1325
9c84b797
S		 1326 /* cleanup tx queues */
1327 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1328 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1329 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797 1330
75d7839f 1331 if ((sc->btcoex.no_stomp_timer) &&
766ec4a9 1332 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1333 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
2568835c 1334}
1773912b 1335
2568835c
LR		 1336void ath_detach(struct ath_softc *sc)
1337{
1338 ath_clean_core(sc);
7fda1666 1339 ath9k_uninit_hw(sc);
f078f209
LR		 1340}
1341
bd96d390
LR		 1342void ath_cleanup(struct ath_softc *sc)
1343{
1344 struct ath_hw *ah = sc->sc_ah;
1345 struct ath_common *common = ath9k_hw_common(ah);
1346
1347 ath_clean_core(sc);
1348 free_irq(sc->irq, sc);
1349 ath_bus_cleanup(common);
1350 kfree(sc->sec_wiphy);
1351 ieee80211_free_hw(sc->hw);
1352
1353 ath9k_uninit_hw(sc);
1354}
1355
e3bb249b
BC		 1356static int ath9k_reg_notifier(struct wiphy *wiphy,
1357 struct regulatory_request *request)
1358{
1359 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1360 struct ath_wiphy *aphy = hw->priv;
1361 struct ath_softc *sc = aphy->sc;
27c51f1a 1362 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
e3bb249b
BC		 1363
1364 return ath_reg_notifier_apply(wiphy, request, reg);
1365}
1366
75d7839f
LR		 1367/*
1368 * Detects if there is any priority bt traffic
1369 */
1370static void ath_detect_bt_priority(struct ath_softc *sc)
1371{
1372 struct ath_btcoex *btcoex = &sc->btcoex;
1373 struct ath_hw *ah = sc->sc_ah;
1374
766ec4a9 1375 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
75d7839f
LR		 1376 btcoex->bt_priority_cnt++;
1377
1378 if (time_after(jiffies, btcoex->bt_priority_time +
1379 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1380 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
c46917bb
LR		 1381 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1382 "BT priority traffic detected");
75d7839f
LR		 1383 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1384 } else {
1385 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1386 }
1387
1388 btcoex->bt_priority_cnt = 0;
1389 btcoex->bt_priority_time = jiffies;
1390 }
1391}
1392
75d7839f
LR		 1393/*
1394 * Configures appropriate weight based on stomp type.
1395 */
269ad812
LR		 1396static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1397 enum ath_stomp_type stomp_type)
75d7839f 1398{
269ad812 1399 struct ath_hw *ah = sc->sc_ah;
75d7839f
LR		 1400
1401 switch (stomp_type) {
1402 case ATH_BTCOEX_STOMP_ALL:
269ad812
LR		 1403 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1404 AR_STOMP_ALL_WLAN_WGHT);
75d7839f
LR		 1405 break;
1406 case ATH_BTCOEX_STOMP_LOW:
269ad812
LR		 1407 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1408 AR_STOMP_LOW_WLAN_WGHT);
75d7839f
LR		 1409 break;
1410 case ATH_BTCOEX_STOMP_NONE:
269ad812
LR		 1411 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1412 AR_STOMP_NONE_WLAN_WGHT);
75d7839f
LR		 1413 break;
1414 default:
c46917bb
LR		 1415 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1416 "Invalid Stomptype\n");
75d7839f
LR		 1417 break;
1418 }
1419
269ad812 1420 ath9k_hw_btcoex_enable(ah);
75d7839f
LR		 1421}
1422
cd9bf689
LR		 1423static void ath9k_gen_timer_start(struct ath_hw *ah,
1424 struct ath_gen_timer *timer,
1425 u32 timer_next,
1426 u32 timer_period)
1427{
bc974f4a
LR		 1428 struct ath_common *common = ath9k_hw_common(ah);
1429 struct ath_softc *sc = (struct ath_softc *) common->priv;
1430
cd9bf689
LR		 1431 ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1432
bc974f4a 1433 if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
cd9bf689 1434 ath9k_hw_set_interrupts(ah, 0);
bc974f4a
LR		 1435 sc->imask |= ATH9K_INT_GENTIMER;
1436 ath9k_hw_set_interrupts(ah, sc->imask);
cd9bf689
LR		 1437 }
1438}
1439
1440static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1441{
bc974f4a
LR		 1442 struct ath_common *common = ath9k_hw_common(ah);
1443 struct ath_softc *sc = (struct ath_softc *) common->priv;
cd9bf689
LR		 1444 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1445
1446 ath9k_hw_gen_timer_stop(ah, timer);
1447
1448 /* if no timer is enabled, turn off interrupt mask */
1449 if (timer_table->timer_mask.val == 0) {
1450 ath9k_hw_set_interrupts(ah, 0);
bc974f4a
LR		 1451 sc->imask &= ~ATH9K_INT_GENTIMER;
1452 ath9k_hw_set_interrupts(ah, sc->imask);
cd9bf689
LR		 1453 }
1454}
1455
75d7839f
LR		 1456/*
1457 * This is the master bt coex timer which runs for every
1458 * 45ms, bt traffic will be given priority during 55% of this
1459 * period while wlan gets remaining 45%
1460 */
1461static void ath_btcoex_period_timer(unsigned long data)
1462{
1463 struct ath_softc *sc = (struct ath_softc *) data;
1464 struct ath_hw *ah = sc->sc_ah;
1465 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f
LR		 1466
1467 ath_detect_bt_priority(sc);
1468
1469 spin_lock_bh(&btcoex->btcoex_lock);
1470
269ad812 1471 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
75d7839f
LR		 1472
1473 spin_unlock_bh(&btcoex->btcoex_lock);
1474
1475 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1476 if (btcoex->hw_timer_enabled)
cd9bf689 1477 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
75d7839f 1478
cd9bf689
LR		 1479 ath9k_gen_timer_start(ah,
1480 btcoex->no_stomp_timer,
1481 (ath9k_hw_gettsf32(ah) +
1482 btcoex->btcoex_no_stomp),
1483 btcoex->btcoex_no_stomp * 10);
75d7839f
LR		 1484 btcoex->hw_timer_enabled = true;
1485 }
1486
1487 mod_timer(&btcoex->period_timer, jiffies +
1488 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1489}
1490
1491/*
1492 * Generic tsf based hw timer which configures weight
1493 * registers to time slice between wlan and bt traffic
1494 */
1495static void ath_btcoex_no_stomp_timer(void *arg)
1496{
1497 struct ath_softc *sc = (struct ath_softc *)arg;
1498 struct ath_hw *ah = sc->sc_ah;
1499 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f 1500
c46917bb
LR		 1501 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1502 "no stomp timer running \n");
75d7839f
LR		 1503
1504 spin_lock_bh(&btcoex->btcoex_lock);
1505
e08a6ace 1506 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
269ad812 1507 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
e08a6ace 1508 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
269ad812 1509 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
75d7839f
LR		 1510
1511 spin_unlock_bh(&btcoex->btcoex_lock);
1512}
1513
1514static int ath_init_btcoex_timer(struct ath_softc *sc)
1515{
1516 struct ath_btcoex *btcoex = &sc->btcoex;
1517
1518 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1519 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1520 btcoex->btcoex_period / 100;
1521
1522 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1523 (unsigned long) sc);
1524
1525 spin_lock_init(&btcoex->btcoex_lock);
1526
1527 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1528 ath_btcoex_no_stomp_timer,
1529 ath_btcoex_no_stomp_timer,
1530 (void *) sc, AR_FIRST_NDP_TIMER);
1531
1532 if (!btcoex->no_stomp_timer)
1533 return -ENOMEM;
1534
1535 return 0;
1536}
1537
9e4bffd2
LR		 1538/*
1539 * Read and write, they both share the same lock. We do this to serialize
1540 * reads and writes on Atheros 802.11n PCI devices only. This is required
1541 * as the FIFO on these devices can only accept sanely 2 requests. After
1542 * that the device goes bananas. Serializing the reads/writes prevents this
1543 * from happening.
1544 */
1545
1546static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1547{
1548 struct ath_hw *ah = (struct ath_hw *) hw_priv;
bc974f4a
LR		 1549 struct ath_common *common = ath9k_hw_common(ah);
1550 struct ath_softc *sc = (struct ath_softc *) common->priv;
9e4bffd2
LR		 1551
1552 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1553 unsigned long flags;
bc974f4a
LR		 1554 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1555 iowrite32(val, sc->mem + reg_offset);
1556 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
9e4bffd2 1557 } else
bc974f4a 1558 iowrite32(val, sc->mem + reg_offset);
9e4bffd2
LR		 1559}
1560
1561static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1562{
1563 struct ath_hw *ah = (struct ath_hw *) hw_priv;
bc974f4a
LR		 1564 struct ath_common *common = ath9k_hw_common(ah);
1565 struct ath_softc *sc = (struct ath_softc *) common->priv;
9e4bffd2
LR		 1566 u32 val;
1567
1568 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1569 unsigned long flags;
bc974f4a
LR		 1570 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1571 val = ioread32(sc->mem + reg_offset);
1572 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
9e4bffd2 1573 } else
bc974f4a 1574 val = ioread32(sc->mem + reg_offset);
9e4bffd2
LR		 1575 return val;
1576}
1577
2ddb5c8b 1578static const struct ath_ops ath9k_common_ops = {
9e4bffd2
LR		 1579 .read = ath9k_ioread32,
1580 .write = ath9k_iowrite32,
1581};
1582
1e40bcfa
LR		 1583/*
1584 * Initialize and fill ath_softc, ath_sofct is the
1585 * "Software Carrier" struct. Historically it has existed
1586 * to allow the separation between hardware specific
1587 * variables (now in ath_hw) and driver specific variables.
1588 */
5bb12791
LR		 1589static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1590 const struct ath_bus_ops *bus_ops)
ff37e337 1591{
cbe61d8a 1592 struct ath_hw *ah = NULL;
1510718d 1593 struct ath_common *common;
4f3acf81 1594 int r = 0, i;
ff37e337 1595 int csz = 0;
75d7839f 1596 int qnum;
ff37e337
S		 1597
1598 /* XXX: hardware will not be ready until ath_open() being called */
1599 sc->sc_flags |= SC_OP_INVALID;
88b126af 1600
c52f33d0 1601 spin_lock_init(&sc->wiphy_lock);
ff37e337 1602 spin_lock_init(&sc->sc_resetlock);
6158425b 1603 spin_lock_init(&sc->sc_serial_rw);
04717ccd 1604 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1605 mutex_init(&sc->mutex);
ff37e337 1606 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1607 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1608 (unsigned long)sc);
1609
4f3acf81 1610 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
211f5859
LR		 1611 if (!ah)
1612 return -ENOMEM;
4f3acf81 1613
8df5d1b7 1614 ah->hw_version.devid = devid;
aeac355d 1615 ah->hw_version.subsysid = subsysid;
e1e2f93f 1616 sc->sc_ah = ah;
4f3acf81 1617
27c51f1a 1618 common = ath9k_hw_common(ah);
9e4bffd2 1619 common->ops = &ath9k_common_ops;
5bb12791 1620 common->bus_ops = bus_ops;
13b81559 1621 common->ah = ah;
b002a4a9 1622 common->hw = sc->hw;
bc974f4a 1623 common->priv = sc;
faa27fae 1624 common->debug_mask = ath9k_debug;
27c51f1a
LR		 1625
1626 /*
1627 * Cache line size is used to size and align various
1628 * structures used to communicate with the hardware.
1629 */
5bb12791 1630 ath_read_cachesize(common, &csz);
27c51f1a
LR		 1631 /* XXX assert csz is non-zero */
1632 common->cachelsz = csz << 2; /* convert to bytes */
1633
f637cfd6 1634 r = ath9k_hw_init(ah);
4f3acf81 1635 if (r) {
c46917bb
LR		 1636 ath_print(common, ATH_DBG_FATAL,
1637 "Unable to initialize hardware; "
1638 "initialization status: %d\n", r);
211f5859
LR		 1639 goto bad_free_hw;
1640 }
1641
1642 if (ath9k_init_debug(ah) < 0) {
1643 ath_print(common, ATH_DBG_FATAL,
1644 "Unable to create debugfs files\n");
1645 goto bad_free_hw;
ff37e337 1646 }
ff37e337
S		 1647
1648 /* Get the hardware key cache size. */
7e86c104
LR		 1649 common->keymax = ah->caps.keycache_size;
1650 if (common->keymax > ATH_KEYMAX) {
c46917bb
LR		 1651 ath_print(common, ATH_DBG_ANY,
1652 "Warning, using only %u entries in %u key cache\n",
7e86c104
LR		 1653 ATH_KEYMAX, common->keymax);
1654 common->keymax = ATH_KEYMAX;
ff37e337
S		 1655 }
1656
1657 /*
1658 * Reset the key cache since some parts do not
1659 * reset the contents on initial power up.
1660 */
7e86c104 1661 for (i = 0; i < common->keymax; i++)
ff37e337 1662 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1663
ff37e337 1664 /* default to MONITOR mode */
2660b81a 1665 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1666
ff37e337
S		 1667 /*
1668 * Allocate hardware transmit queues: one queue for
1669 * beacon frames and one data queue for each QoS
1670 * priority. Note that the hal handles reseting
1671 * these queues at the needed time.
1672 */
536b3a7a 1673 sc->beacon.beaconq = ath9k_hw_beaconq_setup(ah);
b77f483f 1674 if (sc->beacon.beaconq == -1) {
c46917bb
LR		 1675 ath_print(common, ATH_DBG_FATAL,
1676 "Unable to setup a beacon xmit queue\n");
4f3acf81 1677 r = -EIO;
ff37e337
S		 1678 goto bad2;
1679 }
b77f483f
S		 1680 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1681 if (sc->beacon.cabq == NULL) {
c46917bb
LR		 1682 ath_print(common, ATH_DBG_FATAL,
1683 "Unable to setup CAB xmit queue\n");
4f3acf81 1684 r = -EIO;
ff37e337
S		 1685 goto bad2;
1686 }
1687
17d7904d 1688 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1689 ath_cabq_update(sc);
1690
b77f483f
S		 1691 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1692 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1693
1694 /* Setup data queues */
1695 /* NB: ensure BK queue is the lowest priority h/w queue */
1696 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
c46917bb
LR		 1697 ath_print(common, ATH_DBG_FATAL,
1698 "Unable to setup xmit queue for BK traffic\n");
4f3acf81 1699 r = -EIO;
ff37e337
S		 1700 goto bad2;
1701 }
1702
1703 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
c46917bb
LR		 1704 ath_print(common, ATH_DBG_FATAL,
1705 "Unable to setup xmit queue for BE traffic\n");
4f3acf81 1706 r = -EIO;
ff37e337
S		 1707 goto bad2;
1708 }
1709 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
c46917bb
LR		 1710 ath_print(common, ATH_DBG_FATAL,
1711 "Unable to setup xmit queue for VI traffic\n");
4f3acf81 1712 r = -EIO;
ff37e337
S		 1713 goto bad2;
1714 }
1715 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
c46917bb
LR		 1716 ath_print(common, ATH_DBG_FATAL,
1717 "Unable to setup xmit queue for VO traffic\n");
4f3acf81 1718 r = -EIO;
ff37e337
S		 1719 goto bad2;
1720 }
1721
1722 /* Initializes the noise floor to a reasonable default value.
1723 * Later on this will be updated during ANI processing. */
1724
3d536acf
LR		 1725 common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1726 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1727
1728 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1729 ATH9K_CIPHER_TKIP, NULL)) {
1730 /*
1731 * Whether we should enable h/w TKIP MIC.
1732 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1733 * report WMM capable, so it's always safe to turn on
1734 * TKIP MIC in this case.
1735 */
1736 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1737 0, 1, NULL);
1738 }
1739
1740 /*
1741 * Check whether the separate key cache entries
1742 * are required to handle both tx+rx MIC keys.
1743 * With split mic keys the number of stations is limited
1744 * to 27 otherwise 59.
1745 */
1746 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1747 ATH9K_CIPHER_TKIP, NULL)
1748 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1749 ATH9K_CIPHER_MIC, NULL)
1750 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1751 0, NULL))
7e86c104 1752 common->splitmic = 1;
ff37e337
S		 1753
1754 /* turn on mcast key search if possible */
1755 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1756 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1757 1, NULL);
1758
17d7904d 1759 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1760
1761 /* 11n Capabilities */
2660b81a 1762 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1763 sc->sc_flags |= SC_OP_TXAGGR;
1764 sc->sc_flags |= SC_OP_RXAGGR;
1765 }
1766
43c27613
LR		 1767 common->tx_chainmask = ah->caps.tx_chainmask;
1768 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1769
1770 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1771 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1772
8ca21f01 1773 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1510718d 1774 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1775
b77f483f 1776 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1777
1778 /* initialize beacon slots */
c52f33d0 1779 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1780 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1781 sc->beacon.bslot_aphy[i] = NULL;
1782 }
ff37e337 1783
ff37e337
S		 1784 /* setup channels and rates */
1785
a9a29ce6
GJ		 1786 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
1787 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1788 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1789 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1790 ARRAY_SIZE(ath9k_2ghz_chantable);
1791 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
1792 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
1793 ARRAY_SIZE(ath9k_legacy_rates);
1794 }
ff37e337 1795
2660b81a 1796 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1797 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337 1798 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1799 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1800 ARRAY_SIZE(ath9k_5ghz_chantable);
545750d3
FF		 1801 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1802 ath9k_legacy_rates + 4;
1803 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
1804 ARRAY_SIZE(ath9k_legacy_rates) - 4;
ff37e337
S		 1805 }
1806
766ec4a9 1807 switch (ah->btcoex_hw.scheme) {
75d7839f
LR		 1808 case ATH_BTCOEX_CFG_NONE:
1809 break;
1810 case ATH_BTCOEX_CFG_2WIRE:
1811 ath9k_hw_btcoex_init_2wire(ah);
1812 break;
1813 case ATH_BTCOEX_CFG_3WIRE:
1814 ath9k_hw_btcoex_init_3wire(ah);
1815 r = ath_init_btcoex_timer(sc);
1773912b
VT		 1816 if (r)
1817 goto bad2;
75d7839f 1818 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
766ec4a9 1819 ath9k_hw_init_btcoex_hw(ah, qnum);
e08a6ace 1820 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
75d7839f
LR		 1821 break;
1822 default:
1823 WARN_ON(1);
1824 break;
1773912b 1825 }
c97c92d9 1826
ff37e337
S		 1827 return 0;
1828bad2:
1829 /* cleanup tx queues */
1830 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1831 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1832 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
211f5859 1833
211f5859 1834bad_free_hw:
7fda1666 1835 ath9k_uninit_hw(sc);
4f3acf81 1836 return r;
ff37e337
S		 1837}
1838
c52f33d0 1839void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1840{
9c84b797
S		 1841 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1842 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1843 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1844 IEEE80211_HW_AMPDU_AGGREGATION |
1845 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1846 IEEE80211_HW_PS_NULLFUNC_STACK |
1847 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1848
b3bd89ce 1849 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1850 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1851
9c84b797
S		 1852 hw->wiphy->interface_modes =
1853 BIT(NL80211_IFTYPE_AP) |
1854 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1855 BIT(NL80211_IFTYPE_ADHOC) |
1856 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1857
18b6c9a2
JL		 1858 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1859
8feceb67 1860 hw->queues = 4;
e63835b0 1861 hw->max_rates = 4;
171387ef 1862 hw->channel_change_time = 5000;
465ca84d 1863 hw->max_listen_interval = 10;
dd190183
LR		 1864 /* Hardware supports 10 but we use 4 */
1865 hw->max_rate_tries = 4;
528f0c6b 1866 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1867 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1868
8feceb67 1869 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1870
a9a29ce6
GJ		 1871 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
1872 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1873 &sc->sbands[IEEE80211_BAND_2GHZ];
c52f33d0
JM		 1874 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1875 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1876 &sc->sbands[IEEE80211_BAND_5GHZ];
1877}
1878
1e40bcfa 1879/* Device driver core initialization */
5bb12791
LR		 1880int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1881 const struct ath_bus_ops *bus_ops)
c52f33d0
JM		 1882{
1883 struct ieee80211_hw *hw = sc->hw;
1510718d 1884 struct ath_common *common;
4d6b228d 1885 struct ath_hw *ah;
c52f33d0 1886 int error = 0, i;
3a702e49 1887 struct ath_regulatory *reg;
c52f33d0 1888
4d6b228d 1889 dev_dbg(sc->dev, "Attach ATH hw\n");
c52f33d0 1890
5bb12791 1891 error = ath_init_softc(devid, sc, subsysid, bus_ops);
c52f33d0
JM		 1892 if (error != 0)
1893 return error;
1894
4d6b228d 1895 ah = sc->sc_ah;
1510718d 1896 common = ath9k_hw_common(ah);
4d6b228d 1897
c52f33d0
JM		 1898 /* get mac address from hardware and set in mac80211 */
1899
1510718d 1900 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
c52f33d0
JM		 1901
1902 ath_set_hw_capab(sc, hw);
1903
1510718d 1904 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
c26c2e57
LR		 1905 ath9k_reg_notifier);
1906 if (error)
1907 return error;
1908
1510718d 1909 reg = &common->regulatory;
c26c2e57 1910
4d6b228d 1911 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
a9a29ce6
GJ		 1912 if (test_bit(ATH9K_MODE_11G, ah->caps.wireless_modes))
1913 setup_ht_cap(sc,
1914 &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
4d6b228d 1915 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
a9a29ce6
GJ		 1916 setup_ht_cap(sc,
1917 &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1918 }
1919
db93e7b5
SB		 1920 /* initialize tx/rx engine */
1921 error = ath_tx_init(sc, ATH_TXBUF);
1922 if (error != 0)
40b130a9 1923 goto error_attach;
8feceb67 1924
db93e7b5
SB		 1925 error = ath_rx_init(sc, ATH_RXBUF);
1926 if (error != 0)
40b130a9 1927 goto error_attach;
8feceb67 1928
0e2dedf9 1929 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1930 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1931 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1932
db93e7b5 1933 error = ieee80211_register_hw(hw);
8feceb67 1934
3a702e49 1935 if (!ath_is_world_regd(reg)) {
c02cf373 1936 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1937 if (error)
1938 goto error_attach;
1939 }
5f8e077c 1940
db93e7b5
SB		 1941 /* Initialize LED control */
1942 ath_init_leds(sc);
8feceb67 1943
3b319aae 1944 ath_start_rfkill_poll(sc);
5f8e077c 1945
8feceb67 1946 return 0;
40b130a9
VT		 1947
1948error_attach:
1949 /* cleanup tx queues */
1950 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1951 if (ATH_TXQ_SETUP(sc, i))
1952 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1953
7fda1666 1954 ath9k_uninit_hw(sc);
40b130a9 1955
8feceb67 1956 return error;
f078f209
LR		 1957}
1958
ff37e337
S		 1959int ath_reset(struct ath_softc *sc, bool retry_tx)
1960{
cbe61d8a 1961 struct ath_hw *ah = sc->sc_ah;
c46917bb 1962 struct ath_common *common = ath9k_hw_common(ah);
030bb495 1963 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1964 int r;
ff37e337 1965
2ab81d4a
S		 1966 /* Stop ANI */
1967 del_timer_sync(&common->ani.timer);
1968
ff37e337 1969 ath9k_hw_set_interrupts(ah, 0);
043a0405 1970 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1971 ath_stoprecv(sc);
1972 ath_flushrecv(sc);
1973
1974 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1975 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1976 if (r)
c46917bb
LR		 1977 ath_print(common, ATH_DBG_FATAL,
1978 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1979 spin_unlock_bh(&sc->sc_resetlock);
1980
1981 if (ath_startrecv(sc) != 0)
c46917bb
LR		 1982 ath_print(common, ATH_DBG_FATAL,
1983 "Unable to start recv logic\n");
ff37e337
S		 1984
1985 /*
1986 * We may be doing a reset in response to a request
1987 * that changes the channel so update any state that
1988 * might change as a result.
1989 */
ce111bad 1990 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1991
1992 ath_update_txpow(sc);
1993
1994 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1995 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1996
17d7904d 1997 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1998
1999 if (retry_tx) {
2000 int i;
2001 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2002 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 2003 spin_lock_bh(&sc->tx.txq[i].axq_lock);
2004 ath_txq_schedule(sc, &sc->tx.txq[i]);
2005 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 2006 }
2007 }
2008 }
2009
2ab81d4a
S		 2010 /* Start ANI */
2011 ath_start_ani(common);
2012
ae8d2858 2013 return r;
ff37e337
S		 2014}
2015
2016/*
2017 * This function will allocate both the DMA descriptor structure, and the
2018 * buffers it contains. These are used to contain the descriptors used
2019 * by the system.
2020*/
2021int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2022 struct list_head *head, const char *name,
2023 int nbuf, int ndesc)
2024{
2025#define DS2PHYS(_dd, _ds) \
2026 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2027#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2028#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
c46917bb 2029 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
ff37e337
S		 2030 struct ath_desc *ds;
2031 struct ath_buf *bf;
2032 int i, bsize, error;
2033
c46917bb
LR		 2034 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2035 name, nbuf, ndesc);
ff37e337 2036
b03a9db9 2037 INIT_LIST_HEAD(head);
ff37e337
S		 2038 /* ath_desc must be a multiple of DWORDs */
2039 if ((sizeof(struct ath_desc) % 4) != 0) {
c46917bb
LR		 2040 ath_print(common, ATH_DBG_FATAL,
2041 "ath_desc not DWORD aligned\n");
9680e8a3 2042 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
ff37e337
S		 2043 error = -ENOMEM;
2044 goto fail;
2045 }
2046
ff37e337
S		 2047 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2048
2049 /*
2050 * Need additional DMA memory because we can't use
2051 * descriptors that cross the 4K page boundary. Assume
2052 * one skipped descriptor per 4K page.
2053 */
2660b81a 2054 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 2055 u32 ndesc_skipped =
2056 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2057 u32 dma_len;
2058
2059 while (ndesc_skipped) {
2060 dma_len = ndesc_skipped * sizeof(struct ath_desc);
2061 dd->dd_desc_len += dma_len;
2062
2063 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2064 };
2065 }
2066
2067 /* allocate descriptors */
7da3c55c 2068 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 2069 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 2070 if (dd->dd_desc == NULL) {
2071 error = -ENOMEM;
2072 goto fail;
2073 }
2074 ds = dd->dd_desc;
c46917bb
LR		 2075 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2076 name, ds, (u32) dd->dd_desc_len,
2077 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
ff37e337
S		 2078
2079 /* allocate buffers */
2080 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 2081 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 2082 if (bf == NULL) {
2083 error = -ENOMEM;
2084 goto fail2;
2085 }
ff37e337
S		 2086 dd->dd_bufptr = bf;
2087
ff37e337
S		 2088 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2089 bf->bf_desc = ds;
2090 bf->bf_daddr = DS2PHYS(dd, ds);
2091
2660b81a 2092 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 2093 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2094 /*
2095 * Skip descriptor addresses which can cause 4KB
2096 * boundary crossing (addr + length) with a 32 dword
2097 * descriptor fetch.
2098 */
2099 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
9680e8a3 2100 BUG_ON((caddr_t) bf->bf_desc >=
ff37e337
S		 2101 ((caddr_t) dd->dd_desc +
2102 dd->dd_desc_len));
2103
2104 ds += ndesc;
2105 bf->bf_desc = ds;
2106 bf->bf_daddr = DS2PHYS(dd, ds);
2107 }
2108 }
2109 list_add_tail(&bf->list, head);
2110 }
2111 return 0;
2112fail2:
7da3c55c
GJ		 2113 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2114 dd->dd_desc_paddr);
ff37e337
S		 2115fail:
2116 memset(dd, 0, sizeof(*dd));
2117 return error;
2118#undef ATH_DESC_4KB_BOUND_CHECK
2119#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2120#undef DS2PHYS
2121}
2122
2123void ath_descdma_cleanup(struct ath_softc *sc,
2124 struct ath_descdma *dd,
2125 struct list_head *head)
2126{
7da3c55c
GJ		 2127 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2128 dd->dd_desc_paddr);
ff37e337
S		 2129
2130 INIT_LIST_HEAD(head);
2131 kfree(dd->dd_bufptr);
2132 memset(dd, 0, sizeof(*dd));
2133}
2134
2135int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2136{
2137 int qnum;
2138
2139 switch (queue) {
2140 case 0:
b77f483f 2141 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 2142 break;
2143 case 1:
b77f483f 2144 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 2145 break;
2146 case 2:
b77f483f 2147 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2148 break;
2149 case 3:
b77f483f 2150 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 2151 break;
2152 default:
b77f483f 2153 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2154 break;
2155 }
2156
2157 return qnum;
2158}
2159
2160int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2161{
2162 int qnum;
2163
2164 switch (queue) {
2165 case ATH9K_WME_AC_VO:
2166 qnum = 0;
2167 break;
2168 case ATH9K_WME_AC_VI:
2169 qnum = 1;
2170 break;
2171 case ATH9K_WME_AC_BE:
2172 qnum = 2;
2173 break;
2174 case ATH9K_WME_AC_BK:
2175 qnum = 3;
2176 break;
2177 default:
2178 qnum = -1;
2179 break;
2180 }
2181
2182 return qnum;
2183}
2184
5f8e077c
LR		 2185/* XXX: Remove me once we don't depend on ath9k_channel for all
2186 * this redundant data */
0e2dedf9
JM		 2187void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2188 struct ath9k_channel *ichan)
5f8e077c 2189{
5f8e077c
LR		 2190 struct ieee80211_channel *chan = hw->conf.channel;
2191 struct ieee80211_conf *conf = &hw->conf;
2192
2193 ichan->channel = chan->center_freq;
2194 ichan->chan = chan;
2195
2196 if (chan->band == IEEE80211_BAND_2GHZ) {
2197 ichan->chanmode = CHANNEL_G;
8813262e 2198 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR		 2199 } else {
2200 ichan->chanmode = CHANNEL_A;
2201 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2202 }
2203
25c56eec 2204 if (conf_is_ht(conf))
5f8e077c
LR		 2205 ichan->chanmode = ath_get_extchanmode(sc, chan,
2206 conf->channel_type);
5f8e077c
LR		 2207}
2208
ff37e337
S		 2209/**********************/
2210/* mac80211 callbacks */
2211/**********************/
2212
75d7839f
LR		 2213/*
2214 * (Re)start btcoex timers
2215 */
2216static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2217{
2218 struct ath_btcoex *btcoex = &sc->btcoex;
2219 struct ath_hw *ah = sc->sc_ah;
2220
c46917bb
LR		 2221 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2222 "Starting btcoex timers");
75d7839f
LR		 2223
2224 /* make sure duty cycle timer is also stopped when resuming */
2225 if (btcoex->hw_timer_enabled)
cd9bf689 2226 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
75d7839f
LR		 2227
2228 btcoex->bt_priority_cnt = 0;
2229 btcoex->bt_priority_time = jiffies;
2230 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2231
2232 mod_timer(&btcoex->period_timer, jiffies);
2233}
2234
8feceb67 2235static int ath9k_start(struct ieee80211_hw *hw)
f078f209 2236{
bce048d7
JM		 2237 struct ath_wiphy *aphy = hw->priv;
2238 struct ath_softc *sc = aphy->sc;
af03abec 2239 struct ath_hw *ah = sc->sc_ah;
c46917bb 2240 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 2241 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 2242 struct ath9k_channel *init_channel;
82880a7c 2243 int r;
f078f209 2244
c46917bb
LR		 2245 ath_print(common, ATH_DBG_CONFIG,
2246 "Starting driver with initial channel: %d MHz\n",
2247 curchan->center_freq);
f078f209 2248
141b38b6
S		 2249 mutex_lock(&sc->mutex);
2250
9580a222
JM		 2251 if (ath9k_wiphy_started(sc)) {
2252 if (sc->chan_idx == curchan->hw_value) {
2253 /*
2254 * Already on the operational channel, the new wiphy
2255 * can be marked active.
2256 */
2257 aphy->state = ATH_WIPHY_ACTIVE;
2258 ieee80211_wake_queues(hw);
2259 } else {
2260 /*
2261 * Another wiphy is on another channel, start the new
2262 * wiphy in paused state.
2263 */
2264 aphy->state = ATH_WIPHY_PAUSED;
2265 ieee80211_stop_queues(hw);
2266 }
2267 mutex_unlock(&sc->mutex);
2268 return 0;
2269 }
2270 aphy->state = ATH_WIPHY_ACTIVE;
2271
8feceb67 2272 /* setup initial channel */
f078f209 2273
82880a7c 2274 sc->chan_idx = curchan->hw_value;
f078f209 2275
82880a7c 2276 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 2277
2278 /* Reset SERDES registers */
af03abec 2279 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S		 2280
2281 /*
2282 * The basic interface to setting the hardware in a good
2283 * state is ``reset''. On return the hardware is known to
2284 * be powered up and with interrupts disabled. This must
2285 * be followed by initialization of the appropriate bits
2286 * and then setup of the interrupt mask.
2287 */
2288 spin_lock_bh(&sc->sc_resetlock);
af03abec 2289 r = ath9k_hw_reset(ah, init_channel, false);
ae8d2858 2290 if (r) {
c46917bb
LR		 2291 ath_print(common, ATH_DBG_FATAL,
2292 "Unable to reset hardware; reset status %d "
2293 "(freq %u MHz)\n", r,
2294 curchan->center_freq);
ff37e337 2295 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2296 goto mutex_unlock;
ff37e337
S		 2297 }
2298 spin_unlock_bh(&sc->sc_resetlock);
2299
2300 /*
2301 * This is needed only to setup initial state
2302 * but it's best done after a reset.
2303 */
2304 ath_update_txpow(sc);
8feceb67 2305
ff37e337
S		 2306 /*
2307 * Setup the hardware after reset:
2308 * The receive engine is set going.
2309 * Frame transmit is handled entirely
2310 * in the frame output path; there's nothing to do
2311 * here except setup the interrupt mask.
2312 */
2313 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 2314 ath_print(common, ATH_DBG_FATAL,
2315 "Unable to start recv logic\n");
141b38b6
S		 2316 r = -EIO;
2317 goto mutex_unlock;
f078f209 2318 }
8feceb67 2319
ff37e337 2320 /* Setup our intr mask. */
17d7904d 2321 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2322 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2323 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2324
af03abec 2325 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2326 sc->imask |= ATH9K_INT_GTT;
ff37e337 2327
af03abec 2328 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2329 sc->imask |= ATH9K_INT_CST;
ff37e337 2330
ce111bad 2331 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2332
2333 sc->sc_flags &= ~SC_OP_INVALID;
2334
2335 /* Disable BMISS interrupt when we're not associated */
17d7904d 2336 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
af03abec 2337 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337 2338
bce048d7 2339 ieee80211_wake_queues(hw);
ff37e337 2340
42935eca 2341 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 2342
766ec4a9
LR		 2343 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2344 !ah->btcoex_hw.enabled) {
5e197292
LR		 2345 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2346 AR_STOMP_LOW_WLAN_WGHT);
af03abec 2347 ath9k_hw_btcoex_enable(ah);
f985ad12 2348
5bb12791
LR		 2349 if (common->bus_ops->bt_coex_prep)
2350 common->bus_ops->bt_coex_prep(common);
766ec4a9 2351 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2352 ath9k_btcoex_timer_resume(sc);
1773912b
VT		 2353 }
2354
141b38b6
S		 2355mutex_unlock:
2356 mutex_unlock(&sc->mutex);
2357
ae8d2858 2358 return r;
f078f209
LR		 2359}
2360
8feceb67
VT		 2361static int ath9k_tx(struct ieee80211_hw *hw,
2362 struct sk_buff *skb)
f078f209 2363{
528f0c6b 2364 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2365 struct ath_wiphy *aphy = hw->priv;
2366 struct ath_softc *sc = aphy->sc;
c46917bb 2367 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 2368 struct ath_tx_control txctl;
1bc14880
BP		 2369 int padpos, padsize;
2370 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 2371
8089cc47 2372 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
c46917bb
LR		 2373 ath_print(common, ATH_DBG_XMIT,
2374 "ath9k: %s: TX in unexpected wiphy state "
2375 "%d\n", wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM		 2376 goto exit;
2377 }
2378
96148326 2379 if (sc->ps_enabled) {
dc8c4585
JM		 2380 /*
2381 * mac80211 does not set PM field for normal data frames, so we
2382 * need to update that based on the current PS mode.
2383 */
2384 if (ieee80211_is_data(hdr->frame_control) &&
2385 !ieee80211_is_nullfunc(hdr->frame_control) &&
2386 !ieee80211_has_pm(hdr->frame_control)) {
c46917bb
LR		 2387 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2388 "while in PS mode\n");
dc8c4585
JM		 2389 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2390 }
2391 }
2392
9a23f9ca
JM		 2393 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2394 /*
2395 * We are using PS-Poll and mac80211 can request TX while in
2396 * power save mode. Need to wake up hardware for the TX to be
2397 * completed and if needed, also for RX of buffered frames.
2398 */
9a23f9ca
JM		 2399 ath9k_ps_wakeup(sc);
2400 ath9k_hw_setrxabort(sc->sc_ah, 0);
2401 if (ieee80211_is_pspoll(hdr->frame_control)) {
c46917bb
LR		 2402 ath_print(common, ATH_DBG_PS,
2403 "Sending PS-Poll to pick a buffered frame\n");
9a23f9ca
JM		 2404 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2405 } else {
c46917bb
LR		 2406 ath_print(common, ATH_DBG_PS,
2407 "Wake up to complete TX\n");
9a23f9ca
JM		 2408 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2409 }
2410 /*
2411 * The actual restore operation will happen only after
2412 * the sc_flags bit is cleared. We are just dropping
2413 * the ps_usecount here.
2414 */
2415 ath9k_ps_restore(sc);
2416 }
2417
528f0c6b 2418 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2419
8feceb67
VT		 2420 /*
2421 * As a temporary workaround, assign seq# here; this will likely need
2422 * to be cleaned up to work better with Beacon transmission and virtual
2423 * BSSes.
2424 */
2425 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
8feceb67 2426 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2427 sc->tx.seq_no += 0x10;
8feceb67 2428 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2429 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2430 }
f078f209 2431
8feceb67 2432 /* Add the padding after the header if this is not already done */
1bc14880
BP		 2433 padpos = ath9k_cmn_padpos(hdr->frame_control);
2434 padsize = padpos & 3;
2435 if (padsize && skb->len>padpos) {
8feceb67
VT		 2436 if (skb_headroom(skb) < padsize)
2437 return -1;
2438 skb_push(skb, padsize);
1bc14880 2439 memmove(skb->data, skb->data + padsize, padpos);
8feceb67
VT		 2440 }
2441
528f0c6b
S		 2442 /* Check if a tx queue is available */
2443
2444 txctl.txq = ath_test_get_txq(sc, skb);
2445 if (!txctl.txq)
2446 goto exit;
2447
c46917bb 2448 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2449
c52f33d0 2450 if (ath_tx_start(hw, skb, &txctl) != 0) {
c46917bb 2451 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2452 goto exit;
8feceb67
VT		 2453 }
2454
528f0c6b
S		 2455 return 0;
2456exit:
2457 dev_kfree_skb_any(skb);
8feceb67 2458 return 0;
f078f209
LR		 2459}
2460
75d7839f
LR		 2461/*
2462 * Pause btcoex timer and bt duty cycle timer
2463 */
2464static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2465{
2466 struct ath_btcoex *btcoex = &sc->btcoex;
2467 struct ath_hw *ah = sc->sc_ah;
2468
2469 del_timer_sync(&btcoex->period_timer);
2470
2471 if (btcoex->hw_timer_enabled)
cd9bf689 2472 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
75d7839f
LR		 2473
2474 btcoex->hw_timer_enabled = false;
2475}
2476
8feceb67 2477static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2478{
bce048d7
JM		 2479 struct ath_wiphy *aphy = hw->priv;
2480 struct ath_softc *sc = aphy->sc;
af03abec 2481 struct ath_hw *ah = sc->sc_ah;
c46917bb 2482 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2483
4c483817
S		 2484 mutex_lock(&sc->mutex);
2485
9580a222
JM		 2486 aphy->state = ATH_WIPHY_INACTIVE;
2487
c94dbff7
LR		 2488 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2489 cancel_delayed_work_sync(&sc->tx_complete_work);
2490
2491 if (!sc->num_sec_wiphy) {
2492 cancel_delayed_work_sync(&sc->wiphy_work);
2493 cancel_work_sync(&sc->chan_work);
2494 }
2495
9c84b797 2496 if (sc->sc_flags & SC_OP_INVALID) {
c46917bb 2497 ath_print(common, ATH_DBG_ANY, "Device not present\n");
4c483817 2498 mutex_unlock(&sc->mutex);
9c84b797
S		 2499 return;
2500 }
8feceb67 2501
9580a222
JM		 2502 if (ath9k_wiphy_started(sc)) {
2503 mutex_unlock(&sc->mutex);
2504 return; /* another wiphy still in use */
2505 }
2506
766ec4a9 2507 if (ah->btcoex_hw.enabled) {
af03abec 2508 ath9k_hw_btcoex_disable(ah);
766ec4a9 2509 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2510 ath9k_btcoex_timer_pause(sc);
1773912b
VT		 2511 }
2512
ff37e337
S		 2513 /* make sure h/w will not generate any interrupt
2514 * before setting the invalid flag. */
af03abec 2515 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S		 2516
2517 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2518 ath_drain_all_txq(sc, false);
ff37e337 2519 ath_stoprecv(sc);
af03abec 2520 ath9k_hw_phy_disable(ah);
ff37e337 2521 } else
b77f483f 2522 sc->rx.rxlink = NULL;
ff37e337 2523
ff37e337 2524 /* disable HAL and put h/w to sleep */
af03abec
LR		 2525 ath9k_hw_disable(ah);
2526 ath9k_hw_configpcipowersave(ah, 1, 1);
9ecdef4b 2527 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ff37e337
S		 2528
2529 sc->sc_flags |= SC_OP_INVALID;
500c064d 2530
141b38b6
S		 2531 mutex_unlock(&sc->mutex);
2532
c46917bb 2533 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2534}
2535
8feceb67
VT		 2536static int ath9k_add_interface(struct ieee80211_hw *hw,
2537 struct ieee80211_if_init_conf *conf)
f078f209 2538{
bce048d7
JM		 2539 struct ath_wiphy *aphy = hw->priv;
2540 struct ath_softc *sc = aphy->sc;
c46917bb 2541 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
17d7904d 2542 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2543 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2544 int ret = 0;
8feceb67 2545
141b38b6
S		 2546 mutex_lock(&sc->mutex);
2547
8ca21f01
JM		 2548 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2549 sc->nvifs > 0) {
2550 ret = -ENOBUFS;
2551 goto out;
2552 }
2553
8feceb67 2554 switch (conf->type) {
05c914fe 2555 case NL80211_IFTYPE_STATION:
d97809db 2556 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2557 break;
05c914fe 2558 case NL80211_IFTYPE_ADHOC:
05c914fe 2559 case NL80211_IFTYPE_AP:
9cb5412b 2560 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2561 if (sc->nbcnvifs >= ATH_BCBUF) {
2562 ret = -ENOBUFS;
2563 goto out;
2564 }
9cb5412b 2565 ic_opmode = conf->type;
f078f209
LR		 2566 break;
2567 default:
c46917bb 2568 ath_print(common, ATH_DBG_FATAL,
04bd4638 2569 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2570 ret = -EOPNOTSUPP;
2571 goto out;
f078f209
LR		 2572 }
2573
c46917bb
LR		 2574 ath_print(common, ATH_DBG_CONFIG,
2575 "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2576
17d7904d 2577 /* Set the VIF opmode */
5640b08e
S		 2578 avp->av_opmode = ic_opmode;
2579 avp->av_bslot = -1;
2580
2c3db3d5 2581 sc->nvifs++;
8ca21f01
JM		 2582
2583 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2584 ath9k_set_bssid_mask(hw);
2585
2c3db3d5
JM		 2586 if (sc->nvifs > 1)
2587 goto out; /* skip global settings for secondary vif */
2588
b238e90e 2589 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2590 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2591 sc->sc_flags |= SC_OP_TSF_RESET;
2592 }
5640b08e 2593
5640b08e 2594 /* Set the device opmode */
2660b81a 2595 sc->sc_ah->opmode = ic_opmode;
5640b08e 2596
4e30ffa2
VN		 2597 /*
2598 * Enable MIB interrupts when there are hardware phy counters.
2599 * Note we only do this (at the moment) for station mode.
2600 */
4af9cf4f 2601 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2602 (conf->type == NL80211_IFTYPE_ADHOC) ||
2603 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 2604 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S		 2605 sc->imask |= ATH9K_INT_TSFOOR;
2606 }
2607
17d7904d 2608 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2609
f38faa31
SB		 2610 if (conf->type == NL80211_IFTYPE_AP ||
2611 conf->type == NL80211_IFTYPE_ADHOC ||
2612 conf->type == NL80211_IFTYPE_MONITOR)
3d536acf 2613 ath_start_ani(common);
6f255425 2614
2c3db3d5 2615out:
141b38b6 2616 mutex_unlock(&sc->mutex);
2c3db3d5 2617 return ret;
f078f209
LR		 2618}
2619
8feceb67
VT		 2620static void ath9k_remove_interface(struct ieee80211_hw *hw,
2621 struct ieee80211_if_init_conf *conf)
f078f209 2622{
bce048d7
JM		 2623 struct ath_wiphy *aphy = hw->priv;
2624 struct ath_softc *sc = aphy->sc;
c46917bb 2625 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
17d7904d 2626 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2627 int i;
f078f209 2628
c46917bb 2629 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2630
141b38b6
S		 2631 mutex_lock(&sc->mutex);
2632
6f255425 2633 /* Stop ANI */
3d536acf 2634 del_timer_sync(&common->ani.timer);
580f0b8a 2635
8feceb67 2636 /* Reclaim beacon resources */
9cb5412b
PE		 2637 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2638 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2639 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2640 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2641 ath_beacon_return(sc, avp);
580f0b8a 2642 }
f078f209 2643
8feceb67 2644 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2645
2c3db3d5
JM		 2646 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2647 if (sc->beacon.bslot[i] == conf->vif) {
2648 printk(KERN_DEBUG "%s: vif had allocated beacon "
2649 "slot\n", __func__);
2650 sc->beacon.bslot[i] = NULL;
c52f33d0 2651 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2652 }
2653 }
2654
17d7904d 2655 sc->nvifs--;
141b38b6
S		 2656
2657 mutex_unlock(&sc->mutex);
f078f209
LR		 2658}
2659
e8975581 2660static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2661{
bce048d7
JM		 2662 struct ath_wiphy *aphy = hw->priv;
2663 struct ath_softc *sc = aphy->sc;
c46917bb 2664 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e8975581 2665 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2666 struct ath_hw *ah = sc->sc_ah;
194b7c13 2667 bool disable_radio;
f078f209 2668
aa33de09 2669 mutex_lock(&sc->mutex);
141b38b6 2670
194b7c13
LR		 2671 /*
2672 * Leave this as the first check because we need to turn on the
2673 * radio if it was disabled before prior to processing the rest
2674 * of the changes. Likewise we must only disable the radio towards
2675 * the end.
2676 */
64839170 2677 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
194b7c13
LR		 2678 bool enable_radio;
2679 bool all_wiphys_idle;
2680 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
64839170
LR		 2681
2682 spin_lock_bh(&sc->wiphy_lock);
2683 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
194b7c13
LR		 2684 ath9k_set_wiphy_idle(aphy, idle);
2685
2686 if (!idle && all_wiphys_idle)
2687 enable_radio = true;
2688
2689 /*
2690 * After we unlock here its possible another wiphy
2691 * can be re-renabled so to account for that we will
2692 * only disable the radio toward the end of this routine
2693 * if by then all wiphys are still idle.
2694 */
64839170
LR		 2695 spin_unlock_bh(&sc->wiphy_lock);
2696
194b7c13 2697 if (enable_radio) {
68a89116 2698 ath_radio_enable(sc, hw);
c46917bb
LR		 2699 ath_print(common, ATH_DBG_CONFIG,
2700 "not-idle: enabling radio\n");
64839170
LR		 2701 }
2702 }
2703
e7824a50
LR		 2704 /*
2705 * We just prepare to enable PS. We have to wait until our AP has
2706 * ACK'd our null data frame to disable RX otherwise we'll ignore
2707 * those ACKs and end up retransmitting the same null data frames.
2708 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
2709 */
3cbb5dd7
VN		 2710 if (changed & IEEE80211_CONF_CHANGE_PS) {
2711 if (conf->flags & IEEE80211_CONF_PS) {
e7824a50 2712 sc->sc_flags |= SC_OP_PS_ENABLED;
8782b41d
VN		 2713 if (!(ah->caps.hw_caps &
2714 ATH9K_HW_CAP_AUTOSLEEP)) {
2715 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2716 sc->imask |= ATH9K_INT_TIM_TIMER;
2717 ath9k_hw_set_interrupts(sc->sc_ah,
2718 sc->imask);
2719 }
3cbb5dd7 2720 }
e7824a50
LR		 2721 /*
2722 * At this point we know hardware has received an ACK
2723 * of a previously sent null data frame.
2724 */
2725 if ((sc->sc_flags & SC_OP_NULLFUNC_COMPLETED)) {
2726 sc->sc_flags &= ~SC_OP_NULLFUNC_COMPLETED;
2727 sc->ps_enabled = true;
2728 ath9k_hw_setrxabort(sc->sc_ah, 1);
2729 }
3cbb5dd7 2730 } else {
96148326 2731 sc->ps_enabled = false;
e7824a50
LR		 2732 sc->sc_flags &= ~(SC_OP_PS_ENABLED |
2733 SC_OP_NULLFUNC_COMPLETED);
9ecdef4b 2734 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8782b41d
VN		 2735 if (!(ah->caps.hw_caps &
2736 ATH9K_HW_CAP_AUTOSLEEP)) {
2737 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2738 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2739 SC_OP_WAIT_FOR_CAB |
2740 SC_OP_WAIT_FOR_PSPOLL_DATA |
2741 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2742 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2743 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2744 ath9k_hw_set_interrupts(sc->sc_ah,
2745 sc->imask);
2746 }
3cbb5dd7
VN		 2747 }
2748 }
2749 }
2750
4797938c 2751 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2752 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2753 int pos = curchan->hw_value;
ae5eb026 2754
0e2dedf9
JM		 2755 aphy->chan_idx = pos;
2756 aphy->chan_is_ht = conf_is_ht(conf);
2757
8089cc47
JM		 2758 if (aphy->state == ATH_WIPHY_SCAN ||
2759 aphy->state == ATH_WIPHY_ACTIVE)
2760 ath9k_wiphy_pause_all_forced(sc, aphy);
2761 else {
2762 /*
2763 * Do not change operational channel based on a paused
2764 * wiphy changes.
2765 */
2766 goto skip_chan_change;
2767 }
0e2dedf9 2768
c46917bb
LR		 2769 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2770 curchan->center_freq);
f078f209 2771
5f8e077c 2772 /* XXX: remove me eventualy */
0e2dedf9 2773 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2774
ecf70441 2775 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2776
0e2dedf9 2777 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
c46917bb
LR		 2778 ath_print(common, ATH_DBG_FATAL,
2779 "Unable to set channel\n");
aa33de09 2780 mutex_unlock(&sc->mutex);
e11602b7
S		 2781 return -EINVAL;
2782 }
094d05dc 2783 }
f078f209 2784
8089cc47 2785skip_chan_change:
5c020dc6 2786 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2787 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2788
194b7c13
LR		 2789 spin_lock_bh(&sc->wiphy_lock);
2790 disable_radio = ath9k_all_wiphys_idle(sc);
2791 spin_unlock_bh(&sc->wiphy_lock);
2792
64839170 2793 if (disable_radio) {
c46917bb 2794 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
68a89116 2795 ath_radio_disable(sc, hw);
64839170
LR		 2796 }
2797
aa33de09 2798 mutex_unlock(&sc->mutex);
141b38b6 2799
f078f209
LR		 2800 return 0;
2801}
2802
8feceb67
VT		 2803#define SUPPORTED_FILTERS \
2804 (FIF_PROMISC_IN_BSS | \
2805 FIF_ALLMULTI | \
2806 FIF_CONTROL | \
af6a3fc7 2807 FIF_PSPOLL | \
8feceb67
VT		 2808 FIF_OTHER_BSS | \
2809 FIF_BCN_PRBRESP_PROMISC | \
2810 FIF_FCSFAIL)
c83be688 2811
8feceb67
VT		 2812/* FIXME: sc->sc_full_reset ? */
2813static void ath9k_configure_filter(struct ieee80211_hw *hw,
2814 unsigned int changed_flags,
2815 unsigned int *total_flags,
3ac64bee 2816 u64 multicast)
8feceb67 2817{
bce048d7
JM		 2818 struct ath_wiphy *aphy = hw->priv;
2819 struct ath_softc *sc = aphy->sc;
8feceb67 2820 u32 rfilt;
f078f209 2821
8feceb67
VT		 2822 changed_flags &= SUPPORTED_FILTERS;
2823 *total_flags &= SUPPORTED_FILTERS;
f078f209 2824
b77f483f 2825 sc->rx.rxfilter = *total_flags;
aa68aeaa 2826 ath9k_ps_wakeup(sc);
8feceb67
VT		 2827 rfilt = ath_calcrxfilter(sc);
2828 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2829 ath9k_ps_restore(sc);
f078f209 2830
c46917bb
LR		 2831 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2832 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 2833}
f078f209 2834
8feceb67
VT		 2835static void ath9k_sta_notify(struct ieee80211_hw *hw,
2836 struct ieee80211_vif *vif,
2837 enum sta_notify_cmd cmd,
17741cdc 2838 struct ieee80211_sta *sta)
8feceb67 2839{
bce048d7
JM		 2840 struct ath_wiphy *aphy = hw->priv;
2841 struct ath_softc *sc = aphy->sc;
f078f209 2842
8feceb67
VT		 2843 switch (cmd) {
2844 case STA_NOTIFY_ADD:
5640b08e 2845 ath_node_attach(sc, sta);
8feceb67
VT		 2846 break;
2847 case STA_NOTIFY_REMOVE:
b5aa9bf9 2848 ath_node_detach(sc, sta);
8feceb67
VT		 2849 break;
2850 default:
2851 break;
2852 }
f078f209
LR		 2853}
2854
141b38b6 2855static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2856 const struct ieee80211_tx_queue_params *params)
f078f209 2857{
bce048d7
JM		 2858 struct ath_wiphy *aphy = hw->priv;
2859 struct ath_softc *sc = aphy->sc;
c46917bb 2860 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67
VT		 2861 struct ath9k_tx_queue_info qi;
2862 int ret = 0, qnum;
f078f209 2863
8feceb67
VT		 2864 if (queue >= WME_NUM_AC)
2865 return 0;
f078f209 2866
141b38b6
S		 2867 mutex_lock(&sc->mutex);
2868
1ffb0610
S		 2869 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2870
8feceb67
VT		 2871 qi.tqi_aifs = params->aifs;
2872 qi.tqi_cwmin = params->cw_min;
2873 qi.tqi_cwmax = params->cw_max;
2874 qi.tqi_burstTime = params->txop;
2875 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2876
c46917bb
LR		 2877 ath_print(common, ATH_DBG_CONFIG,
2878 "Configure tx [queue/halq] [%d/%d], "
2879 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2880 queue, qnum, params->aifs, params->cw_min,
2881 params->cw_max, params->txop);
f078f209 2882
8feceb67
VT		 2883 ret = ath_txq_update(sc, qnum, &qi);
2884 if (ret)
c46917bb 2885 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2886
94db2936
VN		 2887 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
2888 if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret)
2889 ath_beaconq_config(sc);
2890
141b38b6
S		 2891 mutex_unlock(&sc->mutex);
2892
8feceb67
VT		 2893 return ret;
2894}
f078f209 2895
8feceb67
VT		 2896static int ath9k_set_key(struct ieee80211_hw *hw,
2897 enum set_key_cmd cmd,
dc822b5d
JB		 2898 struct ieee80211_vif *vif,
2899 struct ieee80211_sta *sta,
8feceb67
VT		 2900 struct ieee80211_key_conf *key)
2901{
bce048d7
JM		 2902 struct ath_wiphy *aphy = hw->priv;
2903 struct ath_softc *sc = aphy->sc;
c46917bb 2904 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 2905 int ret = 0;
f078f209 2906
b3bd89ce
JM		 2907 if (modparam_nohwcrypt)
2908 return -ENOSPC;
2909
141b38b6 2910 mutex_lock(&sc->mutex);
3cbb5dd7 2911 ath9k_ps_wakeup(sc);
c46917bb 2912 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2913
8feceb67
VT		 2914 switch (cmd) {
2915 case SET_KEY:
7e86c104 2916 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM		 2917 if (ret >= 0) {
2918 key->hw_key_idx = ret;
8feceb67
VT		 2919 /* push IV and Michael MIC generation to stack */
2920 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2921 if (key->alg == ALG_TKIP)
2922 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2923 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2924 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2925 ret = 0;
8feceb67
VT		 2926 }
2927 break;
2928 case DISABLE_KEY:
7e86c104 2929 ath_key_delete(common, key);
8feceb67
VT		 2930 break;
2931 default:
2932 ret = -EINVAL;
2933 }
f078f209 2934
3cbb5dd7 2935 ath9k_ps_restore(sc);
141b38b6
S		 2936 mutex_unlock(&sc->mutex);
2937
8feceb67
VT		 2938 return ret;
2939}
f078f209 2940
8feceb67
VT		 2941static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2942 struct ieee80211_vif *vif,
2943 struct ieee80211_bss_conf *bss_conf,
2944 u32 changed)
2945{
bce048d7
JM		 2946 struct ath_wiphy *aphy = hw->priv;
2947 struct ath_softc *sc = aphy->sc;
2d0ddec5 2948 struct ath_hw *ah = sc->sc_ah;
1510718d 2949 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 2950 struct ath_vif *avp = (void *)vif->drv_priv;
c6089ccc 2951 int error;
f078f209 2952
141b38b6
S		 2953 mutex_lock(&sc->mutex);
2954
c6089ccc
S		 2955 if (changed & BSS_CHANGED_BSSID) {
2956 /* Set BSSID */
2957 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2958 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 2959 common->curaid = 0;
f2b2143e 2960 ath9k_hw_write_associd(ah);
2d0ddec5 2961
c6089ccc
S		 2962 /* Set aggregation protection mode parameters */
2963 sc->config.ath_aggr_prot = 0;
2d0ddec5 2964
c6089ccc
S		 2965 /* Only legacy IBSS for now */
2966 if (vif->type == NL80211_IFTYPE_ADHOC)
2967 ath_update_chainmask(sc, 0);
2d0ddec5 2968
c6089ccc
S		 2969 ath_print(common, ATH_DBG_CONFIG,
2970 "BSSID: %pM aid: 0x%x\n",
2971 common->curbssid, common->curaid);
2d0ddec5 2972
c6089ccc
S		 2973 /* need to reconfigure the beacon */
2974 sc->sc_flags &= ~SC_OP_BEACONS ;
2975 }
2d0ddec5 2976
c6089ccc
S		 2977 /* Enable transmission of beacons (AP, IBSS, MESH) */
2978 if ((changed & BSS_CHANGED_BEACON) ||
2979 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
2980 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2981 error = ath_beacon_alloc(aphy, vif);
2982 if (!error)
2983 ath_beacon_config(sc, vif);
2d0ddec5
JB		 2984 }
2985
c6089ccc
S		 2986 /* Disable transmission of beacons */
2987 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
2988 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5 2989
c6089ccc
S		 2990 if (changed & BSS_CHANGED_BEACON_INT) {
2991 sc->beacon_interval = bss_conf->beacon_int;
2992 /*
2993 * In case of AP mode, the HW TSF has to be reset
2994 * when the beacon interval changes.
2995 */
2996 if (vif->type == NL80211_IFTYPE_AP) {
2997 sc->sc_flags |= SC_OP_TSF_RESET;
2998 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5
JB		 2999 error = ath_beacon_alloc(aphy, vif);
3000 if (!error)
3001 ath_beacon_config(sc, vif);
c6089ccc
S		 3002 } else {
3003 ath_beacon_config(sc, vif);
2d0ddec5
JB		 3004 }
3005 }
3006
8feceb67 3007 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
c46917bb
LR		 3008 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
3009 bss_conf->use_short_preamble);
8feceb67
VT		 3010 if (bss_conf->use_short_preamble)
3011 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
3012 else
3013 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
3014 }
f078f209 3015
8feceb67 3016 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
c46917bb
LR		 3017 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3018 bss_conf->use_cts_prot);
8feceb67
VT		 3019 if (bss_conf->use_cts_prot &&
3020 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3021 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3022 else
3023 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3024 }
f078f209 3025
8feceb67 3026 if (changed & BSS_CHANGED_ASSOC) {
c46917bb 3027 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 3028 bss_conf->assoc);
5640b08e 3029 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 3030 }
141b38b6
S		 3031
3032 mutex_unlock(&sc->mutex);
8feceb67 3033}
f078f209 3034
8feceb67
VT		 3035static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3036{
3037 u64 tsf;
bce048d7
JM		 3038 struct ath_wiphy *aphy = hw->priv;
3039 struct ath_softc *sc = aphy->sc;
f078f209 3040
141b38b6
S		 3041 mutex_lock(&sc->mutex);
3042 tsf = ath9k_hw_gettsf64(sc->sc_ah);
3043 mutex_unlock(&sc->mutex);
f078f209 3044
8feceb67
VT		 3045 return tsf;
3046}
f078f209 3047
3b5d665b
AF		 3048static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3049{
bce048d7
JM		 3050 struct ath_wiphy *aphy = hw->priv;
3051 struct ath_softc *sc = aphy->sc;
3b5d665b 3052
141b38b6
S		 3053 mutex_lock(&sc->mutex);
3054 ath9k_hw_settsf64(sc->sc_ah, tsf);
3055 mutex_unlock(&sc->mutex);
3b5d665b
AF		 3056}
3057
8feceb67
VT		 3058static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3059{
bce048d7
JM		 3060 struct ath_wiphy *aphy = hw->priv;
3061 struct ath_softc *sc = aphy->sc;
c83be688 3062
141b38b6 3063 mutex_lock(&sc->mutex);
21526d57
LR		 3064
3065 ath9k_ps_wakeup(sc);
141b38b6 3066 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 3067 ath9k_ps_restore(sc);
3068
141b38b6 3069 mutex_unlock(&sc->mutex);
8feceb67 3070}
f078f209 3071
8feceb67 3072static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 3073 struct ieee80211_vif *vif,
141b38b6
S		 3074 enum ieee80211_ampdu_mlme_action action,
3075 struct ieee80211_sta *sta,
3076 u16 tid, u16 *ssn)
8feceb67 3077{
bce048d7
JM		 3078 struct ath_wiphy *aphy = hw->priv;
3079 struct ath_softc *sc = aphy->sc;
8feceb67 3080 int ret = 0;
f078f209 3081
8feceb67
VT		 3082 switch (action) {
3083 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 3084 if (!(sc->sc_flags & SC_OP_RXAGGR))
3085 ret = -ENOTSUPP;
8feceb67
VT		 3086 break;
3087 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 3088 break;
3089 case IEEE80211_AMPDU_TX_START:
f83da965 3090 ath_tx_aggr_start(sc, sta, tid, ssn);
c951ad35 3091 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8feceb67
VT		 3092 break;
3093 case IEEE80211_AMPDU_TX_STOP:
f83da965 3094 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 3095 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8feceb67 3096 break;
b1720231 3097 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 3098 ath_tx_aggr_resume(sc, sta, tid);
3099 break;
8feceb67 3100 default:
c46917bb
LR		 3101 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3102 "Unknown AMPDU action\n");
8feceb67
VT		 3103 }
3104
3105 return ret;
f078f209
LR		 3106}
3107
0c98de65
S		 3108static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3109{
bce048d7
JM		 3110 struct ath_wiphy *aphy = hw->priv;
3111 struct ath_softc *sc = aphy->sc;
05c78d6d 3112 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0c98de65 3113
3d832611 3114 mutex_lock(&sc->mutex);
8089cc47
JM		 3115 if (ath9k_wiphy_scanning(sc)) {
3116 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3117 "same time\n");
3118 /*
3119 * Do not allow the concurrent scanning state for now. This
3120 * could be improved with scanning control moved into ath9k.
3121 */
3d832611 3122 mutex_unlock(&sc->mutex);
8089cc47
JM		 3123 return;
3124 }
3125
3126 aphy->state = ATH_WIPHY_SCAN;
3127 ath9k_wiphy_pause_all_forced(sc, aphy);
0c98de65 3128 sc->sc_flags |= SC_OP_SCANNING;
05c78d6d 3129 del_timer_sync(&common->ani.timer);
b6ce5c33 3130 cancel_delayed_work_sync(&sc->tx_complete_work);
3d832611 3131 mutex_unlock(&sc->mutex);
0c98de65
S		 3132}
3133
3134static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3135{
bce048d7
JM		 3136 struct ath_wiphy *aphy = hw->priv;
3137 struct ath_softc *sc = aphy->sc;
05c78d6d 3138 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0c98de65 3139
3d832611 3140 mutex_lock(&sc->mutex);
8089cc47 3141 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 3142 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 3143 sc->sc_flags |= SC_OP_FULL_RESET;
05c78d6d 3144 ath_start_ani(common);
b6ce5c33 3145 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
d0bec342 3146 ath_beacon_config(sc, NULL);
3d832611 3147 mutex_unlock(&sc->mutex);
0c98de65
S		 3148}
3149
6baff7f9 3150struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 3151 .tx = ath9k_tx,
3152 .start = ath9k_start,
3153 .stop = ath9k_stop,
3154 .add_interface = ath9k_add_interface,
3155 .remove_interface = ath9k_remove_interface,
3156 .config = ath9k_config,
8feceb67 3157 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 3158 .sta_notify = ath9k_sta_notify,
3159 .conf_tx = ath9k_conf_tx,
8feceb67 3160 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 3161 .set_key = ath9k_set_key,
8feceb67 3162 .get_tsf = ath9k_get_tsf,
3b5d665b 3163 .set_tsf = ath9k_set_tsf,
8feceb67 3164 .reset_tsf = ath9k_reset_tsf,
4233df6b 3165 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 3166 .sw_scan_start = ath9k_sw_scan_start,
3167 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 3168 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 3169};
3170
6baff7f9 3171static int __init ath9k_init(void)
f078f209 3172{
ca8a8560
VT		 3173 int error;
3174
ca8a8560
VT		 3175 /* Register rate control algorithm */
3176 error = ath_rate_control_register();
3177 if (error != 0) {
3178 printk(KERN_ERR
b51bb3cd
LR		 3179 "ath9k: Unable to register rate control "
3180 "algorithm: %d\n",
ca8a8560 3181 error);
6baff7f9 3182 goto err_out;
ca8a8560
VT		 3183 }
3184
19d8bc22
GJ		 3185 error = ath9k_debug_create_root();
3186 if (error) {
3187 printk(KERN_ERR
3188 "ath9k: Unable to create debugfs root: %d\n",
3189 error);
3190 goto err_rate_unregister;
3191 }
3192
6baff7f9
GJ		 3193 error = ath_pci_init();
3194 if (error < 0) {
f078f209 3195 printk(KERN_ERR
b51bb3cd 3196 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 3197 error = -ENODEV;
19d8bc22 3198 goto err_remove_root;
f078f209
LR		 3199 }
3200
09329d37
GJ		 3201 error = ath_ahb_init();
3202 if (error < 0) {
3203 error = -ENODEV;
3204 goto err_pci_exit;
3205 }
3206
f078f209 3207 return 0;
6baff7f9 3208
09329d37
GJ		 3209 err_pci_exit:
3210 ath_pci_exit();
3211
19d8bc22
GJ		 3212 err_remove_root:
3213 ath9k_debug_remove_root();
6baff7f9
GJ		 3214 err_rate_unregister:
3215 ath_rate_control_unregister();
3216 err_out:
3217 return error;
f078f209 3218}
6baff7f9 3219module_init(ath9k_init);
f078f209 3220
6baff7f9 3221static void __exit ath9k_exit(void)
f078f209 3222{
09329d37 3223 ath_ahb_exit();
6baff7f9 3224 ath_pci_exit();
19d8bc22 3225 ath9k_debug_remove_root();
ca8a8560 3226 ath_rate_control_unregister();
04bd4638 3227 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 3228}
6baff7f9 3229module_exit(ath9k_exit);
Linux 6.x block layer and io_uring tree(s)