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ath9k: Add helper to get ath9k specific current channel
[linux-block.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
eeddfd9d 38 .max_power = 20, \
5f8e077c
LR		 39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
eeddfd9d 45 .max_power = 20, \
5f8e077c
LR		 46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
4f0fc7c3 192 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
82880a7c
VT		 234static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
236{
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
239 u8 chan_idx;
240
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
244 return channel;
245}
246
ff37e337
S		 247/*
248 * Set/change channels. If the channel is really being changed, it's done
249 * by reseting the chip. To accomplish this we must first cleanup any pending
250 * DMA, then restart stuff.
251*/
0e2dedf9
JM		 252int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
253 struct ath9k_channel *hchan)
ff37e337 254{
cbe61d8a 255 struct ath_hw *ah = sc->sc_ah;
ff37e337 256 bool fastcc = true, stopped;
ae8d2858
LR		 257 struct ieee80211_channel *channel = hw->conf.channel;
258 int r;
ff37e337
S		 259
260 if (sc->sc_flags & SC_OP_INVALID)
261 return -EIO;
262
3cbb5dd7
VN		 263 ath9k_ps_wakeup(sc);
264
c0d7c7af
LR		 265 /*
266 * This is only performed if the channel settings have
267 * actually changed.
268 *
269 * To switch channels clear any pending DMA operations;
270 * wait long enough for the RX fifo to drain, reset the
271 * hardware at the new frequency, and then re-enable
272 * the relevant bits of the h/w.
273 */
274 ath9k_hw_set_interrupts(ah, 0);
043a0405 275 ath_drain_all_txq(sc, false);
c0d7c7af 276 stopped = ath_stoprecv(sc);
ff37e337 277
c0d7c7af
LR		 278 /* XXX: do not flush receive queue here. We don't want
279 * to flush data frames already in queue because of
280 * changing channel. */
ff37e337 281
c0d7c7af
LR		 282 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
283 fastcc = false;
284
285 DPRINTF(sc, ATH_DBG_CONFIG,
286 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 287 sc->sc_ah->curchan->channel,
c0d7c7af 288 channel->center_freq, sc->tx_chan_width);
ff37e337 289
c0d7c7af
LR		 290 spin_lock_bh(&sc->sc_resetlock);
291
292 r = ath9k_hw_reset(ah, hchan, fastcc);
293 if (r) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to reset channel (%u Mhz) "
6b45784f 296 "reset status %d\n",
c0d7c7af
LR		 297 channel->center_freq, r);
298 spin_unlock_bh(&sc->sc_resetlock);
299 return r;
ff37e337 300 }
c0d7c7af
LR		 301 spin_unlock_bh(&sc->sc_resetlock);
302
c0d7c7af
LR		 303 sc->sc_flags &= ~SC_OP_FULL_RESET;
304
305 if (ath_startrecv(sc) != 0) {
306 DPRINTF(sc, ATH_DBG_FATAL,
307 "Unable to restart recv logic\n");
308 return -EIO;
309 }
310
311 ath_cache_conf_rate(sc, &hw->conf);
312 ath_update_txpow(sc);
17d7904d 313 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 314 ath9k_ps_restore(sc);
ff37e337
S		 315 return 0;
316}
317
318/*
319 * This routine performs the periodic noise floor calibration function
320 * that is used to adjust and optimize the chip performance. This
321 * takes environmental changes (location, temperature) into account.
322 * When the task is complete, it reschedules itself depending on the
323 * appropriate interval that was calculated.
324 */
325static void ath_ani_calibrate(unsigned long data)
326{
20977d3e
S		 327 struct ath_softc *sc = (struct ath_softc *)data;
328 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 329 bool longcal = false;
330 bool shortcal = false;
331 bool aniflag = false;
332 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 333 u32 cal_interval, short_cal_interval;
ff37e337 334
20977d3e
S		 335 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
336 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 337
338 /*
339 * don't calibrate when we're scanning.
340 * we are most likely not on our home channel.
341 */
0c98de65 342 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 343 goto set_timer;
ff37e337 344
1ffc1c61
JM		 345 /* Only calibrate if awake */
346 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
347 goto set_timer;
348
349 ath9k_ps_wakeup(sc);
350
ff37e337 351 /* Long calibration runs independently of short calibration. */
17d7904d 352 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 353 longcal = true;
04bd4638 354 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 355 sc->ani.longcal_timer = timestamp;
ff37e337
S		 356 }
357
17d7904d
S		 358 /* Short calibration applies only while caldone is false */
359 if (!sc->ani.caldone) {
20977d3e 360 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 361 shortcal = true;
04bd4638 362 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 363 sc->ani.shortcal_timer = timestamp;
364 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 365 }
366 } else {
17d7904d 367 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 368 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 369 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
370 if (sc->ani.caldone)
371 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 372 }
373 }
374
375 /* Verify whether we must check ANI */
20977d3e 376 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 377 aniflag = true;
17d7904d 378 sc->ani.checkani_timer = timestamp;
ff37e337
S		 379 }
380
381 /* Skip all processing if there's nothing to do. */
382 if (longcal || shortcal || aniflag) {
383 /* Call ANI routine if necessary */
384 if (aniflag)
20977d3e 385 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 386
387 /* Perform calibration if necessary */
388 if (longcal || shortcal) {
379f0440
S		 389 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
390 sc->rx_chainmask, longcal);
391
392 if (longcal)
393 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
394 ah->curchan);
395
396 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
397 ah->curchan->channel, ah->curchan->channelFlags,
398 sc->ani.noise_floor);
ff37e337
S		 399 }
400 }
401
1ffc1c61
JM		 402 ath9k_ps_restore(sc);
403
20977d3e 404set_timer:
ff37e337
S		 405 /*
406 * Set timer interval based on previous results.
407 * The interval must be the shortest necessary to satisfy ANI,
408 * short calibration and long calibration.
409 */
aac9207e 410 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 411 if (sc->sc_ah->config.enable_ani)
aac9207e 412 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 413 if (!sc->ani.caldone)
20977d3e 414 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 415
17d7904d 416 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 417}
418
415f738e
S		 419static void ath_start_ani(struct ath_softc *sc)
420{
421 unsigned long timestamp = jiffies_to_msecs(jiffies);
422
423 sc->ani.longcal_timer = timestamp;
424 sc->ani.shortcal_timer = timestamp;
425 sc->ani.checkani_timer = timestamp;
426
427 mod_timer(&sc->ani.timer,
428 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
429}
430
ff37e337
S		 431/*
432 * Update tx/rx chainmask. For legacy association,
433 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 434 * the chainmask configuration, for bt coexistence, use
435 * the chainmask configuration even in legacy mode.
ff37e337 436 */
0e2dedf9 437void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 438{
c97c92d9 439 if (is_ht ||
2660b81a
S		 440 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
441 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
442 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 443 } else {
17d7904d
S		 444 sc->tx_chainmask = 1;
445 sc->rx_chainmask = 1;
ff37e337
S		 446 }
447
04bd4638 448 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 449 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 450}
451
452static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
453{
454 struct ath_node *an;
455
456 an = (struct ath_node *)sta->drv_priv;
457
87792efc 458 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 459 ath_tx_node_init(sc, an);
87792efc
S		 460 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
461 sta->ht_cap.ampdu_factor);
462 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
463 }
ff37e337
S		 464}
465
466static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
467{
468 struct ath_node *an = (struct ath_node *)sta->drv_priv;
469
470 if (sc->sc_flags & SC_OP_TXAGGR)
471 ath_tx_node_cleanup(sc, an);
472}
473
474static void ath9k_tasklet(unsigned long data)
475{
476 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 477 u32 status = sc->intrstatus;
ff37e337 478
153e080d
VT		 479 ath9k_ps_wakeup(sc);
480
ff37e337 481 if (status & ATH9K_INT_FATAL) {
ff37e337 482 ath_reset(sc, false);
153e080d 483 ath9k_ps_restore(sc);
ff37e337 484 return;
063d8be3 485 }
ff37e337 486
063d8be3
S		 487 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
488 spin_lock_bh(&sc->rx.rxflushlock);
489 ath_rx_tasklet(sc, 0);
490 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 491 }
492
063d8be3
S		 493 if (status & ATH9K_INT_TX)
494 ath_tx_tasklet(sc);
495
54ce846e
JM		 496 if ((status & ATH9K_INT_TSFOOR) &&
497 (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
498 /*
499 * TSF sync does not look correct; remain awake to sync with
500 * the next Beacon.
501 */
502 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 503 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 504 }
505
ff37e337 506 /* re-enable hardware interrupt */
17d7904d 507 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
153e080d 508 ath9k_ps_restore(sc);
ff37e337
S		 509}
510
6baff7f9 511irqreturn_t ath_isr(int irq, void *dev)
ff37e337 512{
063d8be3
S		 513#define SCHED_INTR ( \
514 ATH9K_INT_FATAL | \
515 ATH9K_INT_RXORN | \
516 ATH9K_INT_RXEOL | \
517 ATH9K_INT_RX | \
518 ATH9K_INT_TX | \
519 ATH9K_INT_BMISS | \
520 ATH9K_INT_CST | \
521 ATH9K_INT_TSFOOR)
522
ff37e337 523 struct ath_softc *sc = dev;
cbe61d8a 524 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 525 enum ath9k_int status;
526 bool sched = false;
527
063d8be3
S		 528 /*
529 * The hardware is not ready/present, don't
530 * touch anything. Note this can happen early
531 * on if the IRQ is shared.
532 */
533 if (sc->sc_flags & SC_OP_INVALID)
534 return IRQ_NONE;
ff37e337 535
063d8be3
S		 536
537 /* shared irq, not for us */
538
153e080d 539 if (!ath9k_hw_intrpend(ah))
063d8be3 540 return IRQ_NONE;
063d8be3
S		 541
542 /*
543 * Figure out the reason(s) for the interrupt. Note
544 * that the hal returns a pseudo-ISR that may include
545 * bits we haven't explicitly enabled so we mask the
546 * value to insure we only process bits we requested.
547 */
548 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
549 status &= sc->imask; /* discard unasked-for bits */
ff37e337 550
063d8be3
S		 551 /*
552 * If there are no status bits set, then this interrupt was not
553 * for me (should have been caught above).
554 */
153e080d 555 if (!status)
063d8be3 556 return IRQ_NONE;
ff37e337 557
063d8be3
S		 558 /* Cache the status */
559 sc->intrstatus = status;
560
561 if (status & SCHED_INTR)
562 sched = true;
563
564 /*
565 * If a FATAL or RXORN interrupt is received, we have to reset the
566 * chip immediately.
567 */
568 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
569 goto chip_reset;
570
571 if (status & ATH9K_INT_SWBA)
572 tasklet_schedule(&sc->bcon_tasklet);
573
574 if (status & ATH9K_INT_TXURN)
575 ath9k_hw_updatetxtriglevel(ah, true);
576
577 if (status & ATH9K_INT_MIB) {
ff37e337 578 /*
063d8be3
S		 579 * Disable interrupts until we service the MIB
580 * interrupt; otherwise it will continue to
581 * fire.
ff37e337 582 */
063d8be3
S		 583 ath9k_hw_set_interrupts(ah, 0);
584 /*
585 * Let the hal handle the event. We assume
586 * it will clear whatever condition caused
587 * the interrupt.
588 */
589 ath9k_hw_procmibevent(ah, &sc->nodestats);
590 ath9k_hw_set_interrupts(ah, sc->imask);
591 }
ff37e337 592
153e080d
VT		 593 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
594 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 595 /* Clear RxAbort bit so that we can
596 * receive frames */
597 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 598 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 599 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 600 }
063d8be3
S		 601
602chip_reset:
ff37e337 603
817e11de
S		 604 ath_debug_stat_interrupt(sc, status);
605
ff37e337
S		 606 if (sched) {
607 /* turn off every interrupt except SWBA */
17d7904d 608 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 609 tasklet_schedule(&sc->intr_tq);
610 }
611
612 return IRQ_HANDLED;
063d8be3
S		 613
614#undef SCHED_INTR
ff37e337
S		 615}
616
f078f209 617static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 618 struct ieee80211_channel *chan,
094d05dc 619 enum nl80211_channel_type channel_type)
f078f209
LR		 620{
621 u32 chanmode = 0;
f078f209
LR		 622
623 switch (chan->band) {
624 case IEEE80211_BAND_2GHZ:
094d05dc
S		 625 switch(channel_type) {
626 case NL80211_CHAN_NO_HT:
627 case NL80211_CHAN_HT20:
f078f209 628 chanmode = CHANNEL_G_HT20;
094d05dc
S		 629 break;
630 case NL80211_CHAN_HT40PLUS:
f078f209 631 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 632 break;
633 case NL80211_CHAN_HT40MINUS:
f078f209 634 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 635 break;
636 }
f078f209
LR		 637 break;
638 case IEEE80211_BAND_5GHZ:
094d05dc
S		 639 switch(channel_type) {
640 case NL80211_CHAN_NO_HT:
641 case NL80211_CHAN_HT20:
f078f209 642 chanmode = CHANNEL_A_HT20;
094d05dc
S		 643 break;
644 case NL80211_CHAN_HT40PLUS:
f078f209 645 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 646 break;
647 case NL80211_CHAN_HT40MINUS:
f078f209 648 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 649 break;
650 }
f078f209
LR		 651 break;
652 default:
653 break;
654 }
655
656 return chanmode;
657}
658
6ace2891 659static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 660 struct ath9k_keyval *hk, const u8 *addr,
661 bool authenticator)
f078f209 662{
6ace2891
JM		 663 const u8 *key_rxmic;
664 const u8 *key_txmic;
f078f209 665
6ace2891
JM		 666 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
667 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 668
669 if (addr == NULL) {
d216aaa6
JM		 670 /*
671 * Group key installation - only two key cache entries are used
672 * regardless of splitmic capability since group key is only
673 * used either for TX or RX.
674 */
3f53dd64
JM		 675 if (authenticator) {
676 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
677 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
678 } else {
679 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
680 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
681 }
d216aaa6 682 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 683 }
17d7904d 684 if (!sc->splitmic) {
d216aaa6 685 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 686 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
687 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 688 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 689 }
d216aaa6
JM		 690
691 /* Separate key cache entries for TX and RX */
692
693 /* TX key goes at first index, RX key at +32. */
f078f209 694 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 695 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
696 /* TX MIC entry failed. No need to proceed further */
d8baa939 697 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 698 "Setting TX MIC Key Failed\n");
f078f209
LR		 699 return 0;
700 }
701
702 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
703 /* XXX delete tx key on failure? */
d216aaa6 704 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 705}
706
707static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
708{
709 int i;
710
17d7904d
S		 711 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
712 if (test_bit(i, sc->keymap) ||
713 test_bit(i + 64, sc->keymap))
6ace2891 714 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 715 if (sc->splitmic &&
716 (test_bit(i + 32, sc->keymap) ||
717 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 718 continue; /* At least one part of TKIP key allocated */
719
720 /* Found a free slot for a TKIP key */
721 return i;
722 }
723 return -1;
724}
725
726static int ath_reserve_key_cache_slot(struct ath_softc *sc)
727{
728 int i;
729
730 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 731 if (sc->splitmic) {
732 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
733 if (!test_bit(i, sc->keymap) &&
734 (test_bit(i + 32, sc->keymap) ||
735 test_bit(i + 64, sc->keymap) ||
736 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 737 return i;
17d7904d
S		 738 if (!test_bit(i + 32, sc->keymap) &&
739 (test_bit(i, sc->keymap) ||
740 test_bit(i + 64, sc->keymap) ||
741 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 742 return i + 32;
17d7904d
S		 743 if (!test_bit(i + 64, sc->keymap) &&
744 (test_bit(i , sc->keymap) ||
745 test_bit(i + 32, sc->keymap) ||
746 test_bit(i + 64 + 32, sc->keymap)))
ea612132 747 return i + 64;
17d7904d
S		 748 if (!test_bit(i + 64 + 32, sc->keymap) &&
749 (test_bit(i, sc->keymap) ||
750 test_bit(i + 32, sc->keymap) ||
751 test_bit(i + 64, sc->keymap)))
ea612132 752 return i + 64 + 32;
6ace2891
JM		 753 }
754 } else {
17d7904d
S		 755 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
756 if (!test_bit(i, sc->keymap) &&
757 test_bit(i + 64, sc->keymap))
6ace2891 758 return i;
17d7904d
S		 759 if (test_bit(i, sc->keymap) &&
760 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 761 return i + 64;
762 }
763 }
764
765 /* No partially used TKIP slots, pick any available slot */
17d7904d 766 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 767 /* Do not allow slots that could be needed for TKIP group keys
768 * to be used. This limitation could be removed if we know that
769 * TKIP will not be used. */
770 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
771 continue;
17d7904d 772 if (sc->splitmic) {
be2864cf
JM		 773 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
774 continue;
775 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
776 continue;
777 }
778
17d7904d 779 if (!test_bit(i, sc->keymap))
6ace2891
JM		 780 return i; /* Found a free slot for a key */
781 }
782
783 /* No free slot found */
784 return -1;
f078f209
LR		 785}
786
787static int ath_key_config(struct ath_softc *sc,
3f53dd64 788 struct ieee80211_vif *vif,
dc822b5d 789 struct ieee80211_sta *sta,
f078f209
LR		 790 struct ieee80211_key_conf *key)
791{
f078f209
LR		 792 struct ath9k_keyval hk;
793 const u8 *mac = NULL;
794 int ret = 0;
6ace2891 795 int idx;
f078f209
LR		 796
797 memset(&hk, 0, sizeof(hk));
798
799 switch (key->alg) {
800 case ALG_WEP:
801 hk.kv_type = ATH9K_CIPHER_WEP;
802 break;
803 case ALG_TKIP:
804 hk.kv_type = ATH9K_CIPHER_TKIP;
805 break;
806 case ALG_CCMP:
807 hk.kv_type = ATH9K_CIPHER_AES_CCM;
808 break;
809 default:
ca470b29 810 return -EOPNOTSUPP;
f078f209
LR		 811 }
812
6ace2891 813 hk.kv_len = key->keylen;
f078f209
LR		 814 memcpy(hk.kv_val, key->key, key->keylen);
815
6ace2891
JM		 816 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
817 /* For now, use the default keys for broadcast keys. This may
818 * need to change with virtual interfaces. */
819 idx = key->keyidx;
820 } else if (key->keyidx) {
dc822b5d
JB		 821 if (WARN_ON(!sta))
822 return -EOPNOTSUPP;
823 mac = sta->addr;
824
6ace2891
JM		 825 if (vif->type != NL80211_IFTYPE_AP) {
826 /* Only keyidx 0 should be used with unicast key, but
827 * allow this for client mode for now. */
828 idx = key->keyidx;
829 } else
830 return -EIO;
f078f209 831 } else {
dc822b5d
JB		 832 if (WARN_ON(!sta))
833 return -EOPNOTSUPP;
834 mac = sta->addr;
835
6ace2891
JM		 836 if (key->alg == ALG_TKIP)
837 idx = ath_reserve_key_cache_slot_tkip(sc);
838 else
839 idx = ath_reserve_key_cache_slot(sc);
840 if (idx < 0)
ca470b29 841 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 842 }
843
844 if (key->alg == ALG_TKIP)
3f53dd64
JM		 845 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
846 vif->type == NL80211_IFTYPE_AP);
f078f209 847 else
d216aaa6 848 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 849
850 if (!ret)
851 return -EIO;
852
17d7904d 853 set_bit(idx, sc->keymap);
6ace2891 854 if (key->alg == ALG_TKIP) {
17d7904d
S		 855 set_bit(idx + 64, sc->keymap);
856 if (sc->splitmic) {
857 set_bit(idx + 32, sc->keymap);
858 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 859 }
860 }
861
862 return idx;
f078f209
LR		 863}
864
865static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
866{
6ace2891
JM		 867 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
868 if (key->hw_key_idx < IEEE80211_WEP_NKID)
869 return;
870
17d7904d 871 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 872 if (key->alg != ALG_TKIP)
873 return;
f078f209 874
17d7904d
S		 875 clear_bit(key->hw_key_idx + 64, sc->keymap);
876 if (sc->splitmic) {
877 clear_bit(key->hw_key_idx + 32, sc->keymap);
878 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 879 }
f078f209
LR		 880}
881
eb2599ca
S		 882static void setup_ht_cap(struct ath_softc *sc,
883 struct ieee80211_sta_ht_cap *ht_info)
f078f209 884{
60653678
S		 885#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
886#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 887
d9fe60de
JB		 888 ht_info->ht_supported = true;
889 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
890 IEEE80211_HT_CAP_SM_PS |
891 IEEE80211_HT_CAP_SGI_40 |
892 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 893
60653678
S		 894 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
895 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 896
d9fe60de
JB		 897 /* set up supported mcs set */
898 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 899
17d7904d 900 switch(sc->rx_chainmask) {
eb2599ca
S		 901 case 1:
902 ht_info->mcs.rx_mask[0] = 0xff;
903 break;
3c457265 904 case 3:
eb2599ca
S		 905 case 5:
906 case 7:
907 default:
908 ht_info->mcs.rx_mask[0] = 0xff;
909 ht_info->mcs.rx_mask[1] = 0xff;
910 break;
911 }
912
d9fe60de 913 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 914}
915
8feceb67 916static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 917 struct ieee80211_vif *vif,
8feceb67 918 struct ieee80211_bss_conf *bss_conf)
f078f209 919{
17d7904d 920 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 921
8feceb67 922 if (bss_conf->assoc) {
094d05dc 923 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 924 bss_conf->aid, sc->curbssid);
f078f209 925
8feceb67 926 /* New association, store aid */
d97809db 927 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 928 sc->curaid = bss_conf->aid;
ba52da58 929 ath9k_hw_write_associd(sc);
ccdfeab6
JM		 930
931 /*
932 * Request a re-configuration of Beacon related timers
933 * on the receipt of the first Beacon frame (i.e.,
934 * after time sync with the AP).
935 */
936 sc->sc_flags |= SC_OP_BEACON_SYNC;
8feceb67 937 }
f078f209 938
8feceb67 939 /* Configure the beacon */
2c3db3d5 940 ath_beacon_config(sc, vif);
f078f209 941
8feceb67 942 /* Reset rssi stats */
17d7904d
S		 943 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
944 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
945 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
946 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 947
415f738e 948 ath_start_ani(sc);
8feceb67 949 } else {
1ffb0610 950 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 951 sc->curaid = 0;
f078f209 952 }
8feceb67 953}
f078f209 954
8feceb67
VT		 955/********************************/
956/* LED functions */
957/********************************/
f078f209 958
f2bffa7e
VT		 959static void ath_led_blink_work(struct work_struct *work)
960{
961 struct ath_softc *sc = container_of(work, struct ath_softc,
962 ath_led_blink_work.work);
963
964 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
965 return;
85067c06
VT		 966
967 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
968 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
969 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
970 else
971 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
972 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 973
974 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
975 (sc->sc_flags & SC_OP_LED_ON) ?
976 msecs_to_jiffies(sc->led_off_duration) :
977 msecs_to_jiffies(sc->led_on_duration));
978
85067c06
VT		 979 sc->led_on_duration = sc->led_on_cnt ?
980 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
981 ATH_LED_ON_DURATION_IDLE;
982 sc->led_off_duration = sc->led_off_cnt ?
983 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
984 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 985 sc->led_on_cnt = sc->led_off_cnt = 0;
986 if (sc->sc_flags & SC_OP_LED_ON)
987 sc->sc_flags &= ~SC_OP_LED_ON;
988 else
989 sc->sc_flags |= SC_OP_LED_ON;
990}
991
8feceb67
VT		 992static void ath_led_brightness(struct led_classdev *led_cdev,
993 enum led_brightness brightness)
994{
995 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
996 struct ath_softc *sc = led->sc;
f078f209 997
8feceb67
VT		 998 switch (brightness) {
999 case LED_OFF:
1000 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 1001 led->led_type == ATH_LED_RADIO) {
1002 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1003 (led->led_type == ATH_LED_RADIO));
8feceb67 1004 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1005 if (led->led_type == ATH_LED_RADIO)
1006 sc->sc_flags &= ~SC_OP_LED_ON;
1007 } else {
1008 sc->led_off_cnt++;
1009 }
8feceb67
VT		 1010 break;
1011 case LED_FULL:
f2bffa7e 1012 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1013 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1014 queue_delayed_work(sc->hw->workqueue,
1015 &sc->ath_led_blink_work, 0);
1016 } else if (led->led_type == ATH_LED_RADIO) {
1017 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1018 sc->sc_flags |= SC_OP_LED_ON;
1019 } else {
1020 sc->led_on_cnt++;
1021 }
8feceb67
VT		 1022 break;
1023 default:
1024 break;
f078f209 1025 }
8feceb67 1026}
f078f209 1027
8feceb67
VT		 1028static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1029 char *trigger)
1030{
1031 int ret;
f078f209 1032
8feceb67
VT		 1033 led->sc = sc;
1034 led->led_cdev.name = led->name;
1035 led->led_cdev.default_trigger = trigger;
1036 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1037
8feceb67
VT		 1038 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1039 if (ret)
1040 DPRINTF(sc, ATH_DBG_FATAL,
1041 "Failed to register led:%s", led->name);
1042 else
1043 led->registered = 1;
1044 return ret;
1045}
f078f209 1046
8feceb67
VT		 1047static void ath_unregister_led(struct ath_led *led)
1048{
1049 if (led->registered) {
1050 led_classdev_unregister(&led->led_cdev);
1051 led->registered = 0;
f078f209 1052 }
f078f209
LR		 1053}
1054
8feceb67 1055static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1056{
f2bffa7e 1057 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1058 ath_unregister_led(&sc->assoc_led);
1059 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1060 ath_unregister_led(&sc->tx_led);
1061 ath_unregister_led(&sc->rx_led);
1062 ath_unregister_led(&sc->radio_led);
1063 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1064}
f078f209 1065
8feceb67
VT		 1066static void ath_init_leds(struct ath_softc *sc)
1067{
1068 char *trigger;
1069 int ret;
f078f209 1070
8feceb67
VT		 1071 /* Configure gpio 1 for output */
1072 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1073 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1074 /* LED off, active low */
1075 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1076
f2bffa7e
VT		 1077 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1078
8feceb67
VT		 1079 trigger = ieee80211_get_radio_led_name(sc->hw);
1080 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1081 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1082 ret = ath_register_led(sc, &sc->radio_led, trigger);
1083 sc->radio_led.led_type = ATH_LED_RADIO;
1084 if (ret)
1085 goto fail;
7dcfdcd9 1086
8feceb67
VT		 1087 trigger = ieee80211_get_assoc_led_name(sc->hw);
1088 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1089 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1090 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1091 sc->assoc_led.led_type = ATH_LED_ASSOC;
1092 if (ret)
1093 goto fail;
f078f209 1094
8feceb67
VT		 1095 trigger = ieee80211_get_tx_led_name(sc->hw);
1096 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1097 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1098 ret = ath_register_led(sc, &sc->tx_led, trigger);
1099 sc->tx_led.led_type = ATH_LED_TX;
1100 if (ret)
1101 goto fail;
f078f209 1102
8feceb67
VT		 1103 trigger = ieee80211_get_rx_led_name(sc->hw);
1104 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1105 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1106 ret = ath_register_led(sc, &sc->rx_led, trigger);
1107 sc->rx_led.led_type = ATH_LED_RX;
1108 if (ret)
1109 goto fail;
f078f209 1110
8feceb67
VT		 1111 return;
1112
1113fail:
1114 ath_deinit_leds(sc);
f078f209
LR		 1115}
1116
7ec3e514 1117void ath_radio_enable(struct ath_softc *sc)
500c064d 1118{
cbe61d8a 1119 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1120 struct ieee80211_channel *channel = sc->hw->conf.channel;
1121 int r;
500c064d 1122
3cbb5dd7 1123 ath9k_ps_wakeup(sc);
d2f5b3a6 1124 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1125
d2f5b3a6 1126 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1127 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1128 if (r) {
500c064d 1129 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1130 "Unable to reset channel %u (%uMhz) ",
6b45784f 1131 "reset status %d\n",
ae8d2858 1132 channel->center_freq, r);
500c064d
VT		 1133 }
1134 spin_unlock_bh(&sc->sc_resetlock);
1135
1136 ath_update_txpow(sc);
1137 if (ath_startrecv(sc) != 0) {
1138 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1139 "Unable to restart recv logic\n");
500c064d
VT		 1140 return;
1141 }
1142
1143 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1144 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1145
1146 /* Re-Enable interrupts */
17d7904d 1147 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1148
1149 /* Enable LED */
1150 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1151 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1152 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1153
1154 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1155 ath9k_ps_restore(sc);
500c064d
VT		 1156}
1157
7ec3e514 1158void ath_radio_disable(struct ath_softc *sc)
500c064d 1159{
cbe61d8a 1160 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1161 struct ieee80211_channel *channel = sc->hw->conf.channel;
1162 int r;
500c064d 1163
3cbb5dd7 1164 ath9k_ps_wakeup(sc);
500c064d
VT		 1165 ieee80211_stop_queues(sc->hw);
1166
1167 /* Disable LED */
1168 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1169 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1170
1171 /* Disable interrupts */
1172 ath9k_hw_set_interrupts(ah, 0);
1173
043a0405 1174 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1175 ath_stoprecv(sc); /* turn off frame recv */
1176 ath_flushrecv(sc); /* flush recv queue */
1177
1178 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1179 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1180 if (r) {
500c064d 1181 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1182 "Unable to reset channel %u (%uMhz) "
6b45784f 1183 "reset status %d\n",
ae8d2858 1184 channel->center_freq, r);
500c064d
VT		 1185 }
1186 spin_unlock_bh(&sc->sc_resetlock);
1187
1188 ath9k_hw_phy_disable(ah);
d2f5b3a6 1189 ath9k_hw_configpcipowersave(ah, 1);
500c064d 1190 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1191 ath9k_ps_restore(sc);
500c064d
VT		 1192}
1193
5077fd35
GJ		 1194#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1195
1196/*******************/
1197/* Rfkill */
1198/*******************/
1199
500c064d
VT		 1200static bool ath_is_rfkill_set(struct ath_softc *sc)
1201{
cbe61d8a 1202 struct ath_hw *ah = sc->sc_ah;
500c064d 1203
2660b81a
S		 1204 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1205 ah->rfkill_polarity;
500c064d
VT		 1206}
1207
19d337df
JB		 1208/* s/w rfkill handlers */
1209static int ath_rfkill_set_block(void *data, bool blocked)
500c064d 1210{
19d337df 1211 struct ath_softc *sc = data;
500c064d 1212
19d337df
JB		 1213 if (blocked)
1214 ath_radio_disable(sc);
1215 else
1216 ath_radio_enable(sc);
500c064d 1217
19d337df 1218 return 0;
500c064d
VT		 1219}
1220
19d337df 1221static void ath_rfkill_poll_state(struct rfkill *rfkill, void *data)
500c064d
VT		 1222{
1223 struct ath_softc *sc = data;
19d337df 1224 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1225
19d337df
JB		 1226 if (rfkill_set_hw_state(rfkill, blocked))
1227 ath_radio_disable(sc);
1228 else
1229 ath_radio_enable(sc);
500c064d
VT		 1230}
1231
1232/* Init s/w rfkill */
1233static int ath_init_sw_rfkill(struct ath_softc *sc)
1234{
19d337df
JB		 1235 sc->rf_kill.ops.set_block = ath_rfkill_set_block;
1236 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1237 sc->rf_kill.ops.poll = ath_rfkill_poll_state;
1238
1239 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1240 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1241
1242 sc->rf_kill.rfkill = rfkill_alloc(sc->rf_kill.rfkill_name,
1243 wiphy_dev(sc->hw->wiphy),
1244 RFKILL_TYPE_WLAN,
1245 &sc->rf_kill.ops, sc);
500c064d
VT		 1246 if (!sc->rf_kill.rfkill) {
1247 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1248 return -ENOMEM;
1249 }
1250
500c064d
VT		 1251 return 0;
1252}
1253
1254/* Deinitialize rfkill */
1255static void ath_deinit_rfkill(struct ath_softc *sc)
1256{
500c064d
VT		 1257 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1258 rfkill_unregister(sc->rf_kill.rfkill);
19d337df 1259 rfkill_destroy(sc->rf_kill.rfkill);
500c064d 1260 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
500c064d
VT		 1261 }
1262}
9c84b797
S		 1263
1264static int ath_start_rfkill_poll(struct ath_softc *sc)
1265{
9c84b797
S		 1266 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1267 if (rfkill_register(sc->rf_kill.rfkill)) {
1268 DPRINTF(sc, ATH_DBG_FATAL,
1269 "Unable to register rfkill\n");
19d337df 1270 rfkill_destroy(sc->rf_kill.rfkill);
9c84b797
S		 1271
1272 /* Deinitialize the device */
39c3c2f2 1273 ath_cleanup(sc);
9c84b797
S		 1274 return -EIO;
1275 } else {
1276 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1277 }
1278 }
1279
1280 return 0;
1281}
500c064d
VT		 1282#endif /* CONFIG_RFKILL */
1283
6baff7f9 1284void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1285{
1286 ath_detach(sc);
1287 free_irq(sc->irq, sc);
1288 ath_bus_cleanup(sc);
c52f33d0 1289 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1290 ieee80211_free_hw(sc->hw);
1291}
1292
6baff7f9 1293void ath_detach(struct ath_softc *sc)
f078f209 1294{
8feceb67 1295 struct ieee80211_hw *hw = sc->hw;
9c84b797 1296 int i = 0;
f078f209 1297
3cbb5dd7
VN		 1298 ath9k_ps_wakeup(sc);
1299
04bd4638 1300 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1301
e97275cb 1302#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1303 ath_deinit_rfkill(sc);
1304#endif
3fcdfb4b 1305 ath_deinit_leds(sc);
0e2dedf9 1306 cancel_work_sync(&sc->chan_work);
f98c3bd2 1307 cancel_delayed_work_sync(&sc->wiphy_work);
3fcdfb4b 1308
c52f33d0
JM		 1309 for (i = 0; i < sc->num_sec_wiphy; i++) {
1310 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1311 if (aphy == NULL)
1312 continue;
1313 sc->sec_wiphy[i] = NULL;
1314 ieee80211_unregister_hw(aphy->hw);
1315 ieee80211_free_hw(aphy->hw);
1316 }
3fcdfb4b 1317 ieee80211_unregister_hw(hw);
8feceb67
VT		 1318 ath_rx_cleanup(sc);
1319 ath_tx_cleanup(sc);
f078f209 1320
9c84b797
S		 1321 tasklet_kill(&sc->intr_tq);
1322 tasklet_kill(&sc->bcon_tasklet);
f078f209 1323
9c84b797
S		 1324 if (!(sc->sc_flags & SC_OP_INVALID))
1325 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1326
9c84b797
S		 1327 /* cleanup tx queues */
1328 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1329 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1330 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1331
1332 ath9k_hw_detach(sc->sc_ah);
826d2680 1333 ath9k_exit_debug(sc);
3cbb5dd7 1334 ath9k_ps_restore(sc);
f078f209
LR		 1335}
1336
e3bb249b
BC		 1337static int ath9k_reg_notifier(struct wiphy *wiphy,
1338 struct regulatory_request *request)
1339{
1340 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1341 struct ath_wiphy *aphy = hw->priv;
1342 struct ath_softc *sc = aphy->sc;
1343 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1344
1345 return ath_reg_notifier_apply(wiphy, request, reg);
1346}
1347
ff37e337
S		 1348static int ath_init(u16 devid, struct ath_softc *sc)
1349{
cbe61d8a 1350 struct ath_hw *ah = NULL;
ff37e337
S		 1351 int status;
1352 int error = 0, i;
1353 int csz = 0;
1354
1355 /* XXX: hardware will not be ready until ath_open() being called */
1356 sc->sc_flags |= SC_OP_INVALID;
88b126af 1357
826d2680
S		 1358 if (ath9k_init_debug(sc) < 0)
1359 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1360
c52f33d0 1361 spin_lock_init(&sc->wiphy_lock);
ff37e337 1362 spin_lock_init(&sc->sc_resetlock);
6158425b 1363 spin_lock_init(&sc->sc_serial_rw);
aa33de09 1364 mutex_init(&sc->mutex);
ff37e337 1365 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1366 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1367 (unsigned long)sc);
1368
1369 /*
1370 * Cache line size is used to size and align various
1371 * structures used to communicate with the hardware.
1372 */
88d15707 1373 ath_read_cachesize(sc, &csz);
ff37e337 1374 /* XXX assert csz is non-zero */
17d7904d 1375 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1376
cbe61d8a 1377 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1378 if (ah == NULL) {
1379 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1380 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1381 error = -ENXIO;
1382 goto bad;
1383 }
1384 sc->sc_ah = ah;
1385
1386 /* Get the hardware key cache size. */
2660b81a 1387 sc->keymax = ah->caps.keycache_size;
17d7904d 1388 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1389 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1390 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1391 ATH_KEYMAX, sc->keymax);
1392 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1393 }
1394
1395 /*
1396 * Reset the key cache since some parts do not
1397 * reset the contents on initial power up.
1398 */
17d7904d 1399 for (i = 0; i < sc->keymax; i++)
ff37e337 1400 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1401
85efc86e 1402 if (error)
ff37e337
S		 1403 goto bad;
1404
1405 /* default to MONITOR mode */
2660b81a 1406 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1407
ff37e337
S		 1408 /* Setup rate tables */
1409
1410 ath_rate_attach(sc);
1411 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1412 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1413
1414 /*
1415 * Allocate hardware transmit queues: one queue for
1416 * beacon frames and one data queue for each QoS
1417 * priority. Note that the hal handles reseting
1418 * these queues at the needed time.
1419 */
b77f483f
S		 1420 sc->beacon.beaconq = ath_beaconq_setup(ah);
1421 if (sc->beacon.beaconq == -1) {
ff37e337 1422 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1423 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1424 error = -EIO;
1425 goto bad2;
1426 }
b77f483f
S		 1427 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1428 if (sc->beacon.cabq == NULL) {
ff37e337 1429 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1430 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1431 error = -EIO;
1432 goto bad2;
1433 }
1434
17d7904d 1435 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1436 ath_cabq_update(sc);
1437
b77f483f
S		 1438 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1439 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1440
1441 /* Setup data queues */
1442 /* NB: ensure BK queue is the lowest priority h/w queue */
1443 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1444 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1445 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1446 error = -EIO;
1447 goto bad2;
1448 }
1449
1450 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1451 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1452 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1453 error = -EIO;
1454 goto bad2;
1455 }
1456 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1457 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1458 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1459 error = -EIO;
1460 goto bad2;
1461 }
1462 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1463 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1464 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1465 error = -EIO;
1466 goto bad2;
1467 }
1468
1469 /* Initializes the noise floor to a reasonable default value.
1470 * Later on this will be updated during ANI processing. */
1471
17d7904d
S		 1472 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1473 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1474
1475 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1476 ATH9K_CIPHER_TKIP, NULL)) {
1477 /*
1478 * Whether we should enable h/w TKIP MIC.
1479 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1480 * report WMM capable, so it's always safe to turn on
1481 * TKIP MIC in this case.
1482 */
1483 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1484 0, 1, NULL);
1485 }
1486
1487 /*
1488 * Check whether the separate key cache entries
1489 * are required to handle both tx+rx MIC keys.
1490 * With split mic keys the number of stations is limited
1491 * to 27 otherwise 59.
1492 */
1493 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1494 ATH9K_CIPHER_TKIP, NULL)
1495 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1496 ATH9K_CIPHER_MIC, NULL)
1497 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1498 0, NULL))
17d7904d 1499 sc->splitmic = 1;
ff37e337
S		 1500
1501 /* turn on mcast key search if possible */
1502 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1503 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1504 1, NULL);
1505
17d7904d 1506 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1507
1508 /* 11n Capabilities */
2660b81a 1509 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1510 sc->sc_flags |= SC_OP_TXAGGR;
1511 sc->sc_flags |= SC_OP_RXAGGR;
1512 }
1513
2660b81a
S		 1514 sc->tx_chainmask = ah->caps.tx_chainmask;
1515 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1516
1517 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1518 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1519
8ca21f01 1520 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1521 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1522
b77f483f 1523 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1524
1525 /* initialize beacon slots */
c52f33d0 1526 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1527 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1528 sc->beacon.bslot_aphy[i] = NULL;
1529 }
ff37e337 1530
ff37e337
S		 1531 /* setup channels and rates */
1532
5f8e077c 1533 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1534 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1535 sc->rates[IEEE80211_BAND_2GHZ];
1536 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1537 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1538 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1539
2660b81a 1540 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1541 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1542 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1543 sc->rates[IEEE80211_BAND_5GHZ];
1544 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1545 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1546 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1547 }
1548
2660b81a 1549 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1550 ath9k_hw_btcoex_enable(sc->sc_ah);
1551
ff37e337
S		 1552 return 0;
1553bad2:
1554 /* cleanup tx queues */
1555 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1556 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1557 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1558bad:
1559 if (ah)
1560 ath9k_hw_detach(ah);
40b130a9 1561 ath9k_exit_debug(sc);
ff37e337
S		 1562
1563 return error;
1564}
1565
c52f33d0 1566void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1567{
9c84b797
S		 1568 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1569 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1570 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1571 IEEE80211_HW_AMPDU_AGGREGATION |
1572 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1573 IEEE80211_HW_PS_NULLFUNC_STACK |
1574 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1575
b3bd89ce 1576 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1577 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1578
9c84b797
S		 1579 hw->wiphy->interface_modes =
1580 BIT(NL80211_IFTYPE_AP) |
1581 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1582 BIT(NL80211_IFTYPE_ADHOC) |
1583 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1584
8feceb67 1585 hw->queues = 4;
e63835b0 1586 hw->max_rates = 4;
171387ef 1587 hw->channel_change_time = 5000;
465ca84d 1588 hw->max_listen_interval = 10;
e63835b0 1589 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1590 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1591 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1592
8feceb67 1593 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1594
c52f33d0
JM		 1595 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1596 &sc->sbands[IEEE80211_BAND_2GHZ];
1597 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1598 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1599 &sc->sbands[IEEE80211_BAND_5GHZ];
1600}
1601
1602int ath_attach(u16 devid, struct ath_softc *sc)
1603{
1604 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1605 int error = 0, i;
3a702e49 1606 struct ath_regulatory *reg;
c52f33d0
JM		 1607
1608 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1609
1610 error = ath_init(devid, sc);
1611 if (error != 0)
1612 return error;
1613
1614 /* get mac address from hardware and set in mac80211 */
1615
1616 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1617
1618 ath_set_hw_capab(sc, hw);
1619
c26c2e57
LR		 1620 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1621 ath9k_reg_notifier);
1622 if (error)
1623 return error;
1624
1625 reg = &sc->sc_ah->regulatory;
1626
2660b81a 1627 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1628 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1629 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1630 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1631 }
1632
db93e7b5
SB		 1633 /* initialize tx/rx engine */
1634 error = ath_tx_init(sc, ATH_TXBUF);
1635 if (error != 0)
40b130a9 1636 goto error_attach;
8feceb67 1637
db93e7b5
SB		 1638 error = ath_rx_init(sc, ATH_RXBUF);
1639 if (error != 0)
40b130a9 1640 goto error_attach;
8feceb67 1641
e97275cb 1642#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1643 /* Initialize s/w rfkill */
40b130a9
VT		 1644 error = ath_init_sw_rfkill(sc);
1645 if (error)
1646 goto error_attach;
500c064d
VT		 1647#endif
1648
0e2dedf9 1649 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1650 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1651 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1652
db93e7b5 1653 error = ieee80211_register_hw(hw);
8feceb67 1654
3a702e49 1655 if (!ath_is_world_regd(reg)) {
c02cf373 1656 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1657 if (error)
1658 goto error_attach;
1659 }
5f8e077c 1660
db93e7b5
SB		 1661 /* Initialize LED control */
1662 ath_init_leds(sc);
8feceb67 1663
5f8e077c 1664
8feceb67 1665 return 0;
40b130a9
VT		 1666
1667error_attach:
1668 /* cleanup tx queues */
1669 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1670 if (ATH_TXQ_SETUP(sc, i))
1671 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1672
1673 ath9k_hw_detach(sc->sc_ah);
1674 ath9k_exit_debug(sc);
1675
8feceb67 1676 return error;
f078f209
LR		 1677}
1678
ff37e337
S		 1679int ath_reset(struct ath_softc *sc, bool retry_tx)
1680{
cbe61d8a 1681 struct ath_hw *ah = sc->sc_ah;
030bb495 1682 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1683 int r;
ff37e337
S		 1684
1685 ath9k_hw_set_interrupts(ah, 0);
043a0405 1686 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1687 ath_stoprecv(sc);
1688 ath_flushrecv(sc);
1689
1690 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1691 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1692 if (r)
ff37e337 1693 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1694 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1695 spin_unlock_bh(&sc->sc_resetlock);
1696
1697 if (ath_startrecv(sc) != 0)
04bd4638 1698 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1699
1700 /*
1701 * We may be doing a reset in response to a request
1702 * that changes the channel so update any state that
1703 * might change as a result.
1704 */
ce111bad 1705 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1706
1707 ath_update_txpow(sc);
1708
1709 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1710 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1711
17d7904d 1712 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1713
1714 if (retry_tx) {
1715 int i;
1716 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1717 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1718 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1719 ath_txq_schedule(sc, &sc->tx.txq[i]);
1720 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1721 }
1722 }
1723 }
1724
ae8d2858 1725 return r;
ff37e337
S		 1726}
1727
1728/*
1729 * This function will allocate both the DMA descriptor structure, and the
1730 * buffers it contains. These are used to contain the descriptors used
1731 * by the system.
1732*/
1733int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1734 struct list_head *head, const char *name,
1735 int nbuf, int ndesc)
1736{
1737#define DS2PHYS(_dd, _ds) \
1738 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1739#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1740#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1741
1742 struct ath_desc *ds;
1743 struct ath_buf *bf;
1744 int i, bsize, error;
1745
04bd4638
S		 1746 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1747 name, nbuf, ndesc);
ff37e337 1748
b03a9db9 1749 INIT_LIST_HEAD(head);
ff37e337
S		 1750 /* ath_desc must be a multiple of DWORDs */
1751 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1752 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1753 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1754 error = -ENOMEM;
1755 goto fail;
1756 }
1757
ff37e337
S		 1758 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1759
1760 /*
1761 * Need additional DMA memory because we can't use
1762 * descriptors that cross the 4K page boundary. Assume
1763 * one skipped descriptor per 4K page.
1764 */
2660b81a 1765 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1766 u32 ndesc_skipped =
1767 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1768 u32 dma_len;
1769
1770 while (ndesc_skipped) {
1771 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1772 dd->dd_desc_len += dma_len;
1773
1774 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1775 };
1776 }
1777
1778 /* allocate descriptors */
7da3c55c 1779 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1780 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1781 if (dd->dd_desc == NULL) {
1782 error = -ENOMEM;
1783 goto fail;
1784 }
1785 ds = dd->dd_desc;
04bd4638 1786 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1787 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1788 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1789
1790 /* allocate buffers */
1791 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1792 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1793 if (bf == NULL) {
1794 error = -ENOMEM;
1795 goto fail2;
1796 }
ff37e337
S		 1797 dd->dd_bufptr = bf;
1798
ff37e337
S		 1799 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1800 bf->bf_desc = ds;
1801 bf->bf_daddr = DS2PHYS(dd, ds);
1802
2660b81a 1803 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1804 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1805 /*
1806 * Skip descriptor addresses which can cause 4KB
1807 * boundary crossing (addr + length) with a 32 dword
1808 * descriptor fetch.
1809 */
1810 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1811 ASSERT((caddr_t) bf->bf_desc <
1812 ((caddr_t) dd->dd_desc +
1813 dd->dd_desc_len));
1814
1815 ds += ndesc;
1816 bf->bf_desc = ds;
1817 bf->bf_daddr = DS2PHYS(dd, ds);
1818 }
1819 }
1820 list_add_tail(&bf->list, head);
1821 }
1822 return 0;
1823fail2:
7da3c55c
GJ		 1824 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1825 dd->dd_desc_paddr);
ff37e337
S		 1826fail:
1827 memset(dd, 0, sizeof(*dd));
1828 return error;
1829#undef ATH_DESC_4KB_BOUND_CHECK
1830#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1831#undef DS2PHYS
1832}
1833
1834void ath_descdma_cleanup(struct ath_softc *sc,
1835 struct ath_descdma *dd,
1836 struct list_head *head)
1837{
7da3c55c
GJ		 1838 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1839 dd->dd_desc_paddr);
ff37e337
S		 1840
1841 INIT_LIST_HEAD(head);
1842 kfree(dd->dd_bufptr);
1843 memset(dd, 0, sizeof(*dd));
1844}
1845
1846int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1847{
1848 int qnum;
1849
1850 switch (queue) {
1851 case 0:
b77f483f 1852 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1853 break;
1854 case 1:
b77f483f 1855 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1856 break;
1857 case 2:
b77f483f 1858 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1859 break;
1860 case 3:
b77f483f 1861 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1862 break;
1863 default:
b77f483f 1864 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1865 break;
1866 }
1867
1868 return qnum;
1869}
1870
1871int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1872{
1873 int qnum;
1874
1875 switch (queue) {
1876 case ATH9K_WME_AC_VO:
1877 qnum = 0;
1878 break;
1879 case ATH9K_WME_AC_VI:
1880 qnum = 1;
1881 break;
1882 case ATH9K_WME_AC_BE:
1883 qnum = 2;
1884 break;
1885 case ATH9K_WME_AC_BK:
1886 qnum = 3;
1887 break;
1888 default:
1889 qnum = -1;
1890 break;
1891 }
1892
1893 return qnum;
1894}
1895
5f8e077c
LR		 1896/* XXX: Remove me once we don't depend on ath9k_channel for all
1897 * this redundant data */
0e2dedf9
JM		 1898void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1899 struct ath9k_channel *ichan)
5f8e077c 1900{
5f8e077c
LR		 1901 struct ieee80211_channel *chan = hw->conf.channel;
1902 struct ieee80211_conf *conf = &hw->conf;
1903
1904 ichan->channel = chan->center_freq;
1905 ichan->chan = chan;
1906
1907 if (chan->band == IEEE80211_BAND_2GHZ) {
1908 ichan->chanmode = CHANNEL_G;
1909 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1910 } else {
1911 ichan->chanmode = CHANNEL_A;
1912 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1913 }
1914
1915 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1916
1917 if (conf_is_ht(conf)) {
1918 if (conf_is_ht40(conf))
1919 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1920
1921 ichan->chanmode = ath_get_extchanmode(sc, chan,
1922 conf->channel_type);
1923 }
1924}
1925
ff37e337
S		 1926/**********************/
1927/* mac80211 callbacks */
1928/**********************/
1929
8feceb67 1930static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1931{
bce048d7
JM		 1932 struct ath_wiphy *aphy = hw->priv;
1933 struct ath_softc *sc = aphy->sc;
8feceb67 1934 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1935 struct ath9k_channel *init_channel;
82880a7c 1936 int r;
f078f209 1937
04bd4638
S		 1938 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1939 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1940
141b38b6
S		 1941 mutex_lock(&sc->mutex);
1942
9580a222
JM		 1943 if (ath9k_wiphy_started(sc)) {
1944 if (sc->chan_idx == curchan->hw_value) {
1945 /*
1946 * Already on the operational channel, the new wiphy
1947 * can be marked active.
1948 */
1949 aphy->state = ATH_WIPHY_ACTIVE;
1950 ieee80211_wake_queues(hw);
1951 } else {
1952 /*
1953 * Another wiphy is on another channel, start the new
1954 * wiphy in paused state.
1955 */
1956 aphy->state = ATH_WIPHY_PAUSED;
1957 ieee80211_stop_queues(hw);
1958 }
1959 mutex_unlock(&sc->mutex);
1960 return 0;
1961 }
1962 aphy->state = ATH_WIPHY_ACTIVE;
1963
8feceb67 1964 /* setup initial channel */
f078f209 1965
82880a7c 1966 sc->chan_idx = curchan->hw_value;
f078f209 1967
82880a7c 1968 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 1969
1970 /* Reset SERDES registers */
1971 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1972
1973 /*
1974 * The basic interface to setting the hardware in a good
1975 * state is ``reset''. On return the hardware is known to
1976 * be powered up and with interrupts disabled. This must
1977 * be followed by initialization of the appropriate bits
1978 * and then setup of the interrupt mask.
1979 */
1980 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1981 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1982 if (r) {
ff37e337 1983 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1984 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 1985 "(freq %u MHz)\n", r,
1986 curchan->center_freq);
ff37e337 1987 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1988 goto mutex_unlock;
ff37e337
S		 1989 }
1990 spin_unlock_bh(&sc->sc_resetlock);
1991
1992 /*
1993 * This is needed only to setup initial state
1994 * but it's best done after a reset.
1995 */
1996 ath_update_txpow(sc);
8feceb67 1997
ff37e337
S		 1998 /*
1999 * Setup the hardware after reset:
2000 * The receive engine is set going.
2001 * Frame transmit is handled entirely
2002 * in the frame output path; there's nothing to do
2003 * here except setup the interrupt mask.
2004 */
2005 if (ath_startrecv(sc) != 0) {
1ffb0610 2006 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 2007 r = -EIO;
2008 goto mutex_unlock;
f078f209 2009 }
8feceb67 2010
ff37e337 2011 /* Setup our intr mask. */
17d7904d 2012 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2013 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2014 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2015
2660b81a 2016 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2017 sc->imask |= ATH9K_INT_GTT;
ff37e337 2018
2660b81a 2019 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2020 sc->imask |= ATH9K_INT_CST;
ff37e337 2021
ce111bad 2022 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2023
2024 sc->sc_flags &= ~SC_OP_INVALID;
2025
2026 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2027 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2028 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 2029
bce048d7 2030 ieee80211_wake_queues(hw);
ff37e337 2031
e97275cb 2032#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2033 r = ath_start_rfkill_poll(sc);
500c064d 2034#endif
141b38b6
S		 2035
2036mutex_unlock:
2037 mutex_unlock(&sc->mutex);
2038
ae8d2858 2039 return r;
f078f209
LR		 2040}
2041
8feceb67
VT		 2042static int ath9k_tx(struct ieee80211_hw *hw,
2043 struct sk_buff *skb)
f078f209 2044{
528f0c6b 2045 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2046 struct ath_wiphy *aphy = hw->priv;
2047 struct ath_softc *sc = aphy->sc;
528f0c6b 2048 struct ath_tx_control txctl;
8feceb67 2049 int hdrlen, padsize;
528f0c6b 2050
8089cc47 2051 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2052 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2053 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2054 goto exit;
2055 }
2056
dc8c4585
JM		 2057 if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
2058 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2059 /*
2060 * mac80211 does not set PM field for normal data frames, so we
2061 * need to update that based on the current PS mode.
2062 */
2063 if (ieee80211_is_data(hdr->frame_control) &&
2064 !ieee80211_is_nullfunc(hdr->frame_control) &&
2065 !ieee80211_has_pm(hdr->frame_control)) {
2066 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2067 "while in PS mode\n");
2068 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2069 }
2070 }
2071
9a23f9ca
JM		 2072 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2073 /*
2074 * We are using PS-Poll and mac80211 can request TX while in
2075 * power save mode. Need to wake up hardware for the TX to be
2076 * completed and if needed, also for RX of buffered frames.
2077 */
2078 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2079 ath9k_ps_wakeup(sc);
2080 ath9k_hw_setrxabort(sc->sc_ah, 0);
2081 if (ieee80211_is_pspoll(hdr->frame_control)) {
2082 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2083 "buffered frame\n");
2084 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2085 } else {
2086 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2087 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2088 }
2089 /*
2090 * The actual restore operation will happen only after
2091 * the sc_flags bit is cleared. We are just dropping
2092 * the ps_usecount here.
2093 */
2094 ath9k_ps_restore(sc);
2095 }
2096
528f0c6b 2097 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2098
8feceb67
VT		 2099 /*
2100 * As a temporary workaround, assign seq# here; this will likely need
2101 * to be cleaned up to work better with Beacon transmission and virtual
2102 * BSSes.
2103 */
2104 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2105 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2106 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2107 sc->tx.seq_no += 0x10;
8feceb67 2108 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2109 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2110 }
f078f209 2111
8feceb67
VT		 2112 /* Add the padding after the header if this is not already done */
2113 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2114 if (hdrlen & 3) {
2115 padsize = hdrlen % 4;
2116 if (skb_headroom(skb) < padsize)
2117 return -1;
2118 skb_push(skb, padsize);
2119 memmove(skb->data, skb->data + padsize, hdrlen);
2120 }
2121
528f0c6b
S		 2122 /* Check if a tx queue is available */
2123
2124 txctl.txq = ath_test_get_txq(sc, skb);
2125 if (!txctl.txq)
2126 goto exit;
2127
04bd4638 2128 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2129
c52f33d0 2130 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2131 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2132 goto exit;
8feceb67
VT		 2133 }
2134
528f0c6b
S		 2135 return 0;
2136exit:
2137 dev_kfree_skb_any(skb);
8feceb67 2138 return 0;
f078f209
LR		 2139}
2140
8feceb67 2141static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2142{
bce048d7
JM		 2143 struct ath_wiphy *aphy = hw->priv;
2144 struct ath_softc *sc = aphy->sc;
f078f209 2145
9580a222
JM		 2146 aphy->state = ATH_WIPHY_INACTIVE;
2147
9c84b797 2148 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2149 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2150 return;
2151 }
8feceb67 2152
141b38b6 2153 mutex_lock(&sc->mutex);
ff37e337 2154
bce048d7 2155 ieee80211_stop_queues(hw);
ff37e337 2156
9580a222
JM		 2157 if (ath9k_wiphy_started(sc)) {
2158 mutex_unlock(&sc->mutex);
2159 return; /* another wiphy still in use */
2160 }
2161
ff37e337
S		 2162 /* make sure h/w will not generate any interrupt
2163 * before setting the invalid flag. */
2164 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2165
2166 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2167 ath_drain_all_txq(sc, false);
ff37e337
S		 2168 ath_stoprecv(sc);
2169 ath9k_hw_phy_disable(sc->sc_ah);
2170 } else
b77f483f 2171 sc->rx.rxlink = NULL;
ff37e337 2172
19d337df
JB		 2173 rfkill_pause_polling(sc->rf_kill.rfkill);
2174
ff37e337
S		 2175 /* disable HAL and put h/w to sleep */
2176 ath9k_hw_disable(sc->sc_ah);
2177 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2178
2179 sc->sc_flags |= SC_OP_INVALID;
500c064d 2180
141b38b6
S		 2181 mutex_unlock(&sc->mutex);
2182
04bd4638 2183 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2184}
2185
8feceb67
VT		 2186static int ath9k_add_interface(struct ieee80211_hw *hw,
2187 struct ieee80211_if_init_conf *conf)
f078f209 2188{
bce048d7
JM		 2189 struct ath_wiphy *aphy = hw->priv;
2190 struct ath_softc *sc = aphy->sc;
17d7904d 2191 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2192 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2193 int ret = 0;
8feceb67 2194
141b38b6
S		 2195 mutex_lock(&sc->mutex);
2196
8ca21f01
JM		 2197 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2198 sc->nvifs > 0) {
2199 ret = -ENOBUFS;
2200 goto out;
2201 }
2202
8feceb67 2203 switch (conf->type) {
05c914fe 2204 case NL80211_IFTYPE_STATION:
d97809db 2205 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2206 break;
05c914fe 2207 case NL80211_IFTYPE_ADHOC:
05c914fe 2208 case NL80211_IFTYPE_AP:
9cb5412b 2209 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2210 if (sc->nbcnvifs >= ATH_BCBUF) {
2211 ret = -ENOBUFS;
2212 goto out;
2213 }
9cb5412b 2214 ic_opmode = conf->type;
f078f209
LR		 2215 break;
2216 default:
2217 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2218 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2219 ret = -EOPNOTSUPP;
2220 goto out;
f078f209
LR		 2221 }
2222
17d7904d 2223 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2224
17d7904d 2225 /* Set the VIF opmode */
5640b08e
S		 2226 avp->av_opmode = ic_opmode;
2227 avp->av_bslot = -1;
2228
2c3db3d5 2229 sc->nvifs++;
8ca21f01
JM		 2230
2231 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2232 ath9k_set_bssid_mask(hw);
2233
2c3db3d5
JM		 2234 if (sc->nvifs > 1)
2235 goto out; /* skip global settings for secondary vif */
2236
b238e90e 2237 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2238 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2239 sc->sc_flags |= SC_OP_TSF_RESET;
2240 }
5640b08e 2241
5640b08e 2242 /* Set the device opmode */
2660b81a 2243 sc->sc_ah->opmode = ic_opmode;
5640b08e 2244
4e30ffa2
VN		 2245 /*
2246 * Enable MIB interrupts when there are hardware phy counters.
2247 * Note we only do this (at the moment) for station mode.
2248 */
4af9cf4f 2249 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2250 (conf->type == NL80211_IFTYPE_ADHOC) ||
2251 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2252 if (ath9k_hw_phycounters(sc->sc_ah))
2253 sc->imask |= ATH9K_INT_MIB;
2254 sc->imask |= ATH9K_INT_TSFOOR;
2255 }
2256
17d7904d 2257 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2258
415f738e
S		 2259 if (conf->type == NL80211_IFTYPE_AP)
2260 ath_start_ani(sc);
6f255425 2261
2c3db3d5 2262out:
141b38b6 2263 mutex_unlock(&sc->mutex);
2c3db3d5 2264 return ret;
f078f209
LR		 2265}
2266
8feceb67
VT		 2267static void ath9k_remove_interface(struct ieee80211_hw *hw,
2268 struct ieee80211_if_init_conf *conf)
f078f209 2269{
bce048d7
JM		 2270 struct ath_wiphy *aphy = hw->priv;
2271 struct ath_softc *sc = aphy->sc;
17d7904d 2272 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2273 int i;
f078f209 2274
04bd4638 2275 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2276
141b38b6
S		 2277 mutex_lock(&sc->mutex);
2278
6f255425 2279 /* Stop ANI */
17d7904d 2280 del_timer_sync(&sc->ani.timer);
580f0b8a 2281
8feceb67 2282 /* Reclaim beacon resources */
9cb5412b
PE		 2283 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2284 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2285 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2286 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2287 ath_beacon_return(sc, avp);
580f0b8a 2288 }
f078f209 2289
8feceb67 2290 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2291
2c3db3d5
JM		 2292 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2293 if (sc->beacon.bslot[i] == conf->vif) {
2294 printk(KERN_DEBUG "%s: vif had allocated beacon "
2295 "slot\n", __func__);
2296 sc->beacon.bslot[i] = NULL;
c52f33d0 2297 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2298 }
2299 }
2300
17d7904d 2301 sc->nvifs--;
141b38b6
S		 2302
2303 mutex_unlock(&sc->mutex);
f078f209
LR		 2304}
2305
e8975581 2306static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2307{
bce048d7
JM		 2308 struct ath_wiphy *aphy = hw->priv;
2309 struct ath_softc *sc = aphy->sc;
e8975581 2310 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2311 struct ath_hw *ah = sc->sc_ah;
f078f209 2312
aa33de09 2313 mutex_lock(&sc->mutex);
141b38b6 2314
3cbb5dd7
VN		 2315 if (changed & IEEE80211_CONF_CHANGE_PS) {
2316 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2317 if (!(ah->caps.hw_caps &
2318 ATH9K_HW_CAP_AUTOSLEEP)) {
2319 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2320 sc->imask |= ATH9K_INT_TIM_TIMER;
2321 ath9k_hw_set_interrupts(sc->sc_ah,
2322 sc->imask);
2323 }
2324 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2325 }
3cbb5dd7
VN		 2326 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2327 } else {
2328 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2329 if (!(ah->caps.hw_caps &
2330 ATH9K_HW_CAP_AUTOSLEEP)) {
2331 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2332 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2333 SC_OP_WAIT_FOR_CAB |
2334 SC_OP_WAIT_FOR_PSPOLL_DATA |
2335 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2336 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2337 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2338 ath9k_hw_set_interrupts(sc->sc_ah,
2339 sc->imask);
2340 }
3cbb5dd7
VN		 2341 }
2342 }
2343 }
2344
4797938c 2345 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2346 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2347 int pos = curchan->hw_value;
ae5eb026 2348
0e2dedf9
JM		 2349 aphy->chan_idx = pos;
2350 aphy->chan_is_ht = conf_is_ht(conf);
2351
8089cc47
JM		 2352 if (aphy->state == ATH_WIPHY_SCAN ||
2353 aphy->state == ATH_WIPHY_ACTIVE)
2354 ath9k_wiphy_pause_all_forced(sc, aphy);
2355 else {
2356 /*
2357 * Do not change operational channel based on a paused
2358 * wiphy changes.
2359 */
2360 goto skip_chan_change;
2361 }
0e2dedf9 2362
04bd4638
S		 2363 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2364 curchan->center_freq);
f078f209 2365
5f8e077c 2366 /* XXX: remove me eventualy */
0e2dedf9 2367 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2368
ecf70441 2369 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2370
0e2dedf9 2371 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2372 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2373 mutex_unlock(&sc->mutex);
e11602b7
S		 2374 return -EINVAL;
2375 }
094d05dc 2376 }
f078f209 2377
8089cc47 2378skip_chan_change:
5c020dc6 2379 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2380 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2381
aa33de09 2382 mutex_unlock(&sc->mutex);
141b38b6 2383
f078f209
LR		 2384 return 0;
2385}
2386
8feceb67
VT		 2387#define SUPPORTED_FILTERS \
2388 (FIF_PROMISC_IN_BSS | \
2389 FIF_ALLMULTI | \
2390 FIF_CONTROL | \
2391 FIF_OTHER_BSS | \
2392 FIF_BCN_PRBRESP_PROMISC | \
2393 FIF_FCSFAIL)
c83be688 2394
8feceb67
VT		 2395/* FIXME: sc->sc_full_reset ? */
2396static void ath9k_configure_filter(struct ieee80211_hw *hw,
2397 unsigned int changed_flags,
2398 unsigned int *total_flags,
2399 int mc_count,
2400 struct dev_mc_list *mclist)
2401{
bce048d7
JM		 2402 struct ath_wiphy *aphy = hw->priv;
2403 struct ath_softc *sc = aphy->sc;
8feceb67 2404 u32 rfilt;
f078f209 2405
8feceb67
VT		 2406 changed_flags &= SUPPORTED_FILTERS;
2407 *total_flags &= SUPPORTED_FILTERS;
f078f209 2408
b77f483f 2409 sc->rx.rxfilter = *total_flags;
aa68aeaa 2410 ath9k_ps_wakeup(sc);
8feceb67
VT		 2411 rfilt = ath_calcrxfilter(sc);
2412 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2413 ath9k_ps_restore(sc);
f078f209 2414
b77f483f 2415 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2416}
f078f209 2417
8feceb67
VT		 2418static void ath9k_sta_notify(struct ieee80211_hw *hw,
2419 struct ieee80211_vif *vif,
2420 enum sta_notify_cmd cmd,
17741cdc 2421 struct ieee80211_sta *sta)
8feceb67 2422{
bce048d7
JM		 2423 struct ath_wiphy *aphy = hw->priv;
2424 struct ath_softc *sc = aphy->sc;
f078f209 2425
8feceb67
VT		 2426 switch (cmd) {
2427 case STA_NOTIFY_ADD:
5640b08e 2428 ath_node_attach(sc, sta);
8feceb67
VT		 2429 break;
2430 case STA_NOTIFY_REMOVE:
b5aa9bf9 2431 ath_node_detach(sc, sta);
8feceb67
VT		 2432 break;
2433 default:
2434 break;
2435 }
f078f209
LR		 2436}
2437
141b38b6 2438static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2439 const struct ieee80211_tx_queue_params *params)
f078f209 2440{
bce048d7
JM		 2441 struct ath_wiphy *aphy = hw->priv;
2442 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2443 struct ath9k_tx_queue_info qi;
2444 int ret = 0, qnum;
f078f209 2445
8feceb67
VT		 2446 if (queue >= WME_NUM_AC)
2447 return 0;
f078f209 2448
141b38b6
S		 2449 mutex_lock(&sc->mutex);
2450
1ffb0610
S		 2451 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2452
8feceb67
VT		 2453 qi.tqi_aifs = params->aifs;
2454 qi.tqi_cwmin = params->cw_min;
2455 qi.tqi_cwmax = params->cw_max;
2456 qi.tqi_burstTime = params->txop;
2457 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2458
8feceb67 2459 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2460 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2461 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2462 queue, qnum, params->aifs, params->cw_min,
2463 params->cw_max, params->txop);
f078f209 2464
8feceb67
VT		 2465 ret = ath_txq_update(sc, qnum, &qi);
2466 if (ret)
04bd4638 2467 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2468
141b38b6
S		 2469 mutex_unlock(&sc->mutex);
2470
8feceb67
VT		 2471 return ret;
2472}
f078f209 2473
8feceb67
VT		 2474static int ath9k_set_key(struct ieee80211_hw *hw,
2475 enum set_key_cmd cmd,
dc822b5d
JB		 2476 struct ieee80211_vif *vif,
2477 struct ieee80211_sta *sta,
8feceb67
VT		 2478 struct ieee80211_key_conf *key)
2479{
bce048d7
JM		 2480 struct ath_wiphy *aphy = hw->priv;
2481 struct ath_softc *sc = aphy->sc;
8feceb67 2482 int ret = 0;
f078f209 2483
b3bd89ce
JM		 2484 if (modparam_nohwcrypt)
2485 return -ENOSPC;
2486
141b38b6 2487 mutex_lock(&sc->mutex);
3cbb5dd7 2488 ath9k_ps_wakeup(sc);
d8baa939 2489 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2490
8feceb67
VT		 2491 switch (cmd) {
2492 case SET_KEY:
3f53dd64 2493 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2494 if (ret >= 0) {
2495 key->hw_key_idx = ret;
8feceb67
VT		 2496 /* push IV and Michael MIC generation to stack */
2497 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2498 if (key->alg == ALG_TKIP)
2499 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2500 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2501 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2502 ret = 0;
8feceb67
VT		 2503 }
2504 break;
2505 case DISABLE_KEY:
2506 ath_key_delete(sc, key);
8feceb67
VT		 2507 break;
2508 default:
2509 ret = -EINVAL;
2510 }
f078f209 2511
3cbb5dd7 2512 ath9k_ps_restore(sc);
141b38b6
S		 2513 mutex_unlock(&sc->mutex);
2514
8feceb67
VT		 2515 return ret;
2516}
f078f209 2517
8feceb67
VT		 2518static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2519 struct ieee80211_vif *vif,
2520 struct ieee80211_bss_conf *bss_conf,
2521 u32 changed)
2522{
bce048d7
JM		 2523 struct ath_wiphy *aphy = hw->priv;
2524 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2525 struct ath_hw *ah = sc->sc_ah;
2526 struct ath_vif *avp = (void *)vif->drv_priv;
2527 u32 rfilt = 0;
2528 int error, i;
f078f209 2529
141b38b6
S		 2530 mutex_lock(&sc->mutex);
2531
2d0ddec5
JB		 2532 /*
2533 * TODO: Need to decide which hw opmode to use for
2534 * multi-interface cases
2535 * XXX: This belongs into add_interface!
2536 */
2537 if (vif->type == NL80211_IFTYPE_AP &&
2538 ah->opmode != NL80211_IFTYPE_AP) {
2539 ah->opmode = NL80211_IFTYPE_STATION;
2540 ath9k_hw_setopmode(ah);
2541 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2542 sc->curaid = 0;
2543 ath9k_hw_write_associd(sc);
2544 /* Request full reset to get hw opmode changed properly */
2545 sc->sc_flags |= SC_OP_FULL_RESET;
2546 }
2547
2548 if ((changed & BSS_CHANGED_BSSID) &&
2549 !is_zero_ether_addr(bss_conf->bssid)) {
2550 switch (vif->type) {
2551 case NL80211_IFTYPE_STATION:
2552 case NL80211_IFTYPE_ADHOC:
2553 case NL80211_IFTYPE_MESH_POINT:
2554 /* Set BSSID */
2555 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2556 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2557 sc->curaid = 0;
2558 ath9k_hw_write_associd(sc);
2559
2560 /* Set aggregation protection mode parameters */
2561 sc->config.ath_aggr_prot = 0;
2562
2563 DPRINTF(sc, ATH_DBG_CONFIG,
2564 "RX filter 0x%x bssid %pM aid 0x%x\n",
2565 rfilt, sc->curbssid, sc->curaid);
2566
2567 /* need to reconfigure the beacon */
2568 sc->sc_flags &= ~SC_OP_BEACONS ;
2569
2570 break;
2571 default:
2572 break;
2573 }
2574 }
2575
2576 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2577 (vif->type == NL80211_IFTYPE_AP) ||
2578 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2579 if ((changed & BSS_CHANGED_BEACON) ||
2580 (changed & BSS_CHANGED_BEACON_ENABLED &&
2581 bss_conf->enable_beacon)) {
2582 /*
2583 * Allocate and setup the beacon frame.
2584 *
2585 * Stop any previous beacon DMA. This may be
2586 * necessary, for example, when an ibss merge
2587 * causes reconfiguration; we may be called
2588 * with beacon transmission active.
2589 */
2590 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2591
2592 error = ath_beacon_alloc(aphy, vif);
2593 if (!error)
2594 ath_beacon_config(sc, vif);
2595 }
2596 }
2597
2598 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2599 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2600 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2601 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2602 ath9k_hw_keysetmac(sc->sc_ah,
2603 (u16)i,
2604 sc->curbssid);
2605 }
2606
2607 /* Only legacy IBSS for now */
2608 if (vif->type == NL80211_IFTYPE_ADHOC)
2609 ath_update_chainmask(sc, 0);
2610
8feceb67 2611 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2612 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2613 bss_conf->use_short_preamble);
2614 if (bss_conf->use_short_preamble)
2615 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2616 else
2617 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2618 }
f078f209 2619
8feceb67 2620 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2621 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2622 bss_conf->use_cts_prot);
2623 if (bss_conf->use_cts_prot &&
2624 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2625 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2626 else
2627 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2628 }
f078f209 2629
8feceb67 2630 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2631 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2632 bss_conf->assoc);
5640b08e 2633 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2634 }
141b38b6 2635
57c4d7b4
JB		 2636 /*
2637 * The HW TSF has to be reset when the beacon interval changes.
2638 * We set the flag here, and ath_beacon_config_ap() would take this
2639 * into account when it gets called through the subsequent
2640 * config_interface() call - with IFCC_BEACON in the changed field.
2641 */
2642
2643 if (changed & BSS_CHANGED_BEACON_INT) {
2644 sc->sc_flags |= SC_OP_TSF_RESET;
2645 sc->beacon_interval = bss_conf->beacon_int;
2646 }
2647
141b38b6 2648 mutex_unlock(&sc->mutex);
8feceb67 2649}
f078f209 2650
8feceb67
VT		 2651static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2652{
2653 u64 tsf;
bce048d7
JM		 2654 struct ath_wiphy *aphy = hw->priv;
2655 struct ath_softc *sc = aphy->sc;
f078f209 2656
141b38b6
S		 2657 mutex_lock(&sc->mutex);
2658 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2659 mutex_unlock(&sc->mutex);
f078f209 2660
8feceb67
VT		 2661 return tsf;
2662}
f078f209 2663
3b5d665b
AF		 2664static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2665{
bce048d7
JM		 2666 struct ath_wiphy *aphy = hw->priv;
2667 struct ath_softc *sc = aphy->sc;
3b5d665b 2668
141b38b6
S		 2669 mutex_lock(&sc->mutex);
2670 ath9k_hw_settsf64(sc->sc_ah, tsf);
2671 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2672}
2673
8feceb67
VT		 2674static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2675{
bce048d7
JM		 2676 struct ath_wiphy *aphy = hw->priv;
2677 struct ath_softc *sc = aphy->sc;
c83be688 2678
141b38b6
S		 2679 mutex_lock(&sc->mutex);
2680 ath9k_hw_reset_tsf(sc->sc_ah);
2681 mutex_unlock(&sc->mutex);
8feceb67 2682}
f078f209 2683
8feceb67 2684static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2685 enum ieee80211_ampdu_mlme_action action,
2686 struct ieee80211_sta *sta,
2687 u16 tid, u16 *ssn)
8feceb67 2688{
bce048d7
JM		 2689 struct ath_wiphy *aphy = hw->priv;
2690 struct ath_softc *sc = aphy->sc;
8feceb67 2691 int ret = 0;
f078f209 2692
8feceb67
VT		 2693 switch (action) {
2694 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2695 if (!(sc->sc_flags & SC_OP_RXAGGR))
2696 ret = -ENOTSUPP;
8feceb67
VT		 2697 break;
2698 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2699 break;
2700 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2701 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2702 if (ret < 0)
2703 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2704 "Unable to start TX aggregation\n");
8feceb67 2705 else
17741cdc 2706 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2707 break;
2708 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2709 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2710 if (ret < 0)
2711 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2712 "Unable to stop TX aggregation\n");
f078f209 2713
17741cdc 2714 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2715 break;
b1720231 2716 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2717 ath_tx_aggr_resume(sc, sta, tid);
2718 break;
8feceb67 2719 default:
04bd4638 2720 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2721 }
2722
2723 return ret;
f078f209
LR		 2724}
2725
0c98de65
S		 2726static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2727{
bce048d7
JM		 2728 struct ath_wiphy *aphy = hw->priv;
2729 struct ath_softc *sc = aphy->sc;
0c98de65 2730
8089cc47
JM		 2731 if (ath9k_wiphy_scanning(sc)) {
2732 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2733 "same time\n");
2734 /*
2735 * Do not allow the concurrent scanning state for now. This
2736 * could be improved with scanning control moved into ath9k.
2737 */
2738 return;
2739 }
2740
2741 aphy->state = ATH_WIPHY_SCAN;
2742 ath9k_wiphy_pause_all_forced(sc, aphy);
2743
0c98de65
S		 2744 mutex_lock(&sc->mutex);
2745 sc->sc_flags |= SC_OP_SCANNING;
2746 mutex_unlock(&sc->mutex);
2747}
2748
2749static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2750{
bce048d7
JM		 2751 struct ath_wiphy *aphy = hw->priv;
2752 struct ath_softc *sc = aphy->sc;
0c98de65
S		 2753
2754 mutex_lock(&sc->mutex);
8089cc47 2755 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2756 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2757 sc->sc_flags |= SC_OP_FULL_RESET;
0c98de65
S		 2758 mutex_unlock(&sc->mutex);
2759}
2760
6baff7f9 2761struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2762 .tx = ath9k_tx,
2763 .start = ath9k_start,
2764 .stop = ath9k_stop,
2765 .add_interface = ath9k_add_interface,
2766 .remove_interface = ath9k_remove_interface,
2767 .config = ath9k_config,
8feceb67 2768 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2769 .sta_notify = ath9k_sta_notify,
2770 .conf_tx = ath9k_conf_tx,
8feceb67 2771 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2772 .set_key = ath9k_set_key,
8feceb67 2773 .get_tsf = ath9k_get_tsf,
3b5d665b 2774 .set_tsf = ath9k_set_tsf,
8feceb67 2775 .reset_tsf = ath9k_reset_tsf,
4233df6b 2776 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2777 .sw_scan_start = ath9k_sw_scan_start,
2778 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67
VT		 2779};
2780
392dff83
BP		 2781static struct {
2782 u32 version;
2783 const char * name;
2784} ath_mac_bb_names[] = {
2785 { AR_SREV_VERSION_5416_PCI, "5416" },
2786 { AR_SREV_VERSION_5416_PCIE, "5418" },
2787 { AR_SREV_VERSION_9100, "9100" },
2788 { AR_SREV_VERSION_9160, "9160" },
2789 { AR_SREV_VERSION_9280, "9280" },
2790 { AR_SREV_VERSION_9285, "9285" }
2791};
2792
2793static struct {
2794 u16 version;
2795 const char * name;
2796} ath_rf_names[] = {
2797 { 0, "5133" },
2798 { AR_RAD5133_SREV_MAJOR, "5133" },
2799 { AR_RAD5122_SREV_MAJOR, "5122" },
2800 { AR_RAD2133_SREV_MAJOR, "2133" },
2801 { AR_RAD2122_SREV_MAJOR, "2122" }
2802};
2803
2804/*
2805 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2806 */
6baff7f9 2807const char *
392dff83
BP		 2808ath_mac_bb_name(u32 mac_bb_version)
2809{
2810 int i;
2811
2812 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2813 if (ath_mac_bb_names[i].version == mac_bb_version) {
2814 return ath_mac_bb_names[i].name;
2815 }
2816 }
2817
2818 return "????";
2819}
2820
2821/*
2822 * Return the RF name. "????" is returned if the RF is unknown.
2823 */
6baff7f9 2824const char *
392dff83
BP		 2825ath_rf_name(u16 rf_version)
2826{
2827 int i;
2828
2829 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2830 if (ath_rf_names[i].version == rf_version) {
2831 return ath_rf_names[i].name;
2832 }
2833 }
2834
2835 return "????";
2836}
2837
6baff7f9 2838static int __init ath9k_init(void)
f078f209 2839{
ca8a8560
VT		 2840 int error;
2841
ca8a8560
VT		 2842 /* Register rate control algorithm */
2843 error = ath_rate_control_register();
2844 if (error != 0) {
2845 printk(KERN_ERR
b51bb3cd
LR		 2846 "ath9k: Unable to register rate control "
2847 "algorithm: %d\n",
ca8a8560 2848 error);
6baff7f9 2849 goto err_out;
ca8a8560
VT		 2850 }
2851
19d8bc22
GJ		 2852 error = ath9k_debug_create_root();
2853 if (error) {
2854 printk(KERN_ERR
2855 "ath9k: Unable to create debugfs root: %d\n",
2856 error);
2857 goto err_rate_unregister;
2858 }
2859
6baff7f9
GJ		 2860 error = ath_pci_init();
2861 if (error < 0) {
f078f209 2862 printk(KERN_ERR
b51bb3cd 2863 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2864 error = -ENODEV;
19d8bc22 2865 goto err_remove_root;
f078f209
LR		 2866 }
2867
09329d37
GJ		 2868 error = ath_ahb_init();
2869 if (error < 0) {
2870 error = -ENODEV;
2871 goto err_pci_exit;
2872 }
2873
f078f209 2874 return 0;
6baff7f9 2875
09329d37
GJ		 2876 err_pci_exit:
2877 ath_pci_exit();
2878
19d8bc22
GJ		 2879 err_remove_root:
2880 ath9k_debug_remove_root();
6baff7f9
GJ		 2881 err_rate_unregister:
2882 ath_rate_control_unregister();
2883 err_out:
2884 return error;
f078f209 2885}
6baff7f9 2886module_init(ath9k_init);
f078f209 2887
6baff7f9 2888static void __exit ath9k_exit(void)
f078f209 2889{
09329d37 2890 ath_ahb_exit();
6baff7f9 2891 ath_pci_exit();
19d8bc22 2892 ath9k_debug_remove_root();
ca8a8560 2893 ath_rate_control_unregister();
04bd4638 2894 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2895}
6baff7f9 2896module_exit(ath9k_exit);
Linux 6.x block layer and io_uring tree(s)