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nl80211: report age of scan results
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
f078f209
LR		 21static char *dev_info = "ath9k";
22
23MODULE_AUTHOR("Atheros Communications");
24MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26MODULE_LICENSE("Dual BSD/GPL");
27
b3bd89ce
JM		 28static int modparam_nohwcrypt;
29module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
5f8e077c
LR		 32/* We use the hw_value as an index into our private channel structure */
33
34#define CHAN2G(_freq, _idx) { \
35 .center_freq = (_freq), \
36 .hw_value = (_idx), \
eeddfd9d 37 .max_power = 20, \
5f8e077c
LR		 38}
39
40#define CHAN5G(_freq, _idx) { \
41 .band = IEEE80211_BAND_5GHZ, \
42 .center_freq = (_freq), \
43 .hw_value = (_idx), \
eeddfd9d 44 .max_power = 20, \
5f8e077c
LR		 45}
46
47/* Some 2 GHz radios are actually tunable on 2312-2732
48 * on 5 MHz steps, we support the channels which we know
49 * we have calibration data for all cards though to make
50 * this static */
51static struct ieee80211_channel ath9k_2ghz_chantable[] = {
52 CHAN2G(2412, 0), /* Channel 1 */
53 CHAN2G(2417, 1), /* Channel 2 */
54 CHAN2G(2422, 2), /* Channel 3 */
55 CHAN2G(2427, 3), /* Channel 4 */
56 CHAN2G(2432, 4), /* Channel 5 */
57 CHAN2G(2437, 5), /* Channel 6 */
58 CHAN2G(2442, 6), /* Channel 7 */
59 CHAN2G(2447, 7), /* Channel 8 */
60 CHAN2G(2452, 8), /* Channel 9 */
61 CHAN2G(2457, 9), /* Channel 10 */
62 CHAN2G(2462, 10), /* Channel 11 */
63 CHAN2G(2467, 11), /* Channel 12 */
64 CHAN2G(2472, 12), /* Channel 13 */
65 CHAN2G(2484, 13), /* Channel 14 */
66};
67
68/* Some 5 GHz radios are actually tunable on XXXX-YYYY
69 * on 5 MHz steps, we support the channels which we know
70 * we have calibration data for all cards though to make
71 * this static */
72static struct ieee80211_channel ath9k_5ghz_chantable[] = {
73 /* _We_ call this UNII 1 */
74 CHAN5G(5180, 14), /* Channel 36 */
75 CHAN5G(5200, 15), /* Channel 40 */
76 CHAN5G(5220, 16), /* Channel 44 */
77 CHAN5G(5240, 17), /* Channel 48 */
78 /* _We_ call this UNII 2 */
79 CHAN5G(5260, 18), /* Channel 52 */
80 CHAN5G(5280, 19), /* Channel 56 */
81 CHAN5G(5300, 20), /* Channel 60 */
82 CHAN5G(5320, 21), /* Channel 64 */
83 /* _We_ call this "Middle band" */
84 CHAN5G(5500, 22), /* Channel 100 */
85 CHAN5G(5520, 23), /* Channel 104 */
86 CHAN5G(5540, 24), /* Channel 108 */
87 CHAN5G(5560, 25), /* Channel 112 */
88 CHAN5G(5580, 26), /* Channel 116 */
89 CHAN5G(5600, 27), /* Channel 120 */
90 CHAN5G(5620, 28), /* Channel 124 */
91 CHAN5G(5640, 29), /* Channel 128 */
92 CHAN5G(5660, 30), /* Channel 132 */
93 CHAN5G(5680, 31), /* Channel 136 */
94 CHAN5G(5700, 32), /* Channel 140 */
95 /* _We_ call this UNII 3 */
96 CHAN5G(5745, 33), /* Channel 149 */
97 CHAN5G(5765, 34), /* Channel 153 */
98 CHAN5G(5785, 35), /* Channel 157 */
99 CHAN5G(5805, 36), /* Channel 161 */
100 CHAN5G(5825, 37), /* Channel 165 */
101};
102
ce111bad
LR		 103static void ath_cache_conf_rate(struct ath_softc *sc,
104 struct ieee80211_conf *conf)
ff37e337 105{
030bb495
LR		 106 switch (conf->channel->band) {
107 case IEEE80211_BAND_2GHZ:
108 if (conf_is_ht20(conf))
109 sc->cur_rate_table =
110 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
111 else if (conf_is_ht40_minus(conf))
112 sc->cur_rate_table =
113 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
114 else if (conf_is_ht40_plus(conf))
115 sc->cur_rate_table =
116 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 117 else
030bb495
LR		 118 sc->cur_rate_table =
119 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 120 break;
121 case IEEE80211_BAND_5GHZ:
122 if (conf_is_ht20(conf))
123 sc->cur_rate_table =
124 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
125 else if (conf_is_ht40_minus(conf))
126 sc->cur_rate_table =
127 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
128 else if (conf_is_ht40_plus(conf))
129 sc->cur_rate_table =
130 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
131 else
96742256
LR		 132 sc->cur_rate_table =
133 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 134 break;
135 default:
ce111bad 136 BUG_ON(1);
030bb495
LR		 137 break;
138 }
ff37e337
S		 139}
140
141static void ath_update_txpow(struct ath_softc *sc)
142{
cbe61d8a 143 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 144 u32 txpow;
145
17d7904d
S		 146 if (sc->curtxpow != sc->config.txpowlimit) {
147 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 148 /* read back in case value is clamped */
149 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 150 sc->curtxpow = txpow;
ff37e337
S		 151 }
152}
153
154static u8 parse_mpdudensity(u8 mpdudensity)
155{
156 /*
157 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
158 * 0 for no restriction
159 * 1 for 1/4 us
160 * 2 for 1/2 us
161 * 3 for 1 us
162 * 4 for 2 us
163 * 5 for 4 us
164 * 6 for 8 us
165 * 7 for 16 us
166 */
167 switch (mpdudensity) {
168 case 0:
169 return 0;
170 case 1:
171 case 2:
172 case 3:
173 /* Our lower layer calculations limit our precision to
174 1 microsecond */
175 return 1;
176 case 4:
177 return 2;
178 case 5:
179 return 4;
180 case 6:
181 return 8;
182 case 7:
183 return 16;
184 default:
185 return 0;
186 }
187}
188
189static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
190{
4f0fc7c3 191 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 192 struct ieee80211_supported_band *sband;
193 struct ieee80211_rate *rate;
194 int i, maxrates;
195
196 switch (band) {
197 case IEEE80211_BAND_2GHZ:
198 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
199 break;
200 case IEEE80211_BAND_5GHZ:
201 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
202 break;
203 default:
204 break;
205 }
206
207 if (rate_table == NULL)
208 return;
209
210 sband = &sc->sbands[band];
211 rate = sc->rates[band];
212
213 if (rate_table->rate_cnt > ATH_RATE_MAX)
214 maxrates = ATH_RATE_MAX;
215 else
216 maxrates = rate_table->rate_cnt;
217
218 for (i = 0; i < maxrates; i++) {
219 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
220 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 221 if (rate_table->info[i].short_preamble) {
222 rate[i].hw_value_short = rate_table->info[i].ratecode |
223 rate_table->info[i].short_preamble;
224 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
225 }
ff37e337 226 sband->n_bitrates++;
f46730d1 227
c46917bb
LR		 228 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
229 "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
82880a7c
VT		 234static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
236{
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
239 u8 chan_idx;
240
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
244 return channel;
245}
246
9ecdef4b 247static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 248{
249 unsigned long flags;
250 bool ret;
251
9ecdef4b
LR		 252 spin_lock_irqsave(&sc->sc_pm_lock, flags);
253 ret = ath9k_hw_setpower(sc->sc_ah, mode);
254 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 255
256 return ret;
257}
258
a91d75ae
LR		 259void ath9k_ps_wakeup(struct ath_softc *sc)
260{
261 unsigned long flags;
262
263 spin_lock_irqsave(&sc->sc_pm_lock, flags);
264 if (++sc->ps_usecount != 1)
265 goto unlock;
266
9ecdef4b 267 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae
LR		 268
269 unlock:
270 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
271}
272
273void ath9k_ps_restore(struct ath_softc *sc)
274{
275 unsigned long flags;
276
277 spin_lock_irqsave(&sc->sc_pm_lock, flags);
278 if (--sc->ps_usecount != 0)
279 goto unlock;
280
281 if (sc->ps_enabled &&
282 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
283 SC_OP_WAIT_FOR_CAB |
284 SC_OP_WAIT_FOR_PSPOLL_DATA |
285 SC_OP_WAIT_FOR_TX_ACK)))
9ecdef4b 286 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR		 287
288 unlock:
289 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
290}
291
ff37e337
S		 292/*
293 * Set/change channels. If the channel is really being changed, it's done
294 * by reseting the chip. To accomplish this we must first cleanup any pending
295 * DMA, then restart stuff.
296*/
0e2dedf9
JM		 297int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
298 struct ath9k_channel *hchan)
ff37e337 299{
cbe61d8a 300 struct ath_hw *ah = sc->sc_ah;
c46917bb 301 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 302 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 303 bool fastcc = true, stopped;
ae8d2858
LR		 304 struct ieee80211_channel *channel = hw->conf.channel;
305 int r;
ff37e337
S		 306
307 if (sc->sc_flags & SC_OP_INVALID)
308 return -EIO;
309
3cbb5dd7
VN		 310 ath9k_ps_wakeup(sc);
311
c0d7c7af
LR		 312 /*
313 * This is only performed if the channel settings have
314 * actually changed.
315 *
316 * To switch channels clear any pending DMA operations;
317 * wait long enough for the RX fifo to drain, reset the
318 * hardware at the new frequency, and then re-enable
319 * the relevant bits of the h/w.
320 */
321 ath9k_hw_set_interrupts(ah, 0);
043a0405 322 ath_drain_all_txq(sc, false);
c0d7c7af 323 stopped = ath_stoprecv(sc);
ff37e337 324
c0d7c7af
LR		 325 /* XXX: do not flush receive queue here. We don't want
326 * to flush data frames already in queue because of
327 * changing channel. */
ff37e337 328
c0d7c7af
LR		 329 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
330 fastcc = false;
331
c46917bb 332 ath_print(common, ATH_DBG_CONFIG,
25c56eec 333 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
c46917bb 334 sc->sc_ah->curchan->channel,
25c56eec 335 channel->center_freq, conf_is_ht40(conf));
ff37e337 336
c0d7c7af
LR		 337 spin_lock_bh(&sc->sc_resetlock);
338
339 r = ath9k_hw_reset(ah, hchan, fastcc);
340 if (r) {
c46917bb
LR		 341 ath_print(common, ATH_DBG_FATAL,
342 "Unable to reset channel (%u Mhz) "
343 "reset status %d\n",
344 channel->center_freq, r);
c0d7c7af 345 spin_unlock_bh(&sc->sc_resetlock);
3989279c 346 goto ps_restore;
ff37e337 347 }
c0d7c7af
LR		 348 spin_unlock_bh(&sc->sc_resetlock);
349
c0d7c7af
LR		 350 sc->sc_flags &= ~SC_OP_FULL_RESET;
351
352 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 353 ath_print(common, ATH_DBG_FATAL,
354 "Unable to restart recv logic\n");
3989279c
GJ		 355 r = -EIO;
356 goto ps_restore;
c0d7c7af
LR		 357 }
358
359 ath_cache_conf_rate(sc, &hw->conf);
360 ath_update_txpow(sc);
17d7904d 361 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 362
363 ps_restore:
3cbb5dd7 364 ath9k_ps_restore(sc);
3989279c 365 return r;
ff37e337
S		 366}
367
368/*
369 * This routine performs the periodic noise floor calibration function
370 * that is used to adjust and optimize the chip performance. This
371 * takes environmental changes (location, temperature) into account.
372 * When the task is complete, it reschedules itself depending on the
373 * appropriate interval that was calculated.
374 */
375static void ath_ani_calibrate(unsigned long data)
376{
20977d3e
S		 377 struct ath_softc *sc = (struct ath_softc *)data;
378 struct ath_hw *ah = sc->sc_ah;
c46917bb 379 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 380 bool longcal = false;
381 bool shortcal = false;
382 bool aniflag = false;
383 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 384 u32 cal_interval, short_cal_interval;
ff37e337 385
20977d3e
S		 386 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
387 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 388
389 /*
390 * don't calibrate when we're scanning.
391 * we are most likely not on our home channel.
392 */
e5f0921a 393 spin_lock(&sc->ani_lock);
0c98de65 394 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 395 goto set_timer;
ff37e337 396
1ffc1c61
JM		 397 /* Only calibrate if awake */
398 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
399 goto set_timer;
400
401 ath9k_ps_wakeup(sc);
402
ff37e337 403 /* Long calibration runs independently of short calibration. */
17d7904d 404 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 405 longcal = true;
c46917bb 406 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 407 sc->ani.longcal_timer = timestamp;
ff37e337
S		 408 }
409
17d7904d
S		 410 /* Short calibration applies only while caldone is false */
411 if (!sc->ani.caldone) {
20977d3e 412 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 413 shortcal = true;
c46917bb
LR		 414 ath_print(common, ATH_DBG_ANI,
415 "shortcal @%lu\n", jiffies);
17d7904d
S		 416 sc->ani.shortcal_timer = timestamp;
417 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 418 }
419 } else {
17d7904d 420 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 421 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 422 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
423 if (sc->ani.caldone)
424 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 425 }
426 }
427
428 /* Verify whether we must check ANI */
20977d3e 429 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 430 aniflag = true;
17d7904d 431 sc->ani.checkani_timer = timestamp;
ff37e337
S		 432 }
433
434 /* Skip all processing if there's nothing to do. */
435 if (longcal || shortcal || aniflag) {
436 /* Call ANI routine if necessary */
437 if (aniflag)
22e66a4c 438 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S		 439
440 /* Perform calibration if necessary */
441 if (longcal || shortcal) {
43c27613
LR		 442 sc->ani.caldone =
443 ath9k_hw_calibrate(ah,
444 ah->curchan,
445 common->rx_chainmask,
446 longcal);
379f0440
S		 447
448 if (longcal)
449 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
450 ah->curchan);
451
c46917bb
LR		 452 ath_print(common, ATH_DBG_ANI,
453 " calibrate chan %u/%x nf: %d\n",
454 ah->curchan->channel,
455 ah->curchan->channelFlags,
456 sc->ani.noise_floor);
ff37e337
S		 457 }
458 }
459
1ffc1c61
JM		 460 ath9k_ps_restore(sc);
461
20977d3e 462set_timer:
e5f0921a 463 spin_unlock(&sc->ani_lock);
ff37e337
S		 464 /*
465 * Set timer interval based on previous results.
466 * The interval must be the shortest necessary to satisfy ANI,
467 * short calibration and long calibration.
468 */
aac9207e 469 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 470 if (sc->sc_ah->config.enable_ani)
aac9207e 471 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 472 if (!sc->ani.caldone)
20977d3e 473 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 474
17d7904d 475 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 476}
477
415f738e
S		 478static void ath_start_ani(struct ath_softc *sc)
479{
480 unsigned long timestamp = jiffies_to_msecs(jiffies);
481
482 sc->ani.longcal_timer = timestamp;
483 sc->ani.shortcal_timer = timestamp;
484 sc->ani.checkani_timer = timestamp;
485
486 mod_timer(&sc->ani.timer,
487 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
488}
489
ff37e337
S		 490/*
491 * Update tx/rx chainmask. For legacy association,
492 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 493 * the chainmask configuration, for bt coexistence, use
494 * the chainmask configuration even in legacy mode.
ff37e337 495 */
0e2dedf9 496void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 497{
af03abec 498 struct ath_hw *ah = sc->sc_ah;
43c27613 499 struct ath_common *common = ath9k_hw_common(ah);
af03abec 500
3d832611 501 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
766ec4a9 502 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
43c27613
LR		 503 common->tx_chainmask = ah->caps.tx_chainmask;
504 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337 505 } else {
43c27613
LR		 506 common->tx_chainmask = 1;
507 common->rx_chainmask = 1;
ff37e337
S		 508 }
509
43c27613 510 ath_print(common, ATH_DBG_CONFIG,
c46917bb 511 "tx chmask: %d, rx chmask: %d\n",
43c27613
LR		 512 common->tx_chainmask,
513 common->rx_chainmask);
ff37e337
S		 514}
515
516static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
517{
518 struct ath_node *an;
519
520 an = (struct ath_node *)sta->drv_priv;
521
87792efc 522 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 523 ath_tx_node_init(sc, an);
9e98ac65 524 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 525 sta->ht_cap.ampdu_factor);
526 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 527 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 528 }
ff37e337
S		 529}
530
531static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
532{
533 struct ath_node *an = (struct ath_node *)sta->drv_priv;
534
535 if (sc->sc_flags & SC_OP_TXAGGR)
536 ath_tx_node_cleanup(sc, an);
537}
538
539static void ath9k_tasklet(unsigned long data)
540{
541 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 542 struct ath_hw *ah = sc->sc_ah;
c46917bb 543 struct ath_common *common = ath9k_hw_common(ah);
af03abec 544
17d7904d 545 u32 status = sc->intrstatus;
ff37e337 546
153e080d
VT		 547 ath9k_ps_wakeup(sc);
548
ff37e337 549 if (status & ATH9K_INT_FATAL) {
ff37e337 550 ath_reset(sc, false);
153e080d 551 ath9k_ps_restore(sc);
ff37e337 552 return;
063d8be3 553 }
ff37e337 554
063d8be3
S		 555 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
556 spin_lock_bh(&sc->rx.rxflushlock);
557 ath_rx_tasklet(sc, 0);
558 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 559 }
560
063d8be3
S		 561 if (status & ATH9K_INT_TX)
562 ath_tx_tasklet(sc);
563
96148326 564 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 565 /*
566 * TSF sync does not look correct; remain awake to sync with
567 * the next Beacon.
568 */
c46917bb
LR		 569 ath_print(common, ATH_DBG_PS,
570 "TSFOOR - Sync with next Beacon\n");
ccdfeab6 571 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 572 }
573
766ec4a9 574 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT		 575 if (status & ATH9K_INT_GENTIMER)
576 ath_gen_timer_isr(sc->sc_ah);
577
ff37e337 578 /* re-enable hardware interrupt */
af03abec 579 ath9k_hw_set_interrupts(ah, sc->imask);
153e080d 580 ath9k_ps_restore(sc);
ff37e337
S		 581}
582
6baff7f9 583irqreturn_t ath_isr(int irq, void *dev)
ff37e337 584{
063d8be3
S		 585#define SCHED_INTR ( \
586 ATH9K_INT_FATAL | \
587 ATH9K_INT_RXORN | \
588 ATH9K_INT_RXEOL | \
589 ATH9K_INT_RX | \
590 ATH9K_INT_TX | \
591 ATH9K_INT_BMISS | \
592 ATH9K_INT_CST | \
ebb8e1d7
VT		 593 ATH9K_INT_TSFOOR | \
594 ATH9K_INT_GENTIMER)
063d8be3 595
ff37e337 596 struct ath_softc *sc = dev;
cbe61d8a 597 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 598 enum ath9k_int status;
599 bool sched = false;
600
063d8be3
S		 601 /*
602 * The hardware is not ready/present, don't
603 * touch anything. Note this can happen early
604 * on if the IRQ is shared.
605 */
606 if (sc->sc_flags & SC_OP_INVALID)
607 return IRQ_NONE;
ff37e337 608
063d8be3
S		 609
610 /* shared irq, not for us */
611
153e080d 612 if (!ath9k_hw_intrpend(ah))
063d8be3 613 return IRQ_NONE;
063d8be3
S		 614
615 /*
616 * Figure out the reason(s) for the interrupt. Note
617 * that the hal returns a pseudo-ISR that may include
618 * bits we haven't explicitly enabled so we mask the
619 * value to insure we only process bits we requested.
620 */
621 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
622 status &= sc->imask; /* discard unasked-for bits */
ff37e337 623
063d8be3
S		 624 /*
625 * If there are no status bits set, then this interrupt was not
626 * for me (should have been caught above).
627 */
153e080d 628 if (!status)
063d8be3 629 return IRQ_NONE;
ff37e337 630
063d8be3
S		 631 /* Cache the status */
632 sc->intrstatus = status;
633
634 if (status & SCHED_INTR)
635 sched = true;
636
637 /*
638 * If a FATAL or RXORN interrupt is received, we have to reset the
639 * chip immediately.
640 */
641 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
642 goto chip_reset;
643
644 if (status & ATH9K_INT_SWBA)
645 tasklet_schedule(&sc->bcon_tasklet);
646
647 if (status & ATH9K_INT_TXURN)
648 ath9k_hw_updatetxtriglevel(ah, true);
649
650 if (status & ATH9K_INT_MIB) {
ff37e337 651 /*
063d8be3
S		 652 * Disable interrupts until we service the MIB
653 * interrupt; otherwise it will continue to
654 * fire.
ff37e337 655 */
063d8be3
S		 656 ath9k_hw_set_interrupts(ah, 0);
657 /*
658 * Let the hal handle the event. We assume
659 * it will clear whatever condition caused
660 * the interrupt.
661 */
22e66a4c 662 ath9k_hw_procmibevent(ah);
063d8be3
S		 663 ath9k_hw_set_interrupts(ah, sc->imask);
664 }
ff37e337 665
153e080d
VT		 666 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
667 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 668 /* Clear RxAbort bit so that we can
669 * receive frames */
9ecdef4b 670 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 671 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 672 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 673 }
063d8be3
S		 674
675chip_reset:
ff37e337 676
817e11de
S		 677 ath_debug_stat_interrupt(sc, status);
678
ff37e337
S		 679 if (sched) {
680 /* turn off every interrupt except SWBA */
17d7904d 681 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 682 tasklet_schedule(&sc->intr_tq);
683 }
684
685 return IRQ_HANDLED;
063d8be3
S		 686
687#undef SCHED_INTR
ff37e337
S		 688}
689
f078f209 690static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 691 struct ieee80211_channel *chan,
094d05dc 692 enum nl80211_channel_type channel_type)
f078f209
LR		 693{
694 u32 chanmode = 0;
f078f209
LR		 695
696 switch (chan->band) {
697 case IEEE80211_BAND_2GHZ:
094d05dc
S		 698 switch(channel_type) {
699 case NL80211_CHAN_NO_HT:
700 case NL80211_CHAN_HT20:
f078f209 701 chanmode = CHANNEL_G_HT20;
094d05dc
S		 702 break;
703 case NL80211_CHAN_HT40PLUS:
f078f209 704 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 705 break;
706 case NL80211_CHAN_HT40MINUS:
f078f209 707 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 708 break;
709 }
f078f209
LR		 710 break;
711 case IEEE80211_BAND_5GHZ:
094d05dc
S		 712 switch(channel_type) {
713 case NL80211_CHAN_NO_HT:
714 case NL80211_CHAN_HT20:
f078f209 715 chanmode = CHANNEL_A_HT20;
094d05dc
S		 716 break;
717 case NL80211_CHAN_HT40PLUS:
f078f209 718 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 719 break;
720 case NL80211_CHAN_HT40MINUS:
f078f209 721 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 722 break;
723 }
f078f209
LR		 724 break;
725 default:
726 break;
727 }
728
729 return chanmode;
730}
731
6ace2891 732static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 733 struct ath9k_keyval *hk, const u8 *addr,
734 bool authenticator)
f078f209 735{
6ace2891
JM		 736 const u8 *key_rxmic;
737 const u8 *key_txmic;
f078f209 738
6ace2891
JM		 739 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
740 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 741
742 if (addr == NULL) {
d216aaa6
JM		 743 /*
744 * Group key installation - only two key cache entries are used
745 * regardless of splitmic capability since group key is only
746 * used either for TX or RX.
747 */
3f53dd64
JM		 748 if (authenticator) {
749 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
750 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
751 } else {
752 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
753 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
754 }
d216aaa6 755 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 756 }
17d7904d 757 if (!sc->splitmic) {
d216aaa6 758 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 759 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
760 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 761 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 762 }
d216aaa6
JM		 763
764 /* Separate key cache entries for TX and RX */
765
766 /* TX key goes at first index, RX key at +32. */
f078f209 767 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 768 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
769 /* TX MIC entry failed. No need to proceed further */
c46917bb
LR		 770 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
771 "Setting TX MIC Key Failed\n");
f078f209
LR		 772 return 0;
773 }
774
775 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
776 /* XXX delete tx key on failure? */
d216aaa6 777 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 778}
779
780static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
781{
782 int i;
783
17d7904d
S		 784 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
785 if (test_bit(i, sc->keymap) ||
786 test_bit(i + 64, sc->keymap))
6ace2891 787 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 788 if (sc->splitmic &&
789 (test_bit(i + 32, sc->keymap) ||
790 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 791 continue; /* At least one part of TKIP key allocated */
792
793 /* Found a free slot for a TKIP key */
794 return i;
795 }
796 return -1;
797}
798
799static int ath_reserve_key_cache_slot(struct ath_softc *sc)
800{
801 int i;
802
803 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 804 if (sc->splitmic) {
805 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
806 if (!test_bit(i, sc->keymap) &&
807 (test_bit(i + 32, sc->keymap) ||
808 test_bit(i + 64, sc->keymap) ||
809 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 810 return i;
17d7904d
S		 811 if (!test_bit(i + 32, sc->keymap) &&
812 (test_bit(i, sc->keymap) ||
813 test_bit(i + 64, sc->keymap) ||
814 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 815 return i + 32;
17d7904d
S		 816 if (!test_bit(i + 64, sc->keymap) &&
817 (test_bit(i , sc->keymap) ||
818 test_bit(i + 32, sc->keymap) ||
819 test_bit(i + 64 + 32, sc->keymap)))
ea612132 820 return i + 64;
17d7904d
S		 821 if (!test_bit(i + 64 + 32, sc->keymap) &&
822 (test_bit(i, sc->keymap) ||
823 test_bit(i + 32, sc->keymap) ||
824 test_bit(i + 64, sc->keymap)))
ea612132 825 return i + 64 + 32;
6ace2891
JM		 826 }
827 } else {
17d7904d
S		 828 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
829 if (!test_bit(i, sc->keymap) &&
830 test_bit(i + 64, sc->keymap))
6ace2891 831 return i;
17d7904d
S		 832 if (test_bit(i, sc->keymap) &&
833 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 834 return i + 64;
835 }
836 }
837
838 /* No partially used TKIP slots, pick any available slot */
17d7904d 839 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 840 /* Do not allow slots that could be needed for TKIP group keys
841 * to be used. This limitation could be removed if we know that
842 * TKIP will not be used. */
843 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
844 continue;
17d7904d 845 if (sc->splitmic) {
be2864cf
JM		 846 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
847 continue;
848 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
849 continue;
850 }
851
17d7904d 852 if (!test_bit(i, sc->keymap))
6ace2891
JM		 853 return i; /* Found a free slot for a key */
854 }
855
856 /* No free slot found */
857 return -1;
f078f209
LR		 858}
859
860static int ath_key_config(struct ath_softc *sc,
3f53dd64 861 struct ieee80211_vif *vif,
dc822b5d 862 struct ieee80211_sta *sta,
f078f209
LR		 863 struct ieee80211_key_conf *key)
864{
f078f209
LR		 865 struct ath9k_keyval hk;
866 const u8 *mac = NULL;
867 int ret = 0;
6ace2891 868 int idx;
f078f209
LR		 869
870 memset(&hk, 0, sizeof(hk));
871
872 switch (key->alg) {
873 case ALG_WEP:
874 hk.kv_type = ATH9K_CIPHER_WEP;
875 break;
876 case ALG_TKIP:
877 hk.kv_type = ATH9K_CIPHER_TKIP;
878 break;
879 case ALG_CCMP:
880 hk.kv_type = ATH9K_CIPHER_AES_CCM;
881 break;
882 default:
ca470b29 883 return -EOPNOTSUPP;
f078f209
LR		 884 }
885
6ace2891 886 hk.kv_len = key->keylen;
f078f209
LR		 887 memcpy(hk.kv_val, key->key, key->keylen);
888
6ace2891
JM		 889 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
890 /* For now, use the default keys for broadcast keys. This may
891 * need to change with virtual interfaces. */
892 idx = key->keyidx;
893 } else if (key->keyidx) {
dc822b5d
JB		 894 if (WARN_ON(!sta))
895 return -EOPNOTSUPP;
896 mac = sta->addr;
897
6ace2891
JM		 898 if (vif->type != NL80211_IFTYPE_AP) {
899 /* Only keyidx 0 should be used with unicast key, but
900 * allow this for client mode for now. */
901 idx = key->keyidx;
902 } else
903 return -EIO;
f078f209 904 } else {
dc822b5d
JB		 905 if (WARN_ON(!sta))
906 return -EOPNOTSUPP;
907 mac = sta->addr;
908
6ace2891
JM		 909 if (key->alg == ALG_TKIP)
910 idx = ath_reserve_key_cache_slot_tkip(sc);
911 else
912 idx = ath_reserve_key_cache_slot(sc);
913 if (idx < 0)
ca470b29 914 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 915 }
916
917 if (key->alg == ALG_TKIP)
3f53dd64
JM		 918 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
919 vif->type == NL80211_IFTYPE_AP);
f078f209 920 else
d216aaa6 921 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 922
923 if (!ret)
924 return -EIO;
925
17d7904d 926 set_bit(idx, sc->keymap);
6ace2891 927 if (key->alg == ALG_TKIP) {
17d7904d
S		 928 set_bit(idx + 64, sc->keymap);
929 if (sc->splitmic) {
930 set_bit(idx + 32, sc->keymap);
931 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 932 }
933 }
934
935 return idx;
f078f209
LR		 936}
937
938static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
939{
6ace2891
JM		 940 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
941 if (key->hw_key_idx < IEEE80211_WEP_NKID)
942 return;
943
17d7904d 944 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 945 if (key->alg != ALG_TKIP)
946 return;
f078f209 947
17d7904d
S		 948 clear_bit(key->hw_key_idx + 64, sc->keymap);
949 if (sc->splitmic) {
950 clear_bit(key->hw_key_idx + 32, sc->keymap);
951 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 952 }
f078f209
LR		 953}
954
eb2599ca
S		 955static void setup_ht_cap(struct ath_softc *sc,
956 struct ieee80211_sta_ht_cap *ht_info)
f078f209 957{
43c27613 958 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
140add21 959 u8 tx_streams, rx_streams;
f078f209 960
d9fe60de
JB		 961 ht_info->ht_supported = true;
962 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
963 IEEE80211_HT_CAP_SM_PS |
964 IEEE80211_HT_CAP_SGI_40 |
965 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 966
9e98ac65
S		 967 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
968 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 969
d9fe60de
JB		 970 /* set up supported mcs set */
971 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
43c27613
LR		 972 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
973 1 : 2;
974 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
975 1 : 2;
140add21
SB		 976
977 if (tx_streams != rx_streams) {
43c27613 978 ath_print(common, ATH_DBG_CONFIG,
c46917bb
LR		 979 "TX streams %d, RX streams: %d\n",
980 tx_streams, rx_streams);
140add21
SB		 981 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
982 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
983 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
984 }
eb2599ca 985
140add21
SB		 986 ht_info->mcs.rx_mask[0] = 0xff;
987 if (rx_streams >= 2)
eb2599ca 988 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 989
140add21 990 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 991}
992
8feceb67 993static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 994 struct ieee80211_vif *vif,
8feceb67 995 struct ieee80211_bss_conf *bss_conf)
f078f209 996{
f2b2143e 997 struct ath_hw *ah = sc->sc_ah;
1510718d 998 struct ath_common *common = ath9k_hw_common(ah);
f078f209 999
8feceb67 1000 if (bss_conf->assoc) {
c46917bb
LR		 1001 ath_print(common, ATH_DBG_CONFIG,
1002 "Bss Info ASSOC %d, bssid: %pM\n",
1003 bss_conf->aid, common->curbssid);
f078f209 1004
8feceb67 1005 /* New association, store aid */
1510718d 1006 common->curaid = bss_conf->aid;
f2b2143e 1007 ath9k_hw_write_associd(ah);
2664f201
SB		 1008
1009 /*
1010 * Request a re-configuration of Beacon related timers
1011 * on the receipt of the first Beacon frame (i.e.,
1012 * after time sync with the AP).
1013 */
1014 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 1015
8feceb67 1016 /* Configure the beacon */
2c3db3d5 1017 ath_beacon_config(sc, vif);
f078f209 1018
8feceb67 1019 /* Reset rssi stats */
22e66a4c 1020 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 1021
415f738e 1022 ath_start_ani(sc);
8feceb67 1023 } else {
c46917bb 1024 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 1025 common->curaid = 0;
f38faa31
SB		 1026 /* Stop ANI */
1027 del_timer_sync(&sc->ani.timer);
f078f209 1028 }
8feceb67 1029}
f078f209 1030
8feceb67
VT		 1031/********************************/
1032/* LED functions */
1033/********************************/
f078f209 1034
f2bffa7e
VT		 1035static void ath_led_blink_work(struct work_struct *work)
1036{
1037 struct ath_softc *sc = container_of(work, struct ath_softc,
1038 ath_led_blink_work.work);
1039
1040 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1041 return;
85067c06
VT		 1042
1043 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1044 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
08fc5c1b 1045 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
85067c06 1046 else
08fc5c1b 1047 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
85067c06 1048 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e 1049
42935eca
LR		 1050 ieee80211_queue_delayed_work(sc->hw,
1051 &sc->ath_led_blink_work,
1052 (sc->sc_flags & SC_OP_LED_ON) ?
1053 msecs_to_jiffies(sc->led_off_duration) :
1054 msecs_to_jiffies(sc->led_on_duration));
f2bffa7e 1055
85067c06
VT		 1056 sc->led_on_duration = sc->led_on_cnt ?
1057 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1058 ATH_LED_ON_DURATION_IDLE;
1059 sc->led_off_duration = sc->led_off_cnt ?
1060 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1061 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 1062 sc->led_on_cnt = sc->led_off_cnt = 0;
1063 if (sc->sc_flags & SC_OP_LED_ON)
1064 sc->sc_flags &= ~SC_OP_LED_ON;
1065 else
1066 sc->sc_flags |= SC_OP_LED_ON;
1067}
1068
8feceb67
VT		 1069static void ath_led_brightness(struct led_classdev *led_cdev,
1070 enum led_brightness brightness)
1071{
1072 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1073 struct ath_softc *sc = led->sc;
f078f209 1074
8feceb67
VT		 1075 switch (brightness) {
1076 case LED_OFF:
1077 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e 1078 led->led_type == ATH_LED_RADIO) {
08fc5c1b 1079 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
f2bffa7e 1080 (led->led_type == ATH_LED_RADIO));
8feceb67 1081 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1082 if (led->led_type == ATH_LED_RADIO)
1083 sc->sc_flags &= ~SC_OP_LED_ON;
1084 } else {
1085 sc->led_off_cnt++;
1086 }
8feceb67
VT		 1087 break;
1088 case LED_FULL:
f2bffa7e 1089 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1090 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
42935eca
LR		 1091 ieee80211_queue_delayed_work(sc->hw,
1092 &sc->ath_led_blink_work, 0);
f2bffa7e 1093 } else if (led->led_type == ATH_LED_RADIO) {
08fc5c1b 1094 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
f2bffa7e
VT		 1095 sc->sc_flags |= SC_OP_LED_ON;
1096 } else {
1097 sc->led_on_cnt++;
1098 }
8feceb67
VT		 1099 break;
1100 default:
1101 break;
f078f209 1102 }
8feceb67 1103}
f078f209 1104
8feceb67
VT		 1105static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1106 char *trigger)
1107{
1108 int ret;
f078f209 1109
8feceb67
VT		 1110 led->sc = sc;
1111 led->led_cdev.name = led->name;
1112 led->led_cdev.default_trigger = trigger;
1113 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1114
8feceb67
VT		 1115 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1116 if (ret)
c46917bb
LR		 1117 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1118 "Failed to register led:%s", led->name);
8feceb67
VT		 1119 else
1120 led->registered = 1;
1121 return ret;
1122}
f078f209 1123
8feceb67
VT		 1124static void ath_unregister_led(struct ath_led *led)
1125{
1126 if (led->registered) {
1127 led_classdev_unregister(&led->led_cdev);
1128 led->registered = 0;
f078f209 1129 }
f078f209
LR		 1130}
1131
8feceb67 1132static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1133{
8feceb67
VT		 1134 ath_unregister_led(&sc->assoc_led);
1135 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1136 ath_unregister_led(&sc->tx_led);
1137 ath_unregister_led(&sc->rx_led);
1138 ath_unregister_led(&sc->radio_led);
08fc5c1b 1139 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
8feceb67 1140}
f078f209 1141
8feceb67
VT		 1142static void ath_init_leds(struct ath_softc *sc)
1143{
1144 char *trigger;
1145 int ret;
f078f209 1146
08fc5c1b
VN		 1147 if (AR_SREV_9287(sc->sc_ah))
1148 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1149 else
1150 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1151
8feceb67 1152 /* Configure gpio 1 for output */
08fc5c1b 1153 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
8feceb67
VT		 1154 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1155 /* LED off, active low */
08fc5c1b 1156 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
7dcfdcd9 1157
f2bffa7e
VT		 1158 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1159
8feceb67
VT		 1160 trigger = ieee80211_get_radio_led_name(sc->hw);
1161 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1162 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1163 ret = ath_register_led(sc, &sc->radio_led, trigger);
1164 sc->radio_led.led_type = ATH_LED_RADIO;
1165 if (ret)
1166 goto fail;
7dcfdcd9 1167
8feceb67
VT		 1168 trigger = ieee80211_get_assoc_led_name(sc->hw);
1169 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1170 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1171 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1172 sc->assoc_led.led_type = ATH_LED_ASSOC;
1173 if (ret)
1174 goto fail;
f078f209 1175
8feceb67
VT		 1176 trigger = ieee80211_get_tx_led_name(sc->hw);
1177 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1178 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1179 ret = ath_register_led(sc, &sc->tx_led, trigger);
1180 sc->tx_led.led_type = ATH_LED_TX;
1181 if (ret)
1182 goto fail;
f078f209 1183
8feceb67
VT		 1184 trigger = ieee80211_get_rx_led_name(sc->hw);
1185 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1186 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1187 ret = ath_register_led(sc, &sc->rx_led, trigger);
1188 sc->rx_led.led_type = ATH_LED_RX;
1189 if (ret)
1190 goto fail;
f078f209 1191
8feceb67
VT		 1192 return;
1193
1194fail:
35c95ab9 1195 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67 1196 ath_deinit_leds(sc);
f078f209
LR		 1197}
1198
7ec3e514 1199void ath_radio_enable(struct ath_softc *sc)
500c064d 1200{
cbe61d8a 1201 struct ath_hw *ah = sc->sc_ah;
c46917bb 1202 struct ath_common *common = ath9k_hw_common(ah);
ae8d2858
LR		 1203 struct ieee80211_channel *channel = sc->hw->conf.channel;
1204 int r;
500c064d 1205
3cbb5dd7 1206 ath9k_ps_wakeup(sc);
93b1b37f 1207 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 1208
159cd468
VT		 1209 if (!ah->curchan)
1210 ah->curchan = ath_get_curchannel(sc, sc->hw);
1211
d2f5b3a6 1212 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1213 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1214 if (r) {
c46917bb
LR		 1215 ath_print(common, ATH_DBG_FATAL,
1216 "Unable to reset channel %u (%uMhz) ",
1217 "reset status %d\n",
1218 channel->center_freq, r);
500c064d
VT		 1219 }
1220 spin_unlock_bh(&sc->sc_resetlock);
1221
1222 ath_update_txpow(sc);
1223 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 1224 ath_print(common, ATH_DBG_FATAL,
1225 "Unable to restart recv logic\n");
500c064d
VT		 1226 return;
1227 }
1228
1229 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1230 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1231
1232 /* Re-Enable interrupts */
17d7904d 1233 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1234
1235 /* Enable LED */
08fc5c1b 1236 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 1237 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 1238 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d
VT		 1239
1240 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1241 ath9k_ps_restore(sc);
500c064d
VT		 1242}
1243
7ec3e514 1244void ath_radio_disable(struct ath_softc *sc)
500c064d 1245{
cbe61d8a 1246 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1247 struct ieee80211_channel *channel = sc->hw->conf.channel;
1248 int r;
500c064d 1249
3cbb5dd7 1250 ath9k_ps_wakeup(sc);
500c064d
VT		 1251 ieee80211_stop_queues(sc->hw);
1252
1253 /* Disable LED */
08fc5c1b
VN		 1254 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1255 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT		 1256
1257 /* Disable interrupts */
1258 ath9k_hw_set_interrupts(ah, 0);
1259
043a0405 1260 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1261 ath_stoprecv(sc); /* turn off frame recv */
1262 ath_flushrecv(sc); /* flush recv queue */
1263
159cd468
VT		 1264 if (!ah->curchan)
1265 ah->curchan = ath_get_curchannel(sc, sc->hw);
1266
500c064d 1267 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1268 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1269 if (r) {
c46917bb
LR		 1270 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1271 "Unable to reset channel %u (%uMhz) "
1272 "reset status %d\n",
1273 channel->center_freq, r);
500c064d
VT		 1274 }
1275 spin_unlock_bh(&sc->sc_resetlock);
1276
1277 ath9k_hw_phy_disable(ah);
93b1b37f 1278 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 1279 ath9k_ps_restore(sc);
9ecdef4b 1280 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1281}
1282
5077fd35
GJ		 1283/*******************/
1284/* Rfkill */
1285/*******************/
1286
500c064d
VT		 1287static bool ath_is_rfkill_set(struct ath_softc *sc)
1288{
cbe61d8a 1289 struct ath_hw *ah = sc->sc_ah;
500c064d 1290
2660b81a
S		 1291 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1292 ah->rfkill_polarity;
500c064d
VT		 1293}
1294
3b319aae 1295static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1296{
3b319aae
JB		 1297 struct ath_wiphy *aphy = hw->priv;
1298 struct ath_softc *sc = aphy->sc;
19d337df 1299 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1300
3b319aae 1301 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
500c064d
VT		 1302}
1303
3b319aae 1304static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1305{
3b319aae 1306 struct ath_hw *ah = sc->sc_ah;
9c84b797 1307
3b319aae
JB		 1308 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1309 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1310}
500c064d 1311
6baff7f9 1312void ath_cleanup(struct ath_softc *sc)
39c3c2f2 1313{
5bb12791
LR		 1314 struct ath_hw *ah = sc->sc_ah;
1315 struct ath_common *common = ath9k_hw_common(ah);
1316
39c3c2f2
GJ		 1317 ath_detach(sc);
1318 free_irq(sc->irq, sc);
5bb12791 1319 ath_bus_cleanup(common);
c52f33d0 1320 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1321 ieee80211_free_hw(sc->hw);
1322}
1323
6baff7f9 1324void ath_detach(struct ath_softc *sc)
f078f209 1325{
8feceb67 1326 struct ieee80211_hw *hw = sc->hw;
4d6b228d 1327 struct ath_hw *ah = sc->sc_ah;
9c84b797 1328 int i = 0;
f078f209 1329
3cbb5dd7
VN		 1330 ath9k_ps_wakeup(sc);
1331
4d6b228d 1332 dev_dbg(sc->dev, "Detach ATH hw\n");
f078f209 1333
35c95ab9 1334 ath_deinit_leds(sc);
e31f7b96 1335 wiphy_rfkill_stop_polling(sc->hw->wiphy);
35c95ab9 1336
c52f33d0
JM		 1337 for (i = 0; i < sc->num_sec_wiphy; i++) {
1338 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1339 if (aphy == NULL)
1340 continue;
1341 sc->sec_wiphy[i] = NULL;
1342 ieee80211_unregister_hw(aphy->hw);
1343 ieee80211_free_hw(aphy->hw);
1344 }
3fcdfb4b 1345 ieee80211_unregister_hw(hw);
8feceb67
VT		 1346 ath_rx_cleanup(sc);
1347 ath_tx_cleanup(sc);
f078f209 1348
9c84b797
S		 1349 tasklet_kill(&sc->intr_tq);
1350 tasklet_kill(&sc->bcon_tasklet);
f078f209 1351
9c84b797 1352 if (!(sc->sc_flags & SC_OP_INVALID))
9ecdef4b 1353 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8feceb67 1354
9c84b797
S		 1355 /* cleanup tx queues */
1356 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1357 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1358 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797 1359
75d7839f 1360 if ((sc->btcoex.no_stomp_timer) &&
766ec4a9 1361 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1362 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1773912b 1363
4d6b228d 1364 ath9k_hw_detach(ah);
af03abec 1365 ath9k_exit_debug(ah);
3ce1b1a9 1366 sc->sc_ah = NULL;
f078f209
LR		 1367}
1368
e3bb249b
BC		 1369static int ath9k_reg_notifier(struct wiphy *wiphy,
1370 struct regulatory_request *request)
1371{
1372 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1373 struct ath_wiphy *aphy = hw->priv;
1374 struct ath_softc *sc = aphy->sc;
27c51f1a 1375 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
e3bb249b
BC		 1376
1377 return ath_reg_notifier_apply(wiphy, request, reg);
1378}
1379
75d7839f
LR		 1380/*
1381 * Detects if there is any priority bt traffic
1382 */
1383static void ath_detect_bt_priority(struct ath_softc *sc)
1384{
1385 struct ath_btcoex *btcoex = &sc->btcoex;
1386 struct ath_hw *ah = sc->sc_ah;
1387
766ec4a9 1388 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
75d7839f
LR		 1389 btcoex->bt_priority_cnt++;
1390
1391 if (time_after(jiffies, btcoex->bt_priority_time +
1392 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1393 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
c46917bb
LR		 1394 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1395 "BT priority traffic detected");
75d7839f
LR		 1396 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1397 } else {
1398 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1399 }
1400
1401 btcoex->bt_priority_cnt = 0;
1402 btcoex->bt_priority_time = jiffies;
1403 }
1404}
1405
75d7839f
LR		 1406/*
1407 * Configures appropriate weight based on stomp type.
1408 */
269ad812
LR		 1409static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1410 enum ath_stomp_type stomp_type)
75d7839f 1411{
269ad812 1412 struct ath_hw *ah = sc->sc_ah;
75d7839f
LR		 1413
1414 switch (stomp_type) {
1415 case ATH_BTCOEX_STOMP_ALL:
269ad812
LR		 1416 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1417 AR_STOMP_ALL_WLAN_WGHT);
75d7839f
LR		 1418 break;
1419 case ATH_BTCOEX_STOMP_LOW:
269ad812
LR		 1420 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1421 AR_STOMP_LOW_WLAN_WGHT);
75d7839f
LR		 1422 break;
1423 case ATH_BTCOEX_STOMP_NONE:
269ad812
LR		 1424 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1425 AR_STOMP_NONE_WLAN_WGHT);
75d7839f
LR		 1426 break;
1427 default:
c46917bb
LR		 1428 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1429 "Invalid Stomptype\n");
75d7839f
LR		 1430 break;
1431 }
1432
269ad812 1433 ath9k_hw_btcoex_enable(ah);
75d7839f
LR		 1434}
1435
cd9bf689
LR		 1436static void ath9k_gen_timer_start(struct ath_hw *ah,
1437 struct ath_gen_timer *timer,
1438 u32 timer_next,
1439 u32 timer_period)
1440{
1441 ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1442
1443 if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
1444 ath9k_hw_set_interrupts(ah, 0);
1445 ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
1446 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
1447 }
1448}
1449
1450static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1451{
1452 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1453
1454 ath9k_hw_gen_timer_stop(ah, timer);
1455
1456 /* if no timer is enabled, turn off interrupt mask */
1457 if (timer_table->timer_mask.val == 0) {
1458 ath9k_hw_set_interrupts(ah, 0);
1459 ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
1460 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
1461 }
1462}
1463
75d7839f
LR		 1464/*
1465 * This is the master bt coex timer which runs for every
1466 * 45ms, bt traffic will be given priority during 55% of this
1467 * period while wlan gets remaining 45%
1468 */
1469static void ath_btcoex_period_timer(unsigned long data)
1470{
1471 struct ath_softc *sc = (struct ath_softc *) data;
1472 struct ath_hw *ah = sc->sc_ah;
1473 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f
LR		 1474
1475 ath_detect_bt_priority(sc);
1476
1477 spin_lock_bh(&btcoex->btcoex_lock);
1478
269ad812 1479 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
75d7839f
LR		 1480
1481 spin_unlock_bh(&btcoex->btcoex_lock);
1482
1483 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1484 if (btcoex->hw_timer_enabled)
cd9bf689 1485 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
75d7839f 1486
cd9bf689
LR		 1487 ath9k_gen_timer_start(ah,
1488 btcoex->no_stomp_timer,
1489 (ath9k_hw_gettsf32(ah) +
1490 btcoex->btcoex_no_stomp),
1491 btcoex->btcoex_no_stomp * 10);
75d7839f
LR		 1492 btcoex->hw_timer_enabled = true;
1493 }
1494
1495 mod_timer(&btcoex->period_timer, jiffies +
1496 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1497}
1498
1499/*
1500 * Generic tsf based hw timer which configures weight
1501 * registers to time slice between wlan and bt traffic
1502 */
1503static void ath_btcoex_no_stomp_timer(void *arg)
1504{
1505 struct ath_softc *sc = (struct ath_softc *)arg;
1506 struct ath_hw *ah = sc->sc_ah;
1507 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f 1508
c46917bb
LR		 1509 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1510 "no stomp timer running \n");
75d7839f
LR		 1511
1512 spin_lock_bh(&btcoex->btcoex_lock);
1513
e08a6ace 1514 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
269ad812 1515 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
e08a6ace 1516 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
269ad812 1517 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
75d7839f
LR		 1518
1519 spin_unlock_bh(&btcoex->btcoex_lock);
1520}
1521
1522static int ath_init_btcoex_timer(struct ath_softc *sc)
1523{
1524 struct ath_btcoex *btcoex = &sc->btcoex;
1525
1526 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1527 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1528 btcoex->btcoex_period / 100;
1529
1530 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1531 (unsigned long) sc);
1532
1533 spin_lock_init(&btcoex->btcoex_lock);
1534
1535 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1536 ath_btcoex_no_stomp_timer,
1537 ath_btcoex_no_stomp_timer,
1538 (void *) sc, AR_FIRST_NDP_TIMER);
1539
1540 if (!btcoex->no_stomp_timer)
1541 return -ENOMEM;
1542
1543 return 0;
1544}
1545
9e4bffd2
LR		 1546/*
1547 * Read and write, they both share the same lock. We do this to serialize
1548 * reads and writes on Atheros 802.11n PCI devices only. This is required
1549 * as the FIFO on these devices can only accept sanely 2 requests. After
1550 * that the device goes bananas. Serializing the reads/writes prevents this
1551 * from happening.
1552 */
1553
1554static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1555{
1556 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1557
1558 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1559 unsigned long flags;
1560 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
1561 iowrite32(val, ah->ah_sc->mem + reg_offset);
1562 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
1563 } else
1564 iowrite32(val, ah->ah_sc->mem + reg_offset);
1565}
1566
1567static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1568{
1569 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1570 u32 val;
1571
1572 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1573 unsigned long flags;
1574 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
1575 val = ioread32(ah->ah_sc->mem + reg_offset);
1576 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
1577 } else
1578 val = ioread32(ah->ah_sc->mem + reg_offset);
1579 return val;
1580}
1581
2ddb5c8b 1582static const struct ath_ops ath9k_common_ops = {
9e4bffd2
LR		 1583 .read = ath9k_ioread32,
1584 .write = ath9k_iowrite32,
1585};
1586
1e40bcfa
LR		 1587/*
1588 * Initialize and fill ath_softc, ath_sofct is the
1589 * "Software Carrier" struct. Historically it has existed
1590 * to allow the separation between hardware specific
1591 * variables (now in ath_hw) and driver specific variables.
1592 */
5bb12791
LR		 1593static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1594 const struct ath_bus_ops *bus_ops)
ff37e337 1595{
cbe61d8a 1596 struct ath_hw *ah = NULL;
1510718d 1597 struct ath_common *common;
4f3acf81 1598 int r = 0, i;
ff37e337 1599 int csz = 0;
75d7839f 1600 int qnum;
ff37e337
S		 1601
1602 /* XXX: hardware will not be ready until ath_open() being called */
1603 sc->sc_flags |= SC_OP_INVALID;
88b126af 1604
c52f33d0 1605 spin_lock_init(&sc->wiphy_lock);
ff37e337 1606 spin_lock_init(&sc->sc_resetlock);
6158425b 1607 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1608 spin_lock_init(&sc->ani_lock);
04717ccd 1609 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1610 mutex_init(&sc->mutex);
ff37e337 1611 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1612 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1613 (unsigned long)sc);
1614
4f3acf81
LR		 1615 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1616 if (!ah) {
4f3acf81
LR		 1617 r = -ENOMEM;
1618 goto bad_no_ah;
1619 }
1620
1621 ah->ah_sc = sc;
8df5d1b7 1622 ah->hw_version.devid = devid;
aeac355d 1623 ah->hw_version.subsysid = subsysid;
e1e2f93f 1624 sc->sc_ah = ah;
4f3acf81 1625
27c51f1a 1626 common = ath9k_hw_common(ah);
9e4bffd2 1627 common->ops = &ath9k_common_ops;
5bb12791 1628 common->bus_ops = bus_ops;
13b81559 1629 common->ah = ah;
b002a4a9 1630 common->hw = sc->hw;
27c51f1a
LR		 1631
1632 /*
1633 * Cache line size is used to size and align various
1634 * structures used to communicate with the hardware.
1635 */
5bb12791 1636 ath_read_cachesize(common, &csz);
27c51f1a
LR		 1637 /* XXX assert csz is non-zero */
1638 common->cachelsz = csz << 2; /* convert to bytes */
1639
4d6b228d
LR		 1640 if (ath9k_init_debug(ah) < 0)
1641 dev_err(sc->dev, "Unable to create debugfs files\n");
1642
f637cfd6 1643 r = ath9k_hw_init(ah);
4f3acf81 1644 if (r) {
c46917bb
LR		 1645 ath_print(common, ATH_DBG_FATAL,
1646 "Unable to initialize hardware; "
1647 "initialization status: %d\n", r);
ff37e337
S		 1648 goto bad;
1649 }
ff37e337
S		 1650
1651 /* Get the hardware key cache size. */
2660b81a 1652 sc->keymax = ah->caps.keycache_size;
17d7904d 1653 if (sc->keymax > ATH_KEYMAX) {
c46917bb
LR		 1654 ath_print(common, ATH_DBG_ANY,
1655 "Warning, using only %u entries in %u key cache\n",
1656 ATH_KEYMAX, sc->keymax);
17d7904d 1657 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1658 }
1659
1660 /*
1661 * Reset the key cache since some parts do not
1662 * reset the contents on initial power up.
1663 */
17d7904d 1664 for (i = 0; i < sc->keymax; i++)
ff37e337 1665 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1666
ff37e337 1667 /* default to MONITOR mode */
2660b81a 1668 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1669
ff37e337
S		 1670 /* Setup rate tables */
1671
1672 ath_rate_attach(sc);
1673 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1674 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1675
1676 /*
1677 * Allocate hardware transmit queues: one queue for
1678 * beacon frames and one data queue for each QoS
1679 * priority. Note that the hal handles reseting
1680 * these queues at the needed time.
1681 */
b77f483f
S		 1682 sc->beacon.beaconq = ath_beaconq_setup(ah);
1683 if (sc->beacon.beaconq == -1) {
c46917bb
LR		 1684 ath_print(common, ATH_DBG_FATAL,
1685 "Unable to setup a beacon xmit queue\n");
4f3acf81 1686 r = -EIO;
ff37e337
S		 1687 goto bad2;
1688 }
b77f483f
S		 1689 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1690 if (sc->beacon.cabq == NULL) {
c46917bb
LR		 1691 ath_print(common, ATH_DBG_FATAL,
1692 "Unable to setup CAB xmit queue\n");
4f3acf81 1693 r = -EIO;
ff37e337
S		 1694 goto bad2;
1695 }
1696
17d7904d 1697 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1698 ath_cabq_update(sc);
1699
b77f483f
S		 1700 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1701 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1702
1703 /* Setup data queues */
1704 /* NB: ensure BK queue is the lowest priority h/w queue */
1705 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
c46917bb
LR		 1706 ath_print(common, ATH_DBG_FATAL,
1707 "Unable to setup xmit queue for BK traffic\n");
4f3acf81 1708 r = -EIO;
ff37e337
S		 1709 goto bad2;
1710 }
1711
1712 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
c46917bb
LR		 1713 ath_print(common, ATH_DBG_FATAL,
1714 "Unable to setup xmit queue for BE traffic\n");
4f3acf81 1715 r = -EIO;
ff37e337
S		 1716 goto bad2;
1717 }
1718 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
c46917bb
LR		 1719 ath_print(common, ATH_DBG_FATAL,
1720 "Unable to setup xmit queue for VI traffic\n");
4f3acf81 1721 r = -EIO;
ff37e337
S		 1722 goto bad2;
1723 }
1724 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
c46917bb
LR		 1725 ath_print(common, ATH_DBG_FATAL,
1726 "Unable to setup xmit queue for VO traffic\n");
4f3acf81 1727 r = -EIO;
ff37e337
S		 1728 goto bad2;
1729 }
1730
1731 /* Initializes the noise floor to a reasonable default value.
1732 * Later on this will be updated during ANI processing. */
1733
17d7904d
S		 1734 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1735 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1736
1737 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1738 ATH9K_CIPHER_TKIP, NULL)) {
1739 /*
1740 * Whether we should enable h/w TKIP MIC.
1741 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1742 * report WMM capable, so it's always safe to turn on
1743 * TKIP MIC in this case.
1744 */
1745 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1746 0, 1, NULL);
1747 }
1748
1749 /*
1750 * Check whether the separate key cache entries
1751 * are required to handle both tx+rx MIC keys.
1752 * With split mic keys the number of stations is limited
1753 * to 27 otherwise 59.
1754 */
1755 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1756 ATH9K_CIPHER_TKIP, NULL)
1757 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1758 ATH9K_CIPHER_MIC, NULL)
1759 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1760 0, NULL))
17d7904d 1761 sc->splitmic = 1;
ff37e337
S		 1762
1763 /* turn on mcast key search if possible */
1764 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1765 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1766 1, NULL);
1767
17d7904d 1768 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1769
1770 /* 11n Capabilities */
2660b81a 1771 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1772 sc->sc_flags |= SC_OP_TXAGGR;
1773 sc->sc_flags |= SC_OP_RXAGGR;
1774 }
1775
43c27613
LR		 1776 common->tx_chainmask = ah->caps.tx_chainmask;
1777 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1778
1779 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1780 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1781
8ca21f01 1782 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1510718d 1783 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1784
b77f483f 1785 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1786
1787 /* initialize beacon slots */
c52f33d0 1788 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1789 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1790 sc->beacon.bslot_aphy[i] = NULL;
1791 }
ff37e337 1792
ff37e337
S		 1793 /* setup channels and rates */
1794
5f8e077c 1795 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1796 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1797 sc->rates[IEEE80211_BAND_2GHZ];
1798 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1799 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1800 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1801
2660b81a 1802 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1803 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1804 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1805 sc->rates[IEEE80211_BAND_5GHZ];
1806 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1807 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1808 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1809 }
1810
766ec4a9 1811 switch (ah->btcoex_hw.scheme) {
75d7839f
LR		 1812 case ATH_BTCOEX_CFG_NONE:
1813 break;
1814 case ATH_BTCOEX_CFG_2WIRE:
1815 ath9k_hw_btcoex_init_2wire(ah);
1816 break;
1817 case ATH_BTCOEX_CFG_3WIRE:
1818 ath9k_hw_btcoex_init_3wire(ah);
1819 r = ath_init_btcoex_timer(sc);
1773912b
VT		 1820 if (r)
1821 goto bad2;
75d7839f 1822 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
766ec4a9 1823 ath9k_hw_init_btcoex_hw(ah, qnum);
e08a6ace 1824 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
75d7839f
LR		 1825 break;
1826 default:
1827 WARN_ON(1);
1828 break;
1773912b 1829 }
c97c92d9 1830
ff37e337
S		 1831 return 0;
1832bad2:
1833 /* cleanup tx queues */
1834 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1835 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1836 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337 1837bad:
95fafca2 1838 ath9k_hw_detach(ah);
4f3acf81 1839bad_no_ah:
4d6b228d
LR		 1840 ath9k_exit_debug(sc->sc_ah);
1841 sc->sc_ah = NULL;
ff37e337 1842
4f3acf81 1843 return r;
ff37e337
S		 1844}
1845
c52f33d0 1846void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1847{
9c84b797
S		 1848 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1849 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1850 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1851 IEEE80211_HW_AMPDU_AGGREGATION |
1852 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1853 IEEE80211_HW_PS_NULLFUNC_STACK |
1854 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1855
b3bd89ce 1856 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1857 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1858
9c84b797
S		 1859 hw->wiphy->interface_modes =
1860 BIT(NL80211_IFTYPE_AP) |
1861 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1862 BIT(NL80211_IFTYPE_ADHOC) |
1863 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1864
8feceb67 1865 hw->queues = 4;
e63835b0 1866 hw->max_rates = 4;
171387ef 1867 hw->channel_change_time = 5000;
465ca84d 1868 hw->max_listen_interval = 10;
dd190183
LR		 1869 /* Hardware supports 10 but we use 4 */
1870 hw->max_rate_tries = 4;
528f0c6b 1871 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1872 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1873
8feceb67 1874 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1875
c52f33d0
JM		 1876 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1877 &sc->sbands[IEEE80211_BAND_2GHZ];
1878 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1879 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1880 &sc->sbands[IEEE80211_BAND_5GHZ];
1881}
1882
1e40bcfa 1883/* Device driver core initialization */
5bb12791
LR		 1884int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1885 const struct ath_bus_ops *bus_ops)
c52f33d0
JM		 1886{
1887 struct ieee80211_hw *hw = sc->hw;
1510718d 1888 struct ath_common *common;
4d6b228d 1889 struct ath_hw *ah;
c52f33d0 1890 int error = 0, i;
3a702e49 1891 struct ath_regulatory *reg;
c52f33d0 1892
4d6b228d 1893 dev_dbg(sc->dev, "Attach ATH hw\n");
c52f33d0 1894
5bb12791 1895 error = ath_init_softc(devid, sc, subsysid, bus_ops);
c52f33d0
JM		 1896 if (error != 0)
1897 return error;
1898
4d6b228d 1899 ah = sc->sc_ah;
1510718d 1900 common = ath9k_hw_common(ah);
4d6b228d 1901
c52f33d0
JM		 1902 /* get mac address from hardware and set in mac80211 */
1903
1510718d 1904 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
c52f33d0
JM		 1905
1906 ath_set_hw_capab(sc, hw);
1907
1510718d 1908 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
c26c2e57
LR		 1909 ath9k_reg_notifier);
1910 if (error)
1911 return error;
1912
1510718d 1913 reg = &common->regulatory;
c26c2e57 1914
4d6b228d 1915 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1916 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
4d6b228d 1917 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
eb2599ca 1918 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1919 }
1920
db93e7b5
SB		 1921 /* initialize tx/rx engine */
1922 error = ath_tx_init(sc, ATH_TXBUF);
1923 if (error != 0)
40b130a9 1924 goto error_attach;
8feceb67 1925
db93e7b5
SB		 1926 error = ath_rx_init(sc, ATH_RXBUF);
1927 if (error != 0)
40b130a9 1928 goto error_attach;
8feceb67 1929
0e2dedf9 1930 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1931 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1932 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1933
db93e7b5 1934 error = ieee80211_register_hw(hw);
8feceb67 1935
3a702e49 1936 if (!ath_is_world_regd(reg)) {
c02cf373 1937 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1938 if (error)
1939 goto error_attach;
1940 }
5f8e077c 1941
db93e7b5
SB		 1942 /* Initialize LED control */
1943 ath_init_leds(sc);
8feceb67 1944
3b319aae 1945 ath_start_rfkill_poll(sc);
5f8e077c 1946
8feceb67 1947 return 0;
40b130a9
VT		 1948
1949error_attach:
1950 /* cleanup tx queues */
1951 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1952 if (ATH_TXQ_SETUP(sc, i))
1953 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1954
4d6b228d
LR		 1955 ath9k_hw_detach(ah);
1956 ath9k_exit_debug(ah);
3ce1b1a9 1957 sc->sc_ah = NULL;
40b130a9 1958
8feceb67 1959 return error;
f078f209
LR		 1960}
1961
ff37e337
S		 1962int ath_reset(struct ath_softc *sc, bool retry_tx)
1963{
cbe61d8a 1964 struct ath_hw *ah = sc->sc_ah;
c46917bb 1965 struct ath_common *common = ath9k_hw_common(ah);
030bb495 1966 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1967 int r;
ff37e337
S		 1968
1969 ath9k_hw_set_interrupts(ah, 0);
043a0405 1970 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1971 ath_stoprecv(sc);
1972 ath_flushrecv(sc);
1973
1974 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1975 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1976 if (r)
c46917bb
LR		 1977 ath_print(common, ATH_DBG_FATAL,
1978 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1979 spin_unlock_bh(&sc->sc_resetlock);
1980
1981 if (ath_startrecv(sc) != 0)
c46917bb
LR		 1982 ath_print(common, ATH_DBG_FATAL,
1983 "Unable to start recv logic\n");
ff37e337
S		 1984
1985 /*
1986 * We may be doing a reset in response to a request
1987 * that changes the channel so update any state that
1988 * might change as a result.
1989 */
ce111bad 1990 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1991
1992 ath_update_txpow(sc);
1993
1994 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1995 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1996
17d7904d 1997 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1998
1999 if (retry_tx) {
2000 int i;
2001 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2002 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 2003 spin_lock_bh(&sc->tx.txq[i].axq_lock);
2004 ath_txq_schedule(sc, &sc->tx.txq[i]);
2005 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 2006 }
2007 }
2008 }
2009
ae8d2858 2010 return r;
ff37e337
S		 2011}
2012
2013/*
2014 * This function will allocate both the DMA descriptor structure, and the
2015 * buffers it contains. These are used to contain the descriptors used
2016 * by the system.
2017*/
2018int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2019 struct list_head *head, const char *name,
2020 int nbuf, int ndesc)
2021{
2022#define DS2PHYS(_dd, _ds) \
2023 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2024#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2025#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
c46917bb 2026 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
ff37e337
S		 2027 struct ath_desc *ds;
2028 struct ath_buf *bf;
2029 int i, bsize, error;
2030
c46917bb
LR		 2031 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2032 name, nbuf, ndesc);
ff37e337 2033
b03a9db9 2034 INIT_LIST_HEAD(head);
ff37e337
S		 2035 /* ath_desc must be a multiple of DWORDs */
2036 if ((sizeof(struct ath_desc) % 4) != 0) {
c46917bb
LR		 2037 ath_print(common, ATH_DBG_FATAL,
2038 "ath_desc not DWORD aligned\n");
9680e8a3 2039 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
ff37e337
S		 2040 error = -ENOMEM;
2041 goto fail;
2042 }
2043
ff37e337
S		 2044 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2045
2046 /*
2047 * Need additional DMA memory because we can't use
2048 * descriptors that cross the 4K page boundary. Assume
2049 * one skipped descriptor per 4K page.
2050 */
2660b81a 2051 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 2052 u32 ndesc_skipped =
2053 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2054 u32 dma_len;
2055
2056 while (ndesc_skipped) {
2057 dma_len = ndesc_skipped * sizeof(struct ath_desc);
2058 dd->dd_desc_len += dma_len;
2059
2060 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2061 };
2062 }
2063
2064 /* allocate descriptors */
7da3c55c 2065 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 2066 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 2067 if (dd->dd_desc == NULL) {
2068 error = -ENOMEM;
2069 goto fail;
2070 }
2071 ds = dd->dd_desc;
c46917bb
LR		 2072 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2073 name, ds, (u32) dd->dd_desc_len,
2074 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
ff37e337
S		 2075
2076 /* allocate buffers */
2077 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 2078 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 2079 if (bf == NULL) {
2080 error = -ENOMEM;
2081 goto fail2;
2082 }
ff37e337
S		 2083 dd->dd_bufptr = bf;
2084
ff37e337
S		 2085 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2086 bf->bf_desc = ds;
2087 bf->bf_daddr = DS2PHYS(dd, ds);
2088
2660b81a 2089 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 2090 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2091 /*
2092 * Skip descriptor addresses which can cause 4KB
2093 * boundary crossing (addr + length) with a 32 dword
2094 * descriptor fetch.
2095 */
2096 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
9680e8a3 2097 BUG_ON((caddr_t) bf->bf_desc >=
ff37e337
S		 2098 ((caddr_t) dd->dd_desc +
2099 dd->dd_desc_len));
2100
2101 ds += ndesc;
2102 bf->bf_desc = ds;
2103 bf->bf_daddr = DS2PHYS(dd, ds);
2104 }
2105 }
2106 list_add_tail(&bf->list, head);
2107 }
2108 return 0;
2109fail2:
7da3c55c
GJ		 2110 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2111 dd->dd_desc_paddr);
ff37e337
S		 2112fail:
2113 memset(dd, 0, sizeof(*dd));
2114 return error;
2115#undef ATH_DESC_4KB_BOUND_CHECK
2116#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2117#undef DS2PHYS
2118}
2119
2120void ath_descdma_cleanup(struct ath_softc *sc,
2121 struct ath_descdma *dd,
2122 struct list_head *head)
2123{
7da3c55c
GJ		 2124 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2125 dd->dd_desc_paddr);
ff37e337
S		 2126
2127 INIT_LIST_HEAD(head);
2128 kfree(dd->dd_bufptr);
2129 memset(dd, 0, sizeof(*dd));
2130}
2131
2132int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2133{
2134 int qnum;
2135
2136 switch (queue) {
2137 case 0:
b77f483f 2138 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 2139 break;
2140 case 1:
b77f483f 2141 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 2142 break;
2143 case 2:
b77f483f 2144 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2145 break;
2146 case 3:
b77f483f 2147 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 2148 break;
2149 default:
b77f483f 2150 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2151 break;
2152 }
2153
2154 return qnum;
2155}
2156
2157int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2158{
2159 int qnum;
2160
2161 switch (queue) {
2162 case ATH9K_WME_AC_VO:
2163 qnum = 0;
2164 break;
2165 case ATH9K_WME_AC_VI:
2166 qnum = 1;
2167 break;
2168 case ATH9K_WME_AC_BE:
2169 qnum = 2;
2170 break;
2171 case ATH9K_WME_AC_BK:
2172 qnum = 3;
2173 break;
2174 default:
2175 qnum = -1;
2176 break;
2177 }
2178
2179 return qnum;
2180}
2181
5f8e077c
LR		 2182/* XXX: Remove me once we don't depend on ath9k_channel for all
2183 * this redundant data */
0e2dedf9
JM		 2184void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2185 struct ath9k_channel *ichan)
5f8e077c 2186{
5f8e077c
LR		 2187 struct ieee80211_channel *chan = hw->conf.channel;
2188 struct ieee80211_conf *conf = &hw->conf;
2189
2190 ichan->channel = chan->center_freq;
2191 ichan->chan = chan;
2192
2193 if (chan->band == IEEE80211_BAND_2GHZ) {
2194 ichan->chanmode = CHANNEL_G;
8813262e 2195 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR		 2196 } else {
2197 ichan->chanmode = CHANNEL_A;
2198 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2199 }
2200
25c56eec 2201 if (conf_is_ht(conf))
5f8e077c
LR		 2202 ichan->chanmode = ath_get_extchanmode(sc, chan,
2203 conf->channel_type);
5f8e077c
LR		 2204}
2205
ff37e337
S		 2206/**********************/
2207/* mac80211 callbacks */
2208/**********************/
2209
75d7839f
LR		 2210/*
2211 * (Re)start btcoex timers
2212 */
2213static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2214{
2215 struct ath_btcoex *btcoex = &sc->btcoex;
2216 struct ath_hw *ah = sc->sc_ah;
2217
c46917bb
LR		 2218 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2219 "Starting btcoex timers");
75d7839f
LR		 2220
2221 /* make sure duty cycle timer is also stopped when resuming */
2222 if (btcoex->hw_timer_enabled)
cd9bf689 2223 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
75d7839f
LR		 2224
2225 btcoex->bt_priority_cnt = 0;
2226 btcoex->bt_priority_time = jiffies;
2227 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2228
2229 mod_timer(&btcoex->period_timer, jiffies);
2230}
2231
8feceb67 2232static int ath9k_start(struct ieee80211_hw *hw)
f078f209 2233{
bce048d7
JM		 2234 struct ath_wiphy *aphy = hw->priv;
2235 struct ath_softc *sc = aphy->sc;
af03abec 2236 struct ath_hw *ah = sc->sc_ah;
c46917bb 2237 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 2238 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 2239 struct ath9k_channel *init_channel;
82880a7c 2240 int r;
f078f209 2241
c46917bb
LR		 2242 ath_print(common, ATH_DBG_CONFIG,
2243 "Starting driver with initial channel: %d MHz\n",
2244 curchan->center_freq);
f078f209 2245
141b38b6
S		 2246 mutex_lock(&sc->mutex);
2247
9580a222
JM		 2248 if (ath9k_wiphy_started(sc)) {
2249 if (sc->chan_idx == curchan->hw_value) {
2250 /*
2251 * Already on the operational channel, the new wiphy
2252 * can be marked active.
2253 */
2254 aphy->state = ATH_WIPHY_ACTIVE;
2255 ieee80211_wake_queues(hw);
2256 } else {
2257 /*
2258 * Another wiphy is on another channel, start the new
2259 * wiphy in paused state.
2260 */
2261 aphy->state = ATH_WIPHY_PAUSED;
2262 ieee80211_stop_queues(hw);
2263 }
2264 mutex_unlock(&sc->mutex);
2265 return 0;
2266 }
2267 aphy->state = ATH_WIPHY_ACTIVE;
2268
8feceb67 2269 /* setup initial channel */
f078f209 2270
82880a7c 2271 sc->chan_idx = curchan->hw_value;
f078f209 2272
82880a7c 2273 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 2274
2275 /* Reset SERDES registers */
af03abec 2276 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S		 2277
2278 /*
2279 * The basic interface to setting the hardware in a good
2280 * state is ``reset''. On return the hardware is known to
2281 * be powered up and with interrupts disabled. This must
2282 * be followed by initialization of the appropriate bits
2283 * and then setup of the interrupt mask.
2284 */
2285 spin_lock_bh(&sc->sc_resetlock);
af03abec 2286 r = ath9k_hw_reset(ah, init_channel, false);
ae8d2858 2287 if (r) {
c46917bb
LR		 2288 ath_print(common, ATH_DBG_FATAL,
2289 "Unable to reset hardware; reset status %d "
2290 "(freq %u MHz)\n", r,
2291 curchan->center_freq);
ff37e337 2292 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2293 goto mutex_unlock;
ff37e337
S		 2294 }
2295 spin_unlock_bh(&sc->sc_resetlock);
2296
2297 /*
2298 * This is needed only to setup initial state
2299 * but it's best done after a reset.
2300 */
2301 ath_update_txpow(sc);
8feceb67 2302
ff37e337
S		 2303 /*
2304 * Setup the hardware after reset:
2305 * The receive engine is set going.
2306 * Frame transmit is handled entirely
2307 * in the frame output path; there's nothing to do
2308 * here except setup the interrupt mask.
2309 */
2310 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 2311 ath_print(common, ATH_DBG_FATAL,
2312 "Unable to start recv logic\n");
141b38b6
S		 2313 r = -EIO;
2314 goto mutex_unlock;
f078f209 2315 }
8feceb67 2316
ff37e337 2317 /* Setup our intr mask. */
17d7904d 2318 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2319 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2320 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2321
af03abec 2322 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2323 sc->imask |= ATH9K_INT_GTT;
ff37e337 2324
af03abec 2325 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2326 sc->imask |= ATH9K_INT_CST;
ff37e337 2327
ce111bad 2328 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2329
2330 sc->sc_flags &= ~SC_OP_INVALID;
2331
2332 /* Disable BMISS interrupt when we're not associated */
17d7904d 2333 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
af03abec 2334 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337 2335
bce048d7 2336 ieee80211_wake_queues(hw);
ff37e337 2337
42935eca 2338 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 2339
766ec4a9
LR		 2340 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2341 !ah->btcoex_hw.enabled) {
5e197292
LR		 2342 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2343 AR_STOMP_LOW_WLAN_WGHT);
af03abec 2344 ath9k_hw_btcoex_enable(ah);
f985ad12 2345
5bb12791
LR		 2346 if (common->bus_ops->bt_coex_prep)
2347 common->bus_ops->bt_coex_prep(common);
766ec4a9 2348 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2349 ath9k_btcoex_timer_resume(sc);
1773912b
VT		 2350 }
2351
141b38b6
S		 2352mutex_unlock:
2353 mutex_unlock(&sc->mutex);
2354
ae8d2858 2355 return r;
f078f209
LR		 2356}
2357
8feceb67
VT		 2358static int ath9k_tx(struct ieee80211_hw *hw,
2359 struct sk_buff *skb)
f078f209 2360{
528f0c6b 2361 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2362 struct ath_wiphy *aphy = hw->priv;
2363 struct ath_softc *sc = aphy->sc;
c46917bb 2364 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 2365 struct ath_tx_control txctl;
8feceb67 2366 int hdrlen, padsize;
528f0c6b 2367
8089cc47 2368 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
c46917bb
LR		 2369 ath_print(common, ATH_DBG_XMIT,
2370 "ath9k: %s: TX in unexpected wiphy state "
2371 "%d\n", wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM		 2372 goto exit;
2373 }
2374
96148326 2375 if (sc->ps_enabled) {
dc8c4585
JM		 2376 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2377 /*
2378 * mac80211 does not set PM field for normal data frames, so we
2379 * need to update that based on the current PS mode.
2380 */
2381 if (ieee80211_is_data(hdr->frame_control) &&
2382 !ieee80211_is_nullfunc(hdr->frame_control) &&
2383 !ieee80211_has_pm(hdr->frame_control)) {
c46917bb
LR		 2384 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2385 "while in PS mode\n");
dc8c4585
JM		 2386 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2387 }
2388 }
2389
9a23f9ca
JM		 2390 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2391 /*
2392 * We are using PS-Poll and mac80211 can request TX while in
2393 * power save mode. Need to wake up hardware for the TX to be
2394 * completed and if needed, also for RX of buffered frames.
2395 */
2396 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2397 ath9k_ps_wakeup(sc);
2398 ath9k_hw_setrxabort(sc->sc_ah, 0);
2399 if (ieee80211_is_pspoll(hdr->frame_control)) {
c46917bb
LR		 2400 ath_print(common, ATH_DBG_PS,
2401 "Sending PS-Poll to pick a buffered frame\n");
9a23f9ca
JM		 2402 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2403 } else {
c46917bb
LR		 2404 ath_print(common, ATH_DBG_PS,
2405 "Wake up to complete TX\n");
9a23f9ca
JM		 2406 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2407 }
2408 /*
2409 * The actual restore operation will happen only after
2410 * the sc_flags bit is cleared. We are just dropping
2411 * the ps_usecount here.
2412 */
2413 ath9k_ps_restore(sc);
2414 }
2415
528f0c6b 2416 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2417
8feceb67
VT		 2418 /*
2419 * As a temporary workaround, assign seq# here; this will likely need
2420 * to be cleaned up to work better with Beacon transmission and virtual
2421 * BSSes.
2422 */
2423 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2424 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2425 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2426 sc->tx.seq_no += 0x10;
8feceb67 2427 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2428 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2429 }
f078f209 2430
8feceb67
VT		 2431 /* Add the padding after the header if this is not already done */
2432 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2433 if (hdrlen & 3) {
2434 padsize = hdrlen % 4;
2435 if (skb_headroom(skb) < padsize)
2436 return -1;
2437 skb_push(skb, padsize);
2438 memmove(skb->data, skb->data + padsize, hdrlen);
2439 }
2440
528f0c6b
S		 2441 /* Check if a tx queue is available */
2442
2443 txctl.txq = ath_test_get_txq(sc, skb);
2444 if (!txctl.txq)
2445 goto exit;
2446
c46917bb 2447 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2448
c52f33d0 2449 if (ath_tx_start(hw, skb, &txctl) != 0) {
c46917bb 2450 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2451 goto exit;
8feceb67
VT		 2452 }
2453
528f0c6b
S		 2454 return 0;
2455exit:
2456 dev_kfree_skb_any(skb);
8feceb67 2457 return 0;
f078f209
LR		 2458}
2459
75d7839f
LR		 2460/*
2461 * Pause btcoex timer and bt duty cycle timer
2462 */
2463static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2464{
2465 struct ath_btcoex *btcoex = &sc->btcoex;
2466 struct ath_hw *ah = sc->sc_ah;
2467
2468 del_timer_sync(&btcoex->period_timer);
2469
2470 if (btcoex->hw_timer_enabled)
cd9bf689 2471 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
75d7839f
LR		 2472
2473 btcoex->hw_timer_enabled = false;
2474}
2475
8feceb67 2476static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2477{
bce048d7
JM		 2478 struct ath_wiphy *aphy = hw->priv;
2479 struct ath_softc *sc = aphy->sc;
af03abec 2480 struct ath_hw *ah = sc->sc_ah;
c46917bb 2481 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2482
4c483817
S		 2483 mutex_lock(&sc->mutex);
2484
9580a222
JM		 2485 aphy->state = ATH_WIPHY_INACTIVE;
2486
c94dbff7
LR		 2487 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2488 cancel_delayed_work_sync(&sc->tx_complete_work);
2489
2490 if (!sc->num_sec_wiphy) {
2491 cancel_delayed_work_sync(&sc->wiphy_work);
2492 cancel_work_sync(&sc->chan_work);
2493 }
2494
9c84b797 2495 if (sc->sc_flags & SC_OP_INVALID) {
c46917bb 2496 ath_print(common, ATH_DBG_ANY, "Device not present\n");
4c483817 2497 mutex_unlock(&sc->mutex);
9c84b797
S		 2498 return;
2499 }
8feceb67 2500
9580a222
JM		 2501 if (ath9k_wiphy_started(sc)) {
2502 mutex_unlock(&sc->mutex);
2503 return; /* another wiphy still in use */
2504 }
2505
766ec4a9 2506 if (ah->btcoex_hw.enabled) {
af03abec 2507 ath9k_hw_btcoex_disable(ah);
766ec4a9 2508 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2509 ath9k_btcoex_timer_pause(sc);
1773912b
VT		 2510 }
2511
ff37e337
S		 2512 /* make sure h/w will not generate any interrupt
2513 * before setting the invalid flag. */
af03abec 2514 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S		 2515
2516 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2517 ath_drain_all_txq(sc, false);
ff37e337 2518 ath_stoprecv(sc);
af03abec 2519 ath9k_hw_phy_disable(ah);
ff37e337 2520 } else
b77f483f 2521 sc->rx.rxlink = NULL;
ff37e337 2522
ff37e337 2523 /* disable HAL and put h/w to sleep */
af03abec
LR		 2524 ath9k_hw_disable(ah);
2525 ath9k_hw_configpcipowersave(ah, 1, 1);
9ecdef4b 2526 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ff37e337
S		 2527
2528 sc->sc_flags |= SC_OP_INVALID;
500c064d 2529
141b38b6
S		 2530 mutex_unlock(&sc->mutex);
2531
c46917bb 2532 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2533}
2534
8feceb67
VT		 2535static int ath9k_add_interface(struct ieee80211_hw *hw,
2536 struct ieee80211_if_init_conf *conf)
f078f209 2537{
bce048d7
JM		 2538 struct ath_wiphy *aphy = hw->priv;
2539 struct ath_softc *sc = aphy->sc;
c46917bb 2540 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
17d7904d 2541 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2542 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2543 int ret = 0;
8feceb67 2544
141b38b6
S		 2545 mutex_lock(&sc->mutex);
2546
8ca21f01
JM		 2547 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2548 sc->nvifs > 0) {
2549 ret = -ENOBUFS;
2550 goto out;
2551 }
2552
8feceb67 2553 switch (conf->type) {
05c914fe 2554 case NL80211_IFTYPE_STATION:
d97809db 2555 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2556 break;
05c914fe 2557 case NL80211_IFTYPE_ADHOC:
05c914fe 2558 case NL80211_IFTYPE_AP:
9cb5412b 2559 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2560 if (sc->nbcnvifs >= ATH_BCBUF) {
2561 ret = -ENOBUFS;
2562 goto out;
2563 }
9cb5412b 2564 ic_opmode = conf->type;
f078f209
LR		 2565 break;
2566 default:
c46917bb 2567 ath_print(common, ATH_DBG_FATAL,
04bd4638 2568 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2569 ret = -EOPNOTSUPP;
2570 goto out;
f078f209
LR		 2571 }
2572
c46917bb
LR		 2573 ath_print(common, ATH_DBG_CONFIG,
2574 "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2575
17d7904d 2576 /* Set the VIF opmode */
5640b08e
S		 2577 avp->av_opmode = ic_opmode;
2578 avp->av_bslot = -1;
2579
2c3db3d5 2580 sc->nvifs++;
8ca21f01
JM		 2581
2582 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2583 ath9k_set_bssid_mask(hw);
2584
2c3db3d5
JM		 2585 if (sc->nvifs > 1)
2586 goto out; /* skip global settings for secondary vif */
2587
b238e90e 2588 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2589 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2590 sc->sc_flags |= SC_OP_TSF_RESET;
2591 }
5640b08e 2592
5640b08e 2593 /* Set the device opmode */
2660b81a 2594 sc->sc_ah->opmode = ic_opmode;
5640b08e 2595
4e30ffa2
VN		 2596 /*
2597 * Enable MIB interrupts when there are hardware phy counters.
2598 * Note we only do this (at the moment) for station mode.
2599 */
4af9cf4f 2600 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2601 (conf->type == NL80211_IFTYPE_ADHOC) ||
2602 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 2603 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S		 2604 sc->imask |= ATH9K_INT_TSFOOR;
2605 }
2606
17d7904d 2607 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2608
f38faa31
SB		 2609 if (conf->type == NL80211_IFTYPE_AP ||
2610 conf->type == NL80211_IFTYPE_ADHOC ||
2611 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2612 ath_start_ani(sc);
6f255425 2613
2c3db3d5 2614out:
141b38b6 2615 mutex_unlock(&sc->mutex);
2c3db3d5 2616 return ret;
f078f209
LR		 2617}
2618
8feceb67
VT		 2619static void ath9k_remove_interface(struct ieee80211_hw *hw,
2620 struct ieee80211_if_init_conf *conf)
f078f209 2621{
bce048d7
JM		 2622 struct ath_wiphy *aphy = hw->priv;
2623 struct ath_softc *sc = aphy->sc;
c46917bb 2624 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
17d7904d 2625 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2626 int i;
f078f209 2627
c46917bb 2628 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2629
141b38b6
S		 2630 mutex_lock(&sc->mutex);
2631
6f255425 2632 /* Stop ANI */
17d7904d 2633 del_timer_sync(&sc->ani.timer);
580f0b8a 2634
8feceb67 2635 /* Reclaim beacon resources */
9cb5412b
PE		 2636 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2637 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2638 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2639 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2640 ath_beacon_return(sc, avp);
580f0b8a 2641 }
f078f209 2642
8feceb67 2643 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2644
2c3db3d5
JM		 2645 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2646 if (sc->beacon.bslot[i] == conf->vif) {
2647 printk(KERN_DEBUG "%s: vif had allocated beacon "
2648 "slot\n", __func__);
2649 sc->beacon.bslot[i] = NULL;
c52f33d0 2650 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2651 }
2652 }
2653
17d7904d 2654 sc->nvifs--;
141b38b6
S		 2655
2656 mutex_unlock(&sc->mutex);
f078f209
LR		 2657}
2658
e8975581 2659static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2660{
bce048d7
JM		 2661 struct ath_wiphy *aphy = hw->priv;
2662 struct ath_softc *sc = aphy->sc;
c46917bb 2663 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e8975581 2664 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2665 struct ath_hw *ah = sc->sc_ah;
64839170 2666 bool all_wiphys_idle = false, disable_radio = false;
f078f209 2667
aa33de09 2668 mutex_lock(&sc->mutex);
141b38b6 2669
64839170
LR		 2670 /* Leave this as the first check */
2671 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2672
2673 spin_lock_bh(&sc->wiphy_lock);
2674 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2675 spin_unlock_bh(&sc->wiphy_lock);
2676
2677 if (conf->flags & IEEE80211_CONF_IDLE){
2678 if (all_wiphys_idle)
2679 disable_radio = true;
2680 }
2681 else if (all_wiphys_idle) {
2682 ath_radio_enable(sc);
c46917bb
LR		 2683 ath_print(common, ATH_DBG_CONFIG,
2684 "not-idle: enabling radio\n");
64839170
LR		 2685 }
2686 }
2687
3cbb5dd7
VN		 2688 if (changed & IEEE80211_CONF_CHANGE_PS) {
2689 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2690 if (!(ah->caps.hw_caps &
2691 ATH9K_HW_CAP_AUTOSLEEP)) {
2692 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2693 sc->imask |= ATH9K_INT_TIM_TIMER;
2694 ath9k_hw_set_interrupts(sc->sc_ah,
2695 sc->imask);
2696 }
2697 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2698 }
96148326 2699 sc->ps_enabled = true;
3cbb5dd7 2700 } else {
96148326 2701 sc->ps_enabled = false;
9ecdef4b 2702 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8782b41d
VN		 2703 if (!(ah->caps.hw_caps &
2704 ATH9K_HW_CAP_AUTOSLEEP)) {
2705 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2706 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2707 SC_OP_WAIT_FOR_CAB |
2708 SC_OP_WAIT_FOR_PSPOLL_DATA |
2709 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2710 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2711 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2712 ath9k_hw_set_interrupts(sc->sc_ah,
2713 sc->imask);
2714 }
3cbb5dd7
VN		 2715 }
2716 }
2717 }
2718
4797938c 2719 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2720 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2721 int pos = curchan->hw_value;
ae5eb026 2722
0e2dedf9
JM		 2723 aphy->chan_idx = pos;
2724 aphy->chan_is_ht = conf_is_ht(conf);
2725
8089cc47
JM		 2726 if (aphy->state == ATH_WIPHY_SCAN ||
2727 aphy->state == ATH_WIPHY_ACTIVE)
2728 ath9k_wiphy_pause_all_forced(sc, aphy);
2729 else {
2730 /*
2731 * Do not change operational channel based on a paused
2732 * wiphy changes.
2733 */
2734 goto skip_chan_change;
2735 }
0e2dedf9 2736
c46917bb
LR		 2737 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2738 curchan->center_freq);
f078f209 2739
5f8e077c 2740 /* XXX: remove me eventualy */
0e2dedf9 2741 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2742
ecf70441 2743 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2744
0e2dedf9 2745 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
c46917bb
LR		 2746 ath_print(common, ATH_DBG_FATAL,
2747 "Unable to set channel\n");
aa33de09 2748 mutex_unlock(&sc->mutex);
e11602b7
S		 2749 return -EINVAL;
2750 }
094d05dc 2751 }
f078f209 2752
8089cc47 2753skip_chan_change:
5c020dc6 2754 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2755 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2756
64839170 2757 if (disable_radio) {
c46917bb 2758 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
64839170
LR		 2759 ath_radio_disable(sc);
2760 }
2761
aa33de09 2762 mutex_unlock(&sc->mutex);
141b38b6 2763
f078f209
LR		 2764 return 0;
2765}
2766
8feceb67
VT		 2767#define SUPPORTED_FILTERS \
2768 (FIF_PROMISC_IN_BSS | \
2769 FIF_ALLMULTI | \
2770 FIF_CONTROL | \
af6a3fc7 2771 FIF_PSPOLL | \
8feceb67
VT		 2772 FIF_OTHER_BSS | \
2773 FIF_BCN_PRBRESP_PROMISC | \
2774 FIF_FCSFAIL)
c83be688 2775
8feceb67
VT		 2776/* FIXME: sc->sc_full_reset ? */
2777static void ath9k_configure_filter(struct ieee80211_hw *hw,
2778 unsigned int changed_flags,
2779 unsigned int *total_flags,
3ac64bee 2780 u64 multicast)
8feceb67 2781{
bce048d7
JM		 2782 struct ath_wiphy *aphy = hw->priv;
2783 struct ath_softc *sc = aphy->sc;
8feceb67 2784 u32 rfilt;
f078f209 2785
8feceb67
VT		 2786 changed_flags &= SUPPORTED_FILTERS;
2787 *total_flags &= SUPPORTED_FILTERS;
f078f209 2788
b77f483f 2789 sc->rx.rxfilter = *total_flags;
aa68aeaa 2790 ath9k_ps_wakeup(sc);
8feceb67
VT		 2791 rfilt = ath_calcrxfilter(sc);
2792 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2793 ath9k_ps_restore(sc);
f078f209 2794
c46917bb
LR		 2795 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2796 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 2797}
f078f209 2798
8feceb67
VT		 2799static void ath9k_sta_notify(struct ieee80211_hw *hw,
2800 struct ieee80211_vif *vif,
2801 enum sta_notify_cmd cmd,
17741cdc 2802 struct ieee80211_sta *sta)
8feceb67 2803{
bce048d7
JM		 2804 struct ath_wiphy *aphy = hw->priv;
2805 struct ath_softc *sc = aphy->sc;
f078f209 2806
8feceb67
VT		 2807 switch (cmd) {
2808 case STA_NOTIFY_ADD:
5640b08e 2809 ath_node_attach(sc, sta);
8feceb67
VT		 2810 break;
2811 case STA_NOTIFY_REMOVE:
b5aa9bf9 2812 ath_node_detach(sc, sta);
8feceb67
VT		 2813 break;
2814 default:
2815 break;
2816 }
f078f209
LR		 2817}
2818
141b38b6 2819static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2820 const struct ieee80211_tx_queue_params *params)
f078f209 2821{
bce048d7
JM		 2822 struct ath_wiphy *aphy = hw->priv;
2823 struct ath_softc *sc = aphy->sc;
c46917bb 2824 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67
VT		 2825 struct ath9k_tx_queue_info qi;
2826 int ret = 0, qnum;
f078f209 2827
8feceb67
VT		 2828 if (queue >= WME_NUM_AC)
2829 return 0;
f078f209 2830
141b38b6
S		 2831 mutex_lock(&sc->mutex);
2832
1ffb0610
S		 2833 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2834
8feceb67
VT		 2835 qi.tqi_aifs = params->aifs;
2836 qi.tqi_cwmin = params->cw_min;
2837 qi.tqi_cwmax = params->cw_max;
2838 qi.tqi_burstTime = params->txop;
2839 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2840
c46917bb
LR		 2841 ath_print(common, ATH_DBG_CONFIG,
2842 "Configure tx [queue/halq] [%d/%d], "
2843 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2844 queue, qnum, params->aifs, params->cw_min,
2845 params->cw_max, params->txop);
f078f209 2846
8feceb67
VT		 2847 ret = ath_txq_update(sc, qnum, &qi);
2848 if (ret)
c46917bb 2849 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2850
141b38b6
S		 2851 mutex_unlock(&sc->mutex);
2852
8feceb67
VT		 2853 return ret;
2854}
f078f209 2855
8feceb67
VT		 2856static int ath9k_set_key(struct ieee80211_hw *hw,
2857 enum set_key_cmd cmd,
dc822b5d
JB		 2858 struct ieee80211_vif *vif,
2859 struct ieee80211_sta *sta,
8feceb67
VT		 2860 struct ieee80211_key_conf *key)
2861{
bce048d7
JM		 2862 struct ath_wiphy *aphy = hw->priv;
2863 struct ath_softc *sc = aphy->sc;
c46917bb 2864 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 2865 int ret = 0;
f078f209 2866
b3bd89ce
JM		 2867 if (modparam_nohwcrypt)
2868 return -ENOSPC;
2869
141b38b6 2870 mutex_lock(&sc->mutex);
3cbb5dd7 2871 ath9k_ps_wakeup(sc);
c46917bb 2872 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2873
8feceb67
VT		 2874 switch (cmd) {
2875 case SET_KEY:
3f53dd64 2876 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2877 if (ret >= 0) {
2878 key->hw_key_idx = ret;
8feceb67
VT		 2879 /* push IV and Michael MIC generation to stack */
2880 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2881 if (key->alg == ALG_TKIP)
2882 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2883 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2884 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2885 ret = 0;
8feceb67
VT		 2886 }
2887 break;
2888 case DISABLE_KEY:
2889 ath_key_delete(sc, key);
8feceb67
VT		 2890 break;
2891 default:
2892 ret = -EINVAL;
2893 }
f078f209 2894
3cbb5dd7 2895 ath9k_ps_restore(sc);
141b38b6
S		 2896 mutex_unlock(&sc->mutex);
2897
8feceb67
VT		 2898 return ret;
2899}
f078f209 2900
8feceb67
VT		 2901static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2902 struct ieee80211_vif *vif,
2903 struct ieee80211_bss_conf *bss_conf,
2904 u32 changed)
2905{
bce048d7
JM		 2906 struct ath_wiphy *aphy = hw->priv;
2907 struct ath_softc *sc = aphy->sc;
2d0ddec5 2908 struct ath_hw *ah = sc->sc_ah;
1510718d 2909 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5
JB		 2910 struct ath_vif *avp = (void *)vif->drv_priv;
2911 u32 rfilt = 0;
2912 int error, i;
f078f209 2913
141b38b6
S		 2914 mutex_lock(&sc->mutex);
2915
2d0ddec5
JB		 2916 /*
2917 * TODO: Need to decide which hw opmode to use for
2918 * multi-interface cases
2919 * XXX: This belongs into add_interface!
2920 */
2921 if (vif->type == NL80211_IFTYPE_AP &&
2922 ah->opmode != NL80211_IFTYPE_AP) {
2923 ah->opmode = NL80211_IFTYPE_STATION;
2924 ath9k_hw_setopmode(ah);
1510718d
LR		 2925 memcpy(common->curbssid, common->macaddr, ETH_ALEN);
2926 common->curaid = 0;
f2b2143e 2927 ath9k_hw_write_associd(ah);
2d0ddec5
JB		 2928 /* Request full reset to get hw opmode changed properly */
2929 sc->sc_flags |= SC_OP_FULL_RESET;
2930 }
2931
2932 if ((changed & BSS_CHANGED_BSSID) &&
2933 !is_zero_ether_addr(bss_conf->bssid)) {
2934 switch (vif->type) {
2935 case NL80211_IFTYPE_STATION:
2936 case NL80211_IFTYPE_ADHOC:
2937 case NL80211_IFTYPE_MESH_POINT:
2938 /* Set BSSID */
1510718d 2939 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2d0ddec5 2940 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 2941 common->curaid = 0;
f2b2143e 2942 ath9k_hw_write_associd(ah);
2d0ddec5
JB		 2943
2944 /* Set aggregation protection mode parameters */
2945 sc->config.ath_aggr_prot = 0;
2946
c46917bb
LR		 2947 ath_print(common, ATH_DBG_CONFIG,
2948 "RX filter 0x%x bssid %pM aid 0x%x\n",
2949 rfilt, common->curbssid, common->curaid);
2d0ddec5
JB		 2950
2951 /* need to reconfigure the beacon */
2952 sc->sc_flags &= ~SC_OP_BEACONS ;
2953
2954 break;
2955 default:
2956 break;
2957 }
2958 }
2959
2960 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2961 (vif->type == NL80211_IFTYPE_AP) ||
2962 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2963 if ((changed & BSS_CHANGED_BEACON) ||
2964 (changed & BSS_CHANGED_BEACON_ENABLED &&
2965 bss_conf->enable_beacon)) {
2966 /*
2967 * Allocate and setup the beacon frame.
2968 *
2969 * Stop any previous beacon DMA. This may be
2970 * necessary, for example, when an ibss merge
2971 * causes reconfiguration; we may be called
2972 * with beacon transmission active.
2973 */
2974 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2975
2976 error = ath_beacon_alloc(aphy, vif);
2977 if (!error)
2978 ath_beacon_config(sc, vif);
2979 }
2980 }
2981
2982 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2983 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2984 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2985 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2986 ath9k_hw_keysetmac(sc->sc_ah,
2987 (u16)i,
1510718d 2988 common->curbssid);
2d0ddec5
JB		 2989 }
2990
2991 /* Only legacy IBSS for now */
2992 if (vif->type == NL80211_IFTYPE_ADHOC)
2993 ath_update_chainmask(sc, 0);
2994
8feceb67 2995 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
c46917bb
LR		 2996 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2997 bss_conf->use_short_preamble);
8feceb67
VT		 2998 if (bss_conf->use_short_preamble)
2999 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
3000 else
3001 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
3002 }
f078f209 3003
8feceb67 3004 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
c46917bb
LR		 3005 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3006 bss_conf->use_cts_prot);
8feceb67
VT		 3007 if (bss_conf->use_cts_prot &&
3008 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3009 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3010 else
3011 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3012 }
f078f209 3013
8feceb67 3014 if (changed & BSS_CHANGED_ASSOC) {
c46917bb 3015 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 3016 bss_conf->assoc);
5640b08e 3017 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 3018 }
141b38b6 3019
57c4d7b4
JB		 3020 /*
3021 * The HW TSF has to be reset when the beacon interval changes.
3022 * We set the flag here, and ath_beacon_config_ap() would take this
3023 * into account when it gets called through the subsequent
3024 * config_interface() call - with IFCC_BEACON in the changed field.
3025 */
3026
3027 if (changed & BSS_CHANGED_BEACON_INT) {
3028 sc->sc_flags |= SC_OP_TSF_RESET;
3029 sc->beacon_interval = bss_conf->beacon_int;
3030 }
3031
141b38b6 3032 mutex_unlock(&sc->mutex);
8feceb67 3033}
f078f209 3034
8feceb67
VT		 3035static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3036{
3037 u64 tsf;
bce048d7
JM		 3038 struct ath_wiphy *aphy = hw->priv;
3039 struct ath_softc *sc = aphy->sc;
f078f209 3040
141b38b6
S		 3041 mutex_lock(&sc->mutex);
3042 tsf = ath9k_hw_gettsf64(sc->sc_ah);
3043 mutex_unlock(&sc->mutex);
f078f209 3044
8feceb67
VT		 3045 return tsf;
3046}
f078f209 3047
3b5d665b
AF		 3048static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3049{
bce048d7
JM		 3050 struct ath_wiphy *aphy = hw->priv;
3051 struct ath_softc *sc = aphy->sc;
3b5d665b 3052
141b38b6
S		 3053 mutex_lock(&sc->mutex);
3054 ath9k_hw_settsf64(sc->sc_ah, tsf);
3055 mutex_unlock(&sc->mutex);
3b5d665b
AF		 3056}
3057
8feceb67
VT		 3058static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3059{
bce048d7
JM		 3060 struct ath_wiphy *aphy = hw->priv;
3061 struct ath_softc *sc = aphy->sc;
c83be688 3062
141b38b6 3063 mutex_lock(&sc->mutex);
21526d57
LR		 3064
3065 ath9k_ps_wakeup(sc);
141b38b6 3066 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 3067 ath9k_ps_restore(sc);
3068
141b38b6 3069 mutex_unlock(&sc->mutex);
8feceb67 3070}
f078f209 3071
8feceb67 3072static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 3073 enum ieee80211_ampdu_mlme_action action,
3074 struct ieee80211_sta *sta,
3075 u16 tid, u16 *ssn)
8feceb67 3076{
bce048d7
JM		 3077 struct ath_wiphy *aphy = hw->priv;
3078 struct ath_softc *sc = aphy->sc;
8feceb67 3079 int ret = 0;
f078f209 3080
8feceb67
VT		 3081 switch (action) {
3082 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 3083 if (!(sc->sc_flags & SC_OP_RXAGGR))
3084 ret = -ENOTSUPP;
8feceb67
VT		 3085 break;
3086 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 3087 break;
3088 case IEEE80211_AMPDU_TX_START:
f83da965
S		 3089 ath_tx_aggr_start(sc, sta, tid, ssn);
3090 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 3091 break;
3092 case IEEE80211_AMPDU_TX_STOP:
f83da965 3093 ath_tx_aggr_stop(sc, sta, tid);
17741cdc 3094 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 3095 break;
b1720231 3096 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 3097 ath_tx_aggr_resume(sc, sta, tid);
3098 break;
8feceb67 3099 default:
c46917bb
LR		 3100 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3101 "Unknown AMPDU action\n");
8feceb67
VT		 3102 }
3103
3104 return ret;
f078f209
LR		 3105}
3106
0c98de65
S		 3107static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3108{
bce048d7
JM		 3109 struct ath_wiphy *aphy = hw->priv;
3110 struct ath_softc *sc = aphy->sc;
0c98de65 3111
3d832611 3112 mutex_lock(&sc->mutex);
8089cc47
JM		 3113 if (ath9k_wiphy_scanning(sc)) {
3114 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3115 "same time\n");
3116 /*
3117 * Do not allow the concurrent scanning state for now. This
3118 * could be improved with scanning control moved into ath9k.
3119 */
3d832611 3120 mutex_unlock(&sc->mutex);
8089cc47
JM		 3121 return;
3122 }
3123
3124 aphy->state = ATH_WIPHY_SCAN;
3125 ath9k_wiphy_pause_all_forced(sc, aphy);
3126
e5f0921a 3127 spin_lock_bh(&sc->ani_lock);
0c98de65 3128 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 3129 spin_unlock_bh(&sc->ani_lock);
3d832611 3130 mutex_unlock(&sc->mutex);
0c98de65
S		 3131}
3132
3133static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3134{
bce048d7
JM		 3135 struct ath_wiphy *aphy = hw->priv;
3136 struct ath_softc *sc = aphy->sc;
0c98de65 3137
3d832611 3138 mutex_lock(&sc->mutex);
e5f0921a 3139 spin_lock_bh(&sc->ani_lock);
8089cc47 3140 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 3141 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 3142 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 3143 spin_unlock_bh(&sc->ani_lock);
d0bec342 3144 ath_beacon_config(sc, NULL);
3d832611 3145 mutex_unlock(&sc->mutex);
0c98de65
S		 3146}
3147
6baff7f9 3148struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 3149 .tx = ath9k_tx,
3150 .start = ath9k_start,
3151 .stop = ath9k_stop,
3152 .add_interface = ath9k_add_interface,
3153 .remove_interface = ath9k_remove_interface,
3154 .config = ath9k_config,
8feceb67 3155 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 3156 .sta_notify = ath9k_sta_notify,
3157 .conf_tx = ath9k_conf_tx,
8feceb67 3158 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 3159 .set_key = ath9k_set_key,
8feceb67 3160 .get_tsf = ath9k_get_tsf,
3b5d665b 3161 .set_tsf = ath9k_set_tsf,
8feceb67 3162 .reset_tsf = ath9k_reset_tsf,
4233df6b 3163 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 3164 .sw_scan_start = ath9k_sw_scan_start,
3165 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 3166 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 3167};
3168
392dff83
BP		 3169static struct {
3170 u32 version;
3171 const char * name;
3172} ath_mac_bb_names[] = {
3173 { AR_SREV_VERSION_5416_PCI, "5416" },
3174 { AR_SREV_VERSION_5416_PCIE, "5418" },
3175 { AR_SREV_VERSION_9100, "9100" },
3176 { AR_SREV_VERSION_9160, "9160" },
3177 { AR_SREV_VERSION_9280, "9280" },
ac88b6ec
VN		 3178 { AR_SREV_VERSION_9285, "9285" },
3179 { AR_SREV_VERSION_9287, "9287" }
392dff83
BP		 3180};
3181
3182static struct {
3183 u16 version;
3184 const char * name;
3185} ath_rf_names[] = {
3186 { 0, "5133" },
3187 { AR_RAD5133_SREV_MAJOR, "5133" },
3188 { AR_RAD5122_SREV_MAJOR, "5122" },
3189 { AR_RAD2133_SREV_MAJOR, "2133" },
3190 { AR_RAD2122_SREV_MAJOR, "2122" }
3191};
3192
3193/*
3194 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3195 */
6baff7f9 3196const char *
392dff83
BP		 3197ath_mac_bb_name(u32 mac_bb_version)
3198{
3199 int i;
3200
3201 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3202 if (ath_mac_bb_names[i].version == mac_bb_version) {
3203 return ath_mac_bb_names[i].name;
3204 }
3205 }
3206
3207 return "????";
3208}
3209
3210/*
3211 * Return the RF name. "????" is returned if the RF is unknown.
3212 */
6baff7f9 3213const char *
392dff83
BP		 3214ath_rf_name(u16 rf_version)
3215{
3216 int i;
3217
3218 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3219 if (ath_rf_names[i].version == rf_version) {
3220 return ath_rf_names[i].name;
3221 }
3222 }
3223
3224 return "????";
3225}
3226
6baff7f9 3227static int __init ath9k_init(void)
f078f209 3228{
ca8a8560
VT		 3229 int error;
3230
ca8a8560
VT		 3231 /* Register rate control algorithm */
3232 error = ath_rate_control_register();
3233 if (error != 0) {
3234 printk(KERN_ERR
b51bb3cd
LR		 3235 "ath9k: Unable to register rate control "
3236 "algorithm: %d\n",
ca8a8560 3237 error);
6baff7f9 3238 goto err_out;
ca8a8560
VT		 3239 }
3240
19d8bc22
GJ		 3241 error = ath9k_debug_create_root();
3242 if (error) {
3243 printk(KERN_ERR
3244 "ath9k: Unable to create debugfs root: %d\n",
3245 error);
3246 goto err_rate_unregister;
3247 }
3248
6baff7f9
GJ		 3249 error = ath_pci_init();
3250 if (error < 0) {
f078f209 3251 printk(KERN_ERR
b51bb3cd 3252 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 3253 error = -ENODEV;
19d8bc22 3254 goto err_remove_root;
f078f209
LR		 3255 }
3256
09329d37
GJ		 3257 error = ath_ahb_init();
3258 if (error < 0) {
3259 error = -ENODEV;
3260 goto err_pci_exit;
3261 }
3262
f078f209 3263 return 0;
6baff7f9 3264
09329d37
GJ		 3265 err_pci_exit:
3266 ath_pci_exit();
3267
19d8bc22
GJ		 3268 err_remove_root:
3269 ath9k_debug_remove_root();
6baff7f9
GJ		 3270 err_rate_unregister:
3271 ath_rate_control_unregister();
3272 err_out:
3273 return error;
f078f209 3274}
6baff7f9 3275module_init(ath9k_init);
f078f209 3276
6baff7f9 3277static void __exit ath9k_exit(void)
f078f209 3278{
09329d37 3279 ath_ahb_exit();
6baff7f9 3280 ath_pci_exit();
19d8bc22 3281 ath9k_debug_remove_root();
ca8a8560 3282 ath_rate_control_unregister();
04bd4638 3283 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 3284}
6baff7f9 3285module_exit(ath9k_exit);
Linux 6.x block layer and io_uring tree(s)