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ath9k: simplify ath_btcoex_bt_stomp()
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
f078f209
LR		 21static char *dev_info = "ath9k";
22
23MODULE_AUTHOR("Atheros Communications");
24MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26MODULE_LICENSE("Dual BSD/GPL");
27
b3bd89ce
JM		 28static int modparam_nohwcrypt;
29module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
5f8e077c
LR		 32/* We use the hw_value as an index into our private channel structure */
33
34#define CHAN2G(_freq, _idx) { \
35 .center_freq = (_freq), \
36 .hw_value = (_idx), \
eeddfd9d 37 .max_power = 20, \
5f8e077c
LR		 38}
39
40#define CHAN5G(_freq, _idx) { \
41 .band = IEEE80211_BAND_5GHZ, \
42 .center_freq = (_freq), \
43 .hw_value = (_idx), \
eeddfd9d 44 .max_power = 20, \
5f8e077c
LR		 45}
46
47/* Some 2 GHz radios are actually tunable on 2312-2732
48 * on 5 MHz steps, we support the channels which we know
49 * we have calibration data for all cards though to make
50 * this static */
51static struct ieee80211_channel ath9k_2ghz_chantable[] = {
52 CHAN2G(2412, 0), /* Channel 1 */
53 CHAN2G(2417, 1), /* Channel 2 */
54 CHAN2G(2422, 2), /* Channel 3 */
55 CHAN2G(2427, 3), /* Channel 4 */
56 CHAN2G(2432, 4), /* Channel 5 */
57 CHAN2G(2437, 5), /* Channel 6 */
58 CHAN2G(2442, 6), /* Channel 7 */
59 CHAN2G(2447, 7), /* Channel 8 */
60 CHAN2G(2452, 8), /* Channel 9 */
61 CHAN2G(2457, 9), /* Channel 10 */
62 CHAN2G(2462, 10), /* Channel 11 */
63 CHAN2G(2467, 11), /* Channel 12 */
64 CHAN2G(2472, 12), /* Channel 13 */
65 CHAN2G(2484, 13), /* Channel 14 */
66};
67
68/* Some 5 GHz radios are actually tunable on XXXX-YYYY
69 * on 5 MHz steps, we support the channels which we know
70 * we have calibration data for all cards though to make
71 * this static */
72static struct ieee80211_channel ath9k_5ghz_chantable[] = {
73 /* _We_ call this UNII 1 */
74 CHAN5G(5180, 14), /* Channel 36 */
75 CHAN5G(5200, 15), /* Channel 40 */
76 CHAN5G(5220, 16), /* Channel 44 */
77 CHAN5G(5240, 17), /* Channel 48 */
78 /* _We_ call this UNII 2 */
79 CHAN5G(5260, 18), /* Channel 52 */
80 CHAN5G(5280, 19), /* Channel 56 */
81 CHAN5G(5300, 20), /* Channel 60 */
82 CHAN5G(5320, 21), /* Channel 64 */
83 /* _We_ call this "Middle band" */
84 CHAN5G(5500, 22), /* Channel 100 */
85 CHAN5G(5520, 23), /* Channel 104 */
86 CHAN5G(5540, 24), /* Channel 108 */
87 CHAN5G(5560, 25), /* Channel 112 */
88 CHAN5G(5580, 26), /* Channel 116 */
89 CHAN5G(5600, 27), /* Channel 120 */
90 CHAN5G(5620, 28), /* Channel 124 */
91 CHAN5G(5640, 29), /* Channel 128 */
92 CHAN5G(5660, 30), /* Channel 132 */
93 CHAN5G(5680, 31), /* Channel 136 */
94 CHAN5G(5700, 32), /* Channel 140 */
95 /* _We_ call this UNII 3 */
96 CHAN5G(5745, 33), /* Channel 149 */
97 CHAN5G(5765, 34), /* Channel 153 */
98 CHAN5G(5785, 35), /* Channel 157 */
99 CHAN5G(5805, 36), /* Channel 161 */
100 CHAN5G(5825, 37), /* Channel 165 */
101};
102
ce111bad
LR		 103static void ath_cache_conf_rate(struct ath_softc *sc,
104 struct ieee80211_conf *conf)
ff37e337 105{
030bb495
LR		 106 switch (conf->channel->band) {
107 case IEEE80211_BAND_2GHZ:
108 if (conf_is_ht20(conf))
109 sc->cur_rate_table =
110 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
111 else if (conf_is_ht40_minus(conf))
112 sc->cur_rate_table =
113 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
114 else if (conf_is_ht40_plus(conf))
115 sc->cur_rate_table =
116 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 117 else
030bb495
LR		 118 sc->cur_rate_table =
119 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 120 break;
121 case IEEE80211_BAND_5GHZ:
122 if (conf_is_ht20(conf))
123 sc->cur_rate_table =
124 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
125 else if (conf_is_ht40_minus(conf))
126 sc->cur_rate_table =
127 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
128 else if (conf_is_ht40_plus(conf))
129 sc->cur_rate_table =
130 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
131 else
96742256
LR		 132 sc->cur_rate_table =
133 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 134 break;
135 default:
ce111bad 136 BUG_ON(1);
030bb495
LR		 137 break;
138 }
ff37e337
S		 139}
140
141static void ath_update_txpow(struct ath_softc *sc)
142{
cbe61d8a 143 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 144 u32 txpow;
145
17d7904d
S		 146 if (sc->curtxpow != sc->config.txpowlimit) {
147 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 148 /* read back in case value is clamped */
149 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 150 sc->curtxpow = txpow;
ff37e337
S		 151 }
152}
153
154static u8 parse_mpdudensity(u8 mpdudensity)
155{
156 /*
157 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
158 * 0 for no restriction
159 * 1 for 1/4 us
160 * 2 for 1/2 us
161 * 3 for 1 us
162 * 4 for 2 us
163 * 5 for 4 us
164 * 6 for 8 us
165 * 7 for 16 us
166 */
167 switch (mpdudensity) {
168 case 0:
169 return 0;
170 case 1:
171 case 2:
172 case 3:
173 /* Our lower layer calculations limit our precision to
174 1 microsecond */
175 return 1;
176 case 4:
177 return 2;
178 case 5:
179 return 4;
180 case 6:
181 return 8;
182 case 7:
183 return 16;
184 default:
185 return 0;
186 }
187}
188
189static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
190{
4f0fc7c3 191 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 192 struct ieee80211_supported_band *sband;
193 struct ieee80211_rate *rate;
194 int i, maxrates;
195
196 switch (band) {
197 case IEEE80211_BAND_2GHZ:
198 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
199 break;
200 case IEEE80211_BAND_5GHZ:
201 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
202 break;
203 default:
204 break;
205 }
206
207 if (rate_table == NULL)
208 return;
209
210 sband = &sc->sbands[band];
211 rate = sc->rates[band];
212
213 if (rate_table->rate_cnt > ATH_RATE_MAX)
214 maxrates = ATH_RATE_MAX;
215 else
216 maxrates = rate_table->rate_cnt;
217
218 for (i = 0; i < maxrates; i++) {
219 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
220 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 221 if (rate_table->info[i].short_preamble) {
222 rate[i].hw_value_short = rate_table->info[i].ratecode |
223 rate_table->info[i].short_preamble;
224 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
225 }
ff37e337 226 sband->n_bitrates++;
f46730d1 227
4d6b228d 228 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
04bd4638 229 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 230 }
231}
232
82880a7c
VT		 233static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
234 struct ieee80211_hw *hw)
235{
236 struct ieee80211_channel *curchan = hw->conf.channel;
237 struct ath9k_channel *channel;
238 u8 chan_idx;
239
240 chan_idx = curchan->hw_value;
241 channel = &sc->sc_ah->channels[chan_idx];
242 ath9k_update_ichannel(sc, hw, channel);
243 return channel;
244}
245
ff37e337
S		 246/*
247 * Set/change channels. If the channel is really being changed, it's done
248 * by reseting the chip. To accomplish this we must first cleanup any pending
249 * DMA, then restart stuff.
250*/
0e2dedf9
JM		 251int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
252 struct ath9k_channel *hchan)
ff37e337 253{
cbe61d8a 254 struct ath_hw *ah = sc->sc_ah;
ff37e337 255 bool fastcc = true, stopped;
ae8d2858
LR		 256 struct ieee80211_channel *channel = hw->conf.channel;
257 int r;
ff37e337
S		 258
259 if (sc->sc_flags & SC_OP_INVALID)
260 return -EIO;
261
3cbb5dd7
VN		 262 ath9k_ps_wakeup(sc);
263
c0d7c7af
LR		 264 /*
265 * This is only performed if the channel settings have
266 * actually changed.
267 *
268 * To switch channels clear any pending DMA operations;
269 * wait long enough for the RX fifo to drain, reset the
270 * hardware at the new frequency, and then re-enable
271 * the relevant bits of the h/w.
272 */
273 ath9k_hw_set_interrupts(ah, 0);
043a0405 274 ath_drain_all_txq(sc, false);
c0d7c7af 275 stopped = ath_stoprecv(sc);
ff37e337 276
c0d7c7af
LR		 277 /* XXX: do not flush receive queue here. We don't want
278 * to flush data frames already in queue because of
279 * changing channel. */
ff37e337 280
c0d7c7af
LR		 281 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
282 fastcc = false;
283
4d6b228d 284 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
c0d7c7af 285 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 286 sc->sc_ah->curchan->channel,
c0d7c7af 287 channel->center_freq, sc->tx_chan_width);
ff37e337 288
c0d7c7af
LR		 289 spin_lock_bh(&sc->sc_resetlock);
290
291 r = ath9k_hw_reset(ah, hchan, fastcc);
292 if (r) {
4d6b228d 293 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
c0d7c7af 294 "Unable to reset channel (%u Mhz) "
6b45784f 295 "reset status %d\n",
c0d7c7af
LR		 296 channel->center_freq, r);
297 spin_unlock_bh(&sc->sc_resetlock);
3989279c 298 goto ps_restore;
ff37e337 299 }
c0d7c7af
LR		 300 spin_unlock_bh(&sc->sc_resetlock);
301
c0d7c7af
LR		 302 sc->sc_flags &= ~SC_OP_FULL_RESET;
303
304 if (ath_startrecv(sc) != 0) {
4d6b228d 305 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
c0d7c7af 306 "Unable to restart recv logic\n");
3989279c
GJ		 307 r = -EIO;
308 goto ps_restore;
c0d7c7af
LR		 309 }
310
311 ath_cache_conf_rate(sc, &hw->conf);
312 ath_update_txpow(sc);
17d7904d 313 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 314
315 ps_restore:
3cbb5dd7 316 ath9k_ps_restore(sc);
3989279c 317 return r;
ff37e337
S		 318}
319
320/*
321 * This routine performs the periodic noise floor calibration function
322 * that is used to adjust and optimize the chip performance. This
323 * takes environmental changes (location, temperature) into account.
324 * When the task is complete, it reschedules itself depending on the
325 * appropriate interval that was calculated.
326 */
327static void ath_ani_calibrate(unsigned long data)
328{
20977d3e
S		 329 struct ath_softc *sc = (struct ath_softc *)data;
330 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 331 bool longcal = false;
332 bool shortcal = false;
333 bool aniflag = false;
334 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 335 u32 cal_interval, short_cal_interval;
ff37e337 336
20977d3e
S		 337 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
338 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 339
340 /*
341 * don't calibrate when we're scanning.
342 * we are most likely not on our home channel.
343 */
e5f0921a 344 spin_lock(&sc->ani_lock);
0c98de65 345 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 346 goto set_timer;
ff37e337 347
1ffc1c61
JM		 348 /* Only calibrate if awake */
349 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
350 goto set_timer;
351
352 ath9k_ps_wakeup(sc);
353
ff37e337 354 /* Long calibration runs independently of short calibration. */
17d7904d 355 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 356 longcal = true;
4d6b228d 357 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 358 sc->ani.longcal_timer = timestamp;
ff37e337
S		 359 }
360
17d7904d
S		 361 /* Short calibration applies only while caldone is false */
362 if (!sc->ani.caldone) {
20977d3e 363 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 364 shortcal = true;
4d6b228d 365 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 366 sc->ani.shortcal_timer = timestamp;
367 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 368 }
369 } else {
17d7904d 370 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 371 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 372 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
373 if (sc->ani.caldone)
374 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 375 }
376 }
377
378 /* Verify whether we must check ANI */
20977d3e 379 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 380 aniflag = true;
17d7904d 381 sc->ani.checkani_timer = timestamp;
ff37e337
S		 382 }
383
384 /* Skip all processing if there's nothing to do. */
385 if (longcal || shortcal || aniflag) {
386 /* Call ANI routine if necessary */
387 if (aniflag)
22e66a4c 388 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S		 389
390 /* Perform calibration if necessary */
391 if (longcal || shortcal) {
379f0440
S		 392 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
393 sc->rx_chainmask, longcal);
394
395 if (longcal)
396 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
397 ah->curchan);
398
4d6b228d 399 DPRINTF(sc->sc_ah, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
379f0440
S		 400 ah->curchan->channel, ah->curchan->channelFlags,
401 sc->ani.noise_floor);
ff37e337
S		 402 }
403 }
404
1ffc1c61
JM		 405 ath9k_ps_restore(sc);
406
20977d3e 407set_timer:
e5f0921a 408 spin_unlock(&sc->ani_lock);
ff37e337
S		 409 /*
410 * Set timer interval based on previous results.
411 * The interval must be the shortest necessary to satisfy ANI,
412 * short calibration and long calibration.
413 */
aac9207e 414 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 415 if (sc->sc_ah->config.enable_ani)
aac9207e 416 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 417 if (!sc->ani.caldone)
20977d3e 418 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 419
17d7904d 420 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 421}
422
415f738e
S		 423static void ath_start_ani(struct ath_softc *sc)
424{
425 unsigned long timestamp = jiffies_to_msecs(jiffies);
426
427 sc->ani.longcal_timer = timestamp;
428 sc->ani.shortcal_timer = timestamp;
429 sc->ani.checkani_timer = timestamp;
430
431 mod_timer(&sc->ani.timer,
432 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
433}
434
ff37e337
S		 435/*
436 * Update tx/rx chainmask. For legacy association,
437 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 438 * the chainmask configuration, for bt coexistence, use
439 * the chainmask configuration even in legacy mode.
ff37e337 440 */
0e2dedf9 441void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 442{
af03abec
LR		 443 struct ath_hw *ah = sc->sc_ah;
444
3d832611 445 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
766ec4a9 446 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
2660b81a
S		 447 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
448 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 449 } else {
17d7904d
S		 450 sc->tx_chainmask = 1;
451 sc->rx_chainmask = 1;
ff37e337
S		 452 }
453
af03abec 454 DPRINTF(ah, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 455 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 456}
457
458static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
459{
460 struct ath_node *an;
461
462 an = (struct ath_node *)sta->drv_priv;
463
87792efc 464 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 465 ath_tx_node_init(sc, an);
9e98ac65 466 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 467 sta->ht_cap.ampdu_factor);
468 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 469 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 470 }
ff37e337
S		 471}
472
473static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
474{
475 struct ath_node *an = (struct ath_node *)sta->drv_priv;
476
477 if (sc->sc_flags & SC_OP_TXAGGR)
478 ath_tx_node_cleanup(sc, an);
479}
480
481static void ath9k_tasklet(unsigned long data)
482{
483 struct ath_softc *sc = (struct ath_softc *)data;
af03abec
LR		 484 struct ath_hw *ah = sc->sc_ah;
485
17d7904d 486 u32 status = sc->intrstatus;
ff37e337 487
153e080d
VT		 488 ath9k_ps_wakeup(sc);
489
ff37e337 490 if (status & ATH9K_INT_FATAL) {
ff37e337 491 ath_reset(sc, false);
153e080d 492 ath9k_ps_restore(sc);
ff37e337 493 return;
063d8be3 494 }
ff37e337 495
063d8be3
S		 496 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
497 spin_lock_bh(&sc->rx.rxflushlock);
498 ath_rx_tasklet(sc, 0);
499 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 500 }
501
063d8be3
S		 502 if (status & ATH9K_INT_TX)
503 ath_tx_tasklet(sc);
504
96148326 505 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 506 /*
507 * TSF sync does not look correct; remain awake to sync with
508 * the next Beacon.
509 */
af03abec 510 DPRINTF(ah, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 511 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 512 }
513
766ec4a9 514 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT		 515 if (status & ATH9K_INT_GENTIMER)
516 ath_gen_timer_isr(sc->sc_ah);
517
ff37e337 518 /* re-enable hardware interrupt */
af03abec 519 ath9k_hw_set_interrupts(ah, sc->imask);
153e080d 520 ath9k_ps_restore(sc);
ff37e337
S		 521}
522
6baff7f9 523irqreturn_t ath_isr(int irq, void *dev)
ff37e337 524{
063d8be3
S		 525#define SCHED_INTR ( \
526 ATH9K_INT_FATAL | \
527 ATH9K_INT_RXORN | \
528 ATH9K_INT_RXEOL | \
529 ATH9K_INT_RX | \
530 ATH9K_INT_TX | \
531 ATH9K_INT_BMISS | \
532 ATH9K_INT_CST | \
ebb8e1d7
VT		 533 ATH9K_INT_TSFOOR | \
534 ATH9K_INT_GENTIMER)
063d8be3 535
ff37e337 536 struct ath_softc *sc = dev;
cbe61d8a 537 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 538 enum ath9k_int status;
539 bool sched = false;
540
063d8be3
S		 541 /*
542 * The hardware is not ready/present, don't
543 * touch anything. Note this can happen early
544 * on if the IRQ is shared.
545 */
546 if (sc->sc_flags & SC_OP_INVALID)
547 return IRQ_NONE;
ff37e337 548
063d8be3
S		 549
550 /* shared irq, not for us */
551
153e080d 552 if (!ath9k_hw_intrpend(ah))
063d8be3 553 return IRQ_NONE;
063d8be3
S		 554
555 /*
556 * Figure out the reason(s) for the interrupt. Note
557 * that the hal returns a pseudo-ISR that may include
558 * bits we haven't explicitly enabled so we mask the
559 * value to insure we only process bits we requested.
560 */
561 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
562 status &= sc->imask; /* discard unasked-for bits */
ff37e337 563
063d8be3
S		 564 /*
565 * If there are no status bits set, then this interrupt was not
566 * for me (should have been caught above).
567 */
153e080d 568 if (!status)
063d8be3 569 return IRQ_NONE;
ff37e337 570
063d8be3
S		 571 /* Cache the status */
572 sc->intrstatus = status;
573
574 if (status & SCHED_INTR)
575 sched = true;
576
577 /*
578 * If a FATAL or RXORN interrupt is received, we have to reset the
579 * chip immediately.
580 */
581 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
582 goto chip_reset;
583
584 if (status & ATH9K_INT_SWBA)
585 tasklet_schedule(&sc->bcon_tasklet);
586
587 if (status & ATH9K_INT_TXURN)
588 ath9k_hw_updatetxtriglevel(ah, true);
589
590 if (status & ATH9K_INT_MIB) {
ff37e337 591 /*
063d8be3
S		 592 * Disable interrupts until we service the MIB
593 * interrupt; otherwise it will continue to
594 * fire.
ff37e337 595 */
063d8be3
S		 596 ath9k_hw_set_interrupts(ah, 0);
597 /*
598 * Let the hal handle the event. We assume
599 * it will clear whatever condition caused
600 * the interrupt.
601 */
22e66a4c 602 ath9k_hw_procmibevent(ah);
063d8be3
S		 603 ath9k_hw_set_interrupts(ah, sc->imask);
604 }
ff37e337 605
153e080d
VT		 606 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
607 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 608 /* Clear RxAbort bit so that we can
609 * receive frames */
610 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 611 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 612 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 613 }
063d8be3
S		 614
615chip_reset:
ff37e337 616
817e11de
S		 617 ath_debug_stat_interrupt(sc, status);
618
ff37e337
S		 619 if (sched) {
620 /* turn off every interrupt except SWBA */
17d7904d 621 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 622 tasklet_schedule(&sc->intr_tq);
623 }
624
625 return IRQ_HANDLED;
063d8be3
S		 626
627#undef SCHED_INTR
ff37e337
S		 628}
629
f078f209 630static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 631 struct ieee80211_channel *chan,
094d05dc 632 enum nl80211_channel_type channel_type)
f078f209
LR		 633{
634 u32 chanmode = 0;
f078f209
LR		 635
636 switch (chan->band) {
637 case IEEE80211_BAND_2GHZ:
094d05dc
S		 638 switch(channel_type) {
639 case NL80211_CHAN_NO_HT:
640 case NL80211_CHAN_HT20:
f078f209 641 chanmode = CHANNEL_G_HT20;
094d05dc
S		 642 break;
643 case NL80211_CHAN_HT40PLUS:
f078f209 644 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 645 break;
646 case NL80211_CHAN_HT40MINUS:
f078f209 647 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 648 break;
649 }
f078f209
LR		 650 break;
651 case IEEE80211_BAND_5GHZ:
094d05dc
S		 652 switch(channel_type) {
653 case NL80211_CHAN_NO_HT:
654 case NL80211_CHAN_HT20:
f078f209 655 chanmode = CHANNEL_A_HT20;
094d05dc
S		 656 break;
657 case NL80211_CHAN_HT40PLUS:
f078f209 658 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 659 break;
660 case NL80211_CHAN_HT40MINUS:
f078f209 661 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 662 break;
663 }
f078f209
LR		 664 break;
665 default:
666 break;
667 }
668
669 return chanmode;
670}
671
6ace2891 672static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 673 struct ath9k_keyval *hk, const u8 *addr,
674 bool authenticator)
f078f209 675{
6ace2891
JM		 676 const u8 *key_rxmic;
677 const u8 *key_txmic;
f078f209 678
6ace2891
JM		 679 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
680 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 681
682 if (addr == NULL) {
d216aaa6
JM		 683 /*
684 * Group key installation - only two key cache entries are used
685 * regardless of splitmic capability since group key is only
686 * used either for TX or RX.
687 */
3f53dd64
JM		 688 if (authenticator) {
689 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
690 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
691 } else {
692 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
693 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
694 }
d216aaa6 695 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 696 }
17d7904d 697 if (!sc->splitmic) {
d216aaa6 698 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 699 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
700 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 701 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 702 }
d216aaa6
JM		 703
704 /* Separate key cache entries for TX and RX */
705
706 /* TX key goes at first index, RX key at +32. */
f078f209 707 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 708 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
709 /* TX MIC entry failed. No need to proceed further */
4d6b228d 710 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
04bd4638 711 "Setting TX MIC Key Failed\n");
f078f209
LR		 712 return 0;
713 }
714
715 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
716 /* XXX delete tx key on failure? */
d216aaa6 717 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 718}
719
720static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
721{
722 int i;
723
17d7904d
S		 724 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
725 if (test_bit(i, sc->keymap) ||
726 test_bit(i + 64, sc->keymap))
6ace2891 727 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 728 if (sc->splitmic &&
729 (test_bit(i + 32, sc->keymap) ||
730 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 731 continue; /* At least one part of TKIP key allocated */
732
733 /* Found a free slot for a TKIP key */
734 return i;
735 }
736 return -1;
737}
738
739static int ath_reserve_key_cache_slot(struct ath_softc *sc)
740{
741 int i;
742
743 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 744 if (sc->splitmic) {
745 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
746 if (!test_bit(i, sc->keymap) &&
747 (test_bit(i + 32, sc->keymap) ||
748 test_bit(i + 64, sc->keymap) ||
749 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 750 return i;
17d7904d
S		 751 if (!test_bit(i + 32, sc->keymap) &&
752 (test_bit(i, sc->keymap) ||
753 test_bit(i + 64, sc->keymap) ||
754 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 755 return i + 32;
17d7904d
S		 756 if (!test_bit(i + 64, sc->keymap) &&
757 (test_bit(i , sc->keymap) ||
758 test_bit(i + 32, sc->keymap) ||
759 test_bit(i + 64 + 32, sc->keymap)))
ea612132 760 return i + 64;
17d7904d
S		 761 if (!test_bit(i + 64 + 32, sc->keymap) &&
762 (test_bit(i, sc->keymap) ||
763 test_bit(i + 32, sc->keymap) ||
764 test_bit(i + 64, sc->keymap)))
ea612132 765 return i + 64 + 32;
6ace2891
JM		 766 }
767 } else {
17d7904d
S		 768 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
769 if (!test_bit(i, sc->keymap) &&
770 test_bit(i + 64, sc->keymap))
6ace2891 771 return i;
17d7904d
S		 772 if (test_bit(i, sc->keymap) &&
773 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 774 return i + 64;
775 }
776 }
777
778 /* No partially used TKIP slots, pick any available slot */
17d7904d 779 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 780 /* Do not allow slots that could be needed for TKIP group keys
781 * to be used. This limitation could be removed if we know that
782 * TKIP will not be used. */
783 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
784 continue;
17d7904d 785 if (sc->splitmic) {
be2864cf
JM		 786 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
787 continue;
788 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
789 continue;
790 }
791
17d7904d 792 if (!test_bit(i, sc->keymap))
6ace2891
JM		 793 return i; /* Found a free slot for a key */
794 }
795
796 /* No free slot found */
797 return -1;
f078f209
LR		 798}
799
800static int ath_key_config(struct ath_softc *sc,
3f53dd64 801 struct ieee80211_vif *vif,
dc822b5d 802 struct ieee80211_sta *sta,
f078f209
LR		 803 struct ieee80211_key_conf *key)
804{
f078f209
LR		 805 struct ath9k_keyval hk;
806 const u8 *mac = NULL;
807 int ret = 0;
6ace2891 808 int idx;
f078f209
LR		 809
810 memset(&hk, 0, sizeof(hk));
811
812 switch (key->alg) {
813 case ALG_WEP:
814 hk.kv_type = ATH9K_CIPHER_WEP;
815 break;
816 case ALG_TKIP:
817 hk.kv_type = ATH9K_CIPHER_TKIP;
818 break;
819 case ALG_CCMP:
820 hk.kv_type = ATH9K_CIPHER_AES_CCM;
821 break;
822 default:
ca470b29 823 return -EOPNOTSUPP;
f078f209
LR		 824 }
825
6ace2891 826 hk.kv_len = key->keylen;
f078f209
LR		 827 memcpy(hk.kv_val, key->key, key->keylen);
828
6ace2891
JM		 829 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
830 /* For now, use the default keys for broadcast keys. This may
831 * need to change with virtual interfaces. */
832 idx = key->keyidx;
833 } else if (key->keyidx) {
dc822b5d
JB		 834 if (WARN_ON(!sta))
835 return -EOPNOTSUPP;
836 mac = sta->addr;
837
6ace2891
JM		 838 if (vif->type != NL80211_IFTYPE_AP) {
839 /* Only keyidx 0 should be used with unicast key, but
840 * allow this for client mode for now. */
841 idx = key->keyidx;
842 } else
843 return -EIO;
f078f209 844 } else {
dc822b5d
JB		 845 if (WARN_ON(!sta))
846 return -EOPNOTSUPP;
847 mac = sta->addr;
848
6ace2891
JM		 849 if (key->alg == ALG_TKIP)
850 idx = ath_reserve_key_cache_slot_tkip(sc);
851 else
852 idx = ath_reserve_key_cache_slot(sc);
853 if (idx < 0)
ca470b29 854 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 855 }
856
857 if (key->alg == ALG_TKIP)
3f53dd64
JM		 858 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
859 vif->type == NL80211_IFTYPE_AP);
f078f209 860 else
d216aaa6 861 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 862
863 if (!ret)
864 return -EIO;
865
17d7904d 866 set_bit(idx, sc->keymap);
6ace2891 867 if (key->alg == ALG_TKIP) {
17d7904d
S		 868 set_bit(idx + 64, sc->keymap);
869 if (sc->splitmic) {
870 set_bit(idx + 32, sc->keymap);
871 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 872 }
873 }
874
875 return idx;
f078f209
LR		 876}
877
878static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
879{
6ace2891
JM		 880 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
881 if (key->hw_key_idx < IEEE80211_WEP_NKID)
882 return;
883
17d7904d 884 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 885 if (key->alg != ALG_TKIP)
886 return;
f078f209 887
17d7904d
S		 888 clear_bit(key->hw_key_idx + 64, sc->keymap);
889 if (sc->splitmic) {
890 clear_bit(key->hw_key_idx + 32, sc->keymap);
891 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 892 }
f078f209
LR		 893}
894
eb2599ca
S		 895static void setup_ht_cap(struct ath_softc *sc,
896 struct ieee80211_sta_ht_cap *ht_info)
f078f209 897{
140add21 898 u8 tx_streams, rx_streams;
f078f209 899
d9fe60de
JB		 900 ht_info->ht_supported = true;
901 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
902 IEEE80211_HT_CAP_SM_PS |
903 IEEE80211_HT_CAP_SGI_40 |
904 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 905
9e98ac65
S		 906 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
907 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 908
d9fe60de
JB		 909 /* set up supported mcs set */
910 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
140add21
SB		 911 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
912 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
913
914 if (tx_streams != rx_streams) {
4d6b228d 915 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
140add21
SB		 916 tx_streams, rx_streams);
917 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
918 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
919 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
920 }
eb2599ca 921
140add21
SB		 922 ht_info->mcs.rx_mask[0] = 0xff;
923 if (rx_streams >= 2)
eb2599ca 924 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 925
140add21 926 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 927}
928
8feceb67 929static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 930 struct ieee80211_vif *vif,
8feceb67 931 struct ieee80211_bss_conf *bss_conf)
f078f209 932{
f078f209 933
8feceb67 934 if (bss_conf->assoc) {
4d6b228d 935 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 936 bss_conf->aid, sc->curbssid);
f078f209 937
8feceb67 938 /* New association, store aid */
2664f201
SB		 939 sc->curaid = bss_conf->aid;
940 ath9k_hw_write_associd(sc);
941
942 /*
943 * Request a re-configuration of Beacon related timers
944 * on the receipt of the first Beacon frame (i.e.,
945 * after time sync with the AP).
946 */
947 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 948
8feceb67 949 /* Configure the beacon */
2c3db3d5 950 ath_beacon_config(sc, vif);
f078f209 951
8feceb67 952 /* Reset rssi stats */
22e66a4c 953 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 954
415f738e 955 ath_start_ani(sc);
8feceb67 956 } else {
4d6b228d 957 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 958 sc->curaid = 0;
f38faa31
SB		 959 /* Stop ANI */
960 del_timer_sync(&sc->ani.timer);
f078f209 961 }
8feceb67 962}
f078f209 963
8feceb67
VT		 964/********************************/
965/* LED functions */
966/********************************/
f078f209 967
f2bffa7e
VT		 968static void ath_led_blink_work(struct work_struct *work)
969{
970 struct ath_softc *sc = container_of(work, struct ath_softc,
971 ath_led_blink_work.work);
972
973 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
974 return;
85067c06
VT		 975
976 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
977 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
08fc5c1b 978 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
85067c06 979 else
08fc5c1b 980 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
85067c06 981 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e 982
42935eca
LR		 983 ieee80211_queue_delayed_work(sc->hw,
984 &sc->ath_led_blink_work,
985 (sc->sc_flags & SC_OP_LED_ON) ?
986 msecs_to_jiffies(sc->led_off_duration) :
987 msecs_to_jiffies(sc->led_on_duration));
f2bffa7e 988
85067c06
VT		 989 sc->led_on_duration = sc->led_on_cnt ?
990 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
991 ATH_LED_ON_DURATION_IDLE;
992 sc->led_off_duration = sc->led_off_cnt ?
993 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
994 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 995 sc->led_on_cnt = sc->led_off_cnt = 0;
996 if (sc->sc_flags & SC_OP_LED_ON)
997 sc->sc_flags &= ~SC_OP_LED_ON;
998 else
999 sc->sc_flags |= SC_OP_LED_ON;
1000}
1001
8feceb67
VT		 1002static void ath_led_brightness(struct led_classdev *led_cdev,
1003 enum led_brightness brightness)
1004{
1005 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1006 struct ath_softc *sc = led->sc;
f078f209 1007
8feceb67
VT		 1008 switch (brightness) {
1009 case LED_OFF:
1010 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e 1011 led->led_type == ATH_LED_RADIO) {
08fc5c1b 1012 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
f2bffa7e 1013 (led->led_type == ATH_LED_RADIO));
8feceb67 1014 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1015 if (led->led_type == ATH_LED_RADIO)
1016 sc->sc_flags &= ~SC_OP_LED_ON;
1017 } else {
1018 sc->led_off_cnt++;
1019 }
8feceb67
VT		 1020 break;
1021 case LED_FULL:
f2bffa7e 1022 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1023 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
42935eca
LR		 1024 ieee80211_queue_delayed_work(sc->hw,
1025 &sc->ath_led_blink_work, 0);
f2bffa7e 1026 } else if (led->led_type == ATH_LED_RADIO) {
08fc5c1b 1027 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
f2bffa7e
VT		 1028 sc->sc_flags |= SC_OP_LED_ON;
1029 } else {
1030 sc->led_on_cnt++;
1031 }
8feceb67
VT		 1032 break;
1033 default:
1034 break;
f078f209 1035 }
8feceb67 1036}
f078f209 1037
8feceb67
VT		 1038static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1039 char *trigger)
1040{
1041 int ret;
f078f209 1042
8feceb67
VT		 1043 led->sc = sc;
1044 led->led_cdev.name = led->name;
1045 led->led_cdev.default_trigger = trigger;
1046 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1047
8feceb67
VT		 1048 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1049 if (ret)
4d6b228d 1050 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
8feceb67
VT		 1051 "Failed to register led:%s", led->name);
1052 else
1053 led->registered = 1;
1054 return ret;
1055}
f078f209 1056
8feceb67
VT		 1057static void ath_unregister_led(struct ath_led *led)
1058{
1059 if (led->registered) {
1060 led_classdev_unregister(&led->led_cdev);
1061 led->registered = 0;
f078f209 1062 }
f078f209
LR		 1063}
1064
8feceb67 1065static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1066{
8feceb67
VT		 1067 ath_unregister_led(&sc->assoc_led);
1068 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1069 ath_unregister_led(&sc->tx_led);
1070 ath_unregister_led(&sc->rx_led);
1071 ath_unregister_led(&sc->radio_led);
08fc5c1b 1072 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
8feceb67 1073}
f078f209 1074
8feceb67
VT		 1075static void ath_init_leds(struct ath_softc *sc)
1076{
1077 char *trigger;
1078 int ret;
f078f209 1079
08fc5c1b
VN		 1080 if (AR_SREV_9287(sc->sc_ah))
1081 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1082 else
1083 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1084
8feceb67 1085 /* Configure gpio 1 for output */
08fc5c1b 1086 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
8feceb67
VT		 1087 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1088 /* LED off, active low */
08fc5c1b 1089 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
7dcfdcd9 1090
f2bffa7e
VT		 1091 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1092
8feceb67
VT		 1093 trigger = ieee80211_get_radio_led_name(sc->hw);
1094 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1095 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1096 ret = ath_register_led(sc, &sc->radio_led, trigger);
1097 sc->radio_led.led_type = ATH_LED_RADIO;
1098 if (ret)
1099 goto fail;
7dcfdcd9 1100
8feceb67
VT		 1101 trigger = ieee80211_get_assoc_led_name(sc->hw);
1102 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1103 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1104 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1105 sc->assoc_led.led_type = ATH_LED_ASSOC;
1106 if (ret)
1107 goto fail;
f078f209 1108
8feceb67
VT		 1109 trigger = ieee80211_get_tx_led_name(sc->hw);
1110 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1111 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1112 ret = ath_register_led(sc, &sc->tx_led, trigger);
1113 sc->tx_led.led_type = ATH_LED_TX;
1114 if (ret)
1115 goto fail;
f078f209 1116
8feceb67
VT		 1117 trigger = ieee80211_get_rx_led_name(sc->hw);
1118 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1119 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1120 ret = ath_register_led(sc, &sc->rx_led, trigger);
1121 sc->rx_led.led_type = ATH_LED_RX;
1122 if (ret)
1123 goto fail;
f078f209 1124
8feceb67
VT		 1125 return;
1126
1127fail:
35c95ab9 1128 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67 1129 ath_deinit_leds(sc);
f078f209
LR		 1130}
1131
7ec3e514 1132void ath_radio_enable(struct ath_softc *sc)
500c064d 1133{
cbe61d8a 1134 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1135 struct ieee80211_channel *channel = sc->hw->conf.channel;
1136 int r;
500c064d 1137
3cbb5dd7 1138 ath9k_ps_wakeup(sc);
93b1b37f 1139 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 1140
159cd468
VT		 1141 if (!ah->curchan)
1142 ah->curchan = ath_get_curchannel(sc, sc->hw);
1143
d2f5b3a6 1144 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1145 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1146 if (r) {
4d6b228d 1147 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
ae8d2858 1148 "Unable to reset channel %u (%uMhz) ",
6b45784f 1149 "reset status %d\n",
ae8d2858 1150 channel->center_freq, r);
500c064d
VT		 1151 }
1152 spin_unlock_bh(&sc->sc_resetlock);
1153
1154 ath_update_txpow(sc);
1155 if (ath_startrecv(sc) != 0) {
4d6b228d 1156 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
04bd4638 1157 "Unable to restart recv logic\n");
500c064d
VT		 1158 return;
1159 }
1160
1161 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1162 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1163
1164 /* Re-Enable interrupts */
17d7904d 1165 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1166
1167 /* Enable LED */
08fc5c1b 1168 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 1169 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 1170 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d
VT		 1171
1172 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1173 ath9k_ps_restore(sc);
500c064d
VT		 1174}
1175
7ec3e514 1176void ath_radio_disable(struct ath_softc *sc)
500c064d 1177{
cbe61d8a 1178 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1179 struct ieee80211_channel *channel = sc->hw->conf.channel;
1180 int r;
500c064d 1181
3cbb5dd7 1182 ath9k_ps_wakeup(sc);
500c064d
VT		 1183 ieee80211_stop_queues(sc->hw);
1184
1185 /* Disable LED */
08fc5c1b
VN		 1186 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1187 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT		 1188
1189 /* Disable interrupts */
1190 ath9k_hw_set_interrupts(ah, 0);
1191
043a0405 1192 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1193 ath_stoprecv(sc); /* turn off frame recv */
1194 ath_flushrecv(sc); /* flush recv queue */
1195
159cd468
VT		 1196 if (!ah->curchan)
1197 ah->curchan = ath_get_curchannel(sc, sc->hw);
1198
500c064d 1199 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1200 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1201 if (r) {
4d6b228d 1202 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
04bd4638 1203 "Unable to reset channel %u (%uMhz) "
6b45784f 1204 "reset status %d\n",
ae8d2858 1205 channel->center_freq, r);
500c064d
VT		 1206 }
1207 spin_unlock_bh(&sc->sc_resetlock);
1208
1209 ath9k_hw_phy_disable(ah);
93b1b37f 1210 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 1211 ath9k_ps_restore(sc);
38ab422e 1212 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1213}
1214
5077fd35
GJ		 1215/*******************/
1216/* Rfkill */
1217/*******************/
1218
500c064d
VT		 1219static bool ath_is_rfkill_set(struct ath_softc *sc)
1220{
cbe61d8a 1221 struct ath_hw *ah = sc->sc_ah;
500c064d 1222
2660b81a
S		 1223 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1224 ah->rfkill_polarity;
500c064d
VT		 1225}
1226
3b319aae 1227static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1228{
3b319aae
JB		 1229 struct ath_wiphy *aphy = hw->priv;
1230 struct ath_softc *sc = aphy->sc;
19d337df 1231 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1232
3b319aae 1233 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
500c064d
VT		 1234}
1235
3b319aae 1236static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1237{
3b319aae 1238 struct ath_hw *ah = sc->sc_ah;
9c84b797 1239
3b319aae
JB		 1240 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1241 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1242}
500c064d 1243
6baff7f9 1244void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1245{
1246 ath_detach(sc);
1247 free_irq(sc->irq, sc);
1248 ath_bus_cleanup(sc);
c52f33d0 1249 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1250 ieee80211_free_hw(sc->hw);
1251}
1252
6baff7f9 1253void ath_detach(struct ath_softc *sc)
f078f209 1254{
8feceb67 1255 struct ieee80211_hw *hw = sc->hw;
4d6b228d 1256 struct ath_hw *ah = sc->sc_ah;
9c84b797 1257 int i = 0;
f078f209 1258
3cbb5dd7
VN		 1259 ath9k_ps_wakeup(sc);
1260
4d6b228d 1261 dev_dbg(sc->dev, "Detach ATH hw\n");
f078f209 1262
35c95ab9 1263 ath_deinit_leds(sc);
e31f7b96 1264 wiphy_rfkill_stop_polling(sc->hw->wiphy);
35c95ab9 1265
c52f33d0
JM		 1266 for (i = 0; i < sc->num_sec_wiphy; i++) {
1267 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1268 if (aphy == NULL)
1269 continue;
1270 sc->sec_wiphy[i] = NULL;
1271 ieee80211_unregister_hw(aphy->hw);
1272 ieee80211_free_hw(aphy->hw);
1273 }
3fcdfb4b 1274 ieee80211_unregister_hw(hw);
8feceb67
VT		 1275 ath_rx_cleanup(sc);
1276 ath_tx_cleanup(sc);
f078f209 1277
9c84b797
S		 1278 tasklet_kill(&sc->intr_tq);
1279 tasklet_kill(&sc->bcon_tasklet);
f078f209 1280
9c84b797 1281 if (!(sc->sc_flags & SC_OP_INVALID))
4d6b228d 1282 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
8feceb67 1283
9c84b797
S		 1284 /* cleanup tx queues */
1285 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1286 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1287 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797 1288
75d7839f 1289 if ((sc->btcoex.no_stomp_timer) &&
766ec4a9 1290 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1291 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1773912b 1292
4d6b228d 1293 ath9k_hw_detach(ah);
af03abec 1294 ath9k_exit_debug(ah);
3ce1b1a9 1295 sc->sc_ah = NULL;
f078f209
LR		 1296}
1297
e3bb249b
BC		 1298static int ath9k_reg_notifier(struct wiphy *wiphy,
1299 struct regulatory_request *request)
1300{
1301 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1302 struct ath_wiphy *aphy = hw->priv;
1303 struct ath_softc *sc = aphy->sc;
608b88cb 1304 struct ath_regulatory *reg = &sc->common.regulatory;
e3bb249b
BC		 1305
1306 return ath_reg_notifier_apply(wiphy, request, reg);
1307}
1308
75d7839f
LR		 1309/*
1310 * Detects if there is any priority bt traffic
1311 */
1312static void ath_detect_bt_priority(struct ath_softc *sc)
1313{
1314 struct ath_btcoex *btcoex = &sc->btcoex;
1315 struct ath_hw *ah = sc->sc_ah;
1316
766ec4a9 1317 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
75d7839f
LR		 1318 btcoex->bt_priority_cnt++;
1319
1320 if (time_after(jiffies, btcoex->bt_priority_time +
1321 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1322 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1323 DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX,
1324 "BT priority traffic detected");
1325 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1326 } else {
1327 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1328 }
1329
1330 btcoex->bt_priority_cnt = 0;
1331 btcoex->bt_priority_time = jiffies;
1332 }
1333}
1334
269ad812
LR		 1335static void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
1336 u32 bt_weight,
1337 u32 wlan_weight)
75d7839f 1338{
269ad812
LR		 1339 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1340
766ec4a9 1341 btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
269ad812 1342 SM(wlan_weight, AR_BTCOEX_WL_WGHT);
75d7839f
LR		 1343}
1344
1345static void ath9k_hw_btcoex_init_weight(struct ath_hw *ah)
1346{
269ad812 1347 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, AR_STOMP_LOW_WLAN_WGHT);
75d7839f
LR		 1348}
1349
1350/*
1351 * Configures appropriate weight based on stomp type.
1352 */
269ad812
LR		 1353static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1354 enum ath_stomp_type stomp_type)
75d7839f 1355{
269ad812 1356 struct ath_hw *ah = sc->sc_ah;
75d7839f
LR		 1357
1358 switch (stomp_type) {
1359 case ATH_BTCOEX_STOMP_ALL:
269ad812
LR		 1360 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1361 AR_STOMP_ALL_WLAN_WGHT);
75d7839f
LR		 1362 break;
1363 case ATH_BTCOEX_STOMP_LOW:
269ad812
LR		 1364 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1365 AR_STOMP_LOW_WLAN_WGHT);
75d7839f
LR		 1366 break;
1367 case ATH_BTCOEX_STOMP_NONE:
269ad812
LR		 1368 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1369 AR_STOMP_NONE_WLAN_WGHT);
75d7839f
LR		 1370 break;
1371 default:
269ad812 1372 DPRINTF(ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
75d7839f
LR		 1373 break;
1374 }
1375
269ad812 1376 ath9k_hw_btcoex_enable(ah);
75d7839f
LR		 1377}
1378
1379/*
1380 * This is the master bt coex timer which runs for every
1381 * 45ms, bt traffic will be given priority during 55% of this
1382 * period while wlan gets remaining 45%
1383 */
1384static void ath_btcoex_period_timer(unsigned long data)
1385{
1386 struct ath_softc *sc = (struct ath_softc *) data;
1387 struct ath_hw *ah = sc->sc_ah;
1388 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f
LR		 1389
1390 ath_detect_bt_priority(sc);
1391
1392 spin_lock_bh(&btcoex->btcoex_lock);
1393
269ad812 1394 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
75d7839f
LR		 1395
1396 spin_unlock_bh(&btcoex->btcoex_lock);
1397
1398 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1399 if (btcoex->hw_timer_enabled)
1400 ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
1401
1402 ath_gen_timer_start(ah,
1403 btcoex->no_stomp_timer,
1404 (ath9k_hw_gettsf32(ah) +
1405 btcoex->btcoex_no_stomp),
1406 btcoex->btcoex_no_stomp * 10);
1407 btcoex->hw_timer_enabled = true;
1408 }
1409
1410 mod_timer(&btcoex->period_timer, jiffies +
1411 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1412}
1413
1414/*
1415 * Generic tsf based hw timer which configures weight
1416 * registers to time slice between wlan and bt traffic
1417 */
1418static void ath_btcoex_no_stomp_timer(void *arg)
1419{
1420 struct ath_softc *sc = (struct ath_softc *)arg;
1421 struct ath_hw *ah = sc->sc_ah;
1422 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f
LR		 1423
1424 DPRINTF(ah, ATH_DBG_BTCOEX, "no stomp timer running \n");
1425
1426 spin_lock_bh(&btcoex->btcoex_lock);
1427
e08a6ace 1428 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
269ad812 1429 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
e08a6ace 1430 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
269ad812 1431 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
75d7839f
LR		 1432
1433 spin_unlock_bh(&btcoex->btcoex_lock);
1434}
1435
1436static int ath_init_btcoex_timer(struct ath_softc *sc)
1437{
1438 struct ath_btcoex *btcoex = &sc->btcoex;
1439
1440 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1441 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1442 btcoex->btcoex_period / 100;
1443
1444 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1445 (unsigned long) sc);
1446
1447 spin_lock_init(&btcoex->btcoex_lock);
1448
1449 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1450 ath_btcoex_no_stomp_timer,
1451 ath_btcoex_no_stomp_timer,
1452 (void *) sc, AR_FIRST_NDP_TIMER);
1453
1454 if (!btcoex->no_stomp_timer)
1455 return -ENOMEM;
1456
1457 return 0;
1458}
1459
1e40bcfa
LR		 1460/*
1461 * Initialize and fill ath_softc, ath_sofct is the
1462 * "Software Carrier" struct. Historically it has existed
1463 * to allow the separation between hardware specific
1464 * variables (now in ath_hw) and driver specific variables.
1465 */
aeac355d 1466static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
ff37e337 1467{
cbe61d8a 1468 struct ath_hw *ah = NULL;
4f3acf81 1469 int r = 0, i;
ff37e337 1470 int csz = 0;
75d7839f 1471 int qnum;
ff37e337
S		 1472
1473 /* XXX: hardware will not be ready until ath_open() being called */
1474 sc->sc_flags |= SC_OP_INVALID;
88b126af 1475
c52f33d0 1476 spin_lock_init(&sc->wiphy_lock);
ff37e337 1477 spin_lock_init(&sc->sc_resetlock);
6158425b 1478 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1479 spin_lock_init(&sc->ani_lock);
04717ccd 1480 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1481 mutex_init(&sc->mutex);
ff37e337 1482 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1483 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1484 (unsigned long)sc);
1485
1486 /*
1487 * Cache line size is used to size and align various
1488 * structures used to communicate with the hardware.
1489 */
88d15707 1490 ath_read_cachesize(sc, &csz);
ff37e337 1491 /* XXX assert csz is non-zero */
d15dd3e5 1492 sc->common.cachelsz = csz << 2; /* convert to bytes */
ff37e337 1493
4f3acf81
LR		 1494 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1495 if (!ah) {
4f3acf81
LR		 1496 r = -ENOMEM;
1497 goto bad_no_ah;
1498 }
1499
1500 ah->ah_sc = sc;
8df5d1b7 1501 ah->hw_version.devid = devid;
aeac355d 1502 ah->hw_version.subsysid = subsysid;
e1e2f93f 1503 sc->sc_ah = ah;
4f3acf81 1504
4d6b228d
LR		 1505 if (ath9k_init_debug(ah) < 0)
1506 dev_err(sc->dev, "Unable to create debugfs files\n");
1507
f637cfd6 1508 r = ath9k_hw_init(ah);
4f3acf81 1509 if (r) {
4d6b228d 1510 DPRINTF(ah, ATH_DBG_FATAL,
f637cfd6 1511 "Unable to initialize hardware; "
4f3acf81 1512 "initialization status: %d\n", r);
ff37e337
S		 1513 goto bad;
1514 }
ff37e337
S		 1515
1516 /* Get the hardware key cache size. */
2660b81a 1517 sc->keymax = ah->caps.keycache_size;
17d7904d 1518 if (sc->keymax > ATH_KEYMAX) {
4d6b228d 1519 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 1520 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1521 ATH_KEYMAX, sc->keymax);
1522 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1523 }
1524
1525 /*
1526 * Reset the key cache since some parts do not
1527 * reset the contents on initial power up.
1528 */
17d7904d 1529 for (i = 0; i < sc->keymax; i++)
ff37e337 1530 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1531
ff37e337 1532 /* default to MONITOR mode */
2660b81a 1533 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1534
ff37e337
S		 1535 /* Setup rate tables */
1536
1537 ath_rate_attach(sc);
1538 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1539 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1540
1541 /*
1542 * Allocate hardware transmit queues: one queue for
1543 * beacon frames and one data queue for each QoS
1544 * priority. Note that the hal handles reseting
1545 * these queues at the needed time.
1546 */
b77f483f
S		 1547 sc->beacon.beaconq = ath_beaconq_setup(ah);
1548 if (sc->beacon.beaconq == -1) {
4d6b228d 1549 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1550 "Unable to setup a beacon xmit queue\n");
4f3acf81 1551 r = -EIO;
ff37e337
S		 1552 goto bad2;
1553 }
b77f483f
S		 1554 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1555 if (sc->beacon.cabq == NULL) {
4d6b228d 1556 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1557 "Unable to setup CAB xmit queue\n");
4f3acf81 1558 r = -EIO;
ff37e337
S		 1559 goto bad2;
1560 }
1561
17d7904d 1562 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1563 ath_cabq_update(sc);
1564
b77f483f
S		 1565 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1566 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1567
1568 /* Setup data queues */
1569 /* NB: ensure BK queue is the lowest priority h/w queue */
1570 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
4d6b228d 1571 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1572 "Unable to setup xmit queue for BK traffic\n");
4f3acf81 1573 r = -EIO;
ff37e337
S		 1574 goto bad2;
1575 }
1576
1577 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
4d6b228d 1578 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1579 "Unable to setup xmit queue for BE traffic\n");
4f3acf81 1580 r = -EIO;
ff37e337
S		 1581 goto bad2;
1582 }
1583 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
4d6b228d 1584 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1585 "Unable to setup xmit queue for VI traffic\n");
4f3acf81 1586 r = -EIO;
ff37e337
S		 1587 goto bad2;
1588 }
1589 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
4d6b228d 1590 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1591 "Unable to setup xmit queue for VO traffic\n");
4f3acf81 1592 r = -EIO;
ff37e337
S		 1593 goto bad2;
1594 }
1595
1596 /* Initializes the noise floor to a reasonable default value.
1597 * Later on this will be updated during ANI processing. */
1598
17d7904d
S		 1599 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1600 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1601
1602 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1603 ATH9K_CIPHER_TKIP, NULL)) {
1604 /*
1605 * Whether we should enable h/w TKIP MIC.
1606 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1607 * report WMM capable, so it's always safe to turn on
1608 * TKIP MIC in this case.
1609 */
1610 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1611 0, 1, NULL);
1612 }
1613
1614 /*
1615 * Check whether the separate key cache entries
1616 * are required to handle both tx+rx MIC keys.
1617 * With split mic keys the number of stations is limited
1618 * to 27 otherwise 59.
1619 */
1620 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1621 ATH9K_CIPHER_TKIP, NULL)
1622 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1623 ATH9K_CIPHER_MIC, NULL)
1624 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1625 0, NULL))
17d7904d 1626 sc->splitmic = 1;
ff37e337
S		 1627
1628 /* turn on mcast key search if possible */
1629 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1630 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1631 1, NULL);
1632
17d7904d 1633 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1634
1635 /* 11n Capabilities */
2660b81a 1636 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1637 sc->sc_flags |= SC_OP_TXAGGR;
1638 sc->sc_flags |= SC_OP_RXAGGR;
1639 }
1640
2660b81a
S		 1641 sc->tx_chainmask = ah->caps.tx_chainmask;
1642 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1643
1644 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1645 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1646
8ca21f01 1647 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1648 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1649
b77f483f 1650 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1651
1652 /* initialize beacon slots */
c52f33d0 1653 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1654 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1655 sc->beacon.bslot_aphy[i] = NULL;
1656 }
ff37e337 1657
ff37e337
S		 1658 /* setup channels and rates */
1659
5f8e077c 1660 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1661 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1662 sc->rates[IEEE80211_BAND_2GHZ];
1663 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1664 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1665 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1666
2660b81a 1667 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1668 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1669 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1670 sc->rates[IEEE80211_BAND_5GHZ];
1671 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1672 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1673 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1674 }
1675
766ec4a9 1676 switch (ah->btcoex_hw.scheme) {
75d7839f
LR		 1677 case ATH_BTCOEX_CFG_NONE:
1678 break;
1679 case ATH_BTCOEX_CFG_2WIRE:
1680 ath9k_hw_btcoex_init_2wire(ah);
1681 break;
1682 case ATH_BTCOEX_CFG_3WIRE:
1683 ath9k_hw_btcoex_init_3wire(ah);
1684 r = ath_init_btcoex_timer(sc);
1773912b
VT		 1685 if (r)
1686 goto bad2;
75d7839f 1687 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
766ec4a9 1688 ath9k_hw_init_btcoex_hw(ah, qnum);
e08a6ace 1689 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
75d7839f
LR		 1690 break;
1691 default:
1692 WARN_ON(1);
1693 break;
1773912b 1694 }
c97c92d9 1695
ff37e337
S		 1696 return 0;
1697bad2:
1698 /* cleanup tx queues */
1699 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1700 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1701 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337 1702bad:
95fafca2 1703 ath9k_hw_detach(ah);
4f3acf81 1704bad_no_ah:
4d6b228d
LR		 1705 ath9k_exit_debug(sc->sc_ah);
1706 sc->sc_ah = NULL;
ff37e337 1707
4f3acf81 1708 return r;
ff37e337
S		 1709}
1710
c52f33d0 1711void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1712{
9c84b797
S		 1713 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1714 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1715 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1716 IEEE80211_HW_AMPDU_AGGREGATION |
1717 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1718 IEEE80211_HW_PS_NULLFUNC_STACK |
1719 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1720
b3bd89ce 1721 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1722 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1723
9c84b797
S		 1724 hw->wiphy->interface_modes =
1725 BIT(NL80211_IFTYPE_AP) |
1726 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1727 BIT(NL80211_IFTYPE_ADHOC) |
1728 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1729
8feceb67 1730 hw->queues = 4;
e63835b0 1731 hw->max_rates = 4;
171387ef 1732 hw->channel_change_time = 5000;
465ca84d 1733 hw->max_listen_interval = 10;
dd190183
LR		 1734 /* Hardware supports 10 but we use 4 */
1735 hw->max_rate_tries = 4;
528f0c6b 1736 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1737 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1738
8feceb67 1739 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1740
c52f33d0
JM		 1741 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1742 &sc->sbands[IEEE80211_BAND_2GHZ];
1743 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1744 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1745 &sc->sbands[IEEE80211_BAND_5GHZ];
1746}
1747
1e40bcfa 1748/* Device driver core initialization */
aeac355d 1749int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
c52f33d0
JM		 1750{
1751 struct ieee80211_hw *hw = sc->hw;
4d6b228d 1752 struct ath_hw *ah;
c52f33d0 1753 int error = 0, i;
3a702e49 1754 struct ath_regulatory *reg;
c52f33d0 1755
4d6b228d 1756 dev_dbg(sc->dev, "Attach ATH hw\n");
c52f33d0 1757
aeac355d 1758 error = ath_init_softc(devid, sc, subsysid);
c52f33d0
JM		 1759 if (error != 0)
1760 return error;
1761
4d6b228d
LR		 1762 ah = sc->sc_ah;
1763
c52f33d0
JM		 1764 /* get mac address from hardware and set in mac80211 */
1765
4d6b228d 1766 SET_IEEE80211_PERM_ADDR(hw, ah->macaddr);
c52f33d0
JM		 1767
1768 ath_set_hw_capab(sc, hw);
1769
608b88cb 1770 error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy,
c26c2e57
LR		 1771 ath9k_reg_notifier);
1772 if (error)
1773 return error;
1774
608b88cb 1775 reg = &sc->common.regulatory;
c26c2e57 1776
4d6b228d 1777 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1778 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
4d6b228d 1779 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
eb2599ca 1780 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1781 }
1782
db93e7b5
SB		 1783 /* initialize tx/rx engine */
1784 error = ath_tx_init(sc, ATH_TXBUF);
1785 if (error != 0)
40b130a9 1786 goto error_attach;
8feceb67 1787
db93e7b5
SB		 1788 error = ath_rx_init(sc, ATH_RXBUF);
1789 if (error != 0)
40b130a9 1790 goto error_attach;
8feceb67 1791
0e2dedf9 1792 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1793 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1794 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1795
db93e7b5 1796 error = ieee80211_register_hw(hw);
8feceb67 1797
3a702e49 1798 if (!ath_is_world_regd(reg)) {
c02cf373 1799 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1800 if (error)
1801 goto error_attach;
1802 }
5f8e077c 1803
db93e7b5
SB		 1804 /* Initialize LED control */
1805 ath_init_leds(sc);
8feceb67 1806
3b319aae 1807 ath_start_rfkill_poll(sc);
5f8e077c 1808
8feceb67 1809 return 0;
40b130a9
VT		 1810
1811error_attach:
1812 /* cleanup tx queues */
1813 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1814 if (ATH_TXQ_SETUP(sc, i))
1815 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1816
4d6b228d
LR		 1817 ath9k_hw_detach(ah);
1818 ath9k_exit_debug(ah);
3ce1b1a9 1819 sc->sc_ah = NULL;
40b130a9 1820
8feceb67 1821 return error;
f078f209
LR		 1822}
1823
ff37e337
S		 1824int ath_reset(struct ath_softc *sc, bool retry_tx)
1825{
cbe61d8a 1826 struct ath_hw *ah = sc->sc_ah;
030bb495 1827 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1828 int r;
ff37e337
S		 1829
1830 ath9k_hw_set_interrupts(ah, 0);
043a0405 1831 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1832 ath_stoprecv(sc);
1833 ath_flushrecv(sc);
1834
1835 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1836 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1837 if (r)
4d6b228d 1838 DPRINTF(ah, ATH_DBG_FATAL,
6b45784f 1839 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1840 spin_unlock_bh(&sc->sc_resetlock);
1841
1842 if (ath_startrecv(sc) != 0)
4d6b228d 1843 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1844
1845 /*
1846 * We may be doing a reset in response to a request
1847 * that changes the channel so update any state that
1848 * might change as a result.
1849 */
ce111bad 1850 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1851
1852 ath_update_txpow(sc);
1853
1854 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1855 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1856
17d7904d 1857 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1858
1859 if (retry_tx) {
1860 int i;
1861 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1862 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1863 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1864 ath_txq_schedule(sc, &sc->tx.txq[i]);
1865 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1866 }
1867 }
1868 }
1869
ae8d2858 1870 return r;
ff37e337
S		 1871}
1872
1873/*
1874 * This function will allocate both the DMA descriptor structure, and the
1875 * buffers it contains. These are used to contain the descriptors used
1876 * by the system.
1877*/
1878int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1879 struct list_head *head, const char *name,
1880 int nbuf, int ndesc)
1881{
1882#define DS2PHYS(_dd, _ds) \
1883 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1884#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1885#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1886
1887 struct ath_desc *ds;
1888 struct ath_buf *bf;
1889 int i, bsize, error;
1890
4d6b228d 1891 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
04bd4638 1892 name, nbuf, ndesc);
ff37e337 1893
b03a9db9 1894 INIT_LIST_HEAD(head);
ff37e337
S		 1895 /* ath_desc must be a multiple of DWORDs */
1896 if ((sizeof(struct ath_desc) % 4) != 0) {
4d6b228d 1897 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1898 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1899 error = -ENOMEM;
1900 goto fail;
1901 }
1902
ff37e337
S		 1903 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1904
1905 /*
1906 * Need additional DMA memory because we can't use
1907 * descriptors that cross the 4K page boundary. Assume
1908 * one skipped descriptor per 4K page.
1909 */
2660b81a 1910 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1911 u32 ndesc_skipped =
1912 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1913 u32 dma_len;
1914
1915 while (ndesc_skipped) {
1916 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1917 dd->dd_desc_len += dma_len;
1918
1919 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1920 };
1921 }
1922
1923 /* allocate descriptors */
7da3c55c 1924 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1925 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1926 if (dd->dd_desc == NULL) {
1927 error = -ENOMEM;
1928 goto fail;
1929 }
1930 ds = dd->dd_desc;
4d6b228d 1931 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1932 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1933 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1934
1935 /* allocate buffers */
1936 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1937 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1938 if (bf == NULL) {
1939 error = -ENOMEM;
1940 goto fail2;
1941 }
ff37e337
S		 1942 dd->dd_bufptr = bf;
1943
ff37e337
S		 1944 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1945 bf->bf_desc = ds;
1946 bf->bf_daddr = DS2PHYS(dd, ds);
1947
2660b81a 1948 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1949 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1950 /*
1951 * Skip descriptor addresses which can cause 4KB
1952 * boundary crossing (addr + length) with a 32 dword
1953 * descriptor fetch.
1954 */
1955 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1956 ASSERT((caddr_t) bf->bf_desc <
1957 ((caddr_t) dd->dd_desc +
1958 dd->dd_desc_len));
1959
1960 ds += ndesc;
1961 bf->bf_desc = ds;
1962 bf->bf_daddr = DS2PHYS(dd, ds);
1963 }
1964 }
1965 list_add_tail(&bf->list, head);
1966 }
1967 return 0;
1968fail2:
7da3c55c
GJ		 1969 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1970 dd->dd_desc_paddr);
ff37e337
S		 1971fail:
1972 memset(dd, 0, sizeof(*dd));
1973 return error;
1974#undef ATH_DESC_4KB_BOUND_CHECK
1975#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1976#undef DS2PHYS
1977}
1978
1979void ath_descdma_cleanup(struct ath_softc *sc,
1980 struct ath_descdma *dd,
1981 struct list_head *head)
1982{
7da3c55c
GJ		 1983 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1984 dd->dd_desc_paddr);
ff37e337
S		 1985
1986 INIT_LIST_HEAD(head);
1987 kfree(dd->dd_bufptr);
1988 memset(dd, 0, sizeof(*dd));
1989}
1990
1991int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1992{
1993 int qnum;
1994
1995 switch (queue) {
1996 case 0:
b77f483f 1997 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1998 break;
1999 case 1:
b77f483f 2000 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 2001 break;
2002 case 2:
b77f483f 2003 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2004 break;
2005 case 3:
b77f483f 2006 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 2007 break;
2008 default:
b77f483f 2009 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2010 break;
2011 }
2012
2013 return qnum;
2014}
2015
2016int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2017{
2018 int qnum;
2019
2020 switch (queue) {
2021 case ATH9K_WME_AC_VO:
2022 qnum = 0;
2023 break;
2024 case ATH9K_WME_AC_VI:
2025 qnum = 1;
2026 break;
2027 case ATH9K_WME_AC_BE:
2028 qnum = 2;
2029 break;
2030 case ATH9K_WME_AC_BK:
2031 qnum = 3;
2032 break;
2033 default:
2034 qnum = -1;
2035 break;
2036 }
2037
2038 return qnum;
2039}
2040
5f8e077c
LR		 2041/* XXX: Remove me once we don't depend on ath9k_channel for all
2042 * this redundant data */
0e2dedf9
JM		 2043void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2044 struct ath9k_channel *ichan)
5f8e077c 2045{
5f8e077c
LR		 2046 struct ieee80211_channel *chan = hw->conf.channel;
2047 struct ieee80211_conf *conf = &hw->conf;
2048
2049 ichan->channel = chan->center_freq;
2050 ichan->chan = chan;
2051
2052 if (chan->band == IEEE80211_BAND_2GHZ) {
2053 ichan->chanmode = CHANNEL_G;
8813262e 2054 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR		 2055 } else {
2056 ichan->chanmode = CHANNEL_A;
2057 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2058 }
2059
2060 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2061
2062 if (conf_is_ht(conf)) {
2063 if (conf_is_ht40(conf))
2064 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2065
2066 ichan->chanmode = ath_get_extchanmode(sc, chan,
2067 conf->channel_type);
2068 }
2069}
2070
ff37e337
S		 2071/**********************/
2072/* mac80211 callbacks */
2073/**********************/
2074
75d7839f
LR		 2075/*
2076 * (Re)start btcoex timers
2077 */
2078static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2079{
2080 struct ath_btcoex *btcoex = &sc->btcoex;
2081 struct ath_hw *ah = sc->sc_ah;
2082
2083 DPRINTF(ah, ATH_DBG_BTCOEX, "Starting btcoex timers");
2084
2085 /* make sure duty cycle timer is also stopped when resuming */
2086 if (btcoex->hw_timer_enabled)
2087 ath_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2088
2089 btcoex->bt_priority_cnt = 0;
2090 btcoex->bt_priority_time = jiffies;
2091 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2092
2093 mod_timer(&btcoex->period_timer, jiffies);
2094}
2095
8feceb67 2096static int ath9k_start(struct ieee80211_hw *hw)
f078f209 2097{
bce048d7
JM		 2098 struct ath_wiphy *aphy = hw->priv;
2099 struct ath_softc *sc = aphy->sc;
af03abec 2100 struct ath_hw *ah = sc->sc_ah;
8feceb67 2101 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 2102 struct ath9k_channel *init_channel;
82880a7c 2103 int r;
f078f209 2104
af03abec 2105 DPRINTF(ah, ATH_DBG_CONFIG, "Starting driver with "
04bd4638 2106 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 2107
141b38b6
S		 2108 mutex_lock(&sc->mutex);
2109
9580a222
JM		 2110 if (ath9k_wiphy_started(sc)) {
2111 if (sc->chan_idx == curchan->hw_value) {
2112 /*
2113 * Already on the operational channel, the new wiphy
2114 * can be marked active.
2115 */
2116 aphy->state = ATH_WIPHY_ACTIVE;
2117 ieee80211_wake_queues(hw);
2118 } else {
2119 /*
2120 * Another wiphy is on another channel, start the new
2121 * wiphy in paused state.
2122 */
2123 aphy->state = ATH_WIPHY_PAUSED;
2124 ieee80211_stop_queues(hw);
2125 }
2126 mutex_unlock(&sc->mutex);
2127 return 0;
2128 }
2129 aphy->state = ATH_WIPHY_ACTIVE;
2130
8feceb67 2131 /* setup initial channel */
f078f209 2132
82880a7c 2133 sc->chan_idx = curchan->hw_value;
f078f209 2134
82880a7c 2135 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 2136
2137 /* Reset SERDES registers */
af03abec 2138 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S		 2139
2140 /*
2141 * The basic interface to setting the hardware in a good
2142 * state is ``reset''. On return the hardware is known to
2143 * be powered up and with interrupts disabled. This must
2144 * be followed by initialization of the appropriate bits
2145 * and then setup of the interrupt mask.
2146 */
2147 spin_lock_bh(&sc->sc_resetlock);
af03abec 2148 r = ath9k_hw_reset(ah, init_channel, false);
ae8d2858 2149 if (r) {
af03abec 2150 DPRINTF(ah, ATH_DBG_FATAL,
6b45784f 2151 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 2152 "(freq %u MHz)\n", r,
2153 curchan->center_freq);
ff37e337 2154 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2155 goto mutex_unlock;
ff37e337
S		 2156 }
2157 spin_unlock_bh(&sc->sc_resetlock);
2158
2159 /*
2160 * This is needed only to setup initial state
2161 * but it's best done after a reset.
2162 */
2163 ath_update_txpow(sc);
8feceb67 2164
ff37e337
S		 2165 /*
2166 * Setup the hardware after reset:
2167 * The receive engine is set going.
2168 * Frame transmit is handled entirely
2169 * in the frame output path; there's nothing to do
2170 * here except setup the interrupt mask.
2171 */
2172 if (ath_startrecv(sc) != 0) {
af03abec 2173 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 2174 r = -EIO;
2175 goto mutex_unlock;
f078f209 2176 }
8feceb67 2177
ff37e337 2178 /* Setup our intr mask. */
17d7904d 2179 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2180 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2181 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2182
af03abec 2183 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2184 sc->imask |= ATH9K_INT_GTT;
ff37e337 2185
af03abec 2186 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2187 sc->imask |= ATH9K_INT_CST;
ff37e337 2188
ce111bad 2189 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2190
2191 sc->sc_flags &= ~SC_OP_INVALID;
2192
2193 /* Disable BMISS interrupt when we're not associated */
17d7904d 2194 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
af03abec 2195 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337 2196
bce048d7 2197 ieee80211_wake_queues(hw);
ff37e337 2198
42935eca 2199 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 2200
766ec4a9
LR		 2201 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2202 !ah->btcoex_hw.enabled) {
af03abec
LR		 2203 ath9k_hw_btcoex_init_weight(ah);
2204 ath9k_hw_btcoex_enable(ah);
f985ad12 2205
7b6840ab 2206 ath_pcie_aspm_disable(sc);
766ec4a9 2207 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2208 ath9k_btcoex_timer_resume(sc);
1773912b
VT		 2209 }
2210
141b38b6
S		 2211mutex_unlock:
2212 mutex_unlock(&sc->mutex);
2213
ae8d2858 2214 return r;
f078f209
LR		 2215}
2216
8feceb67
VT		 2217static int ath9k_tx(struct ieee80211_hw *hw,
2218 struct sk_buff *skb)
f078f209 2219{
528f0c6b 2220 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2221 struct ath_wiphy *aphy = hw->priv;
2222 struct ath_softc *sc = aphy->sc;
528f0c6b 2223 struct ath_tx_control txctl;
8feceb67 2224 int hdrlen, padsize;
528f0c6b 2225
8089cc47 2226 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2227 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2228 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2229 goto exit;
2230 }
2231
96148326 2232 if (sc->ps_enabled) {
dc8c4585
JM		 2233 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2234 /*
2235 * mac80211 does not set PM field for normal data frames, so we
2236 * need to update that based on the current PS mode.
2237 */
2238 if (ieee80211_is_data(hdr->frame_control) &&
2239 !ieee80211_is_nullfunc(hdr->frame_control) &&
2240 !ieee80211_has_pm(hdr->frame_control)) {
4d6b228d 2241 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Add PM=1 for a TX frame "
dc8c4585
JM		 2242 "while in PS mode\n");
2243 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2244 }
2245 }
2246
9a23f9ca
JM		 2247 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2248 /*
2249 * We are using PS-Poll and mac80211 can request TX while in
2250 * power save mode. Need to wake up hardware for the TX to be
2251 * completed and if needed, also for RX of buffered frames.
2252 */
2253 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2254 ath9k_ps_wakeup(sc);
2255 ath9k_hw_setrxabort(sc->sc_ah, 0);
2256 if (ieee80211_is_pspoll(hdr->frame_control)) {
4d6b228d 2257 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Sending PS-Poll to pick a "
9a23f9ca
JM		 2258 "buffered frame\n");
2259 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2260 } else {
4d6b228d 2261 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Wake up to complete TX\n");
9a23f9ca
JM		 2262 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2263 }
2264 /*
2265 * The actual restore operation will happen only after
2266 * the sc_flags bit is cleared. We are just dropping
2267 * the ps_usecount here.
2268 */
2269 ath9k_ps_restore(sc);
2270 }
2271
528f0c6b 2272 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2273
8feceb67
VT		 2274 /*
2275 * As a temporary workaround, assign seq# here; this will likely need
2276 * to be cleaned up to work better with Beacon transmission and virtual
2277 * BSSes.
2278 */
2279 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2280 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2281 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2282 sc->tx.seq_no += 0x10;
8feceb67 2283 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2284 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2285 }
f078f209 2286
8feceb67
VT		 2287 /* Add the padding after the header if this is not already done */
2288 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2289 if (hdrlen & 3) {
2290 padsize = hdrlen % 4;
2291 if (skb_headroom(skb) < padsize)
2292 return -1;
2293 skb_push(skb, padsize);
2294 memmove(skb->data, skb->data + padsize, hdrlen);
2295 }
2296
528f0c6b
S		 2297 /* Check if a tx queue is available */
2298
2299 txctl.txq = ath_test_get_txq(sc, skb);
2300 if (!txctl.txq)
2301 goto exit;
2302
4d6b228d 2303 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2304
c52f33d0 2305 if (ath_tx_start(hw, skb, &txctl) != 0) {
4d6b228d 2306 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2307 goto exit;
8feceb67
VT		 2308 }
2309
528f0c6b
S		 2310 return 0;
2311exit:
2312 dev_kfree_skb_any(skb);
8feceb67 2313 return 0;
f078f209
LR		 2314}
2315
75d7839f
LR		 2316/*
2317 * Pause btcoex timer and bt duty cycle timer
2318 */
2319static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2320{
2321 struct ath_btcoex *btcoex = &sc->btcoex;
2322 struct ath_hw *ah = sc->sc_ah;
2323
2324 del_timer_sync(&btcoex->period_timer);
2325
2326 if (btcoex->hw_timer_enabled)
2327 ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
2328
2329 btcoex->hw_timer_enabled = false;
2330}
2331
8feceb67 2332static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2333{
bce048d7
JM		 2334 struct ath_wiphy *aphy = hw->priv;
2335 struct ath_softc *sc = aphy->sc;
af03abec 2336 struct ath_hw *ah = sc->sc_ah;
f078f209 2337
4c483817
S		 2338 mutex_lock(&sc->mutex);
2339
9580a222
JM		 2340 aphy->state = ATH_WIPHY_INACTIVE;
2341
c94dbff7
LR		 2342 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2343 cancel_delayed_work_sync(&sc->tx_complete_work);
2344
2345 if (!sc->num_sec_wiphy) {
2346 cancel_delayed_work_sync(&sc->wiphy_work);
2347 cancel_work_sync(&sc->chan_work);
2348 }
2349
9c84b797 2350 if (sc->sc_flags & SC_OP_INVALID) {
af03abec 2351 DPRINTF(ah, ATH_DBG_ANY, "Device not present\n");
4c483817 2352 mutex_unlock(&sc->mutex);
9c84b797
S		 2353 return;
2354 }
8feceb67 2355
9580a222
JM		 2356 if (ath9k_wiphy_started(sc)) {
2357 mutex_unlock(&sc->mutex);
2358 return; /* another wiphy still in use */
2359 }
2360
766ec4a9 2361 if (ah->btcoex_hw.enabled) {
af03abec 2362 ath9k_hw_btcoex_disable(ah);
766ec4a9 2363 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2364 ath9k_btcoex_timer_pause(sc);
1773912b
VT		 2365 }
2366
ff37e337
S		 2367 /* make sure h/w will not generate any interrupt
2368 * before setting the invalid flag. */
af03abec 2369 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S		 2370
2371 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2372 ath_drain_all_txq(sc, false);
ff37e337 2373 ath_stoprecv(sc);
af03abec 2374 ath9k_hw_phy_disable(ah);
ff37e337 2375 } else
b77f483f 2376 sc->rx.rxlink = NULL;
ff37e337 2377
ff37e337 2378 /* disable HAL and put h/w to sleep */
af03abec
LR		 2379 ath9k_hw_disable(ah);
2380 ath9k_hw_configpcipowersave(ah, 1, 1);
2381 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
ff37e337
S		 2382
2383 sc->sc_flags |= SC_OP_INVALID;
500c064d 2384
141b38b6
S		 2385 mutex_unlock(&sc->mutex);
2386
af03abec 2387 DPRINTF(ah, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2388}
2389
8feceb67
VT		 2390static int ath9k_add_interface(struct ieee80211_hw *hw,
2391 struct ieee80211_if_init_conf *conf)
f078f209 2392{
bce048d7
JM		 2393 struct ath_wiphy *aphy = hw->priv;
2394 struct ath_softc *sc = aphy->sc;
17d7904d 2395 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2396 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2397 int ret = 0;
8feceb67 2398
141b38b6
S		 2399 mutex_lock(&sc->mutex);
2400
8ca21f01
JM		 2401 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2402 sc->nvifs > 0) {
2403 ret = -ENOBUFS;
2404 goto out;
2405 }
2406
8feceb67 2407 switch (conf->type) {
05c914fe 2408 case NL80211_IFTYPE_STATION:
d97809db 2409 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2410 break;
05c914fe 2411 case NL80211_IFTYPE_ADHOC:
05c914fe 2412 case NL80211_IFTYPE_AP:
9cb5412b 2413 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2414 if (sc->nbcnvifs >= ATH_BCBUF) {
2415 ret = -ENOBUFS;
2416 goto out;
2417 }
9cb5412b 2418 ic_opmode = conf->type;
f078f209
LR		 2419 break;
2420 default:
4d6b228d 2421 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
04bd4638 2422 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2423 ret = -EOPNOTSUPP;
2424 goto out;
f078f209
LR		 2425 }
2426
4d6b228d 2427 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2428
17d7904d 2429 /* Set the VIF opmode */
5640b08e
S		 2430 avp->av_opmode = ic_opmode;
2431 avp->av_bslot = -1;
2432
2c3db3d5 2433 sc->nvifs++;
8ca21f01
JM		 2434
2435 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2436 ath9k_set_bssid_mask(hw);
2437
2c3db3d5
JM		 2438 if (sc->nvifs > 1)
2439 goto out; /* skip global settings for secondary vif */
2440
b238e90e 2441 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2442 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2443 sc->sc_flags |= SC_OP_TSF_RESET;
2444 }
5640b08e 2445
5640b08e 2446 /* Set the device opmode */
2660b81a 2447 sc->sc_ah->opmode = ic_opmode;
5640b08e 2448
4e30ffa2
VN		 2449 /*
2450 * Enable MIB interrupts when there are hardware phy counters.
2451 * Note we only do this (at the moment) for station mode.
2452 */
4af9cf4f 2453 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2454 (conf->type == NL80211_IFTYPE_ADHOC) ||
2455 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 2456 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S		 2457 sc->imask |= ATH9K_INT_TSFOOR;
2458 }
2459
17d7904d 2460 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2461
f38faa31
SB		 2462 if (conf->type == NL80211_IFTYPE_AP ||
2463 conf->type == NL80211_IFTYPE_ADHOC ||
2464 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2465 ath_start_ani(sc);
6f255425 2466
2c3db3d5 2467out:
141b38b6 2468 mutex_unlock(&sc->mutex);
2c3db3d5 2469 return ret;
f078f209
LR		 2470}
2471
8feceb67
VT		 2472static void ath9k_remove_interface(struct ieee80211_hw *hw,
2473 struct ieee80211_if_init_conf *conf)
f078f209 2474{
bce048d7
JM		 2475 struct ath_wiphy *aphy = hw->priv;
2476 struct ath_softc *sc = aphy->sc;
17d7904d 2477 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2478 int i;
f078f209 2479
4d6b228d 2480 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2481
141b38b6
S		 2482 mutex_lock(&sc->mutex);
2483
6f255425 2484 /* Stop ANI */
17d7904d 2485 del_timer_sync(&sc->ani.timer);
580f0b8a 2486
8feceb67 2487 /* Reclaim beacon resources */
9cb5412b
PE		 2488 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2489 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2490 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2491 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2492 ath_beacon_return(sc, avp);
580f0b8a 2493 }
f078f209 2494
8feceb67 2495 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2496
2c3db3d5
JM		 2497 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2498 if (sc->beacon.bslot[i] == conf->vif) {
2499 printk(KERN_DEBUG "%s: vif had allocated beacon "
2500 "slot\n", __func__);
2501 sc->beacon.bslot[i] = NULL;
c52f33d0 2502 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2503 }
2504 }
2505
17d7904d 2506 sc->nvifs--;
141b38b6
S		 2507
2508 mutex_unlock(&sc->mutex);
f078f209
LR		 2509}
2510
e8975581 2511static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2512{
bce048d7
JM		 2513 struct ath_wiphy *aphy = hw->priv;
2514 struct ath_softc *sc = aphy->sc;
e8975581 2515 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2516 struct ath_hw *ah = sc->sc_ah;
64839170 2517 bool all_wiphys_idle = false, disable_radio = false;
f078f209 2518
aa33de09 2519 mutex_lock(&sc->mutex);
141b38b6 2520
64839170
LR		 2521 /* Leave this as the first check */
2522 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2523
2524 spin_lock_bh(&sc->wiphy_lock);
2525 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2526 spin_unlock_bh(&sc->wiphy_lock);
2527
2528 if (conf->flags & IEEE80211_CONF_IDLE){
2529 if (all_wiphys_idle)
2530 disable_radio = true;
2531 }
2532 else if (all_wiphys_idle) {
2533 ath_radio_enable(sc);
4d6b228d 2534 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
64839170
LR		 2535 "not-idle: enabling radio\n");
2536 }
2537 }
2538
3cbb5dd7
VN		 2539 if (changed & IEEE80211_CONF_CHANGE_PS) {
2540 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2541 if (!(ah->caps.hw_caps &
2542 ATH9K_HW_CAP_AUTOSLEEP)) {
2543 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2544 sc->imask |= ATH9K_INT_TIM_TIMER;
2545 ath9k_hw_set_interrupts(sc->sc_ah,
2546 sc->imask);
2547 }
2548 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2549 }
96148326 2550 sc->ps_enabled = true;
3cbb5dd7 2551 } else {
96148326 2552 sc->ps_enabled = false;
3cbb5dd7 2553 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2554 if (!(ah->caps.hw_caps &
2555 ATH9K_HW_CAP_AUTOSLEEP)) {
2556 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2557 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2558 SC_OP_WAIT_FOR_CAB |
2559 SC_OP_WAIT_FOR_PSPOLL_DATA |
2560 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2561 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2562 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2563 ath9k_hw_set_interrupts(sc->sc_ah,
2564 sc->imask);
2565 }
3cbb5dd7
VN		 2566 }
2567 }
2568 }
2569
4797938c 2570 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2571 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2572 int pos = curchan->hw_value;
ae5eb026 2573
0e2dedf9
JM		 2574 aphy->chan_idx = pos;
2575 aphy->chan_is_ht = conf_is_ht(conf);
2576
8089cc47
JM		 2577 if (aphy->state == ATH_WIPHY_SCAN ||
2578 aphy->state == ATH_WIPHY_ACTIVE)
2579 ath9k_wiphy_pause_all_forced(sc, aphy);
2580 else {
2581 /*
2582 * Do not change operational channel based on a paused
2583 * wiphy changes.
2584 */
2585 goto skip_chan_change;
2586 }
0e2dedf9 2587
4d6b228d 2588 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
04bd4638 2589 curchan->center_freq);
f078f209 2590
5f8e077c 2591 /* XXX: remove me eventualy */
0e2dedf9 2592 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2593
ecf70441 2594 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2595
0e2dedf9 2596 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
4d6b228d 2597 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2598 mutex_unlock(&sc->mutex);
e11602b7
S		 2599 return -EINVAL;
2600 }
094d05dc 2601 }
f078f209 2602
8089cc47 2603skip_chan_change:
5c020dc6 2604 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2605 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2606
64839170 2607 if (disable_radio) {
4d6b228d 2608 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "idle: disabling radio\n");
64839170
LR		 2609 ath_radio_disable(sc);
2610 }
2611
aa33de09 2612 mutex_unlock(&sc->mutex);
141b38b6 2613
f078f209
LR		 2614 return 0;
2615}
2616
8feceb67
VT		 2617#define SUPPORTED_FILTERS \
2618 (FIF_PROMISC_IN_BSS | \
2619 FIF_ALLMULTI | \
2620 FIF_CONTROL | \
af6a3fc7 2621 FIF_PSPOLL | \
8feceb67
VT		 2622 FIF_OTHER_BSS | \
2623 FIF_BCN_PRBRESP_PROMISC | \
2624 FIF_FCSFAIL)
c83be688 2625
8feceb67
VT		 2626/* FIXME: sc->sc_full_reset ? */
2627static void ath9k_configure_filter(struct ieee80211_hw *hw,
2628 unsigned int changed_flags,
2629 unsigned int *total_flags,
3ac64bee 2630 u64 multicast)
8feceb67 2631{
bce048d7
JM		 2632 struct ath_wiphy *aphy = hw->priv;
2633 struct ath_softc *sc = aphy->sc;
8feceb67 2634 u32 rfilt;
f078f209 2635
8feceb67
VT		 2636 changed_flags &= SUPPORTED_FILTERS;
2637 *total_flags &= SUPPORTED_FILTERS;
f078f209 2638
b77f483f 2639 sc->rx.rxfilter = *total_flags;
aa68aeaa 2640 ath9k_ps_wakeup(sc);
8feceb67
VT		 2641 rfilt = ath_calcrxfilter(sc);
2642 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2643 ath9k_ps_restore(sc);
f078f209 2644
4d6b228d 2645 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 2646}
f078f209 2647
8feceb67
VT		 2648static void ath9k_sta_notify(struct ieee80211_hw *hw,
2649 struct ieee80211_vif *vif,
2650 enum sta_notify_cmd cmd,
17741cdc 2651 struct ieee80211_sta *sta)
8feceb67 2652{
bce048d7
JM		 2653 struct ath_wiphy *aphy = hw->priv;
2654 struct ath_softc *sc = aphy->sc;
f078f209 2655
8feceb67
VT		 2656 switch (cmd) {
2657 case STA_NOTIFY_ADD:
5640b08e 2658 ath_node_attach(sc, sta);
8feceb67
VT		 2659 break;
2660 case STA_NOTIFY_REMOVE:
b5aa9bf9 2661 ath_node_detach(sc, sta);
8feceb67
VT		 2662 break;
2663 default:
2664 break;
2665 }
f078f209
LR		 2666}
2667
141b38b6 2668static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2669 const struct ieee80211_tx_queue_params *params)
f078f209 2670{
bce048d7
JM		 2671 struct ath_wiphy *aphy = hw->priv;
2672 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2673 struct ath9k_tx_queue_info qi;
2674 int ret = 0, qnum;
f078f209 2675
8feceb67
VT		 2676 if (queue >= WME_NUM_AC)
2677 return 0;
f078f209 2678
141b38b6
S		 2679 mutex_lock(&sc->mutex);
2680
1ffb0610
S		 2681 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2682
8feceb67
VT		 2683 qi.tqi_aifs = params->aifs;
2684 qi.tqi_cwmin = params->cw_min;
2685 qi.tqi_cwmax = params->cw_max;
2686 qi.tqi_burstTime = params->txop;
2687 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2688
4d6b228d 2689 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
04bd4638 2690 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2691 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2692 queue, qnum, params->aifs, params->cw_min,
2693 params->cw_max, params->txop);
f078f209 2694
8feceb67
VT		 2695 ret = ath_txq_update(sc, qnum, &qi);
2696 if (ret)
4d6b228d 2697 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2698
141b38b6
S		 2699 mutex_unlock(&sc->mutex);
2700
8feceb67
VT		 2701 return ret;
2702}
f078f209 2703
8feceb67
VT		 2704static int ath9k_set_key(struct ieee80211_hw *hw,
2705 enum set_key_cmd cmd,
dc822b5d
JB		 2706 struct ieee80211_vif *vif,
2707 struct ieee80211_sta *sta,
8feceb67
VT		 2708 struct ieee80211_key_conf *key)
2709{
bce048d7
JM		 2710 struct ath_wiphy *aphy = hw->priv;
2711 struct ath_softc *sc = aphy->sc;
8feceb67 2712 int ret = 0;
f078f209 2713
b3bd89ce
JM		 2714 if (modparam_nohwcrypt)
2715 return -ENOSPC;
2716
141b38b6 2717 mutex_lock(&sc->mutex);
3cbb5dd7 2718 ath9k_ps_wakeup(sc);
4d6b228d 2719 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2720
8feceb67
VT		 2721 switch (cmd) {
2722 case SET_KEY:
3f53dd64 2723 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2724 if (ret >= 0) {
2725 key->hw_key_idx = ret;
8feceb67
VT		 2726 /* push IV and Michael MIC generation to stack */
2727 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2728 if (key->alg == ALG_TKIP)
2729 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2730 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2731 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2732 ret = 0;
8feceb67
VT		 2733 }
2734 break;
2735 case DISABLE_KEY:
2736 ath_key_delete(sc, key);
8feceb67
VT		 2737 break;
2738 default:
2739 ret = -EINVAL;
2740 }
f078f209 2741
3cbb5dd7 2742 ath9k_ps_restore(sc);
141b38b6
S		 2743 mutex_unlock(&sc->mutex);
2744
8feceb67
VT		 2745 return ret;
2746}
f078f209 2747
8feceb67
VT		 2748static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2749 struct ieee80211_vif *vif,
2750 struct ieee80211_bss_conf *bss_conf,
2751 u32 changed)
2752{
bce048d7
JM		 2753 struct ath_wiphy *aphy = hw->priv;
2754 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2755 struct ath_hw *ah = sc->sc_ah;
2756 struct ath_vif *avp = (void *)vif->drv_priv;
2757 u32 rfilt = 0;
2758 int error, i;
f078f209 2759
141b38b6
S		 2760 mutex_lock(&sc->mutex);
2761
2d0ddec5
JB		 2762 /*
2763 * TODO: Need to decide which hw opmode to use for
2764 * multi-interface cases
2765 * XXX: This belongs into add_interface!
2766 */
2767 if (vif->type == NL80211_IFTYPE_AP &&
2768 ah->opmode != NL80211_IFTYPE_AP) {
2769 ah->opmode = NL80211_IFTYPE_STATION;
2770 ath9k_hw_setopmode(ah);
2771 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2772 sc->curaid = 0;
2773 ath9k_hw_write_associd(sc);
2774 /* Request full reset to get hw opmode changed properly */
2775 sc->sc_flags |= SC_OP_FULL_RESET;
2776 }
2777
2778 if ((changed & BSS_CHANGED_BSSID) &&
2779 !is_zero_ether_addr(bss_conf->bssid)) {
2780 switch (vif->type) {
2781 case NL80211_IFTYPE_STATION:
2782 case NL80211_IFTYPE_ADHOC:
2783 case NL80211_IFTYPE_MESH_POINT:
2784 /* Set BSSID */
2785 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2786 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2787 sc->curaid = 0;
2788 ath9k_hw_write_associd(sc);
2789
2790 /* Set aggregation protection mode parameters */
2791 sc->config.ath_aggr_prot = 0;
2792
4d6b228d 2793 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2d0ddec5
JB		 2794 "RX filter 0x%x bssid %pM aid 0x%x\n",
2795 rfilt, sc->curbssid, sc->curaid);
2796
2797 /* need to reconfigure the beacon */
2798 sc->sc_flags &= ~SC_OP_BEACONS ;
2799
2800 break;
2801 default:
2802 break;
2803 }
2804 }
2805
2806 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2807 (vif->type == NL80211_IFTYPE_AP) ||
2808 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2809 if ((changed & BSS_CHANGED_BEACON) ||
2810 (changed & BSS_CHANGED_BEACON_ENABLED &&
2811 bss_conf->enable_beacon)) {
2812 /*
2813 * Allocate and setup the beacon frame.
2814 *
2815 * Stop any previous beacon DMA. This may be
2816 * necessary, for example, when an ibss merge
2817 * causes reconfiguration; we may be called
2818 * with beacon transmission active.
2819 */
2820 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2821
2822 error = ath_beacon_alloc(aphy, vif);
2823 if (!error)
2824 ath_beacon_config(sc, vif);
2825 }
2826 }
2827
2828 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2829 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2830 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2831 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2832 ath9k_hw_keysetmac(sc->sc_ah,
2833 (u16)i,
2834 sc->curbssid);
2835 }
2836
2837 /* Only legacy IBSS for now */
2838 if (vif->type == NL80211_IFTYPE_ADHOC)
2839 ath_update_chainmask(sc, 0);
2840
8feceb67 2841 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4d6b228d 2842 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2843 bss_conf->use_short_preamble);
2844 if (bss_conf->use_short_preamble)
2845 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2846 else
2847 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2848 }
f078f209 2849
8feceb67 2850 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
4d6b228d 2851 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2852 bss_conf->use_cts_prot);
2853 if (bss_conf->use_cts_prot &&
2854 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2855 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2856 else
2857 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2858 }
f078f209 2859
8feceb67 2860 if (changed & BSS_CHANGED_ASSOC) {
4d6b228d 2861 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2862 bss_conf->assoc);
5640b08e 2863 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2864 }
141b38b6 2865
57c4d7b4
JB		 2866 /*
2867 * The HW TSF has to be reset when the beacon interval changes.
2868 * We set the flag here, and ath_beacon_config_ap() would take this
2869 * into account when it gets called through the subsequent
2870 * config_interface() call - with IFCC_BEACON in the changed field.
2871 */
2872
2873 if (changed & BSS_CHANGED_BEACON_INT) {
2874 sc->sc_flags |= SC_OP_TSF_RESET;
2875 sc->beacon_interval = bss_conf->beacon_int;
2876 }
2877
141b38b6 2878 mutex_unlock(&sc->mutex);
8feceb67 2879}
f078f209 2880
8feceb67
VT		 2881static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2882{
2883 u64 tsf;
bce048d7
JM		 2884 struct ath_wiphy *aphy = hw->priv;
2885 struct ath_softc *sc = aphy->sc;
f078f209 2886
141b38b6
S		 2887 mutex_lock(&sc->mutex);
2888 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2889 mutex_unlock(&sc->mutex);
f078f209 2890
8feceb67
VT		 2891 return tsf;
2892}
f078f209 2893
3b5d665b
AF		 2894static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2895{
bce048d7
JM		 2896 struct ath_wiphy *aphy = hw->priv;
2897 struct ath_softc *sc = aphy->sc;
3b5d665b 2898
141b38b6
S		 2899 mutex_lock(&sc->mutex);
2900 ath9k_hw_settsf64(sc->sc_ah, tsf);
2901 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2902}
2903
8feceb67
VT		 2904static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2905{
bce048d7
JM		 2906 struct ath_wiphy *aphy = hw->priv;
2907 struct ath_softc *sc = aphy->sc;
c83be688 2908
141b38b6
S		 2909 mutex_lock(&sc->mutex);
2910 ath9k_hw_reset_tsf(sc->sc_ah);
2911 mutex_unlock(&sc->mutex);
8feceb67 2912}
f078f209 2913
8feceb67 2914static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2915 enum ieee80211_ampdu_mlme_action action,
2916 struct ieee80211_sta *sta,
2917 u16 tid, u16 *ssn)
8feceb67 2918{
bce048d7
JM		 2919 struct ath_wiphy *aphy = hw->priv;
2920 struct ath_softc *sc = aphy->sc;
8feceb67 2921 int ret = 0;
f078f209 2922
8feceb67
VT		 2923 switch (action) {
2924 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2925 if (!(sc->sc_flags & SC_OP_RXAGGR))
2926 ret = -ENOTSUPP;
8feceb67
VT		 2927 break;
2928 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2929 break;
2930 case IEEE80211_AMPDU_TX_START:
f83da965
S		 2931 ath_tx_aggr_start(sc, sta, tid, ssn);
2932 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2933 break;
2934 case IEEE80211_AMPDU_TX_STOP:
f83da965 2935 ath_tx_aggr_stop(sc, sta, tid);
17741cdc 2936 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2937 break;
b1720231 2938 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2939 ath_tx_aggr_resume(sc, sta, tid);
2940 break;
8feceb67 2941 default:
4d6b228d 2942 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2943 }
2944
2945 return ret;
f078f209
LR		 2946}
2947
0c98de65
S		 2948static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2949{
bce048d7
JM		 2950 struct ath_wiphy *aphy = hw->priv;
2951 struct ath_softc *sc = aphy->sc;
0c98de65 2952
3d832611 2953 mutex_lock(&sc->mutex);
8089cc47
JM		 2954 if (ath9k_wiphy_scanning(sc)) {
2955 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2956 "same time\n");
2957 /*
2958 * Do not allow the concurrent scanning state for now. This
2959 * could be improved with scanning control moved into ath9k.
2960 */
3d832611 2961 mutex_unlock(&sc->mutex);
8089cc47
JM		 2962 return;
2963 }
2964
2965 aphy->state = ATH_WIPHY_SCAN;
2966 ath9k_wiphy_pause_all_forced(sc, aphy);
2967
e5f0921a 2968 spin_lock_bh(&sc->ani_lock);
0c98de65 2969 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 2970 spin_unlock_bh(&sc->ani_lock);
3d832611 2971 mutex_unlock(&sc->mutex);
0c98de65
S		 2972}
2973
2974static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2975{
bce048d7
JM		 2976 struct ath_wiphy *aphy = hw->priv;
2977 struct ath_softc *sc = aphy->sc;
0c98de65 2978
3d832611 2979 mutex_lock(&sc->mutex);
e5f0921a 2980 spin_lock_bh(&sc->ani_lock);
8089cc47 2981 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2982 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2983 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 2984 spin_unlock_bh(&sc->ani_lock);
d0bec342 2985 ath_beacon_config(sc, NULL);
3d832611 2986 mutex_unlock(&sc->mutex);
0c98de65
S		 2987}
2988
6baff7f9 2989struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2990 .tx = ath9k_tx,
2991 .start = ath9k_start,
2992 .stop = ath9k_stop,
2993 .add_interface = ath9k_add_interface,
2994 .remove_interface = ath9k_remove_interface,
2995 .config = ath9k_config,
8feceb67 2996 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2997 .sta_notify = ath9k_sta_notify,
2998 .conf_tx = ath9k_conf_tx,
8feceb67 2999 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 3000 .set_key = ath9k_set_key,
8feceb67 3001 .get_tsf = ath9k_get_tsf,
3b5d665b 3002 .set_tsf = ath9k_set_tsf,
8feceb67 3003 .reset_tsf = ath9k_reset_tsf,
4233df6b 3004 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 3005 .sw_scan_start = ath9k_sw_scan_start,
3006 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 3007 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 3008};
3009
392dff83
BP		 3010static struct {
3011 u32 version;
3012 const char * name;
3013} ath_mac_bb_names[] = {
3014 { AR_SREV_VERSION_5416_PCI, "5416" },
3015 { AR_SREV_VERSION_5416_PCIE, "5418" },
3016 { AR_SREV_VERSION_9100, "9100" },
3017 { AR_SREV_VERSION_9160, "9160" },
3018 { AR_SREV_VERSION_9280, "9280" },
ac88b6ec
VN		 3019 { AR_SREV_VERSION_9285, "9285" },
3020 { AR_SREV_VERSION_9287, "9287" }
392dff83
BP		 3021};
3022
3023static struct {
3024 u16 version;
3025 const char * name;
3026} ath_rf_names[] = {
3027 { 0, "5133" },
3028 { AR_RAD5133_SREV_MAJOR, "5133" },
3029 { AR_RAD5122_SREV_MAJOR, "5122" },
3030 { AR_RAD2133_SREV_MAJOR, "2133" },
3031 { AR_RAD2122_SREV_MAJOR, "2122" }
3032};
3033
3034/*
3035 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3036 */
6baff7f9 3037const char *
392dff83
BP		 3038ath_mac_bb_name(u32 mac_bb_version)
3039{
3040 int i;
3041
3042 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3043 if (ath_mac_bb_names[i].version == mac_bb_version) {
3044 return ath_mac_bb_names[i].name;
3045 }
3046 }
3047
3048 return "????";
3049}
3050
3051/*
3052 * Return the RF name. "????" is returned if the RF is unknown.
3053 */
6baff7f9 3054const char *
392dff83
BP		 3055ath_rf_name(u16 rf_version)
3056{
3057 int i;
3058
3059 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3060 if (ath_rf_names[i].version == rf_version) {
3061 return ath_rf_names[i].name;
3062 }
3063 }
3064
3065 return "????";
3066}
3067
6baff7f9 3068static int __init ath9k_init(void)
f078f209 3069{
ca8a8560
VT		 3070 int error;
3071
ca8a8560
VT		 3072 /* Register rate control algorithm */
3073 error = ath_rate_control_register();
3074 if (error != 0) {
3075 printk(KERN_ERR
b51bb3cd
LR		 3076 "ath9k: Unable to register rate control "
3077 "algorithm: %d\n",
ca8a8560 3078 error);
6baff7f9 3079 goto err_out;
ca8a8560
VT		 3080 }
3081
19d8bc22
GJ		 3082 error = ath9k_debug_create_root();
3083 if (error) {
3084 printk(KERN_ERR
3085 "ath9k: Unable to create debugfs root: %d\n",
3086 error);
3087 goto err_rate_unregister;
3088 }
3089
6baff7f9
GJ		 3090 error = ath_pci_init();
3091 if (error < 0) {
f078f209 3092 printk(KERN_ERR
b51bb3cd 3093 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 3094 error = -ENODEV;
19d8bc22 3095 goto err_remove_root;
f078f209
LR		 3096 }
3097
09329d37
GJ		 3098 error = ath_ahb_init();
3099 if (error < 0) {
3100 error = -ENODEV;
3101 goto err_pci_exit;
3102 }
3103
f078f209 3104 return 0;
6baff7f9 3105
09329d37
GJ		 3106 err_pci_exit:
3107 ath_pci_exit();
3108
19d8bc22
GJ		 3109 err_remove_root:
3110 ath9k_debug_remove_root();
6baff7f9
GJ		 3111 err_rate_unregister:
3112 ath_rate_control_unregister();
3113 err_out:
3114 return error;
f078f209 3115}
6baff7f9 3116module_init(ath9k_init);
f078f209 3117
6baff7f9 3118static void __exit ath9k_exit(void)
f078f209 3119{
09329d37 3120 ath_ahb_exit();
6baff7f9 3121 ath_pci_exit();
19d8bc22 3122 ath9k_debug_remove_root();
ca8a8560 3123 ath_rate_control_unregister();
04bd4638 3124 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 3125}
6baff7f9 3126module_exit(ath9k_exit);
Linux 6.x block layer and io_uring tree(s)