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394cf0a1 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
394cf0a1 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef MAC_H | |
18 | #define MAC_H | |
19 | ||
a8c96d3b | 20 | #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ? \ |
394cf0a1 S |
21 | MS(ads->ds_rxstatus0, AR_RxRate) : \ |
22 | (ads->ds_rxstatus3 >> 2) & 0xFF) | |
23 | ||
24 | #define set11nTries(_series, _index) \ | |
25 | (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) | |
26 | ||
27 | #define set11nRate(_series, _index) \ | |
28 | (SM((_series)[_index].Rate, AR_XmitRate##_index)) | |
29 | ||
30 | #define set11nPktDurRTSCTS(_series, _index) \ | |
31 | (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \ | |
32 | ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \ | |
33 | AR_RTSCTSQual##_index : 0)) | |
34 | ||
35 | #define set11nRateFlags(_series, _index) \ | |
36 | (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ | |
37 | AR_2040_##_index : 0) \ | |
38 | |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ | |
39 | AR_GI##_index : 0) \ | |
40 | |SM((_series)[_index].ChSel, AR_ChainSel##_index)) | |
41 | ||
42 | #define CCK_SIFS_TIME 10 | |
43 | #define CCK_PREAMBLE_BITS 144 | |
44 | #define CCK_PLCP_BITS 48 | |
45 | ||
46 | #define OFDM_SIFS_TIME 16 | |
47 | #define OFDM_PREAMBLE_TIME 20 | |
48 | #define OFDM_PLCP_BITS 22 | |
49 | #define OFDM_SYMBOL_TIME 4 | |
50 | ||
51 | #define OFDM_SIFS_TIME_HALF 32 | |
52 | #define OFDM_PREAMBLE_TIME_HALF 40 | |
53 | #define OFDM_PLCP_BITS_HALF 22 | |
54 | #define OFDM_SYMBOL_TIME_HALF 8 | |
55 | ||
56 | #define OFDM_SIFS_TIME_QUARTER 64 | |
57 | #define OFDM_PREAMBLE_TIME_QUARTER 80 | |
58 | #define OFDM_PLCP_BITS_QUARTER 22 | |
59 | #define OFDM_SYMBOL_TIME_QUARTER 16 | |
60 | ||
61 | #define INIT_AIFS 2 | |
62 | #define INIT_CWMIN 15 | |
63 | #define INIT_CWMIN_11B 31 | |
64 | #define INIT_CWMAX 1023 | |
65 | #define INIT_SH_RETRY 10 | |
66 | #define INIT_LG_RETRY 10 | |
67 | #define INIT_SSH_RETRY 32 | |
68 | #define INIT_SLG_RETRY 32 | |
69 | ||
70 | #define ATH9K_SLOT_TIME_6 6 | |
71 | #define ATH9K_SLOT_TIME_9 9 | |
72 | #define ATH9K_SLOT_TIME_20 20 | |
73 | ||
74 | #define ATH9K_TXERR_XRETRY 0x01 | |
75 | #define ATH9K_TXERR_FILT 0x02 | |
76 | #define ATH9K_TXERR_FIFO 0x04 | |
77 | #define ATH9K_TXERR_XTXOP 0x08 | |
78 | #define ATH9K_TXERR_TIMER_EXPIRED 0x10 | |
e7824a50 | 79 | #define ATH9K_TX_ACKED 0x20 |
394cf0a1 S |
80 | |
81 | #define ATH9K_TX_BA 0x01 | |
82 | #define ATH9K_TX_PWRMGMT 0x02 | |
83 | #define ATH9K_TX_DESC_CFG_ERR 0x04 | |
84 | #define ATH9K_TX_DATA_UNDERRUN 0x08 | |
85 | #define ATH9K_TX_DELIM_UNDERRUN 0x10 | |
86 | #define ATH9K_TX_SW_ABORTED 0x40 | |
87 | #define ATH9K_TX_SW_FILTERED 0x80 | |
88 | ||
89 | #define MIN_TX_FIFO_THRESHOLD 0x1 | |
90 | #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) | |
91 | #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD | |
92 | ||
93 | struct ath_tx_status { | |
94 | u32 ts_tstamp; | |
95 | u16 ts_seqnum; | |
96 | u8 ts_status; | |
97 | u8 ts_ratecode; | |
98 | u8 ts_rateindex; | |
99 | int8_t ts_rssi; | |
100 | u8 ts_shortretry; | |
101 | u8 ts_longretry; | |
102 | u8 ts_virtcol; | |
103 | u8 ts_antenna; | |
104 | u8 ts_flags; | |
105 | int8_t ts_rssi_ctl0; | |
106 | int8_t ts_rssi_ctl1; | |
107 | int8_t ts_rssi_ctl2; | |
108 | int8_t ts_rssi_ext0; | |
109 | int8_t ts_rssi_ext1; | |
110 | int8_t ts_rssi_ext2; | |
111 | u8 pad[3]; | |
112 | u32 ba_low; | |
113 | u32 ba_high; | |
114 | u32 evm0; | |
115 | u32 evm1; | |
116 | u32 evm2; | |
117 | }; | |
118 | ||
119 | struct ath_rx_status { | |
120 | u32 rs_tstamp; | |
121 | u16 rs_datalen; | |
122 | u8 rs_status; | |
123 | u8 rs_phyerr; | |
124 | int8_t rs_rssi; | |
125 | u8 rs_keyix; | |
126 | u8 rs_rate; | |
127 | u8 rs_antenna; | |
128 | u8 rs_more; | |
129 | int8_t rs_rssi_ctl0; | |
130 | int8_t rs_rssi_ctl1; | |
131 | int8_t rs_rssi_ctl2; | |
132 | int8_t rs_rssi_ext0; | |
133 | int8_t rs_rssi_ext1; | |
134 | int8_t rs_rssi_ext2; | |
135 | u8 rs_isaggr; | |
136 | u8 rs_moreaggr; | |
137 | u8 rs_num_delims; | |
138 | u8 rs_flags; | |
139 | u32 evm0; | |
140 | u32 evm1; | |
141 | u32 evm2; | |
142 | }; | |
143 | ||
144 | #define ATH9K_RXERR_CRC 0x01 | |
145 | #define ATH9K_RXERR_PHY 0x02 | |
146 | #define ATH9K_RXERR_FIFO 0x04 | |
147 | #define ATH9K_RXERR_DECRYPT 0x08 | |
148 | #define ATH9K_RXERR_MIC 0x10 | |
149 | ||
150 | #define ATH9K_RX_MORE 0x01 | |
151 | #define ATH9K_RX_MORE_AGGR 0x02 | |
152 | #define ATH9K_RX_GI 0x04 | |
153 | #define ATH9K_RX_2040 0x08 | |
154 | #define ATH9K_RX_DELIM_CRC_PRE 0x10 | |
155 | #define ATH9K_RX_DELIM_CRC_POST 0x20 | |
156 | #define ATH9K_RX_DECRYPT_BUSY 0x40 | |
157 | ||
158 | #define ATH9K_RXKEYIX_INVALID ((u8)-1) | |
159 | #define ATH9K_TXKEYIX_INVALID ((u32)-1) | |
160 | ||
161 | struct ath_desc { | |
162 | u32 ds_link; | |
163 | u32 ds_data; | |
164 | u32 ds_ctl0; | |
165 | u32 ds_ctl1; | |
166 | u32 ds_hw[20]; | |
167 | union { | |
168 | struct ath_tx_status tx; | |
169 | struct ath_rx_status rx; | |
170 | void *stats; | |
171 | } ds_us; | |
172 | void *ds_vdata; | |
173 | } __packed; | |
174 | ||
175 | #define ds_txstat ds_us.tx | |
176 | #define ds_rxstat ds_us.rx | |
177 | #define ds_stat ds_us.stats | |
178 | ||
179 | #define ATH9K_TXDESC_CLRDMASK 0x0001 | |
180 | #define ATH9K_TXDESC_NOACK 0x0002 | |
181 | #define ATH9K_TXDESC_RTSENA 0x0004 | |
182 | #define ATH9K_TXDESC_CTSENA 0x0008 | |
183 | /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for | |
184 | * the descriptor its marked on. We take a tx interrupt to reap | |
185 | * descriptors when the h/w hits an EOL condition or | |
186 | * when the descriptor is specifically marked to generate | |
187 | * an interrupt with this flag. Descriptors should be | |
188 | * marked periodically to insure timely replenishing of the | |
189 | * supply needed for sending frames. Defering interrupts | |
190 | * reduces system load and potentially allows more concurrent | |
191 | * work to be done but if done to aggressively can cause | |
192 | * senders to backup. When the hardware queue is left too | |
193 | * large rate control information may also be too out of | |
194 | * date. An Alternative for this is TX interrupt mitigation | |
195 | * but this needs more testing. */ | |
196 | #define ATH9K_TXDESC_INTREQ 0x0010 | |
197 | #define ATH9K_TXDESC_VEOL 0x0020 | |
198 | #define ATH9K_TXDESC_EXT_ONLY 0x0040 | |
199 | #define ATH9K_TXDESC_EXT_AND_CTL 0x0080 | |
200 | #define ATH9K_TXDESC_VMF 0x0100 | |
201 | #define ATH9K_TXDESC_FRAG_IS_ON 0x0200 | |
202 | #define ATH9K_TXDESC_CAB 0x0400 | |
203 | ||
204 | #define ATH9K_RXDESC_INTREQ 0x0020 | |
205 | ||
206 | struct ar5416_desc { | |
207 | u32 ds_link; | |
208 | u32 ds_data; | |
209 | u32 ds_ctl0; | |
210 | u32 ds_ctl1; | |
211 | union { | |
212 | struct { | |
213 | u32 ctl2; | |
214 | u32 ctl3; | |
215 | u32 ctl4; | |
216 | u32 ctl5; | |
217 | u32 ctl6; | |
218 | u32 ctl7; | |
219 | u32 ctl8; | |
220 | u32 ctl9; | |
221 | u32 ctl10; | |
222 | u32 ctl11; | |
223 | u32 status0; | |
224 | u32 status1; | |
225 | u32 status2; | |
226 | u32 status3; | |
227 | u32 status4; | |
228 | u32 status5; | |
229 | u32 status6; | |
230 | u32 status7; | |
231 | u32 status8; | |
232 | u32 status9; | |
233 | } tx; | |
234 | struct { | |
235 | u32 status0; | |
236 | u32 status1; | |
237 | u32 status2; | |
238 | u32 status3; | |
239 | u32 status4; | |
240 | u32 status5; | |
241 | u32 status6; | |
242 | u32 status7; | |
243 | u32 status8; | |
244 | } rx; | |
245 | } u; | |
246 | } __packed; | |
247 | ||
248 | #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) | |
249 | #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) | |
250 | ||
251 | #define ds_ctl2 u.tx.ctl2 | |
252 | #define ds_ctl3 u.tx.ctl3 | |
253 | #define ds_ctl4 u.tx.ctl4 | |
254 | #define ds_ctl5 u.tx.ctl5 | |
255 | #define ds_ctl6 u.tx.ctl6 | |
256 | #define ds_ctl7 u.tx.ctl7 | |
257 | #define ds_ctl8 u.tx.ctl8 | |
258 | #define ds_ctl9 u.tx.ctl9 | |
259 | #define ds_ctl10 u.tx.ctl10 | |
260 | #define ds_ctl11 u.tx.ctl11 | |
261 | ||
262 | #define ds_txstatus0 u.tx.status0 | |
263 | #define ds_txstatus1 u.tx.status1 | |
264 | #define ds_txstatus2 u.tx.status2 | |
265 | #define ds_txstatus3 u.tx.status3 | |
266 | #define ds_txstatus4 u.tx.status4 | |
267 | #define ds_txstatus5 u.tx.status5 | |
268 | #define ds_txstatus6 u.tx.status6 | |
269 | #define ds_txstatus7 u.tx.status7 | |
270 | #define ds_txstatus8 u.tx.status8 | |
271 | #define ds_txstatus9 u.tx.status9 | |
272 | ||
273 | #define ds_rxstatus0 u.rx.status0 | |
274 | #define ds_rxstatus1 u.rx.status1 | |
275 | #define ds_rxstatus2 u.rx.status2 | |
276 | #define ds_rxstatus3 u.rx.status3 | |
277 | #define ds_rxstatus4 u.rx.status4 | |
278 | #define ds_rxstatus5 u.rx.status5 | |
279 | #define ds_rxstatus6 u.rx.status6 | |
280 | #define ds_rxstatus7 u.rx.status7 | |
281 | #define ds_rxstatus8 u.rx.status8 | |
282 | ||
283 | #define AR_FrameLen 0x00000fff | |
284 | #define AR_VirtMoreFrag 0x00001000 | |
285 | #define AR_TxCtlRsvd00 0x0000e000 | |
286 | #define AR_XmitPower 0x003f0000 | |
287 | #define AR_XmitPower_S 16 | |
288 | #define AR_RTSEnable 0x00400000 | |
289 | #define AR_VEOL 0x00800000 | |
290 | #define AR_ClrDestMask 0x01000000 | |
291 | #define AR_TxCtlRsvd01 0x1e000000 | |
292 | #define AR_TxIntrReq 0x20000000 | |
293 | #define AR_DestIdxValid 0x40000000 | |
294 | #define AR_CTSEnable 0x80000000 | |
295 | ||
296 | #define AR_BufLen 0x00000fff | |
297 | #define AR_TxMore 0x00001000 | |
298 | #define AR_DestIdx 0x000fe000 | |
299 | #define AR_DestIdx_S 13 | |
300 | #define AR_FrameType 0x00f00000 | |
301 | #define AR_FrameType_S 20 | |
302 | #define AR_NoAck 0x01000000 | |
303 | #define AR_InsertTS 0x02000000 | |
304 | #define AR_CorruptFCS 0x04000000 | |
305 | #define AR_ExtOnly 0x08000000 | |
306 | #define AR_ExtAndCtl 0x10000000 | |
307 | #define AR_MoreAggr 0x20000000 | |
308 | #define AR_IsAggr 0x40000000 | |
309 | ||
310 | #define AR_BurstDur 0x00007fff | |
311 | #define AR_BurstDur_S 0 | |
312 | #define AR_DurUpdateEna 0x00008000 | |
313 | #define AR_XmitDataTries0 0x000f0000 | |
314 | #define AR_XmitDataTries0_S 16 | |
315 | #define AR_XmitDataTries1 0x00f00000 | |
316 | #define AR_XmitDataTries1_S 20 | |
317 | #define AR_XmitDataTries2 0x0f000000 | |
318 | #define AR_XmitDataTries2_S 24 | |
319 | #define AR_XmitDataTries3 0xf0000000 | |
320 | #define AR_XmitDataTries3_S 28 | |
321 | ||
322 | #define AR_XmitRate0 0x000000ff | |
323 | #define AR_XmitRate0_S 0 | |
324 | #define AR_XmitRate1 0x0000ff00 | |
325 | #define AR_XmitRate1_S 8 | |
326 | #define AR_XmitRate2 0x00ff0000 | |
327 | #define AR_XmitRate2_S 16 | |
328 | #define AR_XmitRate3 0xff000000 | |
329 | #define AR_XmitRate3_S 24 | |
330 | ||
331 | #define AR_PacketDur0 0x00007fff | |
332 | #define AR_PacketDur0_S 0 | |
333 | #define AR_RTSCTSQual0 0x00008000 | |
334 | #define AR_PacketDur1 0x7fff0000 | |
335 | #define AR_PacketDur1_S 16 | |
336 | #define AR_RTSCTSQual1 0x80000000 | |
337 | ||
338 | #define AR_PacketDur2 0x00007fff | |
339 | #define AR_PacketDur2_S 0 | |
340 | #define AR_RTSCTSQual2 0x00008000 | |
341 | #define AR_PacketDur3 0x7fff0000 | |
342 | #define AR_PacketDur3_S 16 | |
343 | #define AR_RTSCTSQual3 0x80000000 | |
344 | ||
345 | #define AR_AggrLen 0x0000ffff | |
346 | #define AR_AggrLen_S 0 | |
347 | #define AR_TxCtlRsvd60 0x00030000 | |
348 | #define AR_PadDelim 0x03fc0000 | |
349 | #define AR_PadDelim_S 18 | |
350 | #define AR_EncrType 0x0c000000 | |
351 | #define AR_EncrType_S 26 | |
352 | #define AR_TxCtlRsvd61 0xf0000000 | |
353 | ||
354 | #define AR_2040_0 0x00000001 | |
355 | #define AR_GI0 0x00000002 | |
356 | #define AR_ChainSel0 0x0000001c | |
357 | #define AR_ChainSel0_S 2 | |
358 | #define AR_2040_1 0x00000020 | |
359 | #define AR_GI1 0x00000040 | |
360 | #define AR_ChainSel1 0x00000380 | |
361 | #define AR_ChainSel1_S 7 | |
362 | #define AR_2040_2 0x00000400 | |
363 | #define AR_GI2 0x00000800 | |
364 | #define AR_ChainSel2 0x00007000 | |
365 | #define AR_ChainSel2_S 12 | |
366 | #define AR_2040_3 0x00008000 | |
367 | #define AR_GI3 0x00010000 | |
368 | #define AR_ChainSel3 0x000e0000 | |
369 | #define AR_ChainSel3_S 17 | |
370 | #define AR_RTSCTSRate 0x0ff00000 | |
371 | #define AR_RTSCTSRate_S 20 | |
372 | #define AR_TxCtlRsvd70 0xf0000000 | |
373 | ||
374 | #define AR_TxRSSIAnt00 0x000000ff | |
375 | #define AR_TxRSSIAnt00_S 0 | |
376 | #define AR_TxRSSIAnt01 0x0000ff00 | |
377 | #define AR_TxRSSIAnt01_S 8 | |
378 | #define AR_TxRSSIAnt02 0x00ff0000 | |
379 | #define AR_TxRSSIAnt02_S 16 | |
380 | #define AR_TxStatusRsvd00 0x3f000000 | |
381 | #define AR_TxBaStatus 0x40000000 | |
382 | #define AR_TxStatusRsvd01 0x80000000 | |
383 | ||
e7824a50 LR |
384 | /* |
385 | * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was | |
386 | * transmitted successfully. If clear, no ACK or BA was received to indicate | |
387 | * successful transmission when we were expecting an ACK or BA. | |
388 | */ | |
394cf0a1 S |
389 | #define AR_FrmXmitOK 0x00000001 |
390 | #define AR_ExcessiveRetries 0x00000002 | |
391 | #define AR_FIFOUnderrun 0x00000004 | |
392 | #define AR_Filtered 0x00000008 | |
393 | #define AR_RTSFailCnt 0x000000f0 | |
394 | #define AR_RTSFailCnt_S 4 | |
395 | #define AR_DataFailCnt 0x00000f00 | |
396 | #define AR_DataFailCnt_S 8 | |
397 | #define AR_VirtRetryCnt 0x0000f000 | |
398 | #define AR_VirtRetryCnt_S 12 | |
399 | #define AR_TxDelimUnderrun 0x00010000 | |
400 | #define AR_TxDataUnderrun 0x00020000 | |
401 | #define AR_DescCfgErr 0x00040000 | |
402 | #define AR_TxTimerExpired 0x00080000 | |
403 | #define AR_TxStatusRsvd10 0xfff00000 | |
404 | ||
405 | #define AR_SendTimestamp ds_txstatus2 | |
406 | #define AR_BaBitmapLow ds_txstatus3 | |
407 | #define AR_BaBitmapHigh ds_txstatus4 | |
408 | ||
409 | #define AR_TxRSSIAnt10 0x000000ff | |
410 | #define AR_TxRSSIAnt10_S 0 | |
411 | #define AR_TxRSSIAnt11 0x0000ff00 | |
412 | #define AR_TxRSSIAnt11_S 8 | |
413 | #define AR_TxRSSIAnt12 0x00ff0000 | |
414 | #define AR_TxRSSIAnt12_S 16 | |
415 | #define AR_TxRSSICombined 0xff000000 | |
416 | #define AR_TxRSSICombined_S 24 | |
417 | ||
418 | #define AR_TxEVM0 ds_txstatus5 | |
419 | #define AR_TxEVM1 ds_txstatus6 | |
420 | #define AR_TxEVM2 ds_txstatus7 | |
421 | ||
422 | #define AR_TxDone 0x00000001 | |
423 | #define AR_SeqNum 0x00001ffe | |
424 | #define AR_SeqNum_S 1 | |
425 | #define AR_TxStatusRsvd80 0x0001e000 | |
426 | #define AR_TxOpExceeded 0x00020000 | |
427 | #define AR_TxStatusRsvd81 0x001c0000 | |
428 | #define AR_FinalTxIdx 0x00600000 | |
429 | #define AR_FinalTxIdx_S 21 | |
430 | #define AR_TxStatusRsvd82 0x01800000 | |
431 | #define AR_PowerMgmt 0x02000000 | |
432 | #define AR_TxStatusRsvd83 0xfc000000 | |
433 | ||
434 | #define AR_RxCTLRsvd00 0xffffffff | |
435 | ||
436 | #define AR_BufLen 0x00000fff | |
437 | #define AR_RxCtlRsvd00 0x00001000 | |
438 | #define AR_RxIntrReq 0x00002000 | |
439 | #define AR_RxCtlRsvd01 0xffffc000 | |
440 | ||
441 | #define AR_RxRSSIAnt00 0x000000ff | |
442 | #define AR_RxRSSIAnt00_S 0 | |
443 | #define AR_RxRSSIAnt01 0x0000ff00 | |
444 | #define AR_RxRSSIAnt01_S 8 | |
445 | #define AR_RxRSSIAnt02 0x00ff0000 | |
446 | #define AR_RxRSSIAnt02_S 16 | |
447 | #define AR_RxRate 0xff000000 | |
448 | #define AR_RxRate_S 24 | |
449 | #define AR_RxStatusRsvd00 0xff000000 | |
450 | ||
451 | #define AR_DataLen 0x00000fff | |
452 | #define AR_RxMore 0x00001000 | |
453 | #define AR_NumDelim 0x003fc000 | |
454 | #define AR_NumDelim_S 14 | |
455 | #define AR_RxStatusRsvd10 0xff800000 | |
456 | ||
457 | #define AR_RcvTimestamp ds_rxstatus2 | |
458 | ||
459 | #define AR_GI 0x00000001 | |
460 | #define AR_2040 0x00000002 | |
461 | #define AR_Parallel40 0x00000004 | |
462 | #define AR_Parallel40_S 2 | |
463 | #define AR_RxStatusRsvd30 0x000000f8 | |
464 | #define AR_RxAntenna 0xffffff00 | |
465 | #define AR_RxAntenna_S 8 | |
466 | ||
467 | #define AR_RxRSSIAnt10 0x000000ff | |
468 | #define AR_RxRSSIAnt10_S 0 | |
469 | #define AR_RxRSSIAnt11 0x0000ff00 | |
470 | #define AR_RxRSSIAnt11_S 8 | |
471 | #define AR_RxRSSIAnt12 0x00ff0000 | |
472 | #define AR_RxRSSIAnt12_S 16 | |
473 | #define AR_RxRSSICombined 0xff000000 | |
474 | #define AR_RxRSSICombined_S 24 | |
475 | ||
476 | #define AR_RxEVM0 ds_rxstatus4 | |
477 | #define AR_RxEVM1 ds_rxstatus5 | |
478 | #define AR_RxEVM2 ds_rxstatus6 | |
479 | ||
480 | #define AR_RxDone 0x00000001 | |
481 | #define AR_RxFrameOK 0x00000002 | |
482 | #define AR_CRCErr 0x00000004 | |
483 | #define AR_DecryptCRCErr 0x00000008 | |
484 | #define AR_PHYErr 0x00000010 | |
485 | #define AR_MichaelErr 0x00000020 | |
486 | #define AR_PreDelimCRCErr 0x00000040 | |
487 | #define AR_RxStatusRsvd70 0x00000080 | |
488 | #define AR_RxKeyIdxValid 0x00000100 | |
489 | #define AR_KeyIdx 0x0000fe00 | |
490 | #define AR_KeyIdx_S 9 | |
491 | #define AR_PHYErrCode 0x0000ff00 | |
492 | #define AR_PHYErrCode_S 8 | |
493 | #define AR_RxMoreAggr 0x00010000 | |
494 | #define AR_RxAggr 0x00020000 | |
495 | #define AR_PostDelimCRCErr 0x00040000 | |
496 | #define AR_RxStatusRsvd71 0x3ff80000 | |
497 | #define AR_DecryptBusyErr 0x40000000 | |
498 | #define AR_KeyMiss 0x80000000 | |
499 | ||
500 | enum ath9k_tx_queue { | |
501 | ATH9K_TX_QUEUE_INACTIVE = 0, | |
502 | ATH9K_TX_QUEUE_DATA, | |
503 | ATH9K_TX_QUEUE_BEACON, | |
504 | ATH9K_TX_QUEUE_CAB, | |
505 | ATH9K_TX_QUEUE_UAPSD, | |
506 | ATH9K_TX_QUEUE_PSPOLL | |
507 | }; | |
508 | ||
509 | #define ATH9K_NUM_TX_QUEUES 10 | |
510 | ||
511 | enum ath9k_tx_queue_subtype { | |
512 | ATH9K_WME_AC_BK = 0, | |
513 | ATH9K_WME_AC_BE, | |
514 | ATH9K_WME_AC_VI, | |
515 | ATH9K_WME_AC_VO, | |
516 | ATH9K_WME_UPSD | |
517 | }; | |
518 | ||
519 | enum ath9k_tx_queue_flags { | |
520 | TXQ_FLAG_TXOKINT_ENABLE = 0x0001, | |
521 | TXQ_FLAG_TXERRINT_ENABLE = 0x0001, | |
522 | TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, | |
523 | TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, | |
524 | TXQ_FLAG_TXURNINT_ENABLE = 0x0008, | |
525 | TXQ_FLAG_BACKOFF_DISABLE = 0x0010, | |
526 | TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, | |
527 | TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, | |
528 | TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, | |
529 | }; | |
530 | ||
531 | #define ATH9K_TXQ_USEDEFAULT ((u32) -1) | |
532 | #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 | |
533 | ||
534 | #define ATH9K_DECOMP_MASK_SIZE 128 | |
535 | #define ATH9K_READY_TIME_LO_BOUND 50 | |
536 | #define ATH9K_READY_TIME_HI_BOUND 96 | |
537 | ||
538 | enum ath9k_pkt_type { | |
539 | ATH9K_PKT_TYPE_NORMAL = 0, | |
540 | ATH9K_PKT_TYPE_ATIM, | |
541 | ATH9K_PKT_TYPE_PSPOLL, | |
542 | ATH9K_PKT_TYPE_BEACON, | |
543 | ATH9K_PKT_TYPE_PROBE_RESP, | |
544 | ATH9K_PKT_TYPE_CHIRP, | |
545 | ATH9K_PKT_TYPE_GRP_POLL, | |
546 | }; | |
547 | ||
548 | struct ath9k_tx_queue_info { | |
549 | u32 tqi_ver; | |
550 | enum ath9k_tx_queue tqi_type; | |
551 | enum ath9k_tx_queue_subtype tqi_subtype; | |
552 | enum ath9k_tx_queue_flags tqi_qflags; | |
553 | u32 tqi_priority; | |
554 | u32 tqi_aifs; | |
555 | u32 tqi_cwmin; | |
556 | u32 tqi_cwmax; | |
557 | u16 tqi_shretry; | |
558 | u16 tqi_lgretry; | |
559 | u32 tqi_cbrPeriod; | |
560 | u32 tqi_cbrOverflowLimit; | |
561 | u32 tqi_burstTime; | |
562 | u32 tqi_readyTime; | |
563 | u32 tqi_physCompBuf; | |
564 | u32 tqi_intFlags; | |
565 | }; | |
566 | ||
567 | enum ath9k_rx_filter { | |
568 | ATH9K_RX_FILTER_UCAST = 0x00000001, | |
569 | ATH9K_RX_FILTER_MCAST = 0x00000002, | |
570 | ATH9K_RX_FILTER_BCAST = 0x00000004, | |
571 | ATH9K_RX_FILTER_CONTROL = 0x00000008, | |
572 | ATH9K_RX_FILTER_BEACON = 0x00000010, | |
573 | ATH9K_RX_FILTER_PROM = 0x00000020, | |
574 | ATH9K_RX_FILTER_PROBEREQ = 0x00000080, | |
394cf0a1 | 575 | ATH9K_RX_FILTER_PHYERR = 0x00000100, |
dbaaa147 | 576 | ATH9K_RX_FILTER_MYBEACON = 0x00000200, |
7ea310be | 577 | ATH9K_RX_FILTER_COMP_BAR = 0x00000400, |
dbaaa147 | 578 | ATH9K_RX_FILTER_PSPOLL = 0x00004000, |
394cf0a1 | 579 | ATH9K_RX_FILTER_PHYRADAR = 0x00002000, |
b93bce2a | 580 | ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, |
394cf0a1 S |
581 | }; |
582 | ||
583 | #define ATH9K_RATESERIES_RTS_CTS 0x0001 | |
584 | #define ATH9K_RATESERIES_2040 0x0002 | |
585 | #define ATH9K_RATESERIES_HALFGI 0x0004 | |
586 | ||
587 | struct ath9k_11n_rate_series { | |
588 | u32 Tries; | |
589 | u32 Rate; | |
590 | u32 PktDuration; | |
591 | u32 ChSel; | |
592 | u32 RateFlags; | |
593 | }; | |
594 | ||
595 | struct ath9k_keyval { | |
596 | u8 kv_type; | |
597 | u8 kv_pad; | |
598 | u16 kv_len; | |
672903b3 JM |
599 | u8 kv_val[16]; /* TK */ |
600 | u8 kv_mic[8]; /* Michael MIC key */ | |
601 | u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware | |
602 | * supports both MIC keys in the same key cache entry; | |
603 | * in that case, kv_mic is the RX key) */ | |
394cf0a1 S |
604 | }; |
605 | ||
606 | enum ath9k_key_type { | |
607 | ATH9K_KEY_TYPE_CLEAR, | |
608 | ATH9K_KEY_TYPE_WEP, | |
609 | ATH9K_KEY_TYPE_AES, | |
610 | ATH9K_KEY_TYPE_TKIP, | |
611 | }; | |
612 | ||
613 | enum ath9k_cipher { | |
614 | ATH9K_CIPHER_WEP = 0, | |
615 | ATH9K_CIPHER_AES_OCB = 1, | |
616 | ATH9K_CIPHER_AES_CCM = 2, | |
617 | ATH9K_CIPHER_CKIP = 3, | |
618 | ATH9K_CIPHER_TKIP = 4, | |
619 | ATH9K_CIPHER_CLR = 5, | |
620 | ATH9K_CIPHER_MIC = 127 | |
621 | }; | |
622 | ||
cbe61d8a | 623 | struct ath_hw; |
394cf0a1 | 624 | struct ath9k_channel; |
394cf0a1 | 625 | |
cbe61d8a | 626 | u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); |
54e4cec6 S |
627 | void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); |
628 | void ath9k_hw_txstart(struct ath_hw *ah, u32 q); | |
cbe61d8a S |
629 | u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); |
630 | bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); | |
631 | bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q); | |
54e4cec6 | 632 | void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds, |
394cf0a1 S |
633 | u32 segLen, bool firstSeg, |
634 | bool lastSeg, const struct ath_desc *ds0); | |
cbe61d8a S |
635 | void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds); |
636 | int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds); | |
637 | void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds, | |
394cf0a1 S |
638 | u32 pktLen, enum ath9k_pkt_type type, u32 txPower, |
639 | u32 keyIx, enum ath9k_key_type keyType, u32 flags); | |
cbe61d8a | 640 | void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds, |
394cf0a1 S |
641 | struct ath_desc *lastds, |
642 | u32 durUpdateEn, u32 rtsctsRate, | |
643 | u32 rtsctsDuration, | |
644 | struct ath9k_11n_rate_series series[], | |
645 | u32 nseries, u32 flags); | |
cbe61d8a | 646 | void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds, |
394cf0a1 | 647 | u32 aggrLen); |
cbe61d8a | 648 | void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds, |
394cf0a1 | 649 | u32 numDelims); |
cbe61d8a S |
650 | void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds); |
651 | void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds); | |
652 | void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds, | |
394cf0a1 | 653 | u32 burstDuration); |
cbe61d8a | 654 | void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds, |
394cf0a1 | 655 | u32 vmf); |
cbe61d8a S |
656 | void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs); |
657 | bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, | |
394cf0a1 | 658 | const struct ath9k_tx_queue_info *qinfo); |
cbe61d8a | 659 | bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, |
394cf0a1 | 660 | struct ath9k_tx_queue_info *qinfo); |
cbe61d8a | 661 | int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, |
394cf0a1 | 662 | const struct ath9k_tx_queue_info *qinfo); |
cbe61d8a S |
663 | bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q); |
664 | bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q); | |
665 | int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, | |
394cf0a1 | 666 | u32 pa, struct ath_desc *nds, u64 tsf); |
54e4cec6 | 667 | void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, |
394cf0a1 | 668 | u32 size, u32 flags); |
cbe61d8a S |
669 | bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set); |
670 | void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); | |
671 | void ath9k_hw_rxena(struct ath_hw *ah); | |
672 | void ath9k_hw_startpcureceive(struct ath_hw *ah); | |
673 | void ath9k_hw_stoppcurecv(struct ath_hw *ah); | |
674 | bool ath9k_hw_stopdmarecv(struct ath_hw *ah); | |
536b3a7a | 675 | int ath9k_hw_beaconq_setup(struct ath_hw *ah); |
394cf0a1 S |
676 | |
677 | #endif /* MAC_H */ |