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ath9k_hw: allow for spliting up ANI operations by family
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / mac.c
CommitLineData
f1dc5600 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f1dc5600
S		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
990b70ab 17#include "hw.h"
ac0bb767 18#include "hw-ops.h"
f1dc5600 19
cc610ac0
VT		 20static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
21 struct ath9k_tx_queue_info *qi)
22{
23 ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
24 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
25 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
26 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
27 ah->txurn_interrupt_mask);
28
7d0d0df0
S		 29 ENABLE_REGWRITE_BUFFER(ah);
30
cc610ac0
VT		 31 REG_WRITE(ah, AR_IMR_S0,
32 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
33 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
34 REG_WRITE(ah, AR_IMR_S1,
35 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
36 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
37
38 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
39 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
40 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
7d0d0df0
S		 41
42 REGWRITE_BUFFER_FLUSH(ah);
43 DISABLE_REGWRITE_BUFFER(ah);
cc610ac0
VT		 44}
45
46u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
47{
48 return REG_READ(ah, AR_QTXDP(q));
49}
50EXPORT_SYMBOL(ath9k_hw_gettxbuf);
51
52void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
53{
54 REG_WRITE(ah, AR_QTXDP(q), txdp);
55}
56EXPORT_SYMBOL(ath9k_hw_puttxbuf);
57
58void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
59{
60 ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
61 "Enable TXE on queue: %u\n", q);
62 REG_WRITE(ah, AR_Q_TXE, 1 << q);
63}
64EXPORT_SYMBOL(ath9k_hw_txstart);
65
66void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
67{
68 struct ar5416_desc *ads = AR5416DESC(ds);
69
70 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
71 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
72 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
73 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
74 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
75}
76EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
77
78u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
79{
80 u32 npend;
81
82 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
83 if (npend == 0) {
84
85 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
86 npend = 1;
87 }
88
89 return npend;
90}
91EXPORT_SYMBOL(ath9k_hw_numtxpending);
92
93/**
94 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
95 *
96 * @ah: atheros hardware struct
97 * @bIncTrigLevel: whether or not the frame trigger level should be updated
98 *
99 * The frame trigger level specifies the minimum number of bytes,
100 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
101 * before the PCU will initiate sending the frame on the air. This can
102 * mean we initiate transmit before a full frame is on the PCU TX FIFO.
103 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
104 * first)
105 *
106 * Caution must be taken to ensure to set the frame trigger level based
107 * on the DMA request size. For example if the DMA request size is set to
108 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
109 * there need to be enough space in the tx FIFO for the requested transfer
110 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
111 * the threshold to a value beyond 6, then the transmit will hang.
112 *
113 * Current dual stream devices have a PCU TX FIFO size of 8 KB.
114 * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
115 * there is a hardware issue which forces us to use 2 KB instead so the
116 * frame trigger level must not exceed 2 KB for these chipsets.
117 */
118bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
119{
120 u32 txcfg, curLevel, newLevel;
121 enum ath9k_int omask;
122
123 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
124 return false;
125
126 omask = ath9k_hw_set_interrupts(ah, ah->imask & ~ATH9K_INT_GLOBAL);
127
128 txcfg = REG_READ(ah, AR_TXCFG);
129 curLevel = MS(txcfg, AR_FTRIG);
130 newLevel = curLevel;
131 if (bIncTrigLevel) {
132 if (curLevel < ah->config.max_txtrig_level)
133 newLevel++;
134 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
135 newLevel--;
136 if (newLevel != curLevel)
137 REG_WRITE(ah, AR_TXCFG,
138 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
139
140 ath9k_hw_set_interrupts(ah, omask);
141
142 ah->tx_trig_level = newLevel;
143
144 return newLevel != curLevel;
145}
146EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
147
148bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
149{
150#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
151#define ATH9K_TIME_QUANTUM 100 /* usec */
152 struct ath_common *common = ath9k_hw_common(ah);
153 struct ath9k_hw_capabilities *pCap = &ah->caps;
154 struct ath9k_tx_queue_info *qi;
155 u32 tsfLow, j, wait;
156 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
157
158 if (q >= pCap->total_queues) {
159 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
160 "invalid queue: %u\n", q);
161 return false;
162 }
163
164 qi = &ah->txq[q];
165 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
166 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
167 "inactive queue: %u\n", q);
168 return false;
169 }
170
171 REG_WRITE(ah, AR_Q_TXD, 1 << q);
172
173 for (wait = wait_time; wait != 0; wait--) {
174 if (ath9k_hw_numtxpending(ah, q) == 0)
175 break;
176 udelay(ATH9K_TIME_QUANTUM);
177 }
178
179 if (ath9k_hw_numtxpending(ah, q)) {
180 ath_print(common, ATH_DBG_QUEUE,
181 "%s: Num of pending TX Frames %d on Q %d\n",
182 __func__, ath9k_hw_numtxpending(ah, q), q);
183
184 for (j = 0; j < 2; j++) {
185 tsfLow = REG_READ(ah, AR_TSF_L32);
186 REG_WRITE(ah, AR_QUIET2,
187 SM(10, AR_QUIET2_QUIET_DUR));
188 REG_WRITE(ah, AR_QUIET_PERIOD, 100);
189 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
190 REG_SET_BIT(ah, AR_TIMER_MODE,
191 AR_QUIET_TIMER_EN);
192
193 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
194 break;
195
196 ath_print(common, ATH_DBG_QUEUE,
197 "TSF has moved while trying to set "
198 "quiet time TSF: 0x%08x\n", tsfLow);
199 }
200
201 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
202
203 udelay(200);
204 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
205
206 wait = wait_time;
207 while (ath9k_hw_numtxpending(ah, q)) {
208 if ((--wait) == 0) {
209 ath_print(common, ATH_DBG_FATAL,
210 "Failed to stop TX DMA in 100 "
211 "msec after killing last frame\n");
212 break;
213 }
214 udelay(ATH9K_TIME_QUANTUM);
215 }
216
217 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
218 }
219
220 REG_WRITE(ah, AR_Q_TXD, 0);
221 return wait != 0;
222
223#undef ATH9K_TX_STOP_DMA_TIMEOUT
224#undef ATH9K_TIME_QUANTUM
225}
226EXPORT_SYMBOL(ath9k_hw_stoptxdma);
227
cbe61d8a 228void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
f1dc5600 229{
2660b81a
S		 230 *txqs &= ah->intr_txqs;
231 ah->intr_txqs &= ~(*txqs);
f1dc5600 232}
7322fd19 233EXPORT_SYMBOL(ath9k_hw_gettxintrtxqs);
f1dc5600 234
cbe61d8a 235bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
f1dc5600
S		 236 const struct ath9k_tx_queue_info *qinfo)
237{
238 u32 cw;
c46917bb 239 struct ath_common *common = ath9k_hw_common(ah);
2660b81a 240 struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600
S		 241 struct ath9k_tx_queue_info *qi;
242
243 if (q >= pCap->total_queues) {
c46917bb
LR		 244 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
245 "invalid queue: %u\n", q);
f1dc5600
S		 246 return false;
247 }
248
2660b81a 249 qi = &ah->txq[q];
f1dc5600 250 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
c46917bb
LR		 251 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
252 "inactive queue: %u\n", q);
f1dc5600
S		 253 return false;
254 }
255
c46917bb 256 ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
f1dc5600
S		 257
258 qi->tqi_ver = qinfo->tqi_ver;
259 qi->tqi_subtype = qinfo->tqi_subtype;
260 qi->tqi_qflags = qinfo->tqi_qflags;
261 qi->tqi_priority = qinfo->tqi_priority;
262 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
263 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
264 else
265 qi->tqi_aifs = INIT_AIFS;
266 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
267 cw = min(qinfo->tqi_cwmin, 1024U);
268 qi->tqi_cwmin = 1;
269 while (qi->tqi_cwmin < cw)
270 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
271 } else
272 qi->tqi_cwmin = qinfo->tqi_cwmin;
273 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
274 cw = min(qinfo->tqi_cwmax, 1024U);
275 qi->tqi_cwmax = 1;
276 while (qi->tqi_cwmax < cw)
277 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
278 } else
279 qi->tqi_cwmax = INIT_CWMAX;
280
281 if (qinfo->tqi_shretry != 0)
282 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
283 else
284 qi->tqi_shretry = INIT_SH_RETRY;
285 if (qinfo->tqi_lgretry != 0)
286 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
287 else
288 qi->tqi_lgretry = INIT_LG_RETRY;
289 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
290 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
291 qi->tqi_burstTime = qinfo->tqi_burstTime;
292 qi->tqi_readyTime = qinfo->tqi_readyTime;
293
294 switch (qinfo->tqi_subtype) {
295 case ATH9K_WME_UPSD:
296 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
297 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
298 break;
299 default:
300 break;
301 }
302
303 return true;
304}
7322fd19 305EXPORT_SYMBOL(ath9k_hw_set_txq_props);
f1dc5600 306
cbe61d8a 307bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
f1dc5600
S		 308 struct ath9k_tx_queue_info *qinfo)
309{
c46917bb 310 struct ath_common *common = ath9k_hw_common(ah);
2660b81a 311 struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600
S		 312 struct ath9k_tx_queue_info *qi;
313
314 if (q >= pCap->total_queues) {
c46917bb
LR		 315 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
316 "invalid queue: %u\n", q);
f1dc5600
S		 317 return false;
318 }
319
2660b81a 320 qi = &ah->txq[q];
f1dc5600 321 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
c46917bb
LR		 322 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
323 "inactive queue: %u\n", q);
f1dc5600
S		 324 return false;
325 }
326
327 qinfo->tqi_qflags = qi->tqi_qflags;
328 qinfo->tqi_ver = qi->tqi_ver;
329 qinfo->tqi_subtype = qi->tqi_subtype;
330 qinfo->tqi_qflags = qi->tqi_qflags;
331 qinfo->tqi_priority = qi->tqi_priority;
332 qinfo->tqi_aifs = qi->tqi_aifs;
333 qinfo->tqi_cwmin = qi->tqi_cwmin;
334 qinfo->tqi_cwmax = qi->tqi_cwmax;
335 qinfo->tqi_shretry = qi->tqi_shretry;
336 qinfo->tqi_lgretry = qi->tqi_lgretry;
337 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
338 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
339 qinfo->tqi_burstTime = qi->tqi_burstTime;
340 qinfo->tqi_readyTime = qi->tqi_readyTime;
341
342 return true;
343}
7322fd19 344EXPORT_SYMBOL(ath9k_hw_get_txq_props);
f1dc5600 345
cbe61d8a 346int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
f1dc5600
S		 347 const struct ath9k_tx_queue_info *qinfo)
348{
c46917bb 349 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 350 struct ath9k_tx_queue_info *qi;
2660b81a 351 struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600
S		 352 int q;
353
354 switch (type) {
355 case ATH9K_TX_QUEUE_BEACON:
356 q = pCap->total_queues - 1;
357 break;
358 case ATH9K_TX_QUEUE_CAB:
359 q = pCap->total_queues - 2;
360 break;
361 case ATH9K_TX_QUEUE_PSPOLL:
362 q = 1;
363 break;
364 case ATH9K_TX_QUEUE_UAPSD:
365 q = pCap->total_queues - 3;
366 break;
367 case ATH9K_TX_QUEUE_DATA:
368 for (q = 0; q < pCap->total_queues; q++)
2660b81a 369 if (ah->txq[q].tqi_type ==
f1dc5600
S		 370 ATH9K_TX_QUEUE_INACTIVE)
371 break;
372 if (q == pCap->total_queues) {
c46917bb
LR		 373 ath_print(common, ATH_DBG_FATAL,
374 "No available TX queue\n");
f1dc5600
S		 375 return -1;
376 }
377 break;
378 default:
c46917bb
LR		 379 ath_print(common, ATH_DBG_FATAL,
380 "Invalid TX queue type: %u\n", type);
f1dc5600
S		 381 return -1;
382 }
383
c46917bb 384 ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
f1dc5600 385
2660b81a 386 qi = &ah->txq[q];
f1dc5600 387 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
c46917bb
LR		 388 ath_print(common, ATH_DBG_FATAL,
389 "TX queue: %u already active\n", q);
f1dc5600
S		 390 return -1;
391 }
392 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
393 qi->tqi_type = type;
394 if (qinfo == NULL) {
395 qi->tqi_qflags =
396 TXQ_FLAG_TXOKINT_ENABLE
397 | TXQ_FLAG_TXERRINT_ENABLE
398 | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
399 qi->tqi_aifs = INIT_AIFS;
400 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
401 qi->tqi_cwmax = INIT_CWMAX;
402 qi->tqi_shretry = INIT_SH_RETRY;
403 qi->tqi_lgretry = INIT_LG_RETRY;
404 qi->tqi_physCompBuf = 0;
405 } else {
406 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
407 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
408 }
409
410 return q;
411}
7322fd19 412EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
f1dc5600 413
cbe61d8a 414bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
f1dc5600 415{
2660b81a 416 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 417 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 418 struct ath9k_tx_queue_info *qi;
419
420 if (q >= pCap->total_queues) {
c46917bb
LR		 421 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
422 "invalid queue: %u\n", q);
f1dc5600
S		 423 return false;
424 }
2660b81a 425 qi = &ah->txq[q];
f1dc5600 426 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
c46917bb
LR		 427 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
428 "inactive queue: %u\n", q);
f1dc5600
S		 429 return false;
430 }
431
c46917bb 432 ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
f1dc5600
S		 433
434 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
2660b81a
S		 435 ah->txok_interrupt_mask &= ~(1 << q);
436 ah->txerr_interrupt_mask &= ~(1 << q);
437 ah->txdesc_interrupt_mask &= ~(1 << q);
438 ah->txeol_interrupt_mask &= ~(1 << q);
439 ah->txurn_interrupt_mask &= ~(1 << q);
f1dc5600
S		 440 ath9k_hw_set_txq_interrupts(ah, qi);
441
442 return true;
443}
7322fd19 444EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
f1dc5600 445
cbe61d8a 446bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
f1dc5600 447{
2660b81a 448 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 449 struct ath_common *common = ath9k_hw_common(ah);
2660b81a 450 struct ath9k_channel *chan = ah->curchan;
f1dc5600
S		 451 struct ath9k_tx_queue_info *qi;
452 u32 cwMin, chanCwMin, value;
453
454 if (q >= pCap->total_queues) {
c46917bb
LR		 455 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
456 "invalid queue: %u\n", q);
f1dc5600
S		 457 return false;
458 }
459
2660b81a 460 qi = &ah->txq[q];
f1dc5600 461 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
c46917bb
LR		 462 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
463 "inactive queue: %u\n", q);
f1dc5600
S		 464 return true;
465 }
466
c46917bb 467 ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
f1dc5600
S		 468
469 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
470 if (chan && IS_CHAN_B(chan))
471 chanCwMin = INIT_CWMIN_11B;
472 else
473 chanCwMin = INIT_CWMIN;
474
475 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
476 } else
477 cwMin = qi->tqi_cwmin;
478
7d0d0df0
S		 479 ENABLE_REGWRITE_BUFFER(ah);
480
f1dc5600
S		 481 REG_WRITE(ah, AR_DLCL_IFS(q),
482 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
483 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
484 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
485
486 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
487 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
488 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
489 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
490
491 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
492 REG_WRITE(ah, AR_DMISC(q),
493 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
494
7d0d0df0
S		 495 REGWRITE_BUFFER_FLUSH(ah);
496
f1dc5600
S		 497 if (qi->tqi_cbrPeriod) {
498 REG_WRITE(ah, AR_QCBRCFG(q),
499 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
500 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
501 REG_WRITE(ah, AR_QMISC(q),
502 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
503 (qi->tqi_cbrOverflowLimit ?
504 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
505 }
506 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
507 REG_WRITE(ah, AR_QRDYTIMECFG(q),
508 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
509 AR_Q_RDYTIMECFG_EN);
510 }
511
7d0d0df0
S		 512 REGWRITE_BUFFER_FLUSH(ah);
513
f1dc5600
S		 514 REG_WRITE(ah, AR_DCHNTIME(q),
515 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
516 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
517
518 if (qi->tqi_burstTime
519 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
520 REG_WRITE(ah, AR_QMISC(q),
521 REG_READ(ah, AR_QMISC(q)) |
522 AR_Q_MISC_RDYTIME_EXP_POLICY);
523
524 }
525
526 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
527 REG_WRITE(ah, AR_DMISC(q),
528 REG_READ(ah, AR_DMISC(q)) |
529 AR_D_MISC_POST_FR_BKOFF_DIS);
530 }
7d0d0df0
S		 531
532 REGWRITE_BUFFER_FLUSH(ah);
533 DISABLE_REGWRITE_BUFFER(ah);
534
f1dc5600
S		 535 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
536 REG_WRITE(ah, AR_DMISC(q),
537 REG_READ(ah, AR_DMISC(q)) |
538 AR_D_MISC_FRAG_BKOFF_EN);
539 }
540 switch (qi->tqi_type) {
541 case ATH9K_TX_QUEUE_BEACON:
7d0d0df0
S		 542 ENABLE_REGWRITE_BUFFER(ah);
543
f1dc5600
S		 544 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
545 | AR_Q_MISC_FSP_DBA_GATED
546 | AR_Q_MISC_BEACON_USE
547 | AR_Q_MISC_CBR_INCR_DIS1);
548
549 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
550 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
551 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
552 | AR_D_MISC_BEACON_USE
553 | AR_D_MISC_POST_FR_BKOFF_DIS);
7d0d0df0
S		 554
555 REGWRITE_BUFFER_FLUSH(ah);
556 DISABLE_REGWRITE_BUFFER(ah);
557
3deb4da5
LR		 558 /* cwmin and cwmax should be 0 for beacon queue */
559 if (AR_SREV_9300_20_OR_LATER(ah)) {
560 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
561 | SM(0, AR_D_LCL_IFS_CWMAX)
562 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
563 }
f1dc5600
S		 564 break;
565 case ATH9K_TX_QUEUE_CAB:
7d0d0df0
S		 566 ENABLE_REGWRITE_BUFFER(ah);
567
f1dc5600
S		 568 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
569 | AR_Q_MISC_FSP_DBA_GATED
570 | AR_Q_MISC_CBR_INCR_DIS1
571 | AR_Q_MISC_CBR_INCR_DIS0);
572 value = (qi->tqi_readyTime -
2660b81a
S		 573 (ah->config.sw_beacon_response_time -
574 ah->config.dma_beacon_response_time) -
575 ah->config.additional_swba_backoff) * 1024;
f1dc5600
S		 576 REG_WRITE(ah, AR_QRDYTIMECFG(q),
577 value | AR_Q_RDYTIMECFG_EN);
578 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
579 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
580 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
7d0d0df0
S		 581
582 REGWRITE_BUFFER_FLUSH(ah);
583 DISABLE_REGWRITE_BUFFER(ah);
584
f1dc5600
S		 585 break;
586 case ATH9K_TX_QUEUE_PSPOLL:
587 REG_WRITE(ah, AR_QMISC(q),
588 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
589 break;
590 case ATH9K_TX_QUEUE_UAPSD:
591 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
592 AR_D_MISC_POST_FR_BKOFF_DIS);
593 break;
594 default:
595 break;
596 }
597
598 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
599 REG_WRITE(ah, AR_DMISC(q),
600 REG_READ(ah, AR_DMISC(q)) |
601 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
602 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
603 AR_D_MISC_POST_FR_BKOFF_DIS);
604 }
605
79de2375
LR		 606 if (AR_SREV_9300_20_OR_LATER(ah))
607 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
608
f1dc5600 609 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
2660b81a 610 ah->txok_interrupt_mask |= 1 << q;
f1dc5600 611 else
2660b81a 612 ah->txok_interrupt_mask &= ~(1 << q);
f1dc5600 613 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
2660b81a 614 ah->txerr_interrupt_mask |= 1 << q;
f1dc5600 615 else
2660b81a 616 ah->txerr_interrupt_mask &= ~(1 << q);
f1dc5600 617 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
2660b81a 618 ah->txdesc_interrupt_mask |= 1 << q;
f1dc5600 619 else
2660b81a 620 ah->txdesc_interrupt_mask &= ~(1 << q);
f1dc5600 621 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
2660b81a 622 ah->txeol_interrupt_mask |= 1 << q;
f1dc5600 623 else
2660b81a 624 ah->txeol_interrupt_mask &= ~(1 << q);
f1dc5600 625 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
2660b81a 626 ah->txurn_interrupt_mask |= 1 << q;
f1dc5600 627 else
2660b81a 628 ah->txurn_interrupt_mask &= ~(1 << q);
f1dc5600
S		 629 ath9k_hw_set_txq_interrupts(ah, qi);
630
631 return true;
632}
7322fd19 633EXPORT_SYMBOL(ath9k_hw_resettxqueue);
f1dc5600 634
cbe61d8a 635int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
8e6f5aa2 636 struct ath_rx_status *rs, u64 tsf)
f1dc5600
S		 637{
638 struct ar5416_desc ads;
639 struct ar5416_desc *adsp = AR5416DESC(ds);
640 u32 phyerr;
641
642 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
643 return -EINPROGRESS;
644
645 ads.u.rx = adsp->u.rx;
646
8e6f5aa2
FF		 647 rs->rs_status = 0;
648 rs->rs_flags = 0;
f1dc5600 649
8e6f5aa2
FF		 650 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
651 rs->rs_tstamp = ads.AR_RcvTimestamp;
f1dc5600 652
dd8b15b0 653 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
8e6f5aa2
FF		 654 rs->rs_rssi = ATH9K_RSSI_BAD;
655 rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
656 rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
657 rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
658 rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
659 rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
660 rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
dd8b15b0 661 } else {
8e6f5aa2
FF		 662 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
663 rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
dd8b15b0 664 AR_RxRSSIAnt00);
8e6f5aa2 665 rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
dd8b15b0 666 AR_RxRSSIAnt01);
8e6f5aa2 667 rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
dd8b15b0 668 AR_RxRSSIAnt02);
8e6f5aa2 669 rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
dd8b15b0 670 AR_RxRSSIAnt10);
8e6f5aa2 671 rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
dd8b15b0 672 AR_RxRSSIAnt11);
8e6f5aa2 673 rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
dd8b15b0
SB		 674 AR_RxRSSIAnt12);
675 }
f1dc5600 676 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
8e6f5aa2 677 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
f1dc5600 678 else
8e6f5aa2 679 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
f1dc5600 680
8e6f5aa2
FF		 681 rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
682 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
f1dc5600 683
8e6f5aa2
FF		 684 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
685 rs->rs_moreaggr =
f1dc5600 686 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
8e6f5aa2
FF		 687 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
688 rs->rs_flags =
f1dc5600 689 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
8e6f5aa2 690 rs->rs_flags |=
f1dc5600
S		 691 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
692
693 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
8e6f5aa2 694 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
f1dc5600 695 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
8e6f5aa2 696 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
f1dc5600 697 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
8e6f5aa2 698 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
f1dc5600
S		 699
700 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
701 if (ads.ds_rxstatus8 & AR_CRCErr)
8e6f5aa2 702 rs->rs_status |= ATH9K_RXERR_CRC;
f1dc5600 703 else if (ads.ds_rxstatus8 & AR_PHYErr) {
8e6f5aa2 704 rs->rs_status |= ATH9K_RXERR_PHY;
f1dc5600 705 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
8e6f5aa2 706 rs->rs_phyerr = phyerr;
f1dc5600 707 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
8e6f5aa2 708 rs->rs_status |= ATH9K_RXERR_DECRYPT;
f1dc5600 709 else if (ads.ds_rxstatus8 & AR_MichaelErr)
8e6f5aa2 710 rs->rs_status |= ATH9K_RXERR_MIC;
f1dc5600
S		 711 }
712
713 return 0;
714}
7322fd19 715EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
f1dc5600 716
e7824a50
LR		 717/*
718 * This can stop or re-enables RX.
719 *
720 * If bool is set this will kill any frame which is currently being
721 * transferred between the MAC and baseband and also prevent any new
722 * frames from getting started.
723 */
cbe61d8a 724bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
f1dc5600
S		 725{
726 u32 reg;
727
728 if (set) {
729 REG_SET_BIT(ah, AR_DIAG_SW,
730 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
731
0caa7b14
S		 732 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
733 0, AH_WAIT_TIMEOUT)) {
f1dc5600
S		 734 REG_CLR_BIT(ah, AR_DIAG_SW,
735 (AR_DIAG_RX_DIS |
736 AR_DIAG_RX_ABORT));
737
738 reg = REG_READ(ah, AR_OBS_BUS_1);
c46917bb
LR		 739 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
740 "RX failed to go idle in 10 ms RXSM=0x%x\n",
741 reg);
f1dc5600
S		 742
743 return false;
744 }
745 } else {
746 REG_CLR_BIT(ah, AR_DIAG_SW,
747 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
748 }
749
750 return true;
751}
7322fd19 752EXPORT_SYMBOL(ath9k_hw_setrxabort);
f1dc5600 753
cbe61d8a 754void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
f1dc5600
S		 755{
756 REG_WRITE(ah, AR_RXDP, rxdp);
757}
7322fd19 758EXPORT_SYMBOL(ath9k_hw_putrxbuf);
f1dc5600 759
cbe61d8a 760void ath9k_hw_startpcureceive(struct ath_hw *ah)
f1dc5600 761{
f1dc5600
S		 762 ath9k_enable_mib_counters(ah);
763
764 ath9k_ani_reset(ah);
e7594072 765
8aa15e15 766 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
f1dc5600 767}
7322fd19 768EXPORT_SYMBOL(ath9k_hw_startpcureceive);
f1dc5600 769
cbe61d8a 770void ath9k_hw_stoppcurecv(struct ath_hw *ah)
f1dc5600
S		 771{
772 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
773
774 ath9k_hw_disable_mib_counters(ah);
775}
7322fd19 776EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
f1dc5600 777
9b9cc61c
VT		 778void ath9k_hw_abortpcurecv(struct ath_hw *ah)
779{
780 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
781
782 ath9k_hw_disable_mib_counters(ah);
783}
784EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
785
cbe61d8a 786bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
f1dc5600 787{
0caa7b14
S		 788#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
789#define AH_RX_TIME_QUANTUM 100 /* usec */
c46917bb 790 struct ath_common *common = ath9k_hw_common(ah);
0caa7b14
S		 791 int i;
792
f1dc5600
S		 793 REG_WRITE(ah, AR_CR, AR_CR_RXD);
794
0caa7b14
S		 795 /* Wait for rx enable bit to go low */
796 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
797 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
798 break;
799 udelay(AH_TIME_QUANTUM);
800 }
801
802 if (i == 0) {
c46917bb
LR		 803 ath_print(common, ATH_DBG_FATAL,
804 "DMA failed to stop in %d ms "
805 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
806 AH_RX_STOP_DMA_TIMEOUT / 1000,
807 REG_READ(ah, AR_CR),
808 REG_READ(ah, AR_DIAG_SW));
f1dc5600
S		 809 return false;
810 } else {
811 return true;
812 }
0caa7b14
S		 813
814#undef AH_RX_TIME_QUANTUM
815#undef AH_RX_STOP_DMA_TIMEOUT
f1dc5600 816}
7322fd19 817EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
536b3a7a
LR		 818
819int ath9k_hw_beaconq_setup(struct ath_hw *ah)
820{
821 struct ath9k_tx_queue_info qi;
822
823 memset(&qi, 0, sizeof(qi));
824 qi.tqi_aifs = 1;
825 qi.tqi_cwmin = 0;
826 qi.tqi_cwmax = 0;
827 /* NB: don't enable any interrupts */
828 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
829}
830EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
55e82df4
VT		 831
832bool ath9k_hw_intrpend(struct ath_hw *ah)
833{
834 u32 host_isr;
835
836 if (AR_SREV_9100(ah))
837 return true;
838
839 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
840 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
841 return true;
842
843 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
844 if ((host_isr & AR_INTR_SYNC_DEFAULT)
845 && (host_isr != AR_INTR_SPURIOUS))
846 return true;
847
848 return false;
849}
850EXPORT_SYMBOL(ath9k_hw_intrpend);
851
852enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
853 enum ath9k_int ints)
854{
855 enum ath9k_int omask = ah->imask;
856 u32 mask, mask2;
857 struct ath9k_hw_capabilities *pCap = &ah->caps;
858 struct ath_common *common = ath9k_hw_common(ah);
859
860 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
861
862 if (omask & ATH9K_INT_GLOBAL) {
863 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
864 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
865 (void) REG_READ(ah, AR_IER);
866 if (!AR_SREV_9100(ah)) {
867 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
868 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
869
870 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
871 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
872 }
873 }
874
875 /* TODO: global int Ref count */
876 mask = ints & ATH9K_INT_COMMON;
877 mask2 = 0;
878
879 if (ints & ATH9K_INT_TX) {
880 if (ah->config.tx_intr_mitigation)
881 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
5bea4006
LR		 882 else {
883 if (ah->txok_interrupt_mask)
884 mask |= AR_IMR_TXOK;
885 if (ah->txdesc_interrupt_mask)
886 mask |= AR_IMR_TXDESC;
887 }
55e82df4
VT		 888 if (ah->txerr_interrupt_mask)
889 mask |= AR_IMR_TXERR;
890 if (ah->txeol_interrupt_mask)
891 mask |= AR_IMR_TXEOL;
892 }
893 if (ints & ATH9K_INT_RX) {
894 if (AR_SREV_9300_20_OR_LATER(ah)) {
895 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
896 if (ah->config.rx_intr_mitigation) {
897 mask &= ~AR_IMR_RXOK_LP;
898 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
899 } else {
900 mask |= AR_IMR_RXOK_LP;
901 }
902 } else {
903 if (ah->config.rx_intr_mitigation)
904 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
905 else
906 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
907 }
908 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
909 mask |= AR_IMR_GENTMR;
910 }
911
912 if (ints & (ATH9K_INT_BMISC)) {
913 mask |= AR_IMR_BCNMISC;
914 if (ints & ATH9K_INT_TIM)
915 mask2 |= AR_IMR_S2_TIM;
916 if (ints & ATH9K_INT_DTIM)
917 mask2 |= AR_IMR_S2_DTIM;
918 if (ints & ATH9K_INT_DTIMSYNC)
919 mask2 |= AR_IMR_S2_DTIMSYNC;
920 if (ints & ATH9K_INT_CABEND)
921 mask2 |= AR_IMR_S2_CABEND;
922 if (ints & ATH9K_INT_TSFOOR)
923 mask2 |= AR_IMR_S2_TSFOOR;
924 }
925
926 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
927 mask |= AR_IMR_BCNMISC;
928 if (ints & ATH9K_INT_GTT)
929 mask2 |= AR_IMR_S2_GTT;
930 if (ints & ATH9K_INT_CST)
931 mask2 |= AR_IMR_S2_CST;
932 }
933
934 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
935 REG_WRITE(ah, AR_IMR, mask);
936 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
937 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
938 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
939 ah->imrs2_reg |= mask2;
940 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
941
942 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
943 if (ints & ATH9K_INT_TIM_TIMER)
944 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
945 else
946 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
947 }
948
949 if (ints & ATH9K_INT_GLOBAL) {
950 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
951 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
952 if (!AR_SREV_9100(ah)) {
953 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
954 AR_INTR_MAC_IRQ);
955 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
956
957
958 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
959 AR_INTR_SYNC_DEFAULT);
960 REG_WRITE(ah, AR_INTR_SYNC_MASK,
961 AR_INTR_SYNC_DEFAULT);
962 }
963 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
964 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
965 }
966
967 return omask;
968}
969EXPORT_SYMBOL(ath9k_hw_set_interrupts);
Linux 6.x block layer and io_uring tree(s)