Commit | Line | Data |
---|---|---|
55624204 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
55624204 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
516304b0 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
b7f080cf | 19 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
6fb1b1e1 | 21 | #include <linux/ath9k_platform.h> |
9d9779e7 | 22 | #include <linux/module.h> |
e93d083f | 23 | #include <linux/relay.h> |
b0a1ae97 | 24 | #include <net/ieee80211_radiotap.h> |
5a0e3ad6 | 25 | |
55624204 S |
26 | #include "ath9k.h" |
27 | ||
ab5c4f71 GJ |
28 | struct ath9k_eeprom_ctx { |
29 | struct completion complete; | |
30 | struct ath_hw *ah; | |
31 | }; | |
32 | ||
55624204 S |
33 | static char *dev_info = "ath9k"; |
34 | ||
35 | MODULE_AUTHOR("Atheros Communications"); | |
36 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
37 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
38 | MODULE_LICENSE("Dual BSD/GPL"); | |
39 | ||
40 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
41 | module_param_named(debug, ath9k_debug, uint, 0); | |
42 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
43 | ||
3e6109c5 JL |
44 | int ath9k_modparam_nohwcrypt; |
45 | module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); | |
55624204 S |
46 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); |
47 | ||
0c8a1e43 HX |
48 | int ath9k_led_blink; |
49 | module_param_named(blink, ath9k_led_blink, int, 0444); | |
9a75c2ff VN |
50 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); |
51 | ||
8f5dcb1c VT |
52 | static int ath9k_btcoex_enable; |
53 | module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); | |
54 | MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); | |
55 | ||
63081305 SM |
56 | static int ath9k_bt_ant_diversity; |
57 | module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); | |
58 | MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); | |
e09f2dc7 | 59 | |
8298383c SM |
60 | static int ath9k_ps_enable; |
61 | module_param_named(ps_enable, ath9k_ps_enable, int, 0444); | |
62 | MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave"); | |
63 | ||
499afacc SM |
64 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
65 | ||
78b21949 | 66 | int ath9k_use_chanctx; |
71a5f881 RM |
67 | module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444); |
68 | MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency"); | |
69 | ||
499afacc SM |
70 | #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ |
71 | ||
d584747b | 72 | bool is_ath9k_unloaded; |
55624204 | 73 | |
0cf55c21 FF |
74 | #ifdef CONFIG_MAC80211_LEDS |
75 | static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { | |
76 | { .throughput = 0 * 1024, .blink_time = 334 }, | |
77 | { .throughput = 1 * 1024, .blink_time = 260 }, | |
78 | { .throughput = 5 * 1024, .blink_time = 220 }, | |
79 | { .throughput = 10 * 1024, .blink_time = 190 }, | |
80 | { .throughput = 20 * 1024, .blink_time = 170 }, | |
81 | { .throughput = 50 * 1024, .blink_time = 150 }, | |
82 | { .throughput = 70 * 1024, .blink_time = 130 }, | |
83 | { .throughput = 100 * 1024, .blink_time = 110 }, | |
84 | { .throughput = 200 * 1024, .blink_time = 80 }, | |
85 | { .throughput = 300 * 1024, .blink_time = 50 }, | |
86 | }; | |
87 | #endif | |
88 | ||
285f2dda | 89 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 | 90 | |
d81f9a09 | 91 | static void ath9k_op_ps_wakeup(struct ath_common *common) |
99d2217b OR |
92 | { |
93 | ath9k_ps_wakeup((struct ath_softc *) common->priv); | |
94 | } | |
95 | ||
d81f9a09 | 96 | static void ath9k_op_ps_restore(struct ath_common *common) |
99d2217b OR |
97 | { |
98 | ath9k_ps_restore((struct ath_softc *) common->priv); | |
99 | } | |
100 | ||
d81f9a09 | 101 | static struct ath_ps_ops ath9k_ps_ops = { |
99d2217b OR |
102 | .wakeup = ath9k_op_ps_wakeup, |
103 | .restore = ath9k_op_ps_restore, | |
104 | }; | |
105 | ||
55624204 S |
106 | /* |
107 | * Read and write, they both share the same lock. We do this to serialize | |
108 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
109 | * as the FIFO on these devices can only accept sanely 2 requests. | |
110 | */ | |
111 | ||
112 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
113 | { | |
114 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
115 | struct ath_common *common = ath9k_hw_common(ah); | |
116 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
117 | ||
f3eef645 | 118 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
119 | unsigned long flags; |
120 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
121 | iowrite32(val, sc->mem + reg_offset); | |
122 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
123 | } else | |
124 | iowrite32(val, sc->mem + reg_offset); | |
125 | } | |
126 | ||
127 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
128 | { | |
129 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
130 | struct ath_common *common = ath9k_hw_common(ah); | |
131 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
132 | u32 val; | |
133 | ||
f3eef645 | 134 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
135 | unsigned long flags; |
136 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
137 | val = ioread32(sc->mem + reg_offset); | |
138 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
139 | } else | |
140 | val = ioread32(sc->mem + reg_offset); | |
141 | return val; | |
142 | } | |
143 | ||
d55ce0a6 OR |
144 | static void ath9k_multi_ioread32(void *hw_priv, u32 *addr, |
145 | u32 *val, u16 count) | |
146 | { | |
147 | int i; | |
148 | ||
149 | for (i = 0; i < count; i++) | |
150 | val[i] = ath9k_ioread32(hw_priv, addr[i]); | |
151 | } | |
152 | ||
153 | ||
5479de6e RM |
154 | static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, |
155 | u32 set, u32 clr) | |
156 | { | |
157 | u32 val; | |
158 | ||
159 | val = ioread32(sc->mem + reg_offset); | |
160 | val &= ~clr; | |
161 | val |= set; | |
162 | iowrite32(val, sc->mem + reg_offset); | |
163 | ||
164 | return val; | |
165 | } | |
166 | ||
845e03c9 FF |
167 | static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) |
168 | { | |
169 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
170 | struct ath_common *common = ath9k_hw_common(ah); | |
171 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
172 | unsigned long uninitialized_var(flags); | |
173 | u32 val; | |
174 | ||
f3eef645 | 175 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
845e03c9 | 176 | spin_lock_irqsave(&sc->sc_serial_rw, flags); |
5479de6e | 177 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); |
845e03c9 | 178 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); |
5479de6e RM |
179 | } else |
180 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); | |
845e03c9 FF |
181 | |
182 | return val; | |
183 | } | |
184 | ||
55624204 S |
185 | /**************************/ |
186 | /* Initialization */ | |
187 | /**************************/ | |
188 | ||
0c0280bd LR |
189 | static void ath9k_reg_notifier(struct wiphy *wiphy, |
190 | struct regulatory_request *request) | |
55624204 S |
191 | { |
192 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
9ac58615 | 193 | struct ath_softc *sc = hw->priv; |
687f545e RM |
194 | struct ath_hw *ah = sc->sc_ah; |
195 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
687f545e | 196 | |
0c0280bd | 197 | ath_reg_notifier_apply(wiphy, request, reg); |
687f545e RM |
198 | |
199 | /* Set tx power */ | |
d385c5c2 FF |
200 | if (!ah->curchan) |
201 | return; | |
202 | ||
203 | sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power; | |
204 | ath9k_ps_wakeup(sc); | |
205 | ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false); | |
206 | ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower, | |
207 | sc->cur_chan->txpower, | |
208 | &sc->cur_chan->cur_txpower); | |
209 | /* synchronize DFS detector if regulatory domain changed */ | |
210 | if (sc->dfs_detector != NULL) | |
211 | sc->dfs_detector->set_dfs_domain(sc->dfs_detector, | |
212 | request->dfs_region); | |
213 | ath9k_ps_restore(sc); | |
55624204 S |
214 | } |
215 | ||
216 | /* | |
217 | * This function will allocate both the DMA descriptor structure, and the | |
218 | * buffers it contains. These are used to contain the descriptors used | |
219 | * by the system. | |
220 | */ | |
221 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
222 | struct list_head *head, const char *name, | |
4adfcded | 223 | int nbuf, int ndesc, bool is_tx) |
55624204 | 224 | { |
55624204 | 225 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4adfcded | 226 | u8 *ds; |
b81950b1 | 227 | int i, bsize, desc_len; |
55624204 | 228 | |
d2182b69 | 229 | ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
226afe68 | 230 | name, nbuf, ndesc); |
55624204 S |
231 | |
232 | INIT_LIST_HEAD(head); | |
4adfcded VT |
233 | |
234 | if (is_tx) | |
235 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
236 | else | |
237 | desc_len = sizeof(struct ath_desc); | |
238 | ||
55624204 | 239 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 240 | if ((desc_len % 4) != 0) { |
3800276a | 241 | ath_err(common, "ath_desc not DWORD aligned\n"); |
4adfcded | 242 | BUG_ON((desc_len % 4) != 0); |
b81950b1 | 243 | return -ENOMEM; |
55624204 S |
244 | } |
245 | ||
4adfcded | 246 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
247 | |
248 | /* | |
249 | * Need additional DMA memory because we can't use | |
250 | * descriptors that cross the 4K page boundary. Assume | |
251 | * one skipped descriptor per 4K page. | |
252 | */ | |
253 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
254 | u32 ndesc_skipped = | |
255 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
256 | u32 dma_len; | |
257 | ||
258 | while (ndesc_skipped) { | |
4adfcded | 259 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
260 | dd->dd_desc_len += dma_len; |
261 | ||
262 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 263 | } |
55624204 S |
264 | } |
265 | ||
266 | /* allocate descriptors */ | |
b81950b1 FF |
267 | dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, |
268 | &dd->dd_desc_paddr, GFP_KERNEL); | |
269 | if (!dd->dd_desc) | |
270 | return -ENOMEM; | |
271 | ||
4adfcded | 272 | ds = (u8 *) dd->dd_desc; |
d2182b69 | 273 | ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
226afe68 JP |
274 | name, ds, (u32) dd->dd_desc_len, |
275 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
55624204 S |
276 | |
277 | /* allocate buffers */ | |
1a04d59d FF |
278 | if (is_tx) { |
279 | struct ath_buf *bf; | |
280 | ||
281 | bsize = sizeof(struct ath_buf) * nbuf; | |
282 | bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); | |
283 | if (!bf) | |
284 | return -ENOMEM; | |
285 | ||
286 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { | |
287 | bf->bf_desc = ds; | |
288 | bf->bf_daddr = DS2PHYS(dd, ds); | |
289 | ||
290 | if (!(sc->sc_ah->caps.hw_caps & | |
291 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
292 | /* | |
293 | * Skip descriptor addresses which can cause 4KB | |
294 | * boundary crossing (addr + length) with a 32 dword | |
295 | * descriptor fetch. | |
296 | */ | |
297 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
298 | BUG_ON((caddr_t) bf->bf_desc >= | |
299 | ((caddr_t) dd->dd_desc + | |
300 | dd->dd_desc_len)); | |
301 | ||
302 | ds += (desc_len * ndesc); | |
303 | bf->bf_desc = ds; | |
304 | bf->bf_daddr = DS2PHYS(dd, ds); | |
305 | } | |
306 | } | |
307 | list_add_tail(&bf->list, head); | |
308 | } | |
309 | } else { | |
310 | struct ath_rxbuf *bf; | |
311 | ||
312 | bsize = sizeof(struct ath_rxbuf) * nbuf; | |
313 | bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); | |
314 | if (!bf) | |
315 | return -ENOMEM; | |
316 | ||
317 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { | |
318 | bf->bf_desc = ds; | |
319 | bf->bf_daddr = DS2PHYS(dd, ds); | |
320 | ||
321 | if (!(sc->sc_ah->caps.hw_caps & | |
322 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
323 | /* | |
324 | * Skip descriptor addresses which can cause 4KB | |
325 | * boundary crossing (addr + length) with a 32 dword | |
326 | * descriptor fetch. | |
327 | */ | |
328 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
329 | BUG_ON((caddr_t) bf->bf_desc >= | |
330 | ((caddr_t) dd->dd_desc + | |
331 | dd->dd_desc_len)); | |
332 | ||
333 | ds += (desc_len * ndesc); | |
334 | bf->bf_desc = ds; | |
335 | bf->bf_daddr = DS2PHYS(dd, ds); | |
336 | } | |
55624204 | 337 | } |
1a04d59d | 338 | list_add_tail(&bf->list, head); |
55624204 | 339 | } |
55624204 S |
340 | } |
341 | return 0; | |
55624204 S |
342 | } |
343 | ||
285f2dda S |
344 | static int ath9k_init_queues(struct ath_softc *sc) |
345 | { | |
285f2dda S |
346 | int i = 0; |
347 | ||
285f2dda | 348 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 349 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
350 | ath_cabq_update(sc); |
351 | ||
f2c7a793 FF |
352 | sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); |
353 | ||
bea843c7 | 354 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
066dae93 | 355 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); |
60f2d1d5 | 356 | sc->tx.txq_map[i]->mac80211_qnum = i; |
7702e788 | 357 | sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; |
60f2d1d5 | 358 | } |
285f2dda | 359 | return 0; |
285f2dda S |
360 | } |
361 | ||
285f2dda S |
362 | static void ath9k_init_misc(struct ath_softc *sc) |
363 | { | |
364 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
365 | int i = 0; | |
3d4e20f2 | 366 | |
285f2dda | 367 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); |
55624204 | 368 | |
32efb0cc | 369 | common->last_rssi = ATH_RSSI_DUMMY_MARKER; |
364734fa | 370 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
285f2dda | 371 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 372 | |
7545daf4 | 373 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) |
55624204 | 374 | sc->beacon.bslot[i] = NULL; |
102885a5 VT |
375 | |
376 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
377 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
04ccd4a1 | 378 | |
dd7657be | 379 | sc->spec_priv.ah = sc->sc_ah; |
21af25d0 OR |
380 | sc->spec_priv.spec_config.enabled = 0; |
381 | sc->spec_priv.spec_config.short_repeat = true; | |
382 | sc->spec_priv.spec_config.count = 8; | |
383 | sc->spec_priv.spec_config.endless = false; | |
384 | sc->spec_priv.spec_config.period = 0xFF; | |
385 | sc->spec_priv.spec_config.fft_period = 0xF; | |
285f2dda | 386 | } |
55624204 | 387 | |
0f978bfa | 388 | static void ath9k_init_pcoem_platform(struct ath_softc *sc) |
9b60b64b SM |
389 | { |
390 | struct ath_hw *ah = sc->sc_ah; | |
3f2da955 | 391 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
9b60b64b SM |
392 | struct ath_common *common = ath9k_hw_common(ah); |
393 | ||
935477ed FF |
394 | if (!IS_ENABLED(CONFIG_ATH9K_PCOEM)) |
395 | return; | |
396 | ||
9b60b64b SM |
397 | if (common->bus_ops->ath_bus_type != ATH_PCI) |
398 | return; | |
399 | ||
e861ef52 SM |
400 | if (sc->driver_data & (ATH9K_PCI_CUS198 | |
401 | ATH9K_PCI_CUS230)) { | |
9b60b64b SM |
402 | ah->config.xlna_gpio = 9; |
403 | ah->config.xatten_margin_cfg = true; | |
e083a42e | 404 | ah->config.alt_mingainidx = true; |
31fd216d | 405 | ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; |
3afa6b4f SM |
406 | sc->ant_comb.low_rssi_thresh = 20; |
407 | sc->ant_comb.fast_div_bias = 3; | |
9b60b64b | 408 | |
e861ef52 SM |
409 | ath_info(common, "Set parameters for %s\n", |
410 | (sc->driver_data & ATH9K_PCI_CUS198) ? | |
411 | "CUS198" : "CUS230"); | |
3f2da955 SM |
412 | } |
413 | ||
414 | if (sc->driver_data & ATH9K_PCI_CUS217) | |
12eea640 | 415 | ath_info(common, "CUS217 card detected\n"); |
3f2da955 | 416 | |
10631336 SM |
417 | if (sc->driver_data & ATH9K_PCI_CUS252) |
418 | ath_info(common, "CUS252 card detected\n"); | |
419 | ||
3fcdd0a1 SM |
420 | if (sc->driver_data & ATH9K_PCI_AR9565_1ANT) |
421 | ath_info(common, "WB335 1-ANT card detected\n"); | |
422 | ||
423 | if (sc->driver_data & ATH9K_PCI_AR9565_2ANT) | |
424 | ath_info(common, "WB335 2-ANT card detected\n"); | |
425 | ||
4dd35640 SM |
426 | if (sc->driver_data & ATH9K_PCI_KILLER) |
427 | ath_info(common, "Killer Wireless card detected\n"); | |
428 | ||
3fcdd0a1 SM |
429 | /* |
430 | * Some WB335 cards do not support antenna diversity. Since | |
431 | * we use a hardcoded value for AR9565 instead of using the | |
432 | * EEPROM/OTP data, remove the combining feature from | |
433 | * the HW capabilities bitmap. | |
434 | */ | |
435 | if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { | |
436 | if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV)) | |
437 | pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; | |
438 | } | |
439 | ||
3f2da955 SM |
440 | if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { |
441 | pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; | |
442 | ath_info(common, "Set BT/WLAN RX diversity capability\n"); | |
9b60b64b | 443 | } |
d1ae25a0 SM |
444 | |
445 | if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { | |
446 | ah->config.pcie_waen = 0x0040473b; | |
447 | ath_info(common, "Enable WAR for ASPM D3/L1\n"); | |
448 | } | |
2d22c7dd | 449 | |
afa7e6db SM |
450 | /* |
451 | * The default value of pll_pwrsave is 1. | |
452 | * For certain AR9485 cards, it is set to 0. | |
656cd75c | 453 | * For AR9462, AR9565 it's set to 7. |
afa7e6db SM |
454 | */ |
455 | ah->config.pll_pwrsave = 1; | |
456 | ||
2d22c7dd | 457 | if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { |
afa7e6db | 458 | ah->config.pll_pwrsave = 0; |
2d22c7dd SM |
459 | ath_info(common, "Disable PLL PowerSave\n"); |
460 | } | |
aeeb2065 SM |
461 | |
462 | if (sc->driver_data & ATH9K_PCI_LED_ACT_HI) | |
463 | ah->config.led_active_high = true; | |
9b60b64b SM |
464 | } |
465 | ||
ab5c4f71 GJ |
466 | static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, |
467 | void *ctx) | |
468 | { | |
469 | struct ath9k_eeprom_ctx *ec = ctx; | |
470 | ||
471 | if (eeprom_blob) | |
472 | ec->ah->eeprom_blob = eeprom_blob; | |
473 | ||
474 | complete(&ec->complete); | |
475 | } | |
476 | ||
477 | static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) | |
478 | { | |
479 | struct ath9k_eeprom_ctx ec; | |
480 | struct ath_hw *ah = ah = sc->sc_ah; | |
481 | int err; | |
482 | ||
483 | /* try to load the EEPROM content asynchronously */ | |
484 | init_completion(&ec.complete); | |
485 | ec.ah = sc->sc_ah; | |
486 | ||
487 | err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, | |
488 | &ec, ath9k_eeprom_request_cb); | |
489 | if (err < 0) { | |
490 | ath_err(ath9k_hw_common(ah), | |
491 | "EEPROM request failed\n"); | |
492 | return err; | |
493 | } | |
494 | ||
495 | wait_for_completion(&ec.complete); | |
496 | ||
497 | if (!ah->eeprom_blob) { | |
498 | ath_err(ath9k_hw_common(ah), | |
499 | "Unable to load EEPROM file %s\n", name); | |
500 | return -EINVAL; | |
501 | } | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | static void ath9k_eeprom_release(struct ath_softc *sc) | |
507 | { | |
508 | release_firmware(sc->sc_ah->eeprom_blob); | |
509 | } | |
510 | ||
0f978bfa SM |
511 | static int ath9k_init_soc_platform(struct ath_softc *sc) |
512 | { | |
513 | struct ath9k_platform_data *pdata = sc->dev->platform_data; | |
514 | struct ath_hw *ah = sc->sc_ah; | |
515 | int ret = 0; | |
516 | ||
517 | if (!pdata) | |
518 | return 0; | |
519 | ||
520 | if (pdata->eeprom_name) { | |
521 | ret = ath9k_eeprom_request(sc, pdata->eeprom_name); | |
522 | if (ret) | |
523 | return ret; | |
524 | } | |
525 | ||
526 | if (pdata->tx_gain_buffalo) | |
527 | ah->config.tx_gain_buffalo = true; | |
528 | ||
529 | return ret; | |
530 | } | |
531 | ||
eb93e891 | 532 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, |
285f2dda S |
533 | const struct ath_bus_ops *bus_ops) |
534 | { | |
6fb1b1e1 | 535 | struct ath9k_platform_data *pdata = sc->dev->platform_data; |
285f2dda | 536 | struct ath_hw *ah = NULL; |
3f2da955 | 537 | struct ath9k_hw_capabilities *pCap; |
285f2dda S |
538 | struct ath_common *common; |
539 | int ret = 0, i; | |
540 | int csz = 0; | |
55624204 | 541 | |
b81950b1 | 542 | ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); |
285f2dda S |
543 | if (!ah) |
544 | return -ENOMEM; | |
545 | ||
c1b976d2 | 546 | ah->dev = sc->dev; |
233536e1 | 547 | ah->hw = sc->hw; |
285f2dda | 548 | ah->hw_version.devid = devid; |
f9f84e96 | 549 | ah->reg_ops.read = ath9k_ioread32; |
d55ce0a6 | 550 | ah->reg_ops.multi_read = ath9k_multi_ioread32; |
f9f84e96 | 551 | ah->reg_ops.write = ath9k_iowrite32; |
845e03c9 | 552 | ah->reg_ops.rmw = ath9k_reg_rmw; |
3f2da955 | 553 | pCap = &ah->caps; |
285f2dda | 554 | |
95a5992e | 555 | common = ath9k_hw_common(ah); |
56bdbe0d FF |
556 | |
557 | /* Will be cleared in ath9k_start() */ | |
558 | set_bit(ATH_OP_INVALID, &common->op_flags); | |
559 | ||
560 | sc->sc_ah = ah; | |
95a5992e | 561 | sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); |
89f927af | 562 | sc->tx99_power = MAX_RATE_POWER + 1; |
10e23181 | 563 | init_waitqueue_head(&sc->tx_wait); |
ca900ac9 | 564 | sc->cur_chan = &sc->chanctx[0]; |
499afacc | 565 | if (!ath9k_is_chanctx_enabled()) |
3ad9c386 | 566 | sc->cur_chan->hw_queue_base = 0; |
8e92d3f2 | 567 | |
552a5157 | 568 | if (!pdata || pdata->use_eeprom) { |
a05b5d45 | 569 | ah->ah_flags |= AH_USE_EEPROM; |
6de66dd9 FF |
570 | sc->sc_ah->led_pin = -1; |
571 | } else { | |
572 | sc->sc_ah->gpio_mask = pdata->gpio_mask; | |
573 | sc->sc_ah->gpio_val = pdata->gpio_val; | |
574 | sc->sc_ah->led_pin = pdata->led_pin; | |
f2f5f2a1 | 575 | ah->is_clk_25mhz = pdata->is_clk_25mhz; |
3762561a | 576 | ah->get_mac_revision = pdata->get_mac_revision; |
7d95847c | 577 | ah->external_reset = pdata->external_reset; |
3468968e FF |
578 | ah->disable_2ghz = pdata->disable_2ghz; |
579 | ah->disable_5ghz = pdata->disable_5ghz; | |
a59dadbe FF |
580 | if (!pdata->endian_check) |
581 | ah->ah_flags |= AH_NO_EEP_SWAP; | |
6de66dd9 | 582 | } |
a05b5d45 | 583 | |
f9f84e96 | 584 | common->ops = &ah->reg_ops; |
285f2dda | 585 | common->bus_ops = bus_ops; |
99d2217b | 586 | common->ps_ops = &ath9k_ps_ops; |
285f2dda S |
587 | common->ah = ah; |
588 | common->hw = sc->hw; | |
589 | common->priv = sc; | |
590 | common->debug_mask = ath9k_debug; | |
8f5dcb1c | 591 | common->btcoex_enabled = ath9k_btcoex_enable == 1; |
05c0be2f | 592 | common->disable_ani = false; |
e09f2dc7 | 593 | |
9b60b64b SM |
594 | /* |
595 | * Platform quirks. | |
596 | */ | |
0f978bfa SM |
597 | ath9k_init_pcoem_platform(sc); |
598 | ||
599 | ret = ath9k_init_soc_platform(sc); | |
600 | if (ret) | |
601 | return ret; | |
9b60b64b | 602 | |
e09f2dc7 | 603 | /* |
3f2da955 SM |
604 | * Enable WLAN/BT RX Antenna diversity only when: |
605 | * | |
7d845871 | 606 | * - BTCOEX is disabled. |
3f2da955 SM |
607 | * - the user manually requests the feature. |
608 | * - the HW cap is set using the platform data. | |
e09f2dc7 | 609 | */ |
7d845871 | 610 | if (!common->btcoex_enabled && ath9k_bt_ant_diversity && |
3f2da955 | 611 | (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) |
63081305 | 612 | common->bt_ant_diversity = 1; |
e09f2dc7 | 613 | |
20b25744 | 614 | spin_lock_init(&common->cc_lock); |
285f2dda S |
615 | spin_lock_init(&sc->sc_serial_rw); |
616 | spin_lock_init(&sc->sc_pm_lock); | |
bff11766 | 617 | spin_lock_init(&sc->chan_lock); |
285f2dda S |
618 | mutex_init(&sc->mutex); |
619 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); | |
fb6e252f | 620 | tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, |
285f2dda S |
621 | (unsigned long)sc); |
622 | ||
bf3dac5a | 623 | setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc); |
aaa1ec46 | 624 | INIT_WORK(&sc->hw_reset_work, ath_reset_work); |
aaa1ec46 SM |
625 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); |
626 | INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); | |
705d0bf8 SM |
627 | |
628 | ath9k_init_channel_context(sc); | |
aaa1ec46 | 629 | |
285f2dda S |
630 | /* |
631 | * Cache line size is used to size and align various | |
632 | * structures used to communicate with the hardware. | |
633 | */ | |
634 | ath_read_cachesize(common, &csz); | |
635 | common->cachelsz = csz << 2; /* convert to bytes */ | |
636 | ||
d70357d5 | 637 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 638 | ret = ath9k_hw_init(ah); |
d70357d5 | 639 | if (ret) |
285f2dda | 640 | goto err_hw; |
55624204 | 641 | |
6fb1b1e1 FF |
642 | if (pdata && pdata->macaddr) |
643 | memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); | |
644 | ||
285f2dda S |
645 | ret = ath9k_init_queues(sc); |
646 | if (ret) | |
647 | goto err_queues; | |
648 | ||
649 | ret = ath9k_init_btcoex(sc); | |
650 | if (ret) | |
651 | goto err_btcoex; | |
652 | ||
13f71050 | 653 | ret = ath9k_cmn_init_channels_rates(common); |
f209f529 FF |
654 | if (ret) |
655 | goto err_btcoex; | |
656 | ||
c7dd40c9 SM |
657 | ret = ath9k_init_p2p(sc); |
658 | if (ret) | |
4f681691 | 659 | goto err_btcoex; |
d463af4a | 660 | |
f82b4bde | 661 | ath9k_cmn_init_crypto(sc->sc_ah); |
285f2dda | 662 | ath9k_init_misc(sc); |
fbbcd146 | 663 | ath_chanctx_init(sc); |
e90e302a | 664 | ath9k_offchannel_init(sc); |
285f2dda | 665 | |
d09f5f4c SM |
666 | if (common->bus_ops->aspm_init) |
667 | common->bus_ops->aspm_init(common); | |
668 | ||
55624204 | 669 | return 0; |
285f2dda S |
670 | |
671 | err_btcoex: | |
55624204 S |
672 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
673 | if (ATH_TXQ_SETUP(sc, i)) | |
674 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda | 675 | err_queues: |
285f2dda S |
676 | ath9k_hw_deinit(ah); |
677 | err_hw: | |
ab5c4f71 | 678 | ath9k_eeprom_release(sc); |
89f927af | 679 | dev_kfree_skb_any(sc->tx99_skb); |
285f2dda | 680 | return ret; |
55624204 S |
681 | } |
682 | ||
babcbc29 FF |
683 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
684 | { | |
685 | struct ieee80211_supported_band *sband; | |
686 | struct ieee80211_channel *chan; | |
687 | struct ath_hw *ah = sc->sc_ah; | |
13f71050 | 688 | struct ath_common *common = ath9k_hw_common(ah); |
0671894f | 689 | struct cfg80211_chan_def chandef; |
babcbc29 FF |
690 | int i; |
691 | ||
13f71050 | 692 | sband = &common->sbands[band]; |
babcbc29 FF |
693 | for (i = 0; i < sband->n_channels; i++) { |
694 | chan = &sband->channels[i]; | |
695 | ah->curchan = &ah->channels[chan->hw_value]; | |
0671894f | 696 | cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); |
2297f1c7 | 697 | ath9k_cmn_get_channel(sc->hw, ah, &chandef); |
babcbc29 | 698 | ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); |
babcbc29 FF |
699 | } |
700 | } | |
701 | ||
702 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
703 | { | |
704 | struct ath_hw *ah = sc->sc_ah; | |
705 | struct ath9k_channel *curchan = ah->curchan; | |
706 | ||
707 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
57fbcce3 | 708 | ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ); |
babcbc29 | 709 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
57fbcce3 | 710 | ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ); |
babcbc29 FF |
711 | |
712 | ah->curchan = curchan; | |
713 | } | |
714 | ||
20c8e8dc | 715 | static const struct ieee80211_iface_limit if_limits[] = { |
71a5f881 | 716 | { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, |
20c8e8dc FF |
717 | { .max = 8, .types = |
718 | #ifdef CONFIG_MAC80211_MESH | |
719 | BIT(NL80211_IFTYPE_MESH_POINT) | | |
720 | #endif | |
95ae4812 FF |
721 | BIT(NL80211_IFTYPE_AP) }, |
722 | { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
20c8e8dc FF |
723 | BIT(NL80211_IFTYPE_P2P_GO) }, |
724 | }; | |
725 | ||
71a5f881 RM |
726 | static const struct ieee80211_iface_limit wds_limits[] = { |
727 | { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) }, | |
728 | }; | |
729 | ||
499afacc SM |
730 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
731 | ||
a4068323 | 732 | static const struct ieee80211_iface_limit if_limits_multi[] = { |
86162d49 SM |
733 | { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) | |
734 | BIT(NL80211_IFTYPE_AP) | | |
735 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
a4068323 | 736 | BIT(NL80211_IFTYPE_P2P_GO) }, |
86162d49 | 737 | { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) }, |
eb61f9f6 | 738 | { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) }, |
a4068323 RM |
739 | }; |
740 | ||
a4068323 RM |
741 | static const struct ieee80211_iface_combination if_comb_multi[] = { |
742 | { | |
743 | .limits = if_limits_multi, | |
744 | .n_limits = ARRAY_SIZE(if_limits_multi), | |
eb61f9f6 | 745 | .max_interfaces = 3, |
a4068323 RM |
746 | .num_different_channels = 2, |
747 | .beacon_int_infra_match = true, | |
748 | }, | |
749 | }; | |
750 | ||
499afacc SM |
751 | #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ |
752 | ||
e9cdedf6 ZK |
753 | static const struct ieee80211_iface_combination if_comb[] = { |
754 | { | |
755 | .limits = if_limits, | |
756 | .n_limits = ARRAY_SIZE(if_limits), | |
757 | .max_interfaces = 2048, | |
758 | .num_different_channels = 1, | |
759 | .beacon_int_infra_match = true, | |
1286558e FF |
760 | #ifdef CONFIG_ATH9K_DFS_CERTIFIED |
761 | .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | | |
762 | BIT(NL80211_CHAN_WIDTH_20) | | |
763 | BIT(NL80211_CHAN_WIDTH_40), | |
764 | #endif | |
e9cdedf6 | 765 | }, |
71a5f881 RM |
766 | { |
767 | .limits = wds_limits, | |
768 | .n_limits = ARRAY_SIZE(wds_limits), | |
769 | .max_interfaces = 2048, | |
770 | .num_different_channels = 1, | |
771 | .beacon_int_infra_match = true, | |
772 | }, | |
20c8e8dc | 773 | }; |
43c35284 | 774 | |
868caae3 SM |
775 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
776 | static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw) | |
777 | { | |
778 | struct ath_hw *ah = sc->sc_ah; | |
779 | struct ath_common *common = ath9k_hw_common(ah); | |
780 | ||
781 | if (!ath9k_is_chanctx_enabled()) | |
782 | return; | |
783 | ||
30686bf7 | 784 | ieee80211_hw_set(hw, QUEUE_CONTROL); |
868caae3 SM |
785 | hw->queues = ATH9K_NUM_TX_QUEUES; |
786 | hw->offchannel_tx_hw_queue = hw->queues - 1; | |
787 | hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS); | |
788 | hw->wiphy->iface_combinations = if_comb_multi; | |
789 | hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi); | |
790 | hw->wiphy->max_scan_ssids = 255; | |
791 | hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; | |
792 | hw->wiphy->max_remain_on_channel_duration = 10000; | |
793 | hw->chanctx_data_size = sizeof(void *); | |
794 | hw->extra_beacon_tailroom = | |
795 | sizeof(struct ieee80211_p2p_noa_attr) + 9; | |
796 | ||
797 | ath_dbg(common, CHAN_CTX, "Use channel contexts\n"); | |
798 | } | |
799 | #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ | |
800 | ||
7b6ef998 | 801 | static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 802 | { |
43c35284 FF |
803 | struct ath_hw *ah = sc->sc_ah; |
804 | struct ath_common *common = ath9k_hw_common(ah); | |
285f2dda | 805 | |
30686bf7 JB |
806 | ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES); |
807 | ieee80211_hw_set(hw, SUPPORTS_RC_TABLE); | |
808 | ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); | |
809 | ieee80211_hw_set(hw, SPECTRUM_MGMT); | |
810 | ieee80211_hw_set(hw, PS_NULLFUNC_STACK); | |
811 | ieee80211_hw_set(hw, SIGNAL_DBM); | |
812 | ieee80211_hw_set(hw, RX_INCLUDES_FCS); | |
813 | ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING); | |
f419c5f1 | 814 | ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); |
50e81e2f | 815 | ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS); |
55624204 | 816 | |
8298383c | 817 | if (ath9k_ps_enable) |
30686bf7 | 818 | ieee80211_hw_set(hw, SUPPORTS_PS); |
8298383c | 819 | |
b0a1ae97 | 820 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
30686bf7 | 821 | ieee80211_hw_set(hw, AMPDU_AGGREGATION); |
b0a1ae97 OR |
822 | |
823 | if (AR_SREV_9280_20_OR_LATER(ah)) | |
824 | hw->radiotap_mcs_details |= | |
825 | IEEE80211_RADIOTAP_MCS_HAVE_STBC; | |
826 | } | |
5ffaf8a3 | 827 | |
3e6109c5 | 828 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) |
30686bf7 | 829 | ieee80211_hw_set(hw, MFP_CAPABLE); |
55624204 | 830 | |
fdcf1bd4 SM |
831 | hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR | |
832 | NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE | | |
833 | NL80211_FEATURE_P2P_GO_CTWIN; | |
ec26bcc0 | 834 | |
89f927af LR |
835 | if (!config_enabled(CONFIG_ATH9K_TX99)) { |
836 | hw->wiphy->interface_modes = | |
837 | BIT(NL80211_IFTYPE_P2P_GO) | | |
838 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
839 | BIT(NL80211_IFTYPE_AP) | | |
89f927af LR |
840 | BIT(NL80211_IFTYPE_STATION) | |
841 | BIT(NL80211_IFTYPE_ADHOC) | | |
499afacc | 842 | BIT(NL80211_IFTYPE_MESH_POINT) | |
862a336c JK |
843 | BIT(NL80211_IFTYPE_WDS) | |
844 | BIT(NL80211_IFTYPE_OCB); | |
499afacc | 845 | |
eb61f9f6 JD |
846 | if (ath9k_is_chanctx_enabled()) |
847 | hw->wiphy->interface_modes |= | |
848 | BIT(NL80211_IFTYPE_P2P_DEVICE); | |
849 | ||
362210e0 AB |
850 | hw->wiphy->iface_combinations = if_comb; |
851 | hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); | |
89f927af | 852 | } |
20c8e8dc | 853 | |
531671cb | 854 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
55624204 | 855 | |
cfdc9a8b | 856 | hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; |
fd656234 | 857 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; |
81ddbb5c | 858 | hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; |
6fac8bbc | 859 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; |
d074e8d5 | 860 | hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; |
7b4f663e | 861 | hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; |
cfdc9a8b | 862 | |
868caae3 | 863 | hw->queues = 4; |
55624204 | 864 | hw->max_rates = 4; |
5f2f9e44 | 865 | hw->max_listen_interval = 10; |
65896510 | 866 | hw->max_rate_tries = 10; |
55624204 S |
867 | hw->sta_data_size = sizeof(struct ath_node); |
868 | hw->vif_data_size = sizeof(struct ath_vif); | |
029cd037 | 869 | hw->extra_tx_headroom = 4; |
55624204 | 870 | |
43c35284 FF |
871 | hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; |
872 | hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; | |
873 | ||
874 | /* single chain devices with rx diversity */ | |
875 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
876 | hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); | |
877 | ||
878 | sc->ant_rx = hw->wiphy->available_antennas_rx; | |
879 | sc->ant_tx = hw->wiphy->available_antennas_tx; | |
880 | ||
d4659912 | 881 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
57fbcce3 JB |
882 | hw->wiphy->bands[NL80211_BAND_2GHZ] = |
883 | &common->sbands[NL80211_BAND_2GHZ]; | |
d4659912 | 884 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
57fbcce3 JB |
885 | hw->wiphy->bands[NL80211_BAND_5GHZ] = |
886 | &common->sbands[NL80211_BAND_5GHZ]; | |
285f2dda | 887 | |
868caae3 SM |
888 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
889 | ath9k_set_mcc_capab(sc, hw); | |
890 | #endif | |
babaa80a | 891 | ath9k_init_wow(hw); |
b57ba3b2 | 892 | ath9k_cmn_reload_chainmask(ah); |
285f2dda S |
893 | |
894 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
895 | } |
896 | ||
eb93e891 | 897 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
55624204 S |
898 | const struct ath_bus_ops *bus_ops) |
899 | { | |
900 | struct ieee80211_hw *hw = sc->hw; | |
901 | struct ath_common *common; | |
902 | struct ath_hw *ah; | |
285f2dda | 903 | int error = 0; |
55624204 S |
904 | struct ath_regulatory *reg; |
905 | ||
285f2dda | 906 | /* Bring up device */ |
eb93e891 | 907 | error = ath9k_init_softc(devid, sc, bus_ops); |
b81950b1 FF |
908 | if (error) |
909 | return error; | |
55624204 S |
910 | |
911 | ah = sc->sc_ah; | |
912 | common = ath9k_hw_common(ah); | |
285f2dda | 913 | ath9k_set_hw_capab(sc, hw); |
55624204 | 914 | |
285f2dda | 915 | /* Initialize regulatory */ |
55624204 S |
916 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
917 | ath9k_reg_notifier); | |
918 | if (error) | |
b81950b1 | 919 | goto deinit; |
55624204 S |
920 | |
921 | reg = &common->regulatory; | |
922 | ||
285f2dda | 923 | /* Setup TX DMA */ |
55624204 S |
924 | error = ath_tx_init(sc, ATH_TXBUF); |
925 | if (error != 0) | |
b81950b1 | 926 | goto deinit; |
55624204 | 927 | |
285f2dda | 928 | /* Setup RX DMA */ |
55624204 S |
929 | error = ath_rx_init(sc, ATH_RXBUF); |
930 | if (error != 0) | |
b81950b1 | 931 | goto deinit; |
55624204 | 932 | |
babcbc29 FF |
933 | ath9k_init_txpower_limits(sc); |
934 | ||
0cf55c21 FF |
935 | #ifdef CONFIG_MAC80211_LEDS |
936 | /* must be initialized before ieee80211_register_hw */ | |
937 | sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, | |
938 | IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, | |
939 | ARRAY_SIZE(ath9k_tpt_blink)); | |
940 | #endif | |
941 | ||
285f2dda | 942 | /* Register with mac80211 */ |
55624204 | 943 | error = ieee80211_register_hw(hw); |
285f2dda | 944 | if (error) |
b81950b1 | 945 | goto rx_cleanup; |
55624204 | 946 | |
eb272441 BG |
947 | error = ath9k_init_debug(ah); |
948 | if (error) { | |
3800276a | 949 | ath_err(common, "Unable to create debugfs files\n"); |
b81950b1 | 950 | goto unregister; |
eb272441 BG |
951 | } |
952 | ||
285f2dda | 953 | /* Handle world regulatory */ |
55624204 S |
954 | if (!ath_is_world_regd(reg)) { |
955 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
956 | if (error) | |
af690092 | 957 | goto debug_cleanup; |
55624204 S |
958 | } |
959 | ||
285f2dda | 960 | ath_init_leds(sc); |
55624204 S |
961 | ath_start_rfkill_poll(sc); |
962 | ||
963 | return 0; | |
964 | ||
af690092 SM |
965 | debug_cleanup: |
966 | ath9k_deinit_debug(sc); | |
b81950b1 | 967 | unregister: |
285f2dda | 968 | ieee80211_unregister_hw(hw); |
b81950b1 | 969 | rx_cleanup: |
285f2dda | 970 | ath_rx_cleanup(sc); |
b81950b1 | 971 | deinit: |
285f2dda | 972 | ath9k_deinit_softc(sc); |
55624204 S |
973 | return error; |
974 | } | |
975 | ||
976 | /*****************************/ | |
977 | /* De-Initialization */ | |
978 | /*****************************/ | |
979 | ||
285f2dda | 980 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 981 | { |
285f2dda | 982 | int i = 0; |
55624204 | 983 | |
c7dd40c9 | 984 | ath9k_deinit_p2p(sc); |
5908120f | 985 | ath9k_deinit_btcoex(sc); |
19686ddf | 986 | |
285f2dda S |
987 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
988 | if (ATH_TXQ_SETUP(sc, i)) | |
989 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
990 | ||
bf3dac5a | 991 | del_timer_sync(&sc->sleep_timer); |
285f2dda | 992 | ath9k_hw_deinit(sc->sc_ah); |
8e92d3f2 ZK |
993 | if (sc->dfs_detector != NULL) |
994 | sc->dfs_detector->exit(sc->dfs_detector); | |
285f2dda | 995 | |
ab5c4f71 | 996 | ath9k_eeprom_release(sc); |
55624204 S |
997 | } |
998 | ||
285f2dda | 999 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
1000 | { |
1001 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
1002 | |
1003 | ath9k_ps_wakeup(sc); | |
1004 | ||
55624204 | 1005 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 1006 | ath_deinit_leds(sc); |
55624204 | 1007 | |
c7c18060 RM |
1008 | ath9k_ps_restore(sc); |
1009 | ||
af690092 | 1010 | ath9k_deinit_debug(sc); |
661d2581 | 1011 | ath9k_deinit_wow(hw); |
55624204 S |
1012 | ieee80211_unregister_hw(hw); |
1013 | ath_rx_cleanup(sc); | |
285f2dda | 1014 | ath9k_deinit_softc(sc); |
55624204 S |
1015 | } |
1016 | ||
55624204 S |
1017 | /************************/ |
1018 | /* Module Hooks */ | |
1019 | /************************/ | |
1020 | ||
1021 | static int __init ath9k_init(void) | |
1022 | { | |
1023 | int error; | |
1024 | ||
55624204 S |
1025 | error = ath_pci_init(); |
1026 | if (error < 0) { | |
516304b0 | 1027 | pr_err("No PCI devices found, driver not installed\n"); |
55624204 | 1028 | error = -ENODEV; |
9e495a26 | 1029 | goto err_out; |
55624204 S |
1030 | } |
1031 | ||
1032 | error = ath_ahb_init(); | |
1033 | if (error < 0) { | |
1034 | error = -ENODEV; | |
1035 | goto err_pci_exit; | |
1036 | } | |
1037 | ||
1038 | return 0; | |
1039 | ||
1040 | err_pci_exit: | |
1041 | ath_pci_exit(); | |
55624204 S |
1042 | err_out: |
1043 | return error; | |
1044 | } | |
1045 | module_init(ath9k_init); | |
1046 | ||
1047 | static void __exit ath9k_exit(void) | |
1048 | { | |
d584747b | 1049 | is_ath9k_unloaded = true; |
55624204 S |
1050 | ath_ahb_exit(); |
1051 | ath_pci_exit(); | |
516304b0 | 1052 | pr_info("%s: Driver unloaded\n", dev_info); |
55624204 S |
1053 | } |
1054 | module_exit(ath9k_exit); |