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ath9k_hw: clean up calibration flags
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / hw.h
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
c46917bb 33#include "../debug.h"
3a702e49 34
394cf0a1 35#define ATHEROS_VENDOR_ID 0x168c
7976b426 36
394cf0a1
S		 37#define AR5416_DEVID_PCI 0x0023
38#define AR5416_DEVID_PCIE 0x0024
39#define AR9160_DEVID_PCI 0x0027
40#define AR9280_DEVID_PCI 0x0029
41#define AR9280_DEVID_PCIE 0x002a
42#define AR9285_DEVID_PCIE 0x002b
5ffaf8a3 43#define AR2427_DEVID_PCIE 0x002c
db3cc53a
SB		 44#define AR9287_DEVID_PCI 0x002d
45#define AR9287_DEVID_PCIE 0x002e
46#define AR9300_DEVID_PCIE 0x0030
7976b426 47
394cf0a1 48#define AR5416_AR9100_DEVID 0x000b
7976b426 49
394cf0a1
S		 50#define AR_SUBVENDOR_ID_NOG 0x0e11
51#define AR_SUBVENDOR_ID_NEW_A 0x7065
52#define AR5416_MAGIC 0x19641014
53
fe12946e
VT		 54#define AR9280_COEX2WIRE_SUBSYSID 0x309b
55#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
57
e3d01bfc
LR		 58#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
59
cfe8cba9
LR		 60#define ATH_DEFAULT_NOISE_FLOOR -95
61
04658fba 62#define ATH9K_RSSI_BAD -128
990b70ab 63
394cf0a1 64/* Register read/write primitives */
9e4bffd2
LR		 65#define REG_WRITE(_ah, _reg, _val) \
66 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
67
68#define REG_READ(_ah, _reg) \
69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
394cf0a1 70
20b3efd9
S		 71#define ENABLE_REGWRITE_BUFFER(_ah) \
72 do { \
73 if (AR_SREV_9271(_ah)) \
74 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
75 } while (0)
76
77#define DISABLE_REGWRITE_BUFFER(_ah) \
78 do { \
79 if (AR_SREV_9271(_ah)) \
80 ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
81 } while (0)
82
83#define REGWRITE_BUFFER_FLUSH(_ah) \
84 do { \
85 if (AR_SREV_9271(_ah)) \
86 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
87 } while (0)
88
394cf0a1
S		 89#define SM(_v, _f) (((_v) << _f##_S) & _f)
90#define MS(_v, _f) (((_v) & _f) >> _f##_S)
91#define REG_RMW(_a, _r, _set, _clr) \
92 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
93#define REG_RMW_FIELD(_a, _r, _f, _v) \
94 REG_WRITE(_a, _r, \
95 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
1547da37
LR		 96#define REG_READ_FIELD(_a, _r, _f) \
97 (((REG_READ(_a, _r) & _f) >> _f##_S))
394cf0a1
S		 98#define REG_SET_BIT(_a, _r, _f) \
99 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
100#define REG_CLR_BIT(_a, _r, _f) \
101 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 102
394cf0a1
S		 103#define DO_DELAY(x) do { \
104 if ((++(x) % 64) == 0) \
105 udelay(1); \
106 } while (0)
f078f209 107
394cf0a1
S		 108#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
109 int r; \
110 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
111 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
112 INI_RA((iniarray), r, (column))); \
113 DO_DELAY(regWr); \
114 } \
115 } while (0)
f078f209 116
394cf0a1
S		 117#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
118#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
119#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
120#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 121#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 122#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
123#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 124
394cf0a1
S		 125#define AR_GPIOD_MASK 0x00001FFF
126#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 127
394cf0a1 128#define BASE_ACTIVATE_DELAY 100
63a75b91 129#define RTC_PLL_SETTLE_DELAY 100
394cf0a1
S		 130#define COEF_SCALE_S 24
131#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 132
394cf0a1
S		 133#define ATH9K_ANTENNA0_CHAINMASK 0x1
134#define ATH9K_ANTENNA1_CHAINMASK 0x2
135
136#define ATH9K_NUM_DMA_DEBUG_REGS 8
137#define ATH9K_NUM_QUEUES 10
138
139#define MAX_RATE_POWER 63
0caa7b14 140#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 141#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 142#define AH_TIME_QUANTUM 10
143#define AR_KEYTABLE_SIZE 128
d8caa839 144#define POWER_UP_TIME 10000
394cf0a1
S		 145#define SPUR_RSSI_THRESH 40
146
147#define CAB_TIMEOUT_VAL 10
148#define BEACON_TIMEOUT_VAL 10
149#define MIN_BEACON_TIMEOUT_VAL 1
150#define SLEEP_SLOP 3
151
152#define INIT_CONFIG_STATUS 0x00000000
153#define INIT_RSSI_THR 0x00000700
154#define INIT_BCON_CNTRL_REG 0x00000000
155
156#define TU_TO_USEC(_tu) ((_tu) << 10)
157
ceb26445
VT		 158#define ATH9K_HW_RX_HP_QDEPTH 16
159#define ATH9K_HW_RX_LP_QDEPTH 128
160
717f6bed
FF		 161#define PAPRD_GAIN_TABLE_ENTRIES 32
162#define PAPRD_TABLE_SZ 24
163
13ce3e99
LR		 164enum ath_ini_subsys {
165 ATH_INI_PRE = 0,
166 ATH_INI_CORE,
167 ATH_INI_POST,
168 ATH_INI_NUM_SPLIT,
169};
170
394cf0a1
S		 171enum wireless_mode {
172 ATH9K_MODE_11A = 0,
b9b6e15a
LR		 173 ATH9K_MODE_11G,
174 ATH9K_MODE_11NA_HT20,
175 ATH9K_MODE_11NG_HT20,
176 ATH9K_MODE_11NA_HT40PLUS,
177 ATH9K_MODE_11NA_HT40MINUS,
178 ATH9K_MODE_11NG_HT40PLUS,
179 ATH9K_MODE_11NG_HT40MINUS,
180 ATH9K_MODE_MAX,
394cf0a1 181};
f078f209 182
394cf0a1 183enum ath9k_hw_caps {
364734fa
FF		 184 ATH9K_HW_CAP_HT = BIT(0),
185 ATH9K_HW_CAP_RFSILENT = BIT(1),
186 ATH9K_HW_CAP_CST = BIT(2),
187 ATH9K_HW_CAP_ENHANCEDPM = BIT(3),
188 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
189 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
190 ATH9K_HW_CAP_EDMA = BIT(6),
191 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
192 ATH9K_HW_CAP_LDPC = BIT(8),
193 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
194 ATH9K_HW_CAP_SGI_20 = BIT(10),
195 ATH9K_HW_CAP_PAPRD = BIT(11),
196 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
394cf0a1 197};
f078f209 198
394cf0a1
S		 199struct ath9k_hw_capabilities {
200 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
201 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
202 u16 total_queues;
203 u16 keycache_size;
204 u16 low_5ghz_chan, high_5ghz_chan;
205 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 206 u16 rts_aggr_limit;
207 u8 tx_chainmask;
208 u8 rx_chainmask;
209 u16 tx_triglevel_max;
210 u16 reg_cap;
211 u8 num_gpio_pins;
212 u8 num_antcfg_2ghz;
213 u8 num_antcfg_5ghz;
ceb26445
VT		 214 u8 rx_hp_qdepth;
215 u8 rx_lp_qdepth;
216 u8 rx_status_len;
162c3be3 217 u8 tx_desc_len;
5088c2f1 218 u8 txs_len;
394cf0a1 219};
f078f209 220
394cf0a1
S		 221struct ath9k_ops_config {
222 int dma_beacon_response_time;
223 int sw_beacon_response_time;
224 int additional_swba_backoff;
225 int ack_6mb;
41f3e54d 226 u32 cwm_ignore_extcca;
394cf0a1 227 u8 pcie_powersave_enable;
6a0ec30a 228 bool pcieSerDesWrite;
394cf0a1
S		 229 u8 pcie_clock_req;
230 u32 pcie_waen;
394cf0a1
S		 231 u8 analog_shiftreg;
232 u8 ht_enable;
233 u32 ofdm_trig_low;
234 u32 ofdm_trig_high;
235 u32 cck_trig_high;
236 u32 cck_trig_low;
237 u32 enable_ani;
394cf0a1 238 int serialize_regmode;
0ce024cb 239 bool rx_intr_mitigation;
55e82df4 240 bool tx_intr_mitigation;
394cf0a1
S		 241#define SPUR_DISABLE 0
242#define SPUR_ENABLE_IOCTL 1
243#define SPUR_ENABLE_EEPROM 2
244#define AR_EEPROM_MODAL_SPURS 5
245#define AR_SPUR_5413_1 1640
246#define AR_SPUR_5413_2 1200
247#define AR_NO_SPUR 0x8000
248#define AR_BASE_FREQ_2GHZ 2300
249#define AR_BASE_FREQ_5GHZ 4900
250#define AR_SPUR_FEEQ_BOUND_HT40 19
251#define AR_SPUR_FEEQ_BOUND_HT20 10
252 int spurmode;
253 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
f4709fdf 254 u8 max_txtrig_level;
e36b27af 255 u16 ani_poll_interval; /* ANI poll interval in ms */
394cf0a1 256};
f078f209 257
394cf0a1
S		 258enum ath9k_int {
259 ATH9K_INT_RX = 0x00000001,
260 ATH9K_INT_RXDESC = 0x00000002,
b5c80475
FF		 261 ATH9K_INT_RXHP = 0x00000001,
262 ATH9K_INT_RXLP = 0x00000002,
394cf0a1
S		 263 ATH9K_INT_RXNOFRM = 0x00000008,
264 ATH9K_INT_RXEOL = 0x00000010,
265 ATH9K_INT_RXORN = 0x00000020,
266 ATH9K_INT_TX = 0x00000040,
267 ATH9K_INT_TXDESC = 0x00000080,
268 ATH9K_INT_TIM_TIMER = 0x00000100,
aea702b7 269 ATH9K_INT_BB_WATCHDOG = 0x00000400,
394cf0a1
S		 270 ATH9K_INT_TXURN = 0x00000800,
271 ATH9K_INT_MIB = 0x00001000,
272 ATH9K_INT_RXPHY = 0x00004000,
273 ATH9K_INT_RXKCM = 0x00008000,
274 ATH9K_INT_SWBA = 0x00010000,
275 ATH9K_INT_BMISS = 0x00040000,
276 ATH9K_INT_BNR = 0x00100000,
277 ATH9K_INT_TIM = 0x00200000,
278 ATH9K_INT_DTIM = 0x00400000,
279 ATH9K_INT_DTIMSYNC = 0x00800000,
280 ATH9K_INT_GPIO = 0x01000000,
281 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 282 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 283 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 284 ATH9K_INT_CST = 0x10000000,
285 ATH9K_INT_GTT = 0x20000000,
286 ATH9K_INT_FATAL = 0x40000000,
287 ATH9K_INT_GLOBAL = 0x80000000,
288 ATH9K_INT_BMISC = ATH9K_INT_TIM |
289 ATH9K_INT_DTIM |
290 ATH9K_INT_DTIMSYNC |
4af9cf4f 291 ATH9K_INT_TSFOOR |
394cf0a1
S		 292 ATH9K_INT_CABEND,
293 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
294 ATH9K_INT_RXDESC |
295 ATH9K_INT_RXEOL |
296 ATH9K_INT_RXORN |
297 ATH9K_INT_TXURN |
298 ATH9K_INT_TXDESC |
299 ATH9K_INT_MIB |
300 ATH9K_INT_RXPHY |
301 ATH9K_INT_RXKCM |
302 ATH9K_INT_SWBA |
303 ATH9K_INT_BMISS |
304 ATH9K_INT_GPIO,
305 ATH9K_INT_NOCARD = 0xffffffff
306};
f078f209 307
394cf0a1
S		 308#define CHANNEL_CW_INT 0x00002
309#define CHANNEL_CCK 0x00020
310#define CHANNEL_OFDM 0x00040
311#define CHANNEL_2GHZ 0x00080
312#define CHANNEL_5GHZ 0x00100
313#define CHANNEL_PASSIVE 0x00200
314#define CHANNEL_DYN 0x00400
315#define CHANNEL_HALF 0x04000
316#define CHANNEL_QUARTER 0x08000
317#define CHANNEL_HT20 0x10000
318#define CHANNEL_HT40PLUS 0x20000
319#define CHANNEL_HT40MINUS 0x40000
320
394cf0a1
S		 321#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
322#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
323#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
324#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
325#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
326#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
327#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
328#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
329#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
330#define CHANNEL_ALL \
331 (CHANNEL_OFDM| \
332 CHANNEL_CCK| \
333 CHANNEL_2GHZ | \
334 CHANNEL_5GHZ | \
335 CHANNEL_HT20 | \
336 CHANNEL_HT40PLUS | \
337 CHANNEL_HT40MINUS)
338
20bd2a09 339struct ath9k_hw_cal_data {
394cf0a1
S		 340 u16 channel;
341 u32 channelFlags;
394cf0a1 342 int32_t CalValid;
394cf0a1
S		 343 int8_t iCoff;
344 int8_t qCoff;
717f6bed 345 bool paprd_done;
4254bc1c 346 bool nfcal_pending;
70cf1533 347 bool nfcal_interference;
717f6bed
FF		 348 u16 small_signal_gain[AR9300_MAX_CHAINS];
349 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
20bd2a09
FF		 350 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
351};
352
353struct ath9k_channel {
354 struct ieee80211_channel *chan;
355 u16 channel;
356 u32 channelFlags;
357 u32 chanmode;
d9891c78 358 s16 noisefloor;
394cf0a1 359};
f078f209 360
394cf0a1
S		 361#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
362 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
363 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
364 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
365#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
366#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
367#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 368#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
369#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
6b42e8d0 370#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
394cf0a1 371 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
6b42e8d0 372 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
394cf0a1
S		 373
374/* These macros check chanmode and not channelFlags */
375#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
376#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
377 ((_c)->chanmode == CHANNEL_G_HT20))
378#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
379 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
380 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
381 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
382#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
383
384enum ath9k_power_mode {
385 ATH9K_PM_AWAKE = 0,
386 ATH9K_PM_FULL_SLEEP,
387 ATH9K_PM_NETWORK_SLEEP,
388 ATH9K_PM_UNDEFINED
389};
f078f209 390
394cf0a1
S		 391enum ath9k_tp_scale {
392 ATH9K_TP_SCALE_MAX = 0,
393 ATH9K_TP_SCALE_50,
394 ATH9K_TP_SCALE_25,
395 ATH9K_TP_SCALE_12,
396 ATH9K_TP_SCALE_MIN
397};
f078f209 398
394cf0a1
S		 399enum ser_reg_mode {
400 SER_REG_MODE_OFF = 0,
401 SER_REG_MODE_ON = 1,
402 SER_REG_MODE_AUTO = 2,
403};
f078f209 404
ad7b8060
VT		 405enum ath9k_rx_qtype {
406 ATH9K_RX_QUEUE_HP,
407 ATH9K_RX_QUEUE_LP,
408 ATH9K_RX_QUEUE_MAX,
409};
410
394cf0a1
S		 411struct ath9k_beacon_state {
412 u32 bs_nexttbtt;
413 u32 bs_nextdtim;
414 u32 bs_intval;
415#define ATH9K_BEACON_PERIOD 0x0000ffff
416#define ATH9K_BEACON_ENA 0x00800000
417#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 418#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 419 u32 bs_dtimperiod;
420 u16 bs_cfpperiod;
421 u16 bs_cfpmaxduration;
422 u32 bs_cfpnext;
423 u16 bs_timoffset;
424 u16 bs_bmissthreshold;
425 u32 bs_sleepduration;
4af9cf4f 426 u32 bs_tsfoor_threshold;
394cf0a1 427};
f078f209 428
394cf0a1
S		 429struct chan_centers {
430 u16 synth_center;
431 u16 ctl_center;
432 u16 ext_center;
433};
f078f209 434
394cf0a1
S		 435enum {
436 ATH9K_RESET_POWER_ON,
437 ATH9K_RESET_WARM,
438 ATH9K_RESET_COLD,
439};
f078f209 440
d535a42a
S		 441struct ath9k_hw_version {
442 u32 magic;
443 u16 devid;
444 u16 subvendorid;
445 u32 macVersion;
446 u16 macRev;
447 u16 phyRev;
448 u16 analog5GhzRev;
449 u16 analog2GhzRev;
aeac355d 450 u16 subsysid;
d535a42a 451};
394cf0a1 452
ff155a45
VT		 453/* Generic TSF timer definitions */
454
455#define ATH_MAX_GEN_TIMER 16
456
457#define AR_GENTMR_BIT(_index) (1 << (_index))
458
459/*
77c2061d 460 * Using de Bruijin sequence to look up 1's index in a 32 bit number
ff155a45
VT		 461 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
462 */
c90017dd 463#define debruijn32 0x077CB531U
ff155a45
VT		 464
465struct ath_gen_timer_configuration {
466 u32 next_addr;
467 u32 period_addr;
468 u32 mode_addr;
469 u32 mode_mask;
470};
471
472struct ath_gen_timer {
473 void (*trigger)(void *arg);
474 void (*overflow)(void *arg);
475 void *arg;
476 u8 index;
477};
478
479struct ath_gen_timer_table {
480 u32 gen_timer_index[32];
481 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
482 union {
483 unsigned long timer_bits;
484 u16 val;
485 } timer_mask;
486};
487
21cc630f
VT		 488struct ath_hw_antcomb_conf {
489 u8 main_lna_conf;
490 u8 alt_lna_conf;
491 u8 fast_div_bias;
492};
493
d70357d5
LR		 494/**
495 * struct ath_hw_private_ops - callbacks used internally by hardware code
496 *
497 * This structure contains private callbacks designed to only be used internally
498 * by the hardware core.
499 *
795f5e2c
LR		 500 * @init_cal_settings: setup types of calibrations supported
501 * @init_cal: starts actual calibration
502 *
d70357d5 503 * @init_mode_regs: Initializes mode registers
991312d8 504 * @init_mode_gain_regs: Initialize TX/RX gain registers
d70357d5 505 * @macversion_supported: If this specific mac revision is supported
8fe65368
LR		 506 *
507 * @rf_set_freq: change frequency
508 * @spur_mitigate_freq: spur mitigation
509 * @rf_alloc_ext_banks:
510 * @rf_free_ext_banks:
511 * @set_rf_regs:
64773964
LR		 512 * @compute_pll_control: compute the PLL control value to use for
513 * AR_RTC_PLL_CONTROL for a given channel
795f5e2c
LR		 514 * @setup_calibration: set up calibration
515 * @iscal_supported: used to query if a type of calibration is supported
ac0bb767
LR		 516 *
517 * @ani_reset: reset ANI parameters to default values
518 * @ani_lower_immunity: lower the noise immunity level. The level controls
519 * the power-based packet detection on hardware. If a power jump is
520 * detected the adapter takes it as an indication that a packet has
521 * arrived. The level ranges from 0-5. Each level corresponds to a
522 * few dB more of noise immunity. If you have a strong time-varying
523 * interference that is causing false detections (OFDM timing errors or
524 * CCK timing errors) the level can be increased.
e36b27af
LR		 525 * @ani_cache_ini_regs: cache the values for ANI from the initial
526 * register settings through the register initialization.
d70357d5
LR		 527 */
528struct ath_hw_private_ops {
795f5e2c 529 /* Calibration ops */
d70357d5 530 void (*init_cal_settings)(struct ath_hw *ah);
795f5e2c
LR		 531 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
532
d70357d5 533 void (*init_mode_regs)(struct ath_hw *ah);
991312d8 534 void (*init_mode_gain_regs)(struct ath_hw *ah);
d70357d5 535 bool (*macversion_supported)(u32 macversion);
795f5e2c
LR		 536 void (*setup_calibration)(struct ath_hw *ah,
537 struct ath9k_cal_list *currCal);
8fe65368
LR		 538
539 /* PHY ops */
540 int (*rf_set_freq)(struct ath_hw *ah,
541 struct ath9k_channel *chan);
542 void (*spur_mitigate_freq)(struct ath_hw *ah,
543 struct ath9k_channel *chan);
544 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
545 void (*rf_free_ext_banks)(struct ath_hw *ah);
546 bool (*set_rf_regs)(struct ath_hw *ah,
547 struct ath9k_channel *chan,
548 u16 modesIndex);
549 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
550 void (*init_bb)(struct ath_hw *ah,
551 struct ath9k_channel *chan);
552 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
553 void (*olc_init)(struct ath_hw *ah);
554 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
555 void (*mark_phy_inactive)(struct ath_hw *ah);
556 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
557 bool (*rfbus_req)(struct ath_hw *ah);
558 void (*rfbus_done)(struct ath_hw *ah);
559 void (*enable_rfkill)(struct ath_hw *ah);
560 void (*restore_chainmask)(struct ath_hw *ah);
561 void (*set_diversity)(struct ath_hw *ah, bool value);
64773964
LR		 562 u32 (*compute_pll_control)(struct ath_hw *ah,
563 struct ath9k_channel *chan);
c16fcb49
FF		 564 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
565 int param);
641d9921 566 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
ac0bb767
LR		 567
568 /* ANI */
40346b66 569 void (*ani_reset)(struct ath_hw *ah, bool is_scanning);
ac0bb767 570 void (*ani_lower_immunity)(struct ath_hw *ah);
e36b27af 571 void (*ani_cache_ini_regs)(struct ath_hw *ah);
d70357d5
LR		 572};
573
574/**
575 * struct ath_hw_ops - callbacks used by hardware code and driver code
576 *
577 * This structure contains callbacks designed to to be used internally by
578 * hardware code and also by the lower level driver.
579 *
580 * @config_pci_powersave:
795f5e2c 581 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
ac0bb767
LR		 582 *
583 * @ani_proc_mib_event: process MIB events, this would happen upon specific ANI
584 * thresholds being reached or having overflowed.
585 * @ani_monitor: called periodically by the core driver to collect
586 * MIB stats and adjust ANI if specific thresholds have been reached.
d70357d5
LR		 587 */
588struct ath_hw_ops {
589 void (*config_pci_powersave)(struct ath_hw *ah,
590 int restore,
591 int power_off);
cee1f625 592 void (*rx_enable)(struct ath_hw *ah);
87d5efbb
VT		 593 void (*set_desc_link)(void *ds, u32 link);
594 void (*get_desc_link)(void *ds, u32 **link);
795f5e2c
LR		 595 bool (*calibrate)(struct ath_hw *ah,
596 struct ath9k_channel *chan,
597 u8 rxchainmask,
598 bool longcal);
55e82df4 599 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
cc610ac0
VT		 600 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
601 bool is_firstseg, bool is_is_lastseg,
602 const void *ds0, dma_addr_t buf_addr,
603 unsigned int qcu);
604 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
605 struct ath_tx_status *ts);
606 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
607 u32 pktLen, enum ath9k_pkt_type type,
608 u32 txPower, u32 keyIx,
609 enum ath9k_key_type keyType,
610 u32 flags);
611 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
612 void *lastds,
613 u32 durUpdateEn, u32 rtsctsRate,
614 u32 rtsctsDuration,
615 struct ath9k_11n_rate_series series[],
616 u32 nseries, u32 flags);
617 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
618 u32 aggrLen);
619 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
620 u32 numDelims);
621 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
622 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
623 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
624 u32 burstDuration);
625 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
626 u32 vmf);
ac0bb767
LR		 627
628 void (*ani_proc_mib_event)(struct ath_hw *ah);
629 void (*ani_monitor)(struct ath_hw *ah, struct ath9k_channel *chan);
d70357d5
LR		 630};
631
f2552e28
FF		 632struct ath_nf_limits {
633 s16 max;
634 s16 min;
635 s16 nominal;
636};
637
cbe61d8a 638struct ath_hw {
b002a4a9 639 struct ieee80211_hw *hw;
27c51f1a 640 struct ath_common common;
cbe61d8a 641 struct ath9k_hw_version hw_version;
2660b81a
S		 642 struct ath9k_ops_config config;
643 struct ath9k_hw_capabilities caps;
2660b81a
S		 644 struct ath9k_channel channels[38];
645 struct ath9k_channel *curchan;
394cf0a1 646
cbe61d8a
S		 647 union {
648 struct ar5416_eeprom_def def;
649 struct ar5416_eeprom_4k map4k;
475f5989 650 struct ar9287_eeprom map9287;
15c9ee7a 651 struct ar9300_eeprom ar9300_eep;
2660b81a 652 } eeprom;
f74df6fb 653 const struct eeprom_ops *eep_ops;
cbe61d8a
S		 654
655 bool sw_mgmt_crypto;
2660b81a 656 bool is_pciexpress;
2eb46d9b 657 bool need_an_top2_fixup;
2660b81a 658 u16 tx_trig_level;
f2552e28 659
bbacee13 660 u32 nf_regs[6];
f2552e28
FF		 661 struct ath_nf_limits nf_2g;
662 struct ath_nf_limits nf_5g;
2660b81a
S		 663 u16 rfsilent;
664 u32 rfkill_gpio;
665 u32 rfkill_polarity;
cbe61d8a 666 u32 ah_flags;
394cf0a1 667
d7e7d229
LR		 668 bool htc_reset_init;
669
2660b81a
S		 670 enum nl80211_iftype opmode;
671 enum ath9k_power_mode power_mode;
f078f209 672
20bd2a09 673 struct ath9k_hw_cal_data *caldata;
a13883b0 674 struct ath9k_pacal_info pacal_info;
2660b81a
S		 675 struct ar5416Stats stats;
676 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
677
678 int16_t curchan_rad_index;
3069168c 679 enum ath9k_int imask;
74bad5cb 680 u32 imrs2_reg;
2660b81a
S		 681 u32 txok_interrupt_mask;
682 u32 txerr_interrupt_mask;
683 u32 txdesc_interrupt_mask;
684 u32 txeol_interrupt_mask;
685 u32 txurn_interrupt_mask;
686 bool chip_fullsleep;
687 u32 atim_window;
6a2b9e8c
S		 688
689 /* Calibration */
6497827f 690 u32 supp_cals;
cbfe9468
S		 691 struct ath9k_cal_list iq_caldata;
692 struct ath9k_cal_list adcgain_caldata;
cbfe9468 693 struct ath9k_cal_list adcdc_caldata;
df23acaa 694 struct ath9k_cal_list tempCompCalData;
cbfe9468
S		 695 struct ath9k_cal_list *cal_list;
696 struct ath9k_cal_list *cal_list_last;
697 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 698#define totalPowerMeasI meas0.unsign
699#define totalPowerMeasQ meas1.unsign
700#define totalIqCorrMeas meas2.sign
701#define totalAdcIOddPhase meas0.unsign
702#define totalAdcIEvenPhase meas1.unsign
703#define totalAdcQOddPhase meas2.unsign
704#define totalAdcQEvenPhase meas3.unsign
705#define totalAdcDcOffsetIOddPhase meas0.sign
706#define totalAdcDcOffsetIEvenPhase meas1.sign
707#define totalAdcDcOffsetQOddPhase meas2.sign
708#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 709 union {
710 u32 unsign[AR5416_MAX_CHAINS];
711 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 712 } meas0;
f078f209
LR		 713 union {
714 u32 unsign[AR5416_MAX_CHAINS];
715 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 716 } meas1;
f078f209
LR		 717 union {
718 u32 unsign[AR5416_MAX_CHAINS];
719 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 720 } meas2;
f078f209
LR		 721 union {
722 u32 unsign[AR5416_MAX_CHAINS];
723 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 724 } meas3;
725 u16 cal_samples;
6a2b9e8c 726
2660b81a
S		 727 u32 sta_id1_defaults;
728 u32 misc_mode;
f078f209
LR		 729 enum {
730 AUTO_32KHZ,
731 USE_32KHZ,
732 DONT_USE_32KHZ,
2660b81a 733 } enable_32kHz_clock;
6a2b9e8c 734
d70357d5
LR		 735 /* Private to hardware code */
736 struct ath_hw_private_ops private_ops;
737 /* Accessed by the lower level driver */
738 struct ath_hw_ops ops;
739
e68a060b 740 /* Used to program the radio on non single-chip devices */
2660b81a
S		 741 u32 *analogBank0Data;
742 u32 *analogBank1Data;
743 u32 *analogBank2Data;
744 u32 *analogBank3Data;
745 u32 *analogBank6Data;
746 u32 *analogBank6TPCData;
747 u32 *analogBank7Data;
748 u32 *addac5416_21;
749 u32 *bank6Temp;
750
597a94b3 751 u8 txpower_limit;
2660b81a 752 int16_t txpower_indexoffset;
e239d859 753 int coverage_class;
2660b81a
S		 754 u32 beacon_interval;
755 u32 slottime;
2660b81a 756 u32 globaltxtimeout;
6a2b9e8c
S		 757
758 /* ANI */
2660b81a 759 u32 proc_phyerr;
2660b81a
S		 760 u32 aniperiod;
761 struct ar5416AniState *curani;
762 struct ar5416AniState ani[255];
763 int totalSizeDesired[5];
764 int coarse_high[5];
765 int coarse_low[5];
766 int firpwr[5];
767 enum ath9k_ani_cmd ani_function;
768
af03abec 769 /* Bluetooth coexistance */
766ec4a9 770 struct ath_btcoex_hw btcoex_hw;
af03abec 771
2660b81a 772 u32 intr_txqs;
2660b81a
S		 773 u8 txchainmask;
774 u8 rxchainmask;
775
8bd1d07f
SB		 776 u32 originalGain[22];
777 int initPDADC;
778 int PDADCdelta;
08fc5c1b 779 u8 led_pin;
8bd1d07f 780
2660b81a
S		 781 struct ar5416IniArray iniModes;
782 struct ar5416IniArray iniCommon;
783 struct ar5416IniArray iniBank0;
784 struct ar5416IniArray iniBB_RfGain;
785 struct ar5416IniArray iniBank1;
786 struct ar5416IniArray iniBank2;
787 struct ar5416IniArray iniBank3;
788 struct ar5416IniArray iniBank6;
789 struct ar5416IniArray iniBank6TPC;
790 struct ar5416IniArray iniBank7;
791 struct ar5416IniArray iniAddac;
792 struct ar5416IniArray iniPcieSerdes;
13ce3e99 793 struct ar5416IniArray iniPcieSerdesLowPower;
2660b81a
S		 794 struct ar5416IniArray iniModesAdditional;
795 struct ar5416IniArray iniModesRxGain;
796 struct ar5416IniArray iniModesTxGain;
8564328d 797 struct ar5416IniArray iniModes_9271_1_0_only;
193cd458
S		 798 struct ar5416IniArray iniCckfirNormal;
799 struct ar5416IniArray iniCckfirJapan2484;
70807e99
S		 800 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
801 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
802 struct ar5416IniArray iniModes_9271_ANI_reg;
803 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
804 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
ff155a45 805
13ce3e99
LR		 806 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
807 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
808 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
809 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
810
ff155a45
VT		 811 u32 intr_gen_timer_trigger;
812 u32 intr_gen_timer_thresh;
813 struct ath_gen_timer_table hw_gen_timers;
744d4025
VT		 814
815 struct ar9003_txs *ts_ring;
816 void *ts_start;
817 u32 ts_paddr_start;
818 u32 ts_paddr_end;
819 u16 ts_tail;
820 u8 ts_size;
aea702b7
LR		 821
822 u32 bb_watchdog_last_status;
823 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
717f6bed
FF		 824
825 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
826 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
9a658d2b
LR		 827 /*
828 * Store the permanent value of Reg 0x4004in WARegVal
829 * so we dont have to R/M/W. We should not be reading
830 * this register when in sleep states.
831 */
832 u32 WARegVal;
f078f209 833};
f078f209 834
9e4bffd2
LR		 835static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
836{
837 return &ah->common;
838}
839
840static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
841{
842 return &(ath9k_hw_common(ah)->regulatory);
843}
844
d70357d5
LR		 845static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
846{
847 return &ah->private_ops;
848}
849
850static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
851{
852 return &ah->ops;
853}
854
54bd5006
FF		 855static inline int sign_extend(int val, const int nbits)
856{
857 int order = BIT(nbits-1);
858 return (val ^ order) - order;
859}
860
f637cfd6 861/* Initialization, Detach, Reset */
394cf0a1 862const char *ath9k_hw_probe(u16 vendorid, u16 devid);
285f2dda 863void ath9k_hw_deinit(struct ath_hw *ah);
f637cfd6 864int ath9k_hw_init(struct ath_hw *ah);
cbe61d8a 865int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 866 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
a9a29ce6 867int ath9k_hw_fill_cap_info(struct ath_hw *ah);
8fe65368 868u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
394cf0a1 869
394cf0a1 870/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 871void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
872u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
873void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 874 u32 ah_signal_type);
cbe61d8a 875void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 876u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
877void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
21cc630f
VT		 878void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
879 struct ath_hw_antcomb_conf *antconf);
880void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
881 struct ath_hw_antcomb_conf *antconf);
394cf0a1
S		 882
883/* General Operation */
0caa7b14 884bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 885u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a 886bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
4f0fc7c3 887u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 888 u8 phy, int kbps,
394cf0a1 889 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 890void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 891 struct ath9k_channel *chan,
892 struct chan_centers *centers);
cbe61d8a
S		 893u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
894void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
895bool ath9k_hw_phy_disable(struct ath_hw *ah);
896bool ath9k_hw_disable(struct ath_hw *ah);
8fbff4b8 897void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
cbe61d8a
S		 898void ath9k_hw_setopmode(struct ath_hw *ah);
899void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 900void ath9k_hw_setbssidmask(struct ath_hw *ah);
901void ath9k_hw_write_associd(struct ath_hw *ah);
cbe61d8a
S		 902u64 ath9k_hw_gettsf64(struct ath_hw *ah);
903void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
904void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 905void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
0005baf4 906void ath9k_hw_init_global_settings(struct ath_hw *ah);
25c56eec 907void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 908void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
909void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 910 const struct ath9k_beacon_state *bs);
c9c99e5e 911bool ath9k_hw_check_alive(struct ath_hw *ah);
a91d75ae 912
9ecdef4b 913bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 914
ff155a45
VT		 915/* Generic hw timer primitives */
916struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
917 void (*trigger)(void *),
918 void (*overflow)(void *),
919 void *arg,
920 u8 timer_index);
cd9bf689
LR		 921void ath9k_hw_gen_timer_start(struct ath_hw *ah,
922 struct ath_gen_timer *timer,
923 u32 timer_next,
924 u32 timer_period);
925void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
926
ff155a45
VT		 927void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
928void ath_gen_timer_isr(struct ath_hw *hw);
1773912b 929u32 ath9k_hw_gettsf32(struct ath_hw *ah);
ff155a45 930
f934c4d9 931void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
2da4f01a 932
05020d23
S		 933/* HTC */
934void ath9k_hw_htc_resetinit(struct ath_hw *ah);
935
8fe65368
LR		 936/* PHY */
937void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
938 u32 *coef_mantissa, u32 *coef_exponent);
939
ebd5a14a
LR		 940/*
941 * Code Specific to AR5008, AR9001 or AR9002,
942 * we stuff these here to avoid callbacks for AR9003.
943 */
d8f492b7 944void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
ebd5a14a 945int ar9002_hw_rf_claim(struct ath_hw *ah);
78ec2677 946void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
e9141f71 947void ar9002_hw_update_async_fifo(struct ath_hw *ah);
6c94fdc9 948void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
d8f492b7 949
641d9921 950/*
aea702b7 951 * Code specific to AR9003, we stuff these here to avoid callbacks
641d9921
FF		 952 * for older families
953 */
aea702b7
LR		 954void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
955void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
956void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
717f6bed
FF		 957void ar9003_paprd_enable(struct ath_hw *ah, bool val);
958void ar9003_paprd_populate_single_table(struct ath_hw *ah,
20bd2a09
FF		 959 struct ath9k_hw_cal_data *caldata,
960 int chain);
961int ar9003_paprd_create_curve(struct ath_hw *ah,
962 struct ath9k_hw_cal_data *caldata, int chain);
717f6bed
FF		 963int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
964int ar9003_paprd_init_table(struct ath_hw *ah);
965bool ar9003_paprd_is_done(struct ath_hw *ah);
966void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
641d9921
FF		 967
968/* Hardware family op attach helpers */
8fe65368 969void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
8525f280
LR		 970void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
971void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
8fe65368 972
795f5e2c
LR		 973void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
974void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
975
b3950e6a
LR		 976void ar9002_hw_attach_ops(struct ath_hw *ah);
977void ar9003_hw_attach_ops(struct ath_hw *ah);
978
c2ba3342 979void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767
LR		 980/*
981 * ANI work can be shared between all families but a next
982 * generation implementation of ANI will be used only for AR9003 only
983 * for now as the other families still need to be tested with the same
e36b27af
LR		 984 * next generation ANI. Feel free to start testing it though for the
985 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
ac0bb767 986 */
e36b27af 987extern int modparam_force_new_ani;
ac0bb767 988void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah);
e36b27af 989void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah);
ac0bb767 990
7b6840ab
VT		 991#define ATH_PCIE_CAP_LINK_CTRL 0x70
992#define ATH_PCIE_CAP_LINK_L0S 1
993#define ATH_PCIE_CAP_LINK_L1 2
994
73377256
LR		 995#define ATH9K_CLOCK_RATE_CCK 22
996#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
997#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
998#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
999
f078f209 1000#endif
Linux 6.x block layer and io_uring tree(s)