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Merge tag 'v3.5-rc7' into regulator-drivers
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
f078f209
LR		 20#include <asm/unaligned.h>
21
af03abec 22#include "hw.h"
d70357d5 23#include "hw-ops.h"
cfe8cba9 24#include "rc.h"
b622a720 25#include "ar9003_mac.h"
f4701b5a 26#include "ar9003_mci.h"
462e58f2
BG		 27#include "debug.h"
28#include "ath9k.h"
f078f209 29
cbe61d8a 30static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 31
7322fd19
LR		 32MODULE_AUTHOR("Atheros Communications");
33MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
34MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
35MODULE_LICENSE("Dual BSD/GPL");
36
37static int __init ath9k_init(void)
38{
39 return 0;
40}
41module_init(ath9k_init);
42
43static void __exit ath9k_exit(void)
44{
45 return;
46}
47module_exit(ath9k_exit);
48
d70357d5
LR		 49/* Private hardware callbacks */
50
51static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
52{
53 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
54}
55
56static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
57{
58 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
59}
60
64773964
LR		 61static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
62 struct ath9k_channel *chan)
63{
64 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
65}
66
991312d8
LR		 67static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
68{
69 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
70 return;
71
72 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
73}
74
e36b27af
LR		 75static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
76{
77 /* You will not have this callback if using the old ANI */
78 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
79 return;
80
81 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
82}
83
f1dc5600
S		 84/********************/
85/* Helper Functions */
86/********************/
f078f209 87
462e58f2
BG		 88#ifdef CONFIG_ATH9K_DEBUGFS
89
90void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
91{
92 struct ath_softc *sc = common->priv;
93 if (sync_cause)
94 sc->debug.stats.istats.sync_cause_all++;
95 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
96 sc->debug.stats.istats.sync_rtc_irq++;
97 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
98 sc->debug.stats.istats.sync_mac_irq++;
99 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
100 sc->debug.stats.istats.eeprom_illegal_access++;
101 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
102 sc->debug.stats.istats.apb_timeout++;
103 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
104 sc->debug.stats.istats.pci_mode_conflict++;
105 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
106 sc->debug.stats.istats.host1_fatal++;
107 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
108 sc->debug.stats.istats.host1_perr++;
109 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
110 sc->debug.stats.istats.trcv_fifo_perr++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
112 sc->debug.stats.istats.radm_cpl_ep++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
114 sc->debug.stats.istats.radm_cpl_dllp_abort++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
116 sc->debug.stats.istats.radm_cpl_tlp_abort++;
117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
118 sc->debug.stats.istats.radm_cpl_ecrc_err++;
119 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
120 sc->debug.stats.istats.radm_cpl_timeout++;
121 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
122 sc->debug.stats.istats.local_timeout++;
123 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
124 sc->debug.stats.istats.pm_access++;
125 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
126 sc->debug.stats.istats.mac_awake++;
127 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
128 sc->debug.stats.istats.mac_asleep++;
129 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
130 sc->debug.stats.istats.mac_sleep_access++;
131}
132#endif
133
134
dfdac8ac 135static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 136{
b002a4a9 137 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
dfdac8ac
FF		 138 struct ath_common *common = ath9k_hw_common(ah);
139 unsigned int clockrate;
cbe61d8a 140
087b6ff6
FF		 141 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
142 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
143 clockrate = 117;
144 else if (!ah->curchan) /* should really check for CCK instead */
dfdac8ac
FF		 145 clockrate = ATH9K_CLOCK_RATE_CCK;
146 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
147 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
148 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
149 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 150 else
dfdac8ac
FF		 151 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
152
153 if (conf_is_ht40(conf))
154 clockrate *= 2;
155
906c7205
FF		 156 if (ah->curchan) {
157 if (IS_CHAN_HALF_RATE(ah->curchan))
158 clockrate /= 2;
159 if (IS_CHAN_QUARTER_RATE(ah->curchan))
160 clockrate /= 4;
161 }
162
dfdac8ac 163 common->clockrate = clockrate;
f1dc5600
S		 164}
165
cbe61d8a 166static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 167{
dfdac8ac 168 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 169
dfdac8ac 170 return usecs * common->clockrate;
f1dc5600 171}
f078f209 172
0caa7b14 173bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 174{
175 int i;
176
0caa7b14
S		 177 BUG_ON(timeout < AH_TIME_QUANTUM);
178
179 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 180 if ((REG_READ(ah, reg) & mask) == val)
181 return true;
182
183 udelay(AH_TIME_QUANTUM);
184 }
04bd4638 185
d2182b69 186 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 187 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
188 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 189
f1dc5600 190 return false;
f078f209 191}
7322fd19 192EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 193
7c5adc8d
FF		 194void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
195 int hw_delay)
196{
197 if (IS_CHAN_B(chan))
198 hw_delay = (4 * hw_delay) / 22;
199 else
200 hw_delay /= 10;
201
202 if (IS_CHAN_HALF_RATE(chan))
203 hw_delay *= 2;
204 else if (IS_CHAN_QUARTER_RATE(chan))
205 hw_delay *= 4;
206
207 udelay(hw_delay + BASE_ACTIVATE_DELAY);
208}
209
a9b6b256
FF		 210void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
211 int column, unsigned int *writecnt)
212{
213 int r;
214
215 ENABLE_REGWRITE_BUFFER(ah);
216 for (r = 0; r < array->ia_rows; r++) {
217 REG_WRITE(ah, INI_RA(array, r, 0),
218 INI_RA(array, r, column));
219 DO_DELAY(*writecnt);
220 }
221 REGWRITE_BUFFER_FLUSH(ah);
222}
223
f078f209
LR		 224u32 ath9k_hw_reverse_bits(u32 val, u32 n)
225{
226 u32 retval;
227 int i;
228
229 for (i = 0, retval = 0; i < n; i++) {
230 retval = (retval << 1) | (val & 1);
231 val >>= 1;
232 }
233 return retval;
234}
235
cbe61d8a 236u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 237 u8 phy, int kbps,
f1dc5600
S		 238 u32 frameLen, u16 rateix,
239 bool shortPreamble)
f078f209 240{
f1dc5600 241 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 242
f1dc5600
S		 243 if (kbps == 0)
244 return 0;
f078f209 245
545750d3 246 switch (phy) {
46d14a58 247 case WLAN_RC_PHY_CCK:
f1dc5600 248 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 249 if (shortPreamble)
f1dc5600
S		 250 phyTime >>= 1;
251 numBits = frameLen << 3;
252 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
253 break;
46d14a58 254 case WLAN_RC_PHY_OFDM:
2660b81a 255 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 256 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
257 numBits = OFDM_PLCP_BITS + (frameLen << 3);
258 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
259 txTime = OFDM_SIFS_TIME_QUARTER
260 + OFDM_PREAMBLE_TIME_QUARTER
261 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 262 } else if (ah->curchan &&
263 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
265 numBits = OFDM_PLCP_BITS + (frameLen << 3);
266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
267 txTime = OFDM_SIFS_TIME_HALF +
268 OFDM_PREAMBLE_TIME_HALF
269 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
270 } else {
271 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
272 numBits = OFDM_PLCP_BITS + (frameLen << 3);
273 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
274 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
275 + (numSymbols * OFDM_SYMBOL_TIME);
276 }
277 break;
278 default:
3800276a
JP		 279 ath_err(ath9k_hw_common(ah),
280 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 281 txTime = 0;
282 break;
283 }
f078f209 284
f1dc5600
S		 285 return txTime;
286}
7322fd19 287EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 288
cbe61d8a 289void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 290 struct ath9k_channel *chan,
291 struct chan_centers *centers)
f078f209 292{
f1dc5600 293 int8_t extoff;
f078f209 294
f1dc5600
S		 295 if (!IS_CHAN_HT40(chan)) {
296 centers->ctl_center = centers->ext_center =
297 centers->synth_center = chan->channel;
298 return;
f078f209 299 }
f078f209 300
f1dc5600
S		 301 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
302 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
303 centers->synth_center =
304 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
305 extoff = 1;
306 } else {
307 centers->synth_center =
308 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
309 extoff = -1;
310 }
f078f209 311
f1dc5600
S		 312 centers->ctl_center =
313 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 314 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 315 centers->ext_center =
6420014c 316 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 317}
318
f1dc5600
S		 319/******************/
320/* Chip Revisions */
321/******************/
322
cbe61d8a 323static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 324{
f1dc5600 325 u32 val;
f078f209 326
ecb1d385
VT		 327 switch (ah->hw_version.devid) {
328 case AR5416_AR9100_DEVID:
329 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
330 break;
3762561a
GJ		 331 case AR9300_DEVID_AR9330:
332 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
333 if (ah->get_mac_revision) {
334 ah->hw_version.macRev = ah->get_mac_revision();
335 } else {
336 val = REG_READ(ah, AR_SREV);
337 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
338 }
339 return;
ecb1d385
VT		 340 case AR9300_DEVID_AR9340:
341 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
342 val = REG_READ(ah, AR_SREV);
343 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
344 return;
345 }
346
f1dc5600 347 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 348
f1dc5600
S		 349 if (val == 0xFF) {
350 val = REG_READ(ah, AR_SREV);
d535a42a
S		 351 ah->hw_version.macVersion =
352 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
353 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 354
423e38e8 355 if (AR_SREV_9462(ah))
76ed94be
MSS		 356 ah->is_pciexpress = true;
357 else
358 ah->is_pciexpress = (val &
359 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 360 } else {
361 if (!AR_SREV_9100(ah))
d535a42a 362 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 363
d535a42a 364 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 365
d535a42a 366 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 367 ah->is_pciexpress = true;
f1dc5600 368 }
f078f209
LR		 369}
370
f1dc5600
S		 371/************************************/
372/* HW Attach, Detach, Init Routines */
373/************************************/
374
cbe61d8a 375static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 376{
040b74f7 377 if (!AR_SREV_5416(ah))
f1dc5600 378 return;
f078f209 379
f1dc5600
S		 380 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
384 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
385 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
386 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
387 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
388 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 389
f1dc5600 390 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 391}
392
d4930086
SG		 393static void ath9k_hw_aspm_init(struct ath_hw *ah)
394{
395 struct ath_common *common = ath9k_hw_common(ah);
396
397 if (common->bus_ops->aspm_init)
398 common->bus_ops->aspm_init(common);
399}
400
1f3f0618 401/* This should work for all families including legacy */
cbe61d8a 402static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 403{
c46917bb 404 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 405 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 406 u32 regHold[2];
07b2fa5a
JP		 407 static const u32 patternData[4] = {
408 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
409 };
1f3f0618 410 int i, j, loop_max;
f078f209 411
1f3f0618
SB		 412 if (!AR_SREV_9300_20_OR_LATER(ah)) {
413 loop_max = 2;
414 regAddr[1] = AR_PHY_BASE + (8 << 2);
415 } else
416 loop_max = 1;
417
418 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 419 u32 addr = regAddr[i];
420 u32 wrData, rdData;
f078f209 421
f1dc5600
S		 422 regHold[i] = REG_READ(ah, addr);
423 for (j = 0; j < 0x100; j++) {
424 wrData = (j << 16) | j;
425 REG_WRITE(ah, addr, wrData);
426 rdData = REG_READ(ah, addr);
427 if (rdData != wrData) {
3800276a
JP		 428 ath_err(common,
429 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
430 addr, wrData, rdData);
f1dc5600
S		 431 return false;
432 }
433 }
434 for (j = 0; j < 4; j++) {
435 wrData = patternData[j];
436 REG_WRITE(ah, addr, wrData);
437 rdData = REG_READ(ah, addr);
438 if (wrData != rdData) {
3800276a
JP		 439 ath_err(common,
440 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
441 addr, wrData, rdData);
f1dc5600
S		 442 return false;
443 }
f078f209 444 }
f1dc5600 445 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 446 }
f1dc5600 447 udelay(100);
cbe61d8a 448
f078f209
LR		 449 return true;
450}
451
b8b0f377 452static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 453{
454 int i;
f078f209 455
689e756f
FF		 456 ah->config.dma_beacon_response_time = 1;
457 ah->config.sw_beacon_response_time = 6;
2660b81a
S		 458 ah->config.additional_swba_backoff = 0;
459 ah->config.ack_6mb = 0x0;
460 ah->config.cwm_ignore_extcca = 0;
2660b81a 461 ah->config.pcie_clock_req = 0;
2660b81a
S		 462 ah->config.pcie_waen = 0;
463 ah->config.analog_shiftreg = 1;
03c72518 464 ah->config.enable_ani = true;
f078f209 465
f1dc5600 466 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 467 ah->config.spurchans[i][0] = AR_NO_SPUR;
468 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 469 }
470
6f481010
LR		 471 /* PAPRD needs some more work to be enabled */
472 ah->config.paprd_disable = 1;
473
0ce024cb 474 ah->config.rx_intr_mitigation = true;
6a0ec30a 475 ah->config.pcieSerDesWrite = true;
6158425b
LR		 476
477 /*
478 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
479 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
480 * This means we use it for all AR5416 devices, and the few
481 * minor PCI AR9280 devices out there.
482 *
483 * Serialization is required because these devices do not handle
484 * well the case of two concurrent reads/writes due to the latency
485 * involved. During one read/write another read/write can be issued
486 * on another CPU while the previous read/write may still be working
487 * on our hardware, if we hit this case the hardware poops in a loop.
488 * We prevent this by serializing reads and writes.
489 *
490 * This issue is not present on PCI-Express devices or pre-AR5416
491 * devices (legacy, 802.11abg).
492 */
493 if (num_possible_cpus() > 1)
2d6a5e95 494 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 495}
496
50aca25b 497static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 498{
608b88cb
LR		 499 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
500
501 regulatory->country_code = CTRY_DEFAULT;
502 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 503
d535a42a 504 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 505 ah->hw_version.subvendorid = 0;
f078f209 506
2660b81a 507 ah->atim_window = 0;
16f2411f
FF		 508 ah->sta_id1_defaults =
509 AR_STA_ID1_CRPT_MIC_ENABLE |
510 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 511 if (AR_SREV_9100(ah))
512 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
e3f2acc7 513 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 514 ah->globaltxtimeout = (u32) -1;
cbdec975 515 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 516 ah->htc_reset_init = true;
f078f209
LR		 517}
518
cbe61d8a 519static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 520{
1510718d 521 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 522 u32 sum;
523 int i;
524 u16 eeval;
07b2fa5a 525 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 526
527 sum = 0;
528 for (i = 0; i < 3; i++) {
49101676 529 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 530 sum += eeval;
1510718d
LR		 531 common->macaddr[2 * i] = eeval >> 8;
532 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 533 }
d8baa939 534 if (sum == 0 || sum == 0xffff * 3)
f078f209 535 return -EADDRNOTAVAIL;
f078f209
LR		 536
537 return 0;
538}
539
f637cfd6 540static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 541{
6cae913d 542 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 543 int ecode;
f078f209 544
6cae913d 545 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 546 if (!ath9k_hw_chip_test(ah))
547 return -ENODEV;
548 }
f078f209 549
ebd5a14a
LR		 550 if (!AR_SREV_9300_20_OR_LATER(ah)) {
551 ecode = ar9002_hw_rf_claim(ah);
552 if (ecode != 0)
553 return ecode;
554 }
f078f209 555
f637cfd6 556 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 557 if (ecode != 0)
558 return ecode;
7d01b221 559
d2182b69 560 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 561 ah->eep_ops->get_eeprom_ver(ah),
562 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 563
8fe65368
LR		 564 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
565 if (ecode) {
3800276a
JP		 566 ath_err(ath9k_hw_common(ah),
567 "Failed allocating banks for external radio\n");
48a7c3df 568 ath9k_hw_rf_free_ext_banks(ah);
8fe65368 569 return ecode;
574d6b12 570 }
f078f209 571
4279425c 572 if (ah->config.enable_ani) {
f1dc5600 573 ath9k_hw_ani_setup(ah);
f637cfd6 574 ath9k_hw_ani_init(ah);
f078f209
LR		 575 }
576
f078f209
LR		 577 return 0;
578}
579
8525f280 580static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 581{
8525f280
LR		 582 if (AR_SREV_9300_20_OR_LATER(ah))
583 ar9003_hw_attach_ops(ah);
584 else
585 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 586}
587
d70357d5
LR		 588/* Called for all hardware families */
589static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 590{
c46917bb 591 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 592 int r = 0;
aa4058ae 593
ac45c12d
SB		 594 ath9k_hw_read_revisions(ah);
595
0a8d7cb0
SB		 596 /*
597 * Read back AR_WA into a permanent copy and set bits 14 and 17.
598 * We need to do this to avoid RMW of this register. We cannot
599 * read the reg when chip is asleep.
600 */
601 ah->WARegVal = REG_READ(ah, AR_WA);
602 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
603 AR_WA_ASPM_TIMER_BASED_DISABLE);
604
aa4058ae 605 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 606 ath_err(common, "Couldn't reset chip\n");
95fafca2 607 return -EIO;
aa4058ae
LR		 608 }
609
423e38e8 610 if (AR_SREV_9462(ah))
eec353c5
RM		 611 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
612
bab1f62e
LR		 613 ath9k_hw_init_defaults(ah);
614 ath9k_hw_init_config(ah);
615
8525f280 616 ath9k_hw_attach_ops(ah);
d70357d5 617
9ecdef4b 618 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 619 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 620 return -EIO;
aa4058ae
LR		 621 }
622
f3eef645 623 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
aa4058ae 624 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
7508b657 625 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
4c85ab11 626 !ah->is_pciexpress)) {
aa4058ae
LR		 627 ah->config.serialize_regmode =
628 SER_REG_MODE_ON;
629 } else {
630 ah->config.serialize_regmode =
631 SER_REG_MODE_OFF;
632 }
633 }
634
d2182b69 635 ath_dbg(common, RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 636 ah->config.serialize_regmode);
637
f4709fdf
LR		 638 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
639 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
640 else
641 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
642
6da5a720
FF		 643 switch (ah->hw_version.macVersion) {
644 case AR_SREV_VERSION_5416_PCI:
645 case AR_SREV_VERSION_5416_PCIE:
646 case AR_SREV_VERSION_9160:
647 case AR_SREV_VERSION_9100:
648 case AR_SREV_VERSION_9280:
649 case AR_SREV_VERSION_9285:
650 case AR_SREV_VERSION_9287:
651 case AR_SREV_VERSION_9271:
652 case AR_SREV_VERSION_9300:
2c8e5937 653 case AR_SREV_VERSION_9330:
6da5a720 654 case AR_SREV_VERSION_9485:
bca04689 655 case AR_SREV_VERSION_9340:
423e38e8 656 case AR_SREV_VERSION_9462:
6da5a720
FF		 657 break;
658 default:
3800276a
JP		 659 ath_err(common,
660 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
661 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 662 return -EOPNOTSUPP;
aa4058ae
LR		 663 }
664
2c8e5937
GJ		 665 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
666 AR_SREV_9330(ah))
d7e7d229
LR		 667 ah->is_pciexpress = false;
668
aa4058ae 669 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 670 ath9k_hw_init_cal_settings(ah);
671
672 ah->ani_function = ATH9K_ANI_ALL;
7a37081e 673 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 674 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 675 if (!AR_SREV_9300_20_OR_LATER(ah))
676 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae 677
4f17c48e
NM		 678 /* disable ANI for 9340 */
679 if (AR_SREV_9340(ah))
4279425c
NM		 680 ah->config.enable_ani = false;
681
aa4058ae
LR		 682 ath9k_hw_init_mode_regs(ah);
683
69ce674b 684 if (!ah->is_pciexpress)
aa4058ae
LR		 685 ath9k_hw_disablepcie(ah);
686
f637cfd6 687 r = ath9k_hw_post_init(ah);
aa4058ae 688 if (r)
95fafca2 689 return r;
aa4058ae
LR		 690
691 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 692 r = ath9k_hw_fill_cap_info(ah);
693 if (r)
694 return r;
695
69ce674b
SG		 696 if (ah->is_pciexpress)
697 ath9k_hw_aspm_init(ah);
698
4f3acf81
LR		 699 r = ath9k_hw_init_macaddr(ah);
700 if (r) {
3800276a 701 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 702 return r;
f078f209
LR		 703 }
704
d7e7d229 705 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 706 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 707 else
2660b81a 708 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 709
88e641df
GJ		 710 if (AR_SREV_9330(ah))
711 ah->bb_watchdog_timeout_ms = 85;
712 else
713 ah->bb_watchdog_timeout_ms = 25;
f078f209 714
211f5859
LR		 715 common->state = ATH_HW_INITIALIZED;
716
4f3acf81 717 return 0;
f078f209
LR		 718}
719
d70357d5 720int ath9k_hw_init(struct ath_hw *ah)
f078f209 721{
d70357d5
LR		 722 int ret;
723 struct ath_common *common = ath9k_hw_common(ah);
f078f209 724
d70357d5
LR		 725 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
726 switch (ah->hw_version.devid) {
727 case AR5416_DEVID_PCI:
728 case AR5416_DEVID_PCIE:
729 case AR5416_AR9100_DEVID:
730 case AR9160_DEVID_PCI:
731 case AR9280_DEVID_PCI:
732 case AR9280_DEVID_PCIE:
733 case AR9285_DEVID_PCIE:
db3cc53a
SB		 734 case AR9287_DEVID_PCI:
735 case AR9287_DEVID_PCIE:
d70357d5 736 case AR2427_DEVID_PCIE:
db3cc53a 737 case AR9300_DEVID_PCIE:
3050c914 738 case AR9300_DEVID_AR9485_PCIE:
999a7a88 739 case AR9300_DEVID_AR9330:
bca04689 740 case AR9300_DEVID_AR9340:
5a63ef0f 741 case AR9300_DEVID_AR9580:
423e38e8 742 case AR9300_DEVID_AR9462:
d70357d5
LR		 743 break;
744 default:
745 if (common->bus_ops->ath_bus_type == ATH_USB)
746 break;
3800276a
JP		 747 ath_err(common, "Hardware device ID 0x%04x not supported\n",
748 ah->hw_version.devid);
d70357d5
LR		 749 return -EOPNOTSUPP;
750 }
f078f209 751
d70357d5
LR		 752 ret = __ath9k_hw_init(ah);
753 if (ret) {
3800276a
JP		 754 ath_err(common,
755 "Unable to initialize hardware; initialization status: %d\n",
756 ret);
d70357d5
LR		 757 return ret;
758 }
f078f209 759
d70357d5 760 return 0;
f078f209 761}
d70357d5 762EXPORT_SYMBOL(ath9k_hw_init);
f078f209 763
cbe61d8a 764static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 765{
7d0d0df0
S		 766 ENABLE_REGWRITE_BUFFER(ah);
767
f1dc5600
S		 768 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
769 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 770
f1dc5600
S		 771 REG_WRITE(ah, AR_QOS_NO_ACK,
772 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
773 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
774 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
775
776 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
777 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
778 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
779 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
780 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 781
782 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 783}
784
b84628eb 785u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 786{
f18e3c6b
MSS		 787 struct ath_common *common = ath9k_hw_common(ah);
788 int i = 0;
789
ca7a4deb
FF		 790 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
791 udelay(100);
792 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 793
f18e3c6b
MSS		 794 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
795
ca7a4deb 796 udelay(100);
b1415819 797
f18e3c6b
MSS		 798 if (WARN_ON_ONCE(i >= 100)) {
799 ath_err(common, "PLL4 meaurement not done\n");
800 break;
801 }
802
803 i++;
804 }
805
ca7a4deb 806 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 807}
808EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
809
cbe61d8a 810static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 811 struct ath9k_channel *chan)
f078f209 812{
d09b17f7
VT		 813 u32 pll;
814
22983c30 815 if (AR_SREV_9485(ah)) {
22983c30 816
3dfd7f60
VT		 817 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
818 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
819 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
820 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
821 AR_CH0_DPLL2_KD, 0x40);
822 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
823 AR_CH0_DPLL2_KI, 0x4);
22983c30 824
3dfd7f60
VT		 825 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
826 AR_CH0_BB_DPLL1_REFDIV, 0x5);
827 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
828 AR_CH0_BB_DPLL1_NINI, 0x58);
829 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
830 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 831
832 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 833 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
834 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
835 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 836 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 837 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 838
3dfd7f60 839 /* program BB PLL phase_shift to 0x6 */
22983c30 840 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 841 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
842
843 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
844 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 845 udelay(1000);
a5415d62
GJ		 846 } else if (AR_SREV_9330(ah)) {
847 u32 ddr_dpll2, pll_control2, kd;
848
849 if (ah->is_clk_25mhz) {
850 ddr_dpll2 = 0x18e82f01;
851 pll_control2 = 0xe04a3d;
852 kd = 0x1d;
853 } else {
854 ddr_dpll2 = 0x19e82f01;
855 pll_control2 = 0x886666;
856 kd = 0x3d;
857 }
858
859 /* program DDR PLL ki and kd value */
860 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
861
862 /* program DDR PLL phase_shift */
863 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
864 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
865
866 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
867 udelay(1000);
868
869 /* program refdiv, nint, frac to RTC register */
870 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
871
872 /* program BB PLL kd and ki value */
873 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
874 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
875
876 /* program BB PLL phase_shift */
877 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
878 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
0b488ac6
VT		 879 } else if (AR_SREV_9340(ah)) {
880 u32 regval, pll2_divint, pll2_divfrac, refdiv;
881
882 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
883 udelay(1000);
884
885 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
886 udelay(100);
887
888 if (ah->is_clk_25mhz) {
889 pll2_divint = 0x54;
890 pll2_divfrac = 0x1eb85;
891 refdiv = 3;
892 } else {
893 pll2_divint = 88;
894 pll2_divfrac = 0;
895 refdiv = 5;
896 }
897
898 regval = REG_READ(ah, AR_PHY_PLL_MODE);
899 regval |= (0x1 << 16);
900 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
901 udelay(100);
902
903 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
904 (pll2_divint << 18) | pll2_divfrac);
905 udelay(100);
906
907 regval = REG_READ(ah, AR_PHY_PLL_MODE);
908 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
909 (0x4 << 26) | (0x18 << 19);
910 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
911 REG_WRITE(ah, AR_PHY_PLL_MODE,
912 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
913 udelay(1000);
22983c30 914 }
d09b17f7
VT		 915
916 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 917
d03a66c1 918 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 919
a5415d62 920 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
3dfd7f60
VT		 921 udelay(1000);
922
c75724d1
LR		 923 /* Switch the core clock for ar9271 to 117Mhz */
924 if (AR_SREV_9271(ah)) {
25e2ab17
S		 925 udelay(500);
926 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 927 }
928
f1dc5600
S		 929 udelay(RTC_PLL_SETTLE_DELAY);
930
931 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6
VT		 932
933 if (AR_SREV_9340(ah)) {
934 if (ah->is_clk_25mhz) {
935 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
936 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
937 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
938 } else {
939 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
940 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
941 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
942 }
943 udelay(100);
944 }
f078f209
LR		 945}
946
cbe61d8a 947static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 948 enum nl80211_iftype opmode)
f078f209 949{
79d1d2b8 950 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 951 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 952 AR_IMR_TXURN |
953 AR_IMR_RXERR |
954 AR_IMR_RXORN |
955 AR_IMR_BCNMISC;
f078f209 956
79d1d2b8
VT		 957 if (AR_SREV_9340(ah))
958 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
959
66860240
VT		 960 if (AR_SREV_9300_20_OR_LATER(ah)) {
961 imr_reg |= AR_IMR_RXOK_HP;
962 if (ah->config.rx_intr_mitigation)
963 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
964 else
965 imr_reg |= AR_IMR_RXOK_LP;
f078f209 966
66860240
VT		 967 } else {
968 if (ah->config.rx_intr_mitigation)
969 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
970 else
971 imr_reg |= AR_IMR_RXOK;
972 }
f078f209 973
66860240
VT		 974 if (ah->config.tx_intr_mitigation)
975 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
976 else
977 imr_reg |= AR_IMR_TXOK;
f078f209 978
d97809db 979 if (opmode == NL80211_IFTYPE_AP)
152d530d 980 imr_reg |= AR_IMR_MIB;
f078f209 981
7d0d0df0
S		 982 ENABLE_REGWRITE_BUFFER(ah);
983
152d530d 984 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 985 ah->imrs2_reg |= AR_IMR_S2_GTT;
986 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 987
f1dc5600
S		 988 if (!AR_SREV_9100(ah)) {
989 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 990 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 991 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
992 }
66860240 993
7d0d0df0 994 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 995
66860240
VT		 996 if (AR_SREV_9300_20_OR_LATER(ah)) {
997 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
998 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
999 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
1000 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
1001 }
f078f209
LR		 1002}
1003
b6ba41bb
FF		 1004static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
1005{
1006 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
1007 val = min(val, (u32) 0xFFFF);
1008 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
1009}
1010
0005baf4 1011static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 1012{
0005baf4
FF		 1013 u32 val = ath9k_hw_mac_to_clks(ah, us);
1014 val = min(val, (u32) 0xFFFF);
1015 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 1016}
1017
0005baf4 1018static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1019{
0005baf4
FF		 1020 u32 val = ath9k_hw_mac_to_clks(ah, us);
1021 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1022 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1023}
1024
1025static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1026{
1027 u32 val = ath9k_hw_mac_to_clks(ah, us);
1028 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1029 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 1030}
f1dc5600 1031
cbe61d8a 1032static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1033{
f078f209 1034 if (tu > 0xFFFF) {
d2182b69
JP		 1035 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1036 tu);
2660b81a 1037 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1038 return false;
1039 } else {
1040 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1041 ah->globaltxtimeout = tu;
f078f209
LR		 1042 return true;
1043 }
1044}
1045
0005baf4 1046void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1047{
b6ba41bb
FF		 1048 struct ath_common *common = ath9k_hw_common(ah);
1049 struct ieee80211_conf *conf = &common->hw->conf;
1050 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 1051 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 1052 int slottime;
0005baf4 1053 int sifstime;
b6ba41bb
FF		 1054 int rx_lat = 0, tx_lat = 0, eifs = 0;
1055 u32 reg;
0005baf4 1056
d2182b69 1057 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1058 ah->misc_mode);
f078f209 1059
b6ba41bb
FF		 1060 if (!chan)
1061 return;
1062
2660b81a 1063 if (ah->misc_mode != 0)
ca7a4deb 1064 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1065
81a91d57
RM		 1066 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1067 rx_lat = 41;
1068 else
1069 rx_lat = 37;
b6ba41bb
FF		 1070 tx_lat = 54;
1071
e88e4861
FF		 1072 if (IS_CHAN_5GHZ(chan))
1073 sifstime = 16;
1074 else
1075 sifstime = 10;
1076
b6ba41bb
FF		 1077 if (IS_CHAN_HALF_RATE(chan)) {
1078 eifs = 175;
1079 rx_lat *= 2;
1080 tx_lat *= 2;
1081 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1082 tx_lat += 11;
1083
e88e4861 1084 sifstime *= 2;
e115b7ec 1085 ack_offset = 16;
b6ba41bb 1086 slottime = 13;
b6ba41bb
FF		 1087 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1088 eifs = 340;
81a91d57 1089 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1090 tx_lat *= 4;
1091 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1092 tx_lat += 22;
1093
e88e4861 1094 sifstime *= 4;
e115b7ec 1095 ack_offset = 32;
b6ba41bb 1096 slottime = 21;
b6ba41bb 1097 } else {
a7be039d
RM		 1098 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1099 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1100 reg = AR_USEC_ASYNC_FIFO;
1101 } else {
1102 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1103 common->clockrate;
1104 reg = REG_READ(ah, AR_USEC);
1105 }
b6ba41bb
FF		 1106 rx_lat = MS(reg, AR_USEC_RX_LAT);
1107 tx_lat = MS(reg, AR_USEC_TX_LAT);
1108
1109 slottime = ah->slottime;
b6ba41bb 1110 }
0005baf4 1111
e239d859 1112 /* As defined by IEEE 802.11-2007 17.3.8.6 */
e115b7ec 1113 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset;
adb5066a 1114 ctstimeout = acktimeout;
42c4568a
FF		 1115
1116 /*
1117 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1118 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1119 * This was initially only meant to work around an issue with delayed
1120 * BA frames in some implementations, but it has been found to fix ACK
1121 * timeout issues in other cases as well.
1122 */
e115b7ec
FF		 1123 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ &&
1124 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1125 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1126 ctstimeout += 48 - sifstime - ah->slottime;
1127 }
1128
42c4568a 1129
b6ba41bb
FF		 1130 ath9k_hw_set_sifs_time(ah, sifstime);
1131 ath9k_hw_setslottime(ah, slottime);
0005baf4 1132 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1133 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1134 if (ah->globaltxtimeout != (u32) -1)
1135 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1136
1137 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1138 REG_RMW(ah, AR_USEC,
1139 (common->clockrate - 1) |
1140 SM(rx_lat, AR_USEC_RX_LAT) |
1141 SM(tx_lat, AR_USEC_TX_LAT),
1142 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1143
f1dc5600 1144}
0005baf4 1145EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1146
285f2dda 1147void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1148{
211f5859
LR		 1149 struct ath_common *common = ath9k_hw_common(ah);
1150
736b3a27 1151 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 1152 goto free_hw;
1153
9ecdef4b 1154 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 1155
1156free_hw:
8fe65368 1157 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 1158}
285f2dda 1159EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1160
f1dc5600
S		 1161/*******/
1162/* INI */
1163/*******/
1164
8fe65368 1165u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1166{
1167 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1168
1169 if (IS_CHAN_B(chan))
1170 ctl |= CTL_11B;
1171 else if (IS_CHAN_G(chan))
1172 ctl |= CTL_11G;
1173 else
1174 ctl |= CTL_11A;
1175
1176 return ctl;
1177}
1178
f1dc5600
S		 1179/****************************************/
1180/* Reset and Channel Switching Routines */
1181/****************************************/
f1dc5600 1182
cbe61d8a 1183static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1184{
57b32227 1185 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 1186
7d0d0df0
S		 1187 ENABLE_REGWRITE_BUFFER(ah);
1188
d7e7d229
LR		 1189 /*
1190 * set AHB_MODE not to do cacheline prefetches
1191 */
ca7a4deb
FF		 1192 if (!AR_SREV_9300_20_OR_LATER(ah))
1193 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1194
d7e7d229
LR		 1195 /*
1196 * let mac dma reads be in 128 byte chunks
1197 */
ca7a4deb 1198 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1199
7d0d0df0 1200 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1201
d7e7d229
LR		 1202 /*
1203 * Restore TX Trigger Level to its pre-reset value.
1204 * The initial value depends on whether aggregation is enabled, and is
1205 * adjusted whenever underruns are detected.
1206 */
57b32227
FF		 1207 if (!AR_SREV_9300_20_OR_LATER(ah))
1208 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1209
7d0d0df0 1210 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1211
d7e7d229
LR		 1212 /*
1213 * let mac dma writes be in 128 byte chunks
1214 */
ca7a4deb 1215 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1216
d7e7d229
LR		 1217 /*
1218 * Setup receive FIFO threshold to hold off TX activities
1219 */
f1dc5600
S		 1220 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1221
57b32227
FF		 1222 if (AR_SREV_9300_20_OR_LATER(ah)) {
1223 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1224 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1225
1226 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1227 ah->caps.rx_status_len);
1228 }
1229
d7e7d229
LR		 1230 /*
1231 * reduce the number of usable entries in PCU TXBUF to avoid
1232 * wrap around issues.
1233 */
f1dc5600 1234 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1235 /* For AR9285 the number of Fifos are reduced to half.
1236 * So set the usable tx buf size also to half to
1237 * avoid data/delimiter underruns
1238 */
f1dc5600
S		 1239 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1240 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1241 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1242 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1243 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1244 }
744d4025 1245
7d0d0df0 1246 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1247
744d4025
VT		 1248 if (AR_SREV_9300_20_OR_LATER(ah))
1249 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1250}
1251
cbe61d8a 1252static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1253{
ca7a4deb
FF		 1254 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1255 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1256
f1dc5600 1257 switch (opmode) {
d97809db 1258 case NL80211_IFTYPE_ADHOC:
9cb5412b 1259 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb 1260 set |= AR_STA_ID1_ADHOC;
f1dc5600 1261 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1262 break;
ca7a4deb
FF		 1263 case NL80211_IFTYPE_AP:
1264 set |= AR_STA_ID1_STA_AP;
1265 /* fall through */
d97809db 1266 case NL80211_IFTYPE_STATION:
ca7a4deb 1267 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1268 break;
5f841b41 1269 default:
ca7a4deb
FF		 1270 if (!ah->is_monitoring)
1271 set = 0;
5f841b41 1272 break;
f1dc5600 1273 }
ca7a4deb 1274 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1275}
1276
8fe65368
LR		 1277void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1278 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1279{
1280 u32 coef_exp, coef_man;
1281
1282 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1283 if ((coef_scaled >> coef_exp) & 0x1)
1284 break;
1285
1286 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1287
1288 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1289
1290 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1291 *coef_exponent = coef_exp - 16;
1292}
1293
cbe61d8a 1294static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1295{
1296 u32 rst_flags;
1297 u32 tmpReg;
1298
70768496 1299 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1300 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1301 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1302 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1303 }
1304
7d0d0df0
S		 1305 ENABLE_REGWRITE_BUFFER(ah);
1306
9a658d2b
LR		 1307 if (AR_SREV_9300_20_OR_LATER(ah)) {
1308 REG_WRITE(ah, AR_WA, ah->WARegVal);
1309 udelay(10);
1310 }
1311
f1dc5600
S		 1312 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1313 AR_RTC_FORCE_WAKE_ON_INT);
1314
1315 if (AR_SREV_9100(ah)) {
1316 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1317 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1318 } else {
1319 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1320 if (tmpReg &
1321 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1322 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1323 u32 val;
f1dc5600 1324 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1325
1326 val = AR_RC_HOSTIF;
1327 if (!AR_SREV_9300_20_OR_LATER(ah))
1328 val |= AR_RC_AHB;
1329 REG_WRITE(ah, AR_RC, val);
1330
1331 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1332 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1333
1334 rst_flags = AR_RTC_RC_MAC_WARM;
1335 if (type == ATH9K_RESET_COLD)
1336 rst_flags |= AR_RTC_RC_MAC_COLD;
1337 }
1338
7d95847c
GJ		 1339 if (AR_SREV_9330(ah)) {
1340 int npend = 0;
1341 int i;
1342
1343 /* AR9330 WAR:
1344 * call external reset function to reset WMAC if:
1345 * - doing a cold reset
1346 * - we have pending frames in the TX queues
1347 */
1348
1349 for (i = 0; i < AR_NUM_QCU; i++) {
1350 npend = ath9k_hw_numtxpending(ah, i);
1351 if (npend)
1352 break;
1353 }
1354
1355 if (ah->external_reset &&
1356 (npend || type == ATH9K_RESET_COLD)) {
1357 int reset_err = 0;
1358
d2182b69 1359 ath_dbg(ath9k_hw_common(ah), RESET,
7d95847c
GJ		 1360 "reset MAC via external reset\n");
1361
1362 reset_err = ah->external_reset();
1363 if (reset_err) {
1364 ath_err(ath9k_hw_common(ah),
1365 "External reset failed, err=%d\n",
1366 reset_err);
1367 return false;
1368 }
1369
1370 REG_WRITE(ah, AR_RTC_RESET, 1);
1371 }
1372 }
1373
d03a66c1 1374 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1375
1376 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1377
f1dc5600
S		 1378 udelay(50);
1379
d03a66c1 1380 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1381 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1382 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1383 return false;
1384 }
1385
1386 if (!AR_SREV_9100(ah))
1387 REG_WRITE(ah, AR_RC, 0);
1388
f1dc5600
S		 1389 if (AR_SREV_9100(ah))
1390 udelay(50);
1391
1392 return true;
1393}
1394
cbe61d8a 1395static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1396{
7d0d0df0
S		 1397 ENABLE_REGWRITE_BUFFER(ah);
1398
9a658d2b
LR		 1399 if (AR_SREV_9300_20_OR_LATER(ah)) {
1400 REG_WRITE(ah, AR_WA, ah->WARegVal);
1401 udelay(10);
1402 }
1403
f1dc5600
S		 1404 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1405 AR_RTC_FORCE_WAKE_ON_INT);
1406
42d5bc3f 1407 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1408 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1409
d03a66c1 1410 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1411
7d0d0df0 1412 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1413
84e2169b
SB		 1414 if (!AR_SREV_9300_20_OR_LATER(ah))
1415 udelay(2);
1416
1417 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1418 REG_WRITE(ah, AR_RC, 0);
1419
d03a66c1 1420 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1421
1422 if (!ath9k_hw_wait(ah,
1423 AR_RTC_STATUS,
1424 AR_RTC_STATUS_M,
0caa7b14
S		 1425 AR_RTC_STATUS_ON,
1426 AH_WAIT_TIMEOUT)) {
d2182b69 1427 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1428 return false;
f078f209
LR		 1429 }
1430
f1dc5600
S		 1431 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1432}
1433
cbe61d8a 1434static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1435{
7a9233ff 1436 bool ret = false;
2577c6e8 1437
9a658d2b
LR		 1438 if (AR_SREV_9300_20_OR_LATER(ah)) {
1439 REG_WRITE(ah, AR_WA, ah->WARegVal);
1440 udelay(10);
1441 }
1442
f1dc5600
S		 1443 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1444 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1445
1446 switch (type) {
1447 case ATH9K_RESET_POWER_ON:
7a9233ff
MSS		 1448 ret = ath9k_hw_set_reset_power_on(ah);
1449 break;
f1dc5600
S		 1450 case ATH9K_RESET_WARM:
1451 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1452 ret = ath9k_hw_set_reset(ah, type);
1453 break;
f1dc5600 1454 default:
7a9233ff 1455 break;
f1dc5600 1456 }
7a9233ff
MSS		 1457
1458 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1459 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1460
1461 return ret;
f078f209
LR		 1462}
1463
cbe61d8a 1464static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1465 struct ath9k_channel *chan)
f078f209 1466{
9c083af8
FF		 1467 int reset_type = ATH9K_RESET_WARM;
1468
1469 if (AR_SREV_9280(ah)) {
1470 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1471 reset_type = ATH9K_RESET_POWER_ON;
1472 else
1473 reset_type = ATH9K_RESET_COLD;
1474 }
1475
1476 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1477 return false;
f078f209 1478
9ecdef4b 1479 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1480 return false;
f078f209 1481
2660b81a 1482 ah->chip_fullsleep = false;
bfc441a4
FF		 1483
1484 if (AR_SREV_9330(ah))
1485 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1486 ath9k_hw_init_pll(ah, chan);
f1dc5600 1487 ath9k_hw_set_rfmode(ah, chan);
f078f209 1488
f1dc5600 1489 return true;
f078f209
LR		 1490}
1491
cbe61d8a 1492static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1493 struct ath9k_channel *chan)
f078f209 1494{
c46917bb 1495 struct ath_common *common = ath9k_hw_common(ah);
8fe65368 1496 u32 qnum;
0a3b7bac 1497 int r;
5f0c04ea
RM		 1498 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1499 bool band_switch, mode_diff;
1500 u8 ini_reloaded;
1501
1502 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1503 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1504 CHANNEL_5GHZ));
1505 mode_diff = (chan->chanmode != ah->curchan->chanmode);
f078f209
LR		 1506
1507 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1508 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1509 ath_dbg(common, QUEUE,
226afe68 1510 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1511 return false;
1512 }
1513 }
1514
8fe65368 1515 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1516 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1517 return false;
1518 }
1519
5f0c04ea
RM		 1520 if (edma && (band_switch || mode_diff)) {
1521 ath9k_hw_mark_phy_inactive(ah);
1522 udelay(5);
1523
1524 ath9k_hw_init_pll(ah, NULL);
1525
1526 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1527 ath_err(common, "Failed to do fast channel change\n");
1528 return false;
1529 }
1530 }
1531
8fe65368 1532 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1533
8fe65368 1534 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1535 if (r) {
3800276a 1536 ath_err(common, "Failed to set channel\n");
0a3b7bac 1537 return false;
f078f209 1538 }
dfdac8ac 1539 ath9k_hw_set_clockrate(ah);
64ea57d0 1540 ath9k_hw_apply_txpower(ah, chan, false);
8fe65368 1541 ath9k_hw_rfbus_done(ah);
f078f209 1542
f1dc5600
S		 1543 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1544 ath9k_hw_set_delta_slope(ah, chan);
1545
8fe65368 1546 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1547
5f0c04ea 1548 if (edma && (band_switch || mode_diff)) {
a126ff51 1549 ah->ah_flags |= AH_FASTCC;
5f0c04ea
RM		 1550 if (band_switch || ini_reloaded)
1551 ah->eep_ops->set_board_values(ah, chan);
1552
1553 ath9k_hw_init_bb(ah, chan);
1554
1555 if (band_switch || ini_reloaded)
1556 ath9k_hw_init_cal(ah, chan);
a126ff51 1557 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1558 }
1559
f1dc5600
S		 1560 return true;
1561}
1562
691680b8
FF		 1563static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1564{
1565 u32 gpio_mask = ah->gpio_mask;
1566 int i;
1567
1568 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1569 if (!(gpio_mask & 1))
1570 continue;
1571
1572 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1573 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1574 }
1575}
1576
01e18918
RM		 1577static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1578 int *hang_state, int *hang_pos)
1579{
1580 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1581 u32 chain_state, dcs_pos, i;
1582
1583 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1584 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1585 for (i = 0; i < 3; i++) {
1586 if (chain_state == dcu_chain_state[i]) {
1587 *hang_state = chain_state;
1588 *hang_pos = dcs_pos;
1589 return true;
1590 }
1591 }
1592 }
1593 return false;
1594}
1595
1596#define DCU_COMPLETE_STATE 1
1597#define DCU_COMPLETE_STATE_MASK 0x3
1598#define NUM_STATUS_READS 50
1599static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1600{
1601 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1602 u32 i, hang_pos, hang_state, num_state = 6;
1603
1604 comp_state = REG_READ(ah, AR_DMADBG_6);
1605
1606 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1607 ath_dbg(ath9k_hw_common(ah), RESET,
1608 "MAC Hang signature not found at DCU complete\n");
1609 return false;
1610 }
1611
1612 chain_state = REG_READ(ah, dcs_reg);
1613 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1614 goto hang_check_iter;
1615
1616 dcs_reg = AR_DMADBG_5;
1617 num_state = 4;
1618 chain_state = REG_READ(ah, dcs_reg);
1619 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1620 goto hang_check_iter;
1621
1622 ath_dbg(ath9k_hw_common(ah), RESET,
1623 "MAC Hang signature 1 not found\n");
1624 return false;
1625
1626hang_check_iter:
1627 ath_dbg(ath9k_hw_common(ah), RESET,
1628 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1629 chain_state, comp_state, hang_state, hang_pos);
1630
1631 for (i = 0; i < NUM_STATUS_READS; i++) {
1632 chain_state = REG_READ(ah, dcs_reg);
1633 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1634 comp_state = REG_READ(ah, AR_DMADBG_6);
1635
1636 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1637 DCU_COMPLETE_STATE) ||
1638 (chain_state != hang_state))
1639 return false;
1640 }
1641
1642 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1643
1644 return true;
1645}
1646
c9c99e5e 1647bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1648{
c9c99e5e
FF		 1649 int count = 50;
1650 u32 reg;
1651
01e18918
RM		 1652 if (AR_SREV_9300(ah))
1653 return !ath9k_hw_detect_mac_hang(ah);
1654
e17f83ea 1655 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1656 return true;
1657
1658 do {
1659 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1660
c9c99e5e
FF		 1661 if ((reg & 0x7E7FFFEF) == 0x00702400)
1662 continue;
1663
1664 switch (reg & 0x7E000B00) {
1665 case 0x1E000000:
1666 case 0x52000B00:
1667 case 0x18000B00:
1668 continue;
1669 default:
1670 return true;
1671 }
1672 } while (count-- > 0);
3b319aae 1673
c9c99e5e 1674 return false;
3b319aae 1675}
c9c99e5e 1676EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1677
caed6579
SM		 1678/*
1679 * Fast channel change:
1680 * (Change synthesizer based on channel freq without resetting chip)
1681 *
1682 * Don't do FCC when
1683 * - Flag is not set
1684 * - Chip is just coming out of full sleep
1685 * - Channel to be set is same as current channel
1686 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1687 */
1688static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1689{
1690 struct ath_common *common = ath9k_hw_common(ah);
1691 int ret;
1692
1693 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1694 goto fail;
1695
1696 if (ah->chip_fullsleep)
1697 goto fail;
1698
1699 if (!ah->curchan)
1700 goto fail;
1701
1702 if (chan->channel == ah->curchan->channel)
1703 goto fail;
1704
feb7bc99
FF		 1705 if ((ah->curchan->channelFlags | chan->channelFlags) &
1706 (CHANNEL_HALF | CHANNEL_QUARTER))
1707 goto fail;
1708
caed6579
SM		 1709 if ((chan->channelFlags & CHANNEL_ALL) !=
1710 (ah->curchan->channelFlags & CHANNEL_ALL))
1711 goto fail;
1712
1713 if (!ath9k_hw_check_alive(ah))
1714 goto fail;
1715
1716 /*
1717 * For AR9462, make sure that calibration data for
1718 * re-using are present.
1719 */
8a90555f
SM		 1720 if (AR_SREV_9462(ah) && (ah->caldata &&
1721 (!ah->caldata->done_txiqcal_once ||
1722 !ah->caldata->done_txclcal_once ||
1723 !ah->caldata->rtt_done)))
caed6579
SM		 1724 goto fail;
1725
1726 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1727 ah->curchan->channel, chan->channel);
1728
1729 ret = ath9k_hw_channel_change(ah, chan);
1730 if (!ret)
1731 goto fail;
1732
1733 ath9k_hw_loadnf(ah, ah->curchan);
1734 ath9k_hw_start_nfcal(ah, true);
1735
1736 if ((ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && ar9003_mci_is_ready(ah))
1737 ar9003_mci_2g5g_switch(ah, true);
1738
1739 if (AR_SREV_9271(ah))
1740 ar9002_hw_load_ani_reg(ah, chan);
1741
1742 return 0;
1743fail:
1744 return -EINVAL;
1745}
1746
cbe61d8a 1747int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1748 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1749{
1510718d 1750 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1751 u32 saveLedState;
f078f209
LR		 1752 u32 saveDefAntenna;
1753 u32 macStaId1;
46fe782c 1754 u64 tsf = 0;
8fe65368 1755 int i, r;
caed6579 1756 bool start_mci_reset = false;
63d32967
MSS		 1757 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1758 bool save_fullsleep = ah->chip_fullsleep;
1759
1760 if (mci) {
528e5d36
SM		 1761 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1762 if (start_mci_reset)
1763 return 0;
63d32967
MSS		 1764 }
1765
9ecdef4b 1766 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1767 return -EIO;
f078f209 1768
caed6579
SM		 1769 if (ah->curchan && !ah->chip_fullsleep)
1770 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1771
20bd2a09
FF		 1772 ah->caldata = caldata;
1773 if (caldata &&
1774 (chan->channel != caldata->channel ||
1775 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1776 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1777 /* Operating channel changed, reset channel calibration data */
1778 memset(caldata, 0, sizeof(*caldata));
1779 ath9k_init_nfcal_hist_buffer(ah, chan);
1780 }
f23fba49 1781 ah->noise = ath9k_hw_getchan_noise(ah, chan);
20bd2a09 1782
caed6579
SM		 1783 if (fastcc) {
1784 r = ath9k_hw_do_fastcc(ah, chan);
1785 if (!r)
1786 return r;
f078f209
LR		 1787 }
1788
528e5d36
SM		 1789 if (mci)
1790 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1791
f078f209
LR		 1792 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1793 if (saveDefAntenna == 0)
1794 saveDefAntenna = 1;
1795
1796 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1797
46fe782c 1798 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1799 if (AR_SREV_9100(ah) ||
1800 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1801 tsf = ath9k_hw_gettsf64(ah);
1802
f078f209
LR		 1803 saveLedState = REG_READ(ah, AR_CFG_LED) &
1804 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1805 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1806
1807 ath9k_hw_mark_phy_inactive(ah);
1808
45ef6a0b
VT		 1809 ah->paprd_table_write_done = false;
1810
05020d23 1811 /* Only required on the first reset */
d7e7d229
LR		 1812 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1813 REG_WRITE(ah,
1814 AR9271_RESET_POWER_DOWN_CONTROL,
1815 AR9271_RADIO_RF_RST);
1816 udelay(50);
1817 }
1818
f078f209 1819 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1820 ath_err(common, "Chip reset failed\n");
ae8d2858 1821 return -EINVAL;
f078f209
LR		 1822 }
1823
05020d23 1824 /* Only required on the first reset */
d7e7d229
LR		 1825 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1826 ah->htc_reset_init = false;
1827 REG_WRITE(ah,
1828 AR9271_RESET_POWER_DOWN_CONTROL,
1829 AR9271_GATE_MAC_CTL);
1830 udelay(50);
1831 }
1832
46fe782c 1833 /* Restore TSF */
f860d526 1834 if (tsf)
46fe782c
S		 1835 ath9k_hw_settsf64(ah, tsf);
1836
7a37081e 1837 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1838 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1839
e9141f71
S		 1840 if (!AR_SREV_9300_20_OR_LATER(ah))
1841 ar9002_hw_enable_async_fifo(ah);
1842
25c56eec 1843 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1844 if (r)
1845 return r;
f078f209 1846
63d32967
MSS		 1847 if (mci)
1848 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1849
f860d526
FF		 1850 /*
1851 * Some AR91xx SoC devices frequently fail to accept TSF writes
1852 * right after the chip reset. When that happens, write a new
1853 * value after the initvals have been applied, with an offset
1854 * based on measured time difference
1855 */
1856 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1857 tsf += 1500;
1858 ath9k_hw_settsf64(ah, tsf);
1859 }
1860
0ced0e17
JM		 1861 /* Setup MFP options for CCMP */
1862 if (AR_SREV_9280_20_OR_LATER(ah)) {
1863 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1864 * frames when constructing CCMP AAD. */
1865 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1866 0xc7ff);
1867 ah->sw_mgmt_crypto = false;
1868 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1869 /* Disable hardware crypto for management frames */
1870 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1871 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1872 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1873 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1874 ah->sw_mgmt_crypto = true;
1875 } else
1876 ah->sw_mgmt_crypto = true;
1877
f078f209
LR		 1878 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1879 ath9k_hw_set_delta_slope(ah, chan);
1880
8fe65368 1881 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1882 ah->eep_ops->set_board_values(ah, chan);
a7765828 1883
7d0d0df0
S		 1884 ENABLE_REGWRITE_BUFFER(ah);
1885
1510718d
LR		 1886 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1887 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1888 | macStaId1
1889 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1890 | (ah->config.
60b67f51 1891 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1892 | ah->sta_id1_defaults);
13b81559 1893 ath_hw_setbssidmask(common);
f078f209 1894 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1895 ath9k_hw_write_associd(ah);
f078f209 1896 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1897 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1898
7d0d0df0 1899 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1900
00e0003e
SM		 1901 ath9k_hw_set_operating_mode(ah, ah->opmode);
1902
8fe65368 1903 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1904 if (r)
1905 return r;
f078f209 1906
dfdac8ac
FF		 1907 ath9k_hw_set_clockrate(ah);
1908
7d0d0df0
S		 1909 ENABLE_REGWRITE_BUFFER(ah);
1910
f078f209
LR		 1911 for (i = 0; i < AR_NUM_DCU; i++)
1912 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1913
7d0d0df0 1914 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1915
2660b81a 1916 ah->intr_txqs = 0;
f4c607dc 1917 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
f078f209
LR		 1918 ath9k_hw_resettxqueue(ah, i);
1919
2660b81a 1920 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1921 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1922 ath9k_hw_init_qos(ah);
1923
2660b81a 1924 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1925 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1926
0005baf4 1927 ath9k_hw_init_global_settings(ah);
f078f209 1928
fe2b6afb
FF		 1929 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1930 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1931 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1932 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1933 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1934 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1935 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1936 }
1937
ca7a4deb 1938 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1939
1940 ath9k_hw_set_dma(ah);
1941
1942 REG_WRITE(ah, AR_OBS, 8);
1943
0ce024cb 1944 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1945 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1946 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1947 }
1948
7f62a136
VT		 1949 if (ah->config.tx_intr_mitigation) {
1950 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1951 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1952 }
1953
f078f209
LR		 1954 ath9k_hw_init_bb(ah, chan);
1955
77a5a664 1956 if (caldata) {
5f0c04ea 1957 caldata->done_txiqcal_once = false;
77a5a664
RM		 1958 caldata->done_txclcal_once = false;
1959 }
ae8d2858 1960 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1961 return -EIO;
f078f209 1962
93348928
RM		 1963 ath9k_hw_loadnf(ah, chan);
1964 ath9k_hw_start_nfcal(ah, true);
1965
528e5d36
SM		 1966 if (mci && ar9003_mci_end_reset(ah, chan, caldata))
1967 return -EIO;
63d32967 1968
7d0d0df0 1969 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1970
8fe65368 1971 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1972 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1973
7d0d0df0 1974 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1975
d7e7d229
LR		 1976 /*
1977 * For big endian systems turn on swapping for descriptors
1978 */
f078f209
LR		 1979 if (AR_SREV_9100(ah)) {
1980 u32 mask;
1981 mask = REG_READ(ah, AR_CFG);
1982 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
d2182b69
JP		 1983 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1984 mask);
f078f209
LR		 1985 } else {
1986 mask =
1987 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1988 REG_WRITE(ah, AR_CFG, mask);
d2182b69
JP		 1989 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1990 REG_READ(ah, AR_CFG));
f078f209
LR		 1991 }
1992 } else {
cbba8cd1
S		 1993 if (common->bus_ops->ath_bus_type == ATH_USB) {
1994 /* Configure AR9271 target WLAN */
1995 if (AR_SREV_9271(ah))
1996 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1997 else
1998 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1999 }
f078f209 2000#ifdef __BIG_ENDIAN
4033bdad 2001 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
2be7bfe0
VT		 2002 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
2003 else
d7e7d229 2004 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 2005#endif
2006 }
2007
dbccdd1d 2008 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 2009 ath9k_hw_btcoex_enable(ah);
2010
528e5d36
SM		 2011 if (mci)
2012 ar9003_mci_check_bt(ah);
63d32967 2013
51ac8cbb 2014 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 2015 ar9003_hw_bb_watchdog_config(ah);
d8903a53 2016
51ac8cbb
RM		 2017 ar9003_hw_disable_phy_restart(ah);
2018 }
2019
691680b8
FF		 2020 ath9k_hw_apply_gpio_override(ah);
2021
ae8d2858 2022 return 0;
f078f209 2023}
7322fd19 2024EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2025
f1dc5600
S		 2026/******************************/
2027/* Power Management (Chipset) */
2028/******************************/
2029
42d5bc3f
LR		 2030/*
2031 * Notify Power Mgt is disabled in self-generated frames.
2032 * If requested, force chip to sleep.
2033 */
cbe61d8a 2034static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2035{
f1dc5600
S		 2036 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2037 if (setChip) {
423e38e8 2038 if (AR_SREV_9462(ah)) {
2577c6e8
SB		 2039 REG_WRITE(ah, AR_TIMER_MODE,
2040 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
2041 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
2042 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
2043 REG_WRITE(ah, AR_SLP32_INC,
2044 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
2045 /* xxx Required for WLAN only case ? */
2046 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2047 udelay(100);
2048 }
2049
42d5bc3f
LR		 2050 /*
2051 * Clear the RTC force wake bit to allow the
2052 * mac to go to sleep.
2053 */
2577c6e8
SB		 2054 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2055
423e38e8 2056 if (AR_SREV_9462(ah))
2577c6e8
SB		 2057 udelay(100);
2058
42d5bc3f 2059 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 2060 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2061
42d5bc3f 2062 /* Shutdown chip. Active low */
c91ec465 2063 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2577c6e8
SB		 2064 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2065 udelay(2);
2066 }
f1dc5600 2067 }
9a658d2b
LR		 2068
2069 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2070 if (AR_SREV_9300_20_OR_LATER(ah))
2071 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2072}
2073
bbd79af5
LR		 2074/*
2075 * Notify Power Management is enabled in self-generating
2076 * frames. If request, set power mode of chip to
2077 * auto/normal. Duration in units of 128us (1/8 TU).
2078 */
cbe61d8a 2079static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2080{
2577c6e8
SB		 2081 u32 val;
2082
f1dc5600
S		 2083 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2084 if (setChip) {
2660b81a 2085 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2086
f1dc5600 2087 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 2088 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 2089 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2090 AR_RTC_FORCE_WAKE_ON_INT);
2091 } else {
2577c6e8
SB		 2092
2093 /* When chip goes into network sleep, it could be waken
2094 * up by MCI_INT interrupt caused by BT's HW messages
2095 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2096 * rate (~100us). This will cause chip to leave and
2097 * re-enter network sleep mode frequently, which in
2098 * consequence will have WLAN MCI HW to generate lots of
2099 * SYS_WAKING and SYS_SLEEPING messages which will make
2100 * BT CPU to busy to process.
2101 */
423e38e8 2102 if (AR_SREV_9462(ah)) {
2577c6e8
SB		 2103 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
2104 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
2105 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
2106 }
bbd79af5
LR		 2107 /*
2108 * Clear the RTC force wake bit to allow the
2109 * mac to go to sleep.
2110 */
f1dc5600
S		 2111 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2112 AR_RTC_FORCE_WAKE_EN);
2577c6e8 2113
423e38e8 2114 if (AR_SREV_9462(ah))
2577c6e8 2115 udelay(30);
f078f209 2116 }
f078f209 2117 }
9a658d2b
LR		 2118
2119 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2120 if (AR_SREV_9300_20_OR_LATER(ah))
2121 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2122}
2123
cbe61d8a 2124static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2125{
f1dc5600
S		 2126 u32 val;
2127 int i;
f078f209 2128
9a658d2b
LR		 2129 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2130 if (AR_SREV_9300_20_OR_LATER(ah)) {
2131 REG_WRITE(ah, AR_WA, ah->WARegVal);
2132 udelay(10);
2133 }
2134
f1dc5600
S		 2135 if (setChip) {
2136 if ((REG_READ(ah, AR_RTC_STATUS) &
2137 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
23677ce3 2138 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
f1dc5600
S		 2139 return false;
2140 }
e041228f
LR		 2141 if (!AR_SREV_9300_20_OR_LATER(ah))
2142 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 2143 }
2144 if (AR_SREV_9100(ah))
2145 REG_SET_BIT(ah, AR_RTC_RESET,
2146 AR_RTC_RESET_EN);
f078f209 2147
f1dc5600
S		 2148 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2149 AR_RTC_FORCE_WAKE_EN);
2150 udelay(50);
f078f209 2151
f1dc5600
S		 2152 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2153 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2154 if (val == AR_RTC_STATUS_ON)
2155 break;
2156 udelay(50);
2157 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2158 AR_RTC_FORCE_WAKE_EN);
f078f209 2159 }
f1dc5600 2160 if (i == 0) {
3800276a
JP		 2161 ath_err(ath9k_hw_common(ah),
2162 "Failed to wakeup in %uus\n",
2163 POWER_UP_TIME / 20);
f1dc5600 2164 return false;
f078f209 2165 }
f078f209
LR		 2166 }
2167
f1dc5600 2168 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2169
f1dc5600 2170 return true;
f078f209
LR		 2171}
2172
9ecdef4b 2173bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2174{
c46917bb 2175 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 2176 int status = true, setChip = true;
f1dc5600
S		 2177 static const char *modes[] = {
2178 "AWAKE",
2179 "FULL-SLEEP",
2180 "NETWORK SLEEP",
2181 "UNDEFINED"
2182 };
f1dc5600 2183
cbdec975
GJ		 2184 if (ah->power_mode == mode)
2185 return status;
2186
d2182b69 2187 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2188 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2189
2190 switch (mode) {
2191 case ATH9K_PM_AWAKE:
2192 status = ath9k_hw_set_power_awake(ah, setChip);
1010911e
MSS		 2193
2194 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2195 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2196
f1dc5600
S		 2197 break;
2198 case ATH9K_PM_FULL_SLEEP:
d1ca8b8e
SM		 2199 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2200 ar9003_mci_set_full_sleep(ah);
1010911e 2201
f1dc5600 2202 ath9k_set_power_sleep(ah, setChip);
2660b81a 2203 ah->chip_fullsleep = true;
f1dc5600
S		 2204 break;
2205 case ATH9K_PM_NETWORK_SLEEP:
1010911e
MSS		 2206
2207 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2208 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2209
f1dc5600
S		 2210 ath9k_set_power_network_sleep(ah, setChip);
2211 break;
f078f209 2212 default:
3800276a 2213 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2214 return false;
2215 }
2660b81a 2216 ah->power_mode = mode;
f1dc5600 2217
69f4aab1
LR		 2218 /*
2219 * XXX: If this warning never comes up after a while then
2220 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2221 * ath9k_hw_setpower() return type void.
2222 */
97dcec57
SM		 2223
2224 if (!(ah->ah_flags & AH_UNPLUGGED))
2225 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2226
f1dc5600 2227 return status;
f078f209 2228}
7322fd19 2229EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2230
f1dc5600
S		 2231/*******************/
2232/* Beacon Handling */
2233/*******************/
2234
cbe61d8a 2235void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2236{
f078f209
LR		 2237 int flags = 0;
2238
7d0d0df0
S		 2239 ENABLE_REGWRITE_BUFFER(ah);
2240
2660b81a 2241 switch (ah->opmode) {
d97809db 2242 case NL80211_IFTYPE_ADHOC:
9cb5412b 2243 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 2244 REG_SET_BIT(ah, AR_TXCFG,
2245 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
dd347f2f
FF		 2246 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2247 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
f078f209 2248 flags |= AR_NDP_TIMER_EN;
d97809db 2249 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2250 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2251 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2252 TU_TO_USEC(ah->config.dma_beacon_response_time));
2253 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2254 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2255 flags |=
2256 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2257 break;
d97809db 2258 default:
d2182b69
JP		 2259 ath_dbg(ath9k_hw_common(ah), BEACON,
2260 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2261 return;
2262 break;
f078f209
LR		 2263 }
2264
dd347f2f
FF		 2265 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2266 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2267 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2268 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
f078f209 2269
7d0d0df0 2270 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2271
f078f209
LR		 2272 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2273}
7322fd19 2274EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2275
cbe61d8a 2276void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2277 const struct ath9k_beacon_state *bs)
f078f209
LR		 2278{
2279 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2280 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2281 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2282
7d0d0df0
S		 2283 ENABLE_REGWRITE_BUFFER(ah);
2284
f078f209
LR		 2285 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2286
2287 REG_WRITE(ah, AR_BEACON_PERIOD,
f29f5c08 2288 TU_TO_USEC(bs->bs_intval));
f078f209 2289 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
f29f5c08 2290 TU_TO_USEC(bs->bs_intval));
f078f209 2291
7d0d0df0 2292 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2293
f078f209
LR		 2294 REG_RMW_FIELD(ah, AR_RSSI_THR,
2295 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2296
f29f5c08 2297 beaconintval = bs->bs_intval;
f078f209
LR		 2298
2299 if (bs->bs_sleepduration > beaconintval)
2300 beaconintval = bs->bs_sleepduration;
2301
2302 dtimperiod = bs->bs_dtimperiod;
2303 if (bs->bs_sleepduration > dtimperiod)
2304 dtimperiod = bs->bs_sleepduration;
2305
2306 if (beaconintval == dtimperiod)
2307 nextTbtt = bs->bs_nextdtim;
2308 else
2309 nextTbtt = bs->bs_nexttbtt;
2310
d2182b69
JP		 2311 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2312 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2313 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2314 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2315
7d0d0df0
S		 2316 ENABLE_REGWRITE_BUFFER(ah);
2317
f1dc5600
S		 2318 REG_WRITE(ah, AR_NEXT_DTIM,
2319 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2320 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 2321
f1dc5600
S		 2322 REG_WRITE(ah, AR_SLEEP1,
2323 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2324 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2325
f1dc5600
S		 2326 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2327 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2328 else
2329 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2330
f1dc5600
S		 2331 REG_WRITE(ah, AR_SLEEP2,
2332 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2333
f1dc5600
S		 2334 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2335 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2336
7d0d0df0 2337 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2338
f1dc5600
S		 2339 REG_SET_BIT(ah, AR_TIMER_MODE,
2340 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2341 AR_DTIM_TIMER_EN);
f078f209 2342
4af9cf4f
S		 2343 /* TSF Out of Range Threshold */
2344 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2345}
7322fd19 2346EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2347
f1dc5600
S		 2348/*******************/
2349/* HW Capabilities */
2350/*******************/
2351
6054069a
FF		 2352static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2353{
2354 eeprom_chainmask &= chip_chainmask;
2355 if (eeprom_chainmask)
2356 return eeprom_chainmask;
2357 else
2358 return chip_chainmask;
2359}
2360
9a66af33
ZK		 2361/**
2362 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2363 * @ah: the atheros hardware data structure
2364 *
2365 * We enable DFS support upstream on chipsets which have passed a series
2366 * of tests. The testing requirements are going to be documented. Desired
2367 * test requirements are documented at:
2368 *
2369 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2370 *
2371 * Once a new chipset gets properly tested an individual commit can be used
2372 * to document the testing for DFS for that chipset.
2373 */
2374static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2375{
2376
2377 switch (ah->hw_version.macVersion) {
2378 /* AR9580 will likely be our first target to get testing on */
2379 case AR_SREV_VERSION_9580:
2380 default:
2381 return false;
2382 }
2383}
2384
a9a29ce6 2385int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2386{
2660b81a 2387 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2388 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2389 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2390 unsigned int chip_chainmask;
608b88cb 2391
0ff2b5c0 2392 u16 eeval;
47c80de6 2393 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2394
f74df6fb 2395 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2396 regulatory->current_rd = eeval;
f078f209 2397
2660b81a 2398 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2399 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2400 if (regulatory->current_rd == 0x64 ||
2401 regulatory->current_rd == 0x65)
2402 regulatory->current_rd += 5;
2403 else if (regulatory->current_rd == 0x41)
2404 regulatory->current_rd = 0x43;
d2182b69
JP		 2405 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2406 regulatory->current_rd);
f1dc5600 2407 }
f078f209 2408
f74df6fb 2409 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2410 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2411 ath_err(common,
2412 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2413 return -EINVAL;
2414 }
2415
d4659912
FF		 2416 if (eeval & AR5416_OPFLAGS_11A)
2417 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2418
d4659912
FF		 2419 if (eeval & AR5416_OPFLAGS_11G)
2420 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2421
6054069a
FF		 2422 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2423 chip_chainmask = 1;
ba5736a5
MSS		 2424 else if (AR_SREV_9462(ah))
2425 chip_chainmask = 3;
6054069a
FF		 2426 else if (!AR_SREV_9280_20_OR_LATER(ah))
2427 chip_chainmask = 7;
2428 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2429 chip_chainmask = 3;
2430 else
2431 chip_chainmask = 7;
2432
f74df6fb 2433 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2434 /*
2435 * For AR9271 we will temporarilly uses the rx chainmax as read from
2436 * the EEPROM.
2437 */
8147f5de 2438 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2439 !(eeval & AR5416_OPFLAGS_11A) &&
2440 !(AR_SREV_9271(ah)))
2441 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2442 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2443 else if (AR_SREV_9100(ah))
2444 pCap->rx_chainmask = 0x7;
8147f5de 2445 else
d7e7d229 2446 /* Use rx_chainmask from EEPROM. */
8147f5de 2447 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2448
6054069a
FF		 2449 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2450 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2451 ah->txchainmask = pCap->tx_chainmask;
2452 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2453
7a37081e 2454 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2455
02d2ebb2
FF		 2456 /* enable key search for every frame in an aggregate */
2457 if (AR_SREV_9300_20_OR_LATER(ah))
2458 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2459
ce2220d1
BR		 2460 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2461
0db156e9 2462 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2463 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2464 else
2465 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2466
5b5fa355
S		 2467 if (AR_SREV_9271(ah))
2468 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2469 else if (AR_DEVID_7010(ah))
2470 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2471 else if (AR_SREV_9300_20_OR_LATER(ah))
2472 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2473 else if (AR_SREV_9287_11_OR_LATER(ah))
2474 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2475 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2476 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2477 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2478 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2479 else
2480 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2481
1b2538b2 2482 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2483 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2484 else
f1dc5600 2485 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2486
e97275cb 2487#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2488 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2489 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2490 ah->rfkill_gpio =
2491 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2492 ah->rfkill_polarity =
2493 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2494
2495 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2496 }
f1dc5600 2497#endif
d5d1154f 2498 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2499 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2500 else
2501 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2502
e7594072 2503 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2504 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2505 else
2506 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2507
ceb26445 2508 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2509 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
0e707a94 2510 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
784ad503
VT		 2511 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2512
ceb26445
VT		 2513 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2514 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2515 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2516 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2517 pCap->txs_len = sizeof(struct ar9003_txs);
6f481010
LR		 2518 if (!ah->config.paprd_disable &&
2519 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
4935250a 2520 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 2521 } else {
2522 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2523 if (AR_SREV_9280_20(ah))
6b42e8d0 2524 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2525 }
1adf02ff 2526
6c84ce08
VT		 2527 if (AR_SREV_9300_20_OR_LATER(ah))
2528 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2529
6ee63f55
SB		 2530 if (AR_SREV_9300_20_OR_LATER(ah))
2531 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2532
a42acef0 2533 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2534 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2535
754dc536
VT		 2536 if (AR_SREV_9285(ah))
2537 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2538 ant_div_ctl1 =
2539 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2540 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2541 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2542 }
ea066d5a
MSS		 2543 if (AR_SREV_9300_20_OR_LATER(ah)) {
2544 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2545 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2546 }
2547
2548
431da56a 2549 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
21d2c63a
MSS		 2550 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2551 /*
2552 * enable the diversity-combining algorithm only when
2553 * both enable_lna_div and enable_fast_div are set
2554 * Table for Diversity
2555 * ant_div_alt_lnaconf bit 0-1
2556 * ant_div_main_lnaconf bit 2-3
2557 * ant_div_alt_gaintb bit 4
2558 * ant_div_main_gaintb bit 5
2559 * enable_ant_div_lnadiv bit 6
2560 * enable_ant_fast_div bit 7
2561 */
2562 if ((ant_div_ctl1 >> 0x6) == 0x3)
2563 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2564 }
754dc536 2565
8060e169
VT		 2566 if (AR_SREV_9485_10(ah)) {
2567 pCap->pcie_lcr_extsync_en = true;
2568 pCap->pcie_lcr_offset = 0x80;
2569 }
2570
9a66af33
ZK		 2571 if (ath9k_hw_dfs_tested(ah))
2572 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2573
47c80de6
VT		 2574 tx_chainmask = pCap->tx_chainmask;
2575 rx_chainmask = pCap->rx_chainmask;
2576 while (tx_chainmask || rx_chainmask) {
2577 if (tx_chainmask & BIT(0))
2578 pCap->max_txchains++;
2579 if (rx_chainmask & BIT(0))
2580 pCap->max_rxchains++;
2581
2582 tx_chainmask >>= 1;
2583 rx_chainmask >>= 1;
2584 }
2585
8ad74c4d
RM		 2586 if (AR_SREV_9300_20_OR_LATER(ah)) {
2587 ah->enabled_cals |= TX_IQ_CAL;
6fea593d 2588 if (AR_SREV_9485_OR_LATER(ah))
8ad74c4d
RM		 2589 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2590 }
3789d59c
MSS		 2591
2592 if (AR_SREV_9462(ah)) {
2593
2594 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2595 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2596
2597 if (AR_SREV_9462_20(ah))
2598 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2599
2600 }
2601
324c74ad 2602
a9a29ce6 2603 return 0;
f078f209
LR		 2604}
2605
f1dc5600
S		 2606/****************************/
2607/* GPIO / RFKILL / Antennae */
2608/****************************/
f078f209 2609
cbe61d8a 2610static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2611 u32 gpio, u32 type)
2612{
2613 int addr;
2614 u32 gpio_shift, tmp;
f078f209 2615
f1dc5600
S		 2616 if (gpio > 11)
2617 addr = AR_GPIO_OUTPUT_MUX3;
2618 else if (gpio > 5)
2619 addr = AR_GPIO_OUTPUT_MUX2;
2620 else
2621 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2622
f1dc5600 2623 gpio_shift = (gpio % 6) * 5;
f078f209 2624
f1dc5600
S		 2625 if (AR_SREV_9280_20_OR_LATER(ah)
2626 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2627 REG_RMW(ah, addr, (type << gpio_shift),
2628 (0x1f << gpio_shift));
f078f209 2629 } else {
f1dc5600
S		 2630 tmp = REG_READ(ah, addr);
2631 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2632 tmp &= ~(0x1f << gpio_shift);
2633 tmp |= (type << gpio_shift);
2634 REG_WRITE(ah, addr, tmp);
f078f209 2635 }
f078f209
LR		 2636}
2637
cbe61d8a 2638void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2639{
f1dc5600 2640 u32 gpio_shift;
f078f209 2641
9680e8a3 2642 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2643
88c1f4f6
S		 2644 if (AR_DEVID_7010(ah)) {
2645 gpio_shift = gpio;
2646 REG_RMW(ah, AR7010_GPIO_OE,
2647 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2648 (AR7010_GPIO_OE_MASK << gpio_shift));
2649 return;
2650 }
f078f209 2651
88c1f4f6 2652 gpio_shift = gpio << 1;
f1dc5600
S		 2653 REG_RMW(ah,
2654 AR_GPIO_OE_OUT,
2655 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2656 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2657}
7322fd19 2658EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2659
cbe61d8a 2660u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2661{
cb33c412
SB		 2662#define MS_REG_READ(x, y) \
2663 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2664
2660b81a 2665 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2666 return 0xffffffff;
f078f209 2667
88c1f4f6
S		 2668 if (AR_DEVID_7010(ah)) {
2669 u32 val;
2670 val = REG_READ(ah, AR7010_GPIO_IN);
2671 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2672 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2673 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2674 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2675 else if (AR_SREV_9271(ah))
5b5fa355 2676 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2677 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2678 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2679 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2680 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2681 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2682 return MS_REG_READ(AR928X, gpio) != 0;
2683 else
2684 return MS_REG_READ(AR, gpio) != 0;
f078f209 2685}
7322fd19 2686EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2687
cbe61d8a 2688void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2689 u32 ah_signal_type)
f078f209 2690{
f1dc5600 2691 u32 gpio_shift;
f078f209 2692
88c1f4f6
S		 2693 if (AR_DEVID_7010(ah)) {
2694 gpio_shift = gpio;
2695 REG_RMW(ah, AR7010_GPIO_OE,
2696 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2697 (AR7010_GPIO_OE_MASK << gpio_shift));
2698 return;
2699 }
f078f209 2700
88c1f4f6 2701 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2702 gpio_shift = 2 * gpio;
f1dc5600
S		 2703 REG_RMW(ah,
2704 AR_GPIO_OE_OUT,
2705 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2706 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2707}
7322fd19 2708EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2709
cbe61d8a 2710void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2711{
88c1f4f6
S		 2712 if (AR_DEVID_7010(ah)) {
2713 val = val ? 0 : 1;
2714 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2715 AR_GPIO_BIT(gpio));
2716 return;
2717 }
2718
5b5fa355
S		 2719 if (AR_SREV_9271(ah))
2720 val = ~val;
2721
f1dc5600
S		 2722 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2723 AR_GPIO_BIT(gpio));
f078f209 2724}
7322fd19 2725EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2726
cbe61d8a 2727void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2728{
f1dc5600 2729 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2730}
7322fd19 2731EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2732
f1dc5600
S		 2733/*********************/
2734/* General Operation */
2735/*********************/
2736
cbe61d8a 2737u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2738{
f1dc5600
S		 2739 u32 bits = REG_READ(ah, AR_RX_FILTER);
2740 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2741
f1dc5600
S		 2742 if (phybits & AR_PHY_ERR_RADAR)
2743 bits |= ATH9K_RX_FILTER_PHYRADAR;
2744 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2745 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2746
f1dc5600 2747 return bits;
f078f209 2748}
7322fd19 2749EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2750
cbe61d8a 2751void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2752{
f1dc5600 2753 u32 phybits;
f078f209 2754
7d0d0df0
S		 2755 ENABLE_REGWRITE_BUFFER(ah);
2756
423e38e8 2757 if (AR_SREV_9462(ah))
2577c6e8
SB		 2758 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2759
7ea310be
S		 2760 REG_WRITE(ah, AR_RX_FILTER, bits);
2761
f1dc5600
S		 2762 phybits = 0;
2763 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2764 phybits |= AR_PHY_ERR_RADAR;
2765 if (bits & ATH9K_RX_FILTER_PHYERR)
2766 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2767 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2768
f1dc5600 2769 if (phybits)
ca7a4deb 2770 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2771 else
ca7a4deb 2772 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2773
2774 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2775}
7322fd19 2776EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2777
cbe61d8a 2778bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2779{
63a75b91
SB		 2780 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2781 return false;
2782
2783 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2784 ah->htc_reset_init = true;
63a75b91 2785 return true;
f1dc5600 2786}
7322fd19 2787EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2788
cbe61d8a 2789bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2790{
9ecdef4b 2791 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2792 return false;
f078f209 2793
63a75b91
SB		 2794 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2795 return false;
2796
2797 ath9k_hw_init_pll(ah, NULL);
2798 return true;
f078f209 2799}
7322fd19 2800EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2801
ca2c68cc
FF		 2802static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2803{
2804 enum eeprom_param gain_param;
2805
2806 if (IS_CHAN_2GHZ(chan))
2807 gain_param = EEP_ANTENNA_GAIN_2G;
2808 else
2809 gain_param = EEP_ANTENNA_GAIN_5G;
2810
2811 return ah->eep_ops->get_eeprom(ah, gain_param);
2812}
2813
64ea57d0
GJ		 2814void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2815 bool test)
ca2c68cc
FF		 2816{
2817 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2818 struct ieee80211_channel *channel;
2819 int chan_pwr, new_pwr, max_gain;
2820 int ant_gain, ant_reduction = 0;
2821
2822 if (!chan)
2823 return;
2824
2825 channel = chan->chan;
2826 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2827 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2828 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2829
2830 ant_gain = get_antenna_gain(ah, chan);
2831 if (ant_gain > max_gain)
2832 ant_reduction = ant_gain - max_gain;
2833
2834 ah->eep_ops->set_txpower(ah, chan,
2835 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2836 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2837}
2838
de40f316 2839void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2840{
ca2c68cc 2841 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2842 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2843 struct ieee80211_channel *channel = chan->chan;
9c204b46 2844
48ef5c42 2845 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2846 if (test)
ca2c68cc 2847 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2848
64ea57d0 2849 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2850
ca2c68cc
FF		 2851 if (test)
2852 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2853}
7322fd19 2854EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2855
cbe61d8a 2856void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2857{
2660b81a 2858 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2859}
7322fd19 2860EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2861
cbe61d8a 2862void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2863{
f1dc5600
S		 2864 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2865 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2866}
7322fd19 2867EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2868
f2b2143e 2869void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2870{
1510718d
LR		 2871 struct ath_common *common = ath9k_hw_common(ah);
2872
2873 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2874 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2875 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2876}
7322fd19 2877EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2878
1c0fc65e
BP		 2879#define ATH9K_MAX_TSF_READ 10
2880
cbe61d8a 2881u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2882{
1c0fc65e
BP		 2883 u32 tsf_lower, tsf_upper1, tsf_upper2;
2884 int i;
2885
2886 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2887 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2888 tsf_lower = REG_READ(ah, AR_TSF_L32);
2889 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2890 if (tsf_upper2 == tsf_upper1)
2891 break;
2892 tsf_upper1 = tsf_upper2;
2893 }
f078f209 2894
1c0fc65e 2895 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2896
1c0fc65e 2897 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2898}
7322fd19 2899EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2900
cbe61d8a 2901void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2902{
27abe060 2903 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2904 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2905}
7322fd19 2906EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2907
cbe61d8a 2908void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2909{
f9b604f6
GJ		 2910 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2911 AH_TSF_WRITE_TIMEOUT))
d2182b69 2912 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2913 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2914
f1dc5600
S		 2915 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2916}
7322fd19 2917EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2918
54e4cec6 2919void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2920{
f1dc5600 2921 if (setting)
2660b81a 2922 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2923 else
2660b81a 2924 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2925}
7322fd19 2926EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2927
25c56eec 2928void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2929{
25c56eec 2930 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2931 u32 macmode;
2932
25c56eec 2933 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2934 macmode = AR_2040_JOINED_RX_CLEAR;
2935 else
2936 macmode = 0;
f078f209 2937
f1dc5600 2938 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2939}
ff155a45
VT		 2940
2941/* HW Generic timers configuration */
2942
2943static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2944{
2945 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2946 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2947 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2948 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2949 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2950 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2951 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2952 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2953 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2954 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2955 AR_NDP2_TIMER_MODE, 0x0002},
2956 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2957 AR_NDP2_TIMER_MODE, 0x0004},
2958 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2959 AR_NDP2_TIMER_MODE, 0x0008},
2960 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2961 AR_NDP2_TIMER_MODE, 0x0010},
2962 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2963 AR_NDP2_TIMER_MODE, 0x0020},
2964 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2965 AR_NDP2_TIMER_MODE, 0x0040},
2966 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2967 AR_NDP2_TIMER_MODE, 0x0080}
2968};
2969
2970/* HW generic timer primitives */
2971
2972/* compute and clear index of rightmost 1 */
2973static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2974{
2975 u32 b;
2976
2977 b = *mask;
2978 b &= (0-b);
2979 *mask &= ~b;
2980 b *= debruijn32;
2981 b >>= 27;
2982
2983 return timer_table->gen_timer_index[b];
2984}
2985
dd347f2f 2986u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2987{
2988 return REG_READ(ah, AR_TSF_L32);
2989}
dd347f2f 2990EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2991
2992struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2993 void (*trigger)(void *),
2994 void (*overflow)(void *),
2995 void *arg,
2996 u8 timer_index)
2997{
2998 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2999 struct ath_gen_timer *timer;
3000
3001 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3002
3003 if (timer == NULL) {
3800276a
JP		 3004 ath_err(ath9k_hw_common(ah),
3005 "Failed to allocate memory for hw timer[%d]\n",
3006 timer_index);
ff155a45
VT		 3007 return NULL;
3008 }
3009
3010 /* allocate a hardware generic timer slot */
3011 timer_table->timers[timer_index] = timer;
3012 timer->index = timer_index;
3013 timer->trigger = trigger;
3014 timer->overflow = overflow;
3015 timer->arg = arg;
3016
3017 return timer;
3018}
7322fd19 3019EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3020
cd9bf689
LR		 3021void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3022 struct ath_gen_timer *timer,
788f6875 3023 u32 trig_timeout,
cd9bf689 3024 u32 timer_period)
ff155a45
VT		 3025{
3026 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
788f6875 3027 u32 tsf, timer_next;
ff155a45
VT		 3028
3029 BUG_ON(!timer_period);
3030
3031 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3032
3033 tsf = ath9k_hw_gettsf32(ah);
3034
788f6875
VT		 3035 timer_next = tsf + trig_timeout;
3036
d2182b69 3037 ath_dbg(ath9k_hw_common(ah), HWTIMER,
226afe68
JP		 3038 "current tsf %x period %x timer_next %x\n",
3039 tsf, timer_period, timer_next);
ff155a45 3040
ff155a45
VT		 3041 /*
3042 * Program generic timer registers
3043 */
3044 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3045 timer_next);
3046 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3047 timer_period);
3048 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3049 gen_tmr_configuration[timer->index].mode_mask);
3050
423e38e8 3051 if (AR_SREV_9462(ah)) {
2577c6e8 3052 /*
423e38e8 3053 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3054 * to use. But we still follow the old rule, 0 - 7 use tsf and
3055 * 8 - 15 use tsf2.
3056 */
3057 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3058 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3059 (1 << timer->index));
3060 else
3061 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3062 (1 << timer->index));
3063 }
3064
ff155a45
VT		 3065 /* Enable both trigger and thresh interrupt masks */
3066 REG_SET_BIT(ah, AR_IMR_S5,
3067 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3068 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 3069}
7322fd19 3070EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3071
cd9bf689 3072void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3073{
3074 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3075
3076 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3077 (timer->index >= ATH_MAX_GEN_TIMER)) {
3078 return;
3079 }
3080
3081 /* Clear generic timer enable bits. */
3082 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3083 gen_tmr_configuration[timer->index].mode_mask);
3084
3085 /* Disable both trigger and thresh interrupt masks */
3086 REG_CLR_BIT(ah, AR_IMR_S5,
3087 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3088 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3089
3090 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3091}
7322fd19 3092EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3093
3094void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3095{
3096 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3097
3098 /* free the hardware generic timer slot */
3099 timer_table->timers[timer->index] = NULL;
3100 kfree(timer);
3101}
7322fd19 3102EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3103
3104/*
3105 * Generic Timer Interrupts handling
3106 */
3107void ath_gen_timer_isr(struct ath_hw *ah)
3108{
3109 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3110 struct ath_gen_timer *timer;
c46917bb 3111 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3112 u32 trigger_mask, thresh_mask, index;
3113
3114 /* get hardware generic timer interrupt status */
3115 trigger_mask = ah->intr_gen_timer_trigger;
3116 thresh_mask = ah->intr_gen_timer_thresh;
3117 trigger_mask &= timer_table->timer_mask.val;
3118 thresh_mask &= timer_table->timer_mask.val;
3119
3120 trigger_mask &= ~thresh_mask;
3121
3122 while (thresh_mask) {
3123 index = rightmost_index(timer_table, &thresh_mask);
3124 timer = timer_table->timers[index];
3125 BUG_ON(!timer);
d2182b69
JP		 3126 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3127 index);
ff155a45
VT		 3128 timer->overflow(timer->arg);
3129 }
3130
3131 while (trigger_mask) {
3132 index = rightmost_index(timer_table, &trigger_mask);
3133 timer = timer_table->timers[index];
3134 BUG_ON(!timer);
d2182b69 3135 ath_dbg(common, HWTIMER,
226afe68 3136 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3137 timer->trigger(timer->arg);
3138 }
3139}
7322fd19 3140EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3141
05020d23
S		 3142/********/
3143/* HTC */
3144/********/
3145
2da4f01a
LR		 3146static struct {
3147 u32 version;
3148 const char * name;
3149} ath_mac_bb_names[] = {
3150 /* Devices with external radios */
3151 { AR_SREV_VERSION_5416_PCI, "5416" },
3152 { AR_SREV_VERSION_5416_PCIE, "5418" },
3153 { AR_SREV_VERSION_9100, "9100" },
3154 { AR_SREV_VERSION_9160, "9160" },
3155 /* Single-chip solutions */
3156 { AR_SREV_VERSION_9280, "9280" },
3157 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3158 { AR_SREV_VERSION_9287, "9287" },
3159 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3160 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3161 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3162 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3163 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3164 { AR_SREV_VERSION_9462, "9462" },
2da4f01a
LR		 3165};
3166
3167/* For devices with external radios */
3168static struct {
3169 u16 version;
3170 const char * name;
3171} ath_rf_names[] = {
3172 { 0, "5133" },
3173 { AR_RAD5133_SREV_MAJOR, "5133" },
3174 { AR_RAD5122_SREV_MAJOR, "5122" },
3175 { AR_RAD2133_SREV_MAJOR, "2133" },
3176 { AR_RAD2122_SREV_MAJOR, "2122" }
3177};
3178
3179/*
3180 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3181 */
f934c4d9 3182static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3183{
3184 int i;
3185
3186 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3187 if (ath_mac_bb_names[i].version == mac_bb_version) {
3188 return ath_mac_bb_names[i].name;
3189 }
3190 }
3191
3192 return "????";
3193}
2da4f01a
LR		 3194
3195/*
3196 * Return the RF name. "????" is returned if the RF is unknown.
3197 * Used for devices with external radios.
3198 */
f934c4d9 3199static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3200{
3201 int i;
3202
3203 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3204 if (ath_rf_names[i].version == rf_version) {
3205 return ath_rf_names[i].name;
3206 }
3207 }
3208
3209 return "????";
3210}
f934c4d9
LR		 3211
3212void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3213{
3214 int used;
3215
3216 /* chipsets >= AR9280 are single-chip */
7a37081e 3217 if (AR_SREV_9280_20_OR_LATER(ah)) {
f934c4d9
LR		 3218 used = snprintf(hw_name, len,
3219 "Atheros AR%s Rev:%x",
3220 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3221 ah->hw_version.macRev);
3222 }
3223 else {
3224 used = snprintf(hw_name, len,
3225 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3226 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3227 ah->hw_version.macRev,
3228 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3229 AR_RADIO_SREV_MAJOR)),
3230 ah->hw_version.phyRev);
3231 }
3232
3233 hw_name[used] = '\0';
3234}
3235EXPORT_SYMBOL(ath9k_hw_name);
Linux 6.x block layer and io_uring tree(s)