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[linux-block.git] / drivers / net / wireless / ath / ath9k / hw.c
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f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
5ca06ebe 22#include <linux/etherdevice.h>
61b559de 23#include <linux/gpio.h>
f078f209
LR		 24#include <asm/unaligned.h>
25
af03abec 26#include "hw.h"
d70357d5 27#include "hw-ops.h"
b622a720 28#include "ar9003_mac.h"
f4701b5a 29#include "ar9003_mci.h"
362cd03f 30#include "ar9003_phy.h"
462e58f2 31#include "ath9k.h"
f078f209 32
cbe61d8a 33static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 34
7322fd19
LR		 35MODULE_AUTHOR("Atheros Communications");
36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38MODULE_LICENSE("Dual BSD/GPL");
39
dfdac8ac 40static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 41{
dfdac8ac 42 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 43 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 44 unsigned int clockrate;
cbe61d8a 45
087b6ff6
FF		 46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
48 clockrate = 117;
e4744ec7 49 else if (!chan) /* should really check for CCK instead */
dfdac8ac 50 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 51 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 55 else
dfdac8ac
FF		 56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
57
beae416b
MN		 58 if (chan) {
59 if (IS_CHAN_HT40(chan))
60 clockrate *= 2;
e4744ec7 61 if (IS_CHAN_HALF_RATE(chan))
906c7205 62 clockrate /= 2;
e4744ec7 63 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 64 clockrate /= 4;
65 }
66
dfdac8ac 67 common->clockrate = clockrate;
f1dc5600
S		 68}
69
cbe61d8a 70static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 71{
dfdac8ac 72 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 73
dfdac8ac 74 return usecs * common->clockrate;
f1dc5600 75}
f078f209 76
0caa7b14 77bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 78{
79 int i;
80
0caa7b14
S		 81 BUG_ON(timeout < AH_TIME_QUANTUM);
82
83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 84 if ((REG_READ(ah, reg) & mask) == val)
85 return true;
86
87 udelay(AH_TIME_QUANTUM);
88 }
04bd4638 89
d2182b69 90 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
92 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 93
f1dc5600 94 return false;
f078f209 95}
7322fd19 96EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 97
7c5adc8d
FF		 98void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
99 int hw_delay)
100{
1a5e6326 101 hw_delay /= 10;
7c5adc8d
FF		 102
103 if (IS_CHAN_HALF_RATE(chan))
104 hw_delay *= 2;
105 else if (IS_CHAN_QUARTER_RATE(chan))
106 hw_delay *= 4;
107
108 udelay(hw_delay + BASE_ACTIVATE_DELAY);
109}
110
0166b4be 111void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 112 int column, unsigned int *writecnt)
113{
114 int r;
115
116 ENABLE_REGWRITE_BUFFER(ah);
117 for (r = 0; r < array->ia_rows; r++) {
118 REG_WRITE(ah, INI_RA(array, r, 0),
119 INI_RA(array, r, column));
120 DO_DELAY(*writecnt);
121 }
122 REGWRITE_BUFFER_FLUSH(ah);
123}
124
a57cb45a
OR		 125void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
126{
127 u32 *tmp_reg_list, *tmp_data;
128 int i;
129
6da2ec56 130 tmp_reg_list = kmalloc_array(size, sizeof(u32), GFP_KERNEL);
a57cb45a
OR		 131 if (!tmp_reg_list) {
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
133 return;
134 }
135
6da2ec56 136 tmp_data = kmalloc_array(size, sizeof(u32), GFP_KERNEL);
a57cb45a
OR		 137 if (!tmp_data) {
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
139 goto error_tmp_data;
140 }
141
142 for (i = 0; i < size; i++)
143 tmp_reg_list[i] = array[i][0];
144
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
146
147 for (i = 0; i < size; i++)
148 array[i][1] = tmp_data[i];
149
150 kfree(tmp_data);
151error_tmp_data:
152 kfree(tmp_reg_list);
153}
154
f078f209
LR		 155u32 ath9k_hw_reverse_bits(u32 val, u32 n)
156{
157 u32 retval;
158 int i;
159
160 for (i = 0, retval = 0; i < n; i++) {
161 retval = (retval << 1) | (val & 1);
162 val >>= 1;
163 }
164 return retval;
165}
166
cbe61d8a 167u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 168 u8 phy, int kbps,
f1dc5600
S		 169 u32 frameLen, u16 rateix,
170 bool shortPreamble)
f078f209 171{
f1dc5600 172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 173
f1dc5600
S		 174 if (kbps == 0)
175 return 0;
f078f209 176
545750d3 177 switch (phy) {
46d14a58 178 case WLAN_RC_PHY_CCK:
f1dc5600 179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 180 if (shortPreamble)
f1dc5600
S		 181 phyTime >>= 1;
182 numBits = frameLen << 3;
183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
184 break;
46d14a58 185 case WLAN_RC_PHY_OFDM:
2660b81a 186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
91f1ee65
WD		 187 bitsPerSymbol =
188 ((kbps >> 2) * OFDM_SYMBOL_TIME_QUARTER) / 1000;
f1dc5600
S		 189 numBits = OFDM_PLCP_BITS + (frameLen << 3);
190 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
191 txTime = OFDM_SIFS_TIME_QUARTER
192 + OFDM_PREAMBLE_TIME_QUARTER
193 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 194 } else if (ah->curchan &&
195 IS_CHAN_HALF_RATE(ah->curchan)) {
91f1ee65
WD		 196 bitsPerSymbol =
197 ((kbps >> 1) * OFDM_SYMBOL_TIME_HALF) / 1000;
f1dc5600
S		 198 numBits = OFDM_PLCP_BITS + (frameLen << 3);
199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
200 txTime = OFDM_SIFS_TIME_HALF +
201 OFDM_PREAMBLE_TIME_HALF
202 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
203 } else {
204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
205 numBits = OFDM_PLCP_BITS + (frameLen << 3);
206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
208 + (numSymbols * OFDM_SYMBOL_TIME);
209 }
210 break;
211 default:
3800276a
JP		 212 ath_err(ath9k_hw_common(ah),
213 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 214 txTime = 0;
215 break;
216 }
f078f209 217
f1dc5600
S		 218 return txTime;
219}
7322fd19 220EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 221
cbe61d8a 222void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 223 struct ath9k_channel *chan,
224 struct chan_centers *centers)
f078f209 225{
f1dc5600 226 int8_t extoff;
f078f209 227
f1dc5600
S		 228 if (!IS_CHAN_HT40(chan)) {
229 centers->ctl_center = centers->ext_center =
230 centers->synth_center = chan->channel;
231 return;
f078f209 232 }
f078f209 233
8896934c 234 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 235 centers->synth_center =
236 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
237 extoff = 1;
238 } else {
239 centers->synth_center =
240 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
241 extoff = -1;
242 }
f078f209 243
f1dc5600
S		 244 centers->ctl_center =
245 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 246 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 247 centers->ext_center =
6420014c 248 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 249}
250
f1dc5600
S		 251/******************/
252/* Chip Revisions */
253/******************/
254
cbe61d8a 255static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 256{
f1dc5600 257 u32 val;
f078f209 258
09c74f7b
FF		 259 if (ah->get_mac_revision)
260 ah->hw_version.macRev = ah->get_mac_revision();
261
ecb1d385
VT		 262 switch (ah->hw_version.devid) {
263 case AR5416_AR9100_DEVID:
264 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
265 break;
3762561a
GJ		 266 case AR9300_DEVID_AR9330:
267 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
09c74f7b 268 if (!ah->get_mac_revision) {
3762561a
GJ		 269 val = REG_READ(ah, AR_SREV);
270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
271 }
272 return;
ecb1d385
VT		 273 case AR9300_DEVID_AR9340:
274 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
ecb1d385 275 return;
813831dc
GJ		 276 case AR9300_DEVID_QCA955X:
277 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
278 return;
e6b1e46e
SM		 279 case AR9300_DEVID_AR953X:
280 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
281 return;
2131fabb
MP		 282 case AR9300_DEVID_QCA956X:
283 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
7865598e 284 return;
ecb1d385
VT		 285 }
286
f1dc5600 287 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 288
f1dc5600
S		 289 if (val == 0xFF) {
290 val = REG_READ(ah, AR_SREV);
d535a42a
S		 291 ah->hw_version.macVersion =
292 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
293 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 294
77fac465 295 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 296 ah->is_pciexpress = true;
297 else
298 ah->is_pciexpress = (val &
299 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 300 } else {
301 if (!AR_SREV_9100(ah))
d535a42a 302 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 303
d535a42a 304 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 305
d535a42a 306 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 307 ah->is_pciexpress = true;
f1dc5600 308 }
f078f209
LR		 309}
310
f1dc5600
S		 311/************************************/
312/* HW Attach, Detach, Init Routines */
313/************************************/
314
cbe61d8a 315static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 316{
040b74f7 317 if (!AR_SREV_5416(ah))
f1dc5600 318 return;
f078f209 319
f1dc5600
S		 320 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
325 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
327 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
328 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 329
f1dc5600 330 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 331}
332
1f3f0618 333/* This should work for all families including legacy */
cbe61d8a 334static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 335{
c46917bb 336 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 337 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 338 u32 regHold[2];
07b2fa5a
JP		 339 static const u32 patternData[4] = {
340 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
341 };
1f3f0618 342 int i, j, loop_max;
f078f209 343
1f3f0618
SB		 344 if (!AR_SREV_9300_20_OR_LATER(ah)) {
345 loop_max = 2;
346 regAddr[1] = AR_PHY_BASE + (8 << 2);
347 } else
348 loop_max = 1;
349
350 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 351 u32 addr = regAddr[i];
352 u32 wrData, rdData;
f078f209 353
f1dc5600
S		 354 regHold[i] = REG_READ(ah, addr);
355 for (j = 0; j < 0x100; j++) {
356 wrData = (j << 16) | j;
357 REG_WRITE(ah, addr, wrData);
358 rdData = REG_READ(ah, addr);
359 if (rdData != wrData) {
3800276a
JP		 360 ath_err(common,
361 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
362 addr, wrData, rdData);
f1dc5600
S		 363 return false;
364 }
365 }
366 for (j = 0; j < 4; j++) {
367 wrData = patternData[j];
368 REG_WRITE(ah, addr, wrData);
369 rdData = REG_READ(ah, addr);
370 if (wrData != rdData) {
3800276a
JP		 371 ath_err(common,
372 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
373 addr, wrData, rdData);
f1dc5600
S		 374 return false;
375 }
f078f209 376 }
f1dc5600 377 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 378 }
f1dc5600 379 udelay(100);
cbe61d8a 380
f078f209
LR		 381 return true;
382}
383
b8b0f377 384static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 385{
f57cf939
SM		 386 struct ath_common *common = ath9k_hw_common(ah);
387
689e756f
FF		 388 ah->config.dma_beacon_response_time = 1;
389 ah->config.sw_beacon_response_time = 6;
621a5f7a 390 ah->config.cwm_ignore_extcca = false;
2660b81a 391 ah->config.analog_shiftreg = 1;
f078f209 392
0ce024cb 393 ah->config.rx_intr_mitigation = true;
6158425b 394
a64e1a45
SM		 395 if (AR_SREV_9300_20_OR_LATER(ah)) {
396 ah->config.rimt_last = 500;
397 ah->config.rimt_first = 2000;
398 } else {
399 ah->config.rimt_last = 250;
400 ah->config.rimt_first = 700;
401 }
402
656cd75c
SM		 403 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
404 ah->config.pll_pwrsave = 7;
405
6158425b
LR		 406 /*
407 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
408 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
409 * This means we use it for all AR5416 devices, and the few
410 * minor PCI AR9280 devices out there.
411 *
412 * Serialization is required because these devices do not handle
413 * well the case of two concurrent reads/writes due to the latency
414 * involved. During one read/write another read/write can be issued
415 * on another CPU while the previous read/write may still be working
416 * on our hardware, if we hit this case the hardware poops in a loop.
417 * We prevent this by serializing reads and writes.
418 *
419 * This issue is not present on PCI-Express devices or pre-AR5416
420 * devices (legacy, 802.11abg).
421 */
422 if (num_possible_cpus() > 1)
2d6a5e95 423 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f57cf939
SM		 424
425 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
426 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
427 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
428 !ah->is_pciexpress)) {
429 ah->config.serialize_regmode = SER_REG_MODE_ON;
430 } else {
431 ah->config.serialize_regmode = SER_REG_MODE_OFF;
432 }
433 }
434
435 ath_dbg(common, RESET, "serialize_regmode is %d\n",
436 ah->config.serialize_regmode);
437
438 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
439 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
440 else
441 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
f078f209
LR		 442}
443
50aca25b 444static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 445{
608b88cb
LR		 446 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
447
448 regulatory->country_code = CTRY_DEFAULT;
449 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 450
d535a42a 451 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 452 ah->hw_version.subvendorid = 0;
f078f209 453
f57cf939
SM		 454 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
455 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 456 if (AR_SREV_9100(ah))
457 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
f57cf939 458
11b0ac2e 459 ah->slottime = 9;
2660b81a 460 ah->globaltxtimeout = (u32) -1;
cbdec975 461 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 462 ah->htc_reset_init = true;
f57cf939 463
c09396eb 464 ah->tpc_enabled = false;
a9abe302 465
f57cf939
SM		 466 ah->ani_function = ATH9K_ANI_ALL;
467 if (!AR_SREV_9300_20_OR_LATER(ah))
468 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
469
470 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
471 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
472 else
473 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209
LR		 474}
475
d323cb71 476static void ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 477{
1510718d 478 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 479 int i;
480 u16 eeval;
07b2fa5a 481 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209 482
0cefa974
MB		 483 /* MAC address may already be loaded via ath9k_platform_data */
484 if (is_valid_ether_addr(common->macaddr))
d323cb71 485 return;
0cefa974 486
f078f209 487 for (i = 0; i < 3; i++) {
49101676 488 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
1510718d
LR		 489 common->macaddr[2 * i] = eeval >> 8;
490 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 491 }
0cefa974
MB		 492
493 if (is_valid_ether_addr(common->macaddr))
d323cb71 494 return;
0cefa974
MB		 495
496 ath_err(common, "eeprom contains invalid mac address: %pM\n",
497 common->macaddr);
498
499 random_ether_addr(common->macaddr);
500 ath_err(common, "random mac address will be used: %pM\n",
501 common->macaddr);
f078f209 502
d323cb71 503 return;
f078f209
LR		 504}
505
f637cfd6 506static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 507{
6cae913d 508 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 509 int ecode;
f078f209 510
6cae913d 511 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 512 if (!ath9k_hw_chip_test(ah))
513 return -ENODEV;
514 }
f078f209 515
ebd5a14a
LR		 516 if (!AR_SREV_9300_20_OR_LATER(ah)) {
517 ecode = ar9002_hw_rf_claim(ah);
518 if (ecode != 0)
519 return ecode;
520 }
f078f209 521
f637cfd6 522 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 523 if (ecode != 0)
524 return ecode;
7d01b221 525
d2182b69 526 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 527 ah->eep_ops->get_eeprom_ver(ah),
528 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 529
e323300d 530 ath9k_hw_ani_init(ah);
f078f209 531
d3b371cb
SM		 532 /*
533 * EEPROM needs to be initialized before we do this.
534 * This is required for regulatory compliance.
535 */
0c7c2bb4 536 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 537 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
538 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 539 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
540 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 541 }
542 }
543
f078f209
LR		 544 return 0;
545}
546
c1b976d2 547static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 548{
c1b976d2
FF		 549 if (!AR_SREV_9300_20_OR_LATER(ah))
550 return ar9002_hw_attach_ops(ah);
551
552 ar9003_hw_attach_ops(ah);
553 return 0;
aa4058ae
LR		 554}
555
d70357d5
LR		 556/* Called for all hardware families */
557static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 558{
c46917bb 559 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 560 int r = 0;
aa4058ae 561
ac45c12d
SB		 562 ath9k_hw_read_revisions(ah);
563
de82582b
SM		 564 switch (ah->hw_version.macVersion) {
565 case AR_SREV_VERSION_5416_PCI:
566 case AR_SREV_VERSION_5416_PCIE:
567 case AR_SREV_VERSION_9160:
568 case AR_SREV_VERSION_9100:
569 case AR_SREV_VERSION_9280:
570 case AR_SREV_VERSION_9285:
571 case AR_SREV_VERSION_9287:
572 case AR_SREV_VERSION_9271:
573 case AR_SREV_VERSION_9300:
574 case AR_SREV_VERSION_9330:
575 case AR_SREV_VERSION_9485:
576 case AR_SREV_VERSION_9340:
577 case AR_SREV_VERSION_9462:
578 case AR_SREV_VERSION_9550:
579 case AR_SREV_VERSION_9565:
e6b1e46e 580 case AR_SREV_VERSION_9531:
2131fabb 581 case AR_SREV_VERSION_9561:
de82582b
SM		 582 break;
583 default:
584 ath_err(common,
585 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
586 ah->hw_version.macVersion, ah->hw_version.macRev);
587 return -EOPNOTSUPP;
588 }
589
0a8d7cb0
SB		 590 /*
591 * Read back AR_WA into a permanent copy and set bits 14 and 17.
592 * We need to do this to avoid RMW of this register. We cannot
593 * read the reg when chip is asleep.
594 */
27251e00
SM		 595 if (AR_SREV_9300_20_OR_LATER(ah)) {
596 ah->WARegVal = REG_READ(ah, AR_WA);
597 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
598 AR_WA_ASPM_TIMER_BASED_DISABLE);
599 }
0a8d7cb0 600
aa4058ae 601 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 602 ath_err(common, "Couldn't reset chip\n");
95fafca2 603 return -EIO;
aa4058ae
LR		 604 }
605
a4a2954f
SM		 606 if (AR_SREV_9565(ah)) {
607 ah->WARegVal |= AR_WA_BIT22;
608 REG_WRITE(ah, AR_WA, ah->WARegVal);
609 }
610
bab1f62e
LR		 611 ath9k_hw_init_defaults(ah);
612 ath9k_hw_init_config(ah);
613
c1b976d2
FF		 614 r = ath9k_hw_attach_ops(ah);
615 if (r)
616 return r;
d70357d5 617
9ecdef4b 618 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 619 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 620 return -EIO;
aa4058ae
LR		 621 }
622
2c8e5937 623 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 624 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 625 ah->is_pciexpress = false;
626
aa4058ae 627 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 628 ath9k_hw_init_cal_settings(ah);
629
69ce674b 630 if (!ah->is_pciexpress)
aa4058ae
LR		 631 ath9k_hw_disablepcie(ah);
632
f637cfd6 633 r = ath9k_hw_post_init(ah);
aa4058ae 634 if (r)
95fafca2 635 return r;
aa4058ae
LR		 636
637 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 638 r = ath9k_hw_fill_cap_info(ah);
639 if (r)
640 return r;
641
d323cb71 642 ath9k_hw_init_macaddr(ah);
4598702d 643 ath9k_hw_init_hang_checks(ah);
f078f209 644
211f5859
LR		 645 common->state = ATH_HW_INITIALIZED;
646
4f3acf81 647 return 0;
f078f209
LR		 648}
649
d70357d5 650int ath9k_hw_init(struct ath_hw *ah)
f078f209 651{
d70357d5
LR		 652 int ret;
653 struct ath_common *common = ath9k_hw_common(ah);
f078f209 654
77fac465 655 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 656 switch (ah->hw_version.devid) {
657 case AR5416_DEVID_PCI:
658 case AR5416_DEVID_PCIE:
659 case AR5416_AR9100_DEVID:
660 case AR9160_DEVID_PCI:
661 case AR9280_DEVID_PCI:
662 case AR9280_DEVID_PCIE:
663 case AR9285_DEVID_PCIE:
db3cc53a
SB		 664 case AR9287_DEVID_PCI:
665 case AR9287_DEVID_PCIE:
d70357d5 666 case AR2427_DEVID_PCIE:
db3cc53a 667 case AR9300_DEVID_PCIE:
3050c914 668 case AR9300_DEVID_AR9485_PCIE:
999a7a88 669 case AR9300_DEVID_AR9330:
bca04689 670 case AR9300_DEVID_AR9340:
2b943a33 671 case AR9300_DEVID_QCA955X:
5a63ef0f 672 case AR9300_DEVID_AR9580:
423e38e8 673 case AR9300_DEVID_AR9462:
d4e5979c 674 case AR9485_DEVID_AR1111:
77fac465 675 case AR9300_DEVID_AR9565:
e6b1e46e 676 case AR9300_DEVID_AR953X:
2131fabb 677 case AR9300_DEVID_QCA956X:
d70357d5
LR		 678 break;
679 default:
680 if (common->bus_ops->ath_bus_type == ATH_USB)
681 break;
3800276a
JP		 682 ath_err(common, "Hardware device ID 0x%04x not supported\n",
683 ah->hw_version.devid);
d70357d5
LR		 684 return -EOPNOTSUPP;
685 }
f078f209 686
d70357d5
LR		 687 ret = __ath9k_hw_init(ah);
688 if (ret) {
3800276a
JP		 689 ath_err(common,
690 "Unable to initialize hardware; initialization status: %d\n",
691 ret);
d70357d5
LR		 692 return ret;
693 }
f078f209 694
c774d57f
LB		 695 ath_dynack_init(ah);
696
d70357d5 697 return 0;
f078f209 698}
d70357d5 699EXPORT_SYMBOL(ath9k_hw_init);
f078f209 700
cbe61d8a 701static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 702{
7d0d0df0
S		 703 ENABLE_REGWRITE_BUFFER(ah);
704
f1dc5600
S		 705 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
706 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 707
f1dc5600
S		 708 REG_WRITE(ah, AR_QOS_NO_ACK,
709 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
710 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
711 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
712
713 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
714 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
715 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
716 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
717 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 718
719 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 720}
721
b84628eb 722u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 723{
f18e3c6b
MSS		 724 struct ath_common *common = ath9k_hw_common(ah);
725 int i = 0;
726
ca7a4deb
FF		 727 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
728 udelay(100);
729 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 730
f18e3c6b
MSS		 731 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
732
ca7a4deb 733 udelay(100);
b1415819 734
f18e3c6b 735 if (WARN_ON_ONCE(i >= 100)) {
714ee339 736 ath_err(common, "PLL4 measurement not done\n");
f18e3c6b
MSS		 737 break;
738 }
739
740 i++;
741 }
742
ca7a4deb 743 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 744}
745EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
746
cbe61d8a 747static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 748 struct ath9k_channel *chan)
f078f209 749{
d09b17f7
VT		 750 u32 pll;
751
5fb9b1b9
FF		 752 pll = ath9k_hw_compute_pll_control(ah, chan);
753
a4a2954f 754 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 755 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
757 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
759 AR_CH0_DPLL2_KD, 0x40);
760 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
761 AR_CH0_DPLL2_KI, 0x4);
22983c30 762
3dfd7f60
VT		 763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
764 AR_CH0_BB_DPLL1_REFDIV, 0x5);
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
766 AR_CH0_BB_DPLL1_NINI, 0x58);
767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
768 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 769
770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 771 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
773 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 775 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 776
3dfd7f60 777 /* program BB PLL phase_shift to 0x6 */
22983c30 778 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 779 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
780
781 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
782 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 783 udelay(1000);
a5415d62
GJ		 784 } else if (AR_SREV_9330(ah)) {
785 u32 ddr_dpll2, pll_control2, kd;
786
787 if (ah->is_clk_25mhz) {
788 ddr_dpll2 = 0x18e82f01;
789 pll_control2 = 0xe04a3d;
790 kd = 0x1d;
791 } else {
792 ddr_dpll2 = 0x19e82f01;
793 pll_control2 = 0x886666;
794 kd = 0x3d;
795 }
796
797 /* program DDR PLL ki and kd value */
798 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
799
800 /* program DDR PLL phase_shift */
801 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
802 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
803
5fb9b1b9
FF		 804 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
805 pll | AR_RTC_9300_PLL_BYPASS);
a5415d62
GJ		 806 udelay(1000);
807
808 /* program refdiv, nint, frac to RTC register */
809 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
810
811 /* program BB PLL kd and ki value */
812 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
814
815 /* program BB PLL phase_shift */
816 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
817 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
ede6a5e7
MP		 818 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
819 AR_SREV_9561(ah)) {
0b488ac6
VT		 820 u32 regval, pll2_divint, pll2_divfrac, refdiv;
821
5fb9b1b9
FF		 822 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
823 pll | AR_RTC_9300_SOC_PLL_BYPASS);
0b488ac6
VT		 824 udelay(1000);
825
826 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
827 udelay(100);
828
829 if (ah->is_clk_25mhz) {
ede6a5e7 830 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
2c323058
SM		 831 pll2_divint = 0x1c;
832 pll2_divfrac = 0xa3d2;
833 refdiv = 1;
834 } else {
835 pll2_divint = 0x54;
836 pll2_divfrac = 0x1eb85;
837 refdiv = 3;
838 }
0b488ac6 839 } else {
fc05a317
GJ		 840 if (AR_SREV_9340(ah)) {
841 pll2_divint = 88;
842 pll2_divfrac = 0;
843 refdiv = 5;
844 } else {
845 pll2_divint = 0x11;
ede6a5e7
MP		 846 pll2_divfrac = (AR_SREV_9531(ah) ||
847 AR_SREV_9561(ah)) ?
848 0x26665 : 0x26666;
fc05a317
GJ		 849 refdiv = 1;
850 }
0b488ac6
VT		 851 }
852
853 regval = REG_READ(ah, AR_PHY_PLL_MODE);
ede6a5e7 854 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
2c323058
SM		 855 regval |= (0x1 << 22);
856 else
857 regval |= (0x1 << 16);
0b488ac6
VT		 858 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
859 udelay(100);
860
861 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
862 (pll2_divint << 18) | pll2_divfrac);
863 udelay(100);
864
865 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317 866 if (AR_SREV_9340(ah))
2c323058
SM		 867 regval = (regval & 0x80071fff) |
868 (0x1 << 30) |
869 (0x1 << 13) |
870 (0x4 << 26) |
871 (0x18 << 19);
ede6a5e7 872 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
2c323058
SM		 873 regval = (regval & 0x01c00fff) |
874 (0x1 << 31) |
875 (0x2 << 29) |
876 (0xa << 25) |
ede6a5e7
MP		 877 (0x1 << 19);
878
879 if (AR_SREV_9531(ah))
880 regval |= (0x6 << 12);
881 } else
2c323058
SM		 882 regval = (regval & 0x80071fff) |
883 (0x3 << 30) |
884 (0x1 << 13) |
885 (0x4 << 26) |
886 (0x60 << 19);
0b488ac6 887 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
2c323058 888
ede6a5e7 889 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
2c323058
SM		 890 REG_WRITE(ah, AR_PHY_PLL_MODE,
891 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
892 else
893 REG_WRITE(ah, AR_PHY_PLL_MODE,
894 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
895
0b488ac6 896 udelay(1000);
22983c30 897 }
d09b17f7 898
8565f8bf
SM		 899 if (AR_SREV_9565(ah))
900 pll |= 0x40000;
d03a66c1 901 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 902
fc05a317
GJ		 903 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
904 AR_SREV_9550(ah))
3dfd7f60
VT		 905 udelay(1000);
906
c75724d1
LR		 907 /* Switch the core clock for ar9271 to 117Mhz */
908 if (AR_SREV_9271(ah)) {
25e2ab17
S		 909 udelay(500);
910 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 911 }
912
f1dc5600
S		 913 udelay(RTC_PLL_SETTLE_DELAY);
914
915 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 916}
917
cbe61d8a 918static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 919 enum nl80211_iftype opmode)
f078f209 920{
79d1d2b8 921 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 922 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 923 AR_IMR_TXURN |
924 AR_IMR_RXERR |
925 AR_IMR_RXORN |
926 AR_IMR_BCNMISC;
7368160f 927 u32 msi_cfg = 0;
f078f209 928
ede6a5e7
MP		 929 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
930 AR_SREV_9561(ah))
79d1d2b8
VT		 931 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
932
66860240
VT		 933 if (AR_SREV_9300_20_OR_LATER(ah)) {
934 imr_reg |= AR_IMR_RXOK_HP;
7368160f 935 if (ah->config.rx_intr_mitigation) {
66860240 936 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
7368160f
RH		 937 msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR;
938 } else {
66860240 939 imr_reg |= AR_IMR_RXOK_LP;
7368160f
RH		 940 msi_cfg |= AR_INTCFG_MSI_RXOK;
941 }
66860240 942 } else {
7368160f 943 if (ah->config.rx_intr_mitigation) {
66860240 944 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
7368160f
RH		 945 msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR;
946 } else {
66860240 947 imr_reg |= AR_IMR_RXOK;
7368160f
RH		 948 msi_cfg |= AR_INTCFG_MSI_RXOK;
949 }
66860240 950 }
f078f209 951
7368160f 952 if (ah->config.tx_intr_mitigation) {
66860240 953 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
7368160f
RH		 954 msi_cfg |= AR_INTCFG_MSI_TXINTM | AR_INTCFG_MSI_TXMINTR;
955 } else {
66860240 956 imr_reg |= AR_IMR_TXOK;
7368160f
RH		 957 msi_cfg |= AR_INTCFG_MSI_TXOK;
958 }
f078f209 959
7d0d0df0
S		 960 ENABLE_REGWRITE_BUFFER(ah);
961
152d530d 962 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 963 ah->imrs2_reg |= AR_IMR_S2_GTT;
964 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 965
7368160f
RH		 966 if (ah->msi_enabled) {
967 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI);
968 ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN;
969 ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64;
970 REG_WRITE(ah, AR_INTCFG, msi_cfg);
971 ath_dbg(ath9k_hw_common(ah), ANY,
972 "value of AR_INTCFG=0x%X, msi_cfg=0x%X\n",
973 REG_READ(ah, AR_INTCFG), msi_cfg);
974 }
975
f1dc5600
S		 976 if (!AR_SREV_9100(ah)) {
977 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 978 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 979 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
980 }
66860240 981
7d0d0df0 982 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 983
66860240
VT		 984 if (AR_SREV_9300_20_OR_LATER(ah)) {
985 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
986 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
987 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
988 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
989 }
f078f209
LR		 990}
991
b6ba41bb
FF		 992static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
993{
994 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
995 val = min(val, (u32) 0xFFFF);
996 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
997}
998
8e15e094 999void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 1000{
0005baf4
FF		 1001 u32 val = ath9k_hw_mac_to_clks(ah, us);
1002 val = min(val, (u32) 0xFFFF);
1003 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 1004}
1005
8e15e094 1006void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1007{
0005baf4
FF		 1008 u32 val = ath9k_hw_mac_to_clks(ah, us);
1009 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1010 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1011}
1012
8e15e094 1013void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
0005baf4
FF		 1014{
1015 u32 val = ath9k_hw_mac_to_clks(ah, us);
1016 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1017 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 1018}
f1dc5600 1019
cbe61d8a 1020static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1021{
f078f209 1022 if (tu > 0xFFFF) {
d2182b69
JP		 1023 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1024 tu);
2660b81a 1025 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1026 return false;
1027 } else {
1028 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1029 ah->globaltxtimeout = tu;
f078f209
LR		 1030 return true;
1031 }
1032}
1033
0005baf4 1034void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1035{
b6ba41bb 1036 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 1037 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 1038 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 1039 int slottime;
0005baf4 1040 int sifstime;
52c528ff 1041 int rx_lat = 0, tx_lat = 0, eifs = 0, ack_shift = 0;
b6ba41bb 1042 u32 reg;
0005baf4 1043
d2182b69 1044 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1045 ah->misc_mode);
f078f209 1046
b6ba41bb
FF		 1047 if (!chan)
1048 return;
1049
2660b81a 1050 if (ah->misc_mode != 0)
ca7a4deb 1051 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1052
81a91d57
RM		 1053 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1054 rx_lat = 41;
1055 else
1056 rx_lat = 37;
b6ba41bb
FF		 1057 tx_lat = 54;
1058
e88e4861
FF		 1059 if (IS_CHAN_5GHZ(chan))
1060 sifstime = 16;
1061 else
1062 sifstime = 10;
1063
b6ba41bb
FF		 1064 if (IS_CHAN_HALF_RATE(chan)) {
1065 eifs = 175;
1066 rx_lat *= 2;
1067 tx_lat *= 2;
1068 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1069 tx_lat += 11;
1070
92367fe7 1071 sifstime = 32;
e115b7ec 1072 ack_offset = 16;
52c528ff 1073 ack_shift = 3;
b6ba41bb 1074 slottime = 13;
b6ba41bb
FF		 1075 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1076 eifs = 340;
81a91d57 1077 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1078 tx_lat *= 4;
1079 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1080 tx_lat += 22;
1081
92367fe7 1082 sifstime = 64;
e115b7ec 1083 ack_offset = 32;
52c528ff 1084 ack_shift = 1;
b6ba41bb 1085 slottime = 21;
b6ba41bb 1086 } else {
a7be039d
RM		 1087 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1088 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1089 reg = AR_USEC_ASYNC_FIFO;
1090 } else {
1091 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1092 common->clockrate;
1093 reg = REG_READ(ah, AR_USEC);
1094 }
b6ba41bb
FF		 1095 rx_lat = MS(reg, AR_USEC_RX_LAT);
1096 tx_lat = MS(reg, AR_USEC_TX_LAT);
1097
1098 slottime = ah->slottime;
b6ba41bb 1099 }
0005baf4 1100
e239d859 1101 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1102 slottime += 3 * ah->coverage_class;
1103 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1104 ctstimeout = acktimeout;
42c4568a
FF		 1105
1106 /*
1107 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1108 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1109 * This was initially only meant to work around an issue with delayed
1110 * BA frames in some implementations, but it has been found to fix ACK
1111 * timeout issues in other cases as well.
1112 */
e4744ec7 1113 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1114 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1115 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1116 ctstimeout += 48 - sifstime - ah->slottime;
1117 }
1118
7aefa8aa
LB		 1119 if (ah->dynack.enabled) {
1120 acktimeout = ah->dynack.ackto;
1121 ctstimeout = acktimeout;
1122 slottime = (acktimeout - 3) / 2;
1123 } else {
1124 ah->dynack.ackto = acktimeout;
1125 }
1126
b6ba41bb
FF		 1127 ath9k_hw_set_sifs_time(ah, sifstime);
1128 ath9k_hw_setslottime(ah, slottime);
0005baf4 1129 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1130 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1131 if (ah->globaltxtimeout != (u32) -1)
1132 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1133
1134 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1135 REG_RMW(ah, AR_USEC,
1136 (common->clockrate - 1) |
1137 SM(rx_lat, AR_USEC_RX_LAT) |
1138 SM(tx_lat, AR_USEC_TX_LAT),
1139 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1140
52c528ff
WD		 1141 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
1142 REG_RMW(ah, AR_TXSIFS,
1143 sifstime | SM(ack_shift, AR_TXSIFS_ACK_SHIFT),
1144 (AR_TXSIFS_TIME | AR_TXSIFS_ACK_SHIFT));
f1dc5600 1145}
0005baf4 1146EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1147
285f2dda 1148void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1149{
211f5859
LR		 1150 struct ath_common *common = ath9k_hw_common(ah);
1151
736b3a27 1152 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1153 return;
211f5859 1154
9ecdef4b 1155 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1156}
285f2dda 1157EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1158
f1dc5600
S		 1159/*******/
1160/* INI */
1161/*******/
1162
8fe65368 1163u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1164{
1165 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1166
6b21fd20 1167 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1168 ctl |= CTL_11G;
1169 else
1170 ctl |= CTL_11A;
1171
1172 return ctl;
1173}
1174
f1dc5600
S		 1175/****************************************/
1176/* Reset and Channel Switching Routines */
1177/****************************************/
f1dc5600 1178
cbe61d8a 1179static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1180{
57b32227 1181 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1182 int txbuf_size;
f1dc5600 1183
7d0d0df0
S		 1184 ENABLE_REGWRITE_BUFFER(ah);
1185
d7e7d229
LR		 1186 /*
1187 * set AHB_MODE not to do cacheline prefetches
1188 */
ca7a4deb
FF		 1189 if (!AR_SREV_9300_20_OR_LATER(ah))
1190 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1191
d7e7d229
LR		 1192 /*
1193 * let mac dma reads be in 128 byte chunks
1194 */
ca7a4deb 1195 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1196
7d0d0df0 1197 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1198
d7e7d229
LR		 1199 /*
1200 * Restore TX Trigger Level to its pre-reset value.
1201 * The initial value depends on whether aggregation is enabled, and is
1202 * adjusted whenever underruns are detected.
1203 */
57b32227
FF		 1204 if (!AR_SREV_9300_20_OR_LATER(ah))
1205 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1206
7d0d0df0 1207 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1208
d7e7d229
LR		 1209 /*
1210 * let mac dma writes be in 128 byte chunks
1211 */
ca7a4deb 1212 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1213
d7e7d229
LR		 1214 /*
1215 * Setup receive FIFO threshold to hold off TX activities
1216 */
f1dc5600
S		 1217 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1218
57b32227
FF		 1219 if (AR_SREV_9300_20_OR_LATER(ah)) {
1220 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1221 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1222
1223 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1224 ah->caps.rx_status_len);
1225 }
1226
d7e7d229
LR		 1227 /*
1228 * reduce the number of usable entries in PCU TXBUF to avoid
1229 * wrap around issues.
1230 */
f1dc5600 1231 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1232 /* For AR9285 the number of Fifos are reduced to half.
1233 * So set the usable tx buf size also to half to
1234 * avoid data/delimiter underruns
1235 */
86c157b3
FF		 1236 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1237 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1238 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1239 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1240 } else {
1241 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1242 }
744d4025 1243
86c157b3
FF		 1244 if (!AR_SREV_9271(ah))
1245 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1246
7d0d0df0 1247 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1248
744d4025
VT		 1249 if (AR_SREV_9300_20_OR_LATER(ah))
1250 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1251}
1252
cbe61d8a 1253static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1254{
ca7a4deb
FF		 1255 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1256 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1257
7b37e0d4 1258 ENABLE_REG_RMW_BUFFER(ah);
f1dc5600 1259 switch (opmode) {
d97809db 1260 case NL80211_IFTYPE_ADHOC:
83322eb8
FF		 1261 if (!AR_SREV_9340_13(ah)) {
1262 set |= AR_STA_ID1_ADHOC;
1263 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1264 break;
1265 }
1266 /* fall through */
862a336c 1267 case NL80211_IFTYPE_OCB:
2664d666 1268 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1269 case NL80211_IFTYPE_AP:
1270 set |= AR_STA_ID1_STA_AP;
1271 /* fall through */
d97809db 1272 case NL80211_IFTYPE_STATION:
ca7a4deb 1273 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1274 break;
5f841b41 1275 default:
ca7a4deb
FF		 1276 if (!ah->is_monitoring)
1277 set = 0;
5f841b41 1278 break;
f1dc5600 1279 }
ca7a4deb 1280 REG_RMW(ah, AR_STA_ID1, set, mask);
7b37e0d4 1281 REG_RMW_BUFFER_FLUSH(ah);
f1dc5600
S		 1282}
1283
8fe65368
LR		 1284void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1285 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1286{
1287 u32 coef_exp, coef_man;
1288
1289 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1290 if ((coef_scaled >> coef_exp) & 0x1)
1291 break;
1292
1293 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1294
1295 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1296
1297 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1298 *coef_exponent = coef_exp - 16;
1299}
1300
d7df7a55
SM		 1301/* AR9330 WAR:
1302 * call external reset function to reset WMAC if:
1303 * - doing a cold reset
1304 * - we have pending frames in the TX queues.
1305 */
1306static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1307{
1308 int i, npend = 0;
1309
1310 for (i = 0; i < AR_NUM_QCU; i++) {
1311 npend = ath9k_hw_numtxpending(ah, i);
1312 if (npend)
1313 break;
1314 }
1315
1316 if (ah->external_reset &&
1317 (npend || type == ATH9K_RESET_COLD)) {
1318 int reset_err = 0;
1319
1320 ath_dbg(ath9k_hw_common(ah), RESET,
1321 "reset MAC via external reset\n");
1322
1323 reset_err = ah->external_reset();
1324 if (reset_err) {
1325 ath_err(ath9k_hw_common(ah),
1326 "External reset failed, err=%d\n",
1327 reset_err);
1328 return false;
1329 }
1330
1331 REG_WRITE(ah, AR_RTC_RESET, 1);
1332 }
1333
1334 return true;
1335}
1336
cbe61d8a 1337static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1338{
1339 u32 rst_flags;
1340 u32 tmpReg;
1341
70768496 1342 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1343 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1344 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1345 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1346 }
1347
7d0d0df0
S		 1348 ENABLE_REGWRITE_BUFFER(ah);
1349
9a658d2b
LR		 1350 if (AR_SREV_9300_20_OR_LATER(ah)) {
1351 REG_WRITE(ah, AR_WA, ah->WARegVal);
1352 udelay(10);
1353 }
1354
f1dc5600
S		 1355 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1356 AR_RTC_FORCE_WAKE_ON_INT);
1357
1358 if (AR_SREV_9100(ah)) {
1359 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1360 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1361 } else {
1362 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1363 if (AR_SREV_9340(ah))
1364 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1365 else
1366 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1367 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1368
1369 if (tmpReg) {
42d5bc3f 1370 u32 val;
f1dc5600 1371 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1372
1373 val = AR_RC_HOSTIF;
1374 if (!AR_SREV_9300_20_OR_LATER(ah))
1375 val |= AR_RC_AHB;
1376 REG_WRITE(ah, AR_RC, val);
1377
1378 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1379 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1380
1381 rst_flags = AR_RTC_RC_MAC_WARM;
1382 if (type == ATH9K_RESET_COLD)
1383 rst_flags |= AR_RTC_RC_MAC_COLD;
1384 }
1385
7d95847c 1386 if (AR_SREV_9330(ah)) {
d7df7a55
SM		 1387 if (!ath9k_hw_ar9330_reset_war(ah, type))
1388 return false;
7d95847c
GJ		 1389 }
1390
3863495b 1391 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1392 ar9003_mci_check_gpm_offset(ah);
3863495b 1393
466b0f02
MP		 1394 /* DMA HALT added to resolve ar9300 and ar9580 bus error during
1395 * RTC_RC reg read
1396 */
1397 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
1398 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1399 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
1400 20 * AH_WAIT_TIMEOUT);
1401 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1402 }
1403
d03a66c1 1404 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1405
1406 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1407
4dc78c43
SM		 1408 if (AR_SREV_9300_20_OR_LATER(ah))
1409 udelay(50);
1410 else if (AR_SREV_9100(ah))
3683a07b 1411 mdelay(10);
4dc78c43
SM		 1412 else
1413 udelay(100);
f1dc5600 1414
d03a66c1 1415 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1416 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1417 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1418 return false;
1419 }
1420
1421 if (!AR_SREV_9100(ah))
1422 REG_WRITE(ah, AR_RC, 0);
1423
f1dc5600
S		 1424 if (AR_SREV_9100(ah))
1425 udelay(50);
1426
1427 return true;
1428}
1429
cbe61d8a 1430static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1431{
7d0d0df0
S		 1432 ENABLE_REGWRITE_BUFFER(ah);
1433
9a658d2b
LR		 1434 if (AR_SREV_9300_20_OR_LATER(ah)) {
1435 REG_WRITE(ah, AR_WA, ah->WARegVal);
1436 udelay(10);
1437 }
1438
f1dc5600
S		 1439 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1440 AR_RTC_FORCE_WAKE_ON_INT);
1441
42d5bc3f 1442 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1443 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1444
d03a66c1 1445 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1446
7d0d0df0 1447 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1448
afe36533 1449 udelay(2);
84e2169b
SB		 1450
1451 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1452 REG_WRITE(ah, AR_RC, 0);
1453
d03a66c1 1454 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1455
1456 if (!ath9k_hw_wait(ah,
1457 AR_RTC_STATUS,
1458 AR_RTC_STATUS_M,
0caa7b14
S		 1459 AR_RTC_STATUS_ON,
1460 AH_WAIT_TIMEOUT)) {
d2182b69 1461 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1462 return false;
f078f209
LR		 1463 }
1464
f1dc5600
S		 1465 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1466}
1467
cbe61d8a 1468static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1469{
7a9233ff 1470 bool ret = false;
2577c6e8 1471
9a658d2b
LR		 1472 if (AR_SREV_9300_20_OR_LATER(ah)) {
1473 REG_WRITE(ah, AR_WA, ah->WARegVal);
1474 udelay(10);
1475 }
1476
f1dc5600
S		 1477 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1478 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1479
ceb26a60
FF		 1480 if (!ah->reset_power_on)
1481 type = ATH9K_RESET_POWER_ON;
1482
f1dc5600
S		 1483 switch (type) {
1484 case ATH9K_RESET_POWER_ON:
7a9233ff 1485 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1486 if (ret)
ceb26a60 1487 ah->reset_power_on = true;
7a9233ff 1488 break;
f1dc5600
S		 1489 case ATH9K_RESET_WARM:
1490 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1491 ret = ath9k_hw_set_reset(ah, type);
1492 break;
f1dc5600 1493 default:
7a9233ff 1494 break;
f1dc5600 1495 }
7a9233ff 1496
7a9233ff 1497 return ret;
f078f209
LR		 1498}
1499
cbe61d8a 1500static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1501 struct ath9k_channel *chan)
f078f209 1502{
9c083af8
FF		 1503 int reset_type = ATH9K_RESET_WARM;
1504
1505 if (AR_SREV_9280(ah)) {
1506 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1507 reset_type = ATH9K_RESET_POWER_ON;
1508 else
1509 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1510 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1511 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1512 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1513
1514 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1515 return false;
f078f209 1516
9ecdef4b 1517 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1518 return false;
f078f209 1519
2660b81a 1520 ah->chip_fullsleep = false;
bfc441a4
FF		 1521
1522 if (AR_SREV_9330(ah))
1523 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1524 ath9k_hw_init_pll(ah, chan);
f078f209 1525
f1dc5600 1526 return true;
f078f209
LR		 1527}
1528
cbe61d8a 1529static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1530 struct ath9k_channel *chan)
f078f209 1531{
c46917bb 1532 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1533 struct ath9k_hw_capabilities *pCap = &ah->caps;
1534 bool band_switch = false, mode_diff = false;
70e89a71 1535 u8 ini_reloaded = 0;
8fe65368 1536 u32 qnum;
0a3b7bac 1537 int r;
5f0c04ea 1538
b840cffe 1539 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1540 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1541 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1542 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1543 }
f078f209
LR		 1544
1545 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1546 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1547 ath_dbg(common, QUEUE,
226afe68 1548 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1549 return false;
1550 }
1551 }
1552
8fe65368 1553 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1554 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1555 return false;
1556 }
1557
b840cffe 1558 if (band_switch || mode_diff) {
5f0c04ea
RM		 1559 ath9k_hw_mark_phy_inactive(ah);
1560 udelay(5);
1561
5f35c0fa
SM		 1562 if (band_switch)
1563 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1564
1565 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1566 ath_err(common, "Failed to do fast channel change\n");
1567 return false;
1568 }
1569 }
1570
8fe65368 1571 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1572
8fe65368 1573 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1574 if (r) {
3800276a 1575 ath_err(common, "Failed to set channel\n");
0a3b7bac 1576 return false;
f078f209 1577 }
dfdac8ac 1578 ath9k_hw_set_clockrate(ah);
64ea57d0 1579 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1580
81c507a8 1581 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1582 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1583
70e89a71
SM		 1584 if (band_switch || ini_reloaded)
1585 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1586
70e89a71
SM		 1587 ath9k_hw_init_bb(ah, chan);
1588 ath9k_hw_rfbus_done(ah);
5f0c04ea 1589
70e89a71
SM		 1590 if (band_switch || ini_reloaded) {
1591 ah->ah_flags |= AH_FASTCC;
1592 ath9k_hw_init_cal(ah, chan);
a126ff51 1593 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1594 }
1595
f1dc5600
S		 1596 return true;
1597}
1598
691680b8
FF		 1599static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1600{
1601 u32 gpio_mask = ah->gpio_mask;
1602 int i;
1603
1604 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1605 if (!(gpio_mask & 1))
1606 continue;
1607
b2d70d49
MP		 1608 ath9k_hw_gpio_request_out(ah, i, NULL,
1609 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
691680b8 1610 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
db222190 1611 ath9k_hw_gpio_free(ah, i);
691680b8
FF		 1612 }
1613}
1614
1e516ca7
SM		 1615void ath9k_hw_check_nav(struct ath_hw *ah)
1616{
1617 struct ath_common *common = ath9k_hw_common(ah);
1618 u32 val;
1619
1620 val = REG_READ(ah, AR_NAV);
1621 if (val != 0xdeadbeef && val > 0x7fff) {
1622 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1623 REG_WRITE(ah, AR_NAV, 0);
1624 }
1625}
1626EXPORT_SYMBOL(ath9k_hw_check_nav);
1627
c9c99e5e 1628bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1629{
c9c99e5e 1630 int count = 50;
d31a36a6 1631 u32 reg, last_val;
c9c99e5e 1632
a34d0a0d
FF		 1633 /* Check if chip failed to wake up */
1634 if (REG_READ(ah, AR_CFG) == 0xdeadbeef)
1635 return false;
1636
01e18918
RM		 1637 if (AR_SREV_9300(ah))
1638 return !ath9k_hw_detect_mac_hang(ah);
1639
e17f83ea 1640 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1641 return true;
1642
d31a36a6 1643 last_val = REG_READ(ah, AR_OBS_BUS_1);
c9c99e5e
FF		 1644 do {
1645 reg = REG_READ(ah, AR_OBS_BUS_1);
d31a36a6
FF		 1646 if (reg != last_val)
1647 return true;
3b319aae 1648
105ff411 1649 udelay(1);
d31a36a6 1650 last_val = reg;
c9c99e5e
FF		 1651 if ((reg & 0x7E7FFFEF) == 0x00702400)
1652 continue;
1653
1654 switch (reg & 0x7E000B00) {
1655 case 0x1E000000:
1656 case 0x52000B00:
1657 case 0x18000B00:
1658 continue;
1659 default:
1660 return true;
1661 }
1662 } while (count-- > 0);
3b319aae 1663
c9c99e5e 1664 return false;
3b319aae 1665}
c9c99e5e 1666EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1667
15d2b585
SM		 1668static void ath9k_hw_init_mfp(struct ath_hw *ah)
1669{
1670 /* Setup MFP options for CCMP */
1671 if (AR_SREV_9280_20_OR_LATER(ah)) {
1672 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1673 * frames when constructing CCMP AAD. */
1674 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1675 0xc7ff);
60fc4962
CYY		 1676 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1677 ah->sw_mgmt_crypto_tx = true;
1678 else
1679 ah->sw_mgmt_crypto_tx = false;
e6510b11 1680 ah->sw_mgmt_crypto_rx = false;
15d2b585
SM		 1681 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1682 /* Disable hardware crypto for management frames */
1683 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1684 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1685 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1686 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
e6510b11
CYY		 1687 ah->sw_mgmt_crypto_tx = true;
1688 ah->sw_mgmt_crypto_rx = true;
15d2b585 1689 } else {
e6510b11
CYY		 1690 ah->sw_mgmt_crypto_tx = true;
1691 ah->sw_mgmt_crypto_rx = true;
15d2b585
SM		 1692 }
1693}
1694
1695static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1696 u32 macStaId1, u32 saveDefAntenna)
1697{
1698 struct ath_common *common = ath9k_hw_common(ah);
1699
1700 ENABLE_REGWRITE_BUFFER(ah);
1701
ecbbed32 1702 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585 1703 | AR_STA_ID1_RTS_USE_DEF
ecbbed32
FF		 1704 | ah->sta_id1_defaults,
1705 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1706 ath_hw_setbssidmask(common);
1707 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1708 ath9k_hw_write_associd(ah);
1709 REG_WRITE(ah, AR_ISR, ~0);
1710 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1711
1712 REGWRITE_BUFFER_FLUSH(ah);
1713
1714 ath9k_hw_set_operating_mode(ah, ah->opmode);
1715}
1716
1717static void ath9k_hw_init_queues(struct ath_hw *ah)
1718{
1719 int i;
1720
1721 ENABLE_REGWRITE_BUFFER(ah);
1722
1723 for (i = 0; i < AR_NUM_DCU; i++)
1724 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1725
1726 REGWRITE_BUFFER_FLUSH(ah);
1727
1728 ah->intr_txqs = 0;
1729 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1730 ath9k_hw_resettxqueue(ah, i);
1731}
1732
1733/*
1734 * For big endian systems turn on swapping for descriptors
1735 */
1736static void ath9k_hw_init_desc(struct ath_hw *ah)
1737{
1738 struct ath_common *common = ath9k_hw_common(ah);
1739
1740 if (AR_SREV_9100(ah)) {
1741 u32 mask;
1742 mask = REG_READ(ah, AR_CFG);
1743 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1744 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1745 mask);
1746 } else {
1747 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1748 REG_WRITE(ah, AR_CFG, mask);
1749 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1750 REG_READ(ah, AR_CFG));
1751 }
1752 } else {
1753 if (common->bus_ops->ath_bus_type == ATH_USB) {
1754 /* Configure AR9271 target WLAN */
1755 if (AR_SREV_9271(ah))
1756 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1757 else
1758 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1759 }
1760#ifdef __BIG_ENDIAN
1761 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
ede6a5e7
MP		 1762 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1763 AR_SREV_9561(ah))
15d2b585
SM		 1764 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1765 else
1766 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1767#endif
1768 }
1769}
1770
caed6579
SM		 1771/*
1772 * Fast channel change:
1773 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1774 */
1775static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1776{
1777 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1778 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1779 int ret;
1780
1781 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1782 goto fail;
1783
1784 if (ah->chip_fullsleep)
1785 goto fail;
1786
1787 if (!ah->curchan)
1788 goto fail;
1789
1790 if (chan->channel == ah->curchan->channel)
1791 goto fail;
1792
feb7bc99
FF		 1793 if ((ah->curchan->channelFlags | chan->channelFlags) &
1794 (CHANNEL_HALF | CHANNEL_QUARTER))
1795 goto fail;
1796
b840cffe 1797 /*
6b21fd20 1798 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1799 */
6b21fd20 1800 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1801 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1802 goto fail;
caed6579
SM		 1803
1804 if (!ath9k_hw_check_alive(ah))
1805 goto fail;
1806
1807 /*
1808 * For AR9462, make sure that calibration data for
1809 * re-using are present.
1810 */
8a90555f 1811 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1812 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1813 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1814 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1815 goto fail;
1816
1817 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1818 ah->curchan->channel, chan->channel);
1819
1820 ret = ath9k_hw_channel_change(ah, chan);
1821 if (!ret)
1822 goto fail;
1823
5955b2b0 1824 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1825 ar9003_mci_2g5g_switch(ah, false);
caed6579 1826
88033318
RM		 1827 ath9k_hw_loadnf(ah, ah->curchan);
1828 ath9k_hw_start_nfcal(ah, true);
1829
caed6579
SM		 1830 if (AR_SREV_9271(ah))
1831 ar9002_hw_load_ani_reg(ah, chan);
1832
1833 return 0;
1834fail:
1835 return -EINVAL;
1836}
1837
8d7e09dd
FF		 1838u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1839{
1840 struct timespec ts;
1841 s64 usec;
1842
1843 if (!cur) {
1844 getrawmonotonic(&ts);
1845 cur = &ts;
1846 }
1847
1848 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1849 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1850
1851 return (u32) usec;
1852}
1853EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1854
cbe61d8a 1855int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1856 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1857{
1510718d 1858 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1859 u32 saveLedState;
f078f209
LR		 1860 u32 saveDefAntenna;
1861 u32 macStaId1;
bec9a94b
BB		 1862 struct timespec tsf_ts;
1863 u32 tsf_offset;
46fe782c 1864 u64 tsf = 0;
15d2b585 1865 int r;
caed6579 1866 bool start_mci_reset = false;
63d32967
MSS		 1867 bool save_fullsleep = ah->chip_fullsleep;
1868
5955b2b0 1869 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1870 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1871 if (start_mci_reset)
1872 return 0;
63d32967
MSS		 1873 }
1874
9ecdef4b 1875 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1876 return -EIO;
f078f209 1877
caed6579
SM		 1878 if (ah->curchan && !ah->chip_fullsleep)
1879 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1880
20bd2a09 1881 ah->caldata = caldata;
fcb9a3de 1882 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1883 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1884 /* Operating channel changed, reset channel calibration data */
1885 memset(caldata, 0, sizeof(*caldata));
1886 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1887 } else if (caldata) {
4b9b42bf 1888 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1889 }
5bc225ac 1890 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1891
caed6579
SM		 1892 if (fastcc) {
1893 r = ath9k_hw_do_fastcc(ah, chan);
1894 if (!r)
1895 return r;
f078f209
LR		 1896 }
1897
5955b2b0 1898 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1899 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1900
f078f209
LR		 1901 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1902 if (saveDefAntenna == 0)
1903 saveDefAntenna = 1;
1904
1905 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1906
09d8e315 1907 /* Save TSF before chip reset, a cold reset clears it */
bec9a94b 1908 getrawmonotonic(&tsf_ts);
09d8e315 1909 tsf = ath9k_hw_gettsf64(ah);
46fe782c 1910
f078f209
LR		 1911 saveLedState = REG_READ(ah, AR_CFG_LED) &
1912 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1913 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1914
1915 ath9k_hw_mark_phy_inactive(ah);
1916
45ef6a0b
VT		 1917 ah->paprd_table_write_done = false;
1918
05020d23 1919 /* Only required on the first reset */
d7e7d229
LR		 1920 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1921 REG_WRITE(ah,
1922 AR9271_RESET_POWER_DOWN_CONTROL,
1923 AR9271_RADIO_RF_RST);
1924 udelay(50);
1925 }
1926
f078f209 1927 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1928 ath_err(common, "Chip reset failed\n");
ae8d2858 1929 return -EINVAL;
f078f209
LR		 1930 }
1931
05020d23 1932 /* Only required on the first reset */
d7e7d229
LR		 1933 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1934 ah->htc_reset_init = false;
1935 REG_WRITE(ah,
1936 AR9271_RESET_POWER_DOWN_CONTROL,
1937 AR9271_GATE_MAC_CTL);
1938 udelay(50);
1939 }
1940
46fe782c 1941 /* Restore TSF */
bec9a94b
BB		 1942 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
1943 ath9k_hw_settsf64(ah, tsf + tsf_offset);
46fe782c 1944
7a37081e 1945 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1946 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1947
e9141f71
S		 1948 if (!AR_SREV_9300_20_OR_LATER(ah))
1949 ar9002_hw_enable_async_fifo(ah);
1950
25c56eec 1951 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1952 if (r)
1953 return r;
f078f209 1954
935d00cc
LB		 1955 ath9k_hw_set_rfmode(ah, chan);
1956
5955b2b0 1957 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1958 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1959
f860d526
FF		 1960 /*
1961 * Some AR91xx SoC devices frequently fail to accept TSF writes
1962 * right after the chip reset. When that happens, write a new
bec9a94b 1963 * value after the initvals have been applied.
f860d526
FF		 1964 */
1965 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
bec9a94b
BB		 1966 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
1967 ath9k_hw_settsf64(ah, tsf + tsf_offset);
f860d526
FF		 1968 }
1969
15d2b585 1970 ath9k_hw_init_mfp(ah);
0ced0e17 1971
81c507a8 1972 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1973 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1974 ah->eep_ops->set_board_values(ah, chan);
a7765828 1975
15d2b585 1976 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1977
8fe65368 1978 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1979 if (r)
1980 return r;
f078f209 1981
dfdac8ac
FF		 1982 ath9k_hw_set_clockrate(ah);
1983
15d2b585 1984 ath9k_hw_init_queues(ah);
2660b81a 1985 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1986 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1987 ath9k_hw_init_qos(ah);
1988
2660b81a 1989 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
b2d70d49 1990 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill");
3b319aae 1991
0005baf4 1992 ath9k_hw_init_global_settings(ah);
f078f209 1993
fe2b6afb
FF		 1994 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1995 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1996 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1997 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1998 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1999 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2000 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 2001 }
2002
ca7a4deb 2003 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 2004
2005 ath9k_hw_set_dma(ah);
2006
ed6ebd8b
RM		 2007 if (!ath9k_hw_mci_is_enabled(ah))
2008 REG_WRITE(ah, AR_OBS, 8);
f078f209 2009
7b37e0d4 2010 ENABLE_REG_RMW_BUFFER(ah);
0ce024cb 2011 if (ah->config.rx_intr_mitigation) {
a64e1a45
SM		 2012 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
2013 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
f078f209
LR		 2014 }
2015
7f62a136
VT		 2016 if (ah->config.tx_intr_mitigation) {
2017 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2018 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2019 }
7b37e0d4 2020 REG_RMW_BUFFER_FLUSH(ah);
7f62a136 2021
f078f209
LR		 2022 ath9k_hw_init_bb(ah, chan);
2023
77a5a664 2024 if (caldata) {
4b9b42bf
SM		 2025 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
2026 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 2027 }
ae8d2858 2028 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2029 return -EIO;
f078f209 2030
5955b2b0 2031 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 2032 return -EIO;
63d32967 2033
7d0d0df0 2034 ENABLE_REGWRITE_BUFFER(ah);
f078f209 2035
8fe65368 2036 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 2037 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2038
7d0d0df0 2039 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2040
f4c34af4
SM		 2041 ath9k_hw_gen_timer_start_tsf2(ah);
2042
15d2b585 2043 ath9k_hw_init_desc(ah);
f078f209 2044
dbccdd1d 2045 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 2046 ath9k_hw_btcoex_enable(ah);
2047
5955b2b0 2048 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 2049 ar9003_mci_check_bt(ah);
63d32967 2050
7b89fccf
FF		 2051 if (AR_SREV_9300_20_OR_LATER(ah)) {
2052 ath9k_hw_loadnf(ah, chan);
2053 ath9k_hw_start_nfcal(ah, true);
2054 }
1fe860ed 2055
a7abaf7d 2056 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 2057 ar9003_hw_bb_watchdog_config(ah);
a7abaf7d
SM		 2058
2059 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
51ac8cbb 2060 ar9003_hw_disable_phy_restart(ah);
51ac8cbb 2061
691680b8
FF		 2062 ath9k_hw_apply_gpio_override(ah);
2063
7bdea96a 2064 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 2065 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2066
4307b0fe
LB		 2067 if (ah->hw->conf.radar_enabled) {
2068 /* set HW specific DFS configuration */
7a0a260a 2069 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
4307b0fe
LB		 2070 ath9k_hw_set_radar_params(ah);
2071 }
2072
ae8d2858 2073 return 0;
f078f209 2074}
7322fd19 2075EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2076
f1dc5600
S		 2077/******************************/
2078/* Power Management (Chipset) */
2079/******************************/
2080
42d5bc3f
LR		 2081/*
2082 * Notify Power Mgt is disabled in self-generated frames.
2083 * If requested, force chip to sleep.
2084 */
31604cf0 2085static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 2086{
f1dc5600 2087 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 2088
a4a2954f 2089 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 2090 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2091 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2092 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 2093 /* xxx Required for WLAN only case ? */
2094 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2095 udelay(100);
2096 }
2577c6e8 2097
31604cf0
SM		 2098 /*
2099 * Clear the RTC force wake bit to allow the
2100 * mac to go to sleep.
2101 */
2102 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2103
153dccd4 2104 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2105 udelay(100);
2577c6e8 2106
31604cf0
SM		 2107 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2108 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2109
31604cf0
SM		 2110 /* Shutdown chip. Active low */
2111 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2112 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2113 udelay(2);
f1dc5600 2114 }
9a658d2b
LR		 2115
2116 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2117 if (AR_SREV_9300_20_OR_LATER(ah))
2118 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2119}
2120
bbd79af5
LR		 2121/*
2122 * Notify Power Management is enabled in self-generating
2123 * frames. If request, set power mode of chip to
2124 * auto/normal. Duration in units of 128us (1/8 TU).
2125 */
31604cf0 2126static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2127{
31604cf0 2128 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2129
f1dc5600 2130 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2131
31604cf0
SM		 2132 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2133 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2134 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2135 AR_RTC_FORCE_WAKE_ON_INT);
2136 } else {
2577c6e8 2137
31604cf0
SM		 2138 /* When chip goes into network sleep, it could be waken
2139 * up by MCI_INT interrupt caused by BT's HW messages
2140 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2141 * rate (~100us). This will cause chip to leave and
2142 * re-enter network sleep mode frequently, which in
2143 * consequence will have WLAN MCI HW to generate lots of
2144 * SYS_WAKING and SYS_SLEEPING messages which will make
2145 * BT CPU to busy to process.
2146 */
153dccd4
RM		 2147 if (ath9k_hw_mci_is_enabled(ah))
2148 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2149 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2150 /*
2151 * Clear the RTC force wake bit to allow the
2152 * mac to go to sleep.
2153 */
153dccd4 2154 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2155
153dccd4 2156 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2157 udelay(30);
f078f209 2158 }
9a658d2b
LR		 2159
2160 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2161 if (AR_SREV_9300_20_OR_LATER(ah))
2162 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2163}
2164
31604cf0 2165static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2166{
f1dc5600
S		 2167 u32 val;
2168 int i;
f078f209 2169
9a658d2b
LR		 2170 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2171 if (AR_SREV_9300_20_OR_LATER(ah)) {
2172 REG_WRITE(ah, AR_WA, ah->WARegVal);
2173 udelay(10);
2174 }
2175
31604cf0
SM		 2176 if ((REG_READ(ah, AR_RTC_STATUS) &
2177 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2178 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2179 return false;
f1dc5600 2180 }
31604cf0
SM		 2181 if (!AR_SREV_9300_20_OR_LATER(ah))
2182 ath9k_hw_init_pll(ah, NULL);
2183 }
2184 if (AR_SREV_9100(ah))
2185 REG_SET_BIT(ah, AR_RTC_RESET,
2186 AR_RTC_RESET_EN);
2187
2188 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2189 AR_RTC_FORCE_WAKE_EN);
04575f21 2190 if (AR_SREV_9100(ah))
3683a07b 2191 mdelay(10);
04575f21
SM		 2192 else
2193 udelay(50);
f078f209 2194
31604cf0
SM		 2195 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2196 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2197 if (val == AR_RTC_STATUS_ON)
2198 break;
2199 udelay(50);
f1dc5600
S		 2200 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2201 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2202 }
2203 if (i == 0) {
2204 ath_err(ath9k_hw_common(ah),
2205 "Failed to wakeup in %uus\n",
2206 POWER_UP_TIME / 20);
2207 return false;
f078f209
LR		 2208 }
2209
cdbe408d
RM		 2210 if (ath9k_hw_mci_is_enabled(ah))
2211 ar9003_mci_set_power_awake(ah);
2212
f1dc5600 2213 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2214
f1dc5600 2215 return true;
f078f209
LR		 2216}
2217
9ecdef4b 2218bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2219{
c46917bb 2220 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2221 int status = true;
f1dc5600
S		 2222 static const char *modes[] = {
2223 "AWAKE",
2224 "FULL-SLEEP",
2225 "NETWORK SLEEP",
2226 "UNDEFINED"
2227 };
f1dc5600 2228
cbdec975
GJ		 2229 if (ah->power_mode == mode)
2230 return status;
2231
d2182b69 2232 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2233 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2234
2235 switch (mode) {
2236 case ATH9K_PM_AWAKE:
31604cf0 2237 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2238 break;
2239 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2240 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2241 ar9003_mci_set_full_sleep(ah);
1010911e 2242
31604cf0 2243 ath9k_set_power_sleep(ah);
2660b81a 2244 ah->chip_fullsleep = true;
f1dc5600
S		 2245 break;
2246 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2247 ath9k_set_power_network_sleep(ah);
f1dc5600 2248 break;
f078f209 2249 default:
3800276a 2250 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2251 return false;
2252 }
2660b81a 2253 ah->power_mode = mode;
f1dc5600 2254
69f4aab1
LR		 2255 /*
2256 * XXX: If this warning never comes up after a while then
2257 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2258 * ath9k_hw_setpower() return type void.
2259 */
97dcec57
SM		 2260
2261 if (!(ah->ah_flags & AH_UNPLUGGED))
2262 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2263
f1dc5600 2264 return status;
f078f209 2265}
7322fd19 2266EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2267
f1dc5600
S		 2268/*******************/
2269/* Beacon Handling */
2270/*******************/
2271
cbe61d8a 2272void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2273{
f078f209
LR		 2274 int flags = 0;
2275
7d0d0df0
S		 2276 ENABLE_REGWRITE_BUFFER(ah);
2277
2660b81a 2278 switch (ah->opmode) {
d97809db 2279 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2280 REG_SET_BIT(ah, AR_TXCFG,
2281 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2282 case NL80211_IFTYPE_MESH_POINT:
d97809db 2283 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2284 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2285 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2286 TU_TO_USEC(ah->config.dma_beacon_response_time));
2287 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2288 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2289 flags |=
2290 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2291 break;
d97809db 2292 default:
d2182b69
JP		 2293 ath_dbg(ath9k_hw_common(ah), BEACON,
2294 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2295 return;
2296 break;
f078f209
LR		 2297 }
2298
dd347f2f
FF		 2299 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2300 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2301 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2302
7d0d0df0 2303 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2304
f078f209
LR		 2305 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2306}
7322fd19 2307EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2308
cbe61d8a 2309void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2310 const struct ath9k_beacon_state *bs)
f078f209
LR		 2311{
2312 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2313 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2314 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2315
7d0d0df0
S		 2316 ENABLE_REGWRITE_BUFFER(ah);
2317
4ed15762
FF		 2318 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2319 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2320 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2321
7d0d0df0 2322 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2323
f078f209
LR		 2324 REG_RMW_FIELD(ah, AR_RSSI_THR,
2325 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2326
f29f5c08 2327 beaconintval = bs->bs_intval;
f078f209
LR		 2328
2329 if (bs->bs_sleepduration > beaconintval)
2330 beaconintval = bs->bs_sleepduration;
2331
2332 dtimperiod = bs->bs_dtimperiod;
2333 if (bs->bs_sleepduration > dtimperiod)
2334 dtimperiod = bs->bs_sleepduration;
2335
2336 if (beaconintval == dtimperiod)
2337 nextTbtt = bs->bs_nextdtim;
2338 else
2339 nextTbtt = bs->bs_nexttbtt;
2340
58bb9ca8
JD		 2341 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim);
2342 ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt);
2343 ath_dbg(common, BEACON, "beacon period %u\n", beaconintval);
2344 ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod);
f078f209 2345
7d0d0df0
S		 2346 ENABLE_REGWRITE_BUFFER(ah);
2347
4ed15762
FF		 2348 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2349 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2350
f1dc5600
S		 2351 REG_WRITE(ah, AR_SLEEP1,
2352 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2353 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2354
f1dc5600
S		 2355 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2356 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2357 else
2358 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2359
f1dc5600
S		 2360 REG_WRITE(ah, AR_SLEEP2,
2361 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2362
4ed15762
FF		 2363 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2364 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2365
7d0d0df0 2366 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2367
f1dc5600
S		 2368 REG_SET_BIT(ah, AR_TIMER_MODE,
2369 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2370 AR_DTIM_TIMER_EN);
f078f209 2371
4af9cf4f
S		 2372 /* TSF Out of Range Threshold */
2373 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2374}
7322fd19 2375EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2376
f1dc5600
S		 2377/*******************/
2378/* HW Capabilities */
2379/*******************/
2380
6054069a
FF		 2381static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2382{
2383 eeprom_chainmask &= chip_chainmask;
2384 if (eeprom_chainmask)
2385 return eeprom_chainmask;
2386 else
2387 return chip_chainmask;
2388}
2389
9a66af33
ZK		 2390/**
2391 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2392 * @ah: the atheros hardware data structure
2393 *
2394 * We enable DFS support upstream on chipsets which have passed a series
2395 * of tests. The testing requirements are going to be documented. Desired
2396 * test requirements are documented at:
2397 *
2398 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2399 *
2400 * Once a new chipset gets properly tested an individual commit can be used
2401 * to document the testing for DFS for that chipset.
2402 */
2403static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2404{
2405
2406 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2407 /* for temporary testing DFS with 9280 */
2408 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2409 /* AR9580 will likely be our first target to get testing on */
2410 case AR_SREV_VERSION_9580:
73e4937d 2411 return true;
9a66af33
ZK		 2412 default:
2413 return false;
2414 }
2415}
2416
a01ab81b
MP		 2417static void ath9k_gpio_cap_init(struct ath_hw *ah)
2418{
2419 struct ath9k_hw_capabilities *pCap = &ah->caps;
2420
2421 if (AR_SREV_9271(ah)) {
2422 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2423 pCap->gpio_mask = AR9271_GPIO_MASK;
2424 } else if (AR_DEVID_7010(ah)) {
2425 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2426 pCap->gpio_mask = AR7010_GPIO_MASK;
2427 } else if (AR_SREV_9287(ah)) {
2428 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2429 pCap->gpio_mask = AR9287_GPIO_MASK;
2430 } else if (AR_SREV_9285(ah)) {
2431 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2432 pCap->gpio_mask = AR9285_GPIO_MASK;
2433 } else if (AR_SREV_9280(ah)) {
2434 pCap->num_gpio_pins = AR9280_NUM_GPIO;
2435 pCap->gpio_mask = AR9280_GPIO_MASK;
2436 } else if (AR_SREV_9300(ah)) {
2437 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2438 pCap->gpio_mask = AR9300_GPIO_MASK;
2439 } else if (AR_SREV_9330(ah)) {
2440 pCap->num_gpio_pins = AR9330_NUM_GPIO;
2441 pCap->gpio_mask = AR9330_GPIO_MASK;
2442 } else if (AR_SREV_9340(ah)) {
2443 pCap->num_gpio_pins = AR9340_NUM_GPIO;
2444 pCap->gpio_mask = AR9340_GPIO_MASK;
2445 } else if (AR_SREV_9462(ah)) {
2446 pCap->num_gpio_pins = AR9462_NUM_GPIO;
2447 pCap->gpio_mask = AR9462_GPIO_MASK;
2448 } else if (AR_SREV_9485(ah)) {
2449 pCap->num_gpio_pins = AR9485_NUM_GPIO;
2450 pCap->gpio_mask = AR9485_GPIO_MASK;
2451 } else if (AR_SREV_9531(ah)) {
2452 pCap->num_gpio_pins = AR9531_NUM_GPIO;
2453 pCap->gpio_mask = AR9531_GPIO_MASK;
2454 } else if (AR_SREV_9550(ah)) {
2455 pCap->num_gpio_pins = AR9550_NUM_GPIO;
2456 pCap->gpio_mask = AR9550_GPIO_MASK;
2457 } else if (AR_SREV_9561(ah)) {
2458 pCap->num_gpio_pins = AR9561_NUM_GPIO;
2459 pCap->gpio_mask = AR9561_GPIO_MASK;
2460 } else if (AR_SREV_9565(ah)) {
2461 pCap->num_gpio_pins = AR9565_NUM_GPIO;
2462 pCap->gpio_mask = AR9565_GPIO_MASK;
2463 } else if (AR_SREV_9580(ah)) {
2464 pCap->num_gpio_pins = AR9580_NUM_GPIO;
2465 pCap->gpio_mask = AR9580_GPIO_MASK;
2466 } else {
2467 pCap->num_gpio_pins = AR_NUM_GPIO;
2468 pCap->gpio_mask = AR_GPIO_MASK;
2469 }
2470}
2471
a9a29ce6 2472int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2473{
2660b81a 2474 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2475 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2476 struct ath_common *common = ath9k_hw_common(ah);
608b88cb 2477
0ff2b5c0 2478 u16 eeval;
47c80de6 2479 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2480
f74df6fb 2481 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2482 regulatory->current_rd = eeval;
f078f209 2483
2660b81a 2484 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2485 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2486 if (regulatory->current_rd == 0x64 ||
2487 regulatory->current_rd == 0x65)
2488 regulatory->current_rd += 5;
2489 else if (regulatory->current_rd == 0x41)
2490 regulatory->current_rd = 0x43;
d2182b69
JP		 2491 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2492 regulatory->current_rd);
f1dc5600 2493 }
f078f209 2494
f74df6fb 2495 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3468968e
FF		 2496
2497 if (eeval & AR5416_OPFLAGS_11A) {
2498 if (ah->disable_5ghz)
2499 ath_warn(common, "disabling 5GHz band\n");
2500 else
2501 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
a9a29ce6
GJ		 2502 }
2503
3468968e
FF		 2504 if (eeval & AR5416_OPFLAGS_11G) {
2505 if (ah->disable_2ghz)
2506 ath_warn(common, "disabling 2GHz band\n");
2507 else
2508 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2509 }
f078f209 2510
3468968e
FF		 2511 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2512 ath_err(common, "both bands are disabled\n");
2513 return -EINVAL;
2514 }
f1dc5600 2515
db7b542e
MP		 2516 ath9k_gpio_cap_init(ah);
2517
e41db61d
SM		 2518 if (AR_SREV_9485(ah) ||
2519 AR_SREV_9285(ah) ||
2520 AR_SREV_9330(ah) ||
2521 AR_SREV_9565(ah))
ee79ccd9 2522 pCap->chip_chainmask = 1;
6054069a 2523 else if (!AR_SREV_9280_20_OR_LATER(ah))
ee79ccd9
SM		 2524 pCap->chip_chainmask = 7;
2525 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2526 AR_SREV_9340(ah) ||
2527 AR_SREV_9462(ah) ||
2528 AR_SREV_9531(ah))
2529 pCap->chip_chainmask = 3;
6054069a 2530 else
ee79ccd9 2531 pCap->chip_chainmask = 7;
6054069a 2532
f74df6fb 2533 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2534 /*
2535 * For AR9271 we will temporarilly uses the rx chainmax as read from
2536 * the EEPROM.
2537 */
8147f5de 2538 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2539 !(eeval & AR5416_OPFLAGS_11A) &&
2540 !(AR_SREV_9271(ah)))
2541 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2542 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2543 else if (AR_SREV_9100(ah))
2544 pCap->rx_chainmask = 0x7;
8147f5de 2545 else
d7e7d229 2546 /* Use rx_chainmask from EEPROM. */
8147f5de 2547 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2548
ee79ccd9
SM		 2549 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2550 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2551 ah->txchainmask = pCap->tx_chainmask;
2552 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2553
7a37081e 2554 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2555
02d2ebb2
FF		 2556 /* enable key search for every frame in an aggregate */
2557 if (AR_SREV_9300_20_OR_LATER(ah))
2558 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2559
ce2220d1
BR		 2560 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2561
0db156e9 2562 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2563 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2564 else
2565 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2566
1b2538b2 2567 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2568 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2569 else
f1dc5600 2570 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2571
74e13060 2572#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2573 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2574 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2575 ah->rfkill_gpio =
2576 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2577 ah->rfkill_polarity =
2578 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2579
2580 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2581 }
f1dc5600 2582#endif
d5d1154f 2583 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2584 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2585 else
2586 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2587
e7594072 2588 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2589 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2590 else
2591 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2592
ceb26445 2593 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2594 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
ede6a5e7
MP		 2595 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2596 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2597 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2598
ceb26445
VT		 2599 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2600 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2601 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2602 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2603 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2604 } else {
2605 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2606 if (AR_SREV_9280_20(ah))
6b42e8d0 2607 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2608 }
1adf02ff 2609
6c84ce08
VT		 2610 if (AR_SREV_9300_20_OR_LATER(ah))
2611 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2612
ede6a5e7
MP		 2613 if (AR_SREV_9561(ah))
2614 ah->ent_mode = 0x3BDA000;
2615 else if (AR_SREV_9300_20_OR_LATER(ah))
6ee63f55
SB		 2616 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2617
a42acef0 2618 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2619 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2620
f85c3371 2621 if (AR_SREV_9285(ah)) {
754dc536
VT		 2622 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2623 ant_div_ctl1 =
2624 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2625 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2626 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2627 ath_info(common, "Enable LNA combining\n");
2628 }
754dc536 2629 }
f85c3371
SM		 2630 }
2631
ea066d5a
MSS		 2632 if (AR_SREV_9300_20_OR_LATER(ah)) {
2633 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2634 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2635 }
2636
06236e53 2637 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2638 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2639 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2640 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2641 ath_info(common, "Enable LNA combining\n");
2642 }
21d2c63a 2643 }
754dc536 2644
9a66af33
ZK		 2645 if (ath9k_hw_dfs_tested(ah))
2646 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2647
47c80de6
VT		 2648 tx_chainmask = pCap->tx_chainmask;
2649 rx_chainmask = pCap->rx_chainmask;
2650 while (tx_chainmask || rx_chainmask) {
2651 if (tx_chainmask & BIT(0))
2652 pCap->max_txchains++;
2653 if (rx_chainmask & BIT(0))
2654 pCap->max_rxchains++;
2655
2656 tx_chainmask >>= 1;
2657 rx_chainmask >>= 1;
2658 }
2659
a4a2954f 2660 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2661 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2662 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2663
2b5e54e2 2664 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2665 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2666 }
2667
0f21ee8d
SM		 2668 if (AR_SREV_9300_20_OR_LATER(ah) &&
2669 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2670 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2671
12a44422
SM		 2672#ifdef CONFIG_ATH9K_WOW
2673 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2674 ah->wow.max_patterns = MAX_NUM_PATTERN;
2675 else
2676 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2677#endif
2678
a9a29ce6 2679 return 0;
f078f209
LR		 2680}
2681
f1dc5600
S		 2682/****************************/
2683/* GPIO / RFKILL / Antennae */
2684/****************************/
f078f209 2685
b2d70d49 2686static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
f1dc5600
S		 2687{
2688 int addr;
2689 u32 gpio_shift, tmp;
f078f209 2690
f1dc5600
S		 2691 if (gpio > 11)
2692 addr = AR_GPIO_OUTPUT_MUX3;
2693 else if (gpio > 5)
2694 addr = AR_GPIO_OUTPUT_MUX2;
2695 else
2696 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2697
f1dc5600 2698 gpio_shift = (gpio % 6) * 5;
f078f209 2699
b2d70d49
MP		 2700 if (AR_SREV_9280_20_OR_LATER(ah) ||
2701 (addr != AR_GPIO_OUTPUT_MUX1)) {
f1dc5600
S		 2702 REG_RMW(ah, addr, (type << gpio_shift),
2703 (0x1f << gpio_shift));
f078f209 2704 } else {
f1dc5600
S		 2705 tmp = REG_READ(ah, addr);
2706 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2707 tmp &= ~(0x1f << gpio_shift);
2708 tmp |= (type << gpio_shift);
2709 REG_WRITE(ah, addr, tmp);
f078f209 2710 }
f078f209
LR		 2711}
2712
b2d70d49
MP		 2713/* BSP should set the corresponding MUX register correctly.
2714 */
2715static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out,
2716 const char *label)
f078f209 2717{
b2d70d49
MP		 2718 if (ah->caps.gpio_requested & BIT(gpio))
2719 return;
f078f209 2720
b2d70d49
MP		 2721 /* may be requested by BSP, free anyway */
2722 gpio_free(gpio);
f078f209 2723
b2d70d49 2724 if (gpio_request_one(gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label))
88c1f4f6 2725 return;
f078f209 2726
b2d70d49 2727 ah->caps.gpio_requested |= BIT(gpio);
f078f209
LR		 2728}
2729
b2d70d49
MP		 2730static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out,
2731 u32 ah_signal_type)
f078f209 2732{
b2d70d49 2733 u32 gpio_set, gpio_shift = gpio;
f078f209 2734
88c1f4f6 2735 if (AR_DEVID_7010(ah)) {
b2d70d49
MP		 2736 gpio_set = out ?
2737 AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT;
2738 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift,
2739 AR7010_GPIO_OE_MASK << gpio_shift);
2740 } else if (AR_SREV_SOC(ah)) {
2741 gpio_set = out ? 1 : 0;
2742 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2743 gpio_set << gpio_shift);
2744 } else {
2745 gpio_shift = gpio << 1;
2746 gpio_set = out ?
2747 AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO;
2748 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2749 AR_GPIO_OE_OUT_DRV << gpio_shift);
2750
2751 if (out)
2752 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2753 }
f078f209
LR		 2754}
2755
b2d70d49
MP		 2756static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out,
2757 const char *label, u32 ah_signal_type)
f078f209 2758{
b2d70d49 2759 WARN_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2760
b2d70d49
MP		 2761 if (BIT(gpio) & ah->caps.gpio_mask)
2762 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type);
2763 else if (AR_SREV_SOC(ah))
2764 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label);
2765 else
2766 WARN_ON(1);
2767}
f078f209 2768
b2d70d49
MP		 2769void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label)
2770{
2771 ath9k_hw_gpio_request(ah, gpio, false, label, 0);
f078f209 2772}
b2d70d49 2773EXPORT_SYMBOL(ath9k_hw_gpio_request_in);
f078f209 2774
b2d70d49
MP		 2775void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
2776 u32 ah_signal_type)
f078f209 2777{
b2d70d49
MP		 2778 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type);
2779}
2780EXPORT_SYMBOL(ath9k_hw_gpio_request_out);
2781
2782void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio)
2783{
2784 if (!AR_SREV_SOC(ah))
88c1f4f6 2785 return;
b2d70d49
MP		 2786
2787 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2788
2789 if (ah->caps.gpio_requested & BIT(gpio)) {
2790 gpio_free(gpio);
2791 ah->caps.gpio_requested &= ~BIT(gpio);
88c1f4f6 2792 }
b2d70d49
MP		 2793}
2794EXPORT_SYMBOL(ath9k_hw_gpio_free);
88c1f4f6 2795
b2d70d49
MP		 2796u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2797{
2798 u32 val = 0xffffffff;
5b5fa355 2799
b2d70d49
MP		 2800#define MS_REG_READ(x, y) \
2801 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y))
2802
2803 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2804
2805 if (BIT(gpio) & ah->caps.gpio_mask) {
2806 if (AR_SREV_9271(ah))
2807 val = MS_REG_READ(AR9271, gpio);
2808 else if (AR_SREV_9287(ah))
2809 val = MS_REG_READ(AR9287, gpio);
2810 else if (AR_SREV_9285(ah))
2811 val = MS_REG_READ(AR9285, gpio);
2812 else if (AR_SREV_9280(ah))
2813 val = MS_REG_READ(AR928X, gpio);
2814 else if (AR_DEVID_7010(ah))
2815 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio);
2816 else if (AR_SREV_9300_20_OR_LATER(ah))
2817 val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio);
2818 else
2819 val = MS_REG_READ(AR, gpio);
2820 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2821 val = gpio_get_value(gpio) & BIT(gpio);
2822 } else {
2823 WARN_ON(1);
2824 }
2825
91851cc7 2826 return !!val;
f078f209 2827}
b2d70d49 2828EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2829
b2d70d49 2830void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
61b559de 2831{
b2d70d49 2832 WARN_ON(gpio >= ah->caps.num_gpio_pins);
61b559de 2833
b2d70d49
MP		 2834 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah))
2835 val = !val;
2836 else
2837 val = !!val;
2838
2839 if (BIT(gpio) & ah->caps.gpio_mask) {
2840 u32 out_addr = AR_DEVID_7010(ah) ?
2841 AR7010_GPIO_OUT : AR_GPIO_IN_OUT;
2842
2843 REG_RMW(ah, out_addr, val << gpio, BIT(gpio));
2844 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2845 gpio_set_value(gpio, val);
2846 } else {
2847 WARN_ON(1);
2848 }
61b559de 2849}
b2d70d49 2850EXPORT_SYMBOL(ath9k_hw_set_gpio);
61b559de 2851
cbe61d8a 2852void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2853{
f1dc5600 2854 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2855}
7322fd19 2856EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2857
f1dc5600
S		 2858/*********************/
2859/* General Operation */
2860/*********************/
2861
cbe61d8a 2862u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2863{
f1dc5600
S		 2864 u32 bits = REG_READ(ah, AR_RX_FILTER);
2865 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2866
f1dc5600
S		 2867 if (phybits & AR_PHY_ERR_RADAR)
2868 bits |= ATH9K_RX_FILTER_PHYRADAR;
2869 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2870 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2871
f1dc5600 2872 return bits;
f078f209 2873}
7322fd19 2874EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2875
cbe61d8a 2876void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2877{
f1dc5600 2878 u32 phybits;
f078f209 2879
7d0d0df0
S		 2880 ENABLE_REGWRITE_BUFFER(ah);
2881
7ea310be
S		 2882 REG_WRITE(ah, AR_RX_FILTER, bits);
2883
f1dc5600
S		 2884 phybits = 0;
2885 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2886 phybits |= AR_PHY_ERR_RADAR;
2887 if (bits & ATH9K_RX_FILTER_PHYERR)
2888 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2889 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2890
f1dc5600 2891 if (phybits)
ca7a4deb 2892 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2893 else
ca7a4deb 2894 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2895
2896 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2897}
7322fd19 2898EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2899
cbe61d8a 2900bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2901{
99922a45
RM		 2902 if (ath9k_hw_mci_is_enabled(ah))
2903 ar9003_mci_bt_gain_ctrl(ah);
2904
63a75b91
SB		 2905 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2906 return false;
2907
2908 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2909 ah->htc_reset_init = true;
63a75b91 2910 return true;
f1dc5600 2911}
7322fd19 2912EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2913
cbe61d8a 2914bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2915{
9ecdef4b 2916 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2917 return false;
f078f209 2918
63a75b91
SB		 2919 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2920 return false;
2921
2922 ath9k_hw_init_pll(ah, NULL);
2923 return true;
f078f209 2924}
7322fd19 2925EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2926
ca2c68cc
FF		 2927static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2928{
2929 enum eeprom_param gain_param;
2930
2931 if (IS_CHAN_2GHZ(chan))
2932 gain_param = EEP_ANTENNA_GAIN_2G;
2933 else
2934 gain_param = EEP_ANTENNA_GAIN_5G;
2935
2936 return ah->eep_ops->get_eeprom(ah, gain_param);
2937}
2938
64ea57d0
GJ		 2939void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2940 bool test)
ca2c68cc
FF		 2941{
2942 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2943 struct ieee80211_channel *channel;
71f5137b 2944 int chan_pwr, new_pwr;
ca2c68cc
FF		 2945
2946 if (!chan)
2947 return;
2948
2949 channel = chan->chan;
2950 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2951 new_pwr = min_t(int, chan_pwr, reg->power_limit);
ca2c68cc
FF		 2952
2953 ah->eep_ops->set_txpower(ah, chan,
2954 ath9k_regd_get_ctl(reg, chan),
71f5137b 2955 get_antenna_gain(ah, chan), new_pwr, test);
ca2c68cc
FF		 2956}
2957
de40f316 2958void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2959{
ca2c68cc 2960 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2961 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2962 struct ieee80211_channel *channel = chan->chan;
9c204b46 2963
48ef5c42 2964 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2965 if (test)
ca2c68cc 2966 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2967
64ea57d0 2968 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2969
ca2c68cc
FF		 2970 if (test)
2971 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2972}
7322fd19 2973EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2974
cbe61d8a 2975void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2976{
2660b81a 2977 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2978}
7322fd19 2979EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2980
cbe61d8a 2981void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2982{
f1dc5600
S		 2983 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2984 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2985}
7322fd19 2986EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2987
f2b2143e 2988void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2989{
1510718d
LR		 2990 struct ath_common *common = ath9k_hw_common(ah);
2991
2992 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2993 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2994 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2995}
7322fd19 2996EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2997
1c0fc65e
BP		 2998#define ATH9K_MAX_TSF_READ 10
2999
cbe61d8a 3000u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 3001{
1c0fc65e
BP		 3002 u32 tsf_lower, tsf_upper1, tsf_upper2;
3003 int i;
3004
3005 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
3006 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
3007 tsf_lower = REG_READ(ah, AR_TSF_L32);
3008 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
3009 if (tsf_upper2 == tsf_upper1)
3010 break;
3011 tsf_upper1 = tsf_upper2;
3012 }
f078f209 3013
1c0fc65e 3014 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 3015
1c0fc65e 3016 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 3017}
7322fd19 3018EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 3019
cbe61d8a 3020void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 3021{
27abe060 3022 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 3023 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 3024}
7322fd19 3025EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 3026
cbe61d8a 3027void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 3028{
f9b604f6
GJ		 3029 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3030 AH_TSF_WRITE_TIMEOUT))
d2182b69 3031 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 3032 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 3033
f1dc5600
S		 3034 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3035}
7322fd19 3036EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 3037
60ca9f87 3038void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 3039{
60ca9f87 3040 if (set)
2660b81a 3041 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 3042 else
2660b81a 3043 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 3044}
7322fd19 3045EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 3046
e4744ec7 3047void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 3048{
3049 u32 macmode;
3050
e4744ec7 3051 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 3052 macmode = AR_2040_JOINED_RX_CLEAR;
3053 else
3054 macmode = 0;
f078f209 3055
f1dc5600 3056 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 3057}
ff155a45
VT		 3058
3059/* HW Generic timers configuration */
3060
3061static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3062{
3063 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3064 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3065 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3066 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3067 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3068 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3069 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3070 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3071 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3072 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3073 AR_NDP2_TIMER_MODE, 0x0002},
3074 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3075 AR_NDP2_TIMER_MODE, 0x0004},
3076 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3077 AR_NDP2_TIMER_MODE, 0x0008},
3078 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3079 AR_NDP2_TIMER_MODE, 0x0010},
3080 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3081 AR_NDP2_TIMER_MODE, 0x0020},
3082 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3083 AR_NDP2_TIMER_MODE, 0x0040},
3084 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3085 AR_NDP2_TIMER_MODE, 0x0080}
3086};
3087
3088/* HW generic timer primitives */
3089
dd347f2f 3090u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 3091{
3092 return REG_READ(ah, AR_TSF_L32);
3093}
dd347f2f 3094EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45 3095
f4c34af4
SM		 3096void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
3097{
3098 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3099
3100 if (timer_table->tsf2_enabled) {
3101 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
3102 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
3103 }
3104}
3105
ff155a45
VT		 3106struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3107 void (*trigger)(void *),
3108 void (*overflow)(void *),
3109 void *arg,
3110 u8 timer_index)
3111{
3112 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3113 struct ath_gen_timer *timer;
3114
c67ce339 3115 if ((timer_index < AR_FIRST_NDP_TIMER) ||
f4c34af4
SM		 3116 (timer_index >= ATH_MAX_GEN_TIMER))
3117 return NULL;
3118
3119 if ((timer_index > AR_FIRST_NDP_TIMER) &&
3120 !AR_SREV_9300_20_OR_LATER(ah))
c67ce339
FF		 3121 return NULL;
3122
ff155a45 3123 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 3124 if (timer == NULL)
ff155a45 3125 return NULL;
ff155a45
VT		 3126
3127 /* allocate a hardware generic timer slot */
3128 timer_table->timers[timer_index] = timer;
3129 timer->index = timer_index;
3130 timer->trigger = trigger;
3131 timer->overflow = overflow;
3132 timer->arg = arg;
3133
f4c34af4
SM		 3134 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
3135 timer_table->tsf2_enabled = true;
3136 ath9k_hw_gen_timer_start_tsf2(ah);
3137 }
3138
ff155a45
VT		 3139 return timer;
3140}
7322fd19 3141EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3142
cd9bf689
LR		 3143void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3144 struct ath_gen_timer *timer,
c67ce339 3145 u32 timer_next,
cd9bf689 3146 u32 timer_period)
ff155a45
VT		 3147{
3148 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 3149 u32 mask = 0;
788f6875 3150
c67ce339 3151 timer_table->timer_mask |= BIT(timer->index);
ff155a45 3152
ff155a45
VT		 3153 /*
3154 * Program generic timer registers
3155 */
3156 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3157 timer_next);
3158 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3159 timer_period);
3160 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3161 gen_tmr_configuration[timer->index].mode_mask);
3162
a4a2954f 3163 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 3164 /*
423e38e8 3165 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3166 * to use. But we still follow the old rule, 0 - 7 use tsf and
3167 * 8 - 15 use tsf2.
3168 */
3169 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3170 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3171 (1 << timer->index));
3172 else
3173 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3174 (1 << timer->index));
3175 }
3176
c67ce339
FF		 3177 if (timer->trigger)
3178 mask |= SM(AR_GENTMR_BIT(timer->index),
3179 AR_IMR_S5_GENTIMER_TRIG);
3180 if (timer->overflow)
3181 mask |= SM(AR_GENTMR_BIT(timer->index),
3182 AR_IMR_S5_GENTIMER_THRESH);
3183
3184 REG_SET_BIT(ah, AR_IMR_S5, mask);
3185
3186 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3187 ah->imask |= ATH9K_INT_GENTIMER;
3188 ath9k_hw_set_interrupts(ah);
3189 }
ff155a45 3190}
7322fd19 3191EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3192
cd9bf689 3193void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3194{
3195 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3196
ff155a45
VT		 3197 /* Clear generic timer enable bits. */
3198 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3199 gen_tmr_configuration[timer->index].mode_mask);
3200
b7f59766
SM		 3201 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3202 /*
3203 * Need to switch back to TSF if it was using TSF2.
3204 */
3205 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3206 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3207 (1 << timer->index));
3208 }
3209 }
3210
ff155a45
VT		 3211 /* Disable both trigger and thresh interrupt masks */
3212 REG_CLR_BIT(ah, AR_IMR_S5,
3213 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3214 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3215
c67ce339
FF		 3216 timer_table->timer_mask &= ~BIT(timer->index);
3217
3218 if (timer_table->timer_mask == 0) {
3219 ah->imask &= ~ATH9K_INT_GENTIMER;
3220 ath9k_hw_set_interrupts(ah);
3221 }
ff155a45 3222}
7322fd19 3223EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3224
3225void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3226{
3227 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3228
3229 /* free the hardware generic timer slot */
3230 timer_table->timers[timer->index] = NULL;
3231 kfree(timer);
3232}
7322fd19 3233EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3234
3235/*
3236 * Generic Timer Interrupts handling
3237 */
3238void ath_gen_timer_isr(struct ath_hw *ah)
3239{
3240 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3241 struct ath_gen_timer *timer;
c67ce339
FF		 3242 unsigned long trigger_mask, thresh_mask;
3243 unsigned int index;
ff155a45
VT		 3244
3245 /* get hardware generic timer interrupt status */
3246 trigger_mask = ah->intr_gen_timer_trigger;
3247 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 3248 trigger_mask &= timer_table->timer_mask;
3249 thresh_mask &= timer_table->timer_mask;
ff155a45 3250
c67ce339 3251 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3252 timer = timer_table->timers[index];
c67ce339
FF		 3253 if (!timer)
3254 continue;
3255 if (!timer->overflow)
3256 continue;
a6a172b2
FF		 3257
3258 trigger_mask &= ~BIT(index);
ff155a45
VT		 3259 timer->overflow(timer->arg);
3260 }
3261
c67ce339 3262 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3263 timer = timer_table->timers[index];
c67ce339
FF		 3264 if (!timer)
3265 continue;
3266 if (!timer->trigger)
3267 continue;
ff155a45
VT		 3268 timer->trigger(timer->arg);
3269 }
3270}
7322fd19 3271EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3272
05020d23
S		 3273/********/
3274/* HTC */
3275/********/
3276
2da4f01a
LR		 3277static struct {
3278 u32 version;
3279 const char * name;
3280} ath_mac_bb_names[] = {
3281 /* Devices with external radios */
3282 { AR_SREV_VERSION_5416_PCI, "5416" },
3283 { AR_SREV_VERSION_5416_PCIE, "5418" },
3284 { AR_SREV_VERSION_9100, "9100" },
3285 { AR_SREV_VERSION_9160, "9160" },
3286 /* Single-chip solutions */
3287 { AR_SREV_VERSION_9280, "9280" },
3288 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3289 { AR_SREV_VERSION_9287, "9287" },
3290 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3291 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3292 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3293 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3294 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3295 { AR_SREV_VERSION_9462, "9462" },
485124cb 3296 { AR_SREV_VERSION_9550, "9550" },
77fac465 3297 { AR_SREV_VERSION_9565, "9565" },
c08148bb 3298 { AR_SREV_VERSION_9531, "9531" },
1165dd90 3299 { AR_SREV_VERSION_9561, "9561" },
2da4f01a
LR		 3300};
3301
3302/* For devices with external radios */
3303static struct {
3304 u16 version;
3305 const char * name;
3306} ath_rf_names[] = {
3307 { 0, "5133" },
3308 { AR_RAD5133_SREV_MAJOR, "5133" },
3309 { AR_RAD5122_SREV_MAJOR, "5122" },
3310 { AR_RAD2133_SREV_MAJOR, "2133" },
3311 { AR_RAD2122_SREV_MAJOR, "2122" }
3312};
3313
3314/*
3315 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3316 */
f934c4d9 3317static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3318{
3319 int i;
3320
3321 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3322 if (ath_mac_bb_names[i].version == mac_bb_version) {
3323 return ath_mac_bb_names[i].name;
3324 }
3325 }
3326
3327 return "????";
3328}
2da4f01a
LR		 3329
3330/*
3331 * Return the RF name. "????" is returned if the RF is unknown.
3332 * Used for devices with external radios.
3333 */
f934c4d9 3334static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3335{
3336 int i;
3337
3338 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3339 if (ath_rf_names[i].version == rf_version) {
3340 return ath_rf_names[i].name;
3341 }
3342 }
3343
3344 return "????";
3345}
f934c4d9
LR		 3346
3347void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3348{
3349 int used;
3350
3351 /* chipsets >= AR9280 are single-chip */
7a37081e 3352 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3353 used = scnprintf(hw_name, len,
3354 "Atheros AR%s Rev:%x",
3355 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3356 ah->hw_version.macRev);
f934c4d9
LR		 3357 }
3358 else {
5e88ba62
ZK		 3359 used = scnprintf(hw_name, len,
3360 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3361 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3362 ah->hw_version.macRev,
3363 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3364 & AR_RADIO_SREV_MAJOR)),
3365 ah->hw_version.phyRev);
f934c4d9
LR		 3366 }
3367
3368 hw_name[used] = '\0';
3369}
3370EXPORT_SYMBOL(ath9k_hw_name);
Linux 6.x block layer and io_uring tree(s)