Commit | Line | Data |
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fb9987d0 S |
1 | /* |
2 | * Copyright (c) 2010 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include "htc.h" | |
18 | ||
19 | MODULE_AUTHOR("Atheros Communications"); | |
20 | MODULE_LICENSE("Dual BSD/GPL"); | |
21 | MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices"); | |
22 | ||
23 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
24 | module_param_named(debug, ath9k_debug, uint, 0); | |
25 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
26 | ||
e1572c5e S |
27 | int htc_modparam_nohwcrypt; |
28 | module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444); | |
fb9987d0 S |
29 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); |
30 | ||
31 | #define CHAN2G(_freq, _idx) { \ | |
32 | .center_freq = (_freq), \ | |
33 | .hw_value = (_idx), \ | |
34 | .max_power = 20, \ | |
35 | } | |
36 | ||
ea46e644 S |
37 | #define CHAN5G(_freq, _idx) { \ |
38 | .band = IEEE80211_BAND_5GHZ, \ | |
39 | .center_freq = (_freq), \ | |
40 | .hw_value = (_idx), \ | |
41 | .max_power = 20, \ | |
42 | } | |
43 | ||
21cb9879 VN |
44 | #define ATH_HTC_BTCOEX_PRODUCT_ID "wb193" |
45 | ||
fb9987d0 S |
46 | static struct ieee80211_channel ath9k_2ghz_channels[] = { |
47 | CHAN2G(2412, 0), /* Channel 1 */ | |
48 | CHAN2G(2417, 1), /* Channel 2 */ | |
49 | CHAN2G(2422, 2), /* Channel 3 */ | |
50 | CHAN2G(2427, 3), /* Channel 4 */ | |
51 | CHAN2G(2432, 4), /* Channel 5 */ | |
52 | CHAN2G(2437, 5), /* Channel 6 */ | |
53 | CHAN2G(2442, 6), /* Channel 7 */ | |
54 | CHAN2G(2447, 7), /* Channel 8 */ | |
55 | CHAN2G(2452, 8), /* Channel 9 */ | |
56 | CHAN2G(2457, 9), /* Channel 10 */ | |
57 | CHAN2G(2462, 10), /* Channel 11 */ | |
58 | CHAN2G(2467, 11), /* Channel 12 */ | |
59 | CHAN2G(2472, 12), /* Channel 13 */ | |
60 | CHAN2G(2484, 13), /* Channel 14 */ | |
61 | }; | |
62 | ||
ea46e644 S |
63 | static struct ieee80211_channel ath9k_5ghz_channels[] = { |
64 | /* _We_ call this UNII 1 */ | |
65 | CHAN5G(5180, 14), /* Channel 36 */ | |
66 | CHAN5G(5200, 15), /* Channel 40 */ | |
67 | CHAN5G(5220, 16), /* Channel 44 */ | |
68 | CHAN5G(5240, 17), /* Channel 48 */ | |
69 | /* _We_ call this UNII 2 */ | |
70 | CHAN5G(5260, 18), /* Channel 52 */ | |
71 | CHAN5G(5280, 19), /* Channel 56 */ | |
72 | CHAN5G(5300, 20), /* Channel 60 */ | |
73 | CHAN5G(5320, 21), /* Channel 64 */ | |
74 | /* _We_ call this "Middle band" */ | |
75 | CHAN5G(5500, 22), /* Channel 100 */ | |
76 | CHAN5G(5520, 23), /* Channel 104 */ | |
77 | CHAN5G(5540, 24), /* Channel 108 */ | |
78 | CHAN5G(5560, 25), /* Channel 112 */ | |
79 | CHAN5G(5580, 26), /* Channel 116 */ | |
80 | CHAN5G(5600, 27), /* Channel 120 */ | |
81 | CHAN5G(5620, 28), /* Channel 124 */ | |
82 | CHAN5G(5640, 29), /* Channel 128 */ | |
83 | CHAN5G(5660, 30), /* Channel 132 */ | |
84 | CHAN5G(5680, 31), /* Channel 136 */ | |
85 | CHAN5G(5700, 32), /* Channel 140 */ | |
86 | /* _We_ call this UNII 3 */ | |
87 | CHAN5G(5745, 33), /* Channel 149 */ | |
88 | CHAN5G(5765, 34), /* Channel 153 */ | |
89 | CHAN5G(5785, 35), /* Channel 157 */ | |
90 | CHAN5G(5805, 36), /* Channel 161 */ | |
91 | CHAN5G(5825, 37), /* Channel 165 */ | |
92 | }; | |
93 | ||
fb9987d0 S |
94 | /* Atheros hardware rate code addition for short premble */ |
95 | #define SHPCHECK(__hw_rate, __flags) \ | |
96 | ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0) | |
97 | ||
98 | #define RATE(_bitrate, _hw_rate, _flags) { \ | |
99 | .bitrate = (_bitrate), \ | |
100 | .flags = (_flags), \ | |
101 | .hw_value = (_hw_rate), \ | |
102 | .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ | |
103 | } | |
104 | ||
105 | static struct ieee80211_rate ath9k_legacy_rates[] = { | |
106 | RATE(10, 0x1b, 0), | |
107 | RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */ | |
108 | RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */ | |
109 | RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */ | |
110 | RATE(60, 0x0b, 0), | |
111 | RATE(90, 0x0f, 0), | |
112 | RATE(120, 0x0a, 0), | |
113 | RATE(180, 0x0e, 0), | |
114 | RATE(240, 0x09, 0), | |
115 | RATE(360, 0x0d, 0), | |
116 | RATE(480, 0x08, 0), | |
117 | RATE(540, 0x0c, 0), | |
118 | }; | |
119 | ||
120 | static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv) | |
121 | { | |
122 | int time_left; | |
123 | ||
d8c49ffb SM |
124 | if (atomic_read(&priv->htc->tgt_ready) > 0) { |
125 | atomic_dec(&priv->htc->tgt_ready); | |
126 | return 0; | |
127 | } | |
128 | ||
fb9987d0 S |
129 | /* Firmware can take up to 50ms to get ready, to be safe use 1 second */ |
130 | time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ); | |
131 | if (!time_left) { | |
132 | dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n"); | |
133 | return -ETIMEDOUT; | |
134 | } | |
135 | ||
d8c49ffb SM |
136 | atomic_dec(&priv->htc->tgt_ready); |
137 | ||
fb9987d0 S |
138 | return 0; |
139 | } | |
140 | ||
141 | static void ath9k_deinit_priv(struct ath9k_htc_priv *priv) | |
142 | { | |
e1572c5e | 143 | ath9k_htc_exit_debug(priv->ah); |
fb9987d0 S |
144 | ath9k_hw_deinit(priv->ah); |
145 | tasklet_kill(&priv->wmi_tasklet); | |
146 | tasklet_kill(&priv->rx_tasklet); | |
147 | tasklet_kill(&priv->tx_tasklet); | |
148 | kfree(priv->ah); | |
149 | priv->ah = NULL; | |
150 | } | |
151 | ||
152 | static void ath9k_deinit_device(struct ath9k_htc_priv *priv) | |
153 | { | |
154 | struct ieee80211_hw *hw = priv->hw; | |
155 | ||
156 | wiphy_rfkill_stop_polling(hw->wiphy); | |
157 | ath9k_deinit_leds(priv); | |
158 | ieee80211_unregister_hw(hw); | |
159 | ath9k_rx_cleanup(priv); | |
160 | ath9k_tx_cleanup(priv); | |
161 | ath9k_deinit_priv(priv); | |
162 | } | |
163 | ||
164 | static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv, | |
165 | u16 service_id, | |
166 | void (*tx) (void *, | |
167 | struct sk_buff *, | |
168 | enum htc_endpoint_id, | |
169 | bool txok), | |
170 | enum htc_endpoint_id *ep_id) | |
171 | { | |
172 | struct htc_service_connreq req; | |
173 | ||
174 | memset(&req, 0, sizeof(struct htc_service_connreq)); | |
175 | ||
176 | req.service_id = service_id; | |
177 | req.ep_callbacks.priv = priv; | |
178 | req.ep_callbacks.rx = ath9k_htc_rxep; | |
179 | req.ep_callbacks.tx = tx; | |
180 | ||
181 | return htc_connect_service(priv->htc, &req, ep_id); | |
182 | } | |
183 | ||
fa6e15e0 RM |
184 | static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid, |
185 | u32 drv_info) | |
fb9987d0 S |
186 | { |
187 | int ret; | |
188 | ||
189 | /* WMI CMD*/ | |
190 | ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep); | |
191 | if (ret) | |
192 | goto err; | |
193 | ||
194 | /* Beacon */ | |
9c6dda4e | 195 | ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep, |
fb9987d0 S |
196 | &priv->beacon_ep); |
197 | if (ret) | |
198 | goto err; | |
199 | ||
200 | /* CAB */ | |
201 | ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep, | |
202 | &priv->cab_ep); | |
203 | if (ret) | |
204 | goto err; | |
205 | ||
206 | ||
207 | /* UAPSD */ | |
208 | ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep, | |
209 | &priv->uapsd_ep); | |
210 | if (ret) | |
211 | goto err; | |
212 | ||
213 | /* MGMT */ | |
214 | ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep, | |
215 | &priv->mgmt_ep); | |
216 | if (ret) | |
217 | goto err; | |
218 | ||
219 | /* DATA BE */ | |
220 | ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep, | |
221 | &priv->data_be_ep); | |
222 | if (ret) | |
223 | goto err; | |
224 | ||
225 | /* DATA BK */ | |
226 | ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep, | |
227 | &priv->data_bk_ep); | |
228 | if (ret) | |
229 | goto err; | |
230 | ||
231 | /* DATA VI */ | |
232 | ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep, | |
233 | &priv->data_vi_ep); | |
234 | if (ret) | |
235 | goto err; | |
236 | ||
237 | /* DATA VO */ | |
238 | ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep, | |
239 | &priv->data_vo_ep); | |
240 | if (ret) | |
241 | goto err; | |
242 | ||
6267dc70 S |
243 | /* |
244 | * Setup required credits before initializing HTC. | |
245 | * This is a bit hacky, but, since queuing is done in | |
246 | * the HIF layer, shouldn't matter much. | |
247 | */ | |
248 | ||
0b5ead91 | 249 | if (IS_AR7010_DEVICE(drv_info)) |
6267dc70 | 250 | priv->htc->credits = 45; |
fa6e15e0 | 251 | else |
4e63f768 | 252 | priv->htc->credits = 33; |
6267dc70 | 253 | |
fb9987d0 S |
254 | ret = htc_init(priv->htc); |
255 | if (ret) | |
256 | goto err; | |
257 | ||
6267dc70 S |
258 | dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n", |
259 | priv->htc->credits); | |
260 | ||
fb9987d0 S |
261 | return 0; |
262 | ||
263 | err: | |
264 | dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n"); | |
265 | return ret; | |
266 | } | |
267 | ||
268 | static int ath9k_reg_notifier(struct wiphy *wiphy, | |
269 | struct regulatory_request *request) | |
270 | { | |
271 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
272 | struct ath9k_htc_priv *priv = hw->priv; | |
273 | ||
274 | return ath_reg_notifier_apply(wiphy, request, | |
275 | ath9k_hw_regulatory(priv->ah)); | |
276 | } | |
277 | ||
4a22fe10 | 278 | static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset) |
fb9987d0 S |
279 | { |
280 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
281 | struct ath_common *common = ath9k_hw_common(ah); | |
282 | struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; | |
283 | __be32 val, reg = cpu_to_be32(reg_offset); | |
284 | int r; | |
285 | ||
286 | r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID, | |
287 | (u8 *) ®, sizeof(reg), | |
288 | (u8 *) &val, sizeof(val), | |
289 | 100); | |
290 | if (unlikely(r)) { | |
226afe68 JP |
291 | ath_dbg(common, ATH_DBG_WMI, |
292 | "REGISTER READ FAILED: (0x%04x, %d)\n", | |
293 | reg_offset, r); | |
fb9987d0 S |
294 | return -EIO; |
295 | } | |
296 | ||
297 | return be32_to_cpu(val); | |
298 | } | |
299 | ||
4a22fe10 | 300 | static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset) |
fb9987d0 S |
301 | { |
302 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
303 | struct ath_common *common = ath9k_hw_common(ah); | |
304 | struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; | |
07b2fa5a | 305 | const __be32 buf[2] = { |
fb9987d0 S |
306 | cpu_to_be32(reg_offset), |
307 | cpu_to_be32(val), | |
308 | }; | |
309 | int r; | |
310 | ||
311 | r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, | |
312 | (u8 *) &buf, sizeof(buf), | |
313 | (u8 *) &val, sizeof(val), | |
314 | 100); | |
315 | if (unlikely(r)) { | |
226afe68 JP |
316 | ath_dbg(common, ATH_DBG_WMI, |
317 | "REGISTER WRITE FAILED:(0x%04x, %d)\n", | |
318 | reg_offset, r); | |
fb9987d0 S |
319 | } |
320 | } | |
321 | ||
4a22fe10 S |
322 | static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset) |
323 | { | |
324 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
325 | struct ath_common *common = ath9k_hw_common(ah); | |
326 | struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; | |
327 | u32 rsp_status; | |
328 | int r; | |
329 | ||
330 | mutex_lock(&priv->wmi->multi_write_mutex); | |
331 | ||
332 | /* Store the register/value */ | |
333 | priv->wmi->multi_write[priv->wmi->multi_write_idx].reg = | |
334 | cpu_to_be32(reg_offset); | |
335 | priv->wmi->multi_write[priv->wmi->multi_write_idx].val = | |
336 | cpu_to_be32(val); | |
337 | ||
338 | priv->wmi->multi_write_idx++; | |
339 | ||
340 | /* If the buffer is full, send it out. */ | |
341 | if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) { | |
342 | r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, | |
343 | (u8 *) &priv->wmi->multi_write, | |
344 | sizeof(struct register_write) * priv->wmi->multi_write_idx, | |
345 | (u8 *) &rsp_status, sizeof(rsp_status), | |
346 | 100); | |
347 | if (unlikely(r)) { | |
226afe68 JP |
348 | ath_dbg(common, ATH_DBG_WMI, |
349 | "REGISTER WRITE FAILED, multi len: %d\n", | |
350 | priv->wmi->multi_write_idx); | |
4a22fe10 S |
351 | } |
352 | priv->wmi->multi_write_idx = 0; | |
353 | } | |
354 | ||
355 | mutex_unlock(&priv->wmi->multi_write_mutex); | |
356 | } | |
357 | ||
358 | static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset) | |
359 | { | |
360 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
361 | struct ath_common *common = ath9k_hw_common(ah); | |
362 | struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; | |
363 | ||
364 | if (atomic_read(&priv->wmi->mwrite_cnt)) | |
365 | ath9k_regwrite_buffer(hw_priv, val, reg_offset); | |
366 | else | |
367 | ath9k_regwrite_single(hw_priv, val, reg_offset); | |
368 | } | |
369 | ||
370 | static void ath9k_enable_regwrite_buffer(void *hw_priv) | |
371 | { | |
372 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
373 | struct ath_common *common = ath9k_hw_common(ah); | |
374 | struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; | |
375 | ||
376 | atomic_inc(&priv->wmi->mwrite_cnt); | |
377 | } | |
378 | ||
4a22fe10 S |
379 | static void ath9k_regwrite_flush(void *hw_priv) |
380 | { | |
381 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
382 | struct ath_common *common = ath9k_hw_common(ah); | |
383 | struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; | |
384 | u32 rsp_status; | |
385 | int r; | |
386 | ||
435c1610 FF |
387 | atomic_dec(&priv->wmi->mwrite_cnt); |
388 | ||
4a22fe10 S |
389 | mutex_lock(&priv->wmi->multi_write_mutex); |
390 | ||
391 | if (priv->wmi->multi_write_idx) { | |
392 | r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, | |
393 | (u8 *) &priv->wmi->multi_write, | |
394 | sizeof(struct register_write) * priv->wmi->multi_write_idx, | |
395 | (u8 *) &rsp_status, sizeof(rsp_status), | |
396 | 100); | |
397 | if (unlikely(r)) { | |
226afe68 JP |
398 | ath_dbg(common, ATH_DBG_WMI, |
399 | "REGISTER WRITE FAILED, multi len: %d\n", | |
400 | priv->wmi->multi_write_idx); | |
4a22fe10 S |
401 | } |
402 | priv->wmi->multi_write_idx = 0; | |
403 | } | |
404 | ||
405 | mutex_unlock(&priv->wmi->multi_write_mutex); | |
406 | } | |
407 | ||
fb9987d0 | 408 | static const struct ath_ops ath9k_common_ops = { |
4a22fe10 S |
409 | .read = ath9k_regread, |
410 | .write = ath9k_regwrite, | |
411 | .enable_write_buffer = ath9k_enable_regwrite_buffer, | |
4a22fe10 | 412 | .write_flush = ath9k_regwrite_flush, |
fb9987d0 S |
413 | }; |
414 | ||
415 | static void ath_usb_read_cachesize(struct ath_common *common, int *csz) | |
416 | { | |
417 | *csz = L1_CACHE_BYTES >> 2; | |
418 | } | |
419 | ||
420 | static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data) | |
421 | { | |
422 | struct ath_hw *ah = (struct ath_hw *) common->ah; | |
423 | ||
424 | (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); | |
425 | ||
426 | if (!ath9k_hw_wait(ah, | |
427 | AR_EEPROM_STATUS_DATA, | |
428 | AR_EEPROM_STATUS_DATA_BUSY | | |
429 | AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, | |
430 | AH_WAIT_TIMEOUT)) | |
431 | return false; | |
432 | ||
433 | *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), | |
434 | AR_EEPROM_STATUS_DATA_VAL); | |
435 | ||
436 | return true; | |
437 | } | |
438 | ||
439 | static const struct ath_bus_ops ath9k_usb_bus_ops = { | |
497ad9ad | 440 | .ath_bus_type = ATH_USB, |
fb9987d0 S |
441 | .read_cachesize = ath_usb_read_cachesize, |
442 | .eeprom_read = ath_usb_eeprom_read, | |
443 | }; | |
444 | ||
445 | static void setup_ht_cap(struct ath9k_htc_priv *priv, | |
446 | struct ieee80211_sta_ht_cap *ht_info) | |
447 | { | |
6debecad S |
448 | struct ath_common *common = ath9k_hw_common(priv->ah); |
449 | u8 tx_streams, rx_streams; | |
450 | int i; | |
451 | ||
fb9987d0 S |
452 | ht_info->ht_supported = true; |
453 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
454 | IEEE80211_HT_CAP_SM_PS | | |
455 | IEEE80211_HT_CAP_SGI_40 | | |
456 | IEEE80211_HT_CAP_DSSSCCK40; | |
457 | ||
b4dec5e8 S |
458 | if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) |
459 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
460 | ||
17525f96 S |
461 | ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); |
462 | ||
fb9987d0 S |
463 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
464 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
465 | ||
466 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
6debecad S |
467 | |
468 | /* ath9k_htc supports only 1 or 2 stream devices */ | |
469 | tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2); | |
470 | rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2); | |
471 | ||
226afe68 JP |
472 | ath_dbg(common, ATH_DBG_CONFIG, |
473 | "TX streams %d, RX streams: %d\n", | |
474 | tx_streams, rx_streams); | |
6debecad S |
475 | |
476 | if (tx_streams != rx_streams) { | |
477 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; | |
478 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
479 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
480 | } | |
481 | ||
482 | for (i = 0; i < rx_streams; i++) | |
483 | ht_info->mcs.rx_mask[i] = 0xff; | |
484 | ||
fb9987d0 S |
485 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; |
486 | } | |
487 | ||
488 | static int ath9k_init_queues(struct ath9k_htc_priv *priv) | |
489 | { | |
490 | struct ath_common *common = ath9k_hw_common(priv->ah); | |
491 | int i; | |
492 | ||
493 | for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++) | |
494 | priv->hwq_map[i] = -1; | |
495 | ||
ca74b83b S |
496 | priv->beaconq = ath9k_hw_beaconq_setup(priv->ah); |
497 | if (priv->beaconq == -1) { | |
3800276a | 498 | ath_err(common, "Unable to setup BEACON xmit queue\n"); |
ca74b83b S |
499 | goto err; |
500 | } | |
501 | ||
502 | priv->cabq = ath9k_htc_cabq_setup(priv); | |
503 | if (priv->cabq == -1) { | |
3800276a | 504 | ath_err(common, "Unable to setup CAB xmit queue\n"); |
ca74b83b S |
505 | goto err; |
506 | } | |
507 | ||
e8c35a77 | 508 | if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) { |
3800276a | 509 | ath_err(common, "Unable to setup xmit queue for BE traffic\n"); |
fb9987d0 S |
510 | goto err; |
511 | } | |
512 | ||
e8c35a77 | 513 | if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) { |
3800276a | 514 | ath_err(common, "Unable to setup xmit queue for BK traffic\n"); |
fb9987d0 S |
515 | goto err; |
516 | } | |
e8c35a77 | 517 | if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) { |
3800276a | 518 | ath_err(common, "Unable to setup xmit queue for VI traffic\n"); |
fb9987d0 S |
519 | goto err; |
520 | } | |
e8c35a77 | 521 | if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) { |
3800276a | 522 | ath_err(common, "Unable to setup xmit queue for VO traffic\n"); |
fb9987d0 S |
523 | goto err; |
524 | } | |
525 | ||
526 | return 0; | |
527 | ||
528 | err: | |
529 | return -EINVAL; | |
530 | } | |
531 | ||
532 | static void ath9k_init_crypto(struct ath9k_htc_priv *priv) | |
533 | { | |
534 | struct ath_common *common = ath9k_hw_common(priv->ah); | |
535 | int i = 0; | |
536 | ||
537 | /* Get the hardware key cache size. */ | |
538 | common->keymax = priv->ah->caps.keycache_size; | |
539 | if (common->keymax > ATH_KEYMAX) { | |
226afe68 JP |
540 | ath_dbg(common, ATH_DBG_ANY, |
541 | "Warning, using only %u entries in %u key cache\n", | |
542 | ATH_KEYMAX, common->keymax); | |
fb9987d0 S |
543 | common->keymax = ATH_KEYMAX; |
544 | } | |
545 | ||
e2b62624 RM |
546 | if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) |
547 | common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED; | |
548 | ||
fb9987d0 S |
549 | /* |
550 | * Reset the key cache since some parts do not | |
551 | * reset the contents on initial power up. | |
552 | */ | |
553 | for (i = 0; i < common->keymax; i++) | |
040e539e | 554 | ath_hw_keyreset(common, (u16) i); |
fb9987d0 S |
555 | } |
556 | ||
557 | static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv) | |
558 | { | |
d4659912 | 559 | if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { |
fb9987d0 S |
560 | priv->sbands[IEEE80211_BAND_2GHZ].channels = |
561 | ath9k_2ghz_channels; | |
562 | priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; | |
563 | priv->sbands[IEEE80211_BAND_2GHZ].n_channels = | |
564 | ARRAY_SIZE(ath9k_2ghz_channels); | |
565 | priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; | |
566 | priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates = | |
567 | ARRAY_SIZE(ath9k_legacy_rates); | |
568 | } | |
ea46e644 | 569 | |
d4659912 | 570 | if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { |
ea46e644 S |
571 | priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels; |
572 | priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; | |
573 | priv->sbands[IEEE80211_BAND_5GHZ].n_channels = | |
574 | ARRAY_SIZE(ath9k_5ghz_channels); | |
575 | priv->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
576 | ath9k_legacy_rates + 4; | |
577 | priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates = | |
578 | ARRAY_SIZE(ath9k_legacy_rates) - 4; | |
579 | } | |
fb9987d0 S |
580 | } |
581 | ||
582 | static void ath9k_init_misc(struct ath9k_htc_priv *priv) | |
583 | { | |
584 | struct ath_common *common = ath9k_hw_common(priv->ah); | |
585 | ||
586 | common->tx_chainmask = priv->ah->caps.tx_chainmask; | |
587 | common->rx_chainmask = priv->ah->caps.rx_chainmask; | |
588 | ||
364734fa | 589 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
fb9987d0 | 590 | |
9f01a84e | 591 | priv->ah->opmode = NL80211_IFTYPE_STATION; |
fb9987d0 S |
592 | } |
593 | ||
21cb9879 VN |
594 | static void ath9k_init_btcoex(struct ath9k_htc_priv *priv) |
595 | { | |
596 | int qnum; | |
597 | ||
598 | switch (priv->ah->btcoex_hw.scheme) { | |
599 | case ATH_BTCOEX_CFG_NONE: | |
600 | break; | |
601 | case ATH_BTCOEX_CFG_3WIRE: | |
602 | priv->ah->btcoex_hw.btactive_gpio = 7; | |
603 | priv->ah->btcoex_hw.btpriority_gpio = 6; | |
604 | priv->ah->btcoex_hw.wlanactive_gpio = 8; | |
605 | priv->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; | |
606 | ath9k_hw_btcoex_init_3wire(priv->ah); | |
607 | ath_htc_init_btcoex_work(priv); | |
608 | qnum = priv->hwq_map[WME_AC_BE]; | |
609 | ath9k_hw_init_btcoex_hw(priv->ah, qnum); | |
610 | break; | |
611 | default: | |
612 | WARN_ON(1); | |
613 | break; | |
614 | } | |
615 | } | |
616 | ||
617 | static int ath9k_init_priv(struct ath9k_htc_priv *priv, | |
fa6e15e0 RM |
618 | u16 devid, char *product, |
619 | u32 drv_info) | |
fb9987d0 S |
620 | { |
621 | struct ath_hw *ah = NULL; | |
622 | struct ath_common *common; | |
623 | int ret = 0, csz = 0; | |
624 | ||
625 | priv->op_flags |= OP_INVALID; | |
626 | ||
627 | ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); | |
628 | if (!ah) | |
629 | return -ENOMEM; | |
630 | ||
631 | ah->hw_version.devid = devid; | |
632 | ah->hw_version.subsysid = 0; /* FIXME */ | |
0b5ead91 | 633 | ah->hw_version.usbdev = drv_info; |
f8afa42b | 634 | ah->ah_flags |= AH_USE_EEPROM; |
fb9987d0 S |
635 | priv->ah = ah; |
636 | ||
637 | common = ath9k_hw_common(ah); | |
638 | common->ops = &ath9k_common_ops; | |
639 | common->bus_ops = &ath9k_usb_bus_ops; | |
640 | common->ah = ah; | |
641 | common->hw = priv->hw; | |
642 | common->priv = priv; | |
643 | common->debug_mask = ath9k_debug; | |
644 | ||
645 | spin_lock_init(&priv->wmi->wmi_lock); | |
646 | spin_lock_init(&priv->beacon_lock); | |
7757dfed | 647 | spin_lock_init(&priv->tx_lock); |
fb9987d0 | 648 | mutex_init(&priv->mutex); |
bde748a4 | 649 | mutex_init(&priv->htc_pm_lock); |
fb9987d0 S |
650 | tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet, |
651 | (unsigned long)priv); | |
652 | tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet, | |
653 | (unsigned long)priv); | |
654 | tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv); | |
fb9987d0 | 655 | INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work); |
bde748a4 | 656 | INIT_WORK(&priv->ps_work, ath9k_ps_work); |
fb9987d0 S |
657 | |
658 | /* | |
659 | * Cache line size is used to size and align various | |
660 | * structures used to communicate with the hardware. | |
661 | */ | |
662 | ath_read_cachesize(common, &csz); | |
663 | common->cachelsz = csz << 2; /* convert to bytes */ | |
664 | ||
665 | ret = ath9k_hw_init(ah); | |
666 | if (ret) { | |
3800276a JP |
667 | ath_err(common, |
668 | "Unable to initialize hardware; initialization status: %d\n", | |
669 | ret); | |
fb9987d0 S |
670 | goto err_hw; |
671 | } | |
672 | ||
e1572c5e | 673 | ret = ath9k_htc_init_debug(ah); |
fb9987d0 | 674 | if (ret) { |
3800276a | 675 | ath_err(common, "Unable to create debugfs files\n"); |
fb9987d0 S |
676 | goto err_debug; |
677 | } | |
678 | ||
679 | ret = ath9k_init_queues(priv); | |
680 | if (ret) | |
681 | goto err_queues; | |
682 | ||
683 | ath9k_init_crypto(priv); | |
684 | ath9k_init_channels_rates(priv); | |
685 | ath9k_init_misc(priv); | |
686 | ||
21cb9879 VN |
687 | if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) { |
688 | ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE; | |
689 | ath9k_init_btcoex(priv); | |
690 | } | |
691 | ||
fb9987d0 S |
692 | return 0; |
693 | ||
694 | err_queues: | |
e1572c5e | 695 | ath9k_htc_exit_debug(ah); |
fb9987d0 S |
696 | err_debug: |
697 | ath9k_hw_deinit(ah); | |
698 | err_hw: | |
699 | ||
700 | kfree(ah); | |
701 | priv->ah = NULL; | |
702 | ||
703 | return ret; | |
704 | } | |
705 | ||
706 | static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv, | |
707 | struct ieee80211_hw *hw) | |
708 | { | |
709 | struct ath_common *common = ath9k_hw_common(priv->ah); | |
710 | ||
711 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
712 | IEEE80211_HW_AMPDU_AGGREGATION | | |
713 | IEEE80211_HW_SPECTRUM_MGMT | | |
32fbccaf | 714 | IEEE80211_HW_HAS_RATE_CONTROL | |
bde748a4 VN |
715 | IEEE80211_HW_RX_INCLUDES_FCS | |
716 | IEEE80211_HW_SUPPORTS_PS | | |
0ce3bcfc MSS |
717 | IEEE80211_HW_PS_NULLFUNC_STACK | |
718 | IEEE80211_HW_NEED_DTIM_PERIOD; | |
fb9987d0 S |
719 | |
720 | hw->wiphy->interface_modes = | |
721 | BIT(NL80211_IFTYPE_STATION) | | |
722 | BIT(NL80211_IFTYPE_ADHOC); | |
723 | ||
bde748a4 VN |
724 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
725 | ||
fb9987d0 S |
726 | hw->queues = 4; |
727 | hw->channel_change_time = 5000; | |
728 | hw->max_listen_interval = 10; | |
729 | hw->vif_data_size = sizeof(struct ath9k_htc_vif); | |
730 | hw->sta_data_size = sizeof(struct ath9k_htc_sta); | |
731 | ||
732 | /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */ | |
733 | hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) + | |
734 | sizeof(struct htc_frame_hdr) + 4; | |
735 | ||
d4659912 | 736 | if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
fb9987d0 S |
737 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
738 | &priv->sbands[IEEE80211_BAND_2GHZ]; | |
d4659912 | 739 | if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
ea46e644 S |
740 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
741 | &priv->sbands[IEEE80211_BAND_5GHZ]; | |
fb9987d0 S |
742 | |
743 | if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) { | |
d4659912 | 744 | if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
fb9987d0 S |
745 | setup_ht_cap(priv, |
746 | &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap); | |
d4659912 | 747 | if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
ea46e644 S |
748 | setup_ht_cap(priv, |
749 | &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap); | |
fb9987d0 S |
750 | } |
751 | ||
752 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
753 | } | |
754 | ||
21cb9879 | 755 | static int ath9k_init_device(struct ath9k_htc_priv *priv, |
fa6e15e0 | 756 | u16 devid, char *product, u32 drv_info) |
fb9987d0 S |
757 | { |
758 | struct ieee80211_hw *hw = priv->hw; | |
759 | struct ath_common *common; | |
760 | struct ath_hw *ah; | |
761 | int error = 0; | |
762 | struct ath_regulatory *reg; | |
763 | ||
764 | /* Bring up device */ | |
fa6e15e0 | 765 | error = ath9k_init_priv(priv, devid, product, drv_info); |
fb9987d0 S |
766 | if (error != 0) |
767 | goto err_init; | |
768 | ||
769 | ah = priv->ah; | |
770 | common = ath9k_hw_common(ah); | |
771 | ath9k_set_hw_capab(priv, hw); | |
772 | ||
773 | /* Initialize regulatory */ | |
774 | error = ath_regd_init(&common->regulatory, priv->hw->wiphy, | |
775 | ath9k_reg_notifier); | |
776 | if (error) | |
777 | goto err_regd; | |
778 | ||
779 | reg = &common->regulatory; | |
780 | ||
781 | /* Setup TX */ | |
782 | error = ath9k_tx_init(priv); | |
783 | if (error != 0) | |
784 | goto err_tx; | |
785 | ||
786 | /* Setup RX */ | |
787 | error = ath9k_rx_init(priv); | |
788 | if (error != 0) | |
789 | goto err_rx; | |
790 | ||
791 | /* Register with mac80211 */ | |
792 | error = ieee80211_register_hw(hw); | |
793 | if (error) | |
794 | goto err_register; | |
795 | ||
796 | /* Handle world regulatory */ | |
797 | if (!ath_is_world_regd(reg)) { | |
798 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
799 | if (error) | |
800 | goto err_world; | |
801 | } | |
802 | ||
803 | ath9k_init_leds(priv); | |
804 | ath9k_start_rfkill_poll(priv); | |
805 | ||
806 | return 0; | |
807 | ||
808 | err_world: | |
809 | ieee80211_unregister_hw(hw); | |
810 | err_register: | |
811 | ath9k_rx_cleanup(priv); | |
812 | err_rx: | |
813 | ath9k_tx_cleanup(priv); | |
814 | err_tx: | |
815 | /* Nothing */ | |
816 | err_regd: | |
817 | ath9k_deinit_priv(priv); | |
818 | err_init: | |
819 | return error; | |
820 | } | |
821 | ||
822 | int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev, | |
fa6e15e0 | 823 | u16 devid, char *product, u32 drv_info) |
fb9987d0 S |
824 | { |
825 | struct ieee80211_hw *hw; | |
826 | struct ath9k_htc_priv *priv; | |
827 | int ret; | |
828 | ||
829 | hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops); | |
830 | if (!hw) | |
831 | return -ENOMEM; | |
832 | ||
833 | priv = hw->priv; | |
834 | priv->hw = hw; | |
835 | priv->htc = htc_handle; | |
836 | priv->dev = dev; | |
837 | htc_handle->drv_priv = priv; | |
838 | SET_IEEE80211_DEV(hw, priv->dev); | |
839 | ||
840 | ret = ath9k_htc_wait_for_target(priv); | |
841 | if (ret) | |
842 | goto err_free; | |
843 | ||
844 | priv->wmi = ath9k_init_wmi(priv); | |
845 | if (!priv->wmi) { | |
846 | ret = -EINVAL; | |
847 | goto err_free; | |
848 | } | |
849 | ||
fa6e15e0 | 850 | ret = ath9k_init_htc_services(priv, devid, drv_info); |
fb9987d0 S |
851 | if (ret) |
852 | goto err_init; | |
853 | ||
fa6e15e0 | 854 | ret = ath9k_init_device(priv, devid, product, drv_info); |
fb9987d0 S |
855 | if (ret) |
856 | goto err_init; | |
857 | ||
858 | return 0; | |
859 | ||
860 | err_init: | |
861 | ath9k_deinit_wmi(priv); | |
862 | err_free: | |
863 | ieee80211_free_hw(hw); | |
864 | return ret; | |
865 | } | |
866 | ||
867 | void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug) | |
868 | { | |
869 | if (htc_handle->drv_priv) { | |
a3be14b7 S |
870 | |
871 | /* Check if the device has been yanked out. */ | |
872 | if (hotunplug) | |
97dcec57 | 873 | htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED; |
a3be14b7 | 874 | |
fb9987d0 S |
875 | ath9k_deinit_device(htc_handle->drv_priv); |
876 | ath9k_deinit_wmi(htc_handle->drv_priv); | |
877 | ieee80211_free_hw(htc_handle->drv_priv->hw); | |
878 | } | |
879 | } | |
880 | ||
881 | #ifdef CONFIG_PM | |
f933ebed SM |
882 | |
883 | void ath9k_htc_suspend(struct htc_target *htc_handle) | |
884 | { | |
885 | ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP); | |
886 | } | |
887 | ||
fb9987d0 S |
888 | int ath9k_htc_resume(struct htc_target *htc_handle) |
889 | { | |
fa6e15e0 | 890 | struct ath9k_htc_priv *priv = htc_handle->drv_priv; |
fb9987d0 S |
891 | int ret; |
892 | ||
fa6e15e0 | 893 | ret = ath9k_htc_wait_for_target(priv); |
fb9987d0 S |
894 | if (ret) |
895 | return ret; | |
896 | ||
fa6e15e0 | 897 | ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid, |
0b5ead91 | 898 | priv->ah->hw_version.usbdev); |
fb9987d0 S |
899 | return ret; |
900 | } | |
901 | #endif | |
902 | ||
903 | static int __init ath9k_htc_init(void) | |
904 | { | |
905 | int error; | |
906 | ||
e1572c5e | 907 | error = ath9k_htc_debug_create_root(); |
fb9987d0 S |
908 | if (error < 0) { |
909 | printk(KERN_ERR | |
910 | "ath9k_htc: Unable to create debugfs root: %d\n", | |
911 | error); | |
912 | goto err_dbg; | |
913 | } | |
914 | ||
915 | error = ath9k_hif_usb_init(); | |
916 | if (error < 0) { | |
917 | printk(KERN_ERR | |
918 | "ath9k_htc: No USB devices found," | |
919 | " driver not installed.\n"); | |
920 | error = -ENODEV; | |
921 | goto err_usb; | |
922 | } | |
923 | ||
924 | return 0; | |
925 | ||
926 | err_usb: | |
e1572c5e | 927 | ath9k_htc_debug_remove_root(); |
fb9987d0 S |
928 | err_dbg: |
929 | return error; | |
930 | } | |
931 | module_init(ath9k_htc_init); | |
932 | ||
933 | static void __exit ath9k_htc_exit(void) | |
934 | { | |
935 | ath9k_hif_usb_exit(); | |
e1572c5e | 936 | ath9k_htc_debug_remove_root(); |
fb9987d0 S |
937 | printk(KERN_INFO "ath9k_htc: Driver unloaded\n"); |
938 | } | |
939 | module_exit(ath9k_htc_exit); |