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ath9k: replace eeprom_param EEP_MINOR_REV with get_eeprom_rev
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / eeprom_def.c
CommitLineData
b5aec950 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
b5aec950
S		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
78fa99ab 17#include <asm/unaligned.h>
c46917bb 18#include "hw.h"
8fe65368 19#include "ar9002_phy.h"
b5aec950
S		 20
21static void ath9k_get_txgain_index(struct ath_hw *ah,
22 struct ath9k_channel *chan,
23 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
24 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
25{
26 u8 pcdac, i = 0;
27 u16 idxL = 0, idxR = 0, numPiers;
28 bool match;
29 struct chan_centers centers;
30
31 ath9k_hw_get_channel_centers(ah, chan, &centers);
32
33 for (numPiers = 0; numPiers < availPiers; numPiers++)
34 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
35 break;
36
37 match = ath9k_hw_get_lower_upper_index(
38 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
39 calChans, numPiers, &idxL, &idxR);
40 if (match) {
41 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
42 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
43 } else {
44 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
45 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
46 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
47 }
48
49 while (pcdac > ah->originalGain[i] &&
50 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
51 i++;
52
53 *pcdacIdx = i;
b5aec950
S		 54}
55
56static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
57 u32 initTxGain,
58 int txPower,
59 u8 *pPDADCValues)
60{
61 u32 i;
62 u32 offset;
63
64 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
65 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
66 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
67 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
68
69 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
70 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
71
72 offset = txPower;
73 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
74 if (i < offset)
75 pPDADCValues[i] = 0x0;
76 else
77 pPDADCValues[i] = 0xFF;
78}
79
80static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
81{
82 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
83}
84
85static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
86{
87 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
88}
89
b5aec950 90#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
04cf53f4
SM		 91
92static bool __ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
93{
b5aec950
S		 94 u16 *eep_data = (u16 *)&ah->eeprom.def;
95 int addr, ar5416_eep_start_loc = 0x100;
96
97 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
0e4b9f2f 98 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
2fd2cdfb 99 eep_data))
b5aec950 100 return false;
b5aec950
S		 101 eep_data++;
102 }
103 return true;
b5aec950
S		 104}
105
04cf53f4
SM		 106static bool __ath9k_hw_usb_def_fill_eeprom(struct ath_hw *ah)
107{
108 u16 *eep_data = (u16 *)&ah->eeprom.def;
109
110 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
111 0x100, SIZE_EEPROM_DEF);
112 return true;
113}
114
115static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
116{
117 struct ath_common *common = ath9k_hw_common(ah);
118
119 if (!ath9k_hw_use_flash(ah)) {
d2182b69 120 ath_dbg(common, EEPROM, "Reading from EEPROM, not flash\n");
04cf53f4
SM		 121 }
122
123 if (common->bus_ops->ath_bus_type == ATH_USB)
124 return __ath9k_hw_usb_def_fill_eeprom(ah);
125 else
126 return __ath9k_hw_def_fill_eeprom(ah);
127}
128
1b37d3e6
RM		 129#if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
130static u32 ath9k_def_dump_modal_eeprom(char *buf, u32 len, u32 size,
131 struct modal_eep_header *modal_hdr)
132{
133 PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
134 PR_EEP("Chain1 Ant. Control", modal_hdr->antCtrlChain[1]);
135 PR_EEP("Chain2 Ant. Control", modal_hdr->antCtrlChain[2]);
136 PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
137 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
138 PR_EEP("Chain1 Ant. Gain", modal_hdr->antennaGainCh[1]);
139 PR_EEP("Chain2 Ant. Gain", modal_hdr->antennaGainCh[2]);
140 PR_EEP("Switch Settle", modal_hdr->switchSettling);
141 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
142 PR_EEP("Chain1 TxRxAtten", modal_hdr->txRxAttenCh[1]);
143 PR_EEP("Chain2 TxRxAtten", modal_hdr->txRxAttenCh[2]);
144 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
145 PR_EEP("Chain1 RxTxMargin", modal_hdr->rxTxMarginCh[1]);
146 PR_EEP("Chain2 RxTxMargin", modal_hdr->rxTxMarginCh[2]);
147 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
148 PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize);
149 PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]);
150 PR_EEP("Chain1 xlna Gain", modal_hdr->xlnaGainCh[1]);
151 PR_EEP("Chain2 xlna Gain", modal_hdr->xlnaGainCh[2]);
152 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
153 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
154 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
155 PR_EEP("CCA Threshold)", modal_hdr->thresh62);
156 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
157 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
158 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
159 PR_EEP("xpdGain", modal_hdr->xpdGain);
160 PR_EEP("External PD", modal_hdr->xpd);
161 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
162 PR_EEP("Chain1 I Coefficient", modal_hdr->iqCalICh[1]);
163 PR_EEP("Chain2 I Coefficient", modal_hdr->iqCalICh[2]);
164 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
165 PR_EEP("Chain1 Q Coefficient", modal_hdr->iqCalQCh[1]);
166 PR_EEP("Chain2 Q Coefficient", modal_hdr->iqCalQCh[2]);
167 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
168 PR_EEP("Chain0 OutputBias", modal_hdr->ob);
169 PR_EEP("Chain0 DriverBias", modal_hdr->db);
170 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
171 PR_EEP("2chain pwr decrease", modal_hdr->pwrDecreaseFor2Chain);
172 PR_EEP("3chain pwr decrease", modal_hdr->pwrDecreaseFor3Chain);
173 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
174 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
175 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
176 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
177 PR_EEP("Chain1 bswAtten", modal_hdr->bswAtten[1]);
178 PR_EEP("Chain2 bswAtten", modal_hdr->bswAtten[2]);
179 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
180 PR_EEP("Chain1 bswMargin", modal_hdr->bswMargin[1]);
181 PR_EEP("Chain2 bswMargin", modal_hdr->bswMargin[2]);
182 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
183 PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]);
184 PR_EEP("Chain1 xatten2Db", modal_hdr->xatten2Db[1]);
185 PR_EEP("Chain2 xatten2Db", modal_hdr->xatten2Db[2]);
186 PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]);
187 PR_EEP("Chain1 xatten2Margin", modal_hdr->xatten2Margin[1]);
188 PR_EEP("Chain2 xatten2Margin", modal_hdr->xatten2Margin[2]);
189 PR_EEP("Chain1 OutputBias", modal_hdr->ob_ch1);
190 PR_EEP("Chain1 DriverBias", modal_hdr->db_ch1);
191 PR_EEP("LNA Control", modal_hdr->lna_ctl);
192 PR_EEP("XPA Bias Freq0", modal_hdr->xpaBiasLvlFreq[0]);
193 PR_EEP("XPA Bias Freq1", modal_hdr->xpaBiasLvlFreq[1]);
194 PR_EEP("XPA Bias Freq2", modal_hdr->xpaBiasLvlFreq[2]);
195
196 return len;
197}
198
199static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
200 u8 *buf, u32 len, u32 size)
201{
202 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
203 struct base_eep_header *pBase = &eep->baseEepHeader;
204
205 if (!dump_base_hdr) {
5e88ba62
ZK		 206 len += scnprintf(buf + len, size - len,
207 "%20s :\n", "2GHz modal Header");
d25360b1 208 len = ath9k_def_dump_modal_eeprom(buf, len, size,
1b37d3e6 209 &eep->modalHeader[0]);
5e88ba62
ZK		 210 len += scnprintf(buf + len, size - len,
211 "%20s :\n", "5GHz modal Header");
d25360b1 212 len = ath9k_def_dump_modal_eeprom(buf, len, size,
1b37d3e6
RM		 213 &eep->modalHeader[1]);
214 goto out;
215 }
216
217 PR_EEP("Major Version", pBase->version >> 12);
218 PR_EEP("Minor Version", pBase->version & 0xFFF);
219 PR_EEP("Checksum", pBase->checksum);
220 PR_EEP("Length", pBase->length);
221 PR_EEP("RegDomain1", pBase->regDmn[0]);
222 PR_EEP("RegDomain2", pBase->regDmn[1]);
223 PR_EEP("TX Mask", pBase->txMask);
224 PR_EEP("RX Mask", pBase->rxMask);
225 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
226 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
227 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
228 AR5416_OPFLAGS_N_2G_HT20));
229 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
230 AR5416_OPFLAGS_N_2G_HT40));
231 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
232 AR5416_OPFLAGS_N_5G_HT20));
233 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
234 AR5416_OPFLAGS_N_5G_HT40));
81a834e3 235 PR_EEP("Big Endian", !!(pBase->eepMisc & AR5416_EEPMISC_BIG_ENDIAN));
1b37d3e6
RM		 236 PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
237 PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
238 PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
239 PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl);
240
5e88ba62
ZK		 241 len += scnprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
242 pBase->macAddr);
1b37d3e6
RM		 243
244out:
245 if (len > size)
246 len = size;
247
248 return len;
249}
250#else
251static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
252 u8 *buf, u32 len, u32 size)
253{
254 return 0;
255}
256#endif
257
b5aec950
S		 258static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
259{
2c208890 260 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
c46917bb 261 struct ath_common *common = ath9k_hw_common(ah);
6fa658fd
MB		 262 u32 el;
263 bool need_swap;
264 int i, err;
b5aec950 265
6fa658fd
MB		 266 err = ath9k_hw_nvram_swap_data(ah, &need_swap, SIZE_EEPROM_DEF);
267 if (err)
268 return err;
b5aec950
S		 269
270 if (need_swap)
6fa658fd 271 el = swab16(eep->baseEepHeader.length);
b5aec950 272 else
6fa658fd 273 el = eep->baseEepHeader.length;
b5aec950 274
6fa658fd
MB		 275 el = min(el / sizeof(u16), SIZE_EEPROM_DEF);
276 if (!ath9k_hw_nvram_validate_checksum(ah, el))
277 return -EINVAL;
b5aec950
S		 278
279 if (need_swap) {
280 u32 integer, j;
281 u16 word;
282
b5aec950
S		 283 word = swab16(eep->baseEepHeader.length);
284 eep->baseEepHeader.length = word;
285
286 word = swab16(eep->baseEepHeader.checksum);
287 eep->baseEepHeader.checksum = word;
288
289 word = swab16(eep->baseEepHeader.version);
290 eep->baseEepHeader.version = word;
291
292 word = swab16(eep->baseEepHeader.regDmn[0]);
293 eep->baseEepHeader.regDmn[0] = word;
294
295 word = swab16(eep->baseEepHeader.regDmn[1]);
296 eep->baseEepHeader.regDmn[1] = word;
297
298 word = swab16(eep->baseEepHeader.rfSilent);
299 eep->baseEepHeader.rfSilent = word;
300
301 word = swab16(eep->baseEepHeader.blueToothOptions);
302 eep->baseEepHeader.blueToothOptions = word;
303
304 word = swab16(eep->baseEepHeader.deviceCap);
305 eep->baseEepHeader.deviceCap = word;
306
307 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
308 struct modal_eep_header *pModal =
309 &eep->modalHeader[j];
310 integer = swab32(pModal->antCtrlCommon);
311 pModal->antCtrlCommon = integer;
312
313 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
314 integer = swab32(pModal->antCtrlChain[i]);
315 pModal->antCtrlChain[i] = integer;
316 }
25f63a5a
AC		 317 for (i = 0; i < 3; i++) {
318 word = swab16(pModal->xpaBiasLvlFreq[i]);
319 pModal->xpaBiasLvlFreq[i] = word;
320 }
b5aec950 321
4ddfcd7d 322 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
b5aec950
S		 323 word = swab16(pModal->spurChans[i].spurChan);
324 pModal->spurChans[i].spurChan = word;
325 }
326 }
327 }
328
6fa658fd
MB		 329 if (!ath9k_hw_nvram_check_version(ah, AR5416_EEP_VER,
330 AR5416_EEP_NO_BACK_VER))
b5aec950 331 return -EINVAL;
b5aec950 332
57b98384 333 /* Enable fixup for AR_AN_TOP2 if necessary */
4d906740
SM		 334 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
335 ((eep->baseEepHeader.version & 0xff) > 0x0a) &&
336 (eep->baseEepHeader.pwdclkind == 0))
3db1cd5c 337 ah->need_an_top2_fixup = true;
57b98384 338
69bdacc8
SM		 339 if ((common->bus_ops->ath_bus_type == ATH_USB) &&
340 (AR_SREV_9280(ah)))
341 eep->modalHeader[0].xpaBiasLvl = 0;
342
b5aec950
S		 343 return 0;
344}
345
6fa658fd
MB		 346#undef SIZE_EEPROM_DEF
347
b5aec950
S		 348static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
349 enum eeprom_param param)
350{
351 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
352 struct modal_eep_header *pModal = eep->modalHeader;
353 struct base_eep_header *pBase = &eep->baseEepHeader;
ca2c68cc 354 int band = 0;
b5aec950
S		 355
356 switch (param) {
357 case EEP_NFTHRESH_5:
358 return pModal[0].noiseFloorThreshCh[0];
359 case EEP_NFTHRESH_2:
360 return pModal[1].noiseFloorThreshCh[0];
49101676 361 case EEP_MAC_LSW:
78fa99ab 362 return get_unaligned_be16(pBase->macAddr);
49101676 363 case EEP_MAC_MID:
78fa99ab 364 return get_unaligned_be16(pBase->macAddr + 2);
49101676 365 case EEP_MAC_MSW:
78fa99ab 366 return get_unaligned_be16(pBase->macAddr + 4);
b5aec950
S		 367 case EEP_REG_0:
368 return pBase->regDmn[0];
b5aec950
S		 369 case EEP_OP_CAP:
370 return pBase->deviceCap;
371 case EEP_OP_MODE:
372 return pBase->opCapFlags;
373 case EEP_RF_SILENT:
374 return pBase->rfSilent;
375 case EEP_OB_5:
376 return pModal[0].ob;
377 case EEP_DB_5:
378 return pModal[0].db;
379 case EEP_OB_2:
380 return pModal[1].ob;
381 case EEP_DB_2:
382 return pModal[1].db;
b5aec950
S		 383 case EEP_TX_MASK:
384 return pBase->txMask;
385 case EEP_RX_MASK:
386 return pBase->rxMask;
5b75d0fc
FF		 387 case EEP_FSTCLK_5G:
388 return pBase->fastClk5g;
b5aec950
S		 389 case EEP_RXGAIN_TYPE:
390 return pBase->rxGainType;
391 case EEP_TXGAIN_TYPE:
392 return pBase->txGainType;
393 case EEP_OL_PWRCTRL:
394 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
395 return pBase->openLoopPwrCntl ? true : false;
396 else
397 return false;
398 case EEP_RC_CHAIN_MASK:
399 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
400 return pBase->rcChainMask;
401 else
402 return 0;
403 case EEP_DAC_HPWR_5G:
404 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
405 return pBase->dacHiPwrMode_5G;
406 else
407 return 0;
408 case EEP_FRAC_N_5G:
409 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
410 return pBase->frac_n_5g;
411 else
412 return 0;
e41f0bfc
SB		 413 case EEP_PWR_TABLE_OFFSET:
414 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
415 return pBase->pwr_table_offset;
416 else
417 return AR5416_PWR_TABLE_OFFSET_DB;
ca2c68cc
FF		 418 case EEP_ANTENNA_GAIN_2G:
419 band = 1;
420 /* fall through */
421 case EEP_ANTENNA_GAIN_5G:
422 return max_t(u8, max_t(u8,
423 pModal[band].antennaGainCh[0],
424 pModal[band].antennaGainCh[1]),
425 pModal[band].antennaGainCh[2]);
b5aec950
S		 426 default:
427 return 0;
428 }
429}
430
431static void ath9k_hw_def_set_gain(struct ath_hw *ah,
432 struct modal_eep_header *pModal,
433 struct ar5416_eeprom_def *eep,
434 u8 txRxAttenLocal, int regChainOffset, int i)
435{
eaa4059d 436 ENABLE_REG_RMW_BUFFER(ah);
b5aec950
S		 437 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
438 txRxAttenLocal = pModal->txRxAttenCh[i];
439
7a37081e 440 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950
S		 441 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
442 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
443 pModal->bswMargin[i]);
444 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
445 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
446 pModal->bswAtten[i]);
447 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
448 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
449 pModal->xatten2Margin[i]);
450 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
451 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
452 pModal->xatten2Db[i]);
453 } else {
eaa4059d
OR		 454 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
455 SM(pModal-> bswMargin[i], AR_PHY_GAIN_2GHZ_BSW_MARGIN),
456 AR_PHY_GAIN_2GHZ_BSW_MARGIN);
457 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
458 SM(pModal->bswAtten[i], AR_PHY_GAIN_2GHZ_BSW_ATTEN),
459 AR_PHY_GAIN_2GHZ_BSW_ATTEN);
b5aec950
S		 460 }
461 }
462
7a37081e 463 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950
S		 464 REG_RMW_FIELD(ah,
465 AR_PHY_RXGAIN + regChainOffset,
466 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
467 REG_RMW_FIELD(ah,
468 AR_PHY_RXGAIN + regChainOffset,
469 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
470 } else {
eaa4059d
OR		 471 REG_RMW(ah, AR_PHY_RXGAIN + regChainOffset,
472 SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN),
473 AR_PHY_RXGAIN_TXRX_ATTEN);
474 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
475 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN),
476 AR_PHY_GAIN_2GHZ_RXTX_MARGIN);
b5aec950 477 }
eaa4059d 478 REG_RMW_BUFFER_FLUSH(ah);
b5aec950
S		 479}
480
481static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
482 struct ath9k_channel *chan)
483{
484 struct modal_eep_header *pModal;
485 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
486 int i, regChainOffset;
487 u8 txRxAttenLocal;
488
489 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
490 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
491
df3c8b2b 492 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
b5aec950
S		 493
494 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
495 if (AR_SREV_9280(ah)) {
496 if (i >= 2)
497 break;
498 }
499
1b8714f7 500 if ((ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
b5aec950
S		 501 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
502 else
503 regChainOffset = i * 0x1000;
504
505 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
506 pModal->antCtrlChain[i]);
507
508 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
509 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
510 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
511 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
512 SM(pModal->iqCalICh[i],
513 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
514 SM(pModal->iqCalQCh[i],
515 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
516
1b8714f7
FF		 517 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
518 regChainOffset, i);
b5aec950
S		 519 }
520
7a37081e 521 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950
S		 522 if (IS_CHAN_2GHZ(chan)) {
523 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
524 AR_AN_RF2G1_CH0_OB,
525 AR_AN_RF2G1_CH0_OB_S,
526 pModal->ob);
527 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
528 AR_AN_RF2G1_CH0_DB,
529 AR_AN_RF2G1_CH0_DB_S,
530 pModal->db);
531 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
532 AR_AN_RF2G1_CH1_OB,
533 AR_AN_RF2G1_CH1_OB_S,
534 pModal->ob_ch1);
535 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
536 AR_AN_RF2G1_CH1_DB,
537 AR_AN_RF2G1_CH1_DB_S,
538 pModal->db_ch1);
539 } else {
540 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
541 AR_AN_RF5G1_CH0_OB5,
542 AR_AN_RF5G1_CH0_OB5_S,
543 pModal->ob);
544 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
545 AR_AN_RF5G1_CH0_DB5,
546 AR_AN_RF5G1_CH0_DB5_S,
547 pModal->db);
548 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
549 AR_AN_RF5G1_CH1_OB5,
550 AR_AN_RF5G1_CH1_OB5_S,
551 pModal->ob_ch1);
552 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
553 AR_AN_RF5G1_CH1_DB5,
554 AR_AN_RF5G1_CH1_DB5_S,
555 pModal->db_ch1);
556 }
557 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
558 AR_AN_TOP2_XPABIAS_LVL,
559 AR_AN_TOP2_XPABIAS_LVL_S,
560 pModal->xpaBiasLvl);
561 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
562 AR_AN_TOP2_LOCALBIAS,
563 AR_AN_TOP2_LOCALBIAS_S,
f67e07eb
FF		 564 !!(pModal->lna_ctl &
565 LNA_CTL_LOCAL_BIAS));
b5aec950 566 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
f67e07eb 567 !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
b5aec950
S		 568 }
569
570 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
571 pModal->switchSettling);
572 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
573 pModal->adcDesiredSize);
574
7a37081e 575 if (!AR_SREV_9280_20_OR_LATER(ah))
b5aec950
S		 576 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
577 AR_PHY_DESIRED_SZ_PGA,
578 pModal->pgaDesiredSize);
579
580 REG_WRITE(ah, AR_PHY_RF_CTL4,
581 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
582 | SM(pModal->txEndToXpaOff,
583 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
584 | SM(pModal->txFrameToXpaOn,
585 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
586 | SM(pModal->txFrameToXpaOn,
587 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
588
589 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
590 pModal->txEndToRxOn);
591
7a37081e 592 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950
S		 593 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
594 pModal->thresh62);
595 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
596 AR_PHY_EXT_CCA0_THRESH62,
597 pModal->thresh62);
598 } else {
599 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
600 pModal->thresh62);
601 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
602 AR_PHY_EXT_CCA_THRESH62,
603 pModal->thresh62);
604 }
605
606 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
607 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
608 AR_PHY_TX_END_DATA_START,
609 pModal->txFrameToDataStart);
610 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
611 pModal->txFrameToPaOn);
612 }
613
614 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
615 if (IS_CHAN_HT40(chan))
616 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
617 AR_PHY_SETTLING_SWITCH,
618 pModal->swSettleHt40);
619 }
620
621 if (AR_SREV_9280_20_OR_LATER(ah) &&
622 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
623 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
624 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
625 pModal->miscBits);
626
627
628 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
629 if (IS_CHAN_2GHZ(chan))
630 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
631 eep->baseEepHeader.dacLpMode);
632 else if (eep->baseEepHeader.dacHiPwrMode_5G)
633 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
634 else
635 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
636 eep->baseEepHeader.dacLpMode);
637
d865ca6c
SB		 638 udelay(100);
639
b5aec950
S		 640 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
641 pModal->miscBits >> 2);
642
643 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
644 AR_PHY_TX_DESIRED_SCALE_CCK,
645 eep->baseEepHeader.desiredScaleCCK);
646 }
647}
648
649static void ath9k_hw_def_set_addac(struct ath_hw *ah,
650 struct ath9k_channel *chan)
651{
652#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
653 struct modal_eep_header *pModal;
654 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
655 u8 biaslevel;
656
657 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
658 return;
659
660 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
661 return;
662
663 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
664
665 if (pModal->xpaBiasLvl != 0xff) {
666 biaslevel = pModal->xpaBiasLvl;
667 } else {
668 u16 resetFreqBin, freqBin, freqCount = 0;
669 struct chan_centers centers;
670
671 ath9k_hw_get_channel_centers(ah, chan, &centers);
672
673 resetFreqBin = FREQ2FBIN(centers.synth_center,
674 IS_CHAN_2GHZ(chan));
675 freqBin = XPA_LVL_FREQ(0) & 0xff;
676 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
677
678 freqCount++;
679
680 while (freqCount < 3) {
681 if (XPA_LVL_FREQ(freqCount) == 0x0)
682 break;
683
684 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
685 if (resetFreqBin >= freqBin)
686 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
687 else
688 break;
689 freqCount++;
690 }
691 }
692
693 if (IS_CHAN_2GHZ(chan)) {
694 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
695 7, 1) & (~0x18)) | biaslevel << 3;
696 } else {
697 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
698 6, 1) & (~0xc0)) | biaslevel << 6;
699 }
700#undef XPA_LVL_FREQ
701}
702
e41f0bfc
SB		 703static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
704 u16 *gb,
705 u16 numXpdGain,
706 u16 pdGainOverlap_t2,
707 int8_t pwr_table_offset,
708 int16_t *diff)
709
710{
711 u16 k;
712
713 /* Prior to writing the boundaries or the pdadc vs. power table
714 * into the chip registers the default starting point on the pdadc
715 * vs. power table needs to be checked and the curve boundaries
716 * adjusted accordingly
717 */
718 if (AR_SREV_9280_20_OR_LATER(ah)) {
719 u16 gb_limit;
720
721 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
722 /* get the difference in dB */
723 *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
724 /* get the number of half dB steps */
725 *diff *= 2;
726 /* change the original gain boundary settings
727 * by the number of half dB steps
728 */
729 for (k = 0; k < numXpdGain; k++)
730 gb[k] = (u16)(gb[k] - *diff);
731 }
732 /* Because of a hardware limitation, ensure the gain boundary
733 * is not larger than (63 - overlap)
734 */
4ddfcd7d 735 gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
e41f0bfc
SB		 736
737 for (k = 0; k < numXpdGain; k++)
738 gb[k] = (u16)min(gb_limit, gb[k]);
739 }
740
741 return *diff;
742}
743
744static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
745 int8_t pwr_table_offset,
746 int16_t diff,
747 u8 *pdadcValues)
748{
749#define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
750 u16 k;
751
752 /* If this is a board that has a pwrTableOffset that differs from
753 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
754 * pdadc vs pwr table needs to be adjusted prior to writing to the
755 * chip.
756 */
757 if (AR_SREV_9280_20_OR_LATER(ah)) {
758 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
759 /* shift the table to start at the new offset */
760 for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
761 pdadcValues[k] = pdadcValues[k + diff];
762 }
763
764 /* fill the back of the table */
765 for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
766 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
767 }
768 }
769 }
770#undef NUM_PDADC
771}
772
b5aec950 773static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
e832bf10 774 struct ath9k_channel *chan)
b5aec950
S		 775{
776#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
777#define SM_PDGAIN_B(x, y) \
778 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
c46917bb 779 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 780 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
781 struct cal_data_per_freq *pRawDataset;
782 u8 *pCalBChans = NULL;
783 u16 pdGainOverlap_t2;
784 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
785 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
786 u16 numPiers, i, j;
6eb90d46 787 int16_t diff = 0;
b5aec950
S		 788 u16 numXpdGain, xpdMask;
789 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
790 u32 reg32, regOffset, regChainOffset;
791 int16_t modalIdx;
e41f0bfc 792 int8_t pwr_table_offset;
b5aec950
S		 793
794 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
795 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
796
e41f0bfc
SB		 797 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
798
b5aec950
S		 799 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
800 AR5416_EEP_MINOR_VER_2) {
801 pdGainOverlap_t2 =
802 pEepData->modalHeader[modalIdx].pdGainOverlap;
803 } else {
804 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
805 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
806 }
807
808 if (IS_CHAN_2GHZ(chan)) {
809 pCalBChans = pEepData->calFreqPier2G;
810 numPiers = AR5416_NUM_2G_CAL_PIERS;
811 } else {
812 pCalBChans = pEepData->calFreqPier5G;
813 numPiers = AR5416_NUM_5G_CAL_PIERS;
814 }
815
816 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
817 pRawDataset = pEepData->calPierData2G[0];
818 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
819 pRawDataset)->vpdPdg[0][0];
820 }
821
822 numXpdGain = 0;
823
824 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
825 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
826 if (numXpdGain >= AR5416_NUM_PD_GAINS)
827 break;
828 xpdGainValues[numXpdGain] =
829 (u16)(AR5416_PD_GAINS_IN_MASK - i);
830 numXpdGain++;
831 }
832 }
833
834 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
835 (numXpdGain - 1) & 0x3);
836 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
837 xpdGainValues[0]);
838 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
839 xpdGainValues[1]);
840 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
841 xpdGainValues[2]);
842
843 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1b8714f7 844 if ((ah->rxchainmask == 5 || ah->txchainmask == 5) &&
b5aec950
S		 845 (i != 0)) {
846 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
847 } else
848 regChainOffset = i * 0x1000;
849
850 if (pEepData->baseEepHeader.txMask & (1 << i)) {
851 if (IS_CHAN_2GHZ(chan))
852 pRawDataset = pEepData->calPierData2G[i];
853 else
854 pRawDataset = pEepData->calPierData5G[i];
855
856
857 if (OLC_FOR_AR9280_20_LATER) {
858 u8 pcdacIdx;
859 u8 txPower;
860
861 ath9k_get_txgain_index(ah, chan,
862 (struct calDataPerFreqOpLoop *)pRawDataset,
863 pCalBChans, numPiers, &txPower, &pcdacIdx);
864 ath9k_olc_get_pdadcs(ah, pcdacIdx,
865 txPower/2, pdadcValues);
866 } else {
115277a3 867 ath9k_hw_get_gain_boundaries_pdadcs(ah,
b5aec950
S		 868 chan, pRawDataset,
869 pCalBChans, numPiers,
870 pdGainOverlap_t2,
b5aec950
S		 871 gainBoundaries,
872 pdadcValues,
873 numXpdGain);
874 }
875
e41f0bfc
SB		 876 diff = ath9k_change_gain_boundary_setting(ah,
877 gainBoundaries,
878 numXpdGain,
879 pdGainOverlap_t2,
880 pwr_table_offset,
881 &diff);
882
e7fc6338
RM		 883 ENABLE_REGWRITE_BUFFER(ah);
884
1b8714f7
FF		 885 if (OLC_FOR_AR9280_20_LATER) {
886 REG_WRITE(ah,
887 AR_PHY_TPCRG5 + regChainOffset,
888 SM(0x6,
889 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
890 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
891 SM_PD_GAIN(3) | SM_PD_GAIN(4));
892 } else {
893 REG_WRITE(ah,
894 AR_PHY_TPCRG5 + regChainOffset,
895 SM(pdGainOverlap_t2,
896 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
897 SM_PDGAIN_B(0, 1) |
898 SM_PDGAIN_B(1, 2) |
899 SM_PDGAIN_B(2, 3) |
900 SM_PDGAIN_B(3, 4));
b5aec950
S		 901 }
902
e41f0bfc
SB		 903 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
904 diff, pdadcValues);
905
b5aec950
S		 906 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
907 for (j = 0; j < 32; j++) {
78fa99ab 908 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
b5aec950
S		 909 REG_WRITE(ah, regOffset, reg32);
910
d2182b69 911 ath_dbg(common, EEPROM,
226afe68
JP		 912 "PDADC (%d,%4x): %4.4x %8.8x\n",
913 i, regChainOffset, regOffset,
914 reg32);
d2182b69
JP		 915 ath_dbg(common, EEPROM,
916 "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n",
226afe68
JP		 917 i, 4 * j, pdadcValues[4 * j],
918 4 * j + 1, pdadcValues[4 * j + 1],
919 4 * j + 2, pdadcValues[4 * j + 2],
920 4 * j + 3, pdadcValues[4 * j + 3]);
b5aec950
S		 921
922 regOffset += 4;
923 }
e7fc6338 924 REGWRITE_BUFFER_FLUSH(ah);
b5aec950
S		 925 }
926 }
927
b5aec950
S		 928#undef SM_PD_GAIN
929#undef SM_PDGAIN_B
930}
931
932static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
933 struct ath9k_channel *chan,
934 int16_t *ratesArray,
935 u16 cfgCtl,
ca2c68cc 936 u16 antenna_reduction,
b5aec950
S		 937 u16 powerLimit)
938{
b5aec950 939 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
a261f0e9 940 u16 twiceMaxEdgePower;
b5aec950 941 int i;
b5aec950
S		 942 struct cal_ctl_data *rep;
943 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
944 0, { 0, 0, 0, 0}
945 };
946 struct cal_target_power_leg targetPowerOfdmExt = {
947 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
948 0, { 0, 0, 0, 0 }
949 };
950 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
951 0, {0, 0, 0, 0}
952 };
ca2c68cc 953 u16 scaledPower = 0, minCtlPower;
07b2fa5a
JP		 954 static const u16 ctlModesFor11a[] = {
955 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
956 };
957 static const u16 ctlModesFor11g[] = {
958 CTL_11B, CTL_11G, CTL_2GHT20,
959 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
960 };
961 u16 numCtlModes;
962 const u16 *pCtlMode;
963 u16 ctlMode, freq;
b5aec950
S		 964 struct chan_centers centers;
965 int tx_chainmask;
966 u16 twiceMinEdgePower;
967
968 tx_chainmask = ah->txchainmask;
969
970 ath9k_hw_get_channel_centers(ah, chan, &centers);
971
ea6f792b
GJ		 972 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
973 antenna_reduction);
b5aec950 974
b5aec950
S		 975 if (IS_CHAN_2GHZ(chan)) {
976 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
977 SUB_NUM_CTL_MODES_AT_2G_40;
978 pCtlMode = ctlModesFor11g;
979
980 ath9k_hw_get_legacy_target_powers(ah, chan,
981 pEepData->calTargetPowerCck,
982 AR5416_NUM_2G_CCK_TARGET_POWERS,
983 &targetPowerCck, 4, false);
984 ath9k_hw_get_legacy_target_powers(ah, chan,
985 pEepData->calTargetPower2G,
986 AR5416_NUM_2G_20_TARGET_POWERS,
987 &targetPowerOfdm, 4, false);
988 ath9k_hw_get_target_powers(ah, chan,
989 pEepData->calTargetPower2GHT20,
990 AR5416_NUM_2G_20_TARGET_POWERS,
991 &targetPowerHt20, 8, false);
992
993 if (IS_CHAN_HT40(chan)) {
994 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
995 ath9k_hw_get_target_powers(ah, chan,
996 pEepData->calTargetPower2GHT40,
997 AR5416_NUM_2G_40_TARGET_POWERS,
998 &targetPowerHt40, 8, true);
999 ath9k_hw_get_legacy_target_powers(ah, chan,
1000 pEepData->calTargetPowerCck,
1001 AR5416_NUM_2G_CCK_TARGET_POWERS,
1002 &targetPowerCckExt, 4, true);
1003 ath9k_hw_get_legacy_target_powers(ah, chan,
1004 pEepData->calTargetPower2G,
1005 AR5416_NUM_2G_20_TARGET_POWERS,
1006 &targetPowerOfdmExt, 4, true);
1007 }
1008 } else {
1009 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1010 SUB_NUM_CTL_MODES_AT_5G_40;
1011 pCtlMode = ctlModesFor11a;
1012
1013 ath9k_hw_get_legacy_target_powers(ah, chan,
1014 pEepData->calTargetPower5G,
1015 AR5416_NUM_5G_20_TARGET_POWERS,
1016 &targetPowerOfdm, 4, false);
1017 ath9k_hw_get_target_powers(ah, chan,
1018 pEepData->calTargetPower5GHT20,
1019 AR5416_NUM_5G_20_TARGET_POWERS,
1020 &targetPowerHt20, 8, false);
1021
1022 if (IS_CHAN_HT40(chan)) {
1023 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1024 ath9k_hw_get_target_powers(ah, chan,
1025 pEepData->calTargetPower5GHT40,
1026 AR5416_NUM_5G_40_TARGET_POWERS,
1027 &targetPowerHt40, 8, true);
1028 ath9k_hw_get_legacy_target_powers(ah, chan,
1029 pEepData->calTargetPower5G,
1030 AR5416_NUM_5G_20_TARGET_POWERS,
1031 &targetPowerOfdmExt, 4, true);
1032 }
1033 }
1034
1035 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1036 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1037 (pCtlMode[ctlMode] == CTL_2GHT40);
1038 if (isHt40CtlMode)
1039 freq = centers.synth_center;
1040 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1041 freq = centers.ext_center;
1042 else
1043 freq = centers.ctl_center;
1044
a261f0e9 1045 twiceMaxEdgePower = MAX_RATE_POWER;
b5aec950
S		 1046
1047 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1048 if ((((cfgCtl & ~CTL_MODE_M) |
1049 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1050 pEepData->ctlIndex[i]) ||
1051 (((cfgCtl & ~CTL_MODE_M) |
1052 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1053 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1054 rep = &(pEepData->ctlData[i]);
1055
1056 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1057 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1058 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1059
1060 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1061 twiceMaxEdgePower = min(twiceMaxEdgePower,
1062 twiceMinEdgePower);
1063 } else {
1064 twiceMaxEdgePower = twiceMinEdgePower;
1065 break;
1066 }
1067 }
1068 }
1069
1070 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1071
1072 switch (pCtlMode[ctlMode]) {
1073 case CTL_11B:
1074 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1075 targetPowerCck.tPow2x[i] =
1076 min((u16)targetPowerCck.tPow2x[i],
1077 minCtlPower);
1078 }
1079 break;
1080 case CTL_11A:
1081 case CTL_11G:
1082 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1083 targetPowerOfdm.tPow2x[i] =
1084 min((u16)targetPowerOfdm.tPow2x[i],
1085 minCtlPower);
1086 }
1087 break;
1088 case CTL_5GHT20:
1089 case CTL_2GHT20:
1090 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1091 targetPowerHt20.tPow2x[i] =
1092 min((u16)targetPowerHt20.tPow2x[i],
1093 minCtlPower);
1094 }
1095 break;
1096 case CTL_11B_EXT:
1097 targetPowerCckExt.tPow2x[0] = min((u16)
1098 targetPowerCckExt.tPow2x[0],
1099 minCtlPower);
1100 break;
1101 case CTL_11A_EXT:
1102 case CTL_11G_EXT:
1103 targetPowerOfdmExt.tPow2x[0] = min((u16)
1104 targetPowerOfdmExt.tPow2x[0],
1105 minCtlPower);
1106 break;
1107 case CTL_5GHT40:
1108 case CTL_2GHT40:
1109 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1110 targetPowerHt40.tPow2x[i] =
1111 min((u16)targetPowerHt40.tPow2x[i],
1112 minCtlPower);
1113 }
1114 break;
1115 default:
1116 break;
1117 }
1118 }
1119
1120 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1121 ratesArray[rate18mb] = ratesArray[rate24mb] =
1122 targetPowerOfdm.tPow2x[0];
1123 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1124 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1125 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1126 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1127
1128 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1129 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1130
1131 if (IS_CHAN_2GHZ(chan)) {
1132 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1133 ratesArray[rate2s] = ratesArray[rate2l] =
1134 targetPowerCck.tPow2x[1];
1135 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1136 targetPowerCck.tPow2x[2];
1137 ratesArray[rate11s] = ratesArray[rate11l] =
1138 targetPowerCck.tPow2x[3];
1139 }
1140 if (IS_CHAN_HT40(chan)) {
1141 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1142 ratesArray[rateHt40_0 + i] =
1143 targetPowerHt40.tPow2x[i];
1144 }
1145 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1146 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1147 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1148 if (IS_CHAN_2GHZ(chan)) {
1149 ratesArray[rateExtCck] =
1150 targetPowerCckExt.tPow2x[0];
1151 }
1152 }
1153}
1154
1155static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1156 struct ath9k_channel *chan,
1157 u16 cfgCtl,
1158 u8 twiceAntennaReduction,
de40f316 1159 u8 powerLimit, bool test)
b5aec950
S		 1160{
1161#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
608b88cb 1162 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 1163 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1164 struct modal_eep_header *pModal =
1165 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1166 int16_t ratesArray[Ar5416RateSize];
b5aec950
S		 1167 u8 ht40PowerIncForPdadc = 2;
1168 int i, cck_ofdm_delta = 0;
1169
1170 memset(ratesArray, 0, sizeof(ratesArray));
1171
1172 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1173 AR5416_EEP_MINOR_VER_2) {
1174 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1175 }
1176
1177 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1178 &ratesArray[0], cfgCtl,
1179 twiceAntennaReduction,
b5aec950
S		 1180 powerLimit);
1181
e832bf10 1182 ath9k_hw_set_def_power_cal_table(ah, chan);
b5aec950 1183
de40f316 1184 regulatory->max_power_level = 0;
b5aec950 1185 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
4ddfcd7d
FF		 1186 if (ratesArray[i] > MAX_RATE_POWER)
1187 ratesArray[i] = MAX_RATE_POWER;
de40f316
FF		 1188 if (ratesArray[i] > regulatory->max_power_level)
1189 regulatory->max_power_level = ratesArray[i];
b5aec950
S		 1190 }
1191
d9e9145e 1192 ath9k_hw_update_regulatory_maxpower(ah);
de40f316
FF		 1193
1194 if (test)
1195 return;
1196
7a37081e 1197 if (AR_SREV_9280_20_OR_LATER(ah)) {
e41f0bfc
SB		 1198 for (i = 0; i < Ar5416RateSize; i++) {
1199 int8_t pwr_table_offset;
1200
1201 pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1202 EEP_PWR_TABLE_OFFSET);
1203 ratesArray[i] -= pwr_table_offset * 2;
1204 }
b5aec950
S		 1205 }
1206
e7fc6338
RM		 1207 ENABLE_REGWRITE_BUFFER(ah);
1208
b5aec950
S		 1209 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1210 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1211 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1212 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1213 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1214 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1215 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1216 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1217 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1218 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1219
1220 if (IS_CHAN_2GHZ(chan)) {
1221 if (OLC_FOR_AR9280_20_LATER) {
1222 cck_ofdm_delta = 2;
1223 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1224 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1225 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1226 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1227 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1228 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1229 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1230 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1231 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1232 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1233 } else {
1234 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1235 ATH9K_POW_SM(ratesArray[rate2s], 24)
1236 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1237 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1238 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1239 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1240 ATH9K_POW_SM(ratesArray[rate11s], 24)
1241 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1242 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1243 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1244 }
1245 }
1246
1247 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1248 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1249 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1250 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1251 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1252 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1253 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1254 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1255 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1256 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1257
1258 if (IS_CHAN_HT40(chan)) {
1259 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1260 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1261 ht40PowerIncForPdadc, 24)
1262 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1263 ht40PowerIncForPdadc, 16)
1264 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1265 ht40PowerIncForPdadc, 8)
1266 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1267 ht40PowerIncForPdadc, 0));
1268 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1269 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1270 ht40PowerIncForPdadc, 24)
1271 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1272 ht40PowerIncForPdadc, 16)
1273 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1274 ht40PowerIncForPdadc, 8)
1275 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1276 ht40PowerIncForPdadc, 0));
1277 if (OLC_FOR_AR9280_20_LATER) {
1278 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1279 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1280 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1281 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1282 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1283 } else {
1284 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1285 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1286 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1287 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1288 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1289 }
1290 }
1291
1292 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1293 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1294 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
e7fc6338 1295
c08267dc
LB		 1296 /* TPC initializations */
1297 if (ah->tpc_enabled) {
1298 int ht40_delta;
1299
1300 ht40_delta = (IS_CHAN_HT40(chan)) ? ht40PowerIncForPdadc : 0;
1301 ar5008_hw_init_rate_txpower(ah, ratesArray, chan, ht40_delta);
1302 /* Enable TPC */
1303 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX,
1304 MAX_RATE_POWER | AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE);
1305 } else {
1306 /* Disable TPC */
1307 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER);
1308 }
1309
e7fc6338 1310 REGWRITE_BUFFER_FLUSH(ah);
b5aec950
S		 1311}
1312
b5aec950
S		 1313static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1314{
ae0c4031 1315 return ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan;
b5aec950
S		 1316}
1317
d8ec2e2a
MB		 1318static u8 ath9k_hw_def_get_eepmisc(struct ath_hw *ah)
1319{
1320 return ah->eeprom.def.baseEepHeader.eepMisc;
1321}
1322
b5aec950
S		 1323const struct eeprom_ops eep_def_ops = {
1324 .check_eeprom = ath9k_hw_def_check_eeprom,
1325 .get_eeprom = ath9k_hw_def_get_eeprom,
1326 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1b37d3e6 1327 .dump_eeprom = ath9k_hw_def_dump_eeprom,
b5aec950
S		 1328 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1329 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
b5aec950
S		 1330 .set_board_values = ath9k_hw_def_set_board_values,
1331 .set_addac = ath9k_hw_def_set_addac,
1332 .set_txpower = ath9k_hw_def_set_txpower,
d8ec2e2a
MB		 1333 .get_spur_channel = ath9k_hw_def_get_spur_channel,
1334 .get_eepmisc = ath9k_hw_def_get_eepmisc
b5aec950 1335};
Linux 6.x block layer and io_uring tree(s)