[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / btcoex.c

/*
 * Copyright (c) 2009-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include "hw.h"

enum ath_bt_mode {
	ATH_BT_COEX_MODE_LEGACY,        /* legacy rx_clear mode */
	ATH_BT_COEX_MODE_UNSLOTTED,     /* untimed/unslotted mode */
	ATH_BT_COEX_MODE_SLOTTED,       /* slotted mode */
	ATH_BT_COEX_MODE_DISALBED,      /* coexistence disabled */
};

struct ath_btcoex_config {
	u8 bt_time_extend;
	bool bt_txstate_extend;
	bool bt_txframe_extend;
	enum ath_bt_mode bt_mode; /* coexistence mode */
	bool bt_quiet_collision;
	bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
	u8 bt_priority_time;
	u8 bt_first_slot_time;
	bool bt_hold_rx_clear;
};

static const u32 ar9003_wlan_weights[ATH_BTCOEX_STOMP_MAX]
				    [AR9300_NUM_WLAN_WEIGHTS] = {
	{ 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0 }, /* STOMP_ALL */
	{ 0x88888880, 0x88888880, 0x88888880, 0x88888880 }, /* STOMP_LOW */
	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* STOMP_NONE */
};

void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
	const struct ath_btcoex_config ath_bt_config = {
		.bt_time_extend = 0,
		.bt_txstate_extend = true,
		.bt_txframe_extend = true,
		.bt_mode = ATH_BT_COEX_MODE_SLOTTED,
		.bt_quiet_collision = true,
		.bt_rxclear_polarity = true,
		.bt_priority_time = 2,
		.bt_first_slot_time = 5,
		.bt_hold_rx_clear = true,
	};
	u32 i, idx;
	bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;

	if (AR_SREV_9300_20_OR_LATER(ah))
		rxclear_polarity = !ath_bt_config.bt_rxclear_polarity;

	btcoex_hw->bt_coex_mode =
		(btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
		SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
		SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
		SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
		SM(ath_bt_config.bt_mode, AR_BT_MODE) |
		SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
		SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
		SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
		SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
		SM(qnum, AR_BT_QCU_THRESH);

	btcoex_hw->bt_coex_mode2 =
		SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
		SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
		AR_BT_DISABLE_BT_ANT;

	for (i = 0; i < 32; i++) {
		idx = (debruijn32 << i) >> 27;
		ah->hw_gen_timers.gen_timer_index[idx] = i;
	}
}
EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);

void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	/* connect bt_active to baseband */
	REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
		    (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
		     AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));

	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
		    AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);

	/* Set input mux for bt_active to gpio pin */
	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
		      AR_GPIO_INPUT_MUX1_BT_ACTIVE,
		      btcoex_hw->btactive_gpio);

	/* Configure the desired gpio port for input */
	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
}
EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);

void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	/* btcoex 3-wire */
	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
			(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
			 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));

	/* Set input mux for bt_prority_async and
	 *                  bt_active_async to GPIO pins */
	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
			AR_GPIO_INPUT_MUX1_BT_ACTIVE,
			btcoex_hw->btactive_gpio);

	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
			AR_GPIO_INPUT_MUX1_BT_PRIORITY,
			btcoex_hw->btpriority_gpio);

	/* Configure the desired GPIO ports for input */

	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
}
EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);

static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	/* Configure the desired GPIO port for TX_FRAME output */
	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
			    AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
}

void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
				u32 bt_weight,
				u32 wlan_weight)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
				     SM(wlan_weight, AR_BTCOEX_WL_WGHT);
}
EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);


static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
	u32  val;
	int i;

	/*
	 * Program coex mode and weight registers to
	 * enable coex 3-wire
	 */
	REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode);
	REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);


	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]);
		REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]);
		for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
			REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i),
				  btcoex->bt_weight[i]);
	} else
		REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights);


	if (AR_SREV_9271(ah)) {
		val = REG_READ(ah, 0x50040);
		val &= 0xFFFFFEFF;
		REG_WRITE(ah, 0x50040, val);
	}

	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
	REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);

	ath9k_hw_cfg_output(ah, btcoex->wlanactive_gpio,
			    AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
}

void ath9k_hw_btcoex_enable(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	switch (btcoex_hw->scheme) {
	case ATH_BTCOEX_CFG_NONE:
		break;
	case ATH_BTCOEX_CFG_2WIRE:
		ath9k_hw_btcoex_enable_2wire(ah);
		break;
	case ATH_BTCOEX_CFG_3WIRE:
		ath9k_hw_btcoex_enable_3wire(ah);
		break;
	}

	REG_RMW(ah, AR_GPIO_PDPU,
		(0x2 << (btcoex_hw->btactive_gpio * 2)),
		(0x3 << (btcoex_hw->btactive_gpio * 2)));

	ah->btcoex_hw.enabled = true;
}
EXPORT_SYMBOL(ath9k_hw_btcoex_enable);

void ath9k_hw_btcoex_disable(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
	int i;

	ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);

	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
			AR_GPIO_OUTPUT_MUX_AS_OUTPUT);

	if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
		REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
		REG_WRITE(ah, AR_BT_COEX_MODE2, 0);

		if (AR_SREV_9300_20_OR_LATER(ah)) {
			REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
			REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
			for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
				REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), 0);
		} else
			REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);

	}

	ah->btcoex_hw.enabled = false;
}
EXPORT_SYMBOL(ath9k_hw_btcoex_disable);

static void ar9003_btcoex_bt_stomp(struct ath_hw *ah,
			 enum ath_stomp_type stomp_type)
{
	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
	int i;

	for (i = 0; i < AR9300_NUM_WLAN_WEIGHTS; i++) {
		btcoex->bt_weight[i] = AR9300_BT_WGHT;
		btcoex->wlan_weight[i] = ar9003_wlan_weights[stomp_type][i];
	}
}

/*
 * Configures appropriate weight based on stomp type.
 */
void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
			      enum ath_stomp_type stomp_type)
{
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		ar9003_btcoex_bt_stomp(ah, stomp_type);
		return;
	}

	switch (stomp_type) {
	case ATH_BTCOEX_STOMP_ALL:
		ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
				AR_STOMP_ALL_WLAN_WGHT);
		break;
	case ATH_BTCOEX_STOMP_LOW:
		ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
				AR_STOMP_LOW_WLAN_WGHT);
		break;
	case ATH_BTCOEX_STOMP_NONE:
		ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
				AR_STOMP_NONE_WLAN_WGHT);
		break;
	default:
		ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
				"Invalid Stomptype\n");
		break;
	}
}
EXPORT_SYMBOL(ath9k_hw_btcoex_bt_stomp);
Commit	Line	Data
17d50d1d	1	/*
5b68138e	2	* Copyright (c) 2009-2011 Atheros Communications Inc.
17d50d1d VT	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
cfe8cba9	17	#include "hw.h"
17d50d1d	18
8b4fc5ba LR	19	enum ath_bt_mode {
	20	ATH_BT_COEX_MODE_LEGACY, /* legacy rx_clear mode */
	21	ATH_BT_COEX_MODE_UNSLOTTED, /* untimed/unslotted mode */
	22	ATH_BT_COEX_MODE_SLOTTED, /* slotted mode */
	23	ATH_BT_COEX_MODE_DISALBED, /* coexistence disabled */
	24	};
	25
	26	struct ath_btcoex_config {
	27	u8 bt_time_extend;
	28	bool bt_txstate_extend;
	29	bool bt_txframe_extend;
	30	enum ath_bt_mode bt_mode; /* coexistence mode */
	31	bool bt_quiet_collision;
	32	bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
	33	u8 bt_priority_time;
	34	u8 bt_first_slot_time;
	35	bool bt_hold_rx_clear;
	36	};
1773912b	37
54f10b05 RM	38	static const u32 ar9003_wlan_weights[ATH_BTCOEX_STOMP_MAX]
	39	[AR9300_NUM_WLAN_WEIGHTS] = {
	40	{ 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0 }, /* STOMP_ALL */
	41	{ 0x88888880, 0x88888880, 0x88888880, 0x88888880 }, /* STOMP_LOW */
	42	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* STOMP_NONE */
	43	};
1773912b	44
766ec4a9	45	void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
af03abec	46	{
766ec4a9	47	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
8b4fc5ba LR	48	const struct ath_btcoex_config ath_bt_config = {
	49	.bt_time_extend = 0,
	50	.bt_txstate_extend = true,
	51	.bt_txframe_extend = true,
	52	.bt_mode = ATH_BT_COEX_MODE_SLOTTED,
	53	.bt_quiet_collision = true,
	54	.bt_rxclear_polarity = true,
	55	.bt_priority_time = 2,
	56	.bt_first_slot_time = 5,
	57	.bt_hold_rx_clear = true,
	58	};
02c5172c	59	u32 i, idx;
a6ef530f VN	60	bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
	61
	62	if (AR_SREV_9300_20_OR_LATER(ah))
	63	rxclear_polarity = !ath_bt_config.bt_rxclear_polarity;
1773912b	64
766ec4a9 LR	65	btcoex_hw->bt_coex_mode =
766ec4a9 LR	66	(btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) \|
1773912b VT	67	SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) \|
	68	SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) \|
	69	SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) \|
	70	SM(ath_bt_config.bt_mode, AR_BT_MODE) \|
	71	SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) \|
a6ef530f	72	SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) \|
1773912b VT	73	SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) \|
	74	SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) \|
	75	SM(qnum, AR_BT_QCU_THRESH);
	76
766ec4a9	77	btcoex_hw->bt_coex_mode2 =
1773912b VT	78	SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) \|
	79	SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) \|
	80	AR_BT_DISABLE_BT_ANT;
	81
02c5172c RM	82	for (i = 0; i < 32; i++) {
	83	idx = (debruijn32 << i) >> 27;
	84	ah->hw_gen_timers.gen_timer_index[idx] = i;
	85	}
1773912b	86	}
7322fd19	87	EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
1773912b	88
75d7839f	89	void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
17d50d1d	90	{
766ec4a9	91	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1773912b	92
7a2f0f58 LR	93	/* connect bt_active to baseband */
	94	REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
	95	(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF \|
	96	AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
1773912b	97
7a2f0f58 LR	98	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
7a2f0f58 LR	99	AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
1773912b	100
7a2f0f58 LR	101	/* Set input mux for bt_active to gpio pin */
	102	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
	103	AR_GPIO_INPUT_MUX1_BT_ACTIVE,
766ec4a9	104	btcoex_hw->btactive_gpio);
f14462c6	105
7a2f0f58	106	/* Configure the desired gpio port for input */
766ec4a9	107	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
7a2f0f58	108	}
7322fd19	109	EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
7a2f0f58	110
75d7839f	111	void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
7a2f0f58	112	{
766ec4a9	113	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
17d50d1d	114
7a2f0f58 LR	115	/* btcoex 3-wire */
	116	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
	117	(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB \|
	118	AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
17d50d1d	119
7a2f0f58 LR	120	/* Set input mux for bt_prority_async and
	121	* bt_active_async to GPIO pins */
	122	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
	123	AR_GPIO_INPUT_MUX1_BT_ACTIVE,
766ec4a9	124	btcoex_hw->btactive_gpio);
17d50d1d	125
7a2f0f58 LR	126	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
7a2f0f58 LR	127	AR_GPIO_INPUT_MUX1_BT_PRIORITY,
766ec4a9	128	btcoex_hw->btpriority_gpio);
1773912b	129
7a2f0f58 LR	130	/* Configure the desired GPIO ports for input */
7a2f0f58 LR	131
766ec4a9 LR	132	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
766ec4a9 LR	133	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
7a2f0f58	134	}
7322fd19	135	EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
7a2f0f58	136
bc74bf8f LR	137	static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
bc74bf8f LR	138	{
766ec4a9	139	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
bc74bf8f LR	140
bc74bf8f LR	141	/* Configure the desired GPIO port for TX_FRAME output */
766ec4a9	142	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
bc74bf8f LR	143	AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
	144	}
	145
5e197292 LR	146	void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
	147	u32 bt_weight,
	148	u32 wlan_weight)
	149	{
	150	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
	151
	152	btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) \|
	153	SM(wlan_weight, AR_BTCOEX_WL_WGHT);
	154	}
7322fd19	155	EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
5e197292	156
a6ef530f	157
bc74bf8f LR	158	static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
bc74bf8f LR	159	{
54f10b05	160	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
21cb9879	161	u32 val;
54f10b05	162	int i;
bc74bf8f LR	163
	164	/*
	165	* Program coex mode and weight registers to
	166	* enable coex 3-wire
	167	*/
54f10b05 RM	168	REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode);
54f10b05 RM	169	REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
bc74bf8f	170
a6ef530f VN	171
a6ef530f VN	172	if (AR_SREV_9300_20_OR_LATER(ah)) {
54f10b05 RM	173	REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]);
	174	REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]);
	175	for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
	176	REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i),
	177	btcoex->bt_weight[i]);
a6ef530f	178	} else
54f10b05	179	REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights);
a6ef530f VN	180
	181
	182
21cb9879 VN	183	if (AR_SREV_9271(ah)) {
	184	val = REG_READ(ah, 0x50040);
	185	val &= 0xFFFFFEFF;
	186	REG_WRITE(ah, 0x50040, val);
	187	}
	188
bc74bf8f LR	189	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
	190	REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
	191
54f10b05	192	ath9k_hw_cfg_output(ah, btcoex->wlanactive_gpio,
bc74bf8f LR	193	AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
	194	}
	195
17d50d1d VT	196	void ath9k_hw_btcoex_enable(struct ath_hw *ah)
17d50d1d VT	197	{
766ec4a9	198	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
f14462c6	199
766ec4a9	200	switch (btcoex_hw->scheme) {
bc74bf8f LR	201	case ATH_BTCOEX_CFG_NONE:
	202	break;
	203	case ATH_BTCOEX_CFG_2WIRE:
	204	ath9k_hw_btcoex_enable_2wire(ah);
	205	break;
	206	case ATH_BTCOEX_CFG_3WIRE:
	207	ath9k_hw_btcoex_enable_3wire(ah);
	208	break;
1773912b VT	209	}
	210
	211	REG_RMW(ah, AR_GPIO_PDPU,
766ec4a9 LR	212	(0x2 << (btcoex_hw->btactive_gpio * 2)),
766ec4a9 LR	213	(0x3 << (btcoex_hw->btactive_gpio * 2)));
17d50d1d	214
766ec4a9	215	ah->btcoex_hw.enabled = true;
17d50d1d	216	}
7322fd19	217	EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
17d50d1d VT	218
	219	void ath9k_hw_btcoex_disable(struct ath_hw *ah)
	220	{
766ec4a9	221	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
54f10b05	222	int i;
f14462c6	223
766ec4a9	224	ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
17d50d1d	225
766ec4a9	226	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
17d50d1d VT	227	AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
17d50d1d VT	228
766ec4a9	229	if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
1773912b	230	REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET \| AR_BT_MODE);
1773912b	231	REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
a6ef530f VN	232
	233	if (AR_SREV_9300_20_OR_LATER(ah)) {
	234	REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
	235	REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
54f10b05 RM	236	for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
54f10b05 RM	237	REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), 0);
a6ef530f VN	238	} else
	239	REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
	240
1773912b VT	241	}
1773912b VT	242
766ec4a9	243	ah->btcoex_hw.enabled = false;
17d50d1d	244	}
7322fd19	245	EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
978f78bf VN	246
	247	static void ar9003_btcoex_bt_stomp(struct ath_hw *ah,
	248	enum ath_stomp_type stomp_type)
	249	{
54f10b05 RM	250	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
54f10b05 RM	251	int i;
978f78bf	252
54f10b05 RM	253	for (i = 0; i < AR9300_NUM_WLAN_WEIGHTS; i++) {
	254	btcoex->bt_weight[i] = AR9300_BT_WGHT;
	255	btcoex->wlan_weight[i] = ar9003_wlan_weights[stomp_type][i];
978f78bf	256	}
978f78bf VN	257	}
	258
	259	/*
	260	* Configures appropriate weight based on stomp type.
	261	*/
	262	void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
	263	enum ath_stomp_type stomp_type)
	264	{
	265	if (AR_SREV_9300_20_OR_LATER(ah)) {
	266	ar9003_btcoex_bt_stomp(ah, stomp_type);
	267	return;
	268	}
	269
	270	switch (stomp_type) {
	271	case ATH_BTCOEX_STOMP_ALL:
	272	ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
	273	AR_STOMP_ALL_WLAN_WGHT);
	274	break;
	275	case ATH_BTCOEX_STOMP_LOW:
	276	ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
	277	AR_STOMP_LOW_WLAN_WGHT);
	278	break;
	279	case ATH_BTCOEX_STOMP_NONE:
	280	ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
	281	AR_STOMP_NONE_WLAN_WGHT);
	282	break;
	283	default:
	284	ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
	285	"Invalid Stomptype\n");
	286	break;
	287	}
978f78bf VN	288	}
978f78bf VN	289	EXPORT_SYMBOL(ath9k_hw_btcoex_bt_stomp);