[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / btcoex.c

/*
 * Copyright (c) 2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include "hw.h"

enum ath_bt_mode {
	ATH_BT_COEX_MODE_LEGACY,        /* legacy rx_clear mode */
	ATH_BT_COEX_MODE_UNSLOTTED,     /* untimed/unslotted mode */
	ATH_BT_COEX_MODE_SLOTTED,       /* slotted mode */
	ATH_BT_COEX_MODE_DISALBED,      /* coexistence disabled */
};

struct ath_btcoex_config {
	u8 bt_time_extend;
	bool bt_txstate_extend;
	bool bt_txframe_extend;
	enum ath_bt_mode bt_mode; /* coexistence mode */
	bool bt_quiet_collision;
	bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
	u8 bt_priority_time;
	u8 bt_first_slot_time;
	bool bt_hold_rx_clear;
};

static const u16 ath_subsysid_tbl[] = {
	AR9280_COEX2WIRE_SUBSYSID,
	AT9285_COEX3WIRE_SA_SUBSYSID,
	AT9285_COEX3WIRE_DA_SUBSYSID
};

/*
 * Checks the subsystem id of the device to see if it
 * supports btcoex
 */
bool ath9k_hw_btcoex_supported(struct ath_hw *ah)
{
	int i;

	if (!ah->hw_version.subsysid)
		return false;

	for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++)
		if (ah->hw_version.subsysid == ath_subsysid_tbl[i])
			return true;

	return false;
}

void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
	const struct ath_btcoex_config ath_bt_config = {
		.bt_time_extend = 0,
		.bt_txstate_extend = true,
		.bt_txframe_extend = true,
		.bt_mode = ATH_BT_COEX_MODE_SLOTTED,
		.bt_quiet_collision = true,
		.bt_rxclear_polarity = true,
		.bt_priority_time = 2,
		.bt_first_slot_time = 5,
		.bt_hold_rx_clear = true,
	};
	u32 i;

	btcoex_hw->bt_coex_mode =
		(btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
		SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
		SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
		SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
		SM(ath_bt_config.bt_mode, AR_BT_MODE) |
		SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
		SM(ath_bt_config.bt_rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
		SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
		SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
		SM(qnum, AR_BT_QCU_THRESH);

	btcoex_hw->bt_coex_mode2 =
		SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
		SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
		AR_BT_DISABLE_BT_ANT;

	for (i = 0; i < 32; i++)
		ah->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i;
}
EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);

void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	/* connect bt_active to baseband */
	REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
		    (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
		     AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));

	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
		    AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);

	/* Set input mux for bt_active to gpio pin */
	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
		      AR_GPIO_INPUT_MUX1_BT_ACTIVE,
		      btcoex_hw->btactive_gpio);

	/* Configure the desired gpio port for input */
	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
}
EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);

void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	/* btcoex 3-wire */
	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
			(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
			 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));

	/* Set input mux for bt_prority_async and
	 *                  bt_active_async to GPIO pins */
	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
			AR_GPIO_INPUT_MUX1_BT_ACTIVE,
			btcoex_hw->btactive_gpio);

	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
			AR_GPIO_INPUT_MUX1_BT_PRIORITY,
			btcoex_hw->btpriority_gpio);

	/* Configure the desired GPIO ports for input */

	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
}
EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);

static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	/* Configure the desired GPIO port for TX_FRAME output */
	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
			    AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
}

void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
				u32 bt_weight,
				u32 wlan_weight)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
				     SM(wlan_weight, AR_BTCOEX_WL_WGHT);
}
EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);

static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	/*
	 * Program coex mode and weight registers to
	 * enable coex 3-wire
	 */
	REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);
	REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
	REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);

	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
	REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);

	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
			    AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
}

void ath9k_hw_btcoex_enable(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	switch (btcoex_hw->scheme) {
	case ATH_BTCOEX_CFG_NONE:
		break;
	case ATH_BTCOEX_CFG_2WIRE:
		ath9k_hw_btcoex_enable_2wire(ah);
		break;
	case ATH_BTCOEX_CFG_3WIRE:
		ath9k_hw_btcoex_enable_3wire(ah);
		break;
	}

	REG_RMW(ah, AR_GPIO_PDPU,
		(0x2 << (btcoex_hw->btactive_gpio * 2)),
		(0x3 << (btcoex_hw->btactive_gpio * 2)));

	ah->btcoex_hw.enabled = true;
}
EXPORT_SYMBOL(ath9k_hw_btcoex_enable);

void ath9k_hw_btcoex_disable(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);

	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
			AR_GPIO_OUTPUT_MUX_AS_OUTPUT);

	if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
		REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
		REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
		REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
	}

	ah->btcoex_hw.enabled = false;
}
EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
Commit	Line	Data
17d50d1d VT	1	/*
	2	* Copyright (c) 2009 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
cfe8cba9	17	#include "hw.h"
17d50d1d	18
8b4fc5ba LR	19	enum ath_bt_mode {
	20	ATH_BT_COEX_MODE_LEGACY, /* legacy rx_clear mode */
	21	ATH_BT_COEX_MODE_UNSLOTTED, /* untimed/unslotted mode */
	22	ATH_BT_COEX_MODE_SLOTTED, /* slotted mode */
	23	ATH_BT_COEX_MODE_DISALBED, /* coexistence disabled */
	24	};
	25
	26	struct ath_btcoex_config {
	27	u8 bt_time_extend;
	28	bool bt_txstate_extend;
	29	bool bt_txframe_extend;
	30	enum ath_bt_mode bt_mode; /* coexistence mode */
	31	bool bt_quiet_collision;
	32	bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
	33	u8 bt_priority_time;
	34	u8 bt_first_slot_time;
	35	bool bt_hold_rx_clear;
	36	};
1773912b	37
fe12946e VT	38	static const u16 ath_subsysid_tbl[] = {
	39	AR9280_COEX2WIRE_SUBSYSID,
	40	AT9285_COEX3WIRE_SA_SUBSYSID,
	41	AT9285_COEX3WIRE_DA_SUBSYSID
	42	};
	43
	44	/*
	45	* Checks the subsystem id of the device to see if it
	46	* supports btcoex
	47	*/
a36cfbca	48	bool ath9k_hw_btcoex_supported(struct ath_hw *ah)
fe12946e VT	49	{
	50	int i;
	51
a36cfbca	52	if (!ah->hw_version.subsysid)
fe12946e VT	53	return false;
	54
	55	for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++)
a36cfbca	56	if (ah->hw_version.subsysid == ath_subsysid_tbl[i])
fe12946e VT	57	return true;
	58
	59	return false;
	60	}
1773912b	61
766ec4a9	62	void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
af03abec	63	{
766ec4a9	64	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
8b4fc5ba LR	65	const struct ath_btcoex_config ath_bt_config = {
	66	.bt_time_extend = 0,
	67	.bt_txstate_extend = true,
	68	.bt_txframe_extend = true,
	69	.bt_mode = ATH_BT_COEX_MODE_SLOTTED,
	70	.bt_quiet_collision = true,
	71	.bt_rxclear_polarity = true,
	72	.bt_priority_time = 2,
	73	.bt_first_slot_time = 5,
	74	.bt_hold_rx_clear = true,
	75	};
1773912b	76	u32 i;
1773912b	77
766ec4a9 LR	78	btcoex_hw->bt_coex_mode =
766ec4a9 LR	79	(btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) \|
1773912b VT	80	SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) \|
	81	SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) \|
	82	SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) \|
	83	SM(ath_bt_config.bt_mode, AR_BT_MODE) \|
	84	SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) \|
	85	SM(ath_bt_config.bt_rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) \|
	86	SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) \|
	87	SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) \|
	88	SM(qnum, AR_BT_QCU_THRESH);
	89
766ec4a9	90	btcoex_hw->bt_coex_mode2 =
1773912b VT	91	SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) \|
	92	SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) \|
	93	AR_BT_DISABLE_BT_ANT;
	94
1773912b	95	for (i = 0; i < 32; i++)
af03abec	96	ah->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i;
1773912b	97	}
7322fd19	98	EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
1773912b	99
75d7839f	100	void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
17d50d1d	101	{
766ec4a9	102	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1773912b	103
7a2f0f58 LR	104	/* connect bt_active to baseband */
	105	REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
	106	(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF \|
	107	AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
1773912b	108
7a2f0f58 LR	109	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
7a2f0f58 LR	110	AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
1773912b	111
7a2f0f58 LR	112	/* Set input mux for bt_active to gpio pin */
	113	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
	114	AR_GPIO_INPUT_MUX1_BT_ACTIVE,
766ec4a9	115	btcoex_hw->btactive_gpio);
f14462c6	116
7a2f0f58	117	/* Configure the desired gpio port for input */
766ec4a9	118	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
7a2f0f58	119	}
7322fd19	120	EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
7a2f0f58	121
75d7839f	122	void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
7a2f0f58	123	{
766ec4a9	124	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
17d50d1d	125
7a2f0f58 LR	126	/* btcoex 3-wire */
	127	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
	128	(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB \|
	129	AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
17d50d1d	130
7a2f0f58 LR	131	/* Set input mux for bt_prority_async and
	132	* bt_active_async to GPIO pins */
	133	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
	134	AR_GPIO_INPUT_MUX1_BT_ACTIVE,
766ec4a9	135	btcoex_hw->btactive_gpio);
17d50d1d	136
7a2f0f58 LR	137	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
7a2f0f58 LR	138	AR_GPIO_INPUT_MUX1_BT_PRIORITY,
766ec4a9	139	btcoex_hw->btpriority_gpio);
1773912b	140
7a2f0f58 LR	141	/* Configure the desired GPIO ports for input */
7a2f0f58 LR	142
766ec4a9 LR	143	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
766ec4a9 LR	144	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
7a2f0f58	145	}
7322fd19	146	EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
7a2f0f58	147
bc74bf8f LR	148	static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
bc74bf8f LR	149	{
766ec4a9	150	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
bc74bf8f LR	151
bc74bf8f LR	152	/* Configure the desired GPIO port for TX_FRAME output */
766ec4a9	153	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
bc74bf8f LR	154	AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
	155	}
	156
5e197292 LR	157	void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
	158	u32 bt_weight,
	159	u32 wlan_weight)
	160	{
	161	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
	162
	163	btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) \|
	164	SM(wlan_weight, AR_BTCOEX_WL_WGHT);
	165	}
7322fd19	166	EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
5e197292	167
bc74bf8f LR	168	static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
bc74bf8f LR	169	{
766ec4a9	170	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
bc74bf8f LR	171
	172	/*
	173	* Program coex mode and weight registers to
	174	* enable coex 3-wire
	175	*/
766ec4a9 LR	176	REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);
	177	REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
	178	REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);
bc74bf8f LR	179
	180	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
	181	REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
	182
766ec4a9	183	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
bc74bf8f LR	184	AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
	185	}
	186
17d50d1d VT	187	void ath9k_hw_btcoex_enable(struct ath_hw *ah)
17d50d1d VT	188	{
766ec4a9	189	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
f14462c6	190
766ec4a9	191	switch (btcoex_hw->scheme) {
bc74bf8f LR	192	case ATH_BTCOEX_CFG_NONE:
	193	break;
	194	case ATH_BTCOEX_CFG_2WIRE:
	195	ath9k_hw_btcoex_enable_2wire(ah);
	196	break;
	197	case ATH_BTCOEX_CFG_3WIRE:
	198	ath9k_hw_btcoex_enable_3wire(ah);
	199	break;
1773912b VT	200	}
	201
	202	REG_RMW(ah, AR_GPIO_PDPU,
766ec4a9 LR	203	(0x2 << (btcoex_hw->btactive_gpio * 2)),
766ec4a9 LR	204	(0x3 << (btcoex_hw->btactive_gpio * 2)));
17d50d1d	205
766ec4a9	206	ah->btcoex_hw.enabled = true;
17d50d1d	207	}
7322fd19	208	EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
17d50d1d VT	209
	210	void ath9k_hw_btcoex_disable(struct ath_hw *ah)
	211	{
766ec4a9	212	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
f14462c6	213
766ec4a9	214	ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
17d50d1d	215
766ec4a9	216	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
17d50d1d VT	217	AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
17d50d1d VT	218
766ec4a9	219	if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
1773912b VT	220	REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET \| AR_BT_MODE);
	221	REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
	222	REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
	223	}
	224
766ec4a9	225	ah->btcoex_hw.enabled = false;
17d50d1d	226	}
7322fd19	227	EXPORT_SYMBOL(ath9k_hw_btcoex_disable);