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ath9k: move spectral_mode to ath_spec_scan_priv
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / ath9k.h
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH9K_H
18#define ATH9K_H
19
394cf0a1
S		 20#include <linux/etherdevice.h>
21#include <linux/device.h>
a6b7a407 22#include <linux/interrupt.h>
394cf0a1 23#include <linux/leds.h>
9f42c2b6 24#include <linux/completion.h>
8d7e09dd 25#include <linux/time.h>
394cf0a1 26
db86f07e 27#include "common.h"
9d83cd5c 28#include "debug.h"
7dc181c2 29#include "mci.h"
8e92d3f2 30#include "dfs.h"
f65c0825 31#include "spectral.h"
db86f07e 32
394cf0a1 33struct ath_node;
11e39a4e 34struct ath_vif;
394cf0a1 35
7b6ef998
SM		 36extern struct ieee80211_ops ath9k_ops;
37extern int ath9k_modparam_nohwcrypt;
38extern int led_blink;
39extern bool is_ath9k_unloaded;
78b21949 40extern int ath9k_use_chanctx;
394cf0a1 41
394cf0a1
S		 42/*************************/
43/* Descriptor Management */
44/*************************/
45
7b6ef998
SM		 46#define ATH_TXSTATUS_RING_SIZE 512
47
48/* Macro to expand scalars to 64-bit objects */
49#define ito64(x) (sizeof(x) == 1) ? \
50 (((unsigned long long int)(x)) & (0xff)) : \
51 (sizeof(x) == 2) ? \
52 (((unsigned long long int)(x)) & 0xffff) : \
53 ((sizeof(x) == 4) ? \
54 (((unsigned long long int)(x)) & 0xffffffff) : \
55 (unsigned long long int)(x))
56
394cf0a1 57#define ATH_TXBUF_RESET(_bf) do { \
394cf0a1
S		 58 (_bf)->bf_lastbf = NULL; \
59 (_bf)->bf_next = NULL; \
60 memset(&((_bf)->bf_state), 0, \
61 sizeof(struct ath_buf_state)); \
62 } while (0)
63
c3d77696
MSS		 64#define DS2PHYS(_dd, _ds) \
65 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
66#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
67#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
68
394cf0a1 69struct ath_descdma {
5088c2f1 70 void *dd_desc;
17d7904d
S		 71 dma_addr_t dd_desc_paddr;
72 u32 dd_desc_len;
394cf0a1
S		 73};
74
75int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
76 struct list_head *head, const char *name,
4adfcded 77 int nbuf, int ndesc, bool is_tx);
394cf0a1
S		 78
79/***********/
80/* RX / TX */
81/***********/
82
7b6ef998
SM		 83#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
84
85/* increment with wrap-around */
86#define INCR(_l, _sz) do { \
87 (_l)++; \
88 (_l) &= ((_sz) - 1); \
89 } while (0)
90
394cf0a1 91#define ATH_RXBUF 512
394cf0a1 92#define ATH_TXBUF 512
84642d6b
FF		 93#define ATH_TXBUF_RESERVE 5
94#define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
394cf0a1 95#define ATH_TXMAXTRY 13
7b6ef998 96#define ATH_MAX_SW_RETRIES 30
394cf0a1
S		 97
98#define TID_TO_WME_AC(_tid) \
bea843c7
SM		 99 ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \
100 (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \
101 (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \
102 IEEE80211_AC_VO)
394cf0a1 103
394cf0a1
S		 104#define ATH_AGGR_DELIM_SZ 4
105#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
106/* number of delimiters for encryption padding */
107#define ATH_AGGR_ENCRYPTDELIM 10
108/* minimum h/w qdepth to be sustained to maximize aggregation */
109#define ATH_AGGR_MIN_QDEPTH 2
2800e82b
FF		 110/* minimum h/w qdepth for non-aggregated traffic */
111#define ATH_NON_AGGR_MIN_QDEPTH 8
7b6ef998
SM		 112#define ATH_TX_COMPLETE_POLL_INT 1000
113#define ATH_TXFIFO_DEPTH 8
114#define ATH_TX_ERROR 0x01
394cf0a1 115
d463af4a
FF		 116/* Stop tx traffic 1ms before the GO goes away */
117#define ATH_P2P_PS_STOP_TIME 1000
118
394cf0a1
S		 119#define IEEE80211_SEQ_SEQ_SHIFT 4
120#define IEEE80211_SEQ_MAX 4096
394cf0a1
S		 121#define IEEE80211_WEP_IVLEN 3
122#define IEEE80211_WEP_KIDLEN 1
123#define IEEE80211_WEP_CRCLEN 4
124#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
125 (IEEE80211_WEP_IVLEN + \
126 IEEE80211_WEP_KIDLEN + \
127 IEEE80211_WEP_CRCLEN))
128
129/* return whether a bit at index _n in bitmap _bm is set
130 * _sz is the size of the bitmap */
131#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
132 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
133
134/* return block-ack bitmap index given sequence and starting sequence */
135#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
136
156369fa
FF		 137/* return the seqno for _start + _offset */
138#define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
139
394cf0a1
S		 140/* returns delimiter padding required given the packet length */
141#define ATH_AGGR_GET_NDELIM(_len) \
39ec2997
VT		 142 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
143 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
394cf0a1
S		 144
145#define BAW_WITHIN(_start, _bawsz, _seqno) \
146 ((((_seqno) - (_start)) & 4095) < (_bawsz))
147
394cf0a1
S		 148#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
149
350e2dcb
SM		 150#define IS_HT_RATE(rate) (rate & 0x80)
151#define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
152#define IS_OFDM_RATE(rate) ((rate >= 0x8) && (rate <= 0xf))
365d2ebc 153
9e495a26
SM		 154enum {
155 WLAN_RC_PHY_OFDM,
156 WLAN_RC_PHY_CCK,
157};
158
394cf0a1 159struct ath_txq {
60f2d1d5
BG		 160 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
161 u32 axq_qnum; /* ath9k hardware queue number */
fce041be 162 void *axq_link;
17d7904d 163 struct list_head axq_q;
394cf0a1 164 spinlock_t axq_lock;
17d7904d 165 u32 axq_depth;
4b3ba66a 166 u32 axq_ampdu_depth;
17d7904d 167 bool stopped;
164ace38 168 bool axq_tx_inprogress;
e5003249 169 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
e5003249
VT		 170 u8 txq_headidx;
171 u8 txq_tailidx;
066dae93 172 int pending_frames;
23de5dc9 173 struct sk_buff_head complete_q;
394cf0a1
S		 174};
175
93ef24b2 176struct ath_atx_ac {
066dae93 177 struct ath_txq *txq;
93ef24b2
S		 178 struct list_head list;
179 struct list_head tid_q;
5519541d 180 bool clear_ps_filter;
50676b81 181 bool sched;
93ef24b2
S		 182};
183
2d42efc4 184struct ath_frame_info {
56dc6336 185 struct ath_buf *bf;
d954cd77
FF		 186 u16 framelen;
187 s8 txq;
2d42efc4 188 enum ath9k_key_type keytype;
a75c0629 189 u8 keyix;
80b08a8d 190 u8 rtscts_rate;
8fed1408
FF		 191 u8 retries : 7;
192 u8 baw_tracked : 1;
2d42efc4
FF		 193};
194
1a04d59d
FF		 195struct ath_rxbuf {
196 struct list_head list;
197 struct sk_buff *bf_mpdu;
198 void *bf_desc;
199 dma_addr_t bf_daddr;
200 dma_addr_t bf_buf_addr;
201};
202
7b6ef998
SM		 203/**
204 * enum buffer_type - Buffer type flags
205 *
206 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
207 * @BUF_AGGR: Indicates whether the buffer can be aggregated
208 * (used in aggregation scheduling)
209 */
210enum buffer_type {
211 BUF_AMPDU = BIT(0),
212 BUF_AGGR = BIT(1),
213};
214
215#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
216#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
217
93ef24b2 218struct ath_buf_state {
93ef24b2 219 u8 bf_type;
9f42c2b6 220 u8 bfs_paprd;
399c6489 221 u8 ndelim;
50676b81 222 bool stale;
6a0ddaef 223 u16 seqno;
9cf04dcc 224 unsigned long bfs_paprd_timestamp;
93ef24b2
S		 225};
226
227struct ath_buf {
228 struct list_head list;
229 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
230 an aggregate) */
231 struct ath_buf *bf_next; /* next subframe in the aggregate */
232 struct sk_buff *bf_mpdu; /* enclosing frame structure */
233 void *bf_desc; /* virtual addr of desc */
234 dma_addr_t bf_daddr; /* physical addr of desc */
c1739eb3 235 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
79acac07 236 struct ieee80211_tx_rate rates[4];
93ef24b2 237 struct ath_buf_state bf_state;
93ef24b2
S		 238};
239
240struct ath_atx_tid {
241 struct list_head list;
56dc6336 242 struct sk_buff_head buf_q;
bb195ff6 243 struct sk_buff_head retry_q;
93ef24b2
S		 244 struct ath_node *an;
245 struct ath_atx_ac *ac;
81ee13ba 246 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
93ef24b2
S		 247 u16 seq_start;
248 u16 seq_next;
249 u16 baw_size;
50676b81 250 u8 tidno;
93ef24b2
S		 251 int baw_head; /* first un-acked tx buffer */
252 int baw_tail; /* next unused tx buffer slot */
50676b81
FF		 253
254 s8 bar_index;
08c96abd 255 bool sched;
08c96abd 256 bool active;
93ef24b2
S		 257};
258
259struct ath_node {
a145daf7 260 struct ath_softc *sc;
7f010c93 261 struct ieee80211_sta *sta; /* station struct we're part of */
7e1e3864 262 struct ieee80211_vif *vif; /* interface with which we're associated */
de7b7604 263 struct ath_atx_tid tid[IEEE80211_NUM_TIDS];
bea843c7 264 struct ath_atx_ac ac[IEEE80211_NUM_ACS];
93ae2dd2 265
93ef24b2
S		 266 u16 maxampdu;
267 u8 mpdudensity;
50676b81 268 s8 ps_key;
5519541d
FF		 269
270 bool sleeping;
f89d1bc4 271 bool no_ps_filter;
350e2dcb
SM		 272
273#ifdef CONFIG_ATH9K_STATION_STATISTICS
274 struct ath_rx_rate_stats rx_rate_stats;
275#endif
4bbf4414 276 u8 key_idx[4];
c774d57f
LB		 277
278 u32 ackto;
279 struct list_head list;
93ef24b2
S		 280};
281
394cf0a1
S		 282struct ath_tx_control {
283 struct ath_txq *txq;
2d42efc4 284 struct ath_node *an;
36323f81 285 struct ieee80211_sta *sta;
befcf7e7
FF		 286 u8 paprd;
287 bool force_channel;
394cf0a1
S		 288};
289
394cf0a1 290
60f2d1d5
BG		 291/**
292 * @txq_map: Index is mac80211 queue number. This is
293 * not necessarily the same as the hardware queue number
294 * (axq_qnum).
295 */
394cf0a1 296struct ath_tx {
394cf0a1 297 u32 txqsetup;
394cf0a1
S		 298 spinlock_t txbuflock;
299 struct list_head txbuf;
300 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
301 struct ath_descdma txdma;
bea843c7 302 struct ath_txq *txq_map[IEEE80211_NUM_ACS];
f2c7a793 303 struct ath_txq *uapsdq;
bea843c7
SM		 304 u32 txq_max_pending[IEEE80211_NUM_ACS];
305 u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32];
394cf0a1
S		 306};
307
b5c80475
FF		 308struct ath_rx_edma {
309 struct sk_buff_head rx_fifo;
b5c80475
FF		 310 u32 rx_fifo_hwsize;
311};
312
394cf0a1
S		 313struct ath_rx {
314 u8 defant;
315 u8 rxotherant;
723e7113 316 bool discard_next;
394cf0a1 317 u32 *rxlink;
6995fb80 318 u32 num_pkts;
394cf0a1
S		 319 struct list_head rxbuf;
320 struct ath_descdma rxdma;
b5c80475 321 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
0d95521e 322
1a04d59d 323 struct ath_rxbuf *buf_hold;
0d95521e 324 struct sk_buff *frag;
21fbbca3
CL		 325
326 u32 ampdu_ref;
394cf0a1
S		 327};
328
fb02e95c
SM		 329/*******************/
330/* Channel Context */
331/*******************/
332
fbbcd146
FF		 333struct ath_chanctx {
334 struct cfg80211_chan_def chandef;
335 struct list_head vifs;
0453531e 336 struct list_head acq[IEEE80211_NUM_ACS];
3ad9c386 337 int hw_queue_base;
0453531e 338
9a9c4fbc
RM		 339 /* do not dereference, use for comparison only */
340 struct ieee80211_vif *primary_sta;
341
ca900ac9 342 struct ath_beacon_config beacon;
b01459e8 343 struct ath9k_hw_cal_data caldata;
8d7e09dd
FF		 344 struct timespec tsf_ts;
345 u64 tsf_val;
58b57375 346 u32 last_beacon;
b01459e8 347
2fae0d9f 348 int flush_timeout;
bc7e1be7 349 u16 txpower;
d385c5c2 350 u16 cur_txpower;
fbbcd146 351 bool offchannel;
bff11766 352 bool stopped;
c083ce99 353 bool active;
39305635 354 bool assigned;
748299f2 355 bool switch_after_beacon;
fce34430 356
ca529c93 357 short nvifs;
2ce73c02 358 short nvifs_assigned;
fce34430 359 unsigned int rxfilter;
748299f2
FF		 360};
361
362enum ath_chanctx_event {
363 ATH_CHANCTX_EVENT_BEACON_PREPARE,
364 ATH_CHANCTX_EVENT_BEACON_SENT,
365 ATH_CHANCTX_EVENT_TSF_TIMER,
58b57375 366 ATH_CHANCTX_EVENT_BEACON_RECEIVED,
b8f9279b 367 ATH_CHANCTX_EVENT_AUTHORIZED,
73fa2f26 368 ATH_CHANCTX_EVENT_SWITCH,
02da18b7 369 ATH_CHANCTX_EVENT_ASSIGN,
73fa2f26 370 ATH_CHANCTX_EVENT_UNASSIGN,
02da18b7 371 ATH_CHANCTX_EVENT_CHANGE,
73fa2f26 372 ATH_CHANCTX_EVENT_ENABLE_MULTICHANNEL,
748299f2
FF		 373};
374
375enum ath_chanctx_state {
376 ATH_CHANCTX_STATE_IDLE,
377 ATH_CHANCTX_STATE_WAIT_FOR_BEACON,
378 ATH_CHANCTX_STATE_WAIT_FOR_TIMER,
379 ATH_CHANCTX_STATE_SWITCH,
6036c284 380 ATH_CHANCTX_STATE_FORCE_ACTIVE,
748299f2
FF		 381};
382
383struct ath_chanctx_sched {
384 bool beacon_pending;
73fa2f26 385 bool offchannel_pending;
367b341e 386 bool wait_switch;
d0975edd 387 bool force_noa_update;
167bf96d 388 bool extend_absence;
c6500ea2 389 bool mgd_prepare_tx;
748299f2 390 enum ath_chanctx_state state;
ec70abe1 391 u8 beacon_miss;
748299f2
FF		 392
393 u32 next_tbtt;
3ae07d39
FF		 394 u32 switch_start_time;
395 unsigned int offchannel_duration;
748299f2 396 unsigned int channel_switch_time;
42eda115
FF		 397
398 /* backup, in case the hardware timer fails */
399 struct timer_list timer;
fbbcd146
FF		 400};
401
78b21949
FF		 402enum ath_offchannel_state {
403 ATH_OFFCHANNEL_IDLE,
404 ATH_OFFCHANNEL_PROBE_SEND,
405 ATH_OFFCHANNEL_PROBE_WAIT,
406 ATH_OFFCHANNEL_SUSPEND,
405393cf
FF		 407 ATH_OFFCHANNEL_ROC_START,
408 ATH_OFFCHANNEL_ROC_WAIT,
409 ATH_OFFCHANNEL_ROC_DONE,
78b21949
FF		 410};
411
412struct ath_offchannel {
413 struct ath_chanctx chan;
414 struct timer_list timer;
415 struct cfg80211_scan_request *scan_req;
416 struct ieee80211_vif *scan_vif;
417 int scan_idx;
418 enum ath_offchannel_state state;
405393cf
FF		 419 struct ieee80211_channel *roc_chan;
420 struct ieee80211_vif *roc_vif;
421 int roc_duration;
ea6ff2de 422 int duration;
78b21949 423};
5a8cbec7
SM		 424
425#define case_rtn_string(val) case val: return #val
426
c4dc0d04
RM		 427#define ath_for_each_chanctx(_sc, _ctx) \
428 for (ctx = &sc->chanctx[0]; \
429 ctx <= &sc->chanctx[ARRAY_SIZE(sc->chanctx) - 1]; \
430 ctx++)
78b21949 431
6e47fafb
SM		 432void ath_chanctx_init(struct ath_softc *sc);
433void ath_chanctx_set_channel(struct ath_softc *sc, struct ath_chanctx *ctx,
434 struct cfg80211_chan_def *chandef);
435
436#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
437
39305635
FF		 438static inline struct ath_chanctx *
439ath_chanctx_get(struct ieee80211_chanctx_conf *ctx)
440{
441 struct ath_chanctx **ptr = (void *) ctx->drv_priv;
442 return *ptr;
443}
6e47fafb 444
499afacc
SM		 445bool ath9k_is_chanctx_enabled(void);
446void ath9k_fill_chanctx_ops(void);
705d0bf8 447void ath9k_init_channel_context(struct ath_softc *sc);
e90e302a 448void ath9k_offchannel_init(struct ath_softc *sc);
ea22df29 449void ath9k_deinit_channel_context(struct ath_softc *sc);
c7dd40c9
SM		 450int ath9k_init_p2p(struct ath_softc *sc);
451void ath9k_deinit_p2p(struct ath_softc *sc);
452void ath9k_p2p_remove_vif(struct ath_softc *sc,
453 struct ieee80211_vif *vif);
454void ath9k_p2p_beacon_sync(struct ath_softc *sc);
455void ath9k_p2p_bss_info_changed(struct ath_softc *sc,
456 struct ieee80211_vif *vif);
11e39a4e
SM		 457void ath9k_beacon_add_noa(struct ath_softc *sc, struct ath_vif *avp,
458 struct sk_buff *skb);
c7dd40c9 459void ath9k_p2p_ps_timer(void *priv);
b3903153 460void ath9k_chanctx_wake_queues(struct ath_softc *sc, struct ath_chanctx *ctx);
a064eaa1 461void ath9k_chanctx_stop_queues(struct ath_softc *sc, struct ath_chanctx *ctx);
a09798f4 462void ath_chanctx_check_active(struct ath_softc *sc, struct ath_chanctx *ctx);
e20a854e 463
a2b28601 464void ath_chanctx_beacon_recv_ev(struct ath_softc *sc,
70b06dac
SM		 465 enum ath_chanctx_event ev);
466void ath_chanctx_beacon_sent_ev(struct ath_softc *sc,
467 enum ath_chanctx_event ev);
27babf9f
SM		 468void ath_chanctx_event(struct ath_softc *sc, struct ieee80211_vif *vif,
469 enum ath_chanctx_event ev);
e20a854e 470void ath_chanctx_set_next(struct ath_softc *sc, bool force);
73b5ef0b
SM		 471void ath_offchannel_next(struct ath_softc *sc);
472void ath_scan_complete(struct ath_softc *sc, bool abort);
473void ath_roc_complete(struct ath_softc *sc, bool abort);
26103b8d 474struct ath_chanctx* ath_is_go_chanctx_present(struct ath_softc *sc);
6e47fafb 475
c7dd40c9 476#else
6e47fafb 477
499afacc
SM		 478static inline bool ath9k_is_chanctx_enabled(void)
479{
480 return false;
481}
482static inline void ath9k_fill_chanctx_ops(void)
483{
484}
705d0bf8
SM		 485static inline void ath9k_init_channel_context(struct ath_softc *sc)
486{
487}
e90e302a
SM		 488static inline void ath9k_offchannel_init(struct ath_softc *sc)
489{
490}
ea22df29
SM		 491static inline void ath9k_deinit_channel_context(struct ath_softc *sc)
492{
493}
a2b28601 494static inline void ath_chanctx_beacon_recv_ev(struct ath_softc *sc,
70b06dac
SM		 495 enum ath_chanctx_event ev)
496{
497}
498static inline void ath_chanctx_beacon_sent_ev(struct ath_softc *sc,
499 enum ath_chanctx_event ev)
500{
501}
27babf9f
SM		 502static inline void ath_chanctx_event(struct ath_softc *sc,
503 struct ieee80211_vif *vif,
504 enum ath_chanctx_event ev)
505{
506}
c7dd40c9
SM		 507static inline int ath9k_init_p2p(struct ath_softc *sc)
508{
509 return 0;
510}
511static inline void ath9k_deinit_p2p(struct ath_softc *sc)
512{
513}
514static inline void ath9k_p2p_remove_vif(struct ath_softc *sc,
515 struct ieee80211_vif *vif)
516{
517}
518static inline void ath9k_p2p_beacon_sync(struct ath_softc *sc)
519{
520}
521static inline void ath9k_p2p_bss_info_changed(struct ath_softc *sc,
522 struct ieee80211_vif *vif)
523{
524}
11e39a4e
SM		 525static inline void ath9k_beacon_add_noa(struct ath_softc *sc, struct ath_vif *avp,
526 struct sk_buff *skb)
527{
528}
c7dd40c9
SM		 529static inline void ath9k_p2p_ps_timer(struct ath_softc *sc)
530{
531}
b3903153
SM		 532static inline void ath9k_chanctx_wake_queues(struct ath_softc *sc,
533 struct ath_chanctx *ctx)
0e08b5fb
SM		 534{
535}
a064eaa1
SM		 536static inline void ath9k_chanctx_stop_queues(struct ath_softc *sc,
537 struct ath_chanctx *ctx)
538{
539}
a09798f4
SM		 540static inline void ath_chanctx_check_active(struct ath_softc *sc,
541 struct ath_chanctx *ctx)
542{
543}
6e47fafb 544
c7dd40c9
SM		 545#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
546
19ec477f 547void ath_startrecv(struct ath_softc *sc);
394cf0a1 548bool ath_stoprecv(struct ath_softc *sc);
394cf0a1
S		 549u32 ath_calcrxfilter(struct ath_softc *sc);
550int ath_rx_init(struct ath_softc *sc, int nbufs);
551void ath_rx_cleanup(struct ath_softc *sc);
b5c80475 552int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
394cf0a1 553struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
ef1b6cd9
SM		 554void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
555void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
556void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
394cf0a1 557void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
1381559b
FF		 558bool ath_drain_all_txq(struct ath_softc *sc);
559void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq);
394cf0a1
S		 560void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
561void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
562void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
0453531e 563void ath_txq_schedule_all(struct ath_softc *sc);
394cf0a1 564int ath_tx_init(struct ath_softc *sc, int nbufs);
394cf0a1
S		 565int ath_txq_update(struct ath_softc *sc, int qnum,
566 struct ath9k_tx_queue_info *q);
aa5955c3 567void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
ca14405e 568void ath_assign_seq(struct ath_common *common, struct sk_buff *skb);
c52f33d0 569int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
394cf0a1 570 struct ath_tx_control *txctl);
59505c02
FF		 571void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
572 struct sk_buff *skb);
394cf0a1 573void ath_tx_tasklet(struct ath_softc *sc);
e5003249 574void ath_tx_edma_tasklet(struct ath_softc *sc);
231c3a1f
FF		 575int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
576 u16 tid, u16 *ssn);
f83da965 577void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
394cf0a1
S		 578void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
579
5519541d 580void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
042ec453
JB		 581void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
582 struct ath_node *an);
86a22acf
FF		 583void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
584 struct ieee80211_sta *sta,
585 u16 tids, int nframes,
586 enum ieee80211_frame_release_type reason,
587 bool more_data);
5519541d 588
394cf0a1 589/********/
17d7904d 590/* VIFs */
394cf0a1 591/********/
f078f209 592
fdcf1bd4
SM		 593#define P2P_DEFAULT_CTWIN 10
594
17d7904d 595struct ath_vif {
fbbcd146
FF		 596 struct list_head list;
597
ca14405e
SM		 598 u16 seq_no;
599
cb35582a 600 /* BSS info */
62ae1aef 601 u8 bssid[ETH_ALEN] __aligned(2);
cb35582a
SM		 602 u16 aid;
603 bool assoc;
604
d463af4a 605 struct ieee80211_vif *vif;
f89d1bc4 606 struct ath_node mcast_node;
394cf0a1 607 int av_bslot;
4ed96f04 608 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
394cf0a1 609 struct ath_buf *av_bcbuf;
fbbcd146 610 struct ath_chanctx *chanctx;
d463af4a
FF		 611
612 /* P2P Client */
613 struct ieee80211_noa_data noa;
3ae07d39
FF		 614
615 /* P2P GO */
616 u8 noa_index;
617 u32 offchannel_start;
618 u32 offchannel_duration;
7414863e 619
d0975edd
SM		 620 /* These are used for both periodic and one-shot */
621 u32 noa_start;
622 u32 noa_duration;
623 bool periodic_noa;
0a019a58 624 bool oneshot_noa;
f078f209
LR		 625};
626
7b6ef998
SM		 627struct ath9k_vif_iter_data {
628 u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
629 u8 mask[ETH_ALEN]; /* bssid mask */
630 bool has_hw_macaddr;
9a9c4fbc
RM		 631 u8 slottime;
632 bool beacons;
7b6ef998
SM		 633
634 int naps; /* number of AP vifs */
635 int nmeshes; /* number of mesh vifs */
636 int nstations; /* number of station vifs */
637 int nwds; /* number of WDS vifs */
638 int nadhocs; /* number of adhoc vifs */
9a9c4fbc 639 struct ieee80211_vif *primary_sta;
7b6ef998
SM		 640};
641
9a9c4fbc
RM		 642void ath9k_calculate_iter_data(struct ath_softc *sc,
643 struct ath_chanctx *ctx,
7b6ef998 644 struct ath9k_vif_iter_data *iter_data);
9a9c4fbc
RM		 645void ath9k_calculate_summary_state(struct ath_softc *sc,
646 struct ath_chanctx *ctx);
7b6ef998 647
394cf0a1
S		 648/*******************/
649/* Beacon Handling */
650/*******************/
f078f209 651
394cf0a1
S		 652/*
653 * Regardless of the number of beacons we stagger, (i.e. regardless of the
654 * number of BSSIDs) if a given beacon does not go out even after waiting this
655 * number of beacon intervals, the game's up.
656 */
c944daf4 657#define BSTUCK_THRESH 9
689e756f 658#define ATH_BCBUF 8
394cf0a1
S		 659#define ATH_DEFAULT_BINTVAL 100 /* TU */
660#define ATH_DEFAULT_BMISS_LIMIT 10
394cf0a1 661
7b6ef998
SM		 662#define TSF_TO_TU(_h,_l) \
663 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
664
394cf0a1
S		 665struct ath_beacon {
666 enum {
667 OK, /* no change needed */
668 UPDATE, /* update pending */
669 COMMIT /* beacon sent, commit change */
670 } updateslot; /* slot time update fsm */
671
672 u32 beaconq;
673 u32 bmisscnt;
2c3db3d5 674 struct ieee80211_vif *bslot[ATH_BCBUF];
394cf0a1
S		 675 int slottime;
676 int slotupdate;
394cf0a1
S		 677 struct ath_descdma bdma;
678 struct ath_txq *cabq;
679 struct list_head bbuf;
ba4903f9
FF		 680
681 bool tx_processed;
682 bool tx_last;
394cf0a1
S		 683};
684
fb6e252f 685void ath9k_beacon_tasklet(unsigned long data);
ef4ad633
SM		 686void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
687 u32 changed);
130ef6e9
SM		 688void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
689void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
ef4ad633 690void ath9k_set_beacon(struct ath_softc *sc);
4effc6fd
MK		 691bool ath9k_csa_is_finished(struct ath_softc *sc, struct ieee80211_vif *vif);
692void ath9k_csa_update(struct ath_softc *sc);
394cf0a1 693
ef1b6cd9
SM		 694/*******************/
695/* Link Monitoring */
696/*******************/
f078f209 697
20977d3e
S		 698#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
699#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
e36b27af
LR		 700#define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
701#define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
6044474e 702#define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
20977d3e
S		 703#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
704#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
7b6ef998
SM		 705#define ATH_ANI_MAX_SKIP_COUNT 10
706#define ATH_PAPRD_TIMEOUT 100 /* msecs */
707#define ATH_PLL_WORK_INTERVAL 100
ca369eb4 708
ef1b6cd9 709void ath_tx_complete_poll_work(struct work_struct *work);
236de514 710void ath_reset_work(struct work_struct *work);
415ec61b 711bool ath_hw_check(struct ath_softc *sc);
9eab61c2 712void ath_hw_pll_work(struct work_struct *work);
9f42c2b6 713void ath_paprd_calibrate(struct work_struct *work);
55624204 714void ath_ani_calibrate(unsigned long data);
da0d45f7
SM		 715void ath_start_ani(struct ath_softc *sc);
716void ath_stop_ani(struct ath_softc *sc);
717void ath_check_ani(struct ath_softc *sc);
ef1b6cd9
SM		 718int ath_update_survey_stats(struct ath_softc *sc);
719void ath_update_survey_nf(struct ath_softc *sc, int channel);
124b979b 720void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
bf3dac5a 721void ath_ps_full_sleep(unsigned long data);
e2d389b5 722void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
25f3bc7d 723 bool sw_pending, bool timeout_override);
55624204 724
0fca65c1
S		 725/**********/
726/* BTCOEX */
727/**********/
728
ac46ba43
SM		 729#define ATH_DUMP_BTCOEX(_s, _val) \
730 do { \
5e88ba62
ZK		 731 len += scnprintf(buf + len, size - len, \
732 "%20s : %10d\n", _s, (_val)); \
ac46ba43
SM		 733 } while (0)
734
e6930c4b
SM		 735enum bt_op_flags {
736 BT_OP_PRIORITY_DETECTED,
737 BT_OP_SCAN,
738};
739
2e20250a 740struct ath_btcoex {
2e20250a
LR		 741 spinlock_t btcoex_lock;
742 struct timer_list period_timer; /* Timer for BT period */
168c6f89 743 struct timer_list no_stomp_timer;
2e20250a
LR		 744 u32 bt_priority_cnt;
745 unsigned long bt_priority_time;
e6930c4b 746 unsigned long op_flags;
e08a6ace 747 int bt_stomp_type; /* Types of BT stomping */
168c6f89 748 u32 btcoex_no_stomp; /* in msec */
94ae77ea 749 u32 btcoex_period; /* in msec */
168c6f89 750 u32 btscan_no_stomp; /* in msec */
7dc181c2 751 u32 duty_cycle;
6995fb80 752 u32 bt_wait_time;
e82cb03f 753 int rssi_count;
7dc181c2 754 struct ath_mci_profile mci;
2884561a 755 u8 stomp_audio;
2e20250a
LR		 756};
757
4daa7760 758#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
5908120f
SM		 759int ath9k_init_btcoex(struct ath_softc *sc);
760void ath9k_deinit_btcoex(struct ath_softc *sc);
df198b17
SM		 761void ath9k_start_btcoex(struct ath_softc *sc);
762void ath9k_stop_btcoex(struct ath_softc *sc);
0fca65c1
S		 763void ath9k_btcoex_timer_resume(struct ath_softc *sc);
764void ath9k_btcoex_timer_pause(struct ath_softc *sc);
56ca0dba 765void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
c0ac53fa 766u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
08d4df41 767void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
ac46ba43 768int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size);
4daa7760
SM		 769#else
770static inline int ath9k_init_btcoex(struct ath_softc *sc)
771{
772 return 0;
773}
774static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
775{
776}
777static inline void ath9k_start_btcoex(struct ath_softc *sc)
778{
779}
780static inline void ath9k_stop_btcoex(struct ath_softc *sc)
781{
782}
783static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
784 u32 status)
785{
786}
787static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
788 u32 max_4ms_framelen)
789{
790 return 0;
791}
08d4df41
RM		 792static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
793{
794}
ac46ba43 795static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size)
4df50ca8
RM		 796{
797 return 0;
798}
4daa7760 799#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
0fca65c1 800
394cf0a1
S		 801/********************/
802/* LED Control */
803/********************/
f078f209 804
08fc5c1b
VN		 805#define ATH_LED_PIN_DEF 1
806#define ATH_LED_PIN_9287 8
353e5019 807#define ATH_LED_PIN_9300 10
15178535 808#define ATH_LED_PIN_9485 6
1a68abb0 809#define ATH_LED_PIN_9462 4
f078f209 810
0cf55c21 811#ifdef CONFIG_MAC80211_LEDS
0fca65c1
S		 812void ath_init_leds(struct ath_softc *sc);
813void ath_deinit_leds(struct ath_softc *sc);
8f176a3a 814void ath_fill_led_pin(struct ath_softc *sc);
0cf55c21
FF		 815#else
816static inline void ath_init_leds(struct ath_softc *sc)
817{
818}
819
820static inline void ath_deinit_leds(struct ath_softc *sc)
8f176a3a
RM		 821{
822}
823static inline void ath_fill_led_pin(struct ath_softc *sc)
0cf55c21
FF		 824{
825}
826#endif
827
e60001e7
SM		 828/************************/
829/* Wake on Wireless LAN */
830/************************/
831
7b6ef998
SM		 832struct ath9k_wow_pattern {
833 u8 pattern_bytes[MAX_PATTERN_SIZE];
834 u8 mask_bytes[MAX_PATTERN_SIZE];
835 u32 pattern_len;
836};
837
e60001e7 838#ifdef CONFIG_ATH9K_WOW
babaa80a 839void ath9k_init_wow(struct ieee80211_hw *hw);
e60001e7
SM		 840int ath9k_suspend(struct ieee80211_hw *hw,
841 struct cfg80211_wowlan *wowlan);
842int ath9k_resume(struct ieee80211_hw *hw);
843void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
844#else
babaa80a
SM		 845static inline void ath9k_init_wow(struct ieee80211_hw *hw)
846{
847}
e60001e7
SM		 848static inline int ath9k_suspend(struct ieee80211_hw *hw,
849 struct cfg80211_wowlan *wowlan)
850{
851 return 0;
852}
853static inline int ath9k_resume(struct ieee80211_hw *hw)
854{
855 return 0;
856}
857static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
858{
859}
860#endif /* CONFIG_ATH9K_WOW */
861
8da07830 862/*******************************/
102885a5 863/* Antenna diversity/combining */
8da07830
SM		 864/*******************************/
865
102885a5
VT		 866#define ATH_ANT_RX_CURRENT_SHIFT 4
867#define ATH_ANT_RX_MAIN_SHIFT 2
868#define ATH_ANT_RX_MASK 0x3
869
870#define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
871#define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
872#define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
873#define ATH_ANT_DIV_COMB_INIT_COUNT 95
874#define ATH_ANT_DIV_COMB_MAX_COUNT 100
875#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
876#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
3afa6b4f
SM		 877#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50
878#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50
102885a5 879
102885a5
VT		 880#define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
881#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
882#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
883
102885a5
VT		 884struct ath_ant_comb {
885 u16 count;
886 u16 total_pkt_count;
887 bool scan;
888 bool scan_not_start;
889 int main_total_rssi;
890 int alt_total_rssi;
891 int alt_recv_cnt;
892 int main_recv_cnt;
893 int rssi_lna1;
894 int rssi_lna2;
895 int rssi_add;
896 int rssi_sub;
897 int rssi_first;
898 int rssi_second;
899 int rssi_third;
3afa6b4f
SM		 900 int ant_ratio;
901 int ant_ratio2;
102885a5
VT		 902 bool alt_good;
903 int quick_scan_cnt;
3fbaf4c5 904 enum ath9k_ant_div_comb_lna_conf main_conf;
102885a5
VT		 905 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
906 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
102885a5
VT		 907 bool first_ratio;
908 bool second_ratio;
909 unsigned long scan_start_time;
3afa6b4f
SM		 910
911 /*
912 * Card-specific config values.
913 */
914 int low_rssi_thresh;
915 int fast_div_bias;
102885a5
VT		 916};
917
8da07830 918void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
8da07830 919
394cf0a1
S		 920/********************/
921/* Main driver core */
922/********************/
f078f209 923
2d22c7dd
SM		 924#define ATH9K_PCI_CUS198 0x0001
925#define ATH9K_PCI_CUS230 0x0002
926#define ATH9K_PCI_CUS217 0x0004
927#define ATH9K_PCI_CUS252 0x0008
928#define ATH9K_PCI_WOW 0x0010
929#define ATH9K_PCI_BT_ANT_DIV 0x0020
930#define ATH9K_PCI_D3_L1_WAR 0x0040
931#define ATH9K_PCI_AR9565_1ANT 0x0080
932#define ATH9K_PCI_AR9565_2ANT 0x0100
933#define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200
4dd35640 934#define ATH9K_PCI_KILLER 0x0400
9b60b64b 935
394cf0a1
S		 936/*
937 * Default cache line size, in bytes.
938 * Used when PCI device not fully initialized by bootrom/BIOS
939*/
940#define DEFAULT_CACHELINE 32
394cf0a1 941#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
394cf0a1 942#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
071aa9a8 943#define MAX_GTT_CNT 5
394cf0a1 944
1b04b930
S		 945/* Powersave flags */
946#define PS_WAIT_FOR_BEACON BIT(0)
947#define PS_WAIT_FOR_CAB BIT(1)
948#define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
949#define PS_WAIT_FOR_TX_ACK BIT(3)
950#define PS_BEACON_SYNC BIT(4)
424749c7 951#define PS_WAIT_FOR_ANI BIT(5)
394cf0a1 952
fbbcd146
FF		 953#define ATH9K_NUM_CHANCTX 2 /* supports 2 operating channels */
954
394cf0a1
S		 955struct ath_softc {
956 struct ieee80211_hw *hw;
957 struct device *dev;
c52f33d0 958
3430098a
FF		 959 struct survey_info *cur_survey;
960 struct survey_info survey[ATH9K_NUM_CHANNELS];
0e2dedf9 961
394cf0a1
S		 962 struct tasklet_struct intr_tq;
963 struct tasklet_struct bcon_tasklet;
cbe61d8a 964 struct ath_hw *sc_ah;
394cf0a1
S		 965 void __iomem *mem;
966 int irq;
2d6a5e95 967 spinlock_t sc_serial_rw;
04717ccd 968 spinlock_t sc_pm_lock;
4bdd1e97 969 spinlock_t sc_pcu_lock;
394cf0a1 970 struct mutex mutex;
9f42c2b6 971 struct work_struct paprd_work;
236de514 972 struct work_struct hw_reset_work;
9f42c2b6 973 struct completion paprd_complete;
10e23181 974 wait_queue_head_t tx_wait;
394cf0a1 975
c7dd40c9 976#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
fb02e95c 977 struct work_struct chanctx_work;
d463af4a
FF		 978 struct ath_gen_timer *p2p_ps_timer;
979 struct ath_vif *p2p_ps_vif;
70b06dac 980 struct ath_chanctx_sched sched;
77843167 981 struct ath_offchannel offchannel;
fb02e95c 982 struct ath_chanctx *next_chan;
c6500ea2 983 struct completion go_beacon;
c7dd40c9 984#endif
d463af4a 985
9b60b64b 986 unsigned long driver_data;
cb8d61de 987
071aa9a8 988 u8 gtt_cnt;
17d7904d 989 u32 intrstatus;
1b04b930 990 u16 ps_flags; /* PS_* */
96148326 991 bool ps_enabled;
1dbfd9d4 992 bool ps_idle;
4801416c 993 short nbcnvifs;
709ade9e 994 unsigned long ps_usecount;
394cf0a1 995
394cf0a1
S		 996 struct ath_rx rx;
997 struct ath_tx tx;
998 struct ath_beacon beacon;
394cf0a1 999
bff11766 1000 struct cfg80211_chan_def cur_chandef;
fbbcd146
FF		 1001 struct ath_chanctx chanctx[ATH9K_NUM_CHANCTX];
1002 struct ath_chanctx *cur_chan;
bff11766 1003 spinlock_t chan_lock;
fbbcd146 1004
0cf55c21
FF		 1005#ifdef CONFIG_MAC80211_LEDS
1006 bool led_registered;
1007 char led_name[32];
1008 struct led_classdev led_cdev;
1009#endif
394cf0a1 1010
a830df07 1011#ifdef CONFIG_ATH9K_DEBUGFS
17d7904d 1012 struct ath9k_debug debug;
394cf0a1 1013#endif
164ace38 1014 struct delayed_work tx_complete_work;
181fb18d 1015 struct delayed_work hw_pll_work;
bf3dac5a 1016 struct timer_list sleep_timer;
4daa7760
SM		 1017
1018#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
2e20250a 1019 struct ath_btcoex btcoex;
9e25365f 1020 struct ath_mci_coex mci_coex;
3c7992e3 1021 struct work_struct mci_work;
4daa7760 1022#endif
5088c2f1
VT		 1023
1024 struct ath_descdma txsdma;
102885a5
VT		 1025
1026 struct ath_ant_comb ant_comb;
43c35284 1027 u8 ant_tx, ant_rx;
8e92d3f2 1028 struct dfs_pattern_detector *dfs_detector;
3f3c09f3 1029 u64 dfs_prev_pulse_ts;
b11e640a 1030 u32 wow_enabled;
e93d083f 1031 /* relay(fs) channel for spectral scan */
04ccd4a1 1032 struct ath_spec_scan spec_config;
911ea79f 1033 struct ath_spec_scan_priv spec_priv;
01c78533 1034
89f927af
LR		 1035 struct ieee80211_vif *tx99_vif;
1036 struct sk_buff *tx99_skb;
1037 bool tx99_state;
1038 s16 tx99_power;
1039
e60001e7 1040#ifdef CONFIG_ATH9K_WOW
01c78533
MSS		 1041 atomic_t wow_got_bmiss_intr;
1042 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
1043 u32 wow_intr_before_sleep;
1044#endif
394cf0a1
S		 1045};
1046
ef6b19e4
SM		 1047/********/
1048/* TX99 */
1049/********/
1050
1051#ifdef CONFIG_ATH9K_TX99
1052void ath9k_tx99_init_debug(struct ath_softc *sc);
89f927af
LR		 1053int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
1054 struct ath_tx_control *txctl);
ef6b19e4
SM		 1055#else
1056static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
1057{
1058}
1059static inline int ath9k_tx99_send(struct ath_softc *sc,
1060 struct sk_buff *skb,
1061 struct ath_tx_control *txctl)
1062{
1063 return 0;
1064}
1065#endif /* CONFIG_ATH9K_TX99 */
89f927af 1066
5bb12791 1067static inline void ath_read_cachesize(struct ath_common *common, int *csz)
394cf0a1 1068{
5bb12791 1069 common->bus_ops->read_cachesize(common, csz);
394cf0a1
S		 1070}
1071
7b6ef998
SM		 1072void ath9k_tasklet(unsigned long data);
1073int ath_cabq_update(struct ath_softc *);
313eb87f 1074u8 ath9k_parse_mpdudensity(u8 mpdudensity);
394cf0a1 1075irqreturn_t ath_isr(int irq, void *dev);
5555c955 1076int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan);
e60001e7
SM		 1077void ath_cancel_work(struct ath_softc *sc);
1078void ath_restart_work(struct ath_softc *sc);
eb93e891 1079int ath9k_init_device(u16 devid, struct ath_softc *sc,
5bb12791 1080 const struct ath_bus_ops *bus_ops);
285f2dda 1081void ath9k_deinit_device(struct ath_softc *sc);
43c35284 1082void ath9k_reload_chainmask_settings(struct ath_softc *sc);
7b6ef998
SM		 1083u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
1084void ath_start_rfkill_poll(struct ath_softc *sc);
1085void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
1086void ath9k_ps_wakeup(struct ath_softc *sc);
1087void ath9k_ps_restore(struct ath_softc *sc);
68a89116 1088
8e26a030 1089#ifdef CONFIG_ATH9K_PCI
394cf0a1
S		 1090int ath_pci_init(void);
1091void ath_pci_exit(void);
1092#else
1093static inline int ath_pci_init(void) { return 0; };
1094static inline void ath_pci_exit(void) {};
f1dc5600 1095#endif
f1dc5600 1096
8e26a030 1097#ifdef CONFIG_ATH9K_AHB
394cf0a1
S		 1098int ath_ahb_init(void);
1099void ath_ahb_exit(void);
1100#else
1101static inline int ath_ahb_init(void) { return 0; };
1102static inline void ath_ahb_exit(void) {};
f078f209 1103#endif
394cf0a1 1104
394cf0a1 1105#endif /* ATH9K_H */
Linux 6.x block layer and io_uring tree(s)