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Merge tag 'kvm-arm-for-4.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / ar9003_hw.c
CommitLineData
b3950e6a 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
b3950e6a
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
b622a720 18#include "ar9003_mac.h"
7284635d 19#include "ar9003_2p2_initvals.h"
0f978bfa 20#include "ar9003_buffalo_initvals.h"
c88457eb 21#include "ar9485_initvals.h"
d89baac8 22#include "ar9340_initvals.h"
172805ad
GJ		 23#include "ar9330_1p1_initvals.h"
24#include "ar9330_1p2_initvals.h"
a0fbb9bd 25#include "ar955x_1p0_initvals.h"
5a63ef0f 26#include "ar9580_1p0_initvals.h"
76db2f8c 27#include "ar9462_2p0_initvals.h"
d567e4eb 28#include "ar9462_2p1_initvals.h"
aaa53ee9 29#include "ar9565_1p0_initvals.h"
3777f7d1 30#include "ar9565_1p1_initvals.h"
b6b5730d 31#include "ar953x_initvals.h"
635d7c50 32#include "ar956x_initvals.h"
b3950e6a
LR		 33
34/* General hardware code for the AR9003 hadware family */
35
886b42bf
LR		 36/*
37 * The AR9003 family uses a new INI format (pre, core, post
38 * arrays per subsystem). This provides support for the
39 * AR9003 2.2 chipsets.
40 */
41static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
7284635d 42{
172805ad
GJ		 43 if (AR_SREV_9330_11(ah)) {
44 /* mac */
172805ad 45 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
a364517b 46 ar9331_1p1_mac_core);
172805ad 47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
a364517b 48 ar9331_1p1_mac_postamble);
172805ad
GJ		 49
50 /* bb */
172805ad 51 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
a364517b 52 ar9331_1p1_baseband_core);
172805ad 53 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
a364517b 54 ar9331_1p1_baseband_postamble);
172805ad
GJ		 55
56 /* radio */
172805ad 57 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
a364517b 58 ar9331_1p1_radio_core);
172805ad
GJ		 59
60 /* soc */
61 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
a364517b 62 ar9331_1p1_soc_preamble);
172805ad 63 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
a364517b 64 ar9331_1p1_soc_postamble);
172805ad
GJ		 65
66 /* rx/tx gain */
67 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 68 ar9331_common_rx_gain_1p1);
172805ad 69 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 70 ar9331_modes_lowest_ob_db_tx_gain_1p1);
172805ad 71
57527f8d
SM		 72 /* Japan 2484 Mhz CCK */
73 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
74 ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
75
172805ad
GJ		 76 /* additional clock settings */
77 if (ah->is_clk_25mhz)
c7d36f9f 78 INIT_INI_ARRAY(&ah->iniAdditional,
a364517b 79 ar9331_1p1_xtal_25M);
172805ad 80 else
c7d36f9f 81 INIT_INI_ARRAY(&ah->iniAdditional,
a364517b 82 ar9331_1p1_xtal_40M);
172805ad
GJ		 83 } else if (AR_SREV_9330_12(ah)) {
84 /* mac */
172805ad 85 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
a364517b 86 ar9331_1p2_mac_core);
172805ad 87 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
a364517b 88 ar9331_1p2_mac_postamble);
172805ad
GJ		 89
90 /* bb */
172805ad 91 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
a364517b 92 ar9331_1p2_baseband_core);
172805ad 93 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
a364517b 94 ar9331_1p2_baseband_postamble);
172805ad
GJ		 95
96 /* radio */
172805ad 97 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
a364517b 98 ar9331_1p2_radio_core);
172805ad
GJ		 99
100 /* soc */
101 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
a364517b 102 ar9331_1p2_soc_preamble);
172805ad 103 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
a364517b 104 ar9331_1p2_soc_postamble);
172805ad
GJ		 105
106 /* rx/tx gain */
107 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 108 ar9331_common_rx_gain_1p2);
172805ad 109 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 110 ar9331_modes_lowest_ob_db_tx_gain_1p2);
172805ad 111
57527f8d
SM		 112 /* Japan 2484 Mhz CCK */
113 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
114 ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
115
172805ad
GJ		 116 /* additional clock settings */
117 if (ah->is_clk_25mhz)
c7d36f9f 118 INIT_INI_ARRAY(&ah->iniAdditional,
a364517b 119 ar9331_1p2_xtal_25M);
172805ad 120 else
c7d36f9f 121 INIT_INI_ARRAY(&ah->iniAdditional,
a364517b 122 ar9331_1p2_xtal_40M);
172805ad 123 } else if (AR_SREV_9340(ah)) {
d89baac8 124 /* mac */
d89baac8 125 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
a364517b 126 ar9340_1p0_mac_core);
d89baac8 127 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
a364517b 128 ar9340_1p0_mac_postamble);
d89baac8
VT		 129
130 /* bb */
d89baac8 131 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
a364517b 132 ar9340_1p0_baseband_core);
d89baac8 133 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
a364517b 134 ar9340_1p0_baseband_postamble);
d89baac8
VT		 135
136 /* radio */
d89baac8 137 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
a364517b 138 ar9340_1p0_radio_core);
d89baac8 139 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
a364517b 140 ar9340_1p0_radio_postamble);
d89baac8
VT		 141
142 /* soc */
143 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
a364517b 144 ar9340_1p0_soc_preamble);
d89baac8 145 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
a364517b 146 ar9340_1p0_soc_postamble);
d89baac8
VT		 147
148 /* rx/tx gain */
149 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 150 ar9340Common_wo_xlna_rx_gain_table_1p0);
d89baac8 151 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 152 ar9340Modes_high_ob_db_tx_gain_table_1p0);
d89baac8 153
c7d36f9f 154 INIT_INI_ARRAY(&ah->iniModesFastClock,
2c8672c1
SM		 155 ar9340Modes_fast_clock_1p0);
156 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
157 ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
4a878b9f
SM		 158 INIT_INI_ARRAY(&ah->ini_dfs,
159 ar9340_1p0_baseband_postamble_dfs_channel);
d89baac8 160
c7d36f9f
FF		 161 if (!ah->is_clk_25mhz)
162 INIT_INI_ARRAY(&ah->iniAdditional,
a364517b 163 ar9340_1p0_radio_core_40M);
fb5a2dcb 164 } else if (AR_SREV_9485_11_OR_LATER(ah)) {
1a63e2ce 165 /* mac */
1a63e2ce 166 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
a364517b 167 ar9485_1_1_mac_core);
1a63e2ce 168 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
a364517b 169 ar9485_1_1_mac_postamble);
1a63e2ce
VN		 170
171 /* bb */
a364517b 172 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
1a63e2ce 173 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
a364517b 174 ar9485_1_1_baseband_core);
1a63e2ce 175 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
a364517b 176 ar9485_1_1_baseband_postamble);
1a63e2ce
VN		 177
178 /* radio */
1a63e2ce 179 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
a364517b 180 ar9485_1_1_radio_core);
1a63e2ce 181 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
a364517b 182 ar9485_1_1_radio_postamble);
1a63e2ce
VN		 183
184 /* soc */
185 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
a364517b 186 ar9485_1_1_soc_preamble);
1a63e2ce
VN		 187
188 /* rx/tx gain */
189 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 190 ar9485Common_wo_xlna_rx_gain_1_1);
1a63e2ce 191 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 192 ar9485_modes_lowest_ob_db_tx_gain_1_1);
1a63e2ce 193
57527f8d
SM		 194 /* Japan 2484 Mhz CCK */
195 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
196 ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
197
afa7e6db 198 if (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) {
2d22c7dd 199 INIT_INI_ARRAY(&ah->iniPcieSerdes,
afa7e6db 200 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
2d22c7dd 201 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
afa7e6db 202 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
2d22c7dd
SM		 203 } else {
204 INIT_INI_ARRAY(&ah->iniPcieSerdes,
afa7e6db 205 ar9485_1_1_pcie_phy_clkreq_disable_L1);
2d22c7dd 206 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
afa7e6db 207 ar9485_1_1_pcie_phy_clkreq_disable_L1);
2d22c7dd 208 }
d567e4eb
SM		 209 } else if (AR_SREV_9462_21(ah)) {
210 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
211 ar9462_2p1_mac_core);
212 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
213 ar9462_2p1_mac_postamble);
214 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
215 ar9462_2p1_baseband_core);
216 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
217 ar9462_2p1_baseband_postamble);
218 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
219 ar9462_2p1_radio_core);
220 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
221 ar9462_2p1_radio_postamble);
222 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
223 ar9462_2p1_radio_postamble_sys2ant);
224 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
225 ar9462_2p1_soc_preamble);
226 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
227 ar9462_2p1_soc_postamble);
228 INIT_INI_ARRAY(&ah->iniModesRxGain,
229 ar9462_2p1_common_rx_gain);
230 INIT_INI_ARRAY(&ah->iniModesFastClock,
231 ar9462_2p1_modes_fast_clock);
232 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
233 ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
93f7d6f3
SM		 234
235 /* Awake -> Sleep Setting */
236 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
237 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
238 INIT_INI_ARRAY(&ah->iniPcieSerdes,
239 ar9462_2p1_pciephy_clkreq_disable_L1);
240 }
241
242 /* Sleep -> Awake Setting */
243 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
244 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
245 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
246 ar9462_2p1_pciephy_clkreq_disable_L1);
247 }
423e38e8 248 } else if (AR_SREV_9462_20(ah)) {
2577c6e8 249
a364517b 250 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
2577c6e8 251 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
a364517b 252 ar9462_2p0_mac_postamble);
2577c6e8 253
2577c6e8 254 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
a364517b 255 ar9462_2p0_baseband_core);
2577c6e8 256 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
a364517b 257 ar9462_2p0_baseband_postamble);
2577c6e8 258
2577c6e8 259 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
a364517b 260 ar9462_2p0_radio_core);
2577c6e8 261 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
a364517b 262 ar9462_2p0_radio_postamble);
2577c6e8 263 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
a364517b 264 ar9462_2p0_radio_postamble_sys2ant);
2577c6e8
SB		 265
266 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
a364517b 267 ar9462_2p0_soc_preamble);
2577c6e8 268 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
a364517b 269 ar9462_2p0_soc_postamble);
2577c6e8
SB		 270
271 INIT_INI_ARRAY(&ah->iniModesRxGain,
dbb3e2fb 272 ar9462_2p0_common_rx_gain);
2577c6e8 273
2577c6e8 274 /* Awake -> Sleep Setting */
93f7d6f3
SM		 275 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
276 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
277 INIT_INI_ARRAY(&ah->iniPcieSerdes,
278 ar9462_2p0_pciephy_clkreq_disable_L1);
279 }
280
2577c6e8 281 /* Sleep -> Awake Setting */
93f7d6f3
SM		 282 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
283 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
284 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
285 ar9462_2p0_pciephy_clkreq_disable_L1);
286 }
2577c6e8
SB		 287
288 /* Fast clock modal settings */
c7d36f9f 289 INIT_INI_ARRAY(&ah->iniModesFastClock,
dbb3e2fb 290 ar9462_2p0_modes_fast_clock);
2577c6e8
SB		 291
292 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
57527f8d 293 ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
8bc45c6b
GJ		 294 } else if (AR_SREV_9550(ah)) {
295 /* mac */
8bc45c6b 296 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
a364517b 297 ar955x_1p0_mac_core);
8bc45c6b 298 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
a364517b 299 ar955x_1p0_mac_postamble);
8bc45c6b
GJ		 300
301 /* bb */
8bc45c6b 302 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
a364517b 303 ar955x_1p0_baseband_core);
8bc45c6b 304 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
a364517b 305 ar955x_1p0_baseband_postamble);
8bc45c6b
GJ		 306
307 /* radio */
8bc45c6b 308 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
a364517b 309 ar955x_1p0_radio_core);
8bc45c6b 310 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
a364517b 311 ar955x_1p0_radio_postamble);
8bc45c6b
GJ		 312
313 /* soc */
314 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
a364517b 315 ar955x_1p0_soc_preamble);
8bc45c6b 316 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
a364517b 317 ar955x_1p0_soc_postamble);
2577c6e8 318
8bc45c6b
GJ		 319 /* rx/tx gain */
320 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 321 ar955x_1p0_common_wo_xlna_rx_gain_table);
8bc45c6b 322 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
a364517b 323 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
8bc45c6b 324 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 325 ar955x_1p0_modes_xpa_tx_gain_table);
8bc45c6b
GJ		 326
327 /* Fast clock modal settings */
328 INIT_INI_ARRAY(&ah->iniModesFastClock,
a364517b 329 ar955x_1p0_modes_fast_clock);
b6b5730d
SM		 330 } else if (AR_SREV_9531(ah)) {
331 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
332 qca953x_1p0_mac_core);
333 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
334 qca953x_1p0_mac_postamble);
c01a7298
RM		 335 if (AR_SREV_9531_20(ah)) {
336 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
337 qca953x_2p0_baseband_core);
338 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
339 qca953x_2p0_baseband_postamble);
340 } else {
341 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
342 qca953x_1p0_baseband_core);
343 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
344 qca953x_1p0_baseband_postamble);
345 }
b6b5730d
SM		 346 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
347 qca953x_1p0_radio_core);
348 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
349 qca953x_1p0_radio_postamble);
350 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
351 qca953x_1p0_soc_preamble);
352 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
353 qca953x_1p0_soc_postamble);
46270d07
MP		 354
355 if (AR_SREV_9531_20(ah)) {
356 INIT_INI_ARRAY(&ah->iniModesRxGain,
357 qca953x_2p0_common_wo_xlna_rx_gain_table);
358 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
359 qca953x_2p0_common_wo_xlna_rx_gain_bounds);
360 } else {
361 INIT_INI_ARRAY(&ah->iniModesRxGain,
362 qca953x_1p0_common_wo_xlna_rx_gain_table);
363 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
364 qca953x_1p0_common_wo_xlna_rx_gain_bounds);
365 }
366
367 if (AR_SREV_9531_20(ah))
368 INIT_INI_ARRAY(&ah->iniModesTxGain,
369 qca953x_2p0_modes_no_xpa_tx_gain_table);
370 else if (AR_SREV_9531_11(ah))
371 INIT_INI_ARRAY(&ah->iniModesTxGain,
372 qca953x_1p1_modes_no_xpa_tx_gain_table);
373 else
374 INIT_INI_ARRAY(&ah->iniModesTxGain,
375 qca953x_1p0_modes_no_xpa_tx_gain_table);
376
b6b5730d
SM		 377 INIT_INI_ARRAY(&ah->iniModesFastClock,
378 qca953x_1p0_modes_fast_clock);
635d7c50
MP		 379 } else if (AR_SREV_9561(ah)) {
380 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
381 qca956x_1p0_mac_core);
382 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
383 qca956x_1p0_mac_postamble);
384
385 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
386 qca956x_1p0_baseband_core);
387 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
388 qca956x_1p0_baseband_postamble);
389
390 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
391 qca956x_1p0_radio_core);
392 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
393 qca956x_1p0_radio_postamble);
394
395 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
396 qca956x_1p0_soc_preamble);
397 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
398 qca956x_1p0_soc_postamble);
399
400 INIT_INI_ARRAY(&ah->iniModesRxGain,
401 qca956x_1p0_common_wo_xlna_rx_gain_table);
402 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
403 qca956x_1p0_common_wo_xlna_rx_gain_bounds);
404 INIT_INI_ARRAY(&ah->iniModesTxGain,
405 qca956x_1p0_modes_no_xpa_tx_gain_table);
406
407 INIT_INI_ARRAY(&ah->ini_dfs,
408 qca956x_1p0_baseband_postamble_dfs_channel);
409 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
410 qca956x_1p0_baseband_core_txfir_coeff_japan_2484);
411 INIT_INI_ARRAY(&ah->iniModesFastClock,
412 qca956x_1p0_modes_fast_clock);
5a63ef0f
LR		 413 } else if (AR_SREV_9580(ah)) {
414 /* mac */
5a63ef0f 415 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
a364517b 416 ar9580_1p0_mac_core);
5a63ef0f 417 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
a364517b 418 ar9580_1p0_mac_postamble);
5a63ef0f
LR		 419
420 /* bb */
5a63ef0f 421 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
a364517b 422 ar9580_1p0_baseband_core);
5a63ef0f 423 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
a364517b 424 ar9580_1p0_baseband_postamble);
5a63ef0f
LR		 425
426 /* radio */
5a63ef0f 427 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
a364517b 428 ar9580_1p0_radio_core);
5a63ef0f 429 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
a364517b 430 ar9580_1p0_radio_postamble);
5a63ef0f
LR		 431
432 /* soc */
433 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
a364517b 434 ar9580_1p0_soc_preamble);
5a63ef0f 435 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
a364517b 436 ar9580_1p0_soc_postamble);
5a63ef0f
LR		 437
438 /* rx/tx gain */
439 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 440 ar9580_1p0_rx_gain_table);
5a63ef0f 441 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 442 ar9580_1p0_low_ob_db_tx_gain_table);
5a63ef0f 443
c7d36f9f 444 INIT_INI_ARRAY(&ah->iniModesFastClock,
2c8672c1
SM		 445 ar9580_1p0_modes_fast_clock);
446 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
447 ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
4a878b9f
SM		 448 INIT_INI_ARRAY(&ah->ini_dfs,
449 ar9580_1p0_baseband_postamble_dfs_channel);
3777f7d1
SM		 450 } else if (AR_SREV_9565_11_OR_LATER(ah)) {
451 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
452 ar9565_1p1_mac_core);
453 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
454 ar9565_1p1_mac_postamble);
455
456 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
457 ar9565_1p1_baseband_core);
458 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
459 ar9565_1p1_baseband_postamble);
460
461 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
462 ar9565_1p1_radio_core);
463 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
464 ar9565_1p1_radio_postamble);
465
466 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
467 ar9565_1p1_soc_preamble);
468 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
469 ar9565_1p1_soc_postamble);
470
471 INIT_INI_ARRAY(&ah->iniModesRxGain,
472 ar9565_1p1_Common_rx_gain_table);
473 INIT_INI_ARRAY(&ah->iniModesTxGain,
474 ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
475
93f7d6f3
SM		 476 /* Awake -> Sleep Setting */
477 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
478 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
479 INIT_INI_ARRAY(&ah->iniPcieSerdes,
480 ar9565_1p1_pciephy_clkreq_disable_L1);
481 }
482
483 /* Sleep -> Awake Setting */
484 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
485 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
486 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
487 ar9565_1p1_pciephy_clkreq_disable_L1);
488 }
3777f7d1
SM		 489
490 INIT_INI_ARRAY(&ah->iniModesFastClock,
491 ar9565_1p1_modes_fast_clock);
492 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
493 ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
aaa53ee9
SM		 494 } else if (AR_SREV_9565(ah)) {
495 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
496 ar9565_1p0_mac_core);
497 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
498 ar9565_1p0_mac_postamble);
499
500 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
501 ar9565_1p0_baseband_core);
502 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
503 ar9565_1p0_baseband_postamble);
504
505 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
506 ar9565_1p0_radio_core);
507 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
508 ar9565_1p0_radio_postamble);
509
510 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
511 ar9565_1p0_soc_preamble);
512 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
513 ar9565_1p0_soc_postamble);
514
515 INIT_INI_ARRAY(&ah->iniModesRxGain,
516 ar9565_1p0_Common_rx_gain_table);
517 INIT_INI_ARRAY(&ah->iniModesTxGain,
518 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
519
93f7d6f3
SM		 520 /* Awake -> Sleep Setting */
521 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
522 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
523 INIT_INI_ARRAY(&ah->iniPcieSerdes,
524 ar9565_1p0_pciephy_clkreq_disable_L1);
525 }
526
527 /* Sleep -> Awake Setting */
528 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
529 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
530 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
531 ar9565_1p0_pciephy_clkreq_disable_L1);
532 }
aaa53ee9
SM		 533
534 INIT_INI_ARRAY(&ah->iniModesFastClock,
535 ar9565_1p0_modes_fast_clock);
6d5228fe
SM		 536 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
537 ar9565_1p0_baseband_core_txfir_coeff_japan_2484);
c88457eb
VT		 538 } else {
539 /* mac */
c88457eb 540 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
a364517b 541 ar9300_2p2_mac_core);
c88457eb 542 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
a364517b 543 ar9300_2p2_mac_postamble);
c88457eb
VT		 544
545 /* bb */
c88457eb 546 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
a364517b 547 ar9300_2p2_baseband_core);
c88457eb 548 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
a364517b 549 ar9300_2p2_baseband_postamble);
c88457eb
VT		 550
551 /* radio */
c88457eb 552 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
a364517b 553 ar9300_2p2_radio_core);
c88457eb 554 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
a364517b 555 ar9300_2p2_radio_postamble);
c88457eb
VT		 556
557 /* soc */
558 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
a364517b 559 ar9300_2p2_soc_preamble);
c88457eb 560 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
a364517b 561 ar9300_2p2_soc_postamble);
c88457eb
VT		 562
563 /* rx/tx gain */
564 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 565 ar9300Common_rx_gain_table_2p2);
c88457eb 566 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 567 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
c88457eb
VT		 568
569 /* Load PCIE SERDES settings from INI */
570
571 /* Awake Setting */
572
573 INIT_INI_ARRAY(&ah->iniPcieSerdes,
a364517b 574 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
c88457eb
VT		 575
576 /* Sleep Setting */
577
578 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
a364517b 579 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
c88457eb
VT		 580
581 /* Fast clock modal settings */
c7d36f9f 582 INIT_INI_ARRAY(&ah->iniModesFastClock,
2c8672c1
SM		 583 ar9300Modes_fast_clock_2p2);
584 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
585 ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
4a878b9f
SM		 586 INIT_INI_ARRAY(&ah->ini_dfs,
587 ar9300_2p2_baseband_postamble_dfs_channel);
c88457eb 588 }
7284635d
LR		 589}
590
4d0707e6
SB		 591static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
592{
593 if (AR_SREV_9330_12(ah))
594 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 595 ar9331_modes_lowest_ob_db_tx_gain_1p2);
4d0707e6
SB		 596 else if (AR_SREV_9330_11(ah))
597 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 598 ar9331_modes_lowest_ob_db_tx_gain_1p1);
4d0707e6
SB		 599 else if (AR_SREV_9340(ah))
600 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 601 ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
fb5a2dcb 602 else if (AR_SREV_9485_11_OR_LATER(ah))
4d0707e6 603 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 604 ar9485_modes_lowest_ob_db_tx_gain_1_1);
8bc45c6b
GJ		 605 else if (AR_SREV_9550(ah))
606 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 607 ar955x_1p0_modes_xpa_tx_gain_table);
46270d07
MP		 608 else if (AR_SREV_9531_10(ah))
609 INIT_INI_ARRAY(&ah->iniModesTxGain,
610 qca953x_1p0_modes_xpa_tx_gain_table);
611 else if (AR_SREV_9531_11(ah))
b6b5730d 612 INIT_INI_ARRAY(&ah->iniModesTxGain,
46270d07
MP		 613 qca953x_1p1_modes_xpa_tx_gain_table);
614 else if (AR_SREV_9531_20(ah))
615 INIT_INI_ARRAY(&ah->iniModesTxGain,
616 qca953x_2p0_modes_xpa_tx_gain_table);
635d7c50
MP		 617 else if (AR_SREV_9561(ah))
618 INIT_INI_ARRAY(&ah->iniModesTxGain,
619 qca956x_1p0_modes_xpa_tx_gain_table);
4d0707e6
SB		 620 else if (AR_SREV_9580(ah))
621 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 622 ar9580_1p0_lowest_ob_db_tx_gain_table);
d567e4eb
SM		 623 else if (AR_SREV_9462_21(ah))
624 INIT_INI_ARRAY(&ah->iniModesTxGain,
625 ar9462_2p1_modes_low_ob_db_tx_gain);
423e38e8 626 else if (AR_SREV_9462_20(ah))
2577c6e8 627 INIT_INI_ARRAY(&ah->iniModesTxGain,
dbb3e2fb 628 ar9462_2p0_modes_low_ob_db_tx_gain);
3777f7d1
SM		 629 else if (AR_SREV_9565_11(ah))
630 INIT_INI_ARRAY(&ah->iniModesTxGain,
631 ar9565_1p1_modes_low_ob_db_tx_gain_table);
aaa53ee9
SM		 632 else if (AR_SREV_9565(ah))
633 INIT_INI_ARRAY(&ah->iniModesTxGain,
634 ar9565_1p0_modes_low_ob_db_tx_gain_table);
4d0707e6
SB		 635 else
636 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 637 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
4d0707e6
SB		 638}
639
640static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
641{
642 if (AR_SREV_9330_12(ah))
643 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 644 ar9331_modes_high_ob_db_tx_gain_1p2);
4d0707e6
SB		 645 else if (AR_SREV_9330_11(ah))
646 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 647 ar9331_modes_high_ob_db_tx_gain_1p1);
4d0707e6
SB		 648 else if (AR_SREV_9340(ah))
649 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 650 ar9340Modes_high_ob_db_tx_gain_table_1p0);
fb5a2dcb 651 else if (AR_SREV_9485_11_OR_LATER(ah))
4d0707e6 652 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 653 ar9485Modes_high_ob_db_tx_gain_1_1);
4d0707e6
SB		 654 else if (AR_SREV_9580(ah))
655 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 656 ar9580_1p0_high_ob_db_tx_gain_table);
8bc45c6b
GJ		 657 else if (AR_SREV_9550(ah))
658 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 659 ar955x_1p0_modes_no_xpa_tx_gain_table);
b6b5730d 660 else if (AR_SREV_9531(ah)) {
46270d07
MP		 661 if (AR_SREV_9531_20(ah))
662 INIT_INI_ARRAY(&ah->iniModesTxGain,
663 qca953x_2p0_modes_no_xpa_tx_gain_table);
664 else if (AR_SREV_9531_11(ah))
b6b5730d
SM		 665 INIT_INI_ARRAY(&ah->iniModesTxGain,
666 qca953x_1p1_modes_no_xpa_tx_gain_table);
667 else
668 INIT_INI_ARRAY(&ah->iniModesTxGain,
669 qca953x_1p0_modes_no_xpa_tx_gain_table);
635d7c50
MP		 670 } else if (AR_SREV_9561(ah))
671 INIT_INI_ARRAY(&ah->iniModesTxGain,
672 qca956x_1p0_modes_no_xpa_tx_gain_table);
673 else if (AR_SREV_9462_21(ah))
d567e4eb
SM		 674 INIT_INI_ARRAY(&ah->iniModesTxGain,
675 ar9462_2p1_modes_high_ob_db_tx_gain);
423e38e8 676 else if (AR_SREV_9462_20(ah))
2577c6e8 677 INIT_INI_ARRAY(&ah->iniModesTxGain,
dbb3e2fb 678 ar9462_2p0_modes_high_ob_db_tx_gain);
3777f7d1
SM		 679 else if (AR_SREV_9565_11(ah))
680 INIT_INI_ARRAY(&ah->iniModesTxGain,
681 ar9565_1p1_modes_high_ob_db_tx_gain_table);
aaa53ee9
SM		 682 else if (AR_SREV_9565(ah))
683 INIT_INI_ARRAY(&ah->iniModesTxGain,
684 ar9565_1p0_modes_high_ob_db_tx_gain_table);
4d0707e6
SB		 685 else
686 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 687 ar9300Modes_high_ob_db_tx_gain_table_2p2);
4d0707e6
SB		 688}
689
690static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
691{
692 if (AR_SREV_9330_12(ah))
693 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 694 ar9331_modes_low_ob_db_tx_gain_1p2);
4d0707e6
SB		 695 else if (AR_SREV_9330_11(ah))
696 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 697 ar9331_modes_low_ob_db_tx_gain_1p1);
4d0707e6
SB		 698 else if (AR_SREV_9340(ah))
699 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 700 ar9340Modes_low_ob_db_tx_gain_table_1p0);
fb5a2dcb 701 else if (AR_SREV_9485_11_OR_LATER(ah))
4d0707e6 702 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 703 ar9485Modes_low_ob_db_tx_gain_1_1);
4d0707e6
SB		 704 else if (AR_SREV_9580(ah))
705 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 706 ar9580_1p0_low_ob_db_tx_gain_table);
635d7c50
MP		 707 else if (AR_SREV_9561(ah))
708 INIT_INI_ARRAY(&ah->iniModesTxGain,
709 qca956x_1p0_modes_no_xpa_low_ob_db_tx_gain_table);
3777f7d1
SM		 710 else if (AR_SREV_9565_11(ah))
711 INIT_INI_ARRAY(&ah->iniModesTxGain,
712 ar9565_1p1_modes_low_ob_db_tx_gain_table);
aaa53ee9
SM		 713 else if (AR_SREV_9565(ah))
714 INIT_INI_ARRAY(&ah->iniModesTxGain,
715 ar9565_1p0_modes_low_ob_db_tx_gain_table);
4d0707e6
SB		 716 else
717 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 718 ar9300Modes_low_ob_db_tx_gain_table_2p2);
4d0707e6
SB		 719}
720
721static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
722{
723 if (AR_SREV_9330_12(ah))
724 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 725 ar9331_modes_high_power_tx_gain_1p2);
4d0707e6
SB		 726 else if (AR_SREV_9330_11(ah))
727 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 728 ar9331_modes_high_power_tx_gain_1p1);
4d0707e6
SB		 729 else if (AR_SREV_9340(ah))
730 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 731 ar9340Modes_high_power_tx_gain_table_1p0);
fb5a2dcb 732 else if (AR_SREV_9485_11_OR_LATER(ah))
4d0707e6 733 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 734 ar9485Modes_high_power_tx_gain_1_1);
4d0707e6
SB		 735 else if (AR_SREV_9580(ah))
736 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 737 ar9580_1p0_high_power_tx_gain_table);
3777f7d1
SM		 738 else if (AR_SREV_9565_11(ah))
739 INIT_INI_ARRAY(&ah->iniModesTxGain,
740 ar9565_1p1_modes_high_power_tx_gain_table);
aaa53ee9
SM		 741 else if (AR_SREV_9565(ah))
742 INIT_INI_ARRAY(&ah->iniModesTxGain,
743 ar9565_1p0_modes_high_power_tx_gain_table);
0f978bfa
SM		 744 else {
745 if (ah->config.tx_gain_buffalo)
746 INIT_INI_ARRAY(&ah->iniModesTxGain,
747 ar9300Modes_high_power_tx_gain_table_buffalo);
748 else
749 INIT_INI_ARRAY(&ah->iniModesTxGain,
750 ar9300Modes_high_power_tx_gain_table_2p2);
751 }
4d0707e6
SB		 752}
753
b05a0111
FF		 754static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
755{
756 if (AR_SREV_9340(ah))
757 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 758 ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
b05a0111
FF		 759 else if (AR_SREV_9580(ah))
760 INIT_INI_ARRAY(&ah->iniModesTxGain,
a364517b 761 ar9580_1p0_mixed_ob_db_tx_gain_table);
d567e4eb
SM		 762 else if (AR_SREV_9462_21(ah))
763 INIT_INI_ARRAY(&ah->iniModesTxGain,
764 ar9462_2p1_modes_mix_ob_db_tx_gain);
9a54c176
SM		 765 else if (AR_SREV_9462_20(ah))
766 INIT_INI_ARRAY(&ah->iniModesTxGain,
dbb3e2fb 767 ar9462_2p0_modes_mix_ob_db_tx_gain);
eab6d792
FF		 768 else
769 INIT_INI_ARRAY(&ah->iniModesTxGain,
770 ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
771}
772
773static void ar9003_tx_gain_table_mode5(struct ath_hw *ah)
774{
fb5a2dcb 775 if (AR_SREV_9485_11_OR_LATER(ah))
eab6d792
FF		 776 INIT_INI_ARRAY(&ah->iniModesTxGain,
777 ar9485Modes_green_ob_db_tx_gain_1_1);
eab6d792
FF		 778 else if (AR_SREV_9580(ah))
779 INIT_INI_ARRAY(&ah->iniModesTxGain,
780 ar9580_1p0_type5_tx_gain_table);
635d7c50
MP		 781 else if (AR_SREV_9561(ah))
782 INIT_INI_ARRAY(&ah->iniModesTxGain,
783 qca956x_1p0_modes_no_xpa_green_tx_gain_table);
eab6d792
FF		 784 else if (AR_SREV_9300_22(ah))
785 INIT_INI_ARRAY(&ah->iniModesTxGain,
786 ar9300Modes_type5_tx_gain_table_2p2);
b05a0111
FF		 787}
788
eab6d792
FF		 789static void ar9003_tx_gain_table_mode6(struct ath_hw *ah)
790{
791 if (AR_SREV_9340(ah))
792 INIT_INI_ARRAY(&ah->iniModesTxGain,
793 ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0);
fb5a2dcb 794 else if (AR_SREV_9485_11_OR_LATER(ah))
eab6d792
FF		 795 INIT_INI_ARRAY(&ah->iniModesTxGain,
796 ar9485Modes_green_spur_ob_db_tx_gain_1_1);
797 else if (AR_SREV_9580(ah))
798 INIT_INI_ARRAY(&ah->iniModesTxGain,
799 ar9580_1p0_type6_tx_gain_table);
800}
801
8fd007ac
SM		 802static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
803{
804 if (AR_SREV_9340(ah))
805 INIT_INI_ARRAY(&ah->iniModesTxGain,
806 ar9340_cus227_tx_gain_table_1p0);
807}
808
eab6d792
FF		 809typedef void (*ath_txgain_tab)(struct ath_hw *ah);
810
c14a85da
LR		 811static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
812{
eab6d792
FF		 813 static const ath_txgain_tab modes[] = {
814 ar9003_tx_gain_table_mode0,
815 ar9003_tx_gain_table_mode1,
816 ar9003_tx_gain_table_mode2,
817 ar9003_tx_gain_table_mode3,
818 ar9003_tx_gain_table_mode4,
819 ar9003_tx_gain_table_mode5,
820 ar9003_tx_gain_table_mode6,
8fd007ac 821 ar9003_tx_gain_table_mode7,
eab6d792
FF		 822 };
823 int idx = ar9003_hw_get_tx_gain_idx(ah);
824
825 if (idx >= ARRAY_SIZE(modes))
826 idx = 0;
827
828 modes[idx](ah);
c14a85da
LR		 829}
830
4d0707e6
SB		 831static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
832{
833 if (AR_SREV_9330_12(ah))
834 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 835 ar9331_common_rx_gain_1p2);
4d0707e6
SB		 836 else if (AR_SREV_9330_11(ah))
837 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 838 ar9331_common_rx_gain_1p1);
4d0707e6
SB		 839 else if (AR_SREV_9340(ah))
840 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 841 ar9340Common_rx_gain_table_1p0);
fb5a2dcb 842 else if (AR_SREV_9485_11_OR_LATER(ah))
4d0707e6 843 INIT_INI_ARRAY(&ah->iniModesRxGain,
a796a1dd 844 ar9485_common_rx_gain_1_1);
8bc45c6b
GJ		 845 else if (AR_SREV_9550(ah)) {
846 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 847 ar955x_1p0_common_rx_gain_table);
8bc45c6b 848 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
a364517b 849 ar955x_1p0_common_rx_gain_bounds);
b6b5730d
SM		 850 } else if (AR_SREV_9531(ah)) {
851 INIT_INI_ARRAY(&ah->iniModesRxGain,
852 qca953x_1p0_common_rx_gain_table);
853 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
854 qca953x_1p0_common_rx_gain_bounds);
635d7c50
MP		 855 } else if (AR_SREV_9561(ah)) {
856 INIT_INI_ARRAY(&ah->iniModesRxGain,
857 qca956x_1p0_common_rx_gain_table);
858 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
859 qca956x_1p0_common_rx_gain_bounds);
871d0051 860 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
635d7c50 861 qca956x_1p0_xlna_only);
8bc45c6b 862 } else if (AR_SREV_9580(ah))
4d0707e6 863 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 864 ar9580_1p0_rx_gain_table);
d567e4eb
SM		 865 else if (AR_SREV_9462_21(ah))
866 INIT_INI_ARRAY(&ah->iniModesRxGain,
867 ar9462_2p1_common_rx_gain);
423e38e8 868 else if (AR_SREV_9462_20(ah))
2577c6e8 869 INIT_INI_ARRAY(&ah->iniModesRxGain,
dbb3e2fb 870 ar9462_2p0_common_rx_gain);
3777f7d1
SM		 871 else if (AR_SREV_9565_11(ah))
872 INIT_INI_ARRAY(&ah->iniModesRxGain,
873 ar9565_1p1_Common_rx_gain_table);
6ac21509
SM		 874 else if (AR_SREV_9565(ah))
875 INIT_INI_ARRAY(&ah->iniModesRxGain,
876 ar9565_1p0_Common_rx_gain_table);
4d0707e6
SB		 877 else
878 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 879 ar9300Common_rx_gain_table_2p2);
4d0707e6
SB		 880}
881
882static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
883{
884 if (AR_SREV_9330_12(ah))
885 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 886 ar9331_common_wo_xlna_rx_gain_1p2);
4d0707e6
SB		 887 else if (AR_SREV_9330_11(ah))
888 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 889 ar9331_common_wo_xlna_rx_gain_1p1);
4d0707e6
SB		 890 else if (AR_SREV_9340(ah))
891 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 892 ar9340Common_wo_xlna_rx_gain_table_1p0);
fb5a2dcb 893 else if (AR_SREV_9485_11_OR_LATER(ah))
4d0707e6 894 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 895 ar9485Common_wo_xlna_rx_gain_1_1);
d567e4eb
SM		 896 else if (AR_SREV_9462_21(ah))
897 INIT_INI_ARRAY(&ah->iniModesRxGain,
898 ar9462_2p1_common_wo_xlna_rx_gain);
423e38e8 899 else if (AR_SREV_9462_20(ah))
2577c6e8 900 INIT_INI_ARRAY(&ah->iniModesRxGain,
dbb3e2fb 901 ar9462_2p0_common_wo_xlna_rx_gain);
8bc45c6b
GJ		 902 else if (AR_SREV_9550(ah)) {
903 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 904 ar955x_1p0_common_wo_xlna_rx_gain_table);
8bc45c6b 905 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
a364517b 906 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
46270d07 907 } else if (AR_SREV_9531_10(ah) || AR_SREV_9531_11(ah)) {
b6b5730d
SM		 908 INIT_INI_ARRAY(&ah->iniModesRxGain,
909 qca953x_1p0_common_wo_xlna_rx_gain_table);
910 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
911 qca953x_1p0_common_wo_xlna_rx_gain_bounds);
46270d07
MP		 912 } else if (AR_SREV_9531_20(ah)) {
913 INIT_INI_ARRAY(&ah->iniModesRxGain,
914 qca953x_2p0_common_wo_xlna_rx_gain_table);
915 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
916 qca953x_2p0_common_wo_xlna_rx_gain_bounds);
635d7c50
MP		 917 } else if (AR_SREV_9561(ah)) {
918 INIT_INI_ARRAY(&ah->iniModesRxGain,
919 qca956x_1p0_common_wo_xlna_rx_gain_table);
920 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
921 qca956x_1p0_common_wo_xlna_rx_gain_bounds);
8bc45c6b 922 } else if (AR_SREV_9580(ah))
4d0707e6 923 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 924 ar9580_1p0_wo_xlna_rx_gain_table);
3777f7d1
SM		 925 else if (AR_SREV_9565_11(ah))
926 INIT_INI_ARRAY(&ah->iniModesRxGain,
927 ar9565_1p1_common_wo_xlna_rx_gain_table);
aaa53ee9
SM		 928 else if (AR_SREV_9565(ah))
929 INIT_INI_ARRAY(&ah->iniModesRxGain,
930 ar9565_1p0_common_wo_xlna_rx_gain_table);
4d0707e6
SB		 931 else
932 INIT_INI_ARRAY(&ah->iniModesRxGain,
a364517b 933 ar9300Common_wo_xlna_rx_gain_table_2p2);
4d0707e6
SB		 934}
935
2577c6e8
SB		 936static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
937{
d567e4eb
SM		 938 if (AR_SREV_9462_21(ah)) {
939 INIT_INI_ARRAY(&ah->iniModesRxGain,
940 ar9462_2p1_common_mixed_rx_gain);
941 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
942 ar9462_2p1_baseband_core_mix_rxgain);
943 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
944 ar9462_2p1_baseband_postamble_mix_rxgain);
871d0051 945 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
d567e4eb
SM		 946 ar9462_2p1_baseband_postamble_5g_xlna);
947 } else if (AR_SREV_9462_20(ah)) {
2577c6e8 948 INIT_INI_ARRAY(&ah->iniModesRxGain,
dbb3e2fb 949 ar9462_2p0_common_mixed_rx_gain);
c177fabe
SM		 950 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
951 ar9462_2p0_baseband_core_mix_rxgain);
952 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
953 ar9462_2p0_baseband_postamble_mix_rxgain);
871d0051 954 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
51dbd0a8
SM		 955 ar9462_2p0_baseband_postamble_5g_xlna);
956 }
957}
958
959static void ar9003_rx_gain_table_mode3(struct ath_hw *ah)
960{
d567e4eb
SM		 961 if (AR_SREV_9462_21(ah)) {
962 INIT_INI_ARRAY(&ah->iniModesRxGain,
dbb3e2fb 963 ar9462_2p1_common_5g_xlna_only_rxgain);
871d0051 964 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
d567e4eb
SM		 965 ar9462_2p1_baseband_postamble_5g_xlna);
966 } else if (AR_SREV_9462_20(ah)) {
51dbd0a8 967 INIT_INI_ARRAY(&ah->iniModesRxGain,
dbb3e2fb 968 ar9462_2p0_common_5g_xlna_only_rxgain);
871d0051 969 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
51dbd0a8
SM		 970 ar9462_2p0_baseband_postamble_5g_xlna);
971 }
2577c6e8
SB		 972}
973
c14a85da
LR		 974static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
975{
976 switch (ar9003_hw_get_rx_gain_idx(ah)) {
977 case 0:
978 default:
4d0707e6 979 ar9003_rx_gain_table_mode0(ah);
c14a85da
LR		 980 break;
981 case 1:
4d0707e6 982 ar9003_rx_gain_table_mode1(ah);
c14a85da 983 break;
2577c6e8
SB		 984 case 2:
985 ar9003_rx_gain_table_mode2(ah);
986 break;
51dbd0a8
SM		 987 case 3:
988 ar9003_rx_gain_table_mode3(ah);
989 break;
c14a85da
LR		 990 }
991}
992
993/* set gain table pointers according to values read from the eeprom */
994static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
995{
996 ar9003_tx_gain_table_apply(ah);
997 ar9003_rx_gain_table_apply(ah);
998}
999
b3950e6a
LR		 1000/*
1001 * Helper for ASPM support.
1002 *
1003 * Disable PLL when in L0s as well as receiver clock when in L1.
1004 * This power saving option must be enabled through the SerDes.
1005 *
1006 * Programming the SerDes must go through the same 288 bit serial shift
1007 * register as the other analog registers. Hence the 9 writes.
1008 */
1009static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
84c87dc8 1010 bool power_off)
b3950e6a 1011{
c6fc7e64
SM		 1012 unsigned int i;
1013 struct ar5416IniArray *array;
1014
b380a43b
SM		 1015 /*
1016 * Increase L1 Entry Latency. Some WB222 boards don't have
1017 * this change in eeprom/OTP.
1018 *
1019 */
1020 if (AR_SREV_9462(ah)) {
1021 u32 val = ah->config.aspm_l1_fix;
1022 if ((val & 0xff000000) == 0x17000000) {
1023 val &= 0x00ffffff;
1024 val |= 0x27000000;
1025 REG_WRITE(ah, 0x570c, val);
1026 }
1027 }
1028
b3950e6a 1029 /* Nothing to do on restore for 11N */
84c87dc8 1030 if (!power_off /* !restore */) {
b3950e6a
LR		 1031 /* set bit 19 to allow forcing of pcie core into L1 state */
1032 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
d1ae25a0 1033 REG_WRITE(ah, AR_WA, ah->WARegVal);
b3950e6a 1034 }
653fe371
LR		 1035
1036 /*
1037 * Configire PCIE after Ini init. SERDES values now come from ini file
1038 * This enables PCIe low power mode.
1039 */
c6fc7e64
SM		 1040 array = power_off ? &ah->iniPcieSerdes :
1041 &ah->iniPcieSerdesLowPower;
d5c4d193 1042
c6fc7e64
SM		 1043 for (i = 0; i < array->ia_rows; i++) {
1044 REG_WRITE(ah,
1045 INI_RA(array, i, 0),
1046 INI_RA(array, i, 1));
653fe371 1047 }
b3950e6a
LR		 1048}
1049
4598702d
SM		 1050static void ar9003_hw_init_hang_checks(struct ath_hw *ah)
1051{
1052 /*
1053 * All chips support detection of BB/MAC hangs.
1054 */
1055 ah->config.hw_hang_checks |= HW_BB_WATCHDOG;
1056 ah->config.hw_hang_checks |= HW_MAC_HANG;
1057
1058 /*
1059 * This is not required for AR9580 1.0
1060 */
1061 if (AR_SREV_9300_22(ah))
1062 ah->config.hw_hang_checks |= HW_PHYRESTART_CLC_WAR;
1063
1064 if (AR_SREV_9330(ah))
1065 ah->bb_watchdog_timeout_ms = 85;
1066 else
1067 ah->bb_watchdog_timeout_ms = 25;
1068}
1069
222e0483
SM		 1070/*
1071 * MAC HW hang check
1072 * =================
1073 *
1074 * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1.
1075 *
1076 * The state of each DCU chain (mapped to TX queues) is available from these
1077 * DMA debug registers:
1078 *
1079 * Chain 0 state : Bits 4:0 of AR_DMADBG_4
1080 * Chain 1 state : Bits 9:5 of AR_DMADBG_4
1081 * Chain 2 state : Bits 14:10 of AR_DMADBG_4
1082 * Chain 3 state : Bits 19:15 of AR_DMADBG_4
1083 * Chain 4 state : Bits 24:20 of AR_DMADBG_4
1084 * Chain 5 state : Bits 29:25 of AR_DMADBG_4
1085 * Chain 6 state : Bits 4:0 of AR_DMADBG_5
1086 * Chain 7 state : Bits 9:5 of AR_DMADBG_5
1087 * Chain 8 state : Bits 14:10 of AR_DMADBG_5
1088 * Chain 9 state : Bits 19:15 of AR_DMADBG_5
1089 *
1090 * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done.
1091 */
990de2b2 1092
222e0483 1093#define NUM_STATUS_READS 50
990de2b2 1094
222e0483 1095static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue)
990de2b2 1096{
222e0483
SM		 1097 u32 dma_dbg_chain, dma_dbg_complete;
1098 u8 dcu_chain_state, dcu_complete_state;
1099 int i;
990de2b2 1100
222e0483
SM		 1101 for (i = 0; i < NUM_STATUS_READS; i++) {
1102 if (queue < 6)
1103 dma_dbg_chain = REG_READ(ah, AR_DMADBG_4);
1104 else
1105 dma_dbg_chain = REG_READ(ah, AR_DMADBG_5);
990de2b2 1106
222e0483 1107 dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);
990de2b2 1108
222e0483
SM		 1109 dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f;
1110 dcu_complete_state = dma_dbg_complete & 0x3;
990de2b2 1111
222e0483
SM		 1112 if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))
1113 return false;
1114 }
990de2b2
SM		 1115
1116 ath_dbg(ath9k_hw_common(ah), RESET,
222e0483 1117 "MAC Hang signature found for queue: %d\n", queue);
990de2b2 1118
222e0483
SM		 1119 return true;
1120}
990de2b2 1121
222e0483
SM		 1122static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
1123{
1124 u32 dma_dbg_4, dma_dbg_5, dma_dbg_6, chk_dbg;
1125 u8 dcu_chain_state, dcu_complete_state;
1126 bool dcu_wait_frdone = false;
1127 unsigned long chk_dcu = 0;
1128 unsigned int i = 0;
1129
1130 dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
1131 dma_dbg_5 = REG_READ(ah, AR_DMADBG_5);
1132 dma_dbg_6 = REG_READ(ah, AR_DMADBG_6);
1133
1134 dcu_complete_state = dma_dbg_6 & 0x3;
1135 if (dcu_complete_state != 0x1)
1136 goto exit;
1137
1138 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1139 if (i < 6)
1140 chk_dbg = dma_dbg_4;
1141 else
1142 chk_dbg = dma_dbg_5;
990de2b2 1143
222e0483
SM		 1144 dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f;
1145 if (dcu_chain_state == 0x6) {
1146 dcu_wait_frdone = true;
1147 chk_dcu |= BIT(i);
1148 }
990de2b2
SM		 1149 }
1150
222e0483
SM		 1151 if ((dcu_complete_state == 0x1) && dcu_wait_frdone) {
1152 for_each_set_bit(i, &chk_dcu, ATH9K_NUM_TX_QUEUES) {
1153 if (ath9k_hw_verify_hang(ah, i))
1154 return true;
1155 }
1156 }
1157exit:
1158 return false;
990de2b2
SM		 1159}
1160
b3950e6a
LR		 1161/* Sets up the AR9003 hardware familiy callbacks */
1162void ar9003_hw_attach_ops(struct ath_hw *ah)
1163{
1164 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1165 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1166
6aaacd86 1167 ar9003_hw_init_mode_regs(ah);
93f7d6f3
SM		 1168
1169 if (AR_SREV_9003_PCOEM(ah)) {
1170 WARN_ON(!ah->iniPcieSerdes.ia_array);
1171 WARN_ON(!ah->iniPcieSerdesLowPower.ia_array);
1172 }
1173
c14a85da 1174 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
4598702d 1175 priv_ops->init_hang_checks = ar9003_hw_init_hang_checks;
990de2b2 1176 priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang;
b3950e6a
LR		 1177
1178 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
1179
1180 ar9003_hw_attach_phy_ops(ah);
1181 ar9003_hw_attach_calib_ops(ah);
1182 ar9003_hw_attach_mac_ops(ah);
637625f2 1183 ar9003_hw_attach_aic_ops(ah);
b3950e6a 1184}
Linux 6.x block layer and io_uring tree(s)