[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / ar9003_eeprom.h

/*
 * Copyright (c) 2010-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef AR9003_EEPROM_H
#define AR9003_EEPROM_H

#include <linux/types.h>

#define AR9300_EEP_VER               0xD000
#define AR9300_EEP_VER_MINOR_MASK    0xFFF
#define AR9300_EEP_MINOR_VER_1       0x1
#define AR9300_EEP_MINOR_VER         AR9300_EEP_MINOR_VER_1

/* 16-bit offset location start of calibration struct */
#define AR9300_EEP_START_LOC         256
#define AR9300_NUM_5G_CAL_PIERS      8
#define AR9300_NUM_2G_CAL_PIERS      3
#define AR9300_NUM_5G_20_TARGET_POWERS  8
#define AR9300_NUM_5G_40_TARGET_POWERS  8
#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
#define AR9300_NUM_2G_20_TARGET_POWERS  3
#define AR9300_NUM_2G_40_TARGET_POWERS  3
/* #define AR9300_NUM_CTLS              21 */
#define AR9300_NUM_CTLS_5G           9
#define AR9300_NUM_CTLS_2G           12
#define AR9300_NUM_BAND_EDGES_5G     8
#define AR9300_NUM_BAND_EDGES_2G     4
#define AR9300_EEPMISC_WOW           0x02
#define AR9300_CUSTOMER_DATA_SIZE    20

#define AR9300_MAX_CHAINS            3
#define AR9300_ANT_16S               25
#define AR9300_FUTURE_MODAL_SZ       6

#define AR9300_PAPRD_RATE_MASK		0x01ffffff
#define AR9300_PAPRD_SCALE_1		0x0e000000
#define AR9300_PAPRD_SCALE_1_S		25
#define AR9300_PAPRD_SCALE_2		0x70000000
#define AR9300_PAPRD_SCALE_2_S		28

#define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE 0xc9

/* Delta from which to start power to pdadc table */
/* This offset is used in both open loop and closed loop power control
 * schemes. In open loop power control, it is not really needed, but for
 * the "sake of consistency" it was kept. For certain AP designs, this
 * value is overwritten by the value in the flag "pwrTableOffset" just
 * before writing the pdadc vs pwr into the chip registers.
 */
#define AR9300_PWR_TABLE_OFFSET  0

/* byte addressable */
#define AR9300_EEPROM_SIZE (16*1024)

#define AR9300_BASE_ADDR_4K 0xfff
#define AR9300_BASE_ADDR 0x3ff
#define AR9300_BASE_ADDR_512 0x1ff

/* AR5416_EEPMISC_BIG_ENDIAN not set indicates little endian */
#define AR9300_EEPMISC_LITTLE_ENDIAN 0

#define AR9300_OTP_BASE \
		((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30000 : 0x14000)
#define AR9300_OTP_STATUS \
		((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x31018 : 0x15f18)
#define AR9300_OTP_STATUS_TYPE		0x7
#define AR9300_OTP_STATUS_VALID		0x4
#define AR9300_OTP_STATUS_ACCESS_BUSY	0x2
#define AR9300_OTP_STATUS_SM_BUSY	0x1
#define AR9300_OTP_READ_DATA \
		((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x3101c : 0x15f1c)

enum targetPowerHTRates {
	HT_TARGET_RATE_0_8_16,
	HT_TARGET_RATE_1_3_9_11_17_19,
	HT_TARGET_RATE_4,
	HT_TARGET_RATE_5,
	HT_TARGET_RATE_6,
	HT_TARGET_RATE_7,
	HT_TARGET_RATE_12,
	HT_TARGET_RATE_13,
	HT_TARGET_RATE_14,
	HT_TARGET_RATE_15,
	HT_TARGET_RATE_20,
	HT_TARGET_RATE_21,
	HT_TARGET_RATE_22,
	HT_TARGET_RATE_23
};

enum targetPowerLegacyRates {
	LEGACY_TARGET_RATE_6_24,
	LEGACY_TARGET_RATE_36,
	LEGACY_TARGET_RATE_48,
	LEGACY_TARGET_RATE_54
};

enum targetPowerCckRates {
	LEGACY_TARGET_RATE_1L_5L,
	LEGACY_TARGET_RATE_5S,
	LEGACY_TARGET_RATE_11L,
	LEGACY_TARGET_RATE_11S
};

enum ar9300_Rates {
	ALL_TARGET_LEGACY_6_24,
	ALL_TARGET_LEGACY_36,
	ALL_TARGET_LEGACY_48,
	ALL_TARGET_LEGACY_54,
	ALL_TARGET_LEGACY_1L_5L,
	ALL_TARGET_LEGACY_5S,
	ALL_TARGET_LEGACY_11L,
	ALL_TARGET_LEGACY_11S,
	ALL_TARGET_HT20_0_8_16,
	ALL_TARGET_HT20_1_3_9_11_17_19,
	ALL_TARGET_HT20_4,
	ALL_TARGET_HT20_5,
	ALL_TARGET_HT20_6,
	ALL_TARGET_HT20_7,
	ALL_TARGET_HT20_12,
	ALL_TARGET_HT20_13,
	ALL_TARGET_HT20_14,
	ALL_TARGET_HT20_15,
	ALL_TARGET_HT20_20,
	ALL_TARGET_HT20_21,
	ALL_TARGET_HT20_22,
	ALL_TARGET_HT20_23,
	ALL_TARGET_HT40_0_8_16,
	ALL_TARGET_HT40_1_3_9_11_17_19,
	ALL_TARGET_HT40_4,
	ALL_TARGET_HT40_5,
	ALL_TARGET_HT40_6,
	ALL_TARGET_HT40_7,
	ALL_TARGET_HT40_12,
	ALL_TARGET_HT40_13,
	ALL_TARGET_HT40_14,
	ALL_TARGET_HT40_15,
	ALL_TARGET_HT40_20,
	ALL_TARGET_HT40_21,
	ALL_TARGET_HT40_22,
	ALL_TARGET_HT40_23,
	ar9300RateSize,
};


struct eepFlags {
	u8 opFlags;
	u8 eepMisc;
} __packed;

enum CompressAlgorithm {
	_CompressNone = 0,
	_CompressLzma,
	_CompressPairs,
	_CompressBlock,
	_Compress4,
	_Compress5,
	_Compress6,
	_Compress7,
};

struct ar9300_base_eep_hdr {
	__le16 regDmn[2];
	/* 4 bits tx and 4 bits rx */
	u8 txrxMask;
	struct eepFlags opCapFlags;
	u8 rfSilent;
	u8 blueToothOptions;
	u8 deviceCap;
	/* takes lower byte in eeprom location */
	u8 deviceType;
	/* offset in dB to be added to beginning
	 * of pdadc table in calibration
	 */
	int8_t pwrTableOffset;
	u8 params_for_tuning_caps[2];
	/*
	 * bit0 - enable tx temp comp
	 * bit1 - enable tx volt comp
	 * bit2 - enable fastClock - default to 1
	 * bit3 - enable doubling - default to 1
	 * bit4 - enable internal regulator - default to 1
	 */
	u8 featureEnable;
	/* misc flags: bit0 - turn down drivestrength */
	u8 miscConfiguration;
	u8 eepromWriteEnableGpio;
	u8 wlanDisableGpio;
	u8 wlanLedGpio;
	u8 rxBandSelectGpio;
	u8 txrxgain;
	/* SW controlled internal regulator fields */
	__le32 swreg;
} __packed;

struct ar9300_modal_eep_header {
	/* 4 idle, t1, t2, b (4 bits per setting) */
	__le32 antCtrlCommon;
	/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
	__le32 antCtrlCommon2;
	/* 6 idle, t, r, rx1, rx12, b (2 bits each) */
	__le16 antCtrlChain[AR9300_MAX_CHAINS];
	/* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
	u8 xatten1DB[AR9300_MAX_CHAINS];
	/* 3  xatten1_margin for merlin (0xa20c/b20c 16:12 */
	u8 xatten1Margin[AR9300_MAX_CHAINS];
	int8_t tempSlope;
	int8_t voltSlope;
	/* spur channels in usual fbin coding format */
	u8 spurChans[AR_EEPROM_MODAL_SPURS];
	/* 3  Check if the register is per chain */
	int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
	u8 reserved[11];
	int8_t quick_drop;
	u8 xpaBiasLvl;
	u8 txFrameToDataStart;
	u8 txFrameToPaOn;
	u8 txClip;
	int8_t antennaGain;
	u8 switchSettling;
	int8_t adcDesiredSize;
	u8 txEndToXpaOff;
	u8 txEndToRxOn;
	u8 txFrameToXpaOn;
	u8 thresh62;
	__le32 papdRateMaskHt20;
	__le32 papdRateMaskHt40;
	__le16 switchcomspdt;
	u8 xlna_bias_strength;
	u8 futureModal[7];
} __packed;

struct ar9300_cal_data_per_freq_op_loop {
	int8_t refPower;
	/* pdadc voltage at power measurement */
	u8 voltMeas;
	/* pcdac used for power measurement   */
	u8 tempMeas;
	/* range is -60 to -127 create a mapping equation 1db resolution */
	int8_t rxNoisefloorCal;
	/*range is same as noisefloor */
	int8_t rxNoisefloorPower;
	/* temp measured when noisefloor cal was performed */
	u8 rxTempMeas;
} __packed;

struct cal_tgt_pow_legacy {
	u8 tPow2x[4];
} __packed;

struct cal_tgt_pow_ht {
	u8 tPow2x[14];
} __packed;

struct cal_ctl_data_2g {
	u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
} __packed;

struct cal_ctl_data_5g {
	u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
} __packed;

#define MAX_BASE_EXTENSION_FUTURE 2

struct ar9300_BaseExtension_1 {
	u8 ant_div_control;
	u8 future[MAX_BASE_EXTENSION_FUTURE];
	/*
	 * misc_enable:
	 *
	 * BIT 0   - TX Gain Cap enable.
	 * BIT 1   - Uncompressed Checksum enable.
	 * BIT 2/3 - MinCCApwr enable 2g/5g.
	 */
	u8 misc_enable;
	int8_t tempslopextension[8];
	int8_t quick_drop_low;
	int8_t quick_drop_high;
} __packed;

struct ar9300_BaseExtension_2 {
	int8_t    tempSlopeLow;
	int8_t    tempSlopeHigh;
	u8   xatten1DBLow[AR9300_MAX_CHAINS];
	u8   xatten1MarginLow[AR9300_MAX_CHAINS];
	u8   xatten1DBHigh[AR9300_MAX_CHAINS];
	u8   xatten1MarginHigh[AR9300_MAX_CHAINS];
} __packed;

struct ar9300_eeprom {
	u8 eepromVersion;
	u8 templateVersion;
	u8 macAddr[6];
	u8 custData[AR9300_CUSTOMER_DATA_SIZE];

	struct ar9300_base_eep_hdr baseEepHeader;

	struct ar9300_modal_eep_header modalHeader2G;
	struct ar9300_BaseExtension_1 base_ext1;
	u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
	struct ar9300_cal_data_per_freq_op_loop
	 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
	u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
	u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
	u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
	u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
	struct cal_tgt_pow_legacy
	 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
	struct cal_tgt_pow_legacy
	 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
	struct cal_tgt_pow_ht
	 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
	struct cal_tgt_pow_ht
	 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
	u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
	u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
	struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
	struct ar9300_modal_eep_header modalHeader5G;
	struct ar9300_BaseExtension_2 base_ext2;
	u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
	struct ar9300_cal_data_per_freq_op_loop
	 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
	u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
	u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
	u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
	struct cal_tgt_pow_legacy
	 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
	struct cal_tgt_pow_ht
	 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
	struct cal_tgt_pow_ht
	 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
	u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
	u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
	struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
} __packed;

s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz);
u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz);

u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);

unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
					   struct ath9k_channel *chan);

void ar9003_hw_internal_regulator_apply(struct ath_hw *ah);
int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray);

#endif
Commit	Line	Data
5b68138e SM	1	/*
	2	* Copyright (c) 2010-2011 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
15c9ee7a SB	17	#ifndef AR9003_EEPROM_H
	18	#define AR9003_EEPROM_H
	19
	20	#include <linux/types.h>
	21
	22	#define AR9300_EEP_VER 0xD000
	23	#define AR9300_EEP_VER_MINOR_MASK 0xFFF
	24	#define AR9300_EEP_MINOR_VER_1 0x1
	25	#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
	26
	27	/* 16-bit offset location start of calibration struct */
	28	#define AR9300_EEP_START_LOC 256
	29	#define AR9300_NUM_5G_CAL_PIERS 8
	30	#define AR9300_NUM_2G_CAL_PIERS 3
	31	#define AR9300_NUM_5G_20_TARGET_POWERS 8
	32	#define AR9300_NUM_5G_40_TARGET_POWERS 8
	33	#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
	34	#define AR9300_NUM_2G_20_TARGET_POWERS 3
	35	#define AR9300_NUM_2G_40_TARGET_POWERS 3
	36	/* #define AR9300_NUM_CTLS 21 */
	37	#define AR9300_NUM_CTLS_5G 9
	38	#define AR9300_NUM_CTLS_2G 12
15c9ee7a SB	39	#define AR9300_NUM_BAND_EDGES_5G 8
15c9ee7a SB	40	#define AR9300_NUM_BAND_EDGES_2G 4
15c9ee7a SB	41	#define AR9300_EEPMISC_WOW 0x02
	42	#define AR9300_CUSTOMER_DATA_SIZE 20
	43
15c9ee7a SB	44	#define AR9300_MAX_CHAINS 3
	45	#define AR9300_ANT_16S 25
	46	#define AR9300_FUTURE_MODAL_SZ 6
	47
1782352d FF	48	#define AR9300_PAPRD_RATE_MASK 0x01ffffff
	49	#define AR9300_PAPRD_SCALE_1 0x0e000000
	50	#define AR9300_PAPRD_SCALE_1_S 25
	51	#define AR9300_PAPRD_SCALE_2 0x70000000
	52	#define AR9300_PAPRD_SCALE_2_S 28
	53
7e12d6a4 SM	54	#define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE 0xc9
7e12d6a4 SM	55
15c9ee7a SB	56	/* Delta from which to start power to pdadc table */
	57	/* This offset is used in both open loop and closed loop power control
	58	* schemes. In open loop power control, it is not really needed, but for
	59	* the "sake of consistency" it was kept. For certain AP designs, this
	60	* value is overwritten by the value in the flag "pwrTableOffset" just
	61	* before writing the pdadc vs pwr into the chip registers.
	62	*/
	63	#define AR9300_PWR_TABLE_OFFSET 0
	64
15c9ee7a SB	65	/* byte addressable */
15c9ee7a SB	66	#define AR9300_EEPROM_SIZE (16*1024)
15c9ee7a	67
60e0c3a7	68	#define AR9300_BASE_ADDR_4K 0xfff
15c9ee7a	69	#define AR9300_BASE_ADDR 0x3ff
488f6ba7 FF	70	#define AR9300_BASE_ADDR_512 0x1ff
488f6ba7 FF	71
291478b7 MB	72	/* AR5416_EEPMISC_BIG_ENDIAN not set indicates little endian */
	73	#define AR9300_EEPMISC_LITTLE_ENDIAN 0
	74
add295a4 GJ	75	#define AR9300_OTP_BASE \
	76	((AR_SREV_9340(ah) \|\| AR_SREV_9550(ah)) ? 0x30000 : 0x14000)
	77	#define AR9300_OTP_STATUS \
c9f1e326	78	((AR_SREV_9340(ah) \|\| AR_SREV_9550(ah)) ? 0x31018 : 0x15f18)
488f6ba7 FF	79	#define AR9300_OTP_STATUS_TYPE 0x7
	80	#define AR9300_OTP_STATUS_VALID 0x4
	81	#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
	82	#define AR9300_OTP_STATUS_SM_BUSY 0x1
add295a4	83	#define AR9300_OTP_READ_DATA \
c9f1e326	84	((AR_SREV_9340(ah) \|\| AR_SREV_9550(ah)) ? 0x3101c : 0x15f1c)
15c9ee7a SB	85
	86	enum targetPowerHTRates {
	87	HT_TARGET_RATE_0_8_16,
	88	HT_TARGET_RATE_1_3_9_11_17_19,
	89	HT_TARGET_RATE_4,
	90	HT_TARGET_RATE_5,
	91	HT_TARGET_RATE_6,
	92	HT_TARGET_RATE_7,
	93	HT_TARGET_RATE_12,
	94	HT_TARGET_RATE_13,
	95	HT_TARGET_RATE_14,
	96	HT_TARGET_RATE_15,
	97	HT_TARGET_RATE_20,
	98	HT_TARGET_RATE_21,
	99	HT_TARGET_RATE_22,
	100	HT_TARGET_RATE_23
	101	};
	102
	103	enum targetPowerLegacyRates {
	104	LEGACY_TARGET_RATE_6_24,
	105	LEGACY_TARGET_RATE_36,
	106	LEGACY_TARGET_RATE_48,
	107	LEGACY_TARGET_RATE_54
	108	};
	109
	110	enum targetPowerCckRates {
	111	LEGACY_TARGET_RATE_1L_5L,
	112	LEGACY_TARGET_RATE_5S,
	113	LEGACY_TARGET_RATE_11L,
	114	LEGACY_TARGET_RATE_11S
	115	};
	116
	117	enum ar9300_Rates {
	118	ALL_TARGET_LEGACY_6_24,
	119	ALL_TARGET_LEGACY_36,
	120	ALL_TARGET_LEGACY_48,
	121	ALL_TARGET_LEGACY_54,
	122	ALL_TARGET_LEGACY_1L_5L,
	123	ALL_TARGET_LEGACY_5S,
	124	ALL_TARGET_LEGACY_11L,
	125	ALL_TARGET_LEGACY_11S,
	126	ALL_TARGET_HT20_0_8_16,
	127	ALL_TARGET_HT20_1_3_9_11_17_19,
	128	ALL_TARGET_HT20_4,
	129	ALL_TARGET_HT20_5,
	130	ALL_TARGET_HT20_6,
	131	ALL_TARGET_HT20_7,
	132	ALL_TARGET_HT20_12,
	133	ALL_TARGET_HT20_13,
	134	ALL_TARGET_HT20_14,
	135	ALL_TARGET_HT20_15,
	136	ALL_TARGET_HT20_20,
	137	ALL_TARGET_HT20_21,
	138	ALL_TARGET_HT20_22,
	139	ALL_TARGET_HT20_23,
	140	ALL_TARGET_HT40_0_8_16,
	141	ALL_TARGET_HT40_1_3_9_11_17_19,
	142	ALL_TARGET_HT40_4,
	143	ALL_TARGET_HT40_5,
	144	ALL_TARGET_HT40_6,
	145	ALL_TARGET_HT40_7,
	146	ALL_TARGET_HT40_12,
	147	ALL_TARGET_HT40_13,
	148	ALL_TARGET_HT40_14,
149	ALL_TARGET_HT40_15,
150	ALL_TARGET_HT40_20,
151	ALL_TARGET_HT40_21,
152	ALL_TARGET_HT40_22,
153	ALL_TARGET_HT40_23,
154	ar9300RateSize,
155	};
156
157
158	struct eepFlags {
159	u8 opFlags;
160	u8 eepMisc;
161	} __packed;
162
163	enum CompressAlgorithm {
164	_CompressNone = 0,
165	_CompressLzma,
166	_CompressPairs,
167	_CompressBlock,
168	_Compress4,
169	_Compress5,
170	_Compress6,
171	_Compress7,
172	};
173
174	struct ar9300_base_eep_hdr {
ffdc4cbe	175	__le16 regDmn[2];
15c9ee7a SB	176	/* 4 bits tx and 4 bits rx */
	177	u8 txrxMask;
	178	struct eepFlags opCapFlags;
	179	u8 rfSilent;
	180	u8 blueToothOptions;
	181	u8 deviceCap;
	182	/* takes lower byte in eeprom location */
	183	u8 deviceType;
	184	/* offset in dB to be added to beginning
	185	* of pdadc table in calibration
	186	*/
	187	int8_t pwrTableOffset;
	188	u8 params_for_tuning_caps[2];
	189	/*
	190	* bit0 - enable tx temp comp
	191	* bit1 - enable tx volt comp
	192	* bit2 - enable fastClock - default to 1
	193	* bit3 - enable doubling - default to 1
	194	* bit4 - enable internal regulator - default to 1
	195	*/
	196	u8 featureEnable;
	197	/* misc flags: bit0 - turn down drivestrength */
	198	u8 miscConfiguration;
	199	u8 eepromWriteEnableGpio;
	200	u8 wlanDisableGpio;
	201	u8 wlanLedGpio;
	202	u8 rxBandSelectGpio;
	203	u8 txrxgain;
	204	/* SW controlled internal regulator fields */
ffdc4cbe	205	__le32 swreg;
15c9ee7a SB	206	} __packed;
	207
	208	struct ar9300_modal_eep_header {
	209	/* 4 idle, t1, t2, b (4 bits per setting) */
ffdc4cbe	210	__le32 antCtrlCommon;
15c9ee7a	211	/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
ffdc4cbe	212	__le32 antCtrlCommon2;
15c9ee7a	213	/* 6 idle, t, r, rx1, rx12, b (2 bits each) */
ffdc4cbe	214	__le16 antCtrlChain[AR9300_MAX_CHAINS];
15c9ee7a SB	215	/* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
	216	u8 xatten1DB[AR9300_MAX_CHAINS];
	217	/* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
	218	u8 xatten1Margin[AR9300_MAX_CHAINS];
	219	int8_t tempSlope;
	220	int8_t voltSlope;
	221	/* spur channels in usual fbin coding format */
4ddfcd7d	222	u8 spurChans[AR_EEPROM_MODAL_SPURS];
15c9ee7a SB	223	/* 3 Check if the register is per chain */
15c9ee7a SB	224	int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
df222edc RM	225	u8 reserved[11];
df222edc RM	226	int8_t quick_drop;
15c9ee7a SB	227	u8 xpaBiasLvl;
	228	u8 txFrameToDataStart;
	229	u8 txFrameToPaOn;
	230	u8 txClip;
	231	int8_t antennaGain;
	232	u8 switchSettling;
	233	int8_t adcDesiredSize;
	234	u8 txEndToXpaOff;
	235	u8 txEndToRxOn;
	236	u8 txFrameToXpaOn;
	237	u8 thresh62;
4935250a FF	238	__le32 papdRateMaskHt20;
4935250a FF	239	__le32 papdRateMaskHt40;
2577c6e8	240	__le16 switchcomspdt;
3e2ea543 FF	241	u8 xlna_bias_strength;
3e2ea543 FF	242	u8 futureModal[7];
15c9ee7a SB	243	} __packed;
	244
	245	struct ar9300_cal_data_per_freq_op_loop {
	246	int8_t refPower;
	247	/* pdadc voltage at power measurement */
	248	u8 voltMeas;
	249	/* pcdac used for power measurement */
	250	u8 tempMeas;
	251	/* range is -60 to -127 create a mapping equation 1db resolution */
	252	int8_t rxNoisefloorCal;
	253	/range is same as noisefloor /
	254	int8_t rxNoisefloorPower;
	255	/* temp measured when noisefloor cal was performed */
	256	u8 rxTempMeas;
	257	} __packed;
	258
	259	struct cal_tgt_pow_legacy {
	260	u8 tPow2x[4];
	261	} __packed;
	262
	263	struct cal_tgt_pow_ht {
	264	u8 tPow2x[14];
	265	} __packed;
	266
15c9ee7a	267	struct cal_ctl_data_2g {
e702ba18	268	u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
15c9ee7a SB	269	} __packed;
	270
	271	struct cal_ctl_data_5g {
e702ba18	272	u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
15c9ee7a SB	273	} __packed;
15c9ee7a SB	274
ee65b388 SM	275	#define MAX_BASE_EXTENSION_FUTURE 2
ee65b388 SM	276
b3dd6bc1 SB	277	struct ar9300_BaseExtension_1 {
b3dd6bc1 SB	278	u8 ant_div_control;
ee65b388 SM	279	u8 future[MAX_BASE_EXTENSION_FUTURE];
	280	/*
	281	* misc_enable:
	282	*
	283	* BIT 0 - TX Gain Cap enable.
	284	* BIT 1 - Uncompressed Checksum enable.
	285	* BIT 2/3 - MinCCApwr enable 2g/5g.
	286	*/
	287	u8 misc_enable;
	288	int8_t tempslopextension[8];
df222edc RM	289	int8_t quick_drop_low;
df222edc RM	290	int8_t quick_drop_high;
b3dd6bc1 SB	291	} __packed;
	292
	293	struct ar9300_BaseExtension_2 {
	294	int8_t tempSlopeLow;
	295	int8_t tempSlopeHigh;
	296	u8 xatten1DBLow[AR9300_MAX_CHAINS];
	297	u8 xatten1MarginLow[AR9300_MAX_CHAINS];
	298	u8 xatten1DBHigh[AR9300_MAX_CHAINS];
	299	u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
	300	} __packed;
	301
15c9ee7a SB	302	struct ar9300_eeprom {
	303	u8 eepromVersion;
	304	u8 templateVersion;
	305	u8 macAddr[6];
	306	u8 custData[AR9300_CUSTOMER_DATA_SIZE];
	307
	308	struct ar9300_base_eep_hdr baseEepHeader;
	309
	310	struct ar9300_modal_eep_header modalHeader2G;
b3dd6bc1	311	struct ar9300_BaseExtension_1 base_ext1;
15c9ee7a SB	312	u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
	313	struct ar9300_cal_data_per_freq_op_loop
	314	calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
	315	u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
	316	u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
	317	u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
	318	u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
	319	struct cal_tgt_pow_legacy
	320	calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
	321	struct cal_tgt_pow_legacy
	322	calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
	323	struct cal_tgt_pow_ht
	324	calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
	325	struct cal_tgt_pow_ht
	326	calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
	327	u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
	328	u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
	329	struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
	330	struct ar9300_modal_eep_header modalHeader5G;
b3dd6bc1	331	struct ar9300_BaseExtension_2 base_ext2;
15c9ee7a SB	332	u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
	333	struct ar9300_cal_data_per_freq_op_loop
	334	calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
	335	u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
	336	u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
	337	u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
	338	struct cal_tgt_pow_legacy
	339	calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
	340	struct cal_tgt_pow_ht
	341	calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
	342	struct cal_tgt_pow_ht
	343	calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
	344	u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
	345	u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
	346	struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
	347	} __packed;
c14a85da LR	348
	349	s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
	350	s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
84893817 SM	351	u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz);
84893817 SM	352	u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz);
c14a85da	353
272ceba8	354	u8 ar9003_get_spur_chan_ptr(struct ath_hw ah, bool is_2ghz);
8698bca6 VT	355
	356	unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
	357	struct ath9k_channel *chan);
bfc441a4 FF	358
bfc441a4 FF	359	void ar9003_hw_internal_regulator_apply(struct ath_hw *ah);
8569f591	360	int ar9003_hw_tx_power_regwrite(struct ath_hw ah, u8 pPwrArray);
bfc441a4	361
15c9ee7a	362	#endif