[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / ar9003_eeprom.h

#ifndef AR9003_EEPROM_H
#define AR9003_EEPROM_H

#include <linux/types.h>

#define AR9300_EEP_VER               0xD000
#define AR9300_EEP_VER_MINOR_MASK    0xFFF
#define AR9300_EEP_MINOR_VER_1       0x1
#define AR9300_EEP_MINOR_VER         AR9300_EEP_MINOR_VER_1

/* 16-bit offset location start of calibration struct */
#define AR9300_EEP_START_LOC         256
#define AR9300_NUM_5G_CAL_PIERS      8
#define AR9300_NUM_2G_CAL_PIERS      3
#define AR9300_NUM_5G_20_TARGET_POWERS  8
#define AR9300_NUM_5G_40_TARGET_POWERS  8
#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
#define AR9300_NUM_2G_20_TARGET_POWERS  3
#define AR9300_NUM_2G_40_TARGET_POWERS  3
/* #define AR9300_NUM_CTLS              21 */
#define AR9300_NUM_CTLS_5G           9
#define AR9300_NUM_CTLS_2G           12
#define AR9300_NUM_BAND_EDGES_5G     8
#define AR9300_NUM_BAND_EDGES_2G     4
#define AR9300_EEPMISC_BIG_ENDIAN    0x01
#define AR9300_EEPMISC_WOW           0x02
#define AR9300_CUSTOMER_DATA_SIZE    20

#define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
#define AR9300_MAX_CHAINS            3
#define AR9300_ANT_16S               25
#define AR9300_FUTURE_MODAL_SZ       6

#define AR9300_PAPRD_RATE_MASK		0x01ffffff
#define AR9300_PAPRD_SCALE_1		0x0e000000
#define AR9300_PAPRD_SCALE_1_S		25
#define AR9300_PAPRD_SCALE_2		0x70000000
#define AR9300_PAPRD_SCALE_2_S		28

/* Delta from which to start power to pdadc table */
/* This offset is used in both open loop and closed loop power control
 * schemes. In open loop power control, it is not really needed, but for
 * the "sake of consistency" it was kept. For certain AP designs, this
 * value is overwritten by the value in the flag "pwrTableOffset" just
 * before writing the pdadc vs pwr into the chip registers.
 */
#define AR9300_PWR_TABLE_OFFSET  0

/* byte addressable */
#define AR9300_EEPROM_SIZE (16*1024)

#define AR9300_BASE_ADDR_4K 0xfff
#define AR9300_BASE_ADDR 0x3ff
#define AR9300_BASE_ADDR_512 0x1ff

#define AR9300_OTP_BASE			0x14000
#define AR9300_OTP_STATUS		0x15f18
#define AR9300_OTP_STATUS_TYPE		0x7
#define AR9300_OTP_STATUS_VALID		0x4
#define AR9300_OTP_STATUS_ACCESS_BUSY	0x2
#define AR9300_OTP_STATUS_SM_BUSY	0x1
#define AR9300_OTP_READ_DATA		0x15f1c

enum targetPowerHTRates {
	HT_TARGET_RATE_0_8_16,
	HT_TARGET_RATE_1_3_9_11_17_19,
	HT_TARGET_RATE_4,
	HT_TARGET_RATE_5,
	HT_TARGET_RATE_6,
	HT_TARGET_RATE_7,
	HT_TARGET_RATE_12,
	HT_TARGET_RATE_13,
	HT_TARGET_RATE_14,
	HT_TARGET_RATE_15,
	HT_TARGET_RATE_20,
	HT_TARGET_RATE_21,
	HT_TARGET_RATE_22,
	HT_TARGET_RATE_23
};

enum targetPowerLegacyRates {
	LEGACY_TARGET_RATE_6_24,
	LEGACY_TARGET_RATE_36,
	LEGACY_TARGET_RATE_48,
	LEGACY_TARGET_RATE_54
};

enum targetPowerCckRates {
	LEGACY_TARGET_RATE_1L_5L,
	LEGACY_TARGET_RATE_5S,
	LEGACY_TARGET_RATE_11L,
	LEGACY_TARGET_RATE_11S
};

enum ar9300_Rates {
	ALL_TARGET_LEGACY_6_24,
	ALL_TARGET_LEGACY_36,
	ALL_TARGET_LEGACY_48,
	ALL_TARGET_LEGACY_54,
	ALL_TARGET_LEGACY_1L_5L,
	ALL_TARGET_LEGACY_5S,
	ALL_TARGET_LEGACY_11L,
	ALL_TARGET_LEGACY_11S,
	ALL_TARGET_HT20_0_8_16,
	ALL_TARGET_HT20_1_3_9_11_17_19,
	ALL_TARGET_HT20_4,
	ALL_TARGET_HT20_5,
	ALL_TARGET_HT20_6,
	ALL_TARGET_HT20_7,
	ALL_TARGET_HT20_12,
	ALL_TARGET_HT20_13,
	ALL_TARGET_HT20_14,
	ALL_TARGET_HT20_15,
	ALL_TARGET_HT20_20,
	ALL_TARGET_HT20_21,
	ALL_TARGET_HT20_22,
	ALL_TARGET_HT20_23,
	ALL_TARGET_HT40_0_8_16,
	ALL_TARGET_HT40_1_3_9_11_17_19,
	ALL_TARGET_HT40_4,
	ALL_TARGET_HT40_5,
	ALL_TARGET_HT40_6,
	ALL_TARGET_HT40_7,
	ALL_TARGET_HT40_12,
	ALL_TARGET_HT40_13,
	ALL_TARGET_HT40_14,
	ALL_TARGET_HT40_15,
	ALL_TARGET_HT40_20,
	ALL_TARGET_HT40_21,
	ALL_TARGET_HT40_22,
	ALL_TARGET_HT40_23,
	ar9300RateSize,
};


struct eepFlags {
	u8 opFlags;
	u8 eepMisc;
} __packed;

enum CompressAlgorithm {
	_CompressNone = 0,
	_CompressLzma,
	_CompressPairs,
	_CompressBlock,
	_Compress4,
	_Compress5,
	_Compress6,
	_Compress7,
};

struct ar9300_base_eep_hdr {
	__le16 regDmn[2];
	/* 4 bits tx and 4 bits rx */
	u8 txrxMask;
	struct eepFlags opCapFlags;
	u8 rfSilent;
	u8 blueToothOptions;
	u8 deviceCap;
	/* takes lower byte in eeprom location */
	u8 deviceType;
	/* offset in dB to be added to beginning
	 * of pdadc table in calibration
	 */
	int8_t pwrTableOffset;
	u8 params_for_tuning_caps[2];
	/*
	 * bit0 - enable tx temp comp
	 * bit1 - enable tx volt comp
	 * bit2 - enable fastClock - default to 1
	 * bit3 - enable doubling - default to 1
	 * bit4 - enable internal regulator - default to 1
	 */
	u8 featureEnable;
	/* misc flags: bit0 - turn down drivestrength */
	u8 miscConfiguration;
	u8 eepromWriteEnableGpio;
	u8 wlanDisableGpio;
	u8 wlanLedGpio;
	u8 rxBandSelectGpio;
	u8 txrxgain;
	/* SW controlled internal regulator fields */
	__le32 swreg;
} __packed;

struct ar9300_modal_eep_header {
	/* 4 idle, t1, t2, b (4 bits per setting) */
	__le32 antCtrlCommon;
	/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
	__le32 antCtrlCommon2;
	/* 6 idle, t, r, rx1, rx12, b (2 bits each) */
	__le16 antCtrlChain[AR9300_MAX_CHAINS];
	/* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
	u8 xatten1DB[AR9300_MAX_CHAINS];
	/* 3  xatten1_margin for merlin (0xa20c/b20c 16:12 */
	u8 xatten1Margin[AR9300_MAX_CHAINS];
	int8_t tempSlope;
	int8_t voltSlope;
	/* spur channels in usual fbin coding format */
	u8 spurChans[AR_EEPROM_MODAL_SPURS];
	/* 3  Check if the register is per chain */
	int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
	u8 ob[AR9300_MAX_CHAINS];
	u8 db_stage2[AR9300_MAX_CHAINS];
	u8 db_stage3[AR9300_MAX_CHAINS];
	u8 db_stage4[AR9300_MAX_CHAINS];
	u8 xpaBiasLvl;
	u8 txFrameToDataStart;
	u8 txFrameToPaOn;
	u8 txClip;
	int8_t antennaGain;
	u8 switchSettling;
	int8_t adcDesiredSize;
	u8 txEndToXpaOff;
	u8 txEndToRxOn;
	u8 txFrameToXpaOn;
	u8 thresh62;
	__le32 papdRateMaskHt20;
	__le32 papdRateMaskHt40;
	u8 futureModal[10];
} __packed;

struct ar9300_cal_data_per_freq_op_loop {
	int8_t refPower;
	/* pdadc voltage at power measurement */
	u8 voltMeas;
	/* pcdac used for power measurement   */
	u8 tempMeas;
	/* range is -60 to -127 create a mapping equation 1db resolution */
	int8_t rxNoisefloorCal;
	/*range is same as noisefloor */
	int8_t rxNoisefloorPower;
	/* temp measured when noisefloor cal was performed */
	u8 rxTempMeas;
} __packed;

struct cal_tgt_pow_legacy {
	u8 tPow2x[4];
} __packed;

struct cal_tgt_pow_ht {
	u8 tPow2x[14];
} __packed;

struct cal_ctl_data_2g {
	u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
} __packed;

struct cal_ctl_data_5g {
	u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
} __packed;

struct ar9300_BaseExtension_1 {
	u8 ant_div_control;
	u8 future[13];
} __packed;

struct ar9300_BaseExtension_2 {
	int8_t    tempSlopeLow;
	int8_t    tempSlopeHigh;
	u8   xatten1DBLow[AR9300_MAX_CHAINS];
	u8   xatten1MarginLow[AR9300_MAX_CHAINS];
	u8   xatten1DBHigh[AR9300_MAX_CHAINS];
	u8   xatten1MarginHigh[AR9300_MAX_CHAINS];
} __packed;

struct ar9300_eeprom {
	u8 eepromVersion;
	u8 templateVersion;
	u8 macAddr[6];
	u8 custData[AR9300_CUSTOMER_DATA_SIZE];

	struct ar9300_base_eep_hdr baseEepHeader;

	struct ar9300_modal_eep_header modalHeader2G;
	struct ar9300_BaseExtension_1 base_ext1;
	u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
	struct ar9300_cal_data_per_freq_op_loop
	 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
	u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
	u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
	u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
	u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
	struct cal_tgt_pow_legacy
	 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
	struct cal_tgt_pow_legacy
	 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
	struct cal_tgt_pow_ht
	 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
	struct cal_tgt_pow_ht
	 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
	u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
	u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
	struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
	struct ar9300_modal_eep_header modalHeader5G;
	struct ar9300_BaseExtension_2 base_ext2;
	u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
	struct ar9300_cal_data_per_freq_op_loop
	 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
	u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
	u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
	u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
	struct cal_tgt_pow_legacy
	 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
	struct cal_tgt_pow_ht
	 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
	struct cal_tgt_pow_ht
	 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
	u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
	u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
	struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
} __packed;

s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);

u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);

unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
					   struct ath9k_channel *chan);
#endif
Commit	Line	Data
15c9ee7a SB	1	#ifndef AR9003_EEPROM_H
	2	#define AR9003_EEPROM_H
	3
	4	#include <linux/types.h>
	5
	6	#define AR9300_EEP_VER 0xD000
	7	#define AR9300_EEP_VER_MINOR_MASK 0xFFF
	8	#define AR9300_EEP_MINOR_VER_1 0x1
	9	#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
	10
	11	/* 16-bit offset location start of calibration struct */
	12	#define AR9300_EEP_START_LOC 256
	13	#define AR9300_NUM_5G_CAL_PIERS 8
	14	#define AR9300_NUM_2G_CAL_PIERS 3
	15	#define AR9300_NUM_5G_20_TARGET_POWERS 8
	16	#define AR9300_NUM_5G_40_TARGET_POWERS 8
	17	#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
	18	#define AR9300_NUM_2G_20_TARGET_POWERS 3
	19	#define AR9300_NUM_2G_40_TARGET_POWERS 3
	20	/* #define AR9300_NUM_CTLS 21 */
	21	#define AR9300_NUM_CTLS_5G 9
	22	#define AR9300_NUM_CTLS_2G 12
15c9ee7a SB	23	#define AR9300_NUM_BAND_EDGES_5G 8
15c9ee7a SB	24	#define AR9300_NUM_BAND_EDGES_2G 4
15c9ee7a SB	25	#define AR9300_EEPMISC_BIG_ENDIAN 0x01
	26	#define AR9300_EEPMISC_WOW 0x02
	27	#define AR9300_CUSTOMER_DATA_SIZE 20
	28
15c9ee7a SB	29	#define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
	30	#define AR9300_MAX_CHAINS 3
	31	#define AR9300_ANT_16S 25
	32	#define AR9300_FUTURE_MODAL_SZ 6
	33
1782352d FF	34	#define AR9300_PAPRD_RATE_MASK 0x01ffffff
	35	#define AR9300_PAPRD_SCALE_1 0x0e000000
	36	#define AR9300_PAPRD_SCALE_1_S 25
	37	#define AR9300_PAPRD_SCALE_2 0x70000000
	38	#define AR9300_PAPRD_SCALE_2_S 28
	39
15c9ee7a SB	40	/* Delta from which to start power to pdadc table */
	41	/* This offset is used in both open loop and closed loop power control
	42	* schemes. In open loop power control, it is not really needed, but for
	43	* the "sake of consistency" it was kept. For certain AP designs, this
	44	* value is overwritten by the value in the flag "pwrTableOffset" just
	45	* before writing the pdadc vs pwr into the chip registers.
	46	*/
	47	#define AR9300_PWR_TABLE_OFFSET 0
	48
15c9ee7a SB	49	/* byte addressable */
15c9ee7a SB	50	#define AR9300_EEPROM_SIZE (16*1024)
15c9ee7a	51
60e0c3a7	52	#define AR9300_BASE_ADDR_4K 0xfff
15c9ee7a	53	#define AR9300_BASE_ADDR 0x3ff
488f6ba7 FF	54	#define AR9300_BASE_ADDR_512 0x1ff
	55
	56	#define AR9300_OTP_BASE 0x14000
	57	#define AR9300_OTP_STATUS 0x15f18
	58	#define AR9300_OTP_STATUS_TYPE 0x7
	59	#define AR9300_OTP_STATUS_VALID 0x4
	60	#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
	61	#define AR9300_OTP_STATUS_SM_BUSY 0x1
	62	#define AR9300_OTP_READ_DATA 0x15f1c
15c9ee7a SB	63
	64	enum targetPowerHTRates {
	65	HT_TARGET_RATE_0_8_16,
	66	HT_TARGET_RATE_1_3_9_11_17_19,
	67	HT_TARGET_RATE_4,
	68	HT_TARGET_RATE_5,
	69	HT_TARGET_RATE_6,
	70	HT_TARGET_RATE_7,
	71	HT_TARGET_RATE_12,
	72	HT_TARGET_RATE_13,
	73	HT_TARGET_RATE_14,
	74	HT_TARGET_RATE_15,
	75	HT_TARGET_RATE_20,
	76	HT_TARGET_RATE_21,
	77	HT_TARGET_RATE_22,
	78	HT_TARGET_RATE_23
	79	};
	80
	81	enum targetPowerLegacyRates {
	82	LEGACY_TARGET_RATE_6_24,
	83	LEGACY_TARGET_RATE_36,
	84	LEGACY_TARGET_RATE_48,
	85	LEGACY_TARGET_RATE_54
	86	};
	87
	88	enum targetPowerCckRates {
	89	LEGACY_TARGET_RATE_1L_5L,
	90	LEGACY_TARGET_RATE_5S,
	91	LEGACY_TARGET_RATE_11L,
	92	LEGACY_TARGET_RATE_11S
	93	};
	94
	95	enum ar9300_Rates {
	96	ALL_TARGET_LEGACY_6_24,
	97	ALL_TARGET_LEGACY_36,
	98	ALL_TARGET_LEGACY_48,
	99	ALL_TARGET_LEGACY_54,
	100	ALL_TARGET_LEGACY_1L_5L,
	101	ALL_TARGET_LEGACY_5S,
	102	ALL_TARGET_LEGACY_11L,
	103	ALL_TARGET_LEGACY_11S,
	104	ALL_TARGET_HT20_0_8_16,
	105	ALL_TARGET_HT20_1_3_9_11_17_19,
	106	ALL_TARGET_HT20_4,
	107	ALL_TARGET_HT20_5,
	108	ALL_TARGET_HT20_6,
	109	ALL_TARGET_HT20_7,
	110	ALL_TARGET_HT20_12,
	111	ALL_TARGET_HT20_13,
	112	ALL_TARGET_HT20_14,
	113	ALL_TARGET_HT20_15,
	114	ALL_TARGET_HT20_20,
	115	ALL_TARGET_HT20_21,
	116	ALL_TARGET_HT20_22,
	117	ALL_TARGET_HT20_23,
	118	ALL_TARGET_HT40_0_8_16,
	119	ALL_TARGET_HT40_1_3_9_11_17_19,
	120	ALL_TARGET_HT40_4,
	121	ALL_TARGET_HT40_5,
	122	ALL_TARGET_HT40_6,
	123	ALL_TARGET_HT40_7,
	124	ALL_TARGET_HT40_12,
	125	ALL_TARGET_HT40_13,
	126	ALL_TARGET_HT40_14,
127	ALL_TARGET_HT40_15,
128	ALL_TARGET_HT40_20,
129	ALL_TARGET_HT40_21,
130	ALL_TARGET_HT40_22,
131	ALL_TARGET_HT40_23,
132	ar9300RateSize,
133	};
134
135
136	struct eepFlags {
137	u8 opFlags;
138	u8 eepMisc;
139	} __packed;
140
141	enum CompressAlgorithm {
142	_CompressNone = 0,
143	_CompressLzma,
144	_CompressPairs,
145	_CompressBlock,
146	_Compress4,
147	_Compress5,
148	_Compress6,
149	_Compress7,
150	};
151
152	struct ar9300_base_eep_hdr {
ffdc4cbe	153	__le16 regDmn[2];
15c9ee7a SB	154	/* 4 bits tx and 4 bits rx */
	155	u8 txrxMask;
	156	struct eepFlags opCapFlags;
	157	u8 rfSilent;
	158	u8 blueToothOptions;
	159	u8 deviceCap;
	160	/* takes lower byte in eeprom location */
	161	u8 deviceType;
	162	/* offset in dB to be added to beginning
	163	* of pdadc table in calibration
	164	*/
	165	int8_t pwrTableOffset;
	166	u8 params_for_tuning_caps[2];
	167	/*
	168	* bit0 - enable tx temp comp
	169	* bit1 - enable tx volt comp
	170	* bit2 - enable fastClock - default to 1
	171	* bit3 - enable doubling - default to 1
	172	* bit4 - enable internal regulator - default to 1
	173	*/
	174	u8 featureEnable;
	175	/* misc flags: bit0 - turn down drivestrength */
	176	u8 miscConfiguration;
	177	u8 eepromWriteEnableGpio;
	178	u8 wlanDisableGpio;
	179	u8 wlanLedGpio;
	180	u8 rxBandSelectGpio;
	181	u8 txrxgain;
	182	/* SW controlled internal regulator fields */
ffdc4cbe	183	__le32 swreg;
15c9ee7a SB	184	} __packed;
	185
	186	struct ar9300_modal_eep_header {
	187	/* 4 idle, t1, t2, b (4 bits per setting) */
ffdc4cbe	188	__le32 antCtrlCommon;
15c9ee7a	189	/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
ffdc4cbe	190	__le32 antCtrlCommon2;
15c9ee7a	191	/* 6 idle, t, r, rx1, rx12, b (2 bits each) */
ffdc4cbe	192	__le16 antCtrlChain[AR9300_MAX_CHAINS];
15c9ee7a SB	193	/* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
	194	u8 xatten1DB[AR9300_MAX_CHAINS];
	195	/* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
	196	u8 xatten1Margin[AR9300_MAX_CHAINS];
	197	int8_t tempSlope;
	198	int8_t voltSlope;
	199	/* spur channels in usual fbin coding format */
4ddfcd7d	200	u8 spurChans[AR_EEPROM_MODAL_SPURS];
15c9ee7a SB	201	/* 3 Check if the register is per chain */
	202	int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
	203	u8 ob[AR9300_MAX_CHAINS];
	204	u8 db_stage2[AR9300_MAX_CHAINS];
	205	u8 db_stage3[AR9300_MAX_CHAINS];
	206	u8 db_stage4[AR9300_MAX_CHAINS];
	207	u8 xpaBiasLvl;
	208	u8 txFrameToDataStart;
	209	u8 txFrameToPaOn;
	210	u8 txClip;
	211	int8_t antennaGain;
	212	u8 switchSettling;
	213	int8_t adcDesiredSize;
	214	u8 txEndToXpaOff;
	215	u8 txEndToRxOn;
	216	u8 txFrameToXpaOn;
	217	u8 thresh62;
4935250a FF	218	__le32 papdRateMaskHt20;
4935250a FF	219	__le32 papdRateMaskHt40;
b3dd6bc1	220	u8 futureModal[10];
15c9ee7a SB	221	} __packed;
	222
	223	struct ar9300_cal_data_per_freq_op_loop {
	224	int8_t refPower;
	225	/* pdadc voltage at power measurement */
	226	u8 voltMeas;
	227	/* pcdac used for power measurement */
	228	u8 tempMeas;
	229	/* range is -60 to -127 create a mapping equation 1db resolution */
	230	int8_t rxNoisefloorCal;
	231	/range is same as noisefloor /
	232	int8_t rxNoisefloorPower;
	233	/* temp measured when noisefloor cal was performed */
	234	u8 rxTempMeas;
	235	} __packed;
	236
	237	struct cal_tgt_pow_legacy {
	238	u8 tPow2x[4];
	239	} __packed;
	240
	241	struct cal_tgt_pow_ht {
	242	u8 tPow2x[14];
	243	} __packed;
	244
15c9ee7a	245	struct cal_ctl_data_2g {
e702ba18	246	u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
15c9ee7a SB	247	} __packed;
	248
	249	struct cal_ctl_data_5g {
e702ba18	250	u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
15c9ee7a SB	251	} __packed;
15c9ee7a SB	252
b3dd6bc1 SB	253	struct ar9300_BaseExtension_1 {
	254	u8 ant_div_control;
	255	u8 future[13];
	256	} __packed;
	257
	258	struct ar9300_BaseExtension_2 {
	259	int8_t tempSlopeLow;
	260	int8_t tempSlopeHigh;
	261	u8 xatten1DBLow[AR9300_MAX_CHAINS];
	262	u8 xatten1MarginLow[AR9300_MAX_CHAINS];
	263	u8 xatten1DBHigh[AR9300_MAX_CHAINS];
	264	u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
	265	} __packed;
	266
15c9ee7a SB	267	struct ar9300_eeprom {
	268	u8 eepromVersion;
	269	u8 templateVersion;
	270	u8 macAddr[6];
	271	u8 custData[AR9300_CUSTOMER_DATA_SIZE];
	272
	273	struct ar9300_base_eep_hdr baseEepHeader;
	274
	275	struct ar9300_modal_eep_header modalHeader2G;
b3dd6bc1	276	struct ar9300_BaseExtension_1 base_ext1;
15c9ee7a SB	277	u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
	278	struct ar9300_cal_data_per_freq_op_loop
	279	calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
	280	u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
	281	u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
	282	u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
	283	u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
	284	struct cal_tgt_pow_legacy
	285	calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
	286	struct cal_tgt_pow_legacy
	287	calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
	288	struct cal_tgt_pow_ht
	289	calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
	290	struct cal_tgt_pow_ht
	291	calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
	292	u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
	293	u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
	294	struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
	295	struct ar9300_modal_eep_header modalHeader5G;
b3dd6bc1	296	struct ar9300_BaseExtension_2 base_ext2;
15c9ee7a SB	297	u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
	298	struct ar9300_cal_data_per_freq_op_loop
	299	calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
	300	u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
	301	u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
	302	u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
	303	struct cal_tgt_pow_legacy
	304	calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
	305	struct cal_tgt_pow_ht
	306	calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
	307	struct cal_tgt_pow_ht
	308	calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
	309	u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
	310	u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
	311	struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
	312	} __packed;
c14a85da LR	313
	314	s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
	315	s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
	316
272ceba8	317	u8 ar9003_get_spur_chan_ptr(struct ath_hw ah, bool is_2ghz);
8698bca6 VT	318
	319	unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
	320	struct ath9k_channel *chan);
15c9ee7a	321	#endif