Commit | Line | Data |
---|---|---|
15c9ee7a SB |
1 | /* |
2 | * Copyright (c) 2010 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include "hw.h" | |
18 | #include "ar9003_phy.h" | |
19 | #include "ar9003_eeprom.h" | |
20 | ||
21 | #define COMP_HDR_LEN 4 | |
22 | #define COMP_CKSUM_LEN 2 | |
23 | ||
24 | #define AR_CH0_TOP (0x00016288) | |
52a0e247 | 25 | #define AR_CH0_TOP_XPABIASLVL (0x300) |
15c9ee7a SB |
26 | #define AR_CH0_TOP_XPABIASLVL_S (8) |
27 | ||
28 | #define AR_CH0_THERM (0x00016290) | |
52a0e247 VT |
29 | #define AR_CH0_THERM_XPABIASLVL_MSB 0x3 |
30 | #define AR_CH0_THERM_XPABIASLVL_MSB_S 0 | |
31 | #define AR_CH0_THERM_XPASHORT2GND 0x4 | |
32 | #define AR_CH0_THERM_XPASHORT2GND_S 2 | |
15c9ee7a SB |
33 | |
34 | #define AR_SWITCH_TABLE_COM_ALL (0xffff) | |
35 | #define AR_SWITCH_TABLE_COM_ALL_S (0) | |
36 | ||
37 | #define AR_SWITCH_TABLE_COM2_ALL (0xffffff) | |
38 | #define AR_SWITCH_TABLE_COM2_ALL_S (0) | |
39 | ||
40 | #define AR_SWITCH_TABLE_ALL (0xfff) | |
41 | #define AR_SWITCH_TABLE_ALL_S (0) | |
42 | ||
ffdc4cbe FF |
43 | #define LE16(x) __constant_cpu_to_le16(x) |
44 | #define LE32(x) __constant_cpu_to_le32(x) | |
45 | ||
824b185a LR |
46 | /* Local defines to distinguish between extension and control CTL's */ |
47 | #define EXT_ADDITIVE (0x8000) | |
48 | #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) | |
49 | #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) | |
50 | #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) | |
51 | #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ | |
52 | #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */ | |
53 | #define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */ | |
54 | #define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */ | |
55 | #define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */ | |
56 | ||
57 | #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ | |
58 | #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ | |
59 | ||
e702ba18 FF |
60 | #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6)) |
61 | ||
d0ce2d17 VT |
62 | #define EEPROM_DATA_LEN_9485 1088 |
63 | ||
f4475a6e VT |
64 | static int ar9003_hw_power_interpolate(int32_t x, |
65 | int32_t *px, int32_t *py, u_int16_t np); | |
fe6c7915 | 66 | |
e702ba18 | 67 | |
15c9ee7a SB |
68 | static const struct ar9300_eeprom ar9300_default = { |
69 | .eepromVersion = 2, | |
70 | .templateVersion = 2, | |
71 | .macAddr = {1, 2, 3, 4, 5, 6}, | |
72 | .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
73 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
74 | .baseEepHeader = { | |
ffdc4cbe | 75 | .regDmn = { LE16(0), LE16(0x1f) }, |
15c9ee7a SB |
76 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ |
77 | .opCapFlags = { | |
4ddfcd7d | 78 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
15c9ee7a SB |
79 | .eepMisc = 0, |
80 | }, | |
81 | .rfSilent = 0, | |
82 | .blueToothOptions = 0, | |
83 | .deviceCap = 0, | |
84 | .deviceType = 5, /* takes lower byte in eeprom location */ | |
85 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, | |
86 | .params_for_tuning_caps = {0, 0}, | |
87 | .featureEnable = 0x0c, | |
88 | /* | |
89 | * bit0 - enable tx temp comp - disabled | |
90 | * bit1 - enable tx volt comp - disabled | |
91 | * bit2 - enable fastClock - enabled | |
92 | * bit3 - enable doubling - enabled | |
93 | * bit4 - enable internal regulator - disabled | |
4935250a | 94 | * bit5 - enable pa predistortion - disabled |
15c9ee7a SB |
95 | */ |
96 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ | |
97 | .eepromWriteEnableGpio = 3, | |
98 | .wlanDisableGpio = 0, | |
99 | .wlanLedGpio = 8, | |
100 | .rxBandSelectGpio = 0xff, | |
101 | .txrxgain = 0, | |
102 | .swreg = 0, | |
103 | }, | |
104 | .modalHeader2G = { | |
105 | /* ar9300_modal_eep_header 2g */ | |
106 | /* 4 idle,t1,t2,b(4 bits per setting) */ | |
ffdc4cbe | 107 | .antCtrlCommon = LE32(0x110), |
15c9ee7a | 108 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ |
ffdc4cbe | 109 | .antCtrlCommon2 = LE32(0x22222), |
15c9ee7a SB |
110 | |
111 | /* | |
112 | * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, | |
113 | * rx1, rx12, b (2 bits each) | |
114 | */ | |
ffdc4cbe | 115 | .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, |
15c9ee7a SB |
116 | |
117 | /* | |
118 | * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db | |
119 | * for ar9280 (0xa20c/b20c 5:0) | |
120 | */ | |
121 | .xatten1DB = {0, 0, 0}, | |
122 | ||
123 | /* | |
124 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
125 | * for ar9280 (0xa20c/b20c 16:12 | |
126 | */ | |
127 | .xatten1Margin = {0, 0, 0}, | |
128 | .tempSlope = 36, | |
129 | .voltSlope = 0, | |
130 | ||
131 | /* | |
132 | * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur | |
133 | * channels in usual fbin coding format | |
134 | */ | |
135 | .spurChans = {0, 0, 0, 0, 0}, | |
136 | ||
137 | /* | |
138 | * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check | |
139 | * if the register is per chain | |
140 | */ | |
141 | .noiseFloorThreshCh = {-1, 0, 0}, | |
142 | .ob = {1, 1, 1},/* 3 chain */ | |
143 | .db_stage2 = {1, 1, 1}, /* 3 chain */ | |
144 | .db_stage3 = {0, 0, 0}, | |
145 | .db_stage4 = {0, 0, 0}, | |
146 | .xpaBiasLvl = 0, | |
147 | .txFrameToDataStart = 0x0e, | |
148 | .txFrameToPaOn = 0x0e, | |
149 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
150 | .antennaGain = 0, | |
151 | .switchSettling = 0x2c, | |
152 | .adcDesiredSize = -30, | |
153 | .txEndToXpaOff = 0, | |
154 | .txEndToRxOn = 0x2, | |
155 | .txFrameToXpaOn = 0xe, | |
156 | .thresh62 = 28, | |
3ceb801b SB |
157 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), |
158 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | |
4935250a | 159 | .futureModal = { |
b3dd6bc1 | 160 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
15c9ee7a SB |
161 | }, |
162 | }, | |
b3dd6bc1 SB |
163 | .base_ext1 = { |
164 | .ant_div_control = 0, | |
165 | .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} | |
166 | }, | |
15c9ee7a SB |
167 | .calFreqPier2G = { |
168 | FREQ2FBIN(2412, 1), | |
169 | FREQ2FBIN(2437, 1), | |
170 | FREQ2FBIN(2472, 1), | |
171 | }, | |
172 | /* ar9300_cal_data_per_freq_op_loop 2g */ | |
173 | .calPierData2G = { | |
174 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
175 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
176 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
177 | }, | |
178 | .calTarget_freqbin_Cck = { | |
179 | FREQ2FBIN(2412, 1), | |
180 | FREQ2FBIN(2484, 1), | |
181 | }, | |
182 | .calTarget_freqbin_2G = { | |
183 | FREQ2FBIN(2412, 1), | |
184 | FREQ2FBIN(2437, 1), | |
185 | FREQ2FBIN(2472, 1) | |
186 | }, | |
187 | .calTarget_freqbin_2GHT20 = { | |
188 | FREQ2FBIN(2412, 1), | |
189 | FREQ2FBIN(2437, 1), | |
190 | FREQ2FBIN(2472, 1) | |
191 | }, | |
192 | .calTarget_freqbin_2GHT40 = { | |
193 | FREQ2FBIN(2412, 1), | |
194 | FREQ2FBIN(2437, 1), | |
195 | FREQ2FBIN(2472, 1) | |
196 | }, | |
197 | .calTargetPowerCck = { | |
198 | /* 1L-5L,5S,11L,11S */ | |
199 | { {36, 36, 36, 36} }, | |
200 | { {36, 36, 36, 36} }, | |
201 | }, | |
202 | .calTargetPower2G = { | |
203 | /* 6-24,36,48,54 */ | |
204 | { {32, 32, 28, 24} }, | |
205 | { {32, 32, 28, 24} }, | |
206 | { {32, 32, 28, 24} }, | |
207 | }, | |
208 | .calTargetPower2GHT20 = { | |
209 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, | |
210 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, | |
211 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, | |
212 | }, | |
213 | .calTargetPower2GHT40 = { | |
214 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, | |
215 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, | |
216 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, | |
217 | }, | |
218 | .ctlIndex_2G = { | |
219 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, | |
220 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, | |
221 | }, | |
222 | .ctl_freqbin_2G = { | |
223 | { | |
224 | FREQ2FBIN(2412, 1), | |
225 | FREQ2FBIN(2417, 1), | |
226 | FREQ2FBIN(2457, 1), | |
227 | FREQ2FBIN(2462, 1) | |
228 | }, | |
229 | { | |
230 | FREQ2FBIN(2412, 1), | |
231 | FREQ2FBIN(2417, 1), | |
232 | FREQ2FBIN(2462, 1), | |
233 | 0xFF, | |
234 | }, | |
235 | ||
236 | { | |
237 | FREQ2FBIN(2412, 1), | |
238 | FREQ2FBIN(2417, 1), | |
239 | FREQ2FBIN(2462, 1), | |
240 | 0xFF, | |
241 | }, | |
242 | { | |
243 | FREQ2FBIN(2422, 1), | |
244 | FREQ2FBIN(2427, 1), | |
245 | FREQ2FBIN(2447, 1), | |
246 | FREQ2FBIN(2452, 1) | |
247 | }, | |
248 | ||
249 | { | |
250 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
251 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
252 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
253 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), | |
254 | }, | |
255 | ||
256 | { | |
257 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
258 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
259 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
260 | 0, | |
261 | }, | |
262 | ||
263 | { | |
264 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
265 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
266 | FREQ2FBIN(2472, 1), | |
267 | 0, | |
268 | }, | |
269 | ||
270 | { | |
271 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
272 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
273 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
274 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
275 | }, | |
276 | ||
277 | { | |
278 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
279 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
280 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
281 | }, | |
282 | ||
283 | { | |
284 | /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
285 | /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
286 | /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
287 | 0 | |
288 | }, | |
289 | ||
290 | { | |
291 | /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
292 | /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
293 | /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
294 | 0 | |
295 | }, | |
296 | ||
297 | { | |
298 | /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
299 | /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
300 | /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
b3dd6bc1 | 301 | /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), |
15c9ee7a SB |
302 | } |
303 | }, | |
304 | .ctlPowerData_2G = { | |
fe6c7915 DM |
305 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
306 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
307 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, | |
15c9ee7a | 308 | |
fe6c7915 DM |
309 | { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } }, |
310 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
311 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
15c9ee7a | 312 | |
fe6c7915 DM |
313 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, |
314 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
315 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
15c9ee7a | 316 | |
fe6c7915 DM |
317 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
318 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
319 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
15c9ee7a SB |
320 | }, |
321 | .modalHeader5G = { | |
322 | /* 4 idle,t1,t2,b (4 bits per setting) */ | |
ffdc4cbe | 323 | .antCtrlCommon = LE32(0x110), |
15c9ee7a | 324 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ |
ffdc4cbe | 325 | .antCtrlCommon2 = LE32(0x22222), |
15c9ee7a SB |
326 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ |
327 | .antCtrlChain = { | |
ffdc4cbe | 328 | LE16(0x000), LE16(0x000), LE16(0x000), |
15c9ee7a SB |
329 | }, |
330 | /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ | |
331 | .xatten1DB = {0, 0, 0}, | |
332 | ||
333 | /* | |
334 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
335 | * for merlin (0xa20c/b20c 16:12 | |
336 | */ | |
337 | .xatten1Margin = {0, 0, 0}, | |
338 | .tempSlope = 68, | |
339 | .voltSlope = 0, | |
340 | /* spurChans spur channels in usual fbin coding format */ | |
341 | .spurChans = {0, 0, 0, 0, 0}, | |
342 | /* noiseFloorThreshCh Check if the register is per chain */ | |
343 | .noiseFloorThreshCh = {-1, 0, 0}, | |
344 | .ob = {3, 3, 3}, /* 3 chain */ | |
345 | .db_stage2 = {3, 3, 3}, /* 3 chain */ | |
346 | .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ | |
347 | .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ | |
348 | .xpaBiasLvl = 0, | |
349 | .txFrameToDataStart = 0x0e, | |
350 | .txFrameToPaOn = 0x0e, | |
351 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
352 | .antennaGain = 0, | |
353 | .switchSettling = 0x2d, | |
354 | .adcDesiredSize = -30, | |
355 | .txEndToXpaOff = 0, | |
356 | .txEndToRxOn = 0x2, | |
357 | .txFrameToXpaOn = 0xe, | |
358 | .thresh62 = 28, | |
3ceb801b SB |
359 | .papdRateMaskHt20 = LE32(0x0c80c080), |
360 | .papdRateMaskHt40 = LE32(0x0080c080), | |
15c9ee7a | 361 | .futureModal = { |
b3dd6bc1 | 362 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
15c9ee7a SB |
363 | }, |
364 | }, | |
b3dd6bc1 SB |
365 | .base_ext2 = { |
366 | .tempSlopeLow = 0, | |
367 | .tempSlopeHigh = 0, | |
368 | .xatten1DBLow = {0, 0, 0}, | |
369 | .xatten1MarginLow = {0, 0, 0}, | |
370 | .xatten1DBHigh = {0, 0, 0}, | |
371 | .xatten1MarginHigh = {0, 0, 0} | |
372 | }, | |
15c9ee7a SB |
373 | .calFreqPier5G = { |
374 | FREQ2FBIN(5180, 0), | |
375 | FREQ2FBIN(5220, 0), | |
376 | FREQ2FBIN(5320, 0), | |
377 | FREQ2FBIN(5400, 0), | |
378 | FREQ2FBIN(5500, 0), | |
379 | FREQ2FBIN(5600, 0), | |
380 | FREQ2FBIN(5725, 0), | |
381 | FREQ2FBIN(5825, 0) | |
382 | }, | |
383 | .calPierData5G = { | |
384 | { | |
385 | {0, 0, 0, 0, 0}, | |
386 | {0, 0, 0, 0, 0}, | |
387 | {0, 0, 0, 0, 0}, | |
388 | {0, 0, 0, 0, 0}, | |
389 | {0, 0, 0, 0, 0}, | |
390 | {0, 0, 0, 0, 0}, | |
391 | {0, 0, 0, 0, 0}, | |
392 | {0, 0, 0, 0, 0}, | |
393 | }, | |
394 | { | |
395 | {0, 0, 0, 0, 0}, | |
396 | {0, 0, 0, 0, 0}, | |
397 | {0, 0, 0, 0, 0}, | |
398 | {0, 0, 0, 0, 0}, | |
399 | {0, 0, 0, 0, 0}, | |
400 | {0, 0, 0, 0, 0}, | |
401 | {0, 0, 0, 0, 0}, | |
402 | {0, 0, 0, 0, 0}, | |
403 | }, | |
404 | { | |
405 | {0, 0, 0, 0, 0}, | |
406 | {0, 0, 0, 0, 0}, | |
407 | {0, 0, 0, 0, 0}, | |
408 | {0, 0, 0, 0, 0}, | |
409 | {0, 0, 0, 0, 0}, | |
410 | {0, 0, 0, 0, 0}, | |
411 | {0, 0, 0, 0, 0}, | |
412 | {0, 0, 0, 0, 0}, | |
413 | }, | |
414 | ||
415 | }, | |
416 | .calTarget_freqbin_5G = { | |
417 | FREQ2FBIN(5180, 0), | |
418 | FREQ2FBIN(5220, 0), | |
419 | FREQ2FBIN(5320, 0), | |
420 | FREQ2FBIN(5400, 0), | |
421 | FREQ2FBIN(5500, 0), | |
422 | FREQ2FBIN(5600, 0), | |
423 | FREQ2FBIN(5725, 0), | |
424 | FREQ2FBIN(5825, 0) | |
425 | }, | |
426 | .calTarget_freqbin_5GHT20 = { | |
427 | FREQ2FBIN(5180, 0), | |
428 | FREQ2FBIN(5240, 0), | |
429 | FREQ2FBIN(5320, 0), | |
430 | FREQ2FBIN(5500, 0), | |
431 | FREQ2FBIN(5700, 0), | |
432 | FREQ2FBIN(5745, 0), | |
433 | FREQ2FBIN(5725, 0), | |
434 | FREQ2FBIN(5825, 0) | |
435 | }, | |
436 | .calTarget_freqbin_5GHT40 = { | |
437 | FREQ2FBIN(5180, 0), | |
438 | FREQ2FBIN(5240, 0), | |
439 | FREQ2FBIN(5320, 0), | |
440 | FREQ2FBIN(5500, 0), | |
441 | FREQ2FBIN(5700, 0), | |
442 | FREQ2FBIN(5745, 0), | |
443 | FREQ2FBIN(5725, 0), | |
444 | FREQ2FBIN(5825, 0) | |
445 | }, | |
446 | .calTargetPower5G = { | |
447 | /* 6-24,36,48,54 */ | |
448 | { {20, 20, 20, 10} }, | |
449 | { {20, 20, 20, 10} }, | |
450 | { {20, 20, 20, 10} }, | |
451 | { {20, 20, 20, 10} }, | |
452 | { {20, 20, 20, 10} }, | |
453 | { {20, 20, 20, 10} }, | |
454 | { {20, 20, 20, 10} }, | |
455 | { {20, 20, 20, 10} }, | |
456 | }, | |
457 | .calTargetPower5GHT20 = { | |
458 | /* | |
459 | * 0_8_16,1-3_9-11_17-19, | |
460 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
461 | */ | |
462 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
463 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
464 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
465 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
466 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
467 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
468 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
469 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
470 | }, | |
471 | .calTargetPower5GHT40 = { | |
472 | /* | |
473 | * 0_8_16,1-3_9-11_17-19, | |
474 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
475 | */ | |
476 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
477 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
478 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
479 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
480 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
481 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
482 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
483 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
484 | }, | |
485 | .ctlIndex_5G = { | |
486 | 0x10, 0x16, 0x18, 0x40, 0x46, | |
487 | 0x48, 0x30, 0x36, 0x38 | |
488 | }, | |
489 | .ctl_freqbin_5G = { | |
490 | { | |
491 | /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
492 | /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
493 | /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
494 | /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
495 | /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), | |
496 | /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
497 | /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
498 | /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
499 | }, | |
500 | { | |
501 | /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
502 | /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
503 | /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
504 | /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
505 | /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), | |
506 | /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
507 | /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
508 | /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
509 | }, | |
510 | ||
511 | { | |
512 | /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
513 | /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
514 | /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
515 | /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), | |
516 | /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), | |
517 | /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), | |
518 | /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), | |
519 | /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) | |
520 | }, | |
521 | ||
522 | { | |
523 | /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
524 | /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
525 | /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), | |
526 | /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), | |
527 | /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
528 | /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
529 | /* Data[3].ctlEdges[6].bChannel */ 0xFF, | |
530 | /* Data[3].ctlEdges[7].bChannel */ 0xFF, | |
531 | }, | |
532 | ||
533 | { | |
534 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
535 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
536 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), | |
537 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), | |
538 | /* Data[4].ctlEdges[4].bChannel */ 0xFF, | |
539 | /* Data[4].ctlEdges[5].bChannel */ 0xFF, | |
540 | /* Data[4].ctlEdges[6].bChannel */ 0xFF, | |
541 | /* Data[4].ctlEdges[7].bChannel */ 0xFF, | |
542 | }, | |
543 | ||
544 | { | |
545 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
546 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), | |
547 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), | |
548 | /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
549 | /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), | |
550 | /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
551 | /* Data[5].ctlEdges[6].bChannel */ 0xFF, | |
552 | /* Data[5].ctlEdges[7].bChannel */ 0xFF | |
553 | }, | |
554 | ||
555 | { | |
556 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
557 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
558 | /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), | |
559 | /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), | |
560 | /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
561 | /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), | |
562 | /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), | |
563 | /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) | |
564 | }, | |
565 | ||
566 | { | |
567 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
568 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
569 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), | |
570 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
571 | /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), | |
572 | /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
573 | /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
574 | /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
575 | }, | |
576 | ||
577 | { | |
578 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
579 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
580 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
581 | /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
582 | /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), | |
583 | /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
584 | /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), | |
585 | /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) | |
586 | } | |
587 | }, | |
588 | .ctlPowerData_5G = { | |
589 | { | |
590 | { | |
fe6c7915 DM |
591 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
592 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
15c9ee7a SB |
593 | } |
594 | }, | |
595 | { | |
596 | { | |
fe6c7915 DM |
597 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
598 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
15c9ee7a SB |
599 | } |
600 | }, | |
601 | { | |
602 | { | |
fe6c7915 DM |
603 | CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
604 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
15c9ee7a SB |
605 | } |
606 | }, | |
607 | { | |
608 | { | |
fe6c7915 DM |
609 | CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
610 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
15c9ee7a SB |
611 | } |
612 | }, | |
613 | { | |
614 | { | |
fe6c7915 DM |
615 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
616 | CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
15c9ee7a SB |
617 | } |
618 | }, | |
619 | { | |
620 | { | |
fe6c7915 DM |
621 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
622 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
15c9ee7a SB |
623 | } |
624 | }, | |
625 | { | |
626 | { | |
fe6c7915 DM |
627 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
628 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
15c9ee7a SB |
629 | } |
630 | }, | |
631 | { | |
632 | { | |
fe6c7915 DM |
633 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
634 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
15c9ee7a SB |
635 | } |
636 | }, | |
637 | { | |
638 | { | |
fe6c7915 DM |
639 | CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), |
640 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), | |
15c9ee7a SB |
641 | } |
642 | }, | |
643 | } | |
644 | }; | |
645 | ||
30923549 SB |
646 | static const struct ar9300_eeprom ar9300_x113 = { |
647 | .eepromVersion = 2, | |
648 | .templateVersion = 6, | |
649 | .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, | |
650 | .custData = {"x113-023-f0000"}, | |
651 | .baseEepHeader = { | |
652 | .regDmn = { LE16(0), LE16(0x1f) }, | |
653 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ | |
654 | .opCapFlags = { | |
4ddfcd7d | 655 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
30923549 SB |
656 | .eepMisc = 0, |
657 | }, | |
658 | .rfSilent = 0, | |
659 | .blueToothOptions = 0, | |
660 | .deviceCap = 0, | |
661 | .deviceType = 5, /* takes lower byte in eeprom location */ | |
662 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, | |
663 | .params_for_tuning_caps = {0, 0}, | |
664 | .featureEnable = 0x0d, | |
665 | /* | |
666 | * bit0 - enable tx temp comp - disabled | |
667 | * bit1 - enable tx volt comp - disabled | |
668 | * bit2 - enable fastClock - enabled | |
669 | * bit3 - enable doubling - enabled | |
670 | * bit4 - enable internal regulator - disabled | |
671 | * bit5 - enable pa predistortion - disabled | |
672 | */ | |
673 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ | |
674 | .eepromWriteEnableGpio = 6, | |
675 | .wlanDisableGpio = 0, | |
676 | .wlanLedGpio = 8, | |
677 | .rxBandSelectGpio = 0xff, | |
678 | .txrxgain = 0x21, | |
679 | .swreg = 0, | |
680 | }, | |
681 | .modalHeader2G = { | |
682 | /* ar9300_modal_eep_header 2g */ | |
683 | /* 4 idle,t1,t2,b(4 bits per setting) */ | |
684 | .antCtrlCommon = LE32(0x110), | |
685 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ | |
686 | .antCtrlCommon2 = LE32(0x44444), | |
687 | ||
688 | /* | |
689 | * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, | |
690 | * rx1, rx12, b (2 bits each) | |
691 | */ | |
692 | .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, | |
693 | ||
694 | /* | |
695 | * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db | |
696 | * for ar9280 (0xa20c/b20c 5:0) | |
697 | */ | |
698 | .xatten1DB = {0, 0, 0}, | |
699 | ||
700 | /* | |
701 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
702 | * for ar9280 (0xa20c/b20c 16:12 | |
703 | */ | |
704 | .xatten1Margin = {0, 0, 0}, | |
705 | .tempSlope = 25, | |
706 | .voltSlope = 0, | |
707 | ||
708 | /* | |
709 | * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur | |
710 | * channels in usual fbin coding format | |
711 | */ | |
712 | .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, | |
713 | ||
714 | /* | |
715 | * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check | |
716 | * if the register is per chain | |
717 | */ | |
718 | .noiseFloorThreshCh = {-1, 0, 0}, | |
719 | .ob = {1, 1, 1},/* 3 chain */ | |
720 | .db_stage2 = {1, 1, 1}, /* 3 chain */ | |
721 | .db_stage3 = {0, 0, 0}, | |
722 | .db_stage4 = {0, 0, 0}, | |
723 | .xpaBiasLvl = 0, | |
724 | .txFrameToDataStart = 0x0e, | |
725 | .txFrameToPaOn = 0x0e, | |
726 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
727 | .antennaGain = 0, | |
728 | .switchSettling = 0x2c, | |
729 | .adcDesiredSize = -30, | |
730 | .txEndToXpaOff = 0, | |
731 | .txEndToRxOn = 0x2, | |
732 | .txFrameToXpaOn = 0xe, | |
733 | .thresh62 = 28, | |
734 | .papdRateMaskHt20 = LE32(0x0c80c080), | |
735 | .papdRateMaskHt40 = LE32(0x0080c080), | |
736 | .futureModal = { | |
737 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
738 | }, | |
739 | }, | |
740 | .base_ext1 = { | |
741 | .ant_div_control = 0, | |
742 | .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} | |
743 | }, | |
744 | .calFreqPier2G = { | |
745 | FREQ2FBIN(2412, 1), | |
746 | FREQ2FBIN(2437, 1), | |
747 | FREQ2FBIN(2472, 1), | |
748 | }, | |
749 | /* ar9300_cal_data_per_freq_op_loop 2g */ | |
750 | .calPierData2G = { | |
751 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
752 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
753 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
754 | }, | |
755 | .calTarget_freqbin_Cck = { | |
756 | FREQ2FBIN(2412, 1), | |
757 | FREQ2FBIN(2472, 1), | |
758 | }, | |
759 | .calTarget_freqbin_2G = { | |
760 | FREQ2FBIN(2412, 1), | |
761 | FREQ2FBIN(2437, 1), | |
762 | FREQ2FBIN(2472, 1) | |
763 | }, | |
764 | .calTarget_freqbin_2GHT20 = { | |
765 | FREQ2FBIN(2412, 1), | |
766 | FREQ2FBIN(2437, 1), | |
767 | FREQ2FBIN(2472, 1) | |
768 | }, | |
769 | .calTarget_freqbin_2GHT40 = { | |
770 | FREQ2FBIN(2412, 1), | |
771 | FREQ2FBIN(2437, 1), | |
772 | FREQ2FBIN(2472, 1) | |
773 | }, | |
774 | .calTargetPowerCck = { | |
775 | /* 1L-5L,5S,11L,11S */ | |
776 | { {34, 34, 34, 34} }, | |
777 | { {34, 34, 34, 34} }, | |
778 | }, | |
779 | .calTargetPower2G = { | |
780 | /* 6-24,36,48,54 */ | |
781 | { {34, 34, 32, 32} }, | |
782 | { {34, 34, 32, 32} }, | |
783 | { {34, 34, 32, 32} }, | |
784 | }, | |
785 | .calTargetPower2GHT20 = { | |
786 | { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, | |
787 | { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, | |
788 | { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, | |
789 | }, | |
790 | .calTargetPower2GHT40 = { | |
791 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, | |
792 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, | |
793 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, | |
794 | }, | |
795 | .ctlIndex_2G = { | |
796 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, | |
797 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, | |
798 | }, | |
799 | .ctl_freqbin_2G = { | |
800 | { | |
801 | FREQ2FBIN(2412, 1), | |
802 | FREQ2FBIN(2417, 1), | |
803 | FREQ2FBIN(2457, 1), | |
804 | FREQ2FBIN(2462, 1) | |
805 | }, | |
806 | { | |
807 | FREQ2FBIN(2412, 1), | |
808 | FREQ2FBIN(2417, 1), | |
809 | FREQ2FBIN(2462, 1), | |
810 | 0xFF, | |
811 | }, | |
812 | ||
813 | { | |
814 | FREQ2FBIN(2412, 1), | |
815 | FREQ2FBIN(2417, 1), | |
816 | FREQ2FBIN(2462, 1), | |
817 | 0xFF, | |
818 | }, | |
819 | { | |
820 | FREQ2FBIN(2422, 1), | |
821 | FREQ2FBIN(2427, 1), | |
822 | FREQ2FBIN(2447, 1), | |
823 | FREQ2FBIN(2452, 1) | |
824 | }, | |
825 | ||
826 | { | |
827 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
828 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
829 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
830 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), | |
831 | }, | |
832 | ||
833 | { | |
834 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
835 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
836 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
837 | 0, | |
838 | }, | |
839 | ||
840 | { | |
841 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
842 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
843 | FREQ2FBIN(2472, 1), | |
844 | 0, | |
845 | }, | |
846 | ||
847 | { | |
848 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
849 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
850 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
851 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
852 | }, | |
853 | ||
854 | { | |
855 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
856 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
857 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
858 | }, | |
859 | ||
860 | { | |
861 | /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
862 | /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
863 | /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
864 | 0 | |
865 | }, | |
866 | ||
867 | { | |
868 | /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
869 | /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
870 | /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
871 | 0 | |
872 | }, | |
873 | ||
874 | { | |
875 | /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
876 | /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
877 | /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
878 | /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
879 | } | |
880 | }, | |
881 | .ctlPowerData_2G = { | |
fe6c7915 DM |
882 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
883 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
884 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, | |
30923549 | 885 | |
fe6c7915 DM |
886 | { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } }, |
887 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
888 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 889 | |
fe6c7915 DM |
890 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, |
891 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
892 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 893 | |
fe6c7915 DM |
894 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
895 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
896 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
30923549 SB |
897 | }, |
898 | .modalHeader5G = { | |
899 | /* 4 idle,t1,t2,b (4 bits per setting) */ | |
900 | .antCtrlCommon = LE32(0x220), | |
901 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ | |
902 | .antCtrlCommon2 = LE32(0x11111), | |
903 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ | |
904 | .antCtrlChain = { | |
905 | LE16(0x150), LE16(0x150), LE16(0x150), | |
906 | }, | |
907 | /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ | |
908 | .xatten1DB = {0, 0, 0}, | |
909 | ||
910 | /* | |
911 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
912 | * for merlin (0xa20c/b20c 16:12 | |
913 | */ | |
914 | .xatten1Margin = {0, 0, 0}, | |
915 | .tempSlope = 68, | |
916 | .voltSlope = 0, | |
917 | /* spurChans spur channels in usual fbin coding format */ | |
918 | .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0}, | |
919 | /* noiseFloorThreshCh Check if the register is per chain */ | |
920 | .noiseFloorThreshCh = {-1, 0, 0}, | |
921 | .ob = {3, 3, 3}, /* 3 chain */ | |
922 | .db_stage2 = {3, 3, 3}, /* 3 chain */ | |
923 | .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ | |
924 | .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ | |
925 | .xpaBiasLvl = 0, | |
926 | .txFrameToDataStart = 0x0e, | |
927 | .txFrameToPaOn = 0x0e, | |
928 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
929 | .antennaGain = 0, | |
930 | .switchSettling = 0x2d, | |
931 | .adcDesiredSize = -30, | |
932 | .txEndToXpaOff = 0, | |
933 | .txEndToRxOn = 0x2, | |
934 | .txFrameToXpaOn = 0xe, | |
935 | .thresh62 = 28, | |
936 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | |
937 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | |
938 | .futureModal = { | |
939 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
940 | }, | |
941 | }, | |
942 | .base_ext2 = { | |
943 | .tempSlopeLow = 72, | |
944 | .tempSlopeHigh = 105, | |
945 | .xatten1DBLow = {0, 0, 0}, | |
946 | .xatten1MarginLow = {0, 0, 0}, | |
947 | .xatten1DBHigh = {0, 0, 0}, | |
948 | .xatten1MarginHigh = {0, 0, 0} | |
949 | }, | |
950 | .calFreqPier5G = { | |
951 | FREQ2FBIN(5180, 0), | |
952 | FREQ2FBIN(5240, 0), | |
953 | FREQ2FBIN(5320, 0), | |
954 | FREQ2FBIN(5400, 0), | |
955 | FREQ2FBIN(5500, 0), | |
956 | FREQ2FBIN(5600, 0), | |
957 | FREQ2FBIN(5745, 0), | |
958 | FREQ2FBIN(5785, 0) | |
959 | }, | |
960 | .calPierData5G = { | |
961 | { | |
962 | {0, 0, 0, 0, 0}, | |
963 | {0, 0, 0, 0, 0}, | |
964 | {0, 0, 0, 0, 0}, | |
965 | {0, 0, 0, 0, 0}, | |
966 | {0, 0, 0, 0, 0}, | |
967 | {0, 0, 0, 0, 0}, | |
968 | {0, 0, 0, 0, 0}, | |
969 | {0, 0, 0, 0, 0}, | |
970 | }, | |
971 | { | |
972 | {0, 0, 0, 0, 0}, | |
973 | {0, 0, 0, 0, 0}, | |
974 | {0, 0, 0, 0, 0}, | |
975 | {0, 0, 0, 0, 0}, | |
976 | {0, 0, 0, 0, 0}, | |
977 | {0, 0, 0, 0, 0}, | |
978 | {0, 0, 0, 0, 0}, | |
979 | {0, 0, 0, 0, 0}, | |
980 | }, | |
981 | { | |
982 | {0, 0, 0, 0, 0}, | |
983 | {0, 0, 0, 0, 0}, | |
984 | {0, 0, 0, 0, 0}, | |
985 | {0, 0, 0, 0, 0}, | |
986 | {0, 0, 0, 0, 0}, | |
987 | {0, 0, 0, 0, 0}, | |
988 | {0, 0, 0, 0, 0}, | |
989 | {0, 0, 0, 0, 0}, | |
990 | }, | |
991 | ||
992 | }, | |
993 | .calTarget_freqbin_5G = { | |
994 | FREQ2FBIN(5180, 0), | |
995 | FREQ2FBIN(5220, 0), | |
996 | FREQ2FBIN(5320, 0), | |
997 | FREQ2FBIN(5400, 0), | |
998 | FREQ2FBIN(5500, 0), | |
999 | FREQ2FBIN(5600, 0), | |
1000 | FREQ2FBIN(5745, 0), | |
1001 | FREQ2FBIN(5785, 0) | |
1002 | }, | |
1003 | .calTarget_freqbin_5GHT20 = { | |
1004 | FREQ2FBIN(5180, 0), | |
1005 | FREQ2FBIN(5240, 0), | |
1006 | FREQ2FBIN(5320, 0), | |
1007 | FREQ2FBIN(5400, 0), | |
1008 | FREQ2FBIN(5500, 0), | |
1009 | FREQ2FBIN(5700, 0), | |
1010 | FREQ2FBIN(5745, 0), | |
1011 | FREQ2FBIN(5825, 0) | |
1012 | }, | |
1013 | .calTarget_freqbin_5GHT40 = { | |
1014 | FREQ2FBIN(5190, 0), | |
1015 | FREQ2FBIN(5230, 0), | |
1016 | FREQ2FBIN(5320, 0), | |
1017 | FREQ2FBIN(5410, 0), | |
1018 | FREQ2FBIN(5510, 0), | |
1019 | FREQ2FBIN(5670, 0), | |
1020 | FREQ2FBIN(5755, 0), | |
1021 | FREQ2FBIN(5825, 0) | |
1022 | }, | |
1023 | .calTargetPower5G = { | |
1024 | /* 6-24,36,48,54 */ | |
1025 | { {42, 40, 40, 34} }, | |
1026 | { {42, 40, 40, 34} }, | |
1027 | { {42, 40, 40, 34} }, | |
1028 | { {42, 40, 40, 34} }, | |
1029 | { {42, 40, 40, 34} }, | |
1030 | { {42, 40, 40, 34} }, | |
1031 | { {42, 40, 40, 34} }, | |
1032 | { {42, 40, 40, 34} }, | |
1033 | }, | |
1034 | .calTargetPower5GHT20 = { | |
1035 | /* | |
1036 | * 0_8_16,1-3_9-11_17-19, | |
1037 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
1038 | */ | |
1039 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, | |
1040 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, | |
1041 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, | |
1042 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, | |
1043 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, | |
1044 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, | |
1045 | { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} }, | |
1046 | { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} }, | |
1047 | }, | |
1048 | .calTargetPower5GHT40 = { | |
1049 | /* | |
1050 | * 0_8_16,1-3_9-11_17-19, | |
1051 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
1052 | */ | |
1053 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, | |
1054 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, | |
1055 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, | |
1056 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, | |
1057 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, | |
1058 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, | |
1059 | { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} }, | |
1060 | { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} }, | |
1061 | }, | |
1062 | .ctlIndex_5G = { | |
1063 | 0x10, 0x16, 0x18, 0x40, 0x46, | |
1064 | 0x48, 0x30, 0x36, 0x38 | |
1065 | }, | |
1066 | .ctl_freqbin_5G = { | |
1067 | { | |
1068 | /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1069 | /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1070 | /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
1071 | /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
1072 | /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), | |
1073 | /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1074 | /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
1075 | /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
1076 | }, | |
1077 | { | |
1078 | /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1079 | /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1080 | /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
1081 | /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
1082 | /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), | |
1083 | /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1084 | /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
1085 | /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
1086 | }, | |
1087 | ||
1088 | { | |
1089 | /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
1090 | /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
1091 | /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
1092 | /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), | |
1093 | /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), | |
1094 | /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), | |
1095 | /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), | |
1096 | /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) | |
1097 | }, | |
1098 | ||
1099 | { | |
1100 | /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1101 | /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
1102 | /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), | |
1103 | /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), | |
1104 | /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
1105 | /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1106 | /* Data[3].ctlEdges[6].bChannel */ 0xFF, | |
1107 | /* Data[3].ctlEdges[7].bChannel */ 0xFF, | |
1108 | }, | |
1109 | ||
1110 | { | |
1111 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1112 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1113 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), | |
1114 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), | |
1115 | /* Data[4].ctlEdges[4].bChannel */ 0xFF, | |
1116 | /* Data[4].ctlEdges[5].bChannel */ 0xFF, | |
1117 | /* Data[4].ctlEdges[6].bChannel */ 0xFF, | |
1118 | /* Data[4].ctlEdges[7].bChannel */ 0xFF, | |
1119 | }, | |
1120 | ||
1121 | { | |
1122 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
1123 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), | |
1124 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), | |
1125 | /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
1126 | /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), | |
1127 | /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
1128 | /* Data[5].ctlEdges[6].bChannel */ 0xFF, | |
1129 | /* Data[5].ctlEdges[7].bChannel */ 0xFF | |
1130 | }, | |
1131 | ||
1132 | { | |
1133 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1134 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
1135 | /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), | |
1136 | /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), | |
1137 | /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
1138 | /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), | |
1139 | /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), | |
1140 | /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) | |
1141 | }, | |
1142 | ||
1143 | { | |
1144 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1145 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1146 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), | |
1147 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
1148 | /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), | |
1149 | /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1150 | /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
1151 | /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
1152 | }, | |
1153 | ||
1154 | { | |
1155 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
1156 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
1157 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
1158 | /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
1159 | /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), | |
1160 | /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
1161 | /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), | |
1162 | /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) | |
1163 | } | |
1164 | }, | |
1165 | .ctlPowerData_5G = { | |
1166 | { | |
1167 | { | |
fe6c7915 DM |
1168 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1169 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
1170 | } |
1171 | }, | |
1172 | { | |
1173 | { | |
fe6c7915 DM |
1174 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1175 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
1176 | } |
1177 | }, | |
1178 | { | |
1179 | { | |
fe6c7915 DM |
1180 | CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
1181 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
1182 | } |
1183 | }, | |
1184 | { | |
1185 | { | |
fe6c7915 DM |
1186 | CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
1187 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
1188 | } |
1189 | }, | |
1190 | { | |
1191 | { | |
fe6c7915 DM |
1192 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
1193 | CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
1194 | } |
1195 | }, | |
1196 | { | |
1197 | { | |
fe6c7915 DM |
1198 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1199 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
1200 | } |
1201 | }, | |
1202 | { | |
1203 | { | |
fe6c7915 DM |
1204 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1205 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
1206 | } |
1207 | }, | |
1208 | { | |
1209 | { | |
fe6c7915 DM |
1210 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
1211 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
1212 | } |
1213 | }, | |
1214 | { | |
1215 | { | |
fe6c7915 DM |
1216 | CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), |
1217 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), | |
30923549 SB |
1218 | } |
1219 | }, | |
1220 | } | |
1221 | }; | |
1222 | ||
1223 | ||
1224 | static const struct ar9300_eeprom ar9300_h112 = { | |
1225 | .eepromVersion = 2, | |
1226 | .templateVersion = 3, | |
1227 | .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, | |
1228 | .custData = {"h112-241-f0000"}, | |
1229 | .baseEepHeader = { | |
1230 | .regDmn = { LE16(0), LE16(0x1f) }, | |
1231 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ | |
1232 | .opCapFlags = { | |
4ddfcd7d | 1233 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
30923549 SB |
1234 | .eepMisc = 0, |
1235 | }, | |
1236 | .rfSilent = 0, | |
1237 | .blueToothOptions = 0, | |
1238 | .deviceCap = 0, | |
1239 | .deviceType = 5, /* takes lower byte in eeprom location */ | |
1240 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, | |
1241 | .params_for_tuning_caps = {0, 0}, | |
1242 | .featureEnable = 0x0d, | |
1243 | /* | |
1244 | * bit0 - enable tx temp comp - disabled | |
1245 | * bit1 - enable tx volt comp - disabled | |
1246 | * bit2 - enable fastClock - enabled | |
1247 | * bit3 - enable doubling - enabled | |
1248 | * bit4 - enable internal regulator - disabled | |
1249 | * bit5 - enable pa predistortion - disabled | |
1250 | */ | |
1251 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ | |
1252 | .eepromWriteEnableGpio = 6, | |
1253 | .wlanDisableGpio = 0, | |
1254 | .wlanLedGpio = 8, | |
1255 | .rxBandSelectGpio = 0xff, | |
1256 | .txrxgain = 0x10, | |
1257 | .swreg = 0, | |
1258 | }, | |
1259 | .modalHeader2G = { | |
1260 | /* ar9300_modal_eep_header 2g */ | |
1261 | /* 4 idle,t1,t2,b(4 bits per setting) */ | |
1262 | .antCtrlCommon = LE32(0x110), | |
1263 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ | |
1264 | .antCtrlCommon2 = LE32(0x44444), | |
1265 | ||
1266 | /* | |
1267 | * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, | |
1268 | * rx1, rx12, b (2 bits each) | |
1269 | */ | |
1270 | .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, | |
1271 | ||
1272 | /* | |
1273 | * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db | |
1274 | * for ar9280 (0xa20c/b20c 5:0) | |
1275 | */ | |
1276 | .xatten1DB = {0, 0, 0}, | |
1277 | ||
1278 | /* | |
1279 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
1280 | * for ar9280 (0xa20c/b20c 16:12 | |
1281 | */ | |
1282 | .xatten1Margin = {0, 0, 0}, | |
1283 | .tempSlope = 25, | |
1284 | .voltSlope = 0, | |
1285 | ||
1286 | /* | |
1287 | * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur | |
1288 | * channels in usual fbin coding format | |
1289 | */ | |
1290 | .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, | |
1291 | ||
1292 | /* | |
1293 | * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check | |
1294 | * if the register is per chain | |
1295 | */ | |
1296 | .noiseFloorThreshCh = {-1, 0, 0}, | |
1297 | .ob = {1, 1, 1},/* 3 chain */ | |
1298 | .db_stage2 = {1, 1, 1}, /* 3 chain */ | |
1299 | .db_stage3 = {0, 0, 0}, | |
1300 | .db_stage4 = {0, 0, 0}, | |
1301 | .xpaBiasLvl = 0, | |
1302 | .txFrameToDataStart = 0x0e, | |
1303 | .txFrameToPaOn = 0x0e, | |
1304 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
1305 | .antennaGain = 0, | |
1306 | .switchSettling = 0x2c, | |
1307 | .adcDesiredSize = -30, | |
1308 | .txEndToXpaOff = 0, | |
1309 | .txEndToRxOn = 0x2, | |
1310 | .txFrameToXpaOn = 0xe, | |
1311 | .thresh62 = 28, | |
1312 | .papdRateMaskHt20 = LE32(0x80c080), | |
1313 | .papdRateMaskHt40 = LE32(0x80c080), | |
1314 | .futureModal = { | |
1315 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1316 | }, | |
1317 | }, | |
1318 | .base_ext1 = { | |
1319 | .ant_div_control = 0, | |
1320 | .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} | |
1321 | }, | |
1322 | .calFreqPier2G = { | |
1323 | FREQ2FBIN(2412, 1), | |
1324 | FREQ2FBIN(2437, 1), | |
1325 | FREQ2FBIN(2472, 1), | |
1326 | }, | |
1327 | /* ar9300_cal_data_per_freq_op_loop 2g */ | |
1328 | .calPierData2G = { | |
1329 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
1330 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
1331 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
1332 | }, | |
1333 | .calTarget_freqbin_Cck = { | |
1334 | FREQ2FBIN(2412, 1), | |
1335 | FREQ2FBIN(2484, 1), | |
1336 | }, | |
1337 | .calTarget_freqbin_2G = { | |
1338 | FREQ2FBIN(2412, 1), | |
1339 | FREQ2FBIN(2437, 1), | |
1340 | FREQ2FBIN(2472, 1) | |
1341 | }, | |
1342 | .calTarget_freqbin_2GHT20 = { | |
1343 | FREQ2FBIN(2412, 1), | |
1344 | FREQ2FBIN(2437, 1), | |
1345 | FREQ2FBIN(2472, 1) | |
1346 | }, | |
1347 | .calTarget_freqbin_2GHT40 = { | |
1348 | FREQ2FBIN(2412, 1), | |
1349 | FREQ2FBIN(2437, 1), | |
1350 | FREQ2FBIN(2472, 1) | |
1351 | }, | |
1352 | .calTargetPowerCck = { | |
1353 | /* 1L-5L,5S,11L,11S */ | |
1354 | { {34, 34, 34, 34} }, | |
1355 | { {34, 34, 34, 34} }, | |
1356 | }, | |
1357 | .calTargetPower2G = { | |
1358 | /* 6-24,36,48,54 */ | |
1359 | { {34, 34, 32, 32} }, | |
1360 | { {34, 34, 32, 32} }, | |
1361 | { {34, 34, 32, 32} }, | |
1362 | }, | |
1363 | .calTargetPower2GHT20 = { | |
1364 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, | |
1365 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, | |
1366 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, | |
1367 | }, | |
1368 | .calTargetPower2GHT40 = { | |
1369 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, | |
1370 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, | |
1371 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, | |
1372 | }, | |
1373 | .ctlIndex_2G = { | |
1374 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, | |
1375 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, | |
1376 | }, | |
1377 | .ctl_freqbin_2G = { | |
1378 | { | |
1379 | FREQ2FBIN(2412, 1), | |
1380 | FREQ2FBIN(2417, 1), | |
1381 | FREQ2FBIN(2457, 1), | |
1382 | FREQ2FBIN(2462, 1) | |
1383 | }, | |
1384 | { | |
1385 | FREQ2FBIN(2412, 1), | |
1386 | FREQ2FBIN(2417, 1), | |
1387 | FREQ2FBIN(2462, 1), | |
1388 | 0xFF, | |
1389 | }, | |
1390 | ||
1391 | { | |
1392 | FREQ2FBIN(2412, 1), | |
1393 | FREQ2FBIN(2417, 1), | |
1394 | FREQ2FBIN(2462, 1), | |
1395 | 0xFF, | |
1396 | }, | |
1397 | { | |
1398 | FREQ2FBIN(2422, 1), | |
1399 | FREQ2FBIN(2427, 1), | |
1400 | FREQ2FBIN(2447, 1), | |
1401 | FREQ2FBIN(2452, 1) | |
1402 | }, | |
1403 | ||
1404 | { | |
1405 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
1406 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
1407 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
1408 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), | |
1409 | }, | |
1410 | ||
1411 | { | |
1412 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
1413 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
1414 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
1415 | 0, | |
1416 | }, | |
1417 | ||
1418 | { | |
1419 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
1420 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
1421 | FREQ2FBIN(2472, 1), | |
1422 | 0, | |
1423 | }, | |
1424 | ||
1425 | { | |
1426 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
1427 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
1428 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
1429 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
1430 | }, | |
1431 | ||
1432 | { | |
1433 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
1434 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
1435 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
1436 | }, | |
1437 | ||
1438 | { | |
1439 | /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
1440 | /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
1441 | /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
1442 | 0 | |
1443 | }, | |
1444 | ||
1445 | { | |
1446 | /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
1447 | /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
1448 | /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
1449 | 0 | |
1450 | }, | |
1451 | ||
1452 | { | |
1453 | /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
1454 | /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
1455 | /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
1456 | /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
1457 | } | |
1458 | }, | |
1459 | .ctlPowerData_2G = { | |
fe6c7915 DM |
1460 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
1461 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
1462 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, | |
30923549 | 1463 | |
fe6c7915 DM |
1464 | { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } }, |
1465 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
1466 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 1467 | |
fe6c7915 DM |
1468 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, |
1469 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
1470 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 1471 | |
fe6c7915 DM |
1472 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
1473 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
1474 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
30923549 SB |
1475 | }, |
1476 | .modalHeader5G = { | |
1477 | /* 4 idle,t1,t2,b (4 bits per setting) */ | |
1478 | .antCtrlCommon = LE32(0x220), | |
1479 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ | |
1480 | .antCtrlCommon2 = LE32(0x44444), | |
1481 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ | |
1482 | .antCtrlChain = { | |
1483 | LE16(0x150), LE16(0x150), LE16(0x150), | |
1484 | }, | |
1485 | /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ | |
1486 | .xatten1DB = {0, 0, 0}, | |
1487 | ||
1488 | /* | |
1489 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
1490 | * for merlin (0xa20c/b20c 16:12 | |
1491 | */ | |
1492 | .xatten1Margin = {0, 0, 0}, | |
1493 | .tempSlope = 45, | |
1494 | .voltSlope = 0, | |
1495 | /* spurChans spur channels in usual fbin coding format */ | |
1496 | .spurChans = {0, 0, 0, 0, 0}, | |
1497 | /* noiseFloorThreshCh Check if the register is per chain */ | |
1498 | .noiseFloorThreshCh = {-1, 0, 0}, | |
1499 | .ob = {3, 3, 3}, /* 3 chain */ | |
1500 | .db_stage2 = {3, 3, 3}, /* 3 chain */ | |
1501 | .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ | |
1502 | .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ | |
1503 | .xpaBiasLvl = 0, | |
1504 | .txFrameToDataStart = 0x0e, | |
1505 | .txFrameToPaOn = 0x0e, | |
1506 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
1507 | .antennaGain = 0, | |
1508 | .switchSettling = 0x2d, | |
1509 | .adcDesiredSize = -30, | |
1510 | .txEndToXpaOff = 0, | |
1511 | .txEndToRxOn = 0x2, | |
1512 | .txFrameToXpaOn = 0xe, | |
1513 | .thresh62 = 28, | |
1514 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | |
1515 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | |
1516 | .futureModal = { | |
1517 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1518 | }, | |
1519 | }, | |
1520 | .base_ext2 = { | |
1521 | .tempSlopeLow = 40, | |
1522 | .tempSlopeHigh = 50, | |
1523 | .xatten1DBLow = {0, 0, 0}, | |
1524 | .xatten1MarginLow = {0, 0, 0}, | |
1525 | .xatten1DBHigh = {0, 0, 0}, | |
1526 | .xatten1MarginHigh = {0, 0, 0} | |
1527 | }, | |
1528 | .calFreqPier5G = { | |
1529 | FREQ2FBIN(5180, 0), | |
1530 | FREQ2FBIN(5220, 0), | |
1531 | FREQ2FBIN(5320, 0), | |
1532 | FREQ2FBIN(5400, 0), | |
1533 | FREQ2FBIN(5500, 0), | |
1534 | FREQ2FBIN(5600, 0), | |
1535 | FREQ2FBIN(5700, 0), | |
1536 | FREQ2FBIN(5825, 0) | |
1537 | }, | |
1538 | .calPierData5G = { | |
1539 | { | |
1540 | {0, 0, 0, 0, 0}, | |
1541 | {0, 0, 0, 0, 0}, | |
1542 | {0, 0, 0, 0, 0}, | |
1543 | {0, 0, 0, 0, 0}, | |
1544 | {0, 0, 0, 0, 0}, | |
1545 | {0, 0, 0, 0, 0}, | |
1546 | {0, 0, 0, 0, 0}, | |
1547 | {0, 0, 0, 0, 0}, | |
1548 | }, | |
1549 | { | |
1550 | {0, 0, 0, 0, 0}, | |
1551 | {0, 0, 0, 0, 0}, | |
1552 | {0, 0, 0, 0, 0}, | |
1553 | {0, 0, 0, 0, 0}, | |
1554 | {0, 0, 0, 0, 0}, | |
1555 | {0, 0, 0, 0, 0}, | |
1556 | {0, 0, 0, 0, 0}, | |
1557 | {0, 0, 0, 0, 0}, | |
1558 | }, | |
1559 | { | |
1560 | {0, 0, 0, 0, 0}, | |
1561 | {0, 0, 0, 0, 0}, | |
1562 | {0, 0, 0, 0, 0}, | |
1563 | {0, 0, 0, 0, 0}, | |
1564 | {0, 0, 0, 0, 0}, | |
1565 | {0, 0, 0, 0, 0}, | |
1566 | {0, 0, 0, 0, 0}, | |
1567 | {0, 0, 0, 0, 0}, | |
1568 | }, | |
1569 | ||
1570 | }, | |
1571 | .calTarget_freqbin_5G = { | |
1572 | FREQ2FBIN(5180, 0), | |
1573 | FREQ2FBIN(5240, 0), | |
1574 | FREQ2FBIN(5320, 0), | |
1575 | FREQ2FBIN(5400, 0), | |
1576 | FREQ2FBIN(5500, 0), | |
1577 | FREQ2FBIN(5600, 0), | |
1578 | FREQ2FBIN(5700, 0), | |
1579 | FREQ2FBIN(5825, 0) | |
1580 | }, | |
1581 | .calTarget_freqbin_5GHT20 = { | |
1582 | FREQ2FBIN(5180, 0), | |
1583 | FREQ2FBIN(5240, 0), | |
1584 | FREQ2FBIN(5320, 0), | |
1585 | FREQ2FBIN(5400, 0), | |
1586 | FREQ2FBIN(5500, 0), | |
1587 | FREQ2FBIN(5700, 0), | |
1588 | FREQ2FBIN(5745, 0), | |
1589 | FREQ2FBIN(5825, 0) | |
1590 | }, | |
1591 | .calTarget_freqbin_5GHT40 = { | |
1592 | FREQ2FBIN(5180, 0), | |
1593 | FREQ2FBIN(5240, 0), | |
1594 | FREQ2FBIN(5320, 0), | |
1595 | FREQ2FBIN(5400, 0), | |
1596 | FREQ2FBIN(5500, 0), | |
1597 | FREQ2FBIN(5700, 0), | |
1598 | FREQ2FBIN(5745, 0), | |
1599 | FREQ2FBIN(5825, 0) | |
1600 | }, | |
1601 | .calTargetPower5G = { | |
1602 | /* 6-24,36,48,54 */ | |
1603 | { {30, 30, 28, 24} }, | |
1604 | { {30, 30, 28, 24} }, | |
1605 | { {30, 30, 28, 24} }, | |
1606 | { {30, 30, 28, 24} }, | |
1607 | { {30, 30, 28, 24} }, | |
1608 | { {30, 30, 28, 24} }, | |
1609 | { {30, 30, 28, 24} }, | |
1610 | { {30, 30, 28, 24} }, | |
1611 | }, | |
1612 | .calTargetPower5GHT20 = { | |
1613 | /* | |
1614 | * 0_8_16,1-3_9-11_17-19, | |
1615 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
1616 | */ | |
1617 | { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} }, | |
1618 | { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} }, | |
1619 | { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} }, | |
1620 | { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} }, | |
1621 | { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} }, | |
1622 | { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} }, | |
1623 | { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} }, | |
1624 | { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} }, | |
1625 | }, | |
1626 | .calTargetPower5GHT40 = { | |
1627 | /* | |
1628 | * 0_8_16,1-3_9-11_17-19, | |
1629 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
1630 | */ | |
1631 | { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} }, | |
1632 | { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} }, | |
1633 | { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} }, | |
1634 | { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} }, | |
1635 | { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} }, | |
1636 | { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} }, | |
1637 | { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} }, | |
1638 | { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} }, | |
1639 | }, | |
1640 | .ctlIndex_5G = { | |
1641 | 0x10, 0x16, 0x18, 0x40, 0x46, | |
1642 | 0x48, 0x30, 0x36, 0x38 | |
1643 | }, | |
1644 | .ctl_freqbin_5G = { | |
1645 | { | |
1646 | /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1647 | /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1648 | /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
1649 | /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
1650 | /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), | |
1651 | /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1652 | /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
1653 | /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
1654 | }, | |
1655 | { | |
1656 | /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1657 | /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1658 | /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
1659 | /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
1660 | /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), | |
1661 | /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1662 | /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
1663 | /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
1664 | }, | |
1665 | ||
1666 | { | |
1667 | /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
1668 | /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
1669 | /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
1670 | /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), | |
1671 | /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), | |
1672 | /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), | |
1673 | /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), | |
1674 | /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) | |
1675 | }, | |
1676 | ||
1677 | { | |
1678 | /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1679 | /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
1680 | /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), | |
1681 | /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), | |
1682 | /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
1683 | /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1684 | /* Data[3].ctlEdges[6].bChannel */ 0xFF, | |
1685 | /* Data[3].ctlEdges[7].bChannel */ 0xFF, | |
1686 | }, | |
1687 | ||
1688 | { | |
1689 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1690 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1691 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), | |
1692 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), | |
1693 | /* Data[4].ctlEdges[4].bChannel */ 0xFF, | |
1694 | /* Data[4].ctlEdges[5].bChannel */ 0xFF, | |
1695 | /* Data[4].ctlEdges[6].bChannel */ 0xFF, | |
1696 | /* Data[4].ctlEdges[7].bChannel */ 0xFF, | |
1697 | }, | |
1698 | ||
1699 | { | |
1700 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
1701 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), | |
1702 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), | |
1703 | /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
1704 | /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), | |
1705 | /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
1706 | /* Data[5].ctlEdges[6].bChannel */ 0xFF, | |
1707 | /* Data[5].ctlEdges[7].bChannel */ 0xFF | |
1708 | }, | |
1709 | ||
1710 | { | |
1711 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1712 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
1713 | /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), | |
1714 | /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), | |
1715 | /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
1716 | /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), | |
1717 | /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), | |
1718 | /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) | |
1719 | }, | |
1720 | ||
1721 | { | |
1722 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1723 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1724 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), | |
1725 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
1726 | /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), | |
1727 | /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1728 | /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
1729 | /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
1730 | }, | |
1731 | ||
1732 | { | |
1733 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
1734 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
1735 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
1736 | /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
1737 | /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), | |
1738 | /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
1739 | /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), | |
1740 | /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) | |
1741 | } | |
1742 | }, | |
1743 | .ctlPowerData_5G = { | |
1744 | { | |
1745 | { | |
fe6c7915 DM |
1746 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1747 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
1748 | } |
1749 | }, | |
1750 | { | |
1751 | { | |
fe6c7915 DM |
1752 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1753 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
1754 | } |
1755 | }, | |
1756 | { | |
1757 | { | |
fe6c7915 DM |
1758 | CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
1759 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
1760 | } |
1761 | }, | |
1762 | { | |
1763 | { | |
fe6c7915 DM |
1764 | CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
1765 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
1766 | } |
1767 | }, | |
1768 | { | |
1769 | { | |
fe6c7915 DM |
1770 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
1771 | CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
1772 | } |
1773 | }, | |
1774 | { | |
1775 | { | |
fe6c7915 DM |
1776 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1777 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
1778 | } |
1779 | }, | |
1780 | { | |
1781 | { | |
fe6c7915 DM |
1782 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1783 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
1784 | } |
1785 | }, | |
1786 | { | |
1787 | { | |
fe6c7915 DM |
1788 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
1789 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
1790 | } |
1791 | }, | |
1792 | { | |
1793 | { | |
fe6c7915 DM |
1794 | CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), |
1795 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), | |
30923549 SB |
1796 | } |
1797 | }, | |
1798 | } | |
1799 | }; | |
1800 | ||
1801 | ||
1802 | static const struct ar9300_eeprom ar9300_x112 = { | |
1803 | .eepromVersion = 2, | |
1804 | .templateVersion = 5, | |
1805 | .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, | |
1806 | .custData = {"x112-041-f0000"}, | |
1807 | .baseEepHeader = { | |
1808 | .regDmn = { LE16(0), LE16(0x1f) }, | |
1809 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ | |
1810 | .opCapFlags = { | |
4ddfcd7d | 1811 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
30923549 SB |
1812 | .eepMisc = 0, |
1813 | }, | |
1814 | .rfSilent = 0, | |
1815 | .blueToothOptions = 0, | |
1816 | .deviceCap = 0, | |
1817 | .deviceType = 5, /* takes lower byte in eeprom location */ | |
1818 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, | |
1819 | .params_for_tuning_caps = {0, 0}, | |
1820 | .featureEnable = 0x0d, | |
1821 | /* | |
1822 | * bit0 - enable tx temp comp - disabled | |
1823 | * bit1 - enable tx volt comp - disabled | |
1824 | * bit2 - enable fastclock - enabled | |
1825 | * bit3 - enable doubling - enabled | |
1826 | * bit4 - enable internal regulator - disabled | |
1827 | * bit5 - enable pa predistortion - disabled | |
1828 | */ | |
1829 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ | |
1830 | .eepromWriteEnableGpio = 6, | |
1831 | .wlanDisableGpio = 0, | |
1832 | .wlanLedGpio = 8, | |
1833 | .rxBandSelectGpio = 0xff, | |
1834 | .txrxgain = 0x0, | |
1835 | .swreg = 0, | |
1836 | }, | |
1837 | .modalHeader2G = { | |
1838 | /* ar9300_modal_eep_header 2g */ | |
1839 | /* 4 idle,t1,t2,b(4 bits per setting) */ | |
1840 | .antCtrlCommon = LE32(0x110), | |
1841 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ | |
1842 | .antCtrlCommon2 = LE32(0x22222), | |
1843 | ||
1844 | /* | |
1845 | * antCtrlChain[ar9300_max_chains]; 6 idle, t, r, | |
1846 | * rx1, rx12, b (2 bits each) | |
1847 | */ | |
1848 | .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) }, | |
1849 | ||
1850 | /* | |
1851 | * xatten1DB[AR9300_max_chains]; 3 xatten1_db | |
1852 | * for ar9280 (0xa20c/b20c 5:0) | |
1853 | */ | |
1854 | .xatten1DB = {0x1b, 0x1b, 0x1b}, | |
1855 | ||
1856 | /* | |
1857 | * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin | |
1858 | * for ar9280 (0xa20c/b20c 16:12 | |
1859 | */ | |
1860 | .xatten1Margin = {0x15, 0x15, 0x15}, | |
1861 | .tempSlope = 50, | |
1862 | .voltSlope = 0, | |
1863 | ||
1864 | /* | |
1865 | * spurChans[OSPrey_eeprom_modal_sPURS]; spur | |
1866 | * channels in usual fbin coding format | |
1867 | */ | |
1868 | .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, | |
1869 | ||
1870 | /* | |
1871 | * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check | |
1872 | * if the register is per chain | |
1873 | */ | |
1874 | .noiseFloorThreshCh = {-1, 0, 0}, | |
1875 | .ob = {1, 1, 1},/* 3 chain */ | |
1876 | .db_stage2 = {1, 1, 1}, /* 3 chain */ | |
1877 | .db_stage3 = {0, 0, 0}, | |
1878 | .db_stage4 = {0, 0, 0}, | |
1879 | .xpaBiasLvl = 0, | |
1880 | .txFrameToDataStart = 0x0e, | |
1881 | .txFrameToPaOn = 0x0e, | |
1882 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
1883 | .antennaGain = 0, | |
1884 | .switchSettling = 0x2c, | |
1885 | .adcDesiredSize = -30, | |
1886 | .txEndToXpaOff = 0, | |
1887 | .txEndToRxOn = 0x2, | |
1888 | .txFrameToXpaOn = 0xe, | |
1889 | .thresh62 = 28, | |
1890 | .papdRateMaskHt20 = LE32(0x0c80c080), | |
1891 | .papdRateMaskHt40 = LE32(0x0080c080), | |
1892 | .futureModal = { | |
1893 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1894 | }, | |
1895 | }, | |
1896 | .base_ext1 = { | |
1897 | .ant_div_control = 0, | |
1898 | .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} | |
1899 | }, | |
1900 | .calFreqPier2G = { | |
1901 | FREQ2FBIN(2412, 1), | |
1902 | FREQ2FBIN(2437, 1), | |
1903 | FREQ2FBIN(2472, 1), | |
1904 | }, | |
1905 | /* ar9300_cal_data_per_freq_op_loop 2g */ | |
1906 | .calPierData2G = { | |
1907 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
1908 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
1909 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
1910 | }, | |
1911 | .calTarget_freqbin_Cck = { | |
1912 | FREQ2FBIN(2412, 1), | |
1913 | FREQ2FBIN(2472, 1), | |
1914 | }, | |
1915 | .calTarget_freqbin_2G = { | |
1916 | FREQ2FBIN(2412, 1), | |
1917 | FREQ2FBIN(2437, 1), | |
1918 | FREQ2FBIN(2472, 1) | |
1919 | }, | |
1920 | .calTarget_freqbin_2GHT20 = { | |
1921 | FREQ2FBIN(2412, 1), | |
1922 | FREQ2FBIN(2437, 1), | |
1923 | FREQ2FBIN(2472, 1) | |
1924 | }, | |
1925 | .calTarget_freqbin_2GHT40 = { | |
1926 | FREQ2FBIN(2412, 1), | |
1927 | FREQ2FBIN(2437, 1), | |
1928 | FREQ2FBIN(2472, 1) | |
1929 | }, | |
1930 | .calTargetPowerCck = { | |
1931 | /* 1L-5L,5S,11L,11s */ | |
1932 | { {38, 38, 38, 38} }, | |
1933 | { {38, 38, 38, 38} }, | |
1934 | }, | |
1935 | .calTargetPower2G = { | |
1936 | /* 6-24,36,48,54 */ | |
1937 | { {38, 38, 36, 34} }, | |
1938 | { {38, 38, 36, 34} }, | |
1939 | { {38, 38, 34, 32} }, | |
1940 | }, | |
1941 | .calTargetPower2GHT20 = { | |
1942 | { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} }, | |
1943 | { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} }, | |
1944 | { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} }, | |
1945 | }, | |
1946 | .calTargetPower2GHT40 = { | |
1947 | { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} }, | |
1948 | { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} }, | |
1949 | { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} }, | |
1950 | }, | |
1951 | .ctlIndex_2G = { | |
1952 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, | |
1953 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, | |
1954 | }, | |
1955 | .ctl_freqbin_2G = { | |
1956 | { | |
1957 | FREQ2FBIN(2412, 1), | |
1958 | FREQ2FBIN(2417, 1), | |
1959 | FREQ2FBIN(2457, 1), | |
1960 | FREQ2FBIN(2462, 1) | |
1961 | }, | |
1962 | { | |
1963 | FREQ2FBIN(2412, 1), | |
1964 | FREQ2FBIN(2417, 1), | |
1965 | FREQ2FBIN(2462, 1), | |
1966 | 0xFF, | |
1967 | }, | |
1968 | ||
1969 | { | |
1970 | FREQ2FBIN(2412, 1), | |
1971 | FREQ2FBIN(2417, 1), | |
1972 | FREQ2FBIN(2462, 1), | |
1973 | 0xFF, | |
1974 | }, | |
1975 | { | |
1976 | FREQ2FBIN(2422, 1), | |
1977 | FREQ2FBIN(2427, 1), | |
1978 | FREQ2FBIN(2447, 1), | |
1979 | FREQ2FBIN(2452, 1) | |
1980 | }, | |
1981 | ||
1982 | { | |
1983 | /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), | |
1984 | /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), | |
1985 | /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), | |
1986 | /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1), | |
1987 | }, | |
1988 | ||
1989 | { | |
1990 | /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), | |
1991 | /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), | |
1992 | /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), | |
1993 | 0, | |
1994 | }, | |
1995 | ||
1996 | { | |
1997 | /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), | |
1998 | /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), | |
1999 | FREQ2FBIN(2472, 1), | |
2000 | 0, | |
2001 | }, | |
2002 | ||
2003 | { | |
2004 | /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1), | |
2005 | /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1), | |
2006 | /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1), | |
2007 | /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1), | |
2008 | }, | |
2009 | ||
2010 | { | |
2011 | /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), | |
2012 | /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), | |
2013 | /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), | |
2014 | }, | |
2015 | ||
2016 | { | |
2017 | /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), | |
2018 | /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), | |
2019 | /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), | |
2020 | 0 | |
2021 | }, | |
2022 | ||
2023 | { | |
2024 | /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), | |
2025 | /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), | |
2026 | /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), | |
2027 | 0 | |
2028 | }, | |
2029 | ||
2030 | { | |
2031 | /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1), | |
2032 | /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1), | |
2033 | /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1), | |
2034 | /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1), | |
2035 | } | |
2036 | }, | |
2037 | .ctlPowerData_2G = { | |
fe6c7915 DM |
2038 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
2039 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
2040 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, | |
30923549 | 2041 | |
fe6c7915 DM |
2042 | { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } }, |
2043 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
2044 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 2045 | |
fe6c7915 DM |
2046 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, |
2047 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
2048 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 2049 | |
fe6c7915 DM |
2050 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
2051 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
2052 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
30923549 SB |
2053 | }, |
2054 | .modalHeader5G = { | |
2055 | /* 4 idle,t1,t2,b (4 bits per setting) */ | |
2056 | .antCtrlCommon = LE32(0x110), | |
2057 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ | |
2058 | .antCtrlCommon2 = LE32(0x22222), | |
2059 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ | |
2060 | .antCtrlChain = { | |
2061 | LE16(0x0), LE16(0x0), LE16(0x0), | |
2062 | }, | |
2063 | /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */ | |
2064 | .xatten1DB = {0x13, 0x19, 0x17}, | |
2065 | ||
2066 | /* | |
2067 | * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin | |
2068 | * for merlin (0xa20c/b20c 16:12 | |
2069 | */ | |
2070 | .xatten1Margin = {0x19, 0x19, 0x19}, | |
2071 | .tempSlope = 70, | |
2072 | .voltSlope = 15, | |
2073 | /* spurChans spur channels in usual fbin coding format */ | |
2074 | .spurChans = {0, 0, 0, 0, 0}, | |
2075 | /* noiseFloorThreshch check if the register is per chain */ | |
2076 | .noiseFloorThreshCh = {-1, 0, 0}, | |
2077 | .ob = {3, 3, 3}, /* 3 chain */ | |
2078 | .db_stage2 = {3, 3, 3}, /* 3 chain */ | |
2079 | .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ | |
2080 | .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ | |
2081 | .xpaBiasLvl = 0, | |
2082 | .txFrameToDataStart = 0x0e, | |
2083 | .txFrameToPaOn = 0x0e, | |
2084 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
2085 | .antennaGain = 0, | |
2086 | .switchSettling = 0x2d, | |
2087 | .adcDesiredSize = -30, | |
2088 | .txEndToXpaOff = 0, | |
2089 | .txEndToRxOn = 0x2, | |
2090 | .txFrameToXpaOn = 0xe, | |
2091 | .thresh62 = 28, | |
2092 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | |
2093 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | |
2094 | .futureModal = { | |
2095 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2096 | }, | |
2097 | }, | |
2098 | .base_ext2 = { | |
2099 | .tempSlopeLow = 72, | |
2100 | .tempSlopeHigh = 105, | |
2101 | .xatten1DBLow = {0x10, 0x14, 0x10}, | |
2102 | .xatten1MarginLow = {0x19, 0x19 , 0x19}, | |
2103 | .xatten1DBHigh = {0x1d, 0x20, 0x24}, | |
2104 | .xatten1MarginHigh = {0x10, 0x10, 0x10} | |
2105 | }, | |
2106 | .calFreqPier5G = { | |
2107 | FREQ2FBIN(5180, 0), | |
2108 | FREQ2FBIN(5220, 0), | |
2109 | FREQ2FBIN(5320, 0), | |
2110 | FREQ2FBIN(5400, 0), | |
2111 | FREQ2FBIN(5500, 0), | |
2112 | FREQ2FBIN(5600, 0), | |
2113 | FREQ2FBIN(5700, 0), | |
2114 | FREQ2FBIN(5785, 0) | |
2115 | }, | |
2116 | .calPierData5G = { | |
2117 | { | |
2118 | {0, 0, 0, 0, 0}, | |
2119 | {0, 0, 0, 0, 0}, | |
2120 | {0, 0, 0, 0, 0}, | |
2121 | {0, 0, 0, 0, 0}, | |
2122 | {0, 0, 0, 0, 0}, | |
2123 | {0, 0, 0, 0, 0}, | |
2124 | {0, 0, 0, 0, 0}, | |
2125 | {0, 0, 0, 0, 0}, | |
2126 | }, | |
2127 | { | |
2128 | {0, 0, 0, 0, 0}, | |
2129 | {0, 0, 0, 0, 0}, | |
2130 | {0, 0, 0, 0, 0}, | |
2131 | {0, 0, 0, 0, 0}, | |
2132 | {0, 0, 0, 0, 0}, | |
2133 | {0, 0, 0, 0, 0}, | |
2134 | {0, 0, 0, 0, 0}, | |
2135 | {0, 0, 0, 0, 0}, | |
2136 | }, | |
2137 | { | |
2138 | {0, 0, 0, 0, 0}, | |
2139 | {0, 0, 0, 0, 0}, | |
2140 | {0, 0, 0, 0, 0}, | |
2141 | {0, 0, 0, 0, 0}, | |
2142 | {0, 0, 0, 0, 0}, | |
2143 | {0, 0, 0, 0, 0}, | |
2144 | {0, 0, 0, 0, 0}, | |
2145 | {0, 0, 0, 0, 0}, | |
2146 | }, | |
2147 | ||
2148 | }, | |
2149 | .calTarget_freqbin_5G = { | |
2150 | FREQ2FBIN(5180, 0), | |
2151 | FREQ2FBIN(5220, 0), | |
2152 | FREQ2FBIN(5320, 0), | |
2153 | FREQ2FBIN(5400, 0), | |
2154 | FREQ2FBIN(5500, 0), | |
2155 | FREQ2FBIN(5600, 0), | |
2156 | FREQ2FBIN(5725, 0), | |
2157 | FREQ2FBIN(5825, 0) | |
2158 | }, | |
2159 | .calTarget_freqbin_5GHT20 = { | |
2160 | FREQ2FBIN(5180, 0), | |
2161 | FREQ2FBIN(5220, 0), | |
2162 | FREQ2FBIN(5320, 0), | |
2163 | FREQ2FBIN(5400, 0), | |
2164 | FREQ2FBIN(5500, 0), | |
2165 | FREQ2FBIN(5600, 0), | |
2166 | FREQ2FBIN(5725, 0), | |
2167 | FREQ2FBIN(5825, 0) | |
2168 | }, | |
2169 | .calTarget_freqbin_5GHT40 = { | |
2170 | FREQ2FBIN(5180, 0), | |
2171 | FREQ2FBIN(5220, 0), | |
2172 | FREQ2FBIN(5320, 0), | |
2173 | FREQ2FBIN(5400, 0), | |
2174 | FREQ2FBIN(5500, 0), | |
2175 | FREQ2FBIN(5600, 0), | |
2176 | FREQ2FBIN(5725, 0), | |
2177 | FREQ2FBIN(5825, 0) | |
2178 | }, | |
2179 | .calTargetPower5G = { | |
2180 | /* 6-24,36,48,54 */ | |
2181 | { {32, 32, 28, 26} }, | |
2182 | { {32, 32, 28, 26} }, | |
2183 | { {32, 32, 28, 26} }, | |
2184 | { {32, 32, 26, 24} }, | |
2185 | { {32, 32, 26, 24} }, | |
2186 | { {32, 32, 24, 22} }, | |
2187 | { {30, 30, 24, 22} }, | |
2188 | { {30, 30, 24, 22} }, | |
2189 | }, | |
2190 | .calTargetPower5GHT20 = { | |
2191 | /* | |
2192 | * 0_8_16,1-3_9-11_17-19, | |
2193 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
2194 | */ | |
2195 | { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, | |
2196 | { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, | |
2197 | { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, | |
2198 | { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} }, | |
2199 | { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} }, | |
2200 | { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} }, | |
2201 | { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} }, | |
2202 | { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} }, | |
2203 | }, | |
2204 | .calTargetPower5GHT40 = { | |
2205 | /* | |
2206 | * 0_8_16,1-3_9-11_17-19, | |
2207 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
2208 | */ | |
2209 | { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, | |
2210 | { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, | |
2211 | { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, | |
2212 | { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} }, | |
2213 | { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} }, | |
2214 | { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, | |
2215 | { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, | |
2216 | { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, | |
2217 | }, | |
2218 | .ctlIndex_5G = { | |
2219 | 0x10, 0x16, 0x18, 0x40, 0x46, | |
2220 | 0x48, 0x30, 0x36, 0x38 | |
2221 | }, | |
2222 | .ctl_freqbin_5G = { | |
2223 | { | |
2224 | /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), | |
2225 | /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), | |
2226 | /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0), | |
2227 | /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), | |
2228 | /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0), | |
2229 | /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), | |
2230 | /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), | |
2231 | /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) | |
2232 | }, | |
2233 | { | |
2234 | /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), | |
2235 | /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), | |
2236 | /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0), | |
2237 | /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), | |
2238 | /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0), | |
2239 | /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), | |
2240 | /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), | |
2241 | /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) | |
2242 | }, | |
2243 | ||
2244 | { | |
2245 | /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), | |
2246 | /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0), | |
2247 | /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0), | |
2248 | /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0), | |
2249 | /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0), | |
2250 | /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0), | |
2251 | /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0), | |
2252 | /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0) | |
2253 | }, | |
2254 | ||
2255 | { | |
2256 | /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), | |
2257 | /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0), | |
2258 | /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0), | |
2259 | /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0), | |
2260 | /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0), | |
2261 | /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), | |
2262 | /* Data[3].ctledges[6].bchannel */ 0xFF, | |
2263 | /* Data[3].ctledges[7].bchannel */ 0xFF, | |
2264 | }, | |
2265 | ||
2266 | { | |
2267 | /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), | |
2268 | /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), | |
2269 | /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0), | |
2270 | /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0), | |
2271 | /* Data[4].ctledges[4].bchannel */ 0xFF, | |
2272 | /* Data[4].ctledges[5].bchannel */ 0xFF, | |
2273 | /* Data[4].ctledges[6].bchannel */ 0xFF, | |
2274 | /* Data[4].ctledges[7].bchannel */ 0xFF, | |
2275 | }, | |
2276 | ||
2277 | { | |
2278 | /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), | |
2279 | /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0), | |
2280 | /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0), | |
2281 | /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0), | |
2282 | /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0), | |
2283 | /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0), | |
2284 | /* Data[5].ctledges[6].bchannel */ 0xFF, | |
2285 | /* Data[5].ctledges[7].bchannel */ 0xFF | |
2286 | }, | |
2287 | ||
2288 | { | |
2289 | /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), | |
2290 | /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0), | |
2291 | /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0), | |
2292 | /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0), | |
2293 | /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0), | |
2294 | /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0), | |
2295 | /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0), | |
2296 | /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0) | |
2297 | }, | |
2298 | ||
2299 | { | |
2300 | /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), | |
2301 | /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), | |
2302 | /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0), | |
2303 | /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), | |
2304 | /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0), | |
2305 | /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), | |
2306 | /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), | |
2307 | /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) | |
2308 | }, | |
2309 | ||
2310 | { | |
2311 | /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), | |
2312 | /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0), | |
2313 | /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0), | |
2314 | /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0), | |
2315 | /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0), | |
2316 | /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0), | |
2317 | /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0), | |
2318 | /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0) | |
2319 | } | |
2320 | }, | |
2321 | .ctlPowerData_5G = { | |
2322 | { | |
2323 | { | |
fe6c7915 DM |
2324 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2325 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
2326 | } |
2327 | }, | |
2328 | { | |
2329 | { | |
fe6c7915 DM |
2330 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2331 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
2332 | } |
2333 | }, | |
2334 | { | |
2335 | { | |
fe6c7915 DM |
2336 | CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
2337 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
2338 | } |
2339 | }, | |
2340 | { | |
2341 | { | |
fe6c7915 DM |
2342 | CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
2343 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
2344 | } |
2345 | }, | |
2346 | { | |
2347 | { | |
fe6c7915 DM |
2348 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
2349 | CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
2350 | } |
2351 | }, | |
2352 | { | |
2353 | { | |
fe6c7915 DM |
2354 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2355 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
2356 | } |
2357 | }, | |
2358 | { | |
2359 | { | |
fe6c7915 DM |
2360 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2361 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
2362 | } |
2363 | }, | |
2364 | { | |
2365 | { | |
fe6c7915 DM |
2366 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
2367 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
2368 | } |
2369 | }, | |
2370 | { | |
2371 | { | |
fe6c7915 DM |
2372 | CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), |
2373 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), | |
30923549 SB |
2374 | } |
2375 | }, | |
2376 | } | |
2377 | }; | |
2378 | ||
2379 | static const struct ar9300_eeprom ar9300_h116 = { | |
2380 | .eepromVersion = 2, | |
2381 | .templateVersion = 4, | |
2382 | .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, | |
2383 | .custData = {"h116-041-f0000"}, | |
2384 | .baseEepHeader = { | |
2385 | .regDmn = { LE16(0), LE16(0x1f) }, | |
2386 | .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */ | |
2387 | .opCapFlags = { | |
4ddfcd7d | 2388 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
30923549 SB |
2389 | .eepMisc = 0, |
2390 | }, | |
2391 | .rfSilent = 0, | |
2392 | .blueToothOptions = 0, | |
2393 | .deviceCap = 0, | |
2394 | .deviceType = 5, /* takes lower byte in eeprom location */ | |
2395 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, | |
2396 | .params_for_tuning_caps = {0, 0}, | |
2397 | .featureEnable = 0x0d, | |
2398 | /* | |
2399 | * bit0 - enable tx temp comp - disabled | |
2400 | * bit1 - enable tx volt comp - disabled | |
2401 | * bit2 - enable fastClock - enabled | |
2402 | * bit3 - enable doubling - enabled | |
2403 | * bit4 - enable internal regulator - disabled | |
2404 | * bit5 - enable pa predistortion - disabled | |
2405 | */ | |
2406 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ | |
2407 | .eepromWriteEnableGpio = 6, | |
2408 | .wlanDisableGpio = 0, | |
2409 | .wlanLedGpio = 8, | |
2410 | .rxBandSelectGpio = 0xff, | |
2411 | .txrxgain = 0x10, | |
2412 | .swreg = 0, | |
2413 | }, | |
2414 | .modalHeader2G = { | |
2415 | /* ar9300_modal_eep_header 2g */ | |
2416 | /* 4 idle,t1,t2,b(4 bits per setting) */ | |
2417 | .antCtrlCommon = LE32(0x110), | |
2418 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ | |
2419 | .antCtrlCommon2 = LE32(0x44444), | |
2420 | ||
2421 | /* | |
2422 | * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, | |
2423 | * rx1, rx12, b (2 bits each) | |
2424 | */ | |
2425 | .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) }, | |
2426 | ||
2427 | /* | |
2428 | * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db | |
2429 | * for ar9280 (0xa20c/b20c 5:0) | |
2430 | */ | |
2431 | .xatten1DB = {0x1f, 0x1f, 0x1f}, | |
2432 | ||
2433 | /* | |
2434 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
2435 | * for ar9280 (0xa20c/b20c 16:12 | |
2436 | */ | |
2437 | .xatten1Margin = {0x12, 0x12, 0x12}, | |
2438 | .tempSlope = 25, | |
2439 | .voltSlope = 0, | |
2440 | ||
2441 | /* | |
2442 | * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur | |
2443 | * channels in usual fbin coding format | |
2444 | */ | |
2445 | .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, | |
2446 | ||
2447 | /* | |
2448 | * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check | |
2449 | * if the register is per chain | |
2450 | */ | |
2451 | .noiseFloorThreshCh = {-1, 0, 0}, | |
2452 | .ob = {1, 1, 1},/* 3 chain */ | |
2453 | .db_stage2 = {1, 1, 1}, /* 3 chain */ | |
2454 | .db_stage3 = {0, 0, 0}, | |
2455 | .db_stage4 = {0, 0, 0}, | |
2456 | .xpaBiasLvl = 0, | |
2457 | .txFrameToDataStart = 0x0e, | |
2458 | .txFrameToPaOn = 0x0e, | |
2459 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
2460 | .antennaGain = 0, | |
2461 | .switchSettling = 0x2c, | |
2462 | .adcDesiredSize = -30, | |
2463 | .txEndToXpaOff = 0, | |
2464 | .txEndToRxOn = 0x2, | |
2465 | .txFrameToXpaOn = 0xe, | |
2466 | .thresh62 = 28, | |
2467 | .papdRateMaskHt20 = LE32(0x0c80C080), | |
2468 | .papdRateMaskHt40 = LE32(0x0080C080), | |
2469 | .futureModal = { | |
2470 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2471 | }, | |
2472 | }, | |
2473 | .base_ext1 = { | |
2474 | .ant_div_control = 0, | |
2475 | .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} | |
2476 | }, | |
2477 | .calFreqPier2G = { | |
2478 | FREQ2FBIN(2412, 1), | |
2479 | FREQ2FBIN(2437, 1), | |
2480 | FREQ2FBIN(2472, 1), | |
2481 | }, | |
2482 | /* ar9300_cal_data_per_freq_op_loop 2g */ | |
2483 | .calPierData2G = { | |
2484 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
2485 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
2486 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
2487 | }, | |
2488 | .calTarget_freqbin_Cck = { | |
2489 | FREQ2FBIN(2412, 1), | |
2490 | FREQ2FBIN(2472, 1), | |
2491 | }, | |
2492 | .calTarget_freqbin_2G = { | |
2493 | FREQ2FBIN(2412, 1), | |
2494 | FREQ2FBIN(2437, 1), | |
2495 | FREQ2FBIN(2472, 1) | |
2496 | }, | |
2497 | .calTarget_freqbin_2GHT20 = { | |
2498 | FREQ2FBIN(2412, 1), | |
2499 | FREQ2FBIN(2437, 1), | |
2500 | FREQ2FBIN(2472, 1) | |
2501 | }, | |
2502 | .calTarget_freqbin_2GHT40 = { | |
2503 | FREQ2FBIN(2412, 1), | |
2504 | FREQ2FBIN(2437, 1), | |
2505 | FREQ2FBIN(2472, 1) | |
2506 | }, | |
2507 | .calTargetPowerCck = { | |
2508 | /* 1L-5L,5S,11L,11S */ | |
2509 | { {34, 34, 34, 34} }, | |
2510 | { {34, 34, 34, 34} }, | |
2511 | }, | |
2512 | .calTargetPower2G = { | |
2513 | /* 6-24,36,48,54 */ | |
2514 | { {34, 34, 32, 32} }, | |
2515 | { {34, 34, 32, 32} }, | |
2516 | { {34, 34, 32, 32} }, | |
2517 | }, | |
2518 | .calTargetPower2GHT20 = { | |
2519 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, | |
2520 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, | |
2521 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, | |
2522 | }, | |
2523 | .calTargetPower2GHT40 = { | |
2524 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, | |
2525 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, | |
2526 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, | |
2527 | }, | |
2528 | .ctlIndex_2G = { | |
2529 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, | |
2530 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, | |
2531 | }, | |
2532 | .ctl_freqbin_2G = { | |
2533 | { | |
2534 | FREQ2FBIN(2412, 1), | |
2535 | FREQ2FBIN(2417, 1), | |
2536 | FREQ2FBIN(2457, 1), | |
2537 | FREQ2FBIN(2462, 1) | |
2538 | }, | |
2539 | { | |
2540 | FREQ2FBIN(2412, 1), | |
2541 | FREQ2FBIN(2417, 1), | |
2542 | FREQ2FBIN(2462, 1), | |
2543 | 0xFF, | |
2544 | }, | |
2545 | ||
2546 | { | |
2547 | FREQ2FBIN(2412, 1), | |
2548 | FREQ2FBIN(2417, 1), | |
2549 | FREQ2FBIN(2462, 1), | |
2550 | 0xFF, | |
2551 | }, | |
2552 | { | |
2553 | FREQ2FBIN(2422, 1), | |
2554 | FREQ2FBIN(2427, 1), | |
2555 | FREQ2FBIN(2447, 1), | |
2556 | FREQ2FBIN(2452, 1) | |
2557 | }, | |
2558 | ||
2559 | { | |
2560 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
2561 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
2562 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
2563 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), | |
2564 | }, | |
2565 | ||
2566 | { | |
2567 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
2568 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
2569 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
2570 | 0, | |
2571 | }, | |
2572 | ||
2573 | { | |
2574 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
2575 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
2576 | FREQ2FBIN(2472, 1), | |
2577 | 0, | |
2578 | }, | |
2579 | ||
2580 | { | |
2581 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
2582 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
2583 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
2584 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
2585 | }, | |
2586 | ||
2587 | { | |
2588 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
2589 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
2590 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
2591 | }, | |
2592 | ||
2593 | { | |
2594 | /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
2595 | /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
2596 | /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
2597 | 0 | |
2598 | }, | |
2599 | ||
2600 | { | |
2601 | /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
2602 | /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
2603 | /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
2604 | 0 | |
2605 | }, | |
2606 | ||
2607 | { | |
2608 | /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
2609 | /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
2610 | /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
2611 | /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
2612 | } | |
2613 | }, | |
2614 | .ctlPowerData_2G = { | |
e702ba18 FF |
2615 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
2616 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
2617 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, | |
30923549 | 2618 | |
e702ba18 FF |
2619 | { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } }, |
2620 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
2621 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 2622 | |
e702ba18 FF |
2623 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, |
2624 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
2625 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 2626 | |
e702ba18 FF |
2627 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
2628 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
2629 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
30923549 SB |
2630 | }, |
2631 | .modalHeader5G = { | |
2632 | /* 4 idle,t1,t2,b (4 bits per setting) */ | |
2633 | .antCtrlCommon = LE32(0x220), | |
2634 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ | |
2635 | .antCtrlCommon2 = LE32(0x44444), | |
2636 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ | |
2637 | .antCtrlChain = { | |
2638 | LE16(0x150), LE16(0x150), LE16(0x150), | |
2639 | }, | |
2640 | /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ | |
2641 | .xatten1DB = {0x19, 0x19, 0x19}, | |
2642 | ||
2643 | /* | |
2644 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
2645 | * for merlin (0xa20c/b20c 16:12 | |
2646 | */ | |
2647 | .xatten1Margin = {0x14, 0x14, 0x14}, | |
2648 | .tempSlope = 70, | |
2649 | .voltSlope = 0, | |
2650 | /* spurChans spur channels in usual fbin coding format */ | |
2651 | .spurChans = {0, 0, 0, 0, 0}, | |
2652 | /* noiseFloorThreshCh Check if the register is per chain */ | |
2653 | .noiseFloorThreshCh = {-1, 0, 0}, | |
2654 | .ob = {3, 3, 3}, /* 3 chain */ | |
2655 | .db_stage2 = {3, 3, 3}, /* 3 chain */ | |
2656 | .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ | |
2657 | .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ | |
2658 | .xpaBiasLvl = 0, | |
2659 | .txFrameToDataStart = 0x0e, | |
2660 | .txFrameToPaOn = 0x0e, | |
2661 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
2662 | .antennaGain = 0, | |
2663 | .switchSettling = 0x2d, | |
2664 | .adcDesiredSize = -30, | |
2665 | .txEndToXpaOff = 0, | |
2666 | .txEndToRxOn = 0x2, | |
2667 | .txFrameToXpaOn = 0xe, | |
2668 | .thresh62 = 28, | |
2669 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | |
2670 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | |
2671 | .futureModal = { | |
2672 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2673 | }, | |
2674 | }, | |
2675 | .base_ext2 = { | |
2676 | .tempSlopeLow = 35, | |
2677 | .tempSlopeHigh = 50, | |
2678 | .xatten1DBLow = {0, 0, 0}, | |
2679 | .xatten1MarginLow = {0, 0, 0}, | |
2680 | .xatten1DBHigh = {0, 0, 0}, | |
2681 | .xatten1MarginHigh = {0, 0, 0} | |
2682 | }, | |
2683 | .calFreqPier5G = { | |
2684 | FREQ2FBIN(5180, 0), | |
2685 | FREQ2FBIN(5220, 0), | |
2686 | FREQ2FBIN(5320, 0), | |
2687 | FREQ2FBIN(5400, 0), | |
2688 | FREQ2FBIN(5500, 0), | |
2689 | FREQ2FBIN(5600, 0), | |
2690 | FREQ2FBIN(5700, 0), | |
2691 | FREQ2FBIN(5785, 0) | |
2692 | }, | |
2693 | .calPierData5G = { | |
2694 | { | |
2695 | {0, 0, 0, 0, 0}, | |
2696 | {0, 0, 0, 0, 0}, | |
2697 | {0, 0, 0, 0, 0}, | |
2698 | {0, 0, 0, 0, 0}, | |
2699 | {0, 0, 0, 0, 0}, | |
2700 | {0, 0, 0, 0, 0}, | |
2701 | {0, 0, 0, 0, 0}, | |
2702 | {0, 0, 0, 0, 0}, | |
2703 | }, | |
2704 | { | |
2705 | {0, 0, 0, 0, 0}, | |
2706 | {0, 0, 0, 0, 0}, | |
2707 | {0, 0, 0, 0, 0}, | |
2708 | {0, 0, 0, 0, 0}, | |
2709 | {0, 0, 0, 0, 0}, | |
2710 | {0, 0, 0, 0, 0}, | |
2711 | {0, 0, 0, 0, 0}, | |
2712 | {0, 0, 0, 0, 0}, | |
2713 | }, | |
2714 | { | |
2715 | {0, 0, 0, 0, 0}, | |
2716 | {0, 0, 0, 0, 0}, | |
2717 | {0, 0, 0, 0, 0}, | |
2718 | {0, 0, 0, 0, 0}, | |
2719 | {0, 0, 0, 0, 0}, | |
2720 | {0, 0, 0, 0, 0}, | |
2721 | {0, 0, 0, 0, 0}, | |
2722 | {0, 0, 0, 0, 0}, | |
2723 | }, | |
2724 | ||
2725 | }, | |
2726 | .calTarget_freqbin_5G = { | |
2727 | FREQ2FBIN(5180, 0), | |
2728 | FREQ2FBIN(5240, 0), | |
2729 | FREQ2FBIN(5320, 0), | |
2730 | FREQ2FBIN(5400, 0), | |
2731 | FREQ2FBIN(5500, 0), | |
2732 | FREQ2FBIN(5600, 0), | |
2733 | FREQ2FBIN(5700, 0), | |
2734 | FREQ2FBIN(5825, 0) | |
2735 | }, | |
2736 | .calTarget_freqbin_5GHT20 = { | |
2737 | FREQ2FBIN(5180, 0), | |
2738 | FREQ2FBIN(5240, 0), | |
2739 | FREQ2FBIN(5320, 0), | |
2740 | FREQ2FBIN(5400, 0), | |
2741 | FREQ2FBIN(5500, 0), | |
2742 | FREQ2FBIN(5700, 0), | |
2743 | FREQ2FBIN(5745, 0), | |
2744 | FREQ2FBIN(5825, 0) | |
2745 | }, | |
2746 | .calTarget_freqbin_5GHT40 = { | |
2747 | FREQ2FBIN(5180, 0), | |
2748 | FREQ2FBIN(5240, 0), | |
2749 | FREQ2FBIN(5320, 0), | |
2750 | FREQ2FBIN(5400, 0), | |
2751 | FREQ2FBIN(5500, 0), | |
2752 | FREQ2FBIN(5700, 0), | |
2753 | FREQ2FBIN(5745, 0), | |
2754 | FREQ2FBIN(5825, 0) | |
2755 | }, | |
2756 | .calTargetPower5G = { | |
2757 | /* 6-24,36,48,54 */ | |
2758 | { {30, 30, 28, 24} }, | |
2759 | { {30, 30, 28, 24} }, | |
2760 | { {30, 30, 28, 24} }, | |
2761 | { {30, 30, 28, 24} }, | |
2762 | { {30, 30, 28, 24} }, | |
2763 | { {30, 30, 28, 24} }, | |
2764 | { {30, 30, 28, 24} }, | |
2765 | { {30, 30, 28, 24} }, | |
2766 | }, | |
2767 | .calTargetPower5GHT20 = { | |
2768 | /* | |
2769 | * 0_8_16,1-3_9-11_17-19, | |
2770 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
2771 | */ | |
2772 | { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} }, | |
2773 | { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} }, | |
2774 | { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} }, | |
2775 | { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} }, | |
2776 | { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} }, | |
2777 | { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} }, | |
2778 | { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} }, | |
2779 | { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} }, | |
2780 | }, | |
2781 | .calTargetPower5GHT40 = { | |
2782 | /* | |
2783 | * 0_8_16,1-3_9-11_17-19, | |
2784 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
2785 | */ | |
2786 | { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} }, | |
2787 | { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} }, | |
2788 | { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} }, | |
2789 | { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} }, | |
2790 | { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} }, | |
2791 | { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} }, | |
2792 | { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} }, | |
2793 | { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} }, | |
2794 | }, | |
2795 | .ctlIndex_5G = { | |
2796 | 0x10, 0x16, 0x18, 0x40, 0x46, | |
2797 | 0x48, 0x30, 0x36, 0x38 | |
2798 | }, | |
2799 | .ctl_freqbin_5G = { | |
2800 | { | |
2801 | /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
2802 | /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
2803 | /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
2804 | /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
2805 | /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), | |
2806 | /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
2807 | /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
2808 | /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
2809 | }, | |
2810 | { | |
2811 | /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
2812 | /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
2813 | /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
2814 | /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
2815 | /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), | |
2816 | /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
2817 | /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
2818 | /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
2819 | }, | |
2820 | ||
2821 | { | |
2822 | /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
2823 | /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
2824 | /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
2825 | /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), | |
2826 | /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), | |
2827 | /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), | |
2828 | /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), | |
2829 | /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) | |
2830 | }, | |
2831 | ||
2832 | { | |
2833 | /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
2834 | /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
2835 | /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), | |
2836 | /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), | |
2837 | /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
2838 | /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
2839 | /* Data[3].ctlEdges[6].bChannel */ 0xFF, | |
2840 | /* Data[3].ctlEdges[7].bChannel */ 0xFF, | |
2841 | }, | |
2842 | ||
2843 | { | |
2844 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
2845 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
2846 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), | |
2847 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), | |
2848 | /* Data[4].ctlEdges[4].bChannel */ 0xFF, | |
2849 | /* Data[4].ctlEdges[5].bChannel */ 0xFF, | |
2850 | /* Data[4].ctlEdges[6].bChannel */ 0xFF, | |
2851 | /* Data[4].ctlEdges[7].bChannel */ 0xFF, | |
2852 | }, | |
2853 | ||
2854 | { | |
2855 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
2856 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), | |
2857 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), | |
2858 | /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
2859 | /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), | |
2860 | /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
2861 | /* Data[5].ctlEdges[6].bChannel */ 0xFF, | |
2862 | /* Data[5].ctlEdges[7].bChannel */ 0xFF | |
2863 | }, | |
2864 | ||
2865 | { | |
2866 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
2867 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
2868 | /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), | |
2869 | /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), | |
2870 | /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
2871 | /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), | |
2872 | /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), | |
2873 | /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) | |
2874 | }, | |
2875 | ||
2876 | { | |
2877 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
2878 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
2879 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), | |
2880 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
2881 | /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), | |
2882 | /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
2883 | /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
2884 | /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
2885 | }, | |
2886 | ||
2887 | { | |
2888 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
2889 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
2890 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
2891 | /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
2892 | /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), | |
2893 | /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
2894 | /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), | |
2895 | /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) | |
2896 | } | |
2897 | }, | |
2898 | .ctlPowerData_5G = { | |
2899 | { | |
2900 | { | |
e702ba18 FF |
2901 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2902 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
2903 | } |
2904 | }, | |
2905 | { | |
2906 | { | |
e702ba18 FF |
2907 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2908 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
2909 | } |
2910 | }, | |
2911 | { | |
2912 | { | |
e702ba18 FF |
2913 | CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
2914 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
2915 | } |
2916 | }, | |
2917 | { | |
2918 | { | |
e702ba18 FF |
2919 | CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
2920 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
2921 | } |
2922 | }, | |
2923 | { | |
2924 | { | |
e702ba18 FF |
2925 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
2926 | CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
2927 | } |
2928 | }, | |
2929 | { | |
2930 | { | |
e702ba18 FF |
2931 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2932 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
2933 | } |
2934 | }, | |
2935 | { | |
2936 | { | |
e702ba18 FF |
2937 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2938 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
2939 | } |
2940 | }, | |
2941 | { | |
2942 | { | |
e702ba18 FF |
2943 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
2944 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
2945 | } |
2946 | }, | |
2947 | { | |
2948 | { | |
e702ba18 FF |
2949 | CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), |
2950 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), | |
30923549 SB |
2951 | } |
2952 | }, | |
2953 | } | |
2954 | }; | |
2955 | ||
2956 | ||
2957 | static const struct ar9300_eeprom *ar9300_eep_templates[] = { | |
2958 | &ar9300_default, | |
2959 | &ar9300_x112, | |
2960 | &ar9300_h116, | |
2961 | &ar9300_h112, | |
2962 | &ar9300_x113, | |
2963 | }; | |
2964 | ||
2965 | static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id) | |
2966 | { | |
2967 | #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0])) | |
2968 | int it; | |
2969 | ||
2970 | for (it = 0; it < N_LOOP; it++) | |
2971 | if (ar9300_eep_templates[it]->templateVersion == id) | |
2972 | return ar9300_eep_templates[it]; | |
2973 | return NULL; | |
2974 | #undef N_LOOP | |
2975 | } | |
2976 | ||
2977 | ||
824b185a LR |
2978 | static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) |
2979 | { | |
4ddfcd7d | 2980 | if (fbin == AR5416_BCHAN_UNUSED) |
824b185a LR |
2981 | return fbin; |
2982 | ||
2983 | return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); | |
2984 | } | |
2985 | ||
15c9ee7a SB |
2986 | static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah) |
2987 | { | |
2988 | return 0; | |
2989 | } | |
2990 | ||
bc206802 VT |
2991 | static int interpolate(int x, int xa, int xb, int ya, int yb) |
2992 | { | |
2993 | int bf, factor, plus; | |
2994 | ||
2995 | bf = 2 * (yb - ya) * (x - xa) / (xb - xa); | |
2996 | factor = bf / 2; | |
2997 | plus = bf % 2; | |
2998 | return ya + factor + plus; | |
2999 | } | |
3000 | ||
15c9ee7a SB |
3001 | static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, |
3002 | enum eeprom_param param) | |
3003 | { | |
3004 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3005 | struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; | |
3006 | ||
3007 | switch (param) { | |
3008 | case EEP_MAC_LSW: | |
3009 | return eep->macAddr[0] << 8 | eep->macAddr[1]; | |
3010 | case EEP_MAC_MID: | |
3011 | return eep->macAddr[2] << 8 | eep->macAddr[3]; | |
3012 | case EEP_MAC_MSW: | |
3013 | return eep->macAddr[4] << 8 | eep->macAddr[5]; | |
3014 | case EEP_REG_0: | |
ffdc4cbe | 3015 | return le16_to_cpu(pBase->regDmn[0]); |
15c9ee7a | 3016 | case EEP_REG_1: |
ffdc4cbe | 3017 | return le16_to_cpu(pBase->regDmn[1]); |
15c9ee7a SB |
3018 | case EEP_OP_CAP: |
3019 | return pBase->deviceCap; | |
3020 | case EEP_OP_MODE: | |
3021 | return pBase->opCapFlags.opFlags; | |
3022 | case EEP_RF_SILENT: | |
3023 | return pBase->rfSilent; | |
3024 | case EEP_TX_MASK: | |
3025 | return (pBase->txrxMask >> 4) & 0xf; | |
3026 | case EEP_RX_MASK: | |
3027 | return pBase->txrxMask & 0xf; | |
3028 | case EEP_DRIVE_STRENGTH: | |
3029 | #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1 | |
3030 | return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH; | |
3031 | case EEP_INTERNAL_REGULATOR: | |
3032 | /* Bit 4 is internal regulator flag */ | |
3033 | return (pBase->featureEnable & 0x10) >> 4; | |
3034 | case EEP_SWREG: | |
ffdc4cbe | 3035 | return le32_to_cpu(pBase->swreg); |
4935250a FF |
3036 | case EEP_PAPRD: |
3037 | return !!(pBase->featureEnable & BIT(5)); | |
ea066d5a MSS |
3038 | case EEP_CHAIN_MASK_REDUCE: |
3039 | return (pBase->miscConfiguration >> 0x3) & 0x1; | |
47e84dfb VT |
3040 | case EEP_ANT_DIV_CTL1: |
3041 | return le32_to_cpu(eep->base_ext1.ant_div_control); | |
15c9ee7a SB |
3042 | default: |
3043 | return 0; | |
3044 | } | |
3045 | } | |
3046 | ||
ffdc4cbe FF |
3047 | static bool ar9300_eeprom_read_byte(struct ath_common *common, int address, |
3048 | u8 *buffer) | |
15c9ee7a | 3049 | { |
ffdc4cbe | 3050 | u16 val; |
0cf31079 | 3051 | |
ffdc4cbe FF |
3052 | if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val))) |
3053 | return false; | |
15c9ee7a | 3054 | |
ffdc4cbe FF |
3055 | *buffer = (val >> (8 * (address % 2))) & 0xff; |
3056 | return true; | |
3057 | } | |
15c9ee7a | 3058 | |
ffdc4cbe FF |
3059 | static bool ar9300_eeprom_read_word(struct ath_common *common, int address, |
3060 | u8 *buffer) | |
3061 | { | |
3062 | u16 val; | |
15c9ee7a | 3063 | |
ffdc4cbe FF |
3064 | if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val))) |
3065 | return false; | |
15c9ee7a | 3066 | |
ffdc4cbe FF |
3067 | buffer[0] = val >> 8; |
3068 | buffer[1] = val & 0xff; | |
15c9ee7a | 3069 | |
ffdc4cbe | 3070 | return true; |
15c9ee7a | 3071 | } |
15c9ee7a | 3072 | |
ffdc4cbe FF |
3073 | static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, |
3074 | int count) | |
15c9ee7a | 3075 | { |
15c9ee7a | 3076 | struct ath_common *common = ath9k_hw_common(ah); |
ffdc4cbe | 3077 | int i; |
15c9ee7a | 3078 | |
ffdc4cbe | 3079 | if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) { |
226afe68 JP |
3080 | ath_dbg(common, ATH_DBG_EEPROM, |
3081 | "eeprom address not in range\n"); | |
15c9ee7a SB |
3082 | return false; |
3083 | } | |
3084 | ||
ffdc4cbe FF |
3085 | /* |
3086 | * Since we're reading the bytes in reverse order from a little-endian | |
3087 | * word stream, an even address means we only use the lower half of | |
3088 | * the 16-bit word at that address | |
3089 | */ | |
3090 | if (address % 2 == 0) { | |
3091 | if (!ar9300_eeprom_read_byte(common, address--, buffer++)) | |
3092 | goto error; | |
3093 | ||
3094 | count--; | |
15c9ee7a SB |
3095 | } |
3096 | ||
ffdc4cbe FF |
3097 | for (i = 0; i < count / 2; i++) { |
3098 | if (!ar9300_eeprom_read_word(common, address, buffer)) | |
3099 | goto error; | |
15c9ee7a | 3100 | |
ffdc4cbe FF |
3101 | address -= 2; |
3102 | buffer += 2; | |
3103 | } | |
3104 | ||
3105 | if (count % 2) | |
3106 | if (!ar9300_eeprom_read_byte(common, address, buffer)) | |
3107 | goto error; | |
15c9ee7a | 3108 | |
15c9ee7a | 3109 | return true; |
ffdc4cbe FF |
3110 | |
3111 | error: | |
226afe68 JP |
3112 | ath_dbg(common, ATH_DBG_EEPROM, |
3113 | "unable to read eeprom region at offset %d\n", address); | |
ffdc4cbe | 3114 | return false; |
15c9ee7a SB |
3115 | } |
3116 | ||
488f6ba7 FF |
3117 | static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data) |
3118 | { | |
3119 | REG_READ(ah, AR9300_OTP_BASE + (4 * addr)); | |
3120 | ||
3121 | if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE, | |
3122 | AR9300_OTP_STATUS_VALID, 1000)) | |
3123 | return false; | |
3124 | ||
3125 | *data = REG_READ(ah, AR9300_OTP_READ_DATA); | |
3126 | return true; | |
3127 | } | |
3128 | ||
3129 | static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer, | |
3130 | int count) | |
3131 | { | |
3132 | u32 data; | |
3133 | int i; | |
3134 | ||
3135 | for (i = 0; i < count; i++) { | |
3136 | int offset = 8 * ((address - i) % 4); | |
3137 | if (!ar9300_otp_read_word(ah, (address - i) / 4, &data)) | |
3138 | return false; | |
3139 | ||
3140 | buffer[i] = (data >> offset) & 0xff; | |
3141 | } | |
3142 | ||
3143 | return true; | |
3144 | } | |
3145 | ||
3146 | ||
15c9ee7a SB |
3147 | static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference, |
3148 | int *length, int *major, int *minor) | |
3149 | { | |
3150 | unsigned long value[4]; | |
3151 | ||
3152 | value[0] = best[0]; | |
3153 | value[1] = best[1]; | |
3154 | value[2] = best[2]; | |
3155 | value[3] = best[3]; | |
3156 | *code = ((value[0] >> 5) & 0x0007); | |
3157 | *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020); | |
3158 | *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f); | |
3159 | *major = (value[2] & 0x000f); | |
3160 | *minor = (value[3] & 0x00ff); | |
3161 | } | |
3162 | ||
3163 | static u16 ar9300_comp_cksum(u8 *data, int dsize) | |
3164 | { | |
3165 | int it, checksum = 0; | |
3166 | ||
3167 | for (it = 0; it < dsize; it++) { | |
3168 | checksum += data[it]; | |
3169 | checksum &= 0xffff; | |
3170 | } | |
3171 | ||
3172 | return checksum; | |
3173 | } | |
3174 | ||
3175 | static bool ar9300_uncompress_block(struct ath_hw *ah, | |
3176 | u8 *mptr, | |
3177 | int mdataSize, | |
3178 | u8 *block, | |
3179 | int size) | |
3180 | { | |
3181 | int it; | |
3182 | int spot; | |
3183 | int offset; | |
3184 | int length; | |
3185 | struct ath_common *common = ath9k_hw_common(ah); | |
3186 | ||
3187 | spot = 0; | |
3188 | ||
3189 | for (it = 0; it < size; it += (length+2)) { | |
3190 | offset = block[it]; | |
3191 | offset &= 0xff; | |
3192 | spot += offset; | |
3193 | length = block[it+1]; | |
3194 | length &= 0xff; | |
3195 | ||
803288e6 | 3196 | if (length > 0 && spot >= 0 && spot+length <= mdataSize) { |
226afe68 JP |
3197 | ath_dbg(common, ATH_DBG_EEPROM, |
3198 | "Restore at %d: spot=%d offset=%d length=%d\n", | |
3199 | it, spot, offset, length); | |
15c9ee7a SB |
3200 | memcpy(&mptr[spot], &block[it+2], length); |
3201 | spot += length; | |
3202 | } else if (length > 0) { | |
226afe68 JP |
3203 | ath_dbg(common, ATH_DBG_EEPROM, |
3204 | "Bad restore at %d: spot=%d offset=%d length=%d\n", | |
3205 | it, spot, offset, length); | |
15c9ee7a SB |
3206 | return false; |
3207 | } | |
3208 | } | |
3209 | return true; | |
3210 | } | |
3211 | ||
3212 | static int ar9300_compress_decision(struct ath_hw *ah, | |
3213 | int it, | |
3214 | int code, | |
3215 | int reference, | |
3216 | u8 *mptr, | |
3217 | u8 *word, int length, int mdata_size) | |
3218 | { | |
3219 | struct ath_common *common = ath9k_hw_common(ah); | |
3220 | u8 *dptr; | |
30923549 | 3221 | const struct ar9300_eeprom *eep = NULL; |
15c9ee7a SB |
3222 | |
3223 | switch (code) { | |
3224 | case _CompressNone: | |
3225 | if (length != mdata_size) { | |
226afe68 JP |
3226 | ath_dbg(common, ATH_DBG_EEPROM, |
3227 | "EEPROM structure size mismatch memory=%d eeprom=%d\n", | |
3228 | mdata_size, length); | |
15c9ee7a SB |
3229 | return -1; |
3230 | } | |
3231 | memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length); | |
226afe68 JP |
3232 | ath_dbg(common, ATH_DBG_EEPROM, |
3233 | "restored eeprom %d: uncompressed, length %d\n", | |
3234 | it, length); | |
15c9ee7a SB |
3235 | break; |
3236 | case _CompressBlock: | |
3237 | if (reference == 0) { | |
3238 | dptr = mptr; | |
3239 | } else { | |
30923549 SB |
3240 | eep = ar9003_eeprom_struct_find_by_id(reference); |
3241 | if (eep == NULL) { | |
226afe68 | 3242 | ath_dbg(common, ATH_DBG_EEPROM, |
25985edc | 3243 | "can't find reference eeprom struct %d\n", |
226afe68 | 3244 | reference); |
15c9ee7a SB |
3245 | return -1; |
3246 | } | |
30923549 | 3247 | memcpy(mptr, eep, mdata_size); |
15c9ee7a | 3248 | } |
226afe68 JP |
3249 | ath_dbg(common, ATH_DBG_EEPROM, |
3250 | "restore eeprom %d: block, reference %d, length %d\n", | |
3251 | it, reference, length); | |
15c9ee7a SB |
3252 | ar9300_uncompress_block(ah, mptr, mdata_size, |
3253 | (u8 *) (word + COMP_HDR_LEN), length); | |
3254 | break; | |
3255 | default: | |
226afe68 JP |
3256 | ath_dbg(common, ATH_DBG_EEPROM, |
3257 | "unknown compression code %d\n", code); | |
15c9ee7a SB |
3258 | return -1; |
3259 | } | |
3260 | return 0; | |
3261 | } | |
3262 | ||
488f6ba7 FF |
3263 | typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer, |
3264 | int count); | |
3265 | ||
3266 | static bool ar9300_check_header(void *data) | |
3267 | { | |
3268 | u32 *word = data; | |
3269 | return !(*word == 0 || *word == ~0); | |
3270 | } | |
3271 | ||
3272 | static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read, | |
3273 | int base_addr) | |
3274 | { | |
3275 | u8 header[4]; | |
3276 | ||
3277 | if (!read(ah, base_addr, header, 4)) | |
3278 | return false; | |
3279 | ||
3280 | return ar9300_check_header(header); | |
3281 | } | |
3282 | ||
aaa13ca2 FF |
3283 | static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr, |
3284 | int mdata_size) | |
3285 | { | |
3286 | struct ath_common *common = ath9k_hw_common(ah); | |
3287 | u16 *data = (u16 *) mptr; | |
3288 | int i; | |
3289 | ||
3290 | for (i = 0; i < mdata_size / 2; i++, data++) | |
3291 | ath9k_hw_nvram_read(common, i, data); | |
3292 | ||
3293 | return 0; | |
3294 | } | |
15c9ee7a SB |
3295 | /* |
3296 | * Read the configuration data from the eeprom. | |
3297 | * The data can be put in any specified memory buffer. | |
3298 | * | |
3299 | * Returns -1 on error. | |
3300 | * Returns address of next memory location on success. | |
3301 | */ | |
3302 | static int ar9300_eeprom_restore_internal(struct ath_hw *ah, | |
3303 | u8 *mptr, int mdata_size) | |
3304 | { | |
3305 | #define MDEFAULT 15 | |
3306 | #define MSTATE 100 | |
3307 | int cptr; | |
3308 | u8 *word; | |
3309 | int code; | |
3310 | int reference, length, major, minor; | |
3311 | int osize; | |
3312 | int it; | |
3313 | u16 checksum, mchecksum; | |
3314 | struct ath_common *common = ath9k_hw_common(ah); | |
488f6ba7 | 3315 | eeprom_read_op read; |
15c9ee7a | 3316 | |
aaa13ca2 FF |
3317 | if (ath9k_hw_use_flash(ah)) |
3318 | return ar9300_eeprom_restore_flash(ah, mptr, mdata_size); | |
3319 | ||
15c9ee7a SB |
3320 | word = kzalloc(2048, GFP_KERNEL); |
3321 | if (!word) | |
3322 | return -1; | |
3323 | ||
3324 | memcpy(mptr, &ar9300_default, mdata_size); | |
3325 | ||
488f6ba7 | 3326 | read = ar9300_read_eeprom; |
60e0c3a7 VT |
3327 | if (AR_SREV_9485(ah)) |
3328 | cptr = AR9300_BASE_ADDR_4K; | |
3329 | else | |
3330 | cptr = AR9300_BASE_ADDR; | |
226afe68 | 3331 | ath_dbg(common, ATH_DBG_EEPROM, |
488f6ba7 FF |
3332 | "Trying EEPROM accesss at Address 0x%04x\n", cptr); |
3333 | if (ar9300_check_eeprom_header(ah, read, cptr)) | |
3334 | goto found; | |
3335 | ||
3336 | cptr = AR9300_BASE_ADDR_512; | |
226afe68 | 3337 | ath_dbg(common, ATH_DBG_EEPROM, |
488f6ba7 FF |
3338 | "Trying EEPROM accesss at Address 0x%04x\n", cptr); |
3339 | if (ar9300_check_eeprom_header(ah, read, cptr)) | |
3340 | goto found; | |
3341 | ||
3342 | read = ar9300_read_otp; | |
3343 | cptr = AR9300_BASE_ADDR; | |
226afe68 | 3344 | ath_dbg(common, ATH_DBG_EEPROM, |
488f6ba7 FF |
3345 | "Trying OTP accesss at Address 0x%04x\n", cptr); |
3346 | if (ar9300_check_eeprom_header(ah, read, cptr)) | |
3347 | goto found; | |
3348 | ||
3349 | cptr = AR9300_BASE_ADDR_512; | |
226afe68 | 3350 | ath_dbg(common, ATH_DBG_EEPROM, |
488f6ba7 FF |
3351 | "Trying OTP accesss at Address 0x%04x\n", cptr); |
3352 | if (ar9300_check_eeprom_header(ah, read, cptr)) | |
3353 | goto found; | |
3354 | ||
3355 | goto fail; | |
3356 | ||
3357 | found: | |
226afe68 | 3358 | ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n"); |
488f6ba7 | 3359 | |
15c9ee7a | 3360 | for (it = 0; it < MSTATE; it++) { |
488f6ba7 | 3361 | if (!read(ah, cptr, word, COMP_HDR_LEN)) |
15c9ee7a SB |
3362 | goto fail; |
3363 | ||
488f6ba7 | 3364 | if (!ar9300_check_header(word)) |
15c9ee7a SB |
3365 | break; |
3366 | ||
3367 | ar9300_comp_hdr_unpack(word, &code, &reference, | |
3368 | &length, &major, &minor); | |
226afe68 JP |
3369 | ath_dbg(common, ATH_DBG_EEPROM, |
3370 | "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n", | |
3371 | cptr, code, reference, length, major, minor); | |
60e0c3a7 | 3372 | if ((!AR_SREV_9485(ah) && length >= 1024) || |
d0ce2d17 | 3373 | (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) { |
226afe68 JP |
3374 | ath_dbg(common, ATH_DBG_EEPROM, |
3375 | "Skipping bad header\n"); | |
15c9ee7a SB |
3376 | cptr -= COMP_HDR_LEN; |
3377 | continue; | |
3378 | } | |
3379 | ||
3380 | osize = length; | |
488f6ba7 | 3381 | read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN); |
15c9ee7a SB |
3382 | checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length); |
3383 | mchecksum = word[COMP_HDR_LEN + osize] | | |
3384 | (word[COMP_HDR_LEN + osize + 1] << 8); | |
226afe68 JP |
3385 | ath_dbg(common, ATH_DBG_EEPROM, |
3386 | "checksum %x %x\n", checksum, mchecksum); | |
15c9ee7a SB |
3387 | if (checksum == mchecksum) { |
3388 | ar9300_compress_decision(ah, it, code, reference, mptr, | |
3389 | word, length, mdata_size); | |
3390 | } else { | |
226afe68 JP |
3391 | ath_dbg(common, ATH_DBG_EEPROM, |
3392 | "skipping block with bad checksum\n"); | |
15c9ee7a SB |
3393 | } |
3394 | cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN); | |
3395 | } | |
3396 | ||
3397 | kfree(word); | |
3398 | return cptr; | |
3399 | ||
3400 | fail: | |
3401 | kfree(word); | |
3402 | return -1; | |
3403 | } | |
3404 | ||
3405 | /* | |
3406 | * Restore the configuration structure by reading the eeprom. | |
3407 | * This function destroys any existing in-memory structure | |
3408 | * content. | |
3409 | */ | |
3410 | static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah) | |
3411 | { | |
ffdc4cbe | 3412 | u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep; |
15c9ee7a | 3413 | |
ffdc4cbe FF |
3414 | if (ar9300_eeprom_restore_internal(ah, mptr, |
3415 | sizeof(struct ar9300_eeprom)) < 0) | |
3416 | return false; | |
15c9ee7a | 3417 | |
ffdc4cbe | 3418 | return true; |
15c9ee7a SB |
3419 | } |
3420 | ||
3421 | /* XXX: review hardware docs */ | |
3422 | static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah) | |
3423 | { | |
3424 | return ah->eeprom.ar9300_eep.eepromVersion; | |
3425 | } | |
3426 | ||
3427 | /* XXX: could be read from the eepromVersion, not sure yet */ | |
3428 | static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah) | |
3429 | { | |
3430 | return 0; | |
3431 | } | |
3432 | ||
15c9ee7a SB |
3433 | static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz) |
3434 | { | |
3435 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3436 | ||
3437 | if (is2ghz) | |
3438 | return eep->modalHeader2G.xpaBiasLvl; | |
3439 | else | |
3440 | return eep->modalHeader5G.xpaBiasLvl; | |
3441 | } | |
3442 | ||
3443 | static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) | |
3444 | { | |
3445 | int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz); | |
9936e65f VT |
3446 | |
3447 | if (AR_SREV_9485(ah)) | |
3448 | REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); | |
3449 | else { | |
3450 | REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); | |
3451 | REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, | |
3452 | bias >> 2); | |
3453 | REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1); | |
3454 | } | |
15c9ee7a SB |
3455 | } |
3456 | ||
3457 | static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) | |
3458 | { | |
3459 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
ffdc4cbe | 3460 | __le32 val; |
15c9ee7a SB |
3461 | |
3462 | if (is2ghz) | |
ffdc4cbe | 3463 | val = eep->modalHeader2G.antCtrlCommon; |
15c9ee7a | 3464 | else |
ffdc4cbe FF |
3465 | val = eep->modalHeader5G.antCtrlCommon; |
3466 | return le32_to_cpu(val); | |
15c9ee7a SB |
3467 | } |
3468 | ||
3469 | static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz) | |
3470 | { | |
3471 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
ffdc4cbe | 3472 | __le32 val; |
15c9ee7a SB |
3473 | |
3474 | if (is2ghz) | |
ffdc4cbe | 3475 | val = eep->modalHeader2G.antCtrlCommon2; |
15c9ee7a | 3476 | else |
ffdc4cbe FF |
3477 | val = eep->modalHeader5G.antCtrlCommon2; |
3478 | return le32_to_cpu(val); | |
15c9ee7a SB |
3479 | } |
3480 | ||
3481 | static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, | |
3482 | int chain, | |
3483 | bool is2ghz) | |
3484 | { | |
3485 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
ffdc4cbe | 3486 | __le16 val = 0; |
15c9ee7a SB |
3487 | |
3488 | if (chain >= 0 && chain < AR9300_MAX_CHAINS) { | |
3489 | if (is2ghz) | |
ffdc4cbe | 3490 | val = eep->modalHeader2G.antCtrlChain[chain]; |
15c9ee7a | 3491 | else |
ffdc4cbe | 3492 | val = eep->modalHeader5G.antCtrlChain[chain]; |
15c9ee7a SB |
3493 | } |
3494 | ||
ffdc4cbe | 3495 | return le16_to_cpu(val); |
15c9ee7a SB |
3496 | } |
3497 | ||
3498 | static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) | |
3499 | { | |
3500 | u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); | |
3501 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value); | |
3502 | ||
3503 | value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz); | |
3504 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value); | |
3505 | ||
3506 | value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz); | |
3507 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value); | |
3508 | ||
47e84dfb VT |
3509 | if (!AR_SREV_9485(ah)) { |
3510 | value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz); | |
3511 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, | |
3512 | value); | |
15c9ee7a | 3513 | |
47e84dfb VT |
3514 | value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz); |
3515 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, | |
3516 | value); | |
3517 | } | |
15c9ee7a | 3518 | |
47e84dfb VT |
3519 | if (AR_SREV_9485(ah)) { |
3520 | value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1); | |
3521 | REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_CTRL_ALL, | |
3522 | value); | |
3523 | REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE, | |
3524 | value >> 6); | |
3525 | REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE, | |
3526 | value >> 7); | |
3527 | } | |
15c9ee7a SB |
3528 | } |
3529 | ||
3530 | static void ar9003_hw_drive_strength_apply(struct ath_hw *ah) | |
3531 | { | |
3532 | int drive_strength; | |
3533 | unsigned long reg; | |
3534 | ||
3535 | drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH); | |
3536 | ||
3537 | if (!drive_strength) | |
3538 | return; | |
3539 | ||
3540 | reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1); | |
3541 | reg &= ~0x00ffffc0; | |
3542 | reg |= 0x5 << 21; | |
3543 | reg |= 0x5 << 18; | |
3544 | reg |= 0x5 << 15; | |
3545 | reg |= 0x5 << 12; | |
3546 | reg |= 0x5 << 9; | |
3547 | reg |= 0x5 << 6; | |
3548 | REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg); | |
3549 | ||
3550 | reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); | |
3551 | reg &= ~0xffffffe0; | |
3552 | reg |= 0x5 << 29; | |
3553 | reg |= 0x5 << 26; | |
3554 | reg |= 0x5 << 23; | |
3555 | reg |= 0x5 << 20; | |
3556 | reg |= 0x5 << 17; | |
3557 | reg |= 0x5 << 14; | |
3558 | reg |= 0x5 << 11; | |
3559 | reg |= 0x5 << 8; | |
3560 | reg |= 0x5 << 5; | |
3561 | REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg); | |
3562 | ||
3563 | reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); | |
3564 | reg &= ~0xff800000; | |
3565 | reg |= 0x5 << 29; | |
3566 | reg |= 0x5 << 26; | |
3567 | reg |= 0x5 << 23; | |
3568 | REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg); | |
3569 | } | |
3570 | ||
f4475a6e VT |
3571 | static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain, |
3572 | struct ath9k_channel *chan) | |
3573 | { | |
3574 | int f[3], t[3]; | |
3575 | u16 value; | |
3576 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3577 | ||
3578 | if (chain >= 0 && chain < 3) { | |
3579 | if (IS_CHAN_2GHZ(chan)) | |
3580 | return eep->modalHeader2G.xatten1DB[chain]; | |
3581 | else if (eep->base_ext2.xatten1DBLow[chain] != 0) { | |
3582 | t[0] = eep->base_ext2.xatten1DBLow[chain]; | |
3583 | f[0] = 5180; | |
3584 | t[1] = eep->modalHeader5G.xatten1DB[chain]; | |
3585 | f[1] = 5500; | |
3586 | t[2] = eep->base_ext2.xatten1DBHigh[chain]; | |
3587 | f[2] = 5785; | |
3588 | value = ar9003_hw_power_interpolate((s32) chan->channel, | |
3589 | f, t, 3); | |
3590 | return value; | |
3591 | } else | |
3592 | return eep->modalHeader5G.xatten1DB[chain]; | |
3593 | } | |
3594 | ||
3595 | return 0; | |
3596 | } | |
3597 | ||
3598 | ||
3599 | static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain, | |
3600 | struct ath9k_channel *chan) | |
3601 | { | |
3602 | int f[3], t[3]; | |
3603 | u16 value; | |
3604 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3605 | ||
3606 | if (chain >= 0 && chain < 3) { | |
3607 | if (IS_CHAN_2GHZ(chan)) | |
3608 | return eep->modalHeader2G.xatten1Margin[chain]; | |
3609 | else if (eep->base_ext2.xatten1MarginLow[chain] != 0) { | |
3610 | t[0] = eep->base_ext2.xatten1MarginLow[chain]; | |
3611 | f[0] = 5180; | |
3612 | t[1] = eep->modalHeader5G.xatten1Margin[chain]; | |
3613 | f[1] = 5500; | |
3614 | t[2] = eep->base_ext2.xatten1MarginHigh[chain]; | |
3615 | f[2] = 5785; | |
3616 | value = ar9003_hw_power_interpolate((s32) chan->channel, | |
3617 | f, t, 3); | |
3618 | return value; | |
3619 | } else | |
3620 | return eep->modalHeader5G.xatten1Margin[chain]; | |
3621 | } | |
3622 | ||
3623 | return 0; | |
3624 | } | |
3625 | ||
3626 | static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan) | |
3627 | { | |
3628 | int i; | |
3629 | u16 value; | |
3630 | unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0, | |
3631 | AR_PHY_EXT_ATTEN_CTL_1, | |
3632 | AR_PHY_EXT_ATTEN_CTL_2, | |
3633 | }; | |
3634 | ||
3635 | /* Test value. if 0 then attenuation is unused. Don't load anything. */ | |
3636 | for (i = 0; i < 3; i++) { | |
3637 | value = ar9003_hw_atten_chain_get(ah, i, chan); | |
3638 | REG_RMW_FIELD(ah, ext_atten_reg[i], | |
3639 | AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value); | |
3640 | ||
3641 | value = ar9003_hw_atten_chain_get_margin(ah, i, chan); | |
3642 | REG_RMW_FIELD(ah, ext_atten_reg[i], | |
3643 | AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value); | |
3644 | } | |
3645 | } | |
3646 | ||
ab09b5b4 VT |
3647 | static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set) |
3648 | { | |
3649 | int timeout = 100; | |
3650 | ||
3651 | while (pmu_set != REG_READ(ah, pmu_reg)) { | |
3652 | if (timeout-- == 0) | |
3653 | return false; | |
3654 | REG_WRITE(ah, pmu_reg, pmu_set); | |
3655 | udelay(10); | |
3656 | } | |
3657 | ||
3658 | return true; | |
3659 | } | |
3660 | ||
15c9ee7a SB |
3661 | static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) |
3662 | { | |
3663 | int internal_regulator = | |
3664 | ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR); | |
3665 | ||
3666 | if (internal_regulator) { | |
ab09b5b4 VT |
3667 | if (AR_SREV_9485(ah)) { |
3668 | int reg_pmu_set; | |
3669 | ||
3670 | reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM; | |
3671 | REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); | |
3672 | if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) | |
3673 | return; | |
3674 | ||
3675 | reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) | | |
ebefce3d | 3676 | (2 << 14) | (6 << 17) | (1 << 20) | |
ab09b5b4 VT |
3677 | (3 << 24) | (1 << 28); |
3678 | ||
3679 | REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set); | |
3680 | if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set)) | |
3681 | return; | |
3682 | ||
3683 | reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000) | |
3684 | | (4 << 26); | |
3685 | REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); | |
3686 | if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) | |
3687 | return; | |
3688 | ||
3689 | reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000) | |
3690 | | (1 << 21); | |
3691 | REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); | |
3692 | if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) | |
3693 | return; | |
3694 | } else { | |
3695 | /* Internal regulator is ON. Write swreg register. */ | |
3696 | int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG); | |
3697 | REG_WRITE(ah, AR_RTC_REG_CONTROL1, | |
3698 | REG_READ(ah, AR_RTC_REG_CONTROL1) & | |
3699 | (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM)); | |
3700 | REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg); | |
3701 | /* Set REG_CONTROL1.SWREG_PROGRAM */ | |
3702 | REG_WRITE(ah, AR_RTC_REG_CONTROL1, | |
3703 | REG_READ(ah, | |
3704 | AR_RTC_REG_CONTROL1) | | |
3705 | AR_RTC_REG_CONTROL1_SWREG_PROGRAM); | |
3706 | } | |
15c9ee7a | 3707 | } else { |
ab09b5b4 VT |
3708 | if (AR_SREV_9485(ah)) { |
3709 | REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0); | |
3710 | while (REG_READ_FIELD(ah, AR_PHY_PMU2, | |
3711 | AR_PHY_PMU2_PGM)) | |
3712 | udelay(10); | |
3713 | ||
3714 | REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); | |
3715 | while (!REG_READ_FIELD(ah, AR_PHY_PMU1, | |
3716 | AR_PHY_PMU1_PWD)) | |
3717 | udelay(10); | |
3718 | REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1); | |
3719 | while (!REG_READ_FIELD(ah, AR_PHY_PMU2, | |
3720 | AR_PHY_PMU2_PGM)) | |
3721 | udelay(10); | |
3722 | } else | |
3723 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, | |
3724 | (REG_READ(ah, | |
3725 | AR_RTC_SLEEP_CLK) | | |
3726 | AR_RTC_FORCE_SWREG_PRD)); | |
15c9ee7a | 3727 | } |
ab09b5b4 | 3728 | |
15c9ee7a SB |
3729 | } |
3730 | ||
dd040f76 VT |
3731 | static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah) |
3732 | { | |
3733 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3734 | u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0]; | |
3735 | ||
3736 | if (eep->baseEepHeader.featureEnable & 0x40) { | |
3737 | tuning_caps_param &= 0x7f; | |
3738 | REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC, | |
3739 | tuning_caps_param); | |
3740 | REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC, | |
3741 | tuning_caps_param); | |
15c9ee7a SB |
3742 | } |
3743 | } | |
3744 | ||
3745 | static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, | |
3746 | struct ath9k_channel *chan) | |
3747 | { | |
3748 | ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan)); | |
3749 | ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan)); | |
3750 | ar9003_hw_drive_strength_apply(ah); | |
f4475a6e | 3751 | ar9003_hw_atten_apply(ah, chan); |
15c9ee7a | 3752 | ar9003_hw_internal_regulator_apply(ah); |
dd040f76 VT |
3753 | if (AR_SREV_9485(ah)) |
3754 | ar9003_hw_apply_tuning_caps(ah); | |
15c9ee7a SB |
3755 | } |
3756 | ||
3757 | static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah, | |
3758 | struct ath9k_channel *chan) | |
3759 | { | |
3760 | } | |
3761 | ||
3762 | /* | |
3763 | * Returns the interpolated y value corresponding to the specified x value | |
3764 | * from the np ordered pairs of data (px,py). | |
3765 | * The pairs do not have to be in any order. | |
3766 | * If the specified x value is less than any of the px, | |
3767 | * the returned y value is equal to the py for the lowest px. | |
3768 | * If the specified x value is greater than any of the px, | |
3769 | * the returned y value is equal to the py for the highest px. | |
3770 | */ | |
3771 | static int ar9003_hw_power_interpolate(int32_t x, | |
3772 | int32_t *px, int32_t *py, u_int16_t np) | |
3773 | { | |
3774 | int ip = 0; | |
3775 | int lx = 0, ly = 0, lhave = 0; | |
3776 | int hx = 0, hy = 0, hhave = 0; | |
3777 | int dx = 0; | |
3778 | int y = 0; | |
3779 | ||
3780 | lhave = 0; | |
3781 | hhave = 0; | |
3782 | ||
3783 | /* identify best lower and higher x calibration measurement */ | |
3784 | for (ip = 0; ip < np; ip++) { | |
3785 | dx = x - px[ip]; | |
3786 | ||
3787 | /* this measurement is higher than our desired x */ | |
3788 | if (dx <= 0) { | |
3789 | if (!hhave || dx > (x - hx)) { | |
3790 | /* new best higher x measurement */ | |
3791 | hx = px[ip]; | |
3792 | hy = py[ip]; | |
3793 | hhave = 1; | |
3794 | } | |
3795 | } | |
3796 | /* this measurement is lower than our desired x */ | |
3797 | if (dx >= 0) { | |
3798 | if (!lhave || dx < (x - lx)) { | |
3799 | /* new best lower x measurement */ | |
3800 | lx = px[ip]; | |
3801 | ly = py[ip]; | |
3802 | lhave = 1; | |
3803 | } | |
3804 | } | |
3805 | } | |
3806 | ||
3807 | /* the low x is good */ | |
3808 | if (lhave) { | |
3809 | /* so is the high x */ | |
3810 | if (hhave) { | |
3811 | /* they're the same, so just pick one */ | |
3812 | if (hx == lx) | |
3813 | y = ly; | |
3814 | else /* interpolate */ | |
bc206802 | 3815 | y = interpolate(x, lx, hx, ly, hy); |
15c9ee7a SB |
3816 | } else /* only low is good, use it */ |
3817 | y = ly; | |
3818 | } else if (hhave) /* only high is good, use it */ | |
3819 | y = hy; | |
3820 | else /* nothing is good,this should never happen unless np=0, ???? */ | |
3821 | y = -(1 << 30); | |
3822 | return y; | |
3823 | } | |
3824 | ||
3825 | static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah, | |
3826 | u16 rateIndex, u16 freq, bool is2GHz) | |
3827 | { | |
3828 | u16 numPiers, i; | |
3829 | s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS]; | |
3830 | s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS]; | |
3831 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3832 | struct cal_tgt_pow_legacy *pEepromTargetPwr; | |
3833 | u8 *pFreqBin; | |
3834 | ||
3835 | if (is2GHz) { | |
d10baf99 | 3836 | numPiers = AR9300_NUM_2G_20_TARGET_POWERS; |
15c9ee7a SB |
3837 | pEepromTargetPwr = eep->calTargetPower2G; |
3838 | pFreqBin = eep->calTarget_freqbin_2G; | |
3839 | } else { | |
3840 | numPiers = AR9300_NUM_5G_20_TARGET_POWERS; | |
3841 | pEepromTargetPwr = eep->calTargetPower5G; | |
3842 | pFreqBin = eep->calTarget_freqbin_5G; | |
3843 | } | |
3844 | ||
3845 | /* | |
3846 | * create array of channels and targetpower from | |
3847 | * targetpower piers stored on eeprom | |
3848 | */ | |
3849 | for (i = 0; i < numPiers; i++) { | |
3850 | freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz); | |
3851 | targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; | |
3852 | } | |
3853 | ||
3854 | /* interpolate to get target power for given frequency */ | |
3855 | return (u8) ar9003_hw_power_interpolate((s32) freq, | |
3856 | freqArray, | |
3857 | targetPowerArray, numPiers); | |
3858 | } | |
3859 | ||
3860 | static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, | |
3861 | u16 rateIndex, | |
3862 | u16 freq, bool is2GHz) | |
3863 | { | |
3864 | u16 numPiers, i; | |
3865 | s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS]; | |
3866 | s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS]; | |
3867 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3868 | struct cal_tgt_pow_ht *pEepromTargetPwr; | |
3869 | u8 *pFreqBin; | |
3870 | ||
3871 | if (is2GHz) { | |
d10baf99 | 3872 | numPiers = AR9300_NUM_2G_20_TARGET_POWERS; |
15c9ee7a SB |
3873 | pEepromTargetPwr = eep->calTargetPower2GHT20; |
3874 | pFreqBin = eep->calTarget_freqbin_2GHT20; | |
3875 | } else { | |
3876 | numPiers = AR9300_NUM_5G_20_TARGET_POWERS; | |
3877 | pEepromTargetPwr = eep->calTargetPower5GHT20; | |
3878 | pFreqBin = eep->calTarget_freqbin_5GHT20; | |
3879 | } | |
3880 | ||
3881 | /* | |
3882 | * create array of channels and targetpower | |
3883 | * from targetpower piers stored on eeprom | |
3884 | */ | |
3885 | for (i = 0; i < numPiers; i++) { | |
3886 | freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz); | |
3887 | targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; | |
3888 | } | |
3889 | ||
3890 | /* interpolate to get target power for given frequency */ | |
3891 | return (u8) ar9003_hw_power_interpolate((s32) freq, | |
3892 | freqArray, | |
3893 | targetPowerArray, numPiers); | |
3894 | } | |
3895 | ||
3896 | static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, | |
3897 | u16 rateIndex, | |
3898 | u16 freq, bool is2GHz) | |
3899 | { | |
3900 | u16 numPiers, i; | |
3901 | s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS]; | |
3902 | s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS]; | |
3903 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3904 | struct cal_tgt_pow_ht *pEepromTargetPwr; | |
3905 | u8 *pFreqBin; | |
3906 | ||
3907 | if (is2GHz) { | |
3908 | numPiers = AR9300_NUM_2G_40_TARGET_POWERS; | |
3909 | pEepromTargetPwr = eep->calTargetPower2GHT40; | |
3910 | pFreqBin = eep->calTarget_freqbin_2GHT40; | |
3911 | } else { | |
3912 | numPiers = AR9300_NUM_5G_40_TARGET_POWERS; | |
3913 | pEepromTargetPwr = eep->calTargetPower5GHT40; | |
3914 | pFreqBin = eep->calTarget_freqbin_5GHT40; | |
3915 | } | |
3916 | ||
3917 | /* | |
3918 | * create array of channels and targetpower from | |
3919 | * targetpower piers stored on eeprom | |
3920 | */ | |
3921 | for (i = 0; i < numPiers; i++) { | |
3922 | freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz); | |
3923 | targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; | |
3924 | } | |
3925 | ||
3926 | /* interpolate to get target power for given frequency */ | |
3927 | return (u8) ar9003_hw_power_interpolate((s32) freq, | |
3928 | freqArray, | |
3929 | targetPowerArray, numPiers); | |
3930 | } | |
3931 | ||
3932 | static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah, | |
3933 | u16 rateIndex, u16 freq) | |
3934 | { | |
3935 | u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i; | |
3936 | s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS]; | |
3937 | s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS]; | |
3938 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3939 | struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck; | |
3940 | u8 *pFreqBin = eep->calTarget_freqbin_Cck; | |
3941 | ||
3942 | /* | |
3943 | * create array of channels and targetpower from | |
3944 | * targetpower piers stored on eeprom | |
3945 | */ | |
3946 | for (i = 0; i < numPiers; i++) { | |
3947 | freqArray[i] = FBIN2FREQ(pFreqBin[i], 1); | |
3948 | targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; | |
3949 | } | |
3950 | ||
3951 | /* interpolate to get target power for given frequency */ | |
3952 | return (u8) ar9003_hw_power_interpolate((s32) freq, | |
3953 | freqArray, | |
3954 | targetPowerArray, numPiers); | |
3955 | } | |
3956 | ||
3957 | /* Set tx power registers to array of values passed in */ | |
3958 | static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray) | |
3959 | { | |
3960 | #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) | |
3961 | /* make sure forced gain is not set */ | |
4a4fdf2e | 3962 | REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0); |
15c9ee7a SB |
3963 | |
3964 | /* Write the OFDM power per rate set */ | |
3965 | ||
3966 | /* 6 (LSB), 9, 12, 18 (MSB) */ | |
4a4fdf2e | 3967 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0), |
15c9ee7a SB |
3968 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) | |
3969 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) | | |
3970 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) | | |
3971 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0)); | |
3972 | ||
3973 | /* 24 (LSB), 36, 48, 54 (MSB) */ | |
4a4fdf2e | 3974 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1), |
15c9ee7a SB |
3975 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) | |
3976 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) | | |
3977 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) | | |
3978 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0)); | |
3979 | ||
3980 | /* Write the CCK power per rate set */ | |
3981 | ||
3982 | /* 1L (LSB), reserved, 2L, 2S (MSB) */ | |
4a4fdf2e | 3983 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2), |
15c9ee7a SB |
3984 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) | |
3985 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) | | |
3986 | /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */ | |
3987 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)); | |
3988 | ||
3989 | /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ | |
4a4fdf2e | 3990 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3), |
15c9ee7a SB |
3991 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) | |
3992 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) | | |
3993 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) | | |
3994 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0) | |
3995 | ); | |
3996 | ||
3997 | /* Write the HT20 power per rate set */ | |
3998 | ||
3999 | /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ | |
4a4fdf2e | 4000 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4), |
15c9ee7a SB |
4001 | POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) | |
4002 | POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) | | |
4003 | POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) | | |
4004 | POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0) | |
4005 | ); | |
4006 | ||
4007 | /* 6 (LSB), 7, 12, 13 (MSB) */ | |
4a4fdf2e | 4008 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5), |
15c9ee7a SB |
4009 | POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) | |
4010 | POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) | | |
4011 | POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) | | |
4012 | POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0) | |
4013 | ); | |
4014 | ||
4015 | /* 14 (LSB), 15, 20, 21 */ | |
4a4fdf2e | 4016 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9), |
15c9ee7a SB |
4017 | POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) | |
4018 | POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) | | |
4019 | POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) | | |
4020 | POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0) | |
4021 | ); | |
4022 | ||
4023 | /* Mixed HT20 and HT40 rates */ | |
4024 | ||
4025 | /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ | |
4a4fdf2e | 4026 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10), |
15c9ee7a SB |
4027 | POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) | |
4028 | POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) | | |
4029 | POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) | | |
4030 | POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0) | |
4031 | ); | |
4032 | ||
4033 | /* | |
4034 | * Write the HT40 power per rate set | |
4035 | * correct PAR difference between HT40 and HT20/LEGACY | |
4036 | * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) | |
4037 | */ | |
4a4fdf2e | 4038 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6), |
15c9ee7a SB |
4039 | POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) | |
4040 | POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) | | |
4041 | POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) | | |
4042 | POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0) | |
4043 | ); | |
4044 | ||
4045 | /* 6 (LSB), 7, 12, 13 (MSB) */ | |
4a4fdf2e | 4046 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7), |
15c9ee7a SB |
4047 | POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) | |
4048 | POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) | | |
4049 | POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) | | |
4050 | POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0) | |
4051 | ); | |
4052 | ||
4053 | /* 14 (LSB), 15, 20, 21 */ | |
4a4fdf2e | 4054 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11), |
15c9ee7a SB |
4055 | POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) | |
4056 | POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) | | |
4057 | POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) | | |
4058 | POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0) | |
4059 | ); | |
4060 | ||
4061 | return 0; | |
4062 | #undef POW_SM | |
4063 | } | |
4064 | ||
824b185a LR |
4065 | static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq, |
4066 | u8 *targetPowerValT2) | |
15c9ee7a | 4067 | { |
15c9ee7a SB |
4068 | /* XXX: hard code for now, need to get from eeprom struct */ |
4069 | u8 ht40PowerIncForPdadc = 0; | |
4070 | bool is2GHz = false; | |
4071 | unsigned int i = 0; | |
4072 | struct ath_common *common = ath9k_hw_common(ah); | |
4073 | ||
4074 | if (freq < 4000) | |
4075 | is2GHz = true; | |
4076 | ||
4077 | targetPowerValT2[ALL_TARGET_LEGACY_6_24] = | |
4078 | ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq, | |
4079 | is2GHz); | |
4080 | targetPowerValT2[ALL_TARGET_LEGACY_36] = | |
4081 | ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq, | |
4082 | is2GHz); | |
4083 | targetPowerValT2[ALL_TARGET_LEGACY_48] = | |
4084 | ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq, | |
4085 | is2GHz); | |
4086 | targetPowerValT2[ALL_TARGET_LEGACY_54] = | |
4087 | ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq, | |
4088 | is2GHz); | |
4089 | targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] = | |
4090 | ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L, | |
4091 | freq); | |
4092 | targetPowerValT2[ALL_TARGET_LEGACY_5S] = | |
4093 | ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq); | |
4094 | targetPowerValT2[ALL_TARGET_LEGACY_11L] = | |
4095 | ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq); | |
4096 | targetPowerValT2[ALL_TARGET_LEGACY_11S] = | |
4097 | ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq); | |
4098 | targetPowerValT2[ALL_TARGET_HT20_0_8_16] = | |
4099 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, | |
4100 | is2GHz); | |
4101 | targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] = | |
4102 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, | |
4103 | freq, is2GHz); | |
4104 | targetPowerValT2[ALL_TARGET_HT20_4] = | |
4105 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq, | |
4106 | is2GHz); | |
4107 | targetPowerValT2[ALL_TARGET_HT20_5] = | |
4108 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq, | |
4109 | is2GHz); | |
4110 | targetPowerValT2[ALL_TARGET_HT20_6] = | |
4111 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq, | |
4112 | is2GHz); | |
4113 | targetPowerValT2[ALL_TARGET_HT20_7] = | |
4114 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq, | |
4115 | is2GHz); | |
4116 | targetPowerValT2[ALL_TARGET_HT20_12] = | |
4117 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq, | |
4118 | is2GHz); | |
4119 | targetPowerValT2[ALL_TARGET_HT20_13] = | |
4120 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq, | |
4121 | is2GHz); | |
4122 | targetPowerValT2[ALL_TARGET_HT20_14] = | |
4123 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq, | |
4124 | is2GHz); | |
4125 | targetPowerValT2[ALL_TARGET_HT20_15] = | |
4126 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq, | |
4127 | is2GHz); | |
4128 | targetPowerValT2[ALL_TARGET_HT20_20] = | |
4129 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq, | |
4130 | is2GHz); | |
4131 | targetPowerValT2[ALL_TARGET_HT20_21] = | |
4132 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq, | |
4133 | is2GHz); | |
4134 | targetPowerValT2[ALL_TARGET_HT20_22] = | |
4135 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq, | |
4136 | is2GHz); | |
4137 | targetPowerValT2[ALL_TARGET_HT20_23] = | |
4138 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq, | |
4139 | is2GHz); | |
4140 | targetPowerValT2[ALL_TARGET_HT40_0_8_16] = | |
4141 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, | |
4142 | is2GHz) + ht40PowerIncForPdadc; | |
4143 | targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] = | |
4144 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, | |
4145 | freq, | |
4146 | is2GHz) + ht40PowerIncForPdadc; | |
4147 | targetPowerValT2[ALL_TARGET_HT40_4] = | |
4148 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq, | |
4149 | is2GHz) + ht40PowerIncForPdadc; | |
4150 | targetPowerValT2[ALL_TARGET_HT40_5] = | |
4151 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq, | |
4152 | is2GHz) + ht40PowerIncForPdadc; | |
4153 | targetPowerValT2[ALL_TARGET_HT40_6] = | |
4154 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq, | |
4155 | is2GHz) + ht40PowerIncForPdadc; | |
4156 | targetPowerValT2[ALL_TARGET_HT40_7] = | |
4157 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq, | |
4158 | is2GHz) + ht40PowerIncForPdadc; | |
4159 | targetPowerValT2[ALL_TARGET_HT40_12] = | |
4160 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq, | |
4161 | is2GHz) + ht40PowerIncForPdadc; | |
4162 | targetPowerValT2[ALL_TARGET_HT40_13] = | |
4163 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq, | |
4164 | is2GHz) + ht40PowerIncForPdadc; | |
4165 | targetPowerValT2[ALL_TARGET_HT40_14] = | |
4166 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq, | |
4167 | is2GHz) + ht40PowerIncForPdadc; | |
4168 | targetPowerValT2[ALL_TARGET_HT40_15] = | |
4169 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq, | |
4170 | is2GHz) + ht40PowerIncForPdadc; | |
4171 | targetPowerValT2[ALL_TARGET_HT40_20] = | |
4172 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq, | |
4173 | is2GHz) + ht40PowerIncForPdadc; | |
4174 | targetPowerValT2[ALL_TARGET_HT40_21] = | |
4175 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq, | |
4176 | is2GHz) + ht40PowerIncForPdadc; | |
4177 | targetPowerValT2[ALL_TARGET_HT40_22] = | |
4178 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq, | |
4179 | is2GHz) + ht40PowerIncForPdadc; | |
4180 | targetPowerValT2[ALL_TARGET_HT40_23] = | |
4181 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq, | |
4182 | is2GHz) + ht40PowerIncForPdadc; | |
4183 | ||
a1cbc7a8 | 4184 | for (i = 0; i < ar9300RateSize; i++) { |
226afe68 JP |
4185 | ath_dbg(common, ATH_DBG_EEPROM, |
4186 | "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]); | |
15c9ee7a | 4187 | } |
15c9ee7a SB |
4188 | } |
4189 | ||
4190 | static int ar9003_hw_cal_pier_get(struct ath_hw *ah, | |
4191 | int mode, | |
4192 | int ipier, | |
4193 | int ichain, | |
4194 | int *pfrequency, | |
4195 | int *pcorrection, | |
4196 | int *ptemperature, int *pvoltage) | |
4197 | { | |
4198 | u8 *pCalPier; | |
4199 | struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct; | |
4200 | int is2GHz; | |
4201 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
4202 | struct ath_common *common = ath9k_hw_common(ah); | |
4203 | ||
4204 | if (ichain >= AR9300_MAX_CHAINS) { | |
226afe68 JP |
4205 | ath_dbg(common, ATH_DBG_EEPROM, |
4206 | "Invalid chain index, must be less than %d\n", | |
4207 | AR9300_MAX_CHAINS); | |
15c9ee7a SB |
4208 | return -1; |
4209 | } | |
4210 | ||
4211 | if (mode) { /* 5GHz */ | |
4212 | if (ipier >= AR9300_NUM_5G_CAL_PIERS) { | |
226afe68 JP |
4213 | ath_dbg(common, ATH_DBG_EEPROM, |
4214 | "Invalid 5GHz cal pier index, must be less than %d\n", | |
4215 | AR9300_NUM_5G_CAL_PIERS); | |
15c9ee7a SB |
4216 | return -1; |
4217 | } | |
4218 | pCalPier = &(eep->calFreqPier5G[ipier]); | |
4219 | pCalPierStruct = &(eep->calPierData5G[ichain][ipier]); | |
4220 | is2GHz = 0; | |
4221 | } else { | |
4222 | if (ipier >= AR9300_NUM_2G_CAL_PIERS) { | |
226afe68 JP |
4223 | ath_dbg(common, ATH_DBG_EEPROM, |
4224 | "Invalid 2GHz cal pier index, must be less than %d\n", | |
4225 | AR9300_NUM_2G_CAL_PIERS); | |
15c9ee7a SB |
4226 | return -1; |
4227 | } | |
4228 | ||
4229 | pCalPier = &(eep->calFreqPier2G[ipier]); | |
4230 | pCalPierStruct = &(eep->calPierData2G[ichain][ipier]); | |
4231 | is2GHz = 1; | |
4232 | } | |
4233 | ||
4234 | *pfrequency = FBIN2FREQ(*pCalPier, is2GHz); | |
4235 | *pcorrection = pCalPierStruct->refPower; | |
4236 | *ptemperature = pCalPierStruct->tempMeas; | |
4237 | *pvoltage = pCalPierStruct->voltMeas; | |
4238 | ||
4239 | return 0; | |
4240 | } | |
4241 | ||
4242 | static int ar9003_hw_power_control_override(struct ath_hw *ah, | |
4243 | int frequency, | |
4244 | int *correction, | |
4245 | int *voltage, int *temperature) | |
4246 | { | |
4247 | int tempSlope = 0; | |
4248 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
15cbbc44 | 4249 | int f[3], t[3]; |
15c9ee7a SB |
4250 | |
4251 | REG_RMW(ah, AR_PHY_TPC_11_B0, | |
4252 | (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), | |
4253 | AR_PHY_TPC_OLPC_GAIN_DELTA); | |
5f139eba VT |
4254 | if (ah->caps.tx_chainmask & BIT(1)) |
4255 | REG_RMW(ah, AR_PHY_TPC_11_B1, | |
4256 | (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), | |
4257 | AR_PHY_TPC_OLPC_GAIN_DELTA); | |
4258 | if (ah->caps.tx_chainmask & BIT(2)) | |
4259 | REG_RMW(ah, AR_PHY_TPC_11_B2, | |
4260 | (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), | |
4261 | AR_PHY_TPC_OLPC_GAIN_DELTA); | |
15c9ee7a SB |
4262 | |
4263 | /* enable open loop power control on chip */ | |
4264 | REG_RMW(ah, AR_PHY_TPC_6_B0, | |
4265 | (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), | |
4266 | AR_PHY_TPC_6_ERROR_EST_MODE); | |
5f139eba VT |
4267 | if (ah->caps.tx_chainmask & BIT(1)) |
4268 | REG_RMW(ah, AR_PHY_TPC_6_B1, | |
4269 | (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), | |
4270 | AR_PHY_TPC_6_ERROR_EST_MODE); | |
4271 | if (ah->caps.tx_chainmask & BIT(2)) | |
4272 | REG_RMW(ah, AR_PHY_TPC_6_B2, | |
4273 | (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), | |
4274 | AR_PHY_TPC_6_ERROR_EST_MODE); | |
15c9ee7a SB |
4275 | |
4276 | /* | |
4277 | * enable temperature compensation | |
4278 | * Need to use register names | |
4279 | */ | |
4280 | if (frequency < 4000) | |
4281 | tempSlope = eep->modalHeader2G.tempSlope; | |
15cbbc44 VT |
4282 | else if (eep->base_ext2.tempSlopeLow != 0) { |
4283 | t[0] = eep->base_ext2.tempSlopeLow; | |
4284 | f[0] = 5180; | |
4285 | t[1] = eep->modalHeader5G.tempSlope; | |
4286 | f[1] = 5500; | |
4287 | t[2] = eep->base_ext2.tempSlopeHigh; | |
4288 | f[2] = 5785; | |
4289 | tempSlope = ar9003_hw_power_interpolate((s32) frequency, | |
4290 | f, t, 3); | |
4291 | } else | |
15c9ee7a SB |
4292 | tempSlope = eep->modalHeader5G.tempSlope; |
4293 | ||
4294 | REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope); | |
4295 | REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE, | |
4296 | temperature[0]); | |
4297 | ||
4298 | return 0; | |
4299 | } | |
4300 | ||
4301 | /* Apply the recorded correction values. */ | |
4302 | static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency) | |
4303 | { | |
4304 | int ichain, ipier, npier; | |
4305 | int mode; | |
4306 | int lfrequency[AR9300_MAX_CHAINS], | |
4307 | lcorrection[AR9300_MAX_CHAINS], | |
4308 | ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS]; | |
4309 | int hfrequency[AR9300_MAX_CHAINS], | |
4310 | hcorrection[AR9300_MAX_CHAINS], | |
4311 | htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS]; | |
4312 | int fdiff; | |
4313 | int correction[AR9300_MAX_CHAINS], | |
4314 | voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS]; | |
4315 | int pfrequency, pcorrection, ptemperature, pvoltage; | |
4316 | struct ath_common *common = ath9k_hw_common(ah); | |
4317 | ||
4318 | mode = (frequency >= 4000); | |
4319 | if (mode) | |
4320 | npier = AR9300_NUM_5G_CAL_PIERS; | |
4321 | else | |
4322 | npier = AR9300_NUM_2G_CAL_PIERS; | |
4323 | ||
4324 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { | |
4325 | lfrequency[ichain] = 0; | |
4326 | hfrequency[ichain] = 100000; | |
4327 | } | |
4328 | /* identify best lower and higher frequency calibration measurement */ | |
4329 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { | |
4330 | for (ipier = 0; ipier < npier; ipier++) { | |
4331 | if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain, | |
4332 | &pfrequency, &pcorrection, | |
4333 | &ptemperature, &pvoltage)) { | |
4334 | fdiff = frequency - pfrequency; | |
4335 | ||
4336 | /* | |
4337 | * this measurement is higher than | |
4338 | * our desired frequency | |
4339 | */ | |
4340 | if (fdiff <= 0) { | |
4341 | if (hfrequency[ichain] <= 0 || | |
4342 | hfrequency[ichain] >= 100000 || | |
4343 | fdiff > | |
4344 | (frequency - hfrequency[ichain])) { | |
4345 | /* | |
4346 | * new best higher | |
4347 | * frequency measurement | |
4348 | */ | |
4349 | hfrequency[ichain] = pfrequency; | |
4350 | hcorrection[ichain] = | |
4351 | pcorrection; | |
4352 | htemperature[ichain] = | |
4353 | ptemperature; | |
4354 | hvoltage[ichain] = pvoltage; | |
4355 | } | |
4356 | } | |
4357 | if (fdiff >= 0) { | |
4358 | if (lfrequency[ichain] <= 0 | |
4359 | || fdiff < | |
4360 | (frequency - lfrequency[ichain])) { | |
4361 | /* | |
4362 | * new best lower | |
4363 | * frequency measurement | |
4364 | */ | |
4365 | lfrequency[ichain] = pfrequency; | |
4366 | lcorrection[ichain] = | |
4367 | pcorrection; | |
4368 | ltemperature[ichain] = | |
4369 | ptemperature; | |
4370 | lvoltage[ichain] = pvoltage; | |
4371 | } | |
4372 | } | |
4373 | } | |
4374 | } | |
4375 | } | |
4376 | ||
4377 | /* interpolate */ | |
4378 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { | |
226afe68 JP |
4379 | ath_dbg(common, ATH_DBG_EEPROM, |
4380 | "ch=%d f=%d low=%d %d h=%d %d\n", | |
4381 | ichain, frequency, lfrequency[ichain], | |
4382 | lcorrection[ichain], hfrequency[ichain], | |
4383 | hcorrection[ichain]); | |
15c9ee7a SB |
4384 | /* they're the same, so just pick one */ |
4385 | if (hfrequency[ichain] == lfrequency[ichain]) { | |
4386 | correction[ichain] = lcorrection[ichain]; | |
4387 | voltage[ichain] = lvoltage[ichain]; | |
4388 | temperature[ichain] = ltemperature[ichain]; | |
4389 | } | |
4390 | /* the low frequency is good */ | |
4391 | else if (frequency - lfrequency[ichain] < 1000) { | |
4392 | /* so is the high frequency, interpolate */ | |
4393 | if (hfrequency[ichain] - frequency < 1000) { | |
4394 | ||
bc206802 VT |
4395 | correction[ichain] = interpolate(frequency, |
4396 | lfrequency[ichain], | |
4397 | hfrequency[ichain], | |
4398 | lcorrection[ichain], | |
4399 | hcorrection[ichain]); | |
4400 | ||
4401 | temperature[ichain] = interpolate(frequency, | |
4402 | lfrequency[ichain], | |
4403 | hfrequency[ichain], | |
4404 | ltemperature[ichain], | |
4405 | htemperature[ichain]); | |
4406 | ||
4407 | voltage[ichain] = interpolate(frequency, | |
4408 | lfrequency[ichain], | |
4409 | hfrequency[ichain], | |
4410 | lvoltage[ichain], | |
4411 | hvoltage[ichain]); | |
15c9ee7a SB |
4412 | } |
4413 | /* only low is good, use it */ | |
4414 | else { | |
4415 | correction[ichain] = lcorrection[ichain]; | |
4416 | temperature[ichain] = ltemperature[ichain]; | |
4417 | voltage[ichain] = lvoltage[ichain]; | |
4418 | } | |
4419 | } | |
4420 | /* only high is good, use it */ | |
4421 | else if (hfrequency[ichain] - frequency < 1000) { | |
4422 | correction[ichain] = hcorrection[ichain]; | |
4423 | temperature[ichain] = htemperature[ichain]; | |
4424 | voltage[ichain] = hvoltage[ichain]; | |
4425 | } else { /* nothing is good, presume 0???? */ | |
4426 | correction[ichain] = 0; | |
4427 | temperature[ichain] = 0; | |
4428 | voltage[ichain] = 0; | |
4429 | } | |
4430 | } | |
4431 | ||
4432 | ar9003_hw_power_control_override(ah, frequency, correction, voltage, | |
4433 | temperature); | |
4434 | ||
226afe68 JP |
4435 | ath_dbg(common, ATH_DBG_EEPROM, |
4436 | "for frequency=%d, calibration correction = %d %d %d\n", | |
4437 | frequency, correction[0], correction[1], correction[2]); | |
15c9ee7a SB |
4438 | |
4439 | return 0; | |
4440 | } | |
4441 | ||
824b185a LR |
4442 | static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep, |
4443 | int idx, | |
4444 | int edge, | |
4445 | bool is2GHz) | |
4446 | { | |
4447 | struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; | |
4448 | struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; | |
4449 | ||
4450 | if (is2GHz) | |
e702ba18 | 4451 | return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]); |
824b185a | 4452 | else |
e702ba18 | 4453 | return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]); |
824b185a LR |
4454 | } |
4455 | ||
4456 | static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, | |
4457 | int idx, | |
4458 | unsigned int edge, | |
4459 | u16 freq, | |
4460 | bool is2GHz) | |
4461 | { | |
4462 | struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; | |
4463 | struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; | |
4464 | ||
4465 | u8 *ctl_freqbin = is2GHz ? | |
4466 | &eep->ctl_freqbin_2G[idx][0] : | |
4467 | &eep->ctl_freqbin_5G[idx][0]; | |
4468 | ||
4469 | if (is2GHz) { | |
4470 | if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq && | |
e702ba18 FF |
4471 | CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1])) |
4472 | return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]); | |
824b185a LR |
4473 | } else { |
4474 | if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq && | |
e702ba18 FF |
4475 | CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1])) |
4476 | return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]); | |
824b185a LR |
4477 | } |
4478 | ||
4ddfcd7d | 4479 | return MAX_RATE_POWER; |
824b185a LR |
4480 | } |
4481 | ||
4482 | /* | |
4483 | * Find the maximum conformance test limit for the given channel and CTL info | |
4484 | */ | |
4485 | static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, | |
4486 | u16 freq, int idx, bool is2GHz) | |
4487 | { | |
4ddfcd7d | 4488 | u16 twiceMaxEdgePower = MAX_RATE_POWER; |
824b185a LR |
4489 | u8 *ctl_freqbin = is2GHz ? |
4490 | &eep->ctl_freqbin_2G[idx][0] : | |
4491 | &eep->ctl_freqbin_5G[idx][0]; | |
4492 | u16 num_edges = is2GHz ? | |
4493 | AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G; | |
4494 | unsigned int edge; | |
4495 | ||
4496 | /* Get the edge power */ | |
4497 | for (edge = 0; | |
4ddfcd7d | 4498 | (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED); |
824b185a LR |
4499 | edge++) { |
4500 | /* | |
4501 | * If there's an exact channel match or an inband flag set | |
4502 | * on the lower channel use the given rdEdgePower | |
4503 | */ | |
4504 | if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) { | |
4505 | twiceMaxEdgePower = | |
4506 | ar9003_hw_get_direct_edge_power(eep, idx, | |
4507 | edge, is2GHz); | |
4508 | break; | |
4509 | } else if ((edge > 0) && | |
4510 | (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge], | |
4511 | is2GHz))) { | |
4512 | twiceMaxEdgePower = | |
4513 | ar9003_hw_get_indirect_edge_power(eep, idx, | |
4514 | edge, freq, | |
4515 | is2GHz); | |
4516 | /* | |
4517 | * Leave loop - no more affecting edges possible in | |
4518 | * this monotonic increasing list | |
4519 | */ | |
4520 | break; | |
4521 | } | |
4522 | } | |
4523 | return twiceMaxEdgePower; | |
4524 | } | |
4525 | ||
4526 | static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, | |
4527 | struct ath9k_channel *chan, | |
4528 | u8 *pPwrArray, u16 cfgCtl, | |
4529 | u8 twiceAntennaReduction, | |
4530 | u8 twiceMaxRegulatoryPower, | |
4531 | u16 powerLimit) | |
4532 | { | |
4533 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); | |
4534 | struct ath_common *common = ath9k_hw_common(ah); | |
4535 | struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; | |
4ddfcd7d | 4536 | u16 twiceMaxEdgePower = MAX_RATE_POWER; |
824b185a | 4537 | static const u16 tpScaleReductionTable[5] = { |
4ddfcd7d | 4538 | 0, 3, 6, 9, MAX_RATE_POWER |
824b185a LR |
4539 | }; |
4540 | int i; | |
4541 | int16_t twiceLargestAntenna; | |
4542 | u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; | |
07b2fa5a | 4543 | static const u16 ctlModesFor11a[] = { |
824b185a LR |
4544 | CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 |
4545 | }; | |
07b2fa5a | 4546 | static const u16 ctlModesFor11g[] = { |
824b185a LR |
4547 | CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, |
4548 | CTL_11G_EXT, CTL_2GHT40 | |
4549 | }; | |
07b2fa5a JP |
4550 | u16 numCtlModes; |
4551 | const u16 *pCtlMode; | |
4552 | u16 ctlMode, freq; | |
824b185a LR |
4553 | struct chan_centers centers; |
4554 | u8 *ctlIndex; | |
4555 | u8 ctlNum; | |
4556 | u16 twiceMinEdgePower; | |
4557 | bool is2ghz = IS_CHAN_2GHZ(chan); | |
4558 | ||
4559 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
4560 | ||
4561 | /* Compute TxPower reduction due to Antenna Gain */ | |
4562 | if (is2ghz) | |
4563 | twiceLargestAntenna = pEepData->modalHeader2G.antennaGain; | |
4564 | else | |
4565 | twiceLargestAntenna = pEepData->modalHeader5G.antennaGain; | |
4566 | ||
4567 | twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) - | |
4568 | twiceLargestAntenna, 0); | |
4569 | ||
4570 | /* | |
4571 | * scaledPower is the minimum of the user input power level | |
4572 | * and the regulatory allowed power level | |
4573 | */ | |
4574 | maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; | |
4575 | ||
4576 | if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) { | |
4577 | maxRegAllowedPower -= | |
4578 | (tpScaleReductionTable[(regulatory->tp_scale)] * 2); | |
4579 | } | |
4580 | ||
4581 | scaledPower = min(powerLimit, maxRegAllowedPower); | |
4582 | ||
4583 | /* | |
4584 | * Reduce scaled Power by number of chains active to get | |
4585 | * to per chain tx power level | |
4586 | */ | |
4587 | switch (ar5416_get_ntxchains(ah->txchainmask)) { | |
4588 | case 1: | |
4589 | break; | |
4590 | case 2: | |
4591 | scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; | |
4592 | break; | |
4593 | case 3: | |
4594 | scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; | |
4595 | break; | |
4596 | } | |
4597 | ||
4598 | scaledPower = max((u16)0, scaledPower); | |
4599 | ||
4600 | /* | |
4601 | * Get target powers from EEPROM - our baseline for TX Power | |
4602 | */ | |
4603 | if (is2ghz) { | |
4604 | /* Setup for CTL modes */ | |
4605 | /* CTL_11B, CTL_11G, CTL_2GHT20 */ | |
4606 | numCtlModes = | |
4607 | ARRAY_SIZE(ctlModesFor11g) - | |
4608 | SUB_NUM_CTL_MODES_AT_2G_40; | |
4609 | pCtlMode = ctlModesFor11g; | |
4610 | if (IS_CHAN_HT40(chan)) | |
4611 | /* All 2G CTL's */ | |
4612 | numCtlModes = ARRAY_SIZE(ctlModesFor11g); | |
4613 | } else { | |
4614 | /* Setup for CTL modes */ | |
4615 | /* CTL_11A, CTL_5GHT20 */ | |
4616 | numCtlModes = ARRAY_SIZE(ctlModesFor11a) - | |
4617 | SUB_NUM_CTL_MODES_AT_5G_40; | |
4618 | pCtlMode = ctlModesFor11a; | |
4619 | if (IS_CHAN_HT40(chan)) | |
4620 | /* All 5G CTL's */ | |
4621 | numCtlModes = ARRAY_SIZE(ctlModesFor11a); | |
4622 | } | |
4623 | ||
4624 | /* | |
4625 | * For MIMO, need to apply regulatory caps individually across | |
4626 | * dynamically running modes: CCK, OFDM, HT20, HT40 | |
4627 | * | |
4628 | * The outer loop walks through each possible applicable runtime mode. | |
4629 | * The inner loop walks through each ctlIndex entry in EEPROM. | |
4630 | * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. | |
4631 | */ | |
4632 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { | |
4633 | bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || | |
4634 | (pCtlMode[ctlMode] == CTL_2GHT40); | |
4635 | if (isHt40CtlMode) | |
4636 | freq = centers.synth_center; | |
4637 | else if (pCtlMode[ctlMode] & EXT_ADDITIVE) | |
4638 | freq = centers.ext_center; | |
4639 | else | |
4640 | freq = centers.ctl_center; | |
4641 | ||
226afe68 JP |
4642 | ath_dbg(common, ATH_DBG_REGULATORY, |
4643 | "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n", | |
4644 | ctlMode, numCtlModes, isHt40CtlMode, | |
4645 | (pCtlMode[ctlMode] & EXT_ADDITIVE)); | |
824b185a LR |
4646 | |
4647 | /* walk through each CTL index stored in EEPROM */ | |
4648 | if (is2ghz) { | |
4649 | ctlIndex = pEepData->ctlIndex_2G; | |
4650 | ctlNum = AR9300_NUM_CTLS_2G; | |
4651 | } else { | |
4652 | ctlIndex = pEepData->ctlIndex_5G; | |
4653 | ctlNum = AR9300_NUM_CTLS_5G; | |
4654 | } | |
4655 | ||
4656 | for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) { | |
226afe68 JP |
4657 | ath_dbg(common, ATH_DBG_REGULATORY, |
4658 | "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n", | |
4659 | i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i], | |
4660 | chan->channel); | |
824b185a LR |
4661 | |
4662 | /* | |
4663 | * compare test group from regulatory | |
4664 | * channel list with test mode from pCtlMode | |
4665 | * list | |
4666 | */ | |
4667 | if ((((cfgCtl & ~CTL_MODE_M) | | |
4668 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
4669 | ctlIndex[i]) || | |
4670 | (((cfgCtl & ~CTL_MODE_M) | | |
4671 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
4672 | ((ctlIndex[i] & CTL_MODE_M) | | |
4673 | SD_NO_CTL))) { | |
4674 | twiceMinEdgePower = | |
4675 | ar9003_hw_get_max_edge_power(pEepData, | |
4676 | freq, i, | |
4677 | is2ghz); | |
4678 | ||
4679 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) | |
4680 | /* | |
4681 | * Find the minimum of all CTL | |
4682 | * edge powers that apply to | |
4683 | * this channel | |
4684 | */ | |
4685 | twiceMaxEdgePower = | |
4686 | min(twiceMaxEdgePower, | |
4687 | twiceMinEdgePower); | |
4688 | else { | |
4689 | /* specific */ | |
4690 | twiceMaxEdgePower = | |
4691 | twiceMinEdgePower; | |
4692 | break; | |
4693 | } | |
4694 | } | |
4695 | } | |
4696 | ||
4697 | minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); | |
4698 | ||
226afe68 JP |
4699 | ath_dbg(common, ATH_DBG_REGULATORY, |
4700 | "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n", | |
4701 | ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, | |
4702 | scaledPower, minCtlPower); | |
824b185a LR |
4703 | |
4704 | /* Apply ctl mode to correct target power set */ | |
4705 | switch (pCtlMode[ctlMode]) { | |
4706 | case CTL_11B: | |
4707 | for (i = ALL_TARGET_LEGACY_1L_5L; | |
4708 | i <= ALL_TARGET_LEGACY_11S; i++) | |
4709 | pPwrArray[i] = | |
4710 | (u8)min((u16)pPwrArray[i], | |
4711 | minCtlPower); | |
4712 | break; | |
4713 | case CTL_11A: | |
4714 | case CTL_11G: | |
4715 | for (i = ALL_TARGET_LEGACY_6_24; | |
4716 | i <= ALL_TARGET_LEGACY_54; i++) | |
4717 | pPwrArray[i] = | |
4718 | (u8)min((u16)pPwrArray[i], | |
4719 | minCtlPower); | |
4720 | break; | |
4721 | case CTL_5GHT20: | |
4722 | case CTL_2GHT20: | |
4723 | for (i = ALL_TARGET_HT20_0_8_16; | |
4724 | i <= ALL_TARGET_HT20_21; i++) | |
4725 | pPwrArray[i] = | |
4726 | (u8)min((u16)pPwrArray[i], | |
4727 | minCtlPower); | |
4728 | pPwrArray[ALL_TARGET_HT20_22] = | |
4729 | (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22], | |
4730 | minCtlPower); | |
4731 | pPwrArray[ALL_TARGET_HT20_23] = | |
4732 | (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23], | |
4733 | minCtlPower); | |
4734 | break; | |
4735 | case CTL_5GHT40: | |
4736 | case CTL_2GHT40: | |
4737 | for (i = ALL_TARGET_HT40_0_8_16; | |
4738 | i <= ALL_TARGET_HT40_23; i++) | |
4739 | pPwrArray[i] = | |
4740 | (u8)min((u16)pPwrArray[i], | |
4741 | minCtlPower); | |
4742 | break; | |
4743 | default: | |
4744 | break; | |
4745 | } | |
4746 | } /* end ctl mode checking */ | |
4747 | } | |
4748 | ||
45ef6a0b VT |
4749 | static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx) |
4750 | { | |
4751 | u8 mod_idx = mcs_idx % 8; | |
4752 | ||
4753 | if (mod_idx <= 3) | |
4754 | return mod_idx ? (base_pwridx + 1) : base_pwridx; | |
4755 | else | |
4756 | return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2; | |
4757 | } | |
4758 | ||
15c9ee7a SB |
4759 | static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, |
4760 | struct ath9k_channel *chan, u16 cfgCtl, | |
4761 | u8 twiceAntennaReduction, | |
4762 | u8 twiceMaxRegulatoryPower, | |
de40f316 | 4763 | u8 powerLimit, bool test) |
15c9ee7a | 4764 | { |
6b7b6cf5 | 4765 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
824b185a | 4766 | struct ath_common *common = ath9k_hw_common(ah); |
7072bf62 | 4767 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
f1a8abb0 | 4768 | struct ar9300_modal_eep_header *modal_hdr; |
824b185a | 4769 | u8 targetPowerValT2[ar9300RateSize]; |
7072bf62 VT |
4770 | u8 target_power_val_t2_eep[ar9300RateSize]; |
4771 | unsigned int i = 0, paprd_scale_factor = 0; | |
45ef6a0b | 4772 | u8 pwr_idx, min_pwridx = 0; |
824b185a LR |
4773 | |
4774 | ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2); | |
7072bf62 VT |
4775 | |
4776 | if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) { | |
4777 | if (IS_CHAN_2GHZ(chan)) | |
f1a8abb0 | 4778 | modal_hdr = &eep->modalHeader2G; |
7072bf62 | 4779 | else |
f1a8abb0 FF |
4780 | modal_hdr = &eep->modalHeader5G; |
4781 | ||
4782 | ah->paprd_ratemask = | |
4783 | le32_to_cpu(modal_hdr->papdRateMaskHt20) & | |
4784 | AR9300_PAPRD_RATE_MASK; | |
4785 | ||
4786 | ah->paprd_ratemask_ht40 = | |
4787 | le32_to_cpu(modal_hdr->papdRateMaskHt40) & | |
4788 | AR9300_PAPRD_RATE_MASK; | |
7072bf62 | 4789 | |
45ef6a0b VT |
4790 | paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan); |
4791 | min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 : | |
4792 | ALL_TARGET_HT20_0_8_16; | |
4793 | ||
4794 | if (!ah->paprd_table_write_done) { | |
4795 | memcpy(target_power_val_t2_eep, targetPowerValT2, | |
4796 | sizeof(targetPowerValT2)); | |
4797 | for (i = 0; i < 24; i++) { | |
4798 | pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx); | |
4799 | if (ah->paprd_ratemask & (1 << i)) { | |
4800 | if (targetPowerValT2[pwr_idx] && | |
4801 | targetPowerValT2[pwr_idx] == | |
4802 | target_power_val_t2_eep[pwr_idx]) | |
4803 | targetPowerValT2[pwr_idx] -= | |
4804 | paprd_scale_factor; | |
4805 | } | |
4806 | } | |
4807 | } | |
7072bf62 VT |
4808 | memcpy(target_power_val_t2_eep, targetPowerValT2, |
4809 | sizeof(targetPowerValT2)); | |
4810 | } | |
4811 | ||
824b185a LR |
4812 | ar9003_hw_set_power_per_rate_table(ah, chan, |
4813 | targetPowerValT2, cfgCtl, | |
4814 | twiceAntennaReduction, | |
4815 | twiceMaxRegulatoryPower, | |
4816 | powerLimit); | |
4817 | ||
7072bf62 | 4818 | if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) { |
7072bf62 VT |
4819 | for (i = 0; i < ar9300RateSize; i++) { |
4820 | if ((ah->paprd_ratemask & (1 << i)) && | |
4821 | (abs(targetPowerValT2[i] - | |
4822 | target_power_val_t2_eep[i]) > | |
4823 | paprd_scale_factor)) { | |
4824 | ah->paprd_ratemask &= ~(1 << i); | |
4825 | ath_dbg(common, ATH_DBG_EEPROM, | |
4826 | "paprd disabled for mcs %d\n", i); | |
4827 | } | |
4828 | } | |
4829 | } | |
4830 | ||
de40f316 FF |
4831 | regulatory->max_power_level = 0; |
4832 | for (i = 0; i < ar9300RateSize; i++) { | |
4833 | if (targetPowerValT2[i] > regulatory->max_power_level) | |
4834 | regulatory->max_power_level = targetPowerValT2[i]; | |
4835 | } | |
4836 | ||
4837 | if (test) | |
4838 | return; | |
4839 | ||
4840 | for (i = 0; i < ar9300RateSize; i++) { | |
226afe68 | 4841 | ath_dbg(common, ATH_DBG_EEPROM, |
a1cbc7a8 | 4842 | "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]); |
824b185a LR |
4843 | } |
4844 | ||
824b185a LR |
4845 | /* |
4846 | * This is the TX power we send back to driver core, | |
4847 | * and it can use to pass to userspace to display our | |
4848 | * currently configured TX power setting. | |
4849 | * | |
4850 | * Since power is rate dependent, use one of the indices | |
4851 | * from the AR9300_Rates enum to select an entry from | |
4852 | * targetPowerValT2[] to report. Currently returns the | |
4853 | * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps | |
4854 | * as CCK power is less interesting (?). | |
4855 | */ | |
4856 | i = ALL_TARGET_LEGACY_6_24; /* legacy */ | |
4857 | if (IS_CHAN_HT40(chan)) | |
4858 | i = ALL_TARGET_HT40_0_8_16; /* ht40 */ | |
4859 | else if (IS_CHAN_HT20(chan)) | |
4860 | i = ALL_TARGET_HT20_0_8_16; /* ht20 */ | |
4861 | ||
4862 | ah->txpower_limit = targetPowerValT2[i]; | |
de40f316 | 4863 | regulatory->max_power_level = targetPowerValT2[i]; |
824b185a | 4864 | |
de40f316 FF |
4865 | /* Write target power array to registers */ |
4866 | ar9003_hw_tx_power_regwrite(ah, targetPowerValT2); | |
15c9ee7a | 4867 | ar9003_hw_calibration_apply(ah, chan->channel); |
1bf38661 FF |
4868 | |
4869 | if (IS_CHAN_2GHZ(chan)) { | |
4870 | if (IS_CHAN_HT40(chan)) | |
4871 | i = ALL_TARGET_HT40_0_8_16; | |
4872 | else | |
4873 | i = ALL_TARGET_HT20_0_8_16; | |
4874 | } else { | |
4875 | if (IS_CHAN_HT40(chan)) | |
4876 | i = ALL_TARGET_HT40_7; | |
4877 | else | |
4878 | i = ALL_TARGET_HT20_7; | |
4879 | } | |
4880 | ah->paprd_target_power = targetPowerValT2[i]; | |
15c9ee7a SB |
4881 | } |
4882 | ||
4883 | static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah, | |
4884 | u16 i, bool is2GHz) | |
4885 | { | |
4886 | return AR_NO_SPUR; | |
4887 | } | |
4888 | ||
c14a85da LR |
4889 | s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah) |
4890 | { | |
4891 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
4892 | ||
4893 | return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */ | |
4894 | } | |
4895 | ||
4896 | s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah) | |
4897 | { | |
4898 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
4899 | ||
4900 | return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */ | |
4901 | } | |
4902 | ||
272ceba8 VT |
4903 | u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz) |
4904 | { | |
4905 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
4906 | ||
4907 | if (is_2ghz) | |
4908 | return eep->modalHeader2G.spurChans; | |
4909 | else | |
4910 | return eep->modalHeader5G.spurChans; | |
4911 | } | |
4912 | ||
8698bca6 VT |
4913 | unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, |
4914 | struct ath9k_channel *chan) | |
4915 | { | |
4916 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
4917 | ||
4918 | if (IS_CHAN_2GHZ(chan)) | |
4919 | return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20), | |
4920 | AR9300_PAPRD_SCALE_1); | |
4921 | else { | |
4922 | if (chan->channel >= 5700) | |
4923 | return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20), | |
4924 | AR9300_PAPRD_SCALE_1); | |
4925 | else if (chan->channel >= 5400) | |
4926 | return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40), | |
4927 | AR9300_PAPRD_SCALE_2); | |
4928 | else | |
4929 | return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40), | |
4930 | AR9300_PAPRD_SCALE_1); | |
4931 | } | |
4932 | } | |
4933 | ||
15c9ee7a SB |
4934 | const struct eeprom_ops eep_ar9300_ops = { |
4935 | .check_eeprom = ath9k_hw_ar9300_check_eeprom, | |
4936 | .get_eeprom = ath9k_hw_ar9300_get_eeprom, | |
4937 | .fill_eeprom = ath9k_hw_ar9300_fill_eeprom, | |
4938 | .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver, | |
4939 | .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev, | |
15c9ee7a SB |
4940 | .set_board_values = ath9k_hw_ar9300_set_board_values, |
4941 | .set_addac = ath9k_hw_ar9300_set_addac, | |
4942 | .set_txpower = ath9k_hw_ar9300_set_txpower, | |
4943 | .get_spur_channel = ath9k_hw_ar9300_get_spur_channel | |
4944 | }; |