[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / ar9002_mac.c

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include "hw.h"
#include <linux/export.h>

#define AR_BufLen           0x00000fff

static void ar9002_hw_rx_enable(struct ath_hw *ah)
{
	REG_WRITE(ah, AR_CR, AR_CR_RXE);
}

static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
{
	((struct ath_desc*) ds)->ds_link = ds_link;
}

static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
{
	u32 isr = 0;
	u32 mask2 = 0;
	struct ath9k_hw_capabilities *pCap = &ah->caps;
	u32 sync_cause = 0;
	bool fatal_int = false;
	struct ath_common *common = ath9k_hw_common(ah);

	if (!AR_SREV_9100(ah)) {
		if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
			if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
			    == AR_RTC_STATUS_ON) {
				isr = REG_READ(ah, AR_ISR);
			}
		}

		sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
			AR_INTR_SYNC_DEFAULT;

		*masked = 0;

		if (!isr && !sync_cause)
			return false;
	} else {
		*masked = 0;
		isr = REG_READ(ah, AR_ISR);
	}

	if (isr) {
		if (isr & AR_ISR_BCNMISC) {
			u32 isr2;
			isr2 = REG_READ(ah, AR_ISR_S2);
			if (isr2 & AR_ISR_S2_TIM)
				mask2 |= ATH9K_INT_TIM;
			if (isr2 & AR_ISR_S2_DTIM)
				mask2 |= ATH9K_INT_DTIM;
			if (isr2 & AR_ISR_S2_DTIMSYNC)
				mask2 |= ATH9K_INT_DTIMSYNC;
			if (isr2 & (AR_ISR_S2_CABEND))
				mask2 |= ATH9K_INT_CABEND;
			if (isr2 & AR_ISR_S2_GTT)
				mask2 |= ATH9K_INT_GTT;
			if (isr2 & AR_ISR_S2_CST)
				mask2 |= ATH9K_INT_CST;
			if (isr2 & AR_ISR_S2_TSFOOR)
				mask2 |= ATH9K_INT_TSFOOR;
		}

		isr = REG_READ(ah, AR_ISR_RAC);
		if (isr == 0xffffffff) {
			*masked = 0;
			return false;
		}

		*masked = isr & ATH9K_INT_COMMON;

		if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
			   AR_ISR_RXOK | AR_ISR_RXERR))
			*masked |= ATH9K_INT_RX;

		if (isr &
		    (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
		     AR_ISR_TXEOL)) {
			u32 s0_s, s1_s;

			*masked |= ATH9K_INT_TX;

			s0_s = REG_READ(ah, AR_ISR_S0_S);
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);

			s1_s = REG_READ(ah, AR_ISR_S1_S);
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
		}

		if (isr & AR_ISR_RXORN) {
			ath_dbg(common, INTERRUPT,
				"receive FIFO overrun interrupt\n");
		}

		*masked |= mask2;
	}

	if (AR_SREV_9100(ah))
		return true;

	if (isr & AR_ISR_GENTMR) {
		u32 s5_s;

		s5_s = REG_READ(ah, AR_ISR_S5_S);
		ah->intr_gen_timer_trigger =
				MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);

		ah->intr_gen_timer_thresh =
			MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);

		if (ah->intr_gen_timer_trigger)
			*masked |= ATH9K_INT_GENTIMER;

		if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
		    !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
			*masked |= ATH9K_INT_TIM_TIMER;
	}

	if (sync_cause) {
		ath9k_debug_sync_cause(common, sync_cause);
		fatal_int =
			(sync_cause &
			 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
			? true : false;

		if (fatal_int) {
			if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
				ath_dbg(common, ANY,
					"received PCI FATAL interrupt\n");
			}
			if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
				ath_dbg(common, ANY,
					"received PCI PERR interrupt\n");
			}
			*masked |= ATH9K_INT_FATAL;
		}
		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
			ath_dbg(common, INTERRUPT,
				"AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
			REG_WRITE(ah, AR_RC, 0);
			*masked |= ATH9K_INT_FATAL;
		}
		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
			ath_dbg(common, INTERRUPT,
				"AR_INTR_SYNC_LOCAL_TIMEOUT\n");
		}

		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
	}

	return true;
}

static void
ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
{
	struct ar5416_desc *ads = AR5416DESC(ds);
	u32 ctl1, ctl6;

	ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
	ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
	ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
	ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
	ads->ds_txstatus8 = ads->ds_txstatus9 = 0;

	ACCESS_ONCE(ads->ds_link) = i->link;
	ACCESS_ONCE(ads->ds_data) = i->buf_addr[0];

	ctl1 = i->buf_len[0] | (i->is_last ? 0 : AR_TxMore);
	ctl6 = SM(i->keytype, AR_EncrType);

	if (AR_SREV_9285(ah)) {
		ads->ds_ctl8 = 0;
		ads->ds_ctl9 = 0;
		ads->ds_ctl10 = 0;
		ads->ds_ctl11 = 0;
	}

	if ((i->is_first || i->is_last) &&
	    i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) {
		ACCESS_ONCE(ads->ds_ctl2) = set11nTries(i->rates, 0)
			| set11nTries(i->rates, 1)
			| set11nTries(i->rates, 2)
			| set11nTries(i->rates, 3)
			| (i->dur_update ? AR_DurUpdateEna : 0)
			| SM(0, AR_BurstDur);

		ACCESS_ONCE(ads->ds_ctl3) = set11nRate(i->rates, 0)
			| set11nRate(i->rates, 1)
			| set11nRate(i->rates, 2)
			| set11nRate(i->rates, 3);
	} else {
		ACCESS_ONCE(ads->ds_ctl2) = 0;
		ACCESS_ONCE(ads->ds_ctl3) = 0;
	}

	if (!i->is_first) {
		ACCESS_ONCE(ads->ds_ctl0) = 0;
		ACCESS_ONCE(ads->ds_ctl1) = ctl1;
		ACCESS_ONCE(ads->ds_ctl6) = ctl6;
		return;
	}

	ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0)
		| SM(i->type, AR_FrameType)
		| (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
		| (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
		| (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);

	switch (i->aggr) {
	case AGGR_BUF_FIRST:
		ctl6 |= SM(i->aggr_len, AR_AggrLen);
		/* fall through */
	case AGGR_BUF_MIDDLE:
		ctl1 |= AR_IsAggr | AR_MoreAggr;
		ctl6 |= SM(i->ndelim, AR_PadDelim);
		break;
	case AGGR_BUF_LAST:
		ctl1 |= AR_IsAggr;
		break;
	case AGGR_BUF_NONE:
		break;
	}

	ACCESS_ONCE(ads->ds_ctl0) = (i->pkt_len & AR_FrameLen)
		| (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
		| SM(i->txpower, AR_XmitPower)
		| (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
		| (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
		| (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
		| (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
		| (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
		   (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));

	ACCESS_ONCE(ads->ds_ctl1) = ctl1;
	ACCESS_ONCE(ads->ds_ctl6) = ctl6;

	if (i->aggr == AGGR_BUF_MIDDLE || i->aggr == AGGR_BUF_LAST)
		return;

	ACCESS_ONCE(ads->ds_ctl4) = set11nPktDurRTSCTS(i->rates, 0)
		| set11nPktDurRTSCTS(i->rates, 1);

	ACCESS_ONCE(ads->ds_ctl5) = set11nPktDurRTSCTS(i->rates, 2)
		| set11nPktDurRTSCTS(i->rates, 3);

	ACCESS_ONCE(ads->ds_ctl7) = set11nRateFlags(i->rates, 0)
		| set11nRateFlags(i->rates, 1)
		| set11nRateFlags(i->rates, 2)
		| set11nRateFlags(i->rates, 3)
		| SM(i->rtscts_rate, AR_RTSCTSRate);
}

static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
				 struct ath_tx_status *ts)
{
	struct ar5416_desc *ads = AR5416DESC(ds);
	u32 status;

	status = ACCESS_ONCE(ads->ds_txstatus9);
	if ((status & AR_TxDone) == 0)
		return -EINPROGRESS;

	ts->ts_tstamp = ads->AR_SendTimestamp;
	ts->ts_status = 0;
	ts->ts_flags = 0;

	if (status & AR_TxOpExceeded)
		ts->ts_status |= ATH9K_TXERR_XTXOP;
	ts->tid = MS(status, AR_TxTid);
	ts->ts_rateindex = MS(status, AR_FinalTxIdx);
	ts->ts_seqnum = MS(status, AR_SeqNum);

	status = ACCESS_ONCE(ads->ds_txstatus0);
	ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
	ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
	ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
	if (status & AR_TxBaStatus) {
		ts->ts_flags |= ATH9K_TX_BA;
		ts->ba_low = ads->AR_BaBitmapLow;
		ts->ba_high = ads->AR_BaBitmapHigh;
	}

	status = ACCESS_ONCE(ads->ds_txstatus1);
	if (status & AR_FrmXmitOK)
		ts->ts_status |= ATH9K_TX_ACKED;
	else {
		if (status & AR_ExcessiveRetries)
			ts->ts_status |= ATH9K_TXERR_XRETRY;
		if (status & AR_Filtered)
			ts->ts_status |= ATH9K_TXERR_FILT;
		if (status & AR_FIFOUnderrun) {
			ts->ts_status |= ATH9K_TXERR_FIFO;
			ath9k_hw_updatetxtriglevel(ah, true);
		}
	}
	if (status & AR_TxTimerExpired)
		ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
	if (status & AR_DescCfgErr)
		ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
	if (status & AR_TxDataUnderrun) {
		ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
		ath9k_hw_updatetxtriglevel(ah, true);
	}
	if (status & AR_TxDelimUnderrun) {
		ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
		ath9k_hw_updatetxtriglevel(ah, true);
	}
	ts->ts_shortretry = MS(status, AR_RTSFailCnt);
	ts->ts_longretry = MS(status, AR_DataFailCnt);
	ts->ts_virtcol = MS(status, AR_VirtRetryCnt);

	status = ACCESS_ONCE(ads->ds_txstatus5);
	ts->ts_rssi = MS(status, AR_TxRSSICombined);
	ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
	ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
	ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);

	ts->evm0 = ads->AR_TxEVM0;
	ts->evm1 = ads->AR_TxEVM1;
	ts->evm2 = ads->AR_TxEVM2;

	return 0;
}

void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
			  u32 size, u32 flags)
{
	struct ar5416_desc *ads = AR5416DESC(ds);

	ads->ds_ctl1 = size & AR_BufLen;
	if (flags & ATH9K_RXDESC_INTREQ)
		ads->ds_ctl1 |= AR_RxIntrReq;

	memset(&ads->u.rx, 0, sizeof(ads->u.rx));
}
EXPORT_SYMBOL(ath9k_hw_setuprxdesc);

void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
{
	struct ath_hw_ops *ops = ath9k_hw_ops(ah);

	ops->rx_enable = ar9002_hw_rx_enable;
	ops->set_desc_link = ar9002_hw_set_desc_link;
	ops->get_isr = ar9002_hw_get_isr;
	ops->set_txdesc = ar9002_set_txdesc;
	ops->proc_txdesc = ar9002_hw_proc_txdesc;
}
Commit	Line	Data
b622a720	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
b622a720 LR	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include "hw.h"
ee40fa06	18	#include <linux/export.h>
b622a720 LR	19
	20	#define AR_BufLen 0x00000fff
	21
	22	static void ar9002_hw_rx_enable(struct ath_hw *ah)
	23	{
	24	REG_WRITE(ah, AR_CR, AR_CR_RXE);
	25	}
	26
	27	static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
	28	{
	29	((struct ath_desc*) ds)->ds_link = ds_link;
	30	}
	31
b622a720 LR	32	static bool ar9002_hw_get_isr(struct ath_hw ah, enum ath9k_int masked)
	33	{
	34	u32 isr = 0;
	35	u32 mask2 = 0;
	36	struct ath9k_hw_capabilities *pCap = &ah->caps;
	37	u32 sync_cause = 0;
	38	bool fatal_int = false;
	39	struct ath_common *common = ath9k_hw_common(ah);
	40
	41	if (!AR_SREV_9100(ah)) {
	42	if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
	43	if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
	44	== AR_RTC_STATUS_ON) {
	45	isr = REG_READ(ah, AR_ISR);
	46	}
	47	}
	48
	49	sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
	50	AR_INTR_SYNC_DEFAULT;
	51
	52	*masked = 0;
	53
	54	if (!isr && !sync_cause)
	55	return false;
	56	} else {
	57	*masked = 0;
	58	isr = REG_READ(ah, AR_ISR);
	59	}
	60
	61	if (isr) {
	62	if (isr & AR_ISR_BCNMISC) {
	63	u32 isr2;
	64	isr2 = REG_READ(ah, AR_ISR_S2);
	65	if (isr2 & AR_ISR_S2_TIM)
	66	mask2 \|= ATH9K_INT_TIM;
	67	if (isr2 & AR_ISR_S2_DTIM)
	68	mask2 \|= ATH9K_INT_DTIM;
	69	if (isr2 & AR_ISR_S2_DTIMSYNC)
	70	mask2 \|= ATH9K_INT_DTIMSYNC;
	71	if (isr2 & (AR_ISR_S2_CABEND))
	72	mask2 \|= ATH9K_INT_CABEND;
	73	if (isr2 & AR_ISR_S2_GTT)
	74	mask2 \|= ATH9K_INT_GTT;
	75	if (isr2 & AR_ISR_S2_CST)
	76	mask2 \|= ATH9K_INT_CST;
	77	if (isr2 & AR_ISR_S2_TSFOOR)
	78	mask2 \|= ATH9K_INT_TSFOOR;
	79	}
	80
	81	isr = REG_READ(ah, AR_ISR_RAC);
	82	if (isr == 0xffffffff) {
	83	*masked = 0;
	84	return false;
	85	}
	86
	87	*masked = isr & ATH9K_INT_COMMON;
	88
45684c75 FF	89	if (isr & (AR_ISR_RXMINTR \| AR_ISR_RXINTM \|
45684c75 FF	90	AR_ISR_RXOK \| AR_ISR_RXERR))
b622a720	91	*masked \|= ATH9K_INT_RX;
45684c75	92
b622a720 LR	93	if (isr &
	94	(AR_ISR_TXOK \| AR_ISR_TXDESC \| AR_ISR_TXERR \|
	95	AR_ISR_TXEOL)) {
	96	u32 s0_s, s1_s;
	97
	98	*masked \|= ATH9K_INT_TX;
	99
	100	s0_s = REG_READ(ah, AR_ISR_S0_S);
	101	ah->intr_txqs \|= MS(s0_s, AR_ISR_S0_QCU_TXOK);
	102	ah->intr_txqs \|= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
	103
	104	s1_s = REG_READ(ah, AR_ISR_S1_S);
	105	ah->intr_txqs \|= MS(s1_s, AR_ISR_S1_QCU_TXERR);
	106	ah->intr_txqs \|= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
	107	}
	108
	109	if (isr & AR_ISR_RXORN) {
d2182b69	110	ath_dbg(common, INTERRUPT,
226afe68	111	"receive FIFO overrun interrupt\n");
b622a720 LR	112	}
b622a720 LR	113
b622a720 LR	114	*masked \|= mask2;
	115	}
	116
	117	if (AR_SREV_9100(ah))
	118	return true;
	119
	120	if (isr & AR_ISR_GENTMR) {
	121	u32 s5_s;
	122
	123	s5_s = REG_READ(ah, AR_ISR_S5_S);
45684c75	124	ah->intr_gen_timer_trigger =
b622a720 LR	125	MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
b622a720 LR	126
45684c75 FF	127	ah->intr_gen_timer_thresh =
45684c75 FF	128	MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
b622a720	129
45684c75 FF	130	if (ah->intr_gen_timer_trigger)
45684c75 FF	131	*masked \|= ATH9K_INT_GENTIMER;
b622a720	132
45684c75 FF	133	if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
	134	!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
	135	*masked \|= ATH9K_INT_TIM_TIMER;
b622a720 LR	136	}
	137
	138	if (sync_cause) {
462e58f2	139	ath9k_debug_sync_cause(common, sync_cause);
b622a720 LR	140	fatal_int =
	141	(sync_cause &
	142	(AR_INTR_SYNC_HOST1_FATAL \| AR_INTR_SYNC_HOST1_PERR))
	143	? true : false;
	144
	145	if (fatal_int) {
	146	if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
d2182b69	147	ath_dbg(common, ANY,
226afe68	148	"received PCI FATAL interrupt\n");
b622a720 LR	149	}
b622a720 LR	150	if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
d2182b69	151	ath_dbg(common, ANY,
226afe68	152	"received PCI PERR interrupt\n");
b622a720 LR	153	}
	154	*masked \|= ATH9K_INT_FATAL;
	155	}
	156	if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
d2182b69	157	ath_dbg(common, INTERRUPT,
226afe68	158	"AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
b622a720 LR	159	REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
	160	REG_WRITE(ah, AR_RC, 0);
	161	*masked \|= ATH9K_INT_FATAL;
	162	}
	163	if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
d2182b69	164	ath_dbg(common, INTERRUPT,
226afe68	165	"AR_INTR_SYNC_LOCAL_TIMEOUT\n");
b622a720 LR	166	}
	167
	168	REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
	169	(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
	170	}
	171
	172	return true;
	173	}
	174
2b63a41d FF	175	static void
	176	ar9002_set_txdesc(struct ath_hw ah, void ds, struct ath_tx_info *i)
	177	{
	178	struct ar5416_desc *ads = AR5416DESC(ds);
	179	u32 ctl1, ctl6;
	180
	181	ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
	182	ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
	183	ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
	184	ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
	185	ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
	186
	187	ACCESS_ONCE(ads->ds_link) = i->link;
	188	ACCESS_ONCE(ads->ds_data) = i->buf_addr[0];
	189
	190	ctl1 = i->buf_len[0] \| (i->is_last ? 0 : AR_TxMore);
	191	ctl6 = SM(i->keytype, AR_EncrType);
	192
	193	if (AR_SREV_9285(ah)) {
	194	ads->ds_ctl8 = 0;
	195	ads->ds_ctl9 = 0;
	196	ads->ds_ctl10 = 0;
	197	ads->ds_ctl11 = 0;
	198	}
	199
	200	if ((i->is_first \|\| i->is_last) &&
	201	i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) {
	202	ACCESS_ONCE(ads->ds_ctl2) = set11nTries(i->rates, 0)
	203	\| set11nTries(i->rates, 1)
	204	\| set11nTries(i->rates, 2)
	205	\| set11nTries(i->rates, 3)
	206	\| (i->dur_update ? AR_DurUpdateEna : 0)
	207	\| SM(0, AR_BurstDur);
	208
	209	ACCESS_ONCE(ads->ds_ctl3) = set11nRate(i->rates, 0)
	210	\| set11nRate(i->rates, 1)
	211	\| set11nRate(i->rates, 2)
	212	\| set11nRate(i->rates, 3);
	213	} else {
	214	ACCESS_ONCE(ads->ds_ctl2) = 0;
	215	ACCESS_ONCE(ads->ds_ctl3) = 0;
	216	}
	217
	218	if (!i->is_first) {
	219	ACCESS_ONCE(ads->ds_ctl0) = 0;
	220	ACCESS_ONCE(ads->ds_ctl1) = ctl1;
	221	ACCESS_ONCE(ads->ds_ctl6) = ctl6;
	222	return;
	223	}
	224
	225	ctl1 \|= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0)
	226	\| SM(i->type, AR_FrameType)
	227	\| (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
	228	\| (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
	229	\| (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
	230
	231	switch (i->aggr) {
	232	case AGGR_BUF_FIRST:
	233	ctl6 \|= SM(i->aggr_len, AR_AggrLen);
	234	/* fall through */
	235	case AGGR_BUF_MIDDLE:
	236	ctl1 \|= AR_IsAggr \| AR_MoreAggr;
	237	ctl6 \|= SM(i->ndelim, AR_PadDelim);
	238	break;
239	case AGGR_BUF_LAST:
240	ctl1 \|= AR_IsAggr;
241	break;
242	case AGGR_BUF_NONE:
243	break;
244	}
245
246	ACCESS_ONCE(ads->ds_ctl0) = (i->pkt_len & AR_FrameLen)
247	\| (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
248	\| SM(i->txpower, AR_XmitPower)
249	\| (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
250	\| (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
251	\| (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
252	\| (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
253	\| (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
254	(i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));
255
256	ACCESS_ONCE(ads->ds_ctl1) = ctl1;
257	ACCESS_ONCE(ads->ds_ctl6) = ctl6;
258
259	if (i->aggr == AGGR_BUF_MIDDLE \|\| i->aggr == AGGR_BUF_LAST)
260	return;
261
262	ACCESS_ONCE(ads->ds_ctl4) = set11nPktDurRTSCTS(i->rates, 0)
263	\| set11nPktDurRTSCTS(i->rates, 1);
264
265	ACCESS_ONCE(ads->ds_ctl5) = set11nPktDurRTSCTS(i->rates, 2)
266	\| set11nPktDurRTSCTS(i->rates, 3);
267
268	ACCESS_ONCE(ads->ds_ctl7) = set11nRateFlags(i->rates, 0)
269	\| set11nRateFlags(i->rates, 1)
270	\| set11nRateFlags(i->rates, 2)
271	\| set11nRateFlags(i->rates, 3)
272	\| SM(i->rtscts_rate, AR_RTSCTSRate);
273	}
274
b622a720 LR	275	static int ar9002_hw_proc_txdesc(struct ath_hw ah, void ds,
	276	struct ath_tx_status *ts)
	277	{
	278	struct ar5416_desc *ads = AR5416DESC(ds);
e0e9bc82	279	u32 status;
b622a720	280
e0e9bc82 FF	281	status = ACCESS_ONCE(ads->ds_txstatus9);
e0e9bc82 FF	282	if ((status & AR_TxDone) == 0)
b622a720 LR	283	return -EINPROGRESS;
b622a720 LR	284
b622a720 LR	285	ts->ts_tstamp = ads->AR_SendTimestamp;
	286	ts->ts_status = 0;
	287	ts->ts_flags = 0;
	288
e0e9bc82 FF	289	if (status & AR_TxOpExceeded)
	290	ts->ts_status \|= ATH9K_TXERR_XTXOP;
	291	ts->tid = MS(status, AR_TxTid);
	292	ts->ts_rateindex = MS(status, AR_FinalTxIdx);
	293	ts->ts_seqnum = MS(status, AR_SeqNum);
	294
	295	status = ACCESS_ONCE(ads->ds_txstatus0);
	296	ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
	297	ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
	298	ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
	299	if (status & AR_TxBaStatus) {
	300	ts->ts_flags \|= ATH9K_TX_BA;
	301	ts->ba_low = ads->AR_BaBitmapLow;
	302	ts->ba_high = ads->AR_BaBitmapHigh;
	303	}
	304
	305	status = ACCESS_ONCE(ads->ds_txstatus1);
	306	if (status & AR_FrmXmitOK)
b622a720	307	ts->ts_status \|= ATH9K_TX_ACKED;
ff32d9cd FF	308	else {
	309	if (status & AR_ExcessiveRetries)
	310	ts->ts_status \|= ATH9K_TXERR_XRETRY;
	311	if (status & AR_Filtered)
	312	ts->ts_status \|= ATH9K_TXERR_FILT;
	313	if (status & AR_FIFOUnderrun) {
	314	ts->ts_status \|= ATH9K_TXERR_FIFO;
	315	ath9k_hw_updatetxtriglevel(ah, true);
	316	}
b622a720	317	}
e0e9bc82	318	if (status & AR_TxTimerExpired)
b622a720	319	ts->ts_status \|= ATH9K_TXERR_TIMER_EXPIRED;
e0e9bc82	320	if (status & AR_DescCfgErr)
b622a720	321	ts->ts_flags \|= ATH9K_TX_DESC_CFG_ERR;
e0e9bc82	322	if (status & AR_TxDataUnderrun) {
b622a720 LR	323	ts->ts_flags \|= ATH9K_TX_DATA_UNDERRUN;
	324	ath9k_hw_updatetxtriglevel(ah, true);
	325	}
e0e9bc82	326	if (status & AR_TxDelimUnderrun) {
b622a720 LR	327	ts->ts_flags \|= ATH9K_TX_DELIM_UNDERRUN;
	328	ath9k_hw_updatetxtriglevel(ah, true);
	329	}
e0e9bc82 FF	330	ts->ts_shortretry = MS(status, AR_RTSFailCnt);
	331	ts->ts_longretry = MS(status, AR_DataFailCnt);
	332	ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
b622a720	333
e0e9bc82 FF	334	status = ACCESS_ONCE(ads->ds_txstatus5);
	335	ts->ts_rssi = MS(status, AR_TxRSSICombined);
	336	ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
	337	ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
	338	ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
b622a720	339
b622a720 LR	340	ts->evm0 = ads->AR_TxEVM0;
	341	ts->evm1 = ads->AR_TxEVM1;
	342	ts->evm2 = ads->AR_TxEVM2;
b622a720 LR	343
	344	return 0;
	345	}
	346
b622a720 LR	347	void ath9k_hw_setuprxdesc(struct ath_hw ah, struct ath_desc ds,
	348	u32 size, u32 flags)
	349	{
	350	struct ar5416_desc *ads = AR5416DESC(ds);
b622a720 LR	351
	352	ads->ds_ctl1 = size & AR_BufLen;
	353	if (flags & ATH9K_RXDESC_INTREQ)
	354	ads->ds_ctl1 \|= AR_RxIntrReq;
	355
aebc0a88	356	memset(&ads->u.rx, 0, sizeof(ads->u.rx));
b622a720 LR	357	}
	358	EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
	359
	360	void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
	361	{
	362	struct ath_hw_ops *ops = ath9k_hw_ops(ah);
	363
	364	ops->rx_enable = ar9002_hw_rx_enable;
	365	ops->set_desc_link = ar9002_hw_set_desc_link;
b622a720	366	ops->get_isr = ar9002_hw_get_isr;
2b63a41d	367	ops->set_txdesc = ar9002_set_txdesc;
b622a720	368	ops->proc_txdesc = ar9002_hw_proc_txdesc;
b622a720	369	}