Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
cfe8cba9 | 17 | #include "hw.h" |
8fe65368 LR |
18 | #include "hw-ops.h" |
19 | #include "../regd.h" | |
20 | #include "ar9002_phy.h" | |
e16393bb | 21 | |
e36b27af LR |
22 | /* All code below is for AR5008, AR9001, AR9002 */ |
23 | ||
24 | static const int firstep_table[] = | |
25 | /* level: 0 1 2 3 4 5 6 7 8 */ | |
26 | { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ | |
27 | ||
28 | static const int cycpwrThr1_table[] = | |
29 | /* level: 0 1 2 3 4 5 6 7 8 */ | |
30 | { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ | |
31 | ||
32 | /* | |
33 | * register values to turn OFDM weak signal detection OFF | |
34 | */ | |
35 | static const int m1ThreshLow_off = 127; | |
36 | static const int m2ThreshLow_off = 127; | |
37 | static const int m1Thresh_off = 127; | |
38 | static const int m2Thresh_off = 127; | |
39 | static const int m2CountThr_off = 31; | |
40 | static const int m2CountThrLow_off = 63; | |
41 | static const int m1ThreshLowExt_off = 127; | |
42 | static const int m2ThreshLowExt_off = 127; | |
43 | static const int m1ThreshExt_off = 127; | |
44 | static const int m2ThreshExt_off = 127; | |
45 | ||
e16393bb | 46 | |
a9b6b256 FF |
47 | static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array, |
48 | int col) | |
49 | { | |
50 | int i; | |
51 | ||
52 | for (i = 0; i < array->ia_rows; i++) | |
53 | bank[i] = INI_RA(array, i, col); | |
54 | } | |
55 | ||
56 | ||
57 | #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \ | |
58 | ar5008_write_rf_array(ah, iniarray, regData, &(regWr)) | |
59 | ||
60 | static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array, | |
61 | u32 *data, unsigned int *writecnt) | |
62 | { | |
63 | int r; | |
64 | ||
65 | ENABLE_REGWRITE_BUFFER(ah); | |
66 | ||
67 | for (r = 0; r < array->ia_rows; r++) { | |
68 | REG_WRITE(ah, INI_RA(array, r, 0), data[r]); | |
69 | DO_DELAY(*writecnt); | |
70 | } | |
71 | ||
72 | REGWRITE_BUFFER_FLUSH(ah); | |
73 | } | |
74 | ||
ddcd4c08 | 75 | /** |
8fe65368 | 76 | * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters |
ddcd4c08 LR |
77 | * @rfbuf: |
78 | * @reg32: | |
79 | * @numBits: | |
80 | * @firstBit: | |
81 | * @column: | |
82 | * | |
83 | * Performs analog "swizzling" of parameters into their location. | |
84 | * Used on external AR2133/AR5133 radios. | |
85 | */ | |
8fe65368 LR |
86 | static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, |
87 | u32 numBits, u32 firstBit, | |
88 | u32 column) | |
ddcd4c08 LR |
89 | { |
90 | u32 tmp32, mask, arrayEntry, lastBit; | |
91 | int32_t bitPosition, bitsLeft; | |
92 | ||
93 | tmp32 = ath9k_hw_reverse_bits(reg32, numBits); | |
94 | arrayEntry = (firstBit - 1) / 8; | |
95 | bitPosition = (firstBit - 1) % 8; | |
96 | bitsLeft = numBits; | |
97 | while (bitsLeft > 0) { | |
98 | lastBit = (bitPosition + bitsLeft > 8) ? | |
99 | 8 : bitPosition + bitsLeft; | |
100 | mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << | |
101 | (column * 8); | |
102 | rfBuf[arrayEntry] &= ~mask; | |
103 | rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << | |
104 | (column * 8)) & mask; | |
105 | bitsLeft -= 8 - bitPosition; | |
106 | tmp32 = tmp32 >> (8 - bitPosition); | |
107 | bitPosition = 0; | |
108 | arrayEntry++; | |
109 | } | |
110 | } | |
111 | ||
a7765828 LR |
112 | /* |
113 | * Fix on 2.4 GHz band for orientation sensitivity issue by increasing | |
114 | * rf_pwd_icsyndiv. | |
115 | * | |
116 | * Theoretical Rules: | |
117 | * if 2 GHz band | |
118 | * if forceBiasAuto | |
119 | * if synth_freq < 2412 | |
120 | * bias = 0 | |
121 | * else if 2412 <= synth_freq <= 2422 | |
122 | * bias = 1 | |
123 | * else // synth_freq > 2422 | |
124 | * bias = 2 | |
125 | * else if forceBias > 0 | |
126 | * bias = forceBias & 7 | |
127 | * else | |
128 | * no change, use value from ini file | |
129 | * else | |
130 | * no change, invalid band | |
131 | * | |
132 | * 1st Mod: | |
133 | * 2422 also uses value of 2 | |
134 | * <approved> | |
135 | * | |
136 | * 2nd Mod: | |
137 | * Less than 2412 uses value of 0, 2412 and above uses value of 2 | |
138 | */ | |
8fe65368 | 139 | static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) |
a7765828 LR |
140 | { |
141 | struct ath_common *common = ath9k_hw_common(ah); | |
142 | u32 tmp_reg; | |
143 | int reg_writes = 0; | |
144 | u32 new_bias = 0; | |
145 | ||
8fe65368 | 146 | if (!AR_SREV_5416(ah) || synth_freq >= 3000) |
a7765828 | 147 | return; |
a7765828 | 148 | |
7a37081e | 149 | BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); |
a7765828 LR |
150 | |
151 | if (synth_freq < 2412) | |
152 | new_bias = 0; | |
153 | else if (synth_freq < 2422) | |
154 | new_bias = 1; | |
155 | else | |
156 | new_bias = 2; | |
157 | ||
158 | /* pre-reverse this field */ | |
159 | tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); | |
160 | ||
d2182b69 | 161 | ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", |
226afe68 | 162 | new_bias, synth_freq); |
a7765828 LR |
163 | |
164 | /* swizzle rf_pwd_icsyndiv */ | |
8fe65368 | 165 | ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); |
a7765828 LR |
166 | |
167 | /* write Bank 6 with new params */ | |
168 | REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes); | |
169 | } | |
170 | ||
e16393bb | 171 | /** |
8fe65368 | 172 | * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios |
25985edc | 173 | * @ah: atheros hardware structure |
e16393bb LR |
174 | * @chan: |
175 | * | |
176 | * For the external AR2133/AR5133 radios, takes the MHz channel value and set | |
177 | * the channel value. Assumes writes enabled to analog bus and bank6 register | |
178 | * cache in ah->analogBank6Data. | |
179 | */ | |
8fe65368 | 180 | static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) |
e16393bb LR |
181 | { |
182 | struct ath_common *common = ath9k_hw_common(ah); | |
183 | u32 channelSel = 0; | |
184 | u32 bModeSynth = 0; | |
185 | u32 aModeRefSel = 0; | |
186 | u32 reg32 = 0; | |
187 | u16 freq; | |
188 | struct chan_centers centers; | |
189 | ||
190 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
191 | freq = centers.synth_center; | |
192 | ||
193 | if (freq < 4800) { | |
194 | u32 txctl; | |
195 | ||
196 | if (((freq - 2192) % 5) == 0) { | |
197 | channelSel = ((freq - 672) * 2 - 3040) / 10; | |
198 | bModeSynth = 0; | |
199 | } else if (((freq - 2224) % 5) == 0) { | |
200 | channelSel = ((freq - 704) * 2 - 3040) / 10; | |
201 | bModeSynth = 1; | |
202 | } else { | |
3800276a | 203 | ath_err(common, "Invalid channel %u MHz\n", freq); |
e16393bb LR |
204 | return -EINVAL; |
205 | } | |
206 | ||
207 | channelSel = (channelSel << 2) & 0xff; | |
208 | channelSel = ath9k_hw_reverse_bits(channelSel, 8); | |
209 | ||
210 | txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); | |
211 | if (freq == 2484) { | |
212 | ||
213 | REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, | |
214 | txctl | AR_PHY_CCK_TX_CTRL_JAPAN); | |
215 | } else { | |
216 | REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, | |
217 | txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); | |
218 | } | |
219 | ||
220 | } else if ((freq % 20) == 0 && freq >= 5120) { | |
221 | channelSel = | |
222 | ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); | |
223 | aModeRefSel = ath9k_hw_reverse_bits(1, 2); | |
224 | } else if ((freq % 10) == 0) { | |
225 | channelSel = | |
226 | ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); | |
227 | if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) | |
228 | aModeRefSel = ath9k_hw_reverse_bits(2, 2); | |
229 | else | |
230 | aModeRefSel = ath9k_hw_reverse_bits(1, 2); | |
231 | } else if ((freq % 5) == 0) { | |
232 | channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); | |
233 | aModeRefSel = ath9k_hw_reverse_bits(1, 2); | |
234 | } else { | |
3800276a | 235 | ath_err(common, "Invalid channel %u MHz\n", freq); |
e16393bb LR |
236 | return -EINVAL; |
237 | } | |
238 | ||
8fe65368 | 239 | ar5008_hw_force_bias(ah, freq); |
a7765828 | 240 | |
e16393bb LR |
241 | reg32 = |
242 | (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | | |
243 | (1 << 5) | 0x1; | |
244 | ||
245 | REG_WRITE(ah, AR_PHY(0x37), reg32); | |
246 | ||
247 | ah->curchan = chan; | |
e16393bb LR |
248 | |
249 | return 0; | |
250 | } | |
251 | ||
252 | /** | |
8fe65368 | 253 | * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios |
e16393bb LR |
254 | * @ah: atheros hardware structure |
255 | * @chan: | |
256 | * | |
257 | * For non single-chip solutions. Converts to baseband spur frequency given the | |
258 | * input channel frequency and compute register settings below. | |
259 | */ | |
8fe65368 LR |
260 | static void ar5008_hw_spur_mitigate(struct ath_hw *ah, |
261 | struct ath9k_channel *chan) | |
e16393bb LR |
262 | { |
263 | int bb_spur = AR_NO_SPUR; | |
264 | int bin, cur_bin; | |
265 | int spur_freq_sd; | |
266 | int spur_delta_phase; | |
267 | int denominator; | |
268 | int upper, lower, cur_vit_mask; | |
269 | int tmp, new; | |
270 | int i; | |
07b2fa5a JP |
271 | static int pilot_mask_reg[4] = { |
272 | AR_PHY_TIMING7, AR_PHY_TIMING8, | |
273 | AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 | |
e16393bb | 274 | }; |
07b2fa5a JP |
275 | static int chan_mask_reg[4] = { |
276 | AR_PHY_TIMING9, AR_PHY_TIMING10, | |
277 | AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 | |
e16393bb | 278 | }; |
07b2fa5a | 279 | static int inc[4] = { 0, 100, 0, 0 }; |
e16393bb LR |
280 | |
281 | int8_t mask_m[123]; | |
282 | int8_t mask_p[123]; | |
283 | int8_t mask_amt; | |
284 | int tmp_mask; | |
285 | int cur_bb_spur; | |
286 | bool is2GHz = IS_CHAN_2GHZ(chan); | |
287 | ||
288 | memset(&mask_m, 0, sizeof(int8_t) * 123); | |
289 | memset(&mask_p, 0, sizeof(int8_t) * 123); | |
290 | ||
291 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { | |
292 | cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); | |
293 | if (AR_NO_SPUR == cur_bb_spur) | |
294 | break; | |
295 | cur_bb_spur = cur_bb_spur - (chan->channel * 10); | |
296 | if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { | |
297 | bb_spur = cur_bb_spur; | |
298 | break; | |
299 | } | |
300 | } | |
301 | ||
302 | if (AR_NO_SPUR == bb_spur) | |
303 | return; | |
304 | ||
305 | bin = bb_spur * 32; | |
306 | ||
307 | tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); | |
308 | new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | | |
309 | AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | | |
310 | AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | | |
311 | AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); | |
312 | ||
313 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); | |
314 | ||
315 | new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | | |
316 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM | | |
317 | AR_PHY_SPUR_REG_MASK_RATE_SELECT | | |
318 | AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | | |
319 | SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); | |
320 | REG_WRITE(ah, AR_PHY_SPUR_REG, new); | |
321 | ||
322 | spur_delta_phase = ((bb_spur * 524288) / 100) & | |
323 | AR_PHY_TIMING11_SPUR_DELTA_PHASE; | |
324 | ||
325 | denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; | |
326 | spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; | |
327 | ||
328 | new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | | |
329 | SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | | |
330 | SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); | |
331 | REG_WRITE(ah, AR_PHY_TIMING11, new); | |
332 | ||
333 | cur_bin = -6000; | |
334 | upper = bin + 100; | |
335 | lower = bin - 100; | |
336 | ||
337 | for (i = 0; i < 4; i++) { | |
338 | int pilot_mask = 0; | |
339 | int chan_mask = 0; | |
340 | int bp = 0; | |
341 | for (bp = 0; bp < 30; bp++) { | |
342 | if ((cur_bin > lower) && (cur_bin < upper)) { | |
343 | pilot_mask = pilot_mask | 0x1 << bp; | |
344 | chan_mask = chan_mask | 0x1 << bp; | |
345 | } | |
346 | cur_bin += 100; | |
347 | } | |
348 | cur_bin += inc[i]; | |
349 | REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); | |
350 | REG_WRITE(ah, chan_mask_reg[i], chan_mask); | |
351 | } | |
352 | ||
353 | cur_vit_mask = 6100; | |
354 | upper = bin + 120; | |
355 | lower = bin - 120; | |
356 | ||
357 | for (i = 0; i < 123; i++) { | |
358 | if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { | |
359 | ||
360 | /* workaround for gcc bug #37014 */ | |
361 | volatile int tmp_v = abs(cur_vit_mask - bin); | |
362 | ||
363 | if (tmp_v < 75) | |
364 | mask_amt = 1; | |
365 | else | |
366 | mask_amt = 0; | |
367 | if (cur_vit_mask < 0) | |
368 | mask_m[abs(cur_vit_mask / 100)] = mask_amt; | |
369 | else | |
370 | mask_p[cur_vit_mask / 100] = mask_amt; | |
371 | } | |
372 | cur_vit_mask -= 100; | |
373 | } | |
374 | ||
375 | tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) | |
376 | | (mask_m[48] << 26) | (mask_m[49] << 24) | |
377 | | (mask_m[50] << 22) | (mask_m[51] << 20) | |
378 | | (mask_m[52] << 18) | (mask_m[53] << 16) | |
379 | | (mask_m[54] << 14) | (mask_m[55] << 12) | |
380 | | (mask_m[56] << 10) | (mask_m[57] << 8) | |
381 | | (mask_m[58] << 6) | (mask_m[59] << 4) | |
382 | | (mask_m[60] << 2) | (mask_m[61] << 0); | |
383 | REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); | |
384 | REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); | |
385 | ||
386 | tmp_mask = (mask_m[31] << 28) | |
387 | | (mask_m[32] << 26) | (mask_m[33] << 24) | |
388 | | (mask_m[34] << 22) | (mask_m[35] << 20) | |
389 | | (mask_m[36] << 18) | (mask_m[37] << 16) | |
390 | | (mask_m[48] << 14) | (mask_m[39] << 12) | |
391 | | (mask_m[40] << 10) | (mask_m[41] << 8) | |
392 | | (mask_m[42] << 6) | (mask_m[43] << 4) | |
393 | | (mask_m[44] << 2) | (mask_m[45] << 0); | |
394 | REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); | |
395 | REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); | |
396 | ||
397 | tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) | |
398 | | (mask_m[18] << 26) | (mask_m[18] << 24) | |
399 | | (mask_m[20] << 22) | (mask_m[20] << 20) | |
400 | | (mask_m[22] << 18) | (mask_m[22] << 16) | |
401 | | (mask_m[24] << 14) | (mask_m[24] << 12) | |
402 | | (mask_m[25] << 10) | (mask_m[26] << 8) | |
403 | | (mask_m[27] << 6) | (mask_m[28] << 4) | |
404 | | (mask_m[29] << 2) | (mask_m[30] << 0); | |
405 | REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); | |
406 | REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); | |
407 | ||
408 | tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) | |
409 | | (mask_m[2] << 26) | (mask_m[3] << 24) | |
410 | | (mask_m[4] << 22) | (mask_m[5] << 20) | |
411 | | (mask_m[6] << 18) | (mask_m[7] << 16) | |
412 | | (mask_m[8] << 14) | (mask_m[9] << 12) | |
413 | | (mask_m[10] << 10) | (mask_m[11] << 8) | |
414 | | (mask_m[12] << 6) | (mask_m[13] << 4) | |
415 | | (mask_m[14] << 2) | (mask_m[15] << 0); | |
416 | REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); | |
417 | REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); | |
418 | ||
419 | tmp_mask = (mask_p[15] << 28) | |
420 | | (mask_p[14] << 26) | (mask_p[13] << 24) | |
421 | | (mask_p[12] << 22) | (mask_p[11] << 20) | |
422 | | (mask_p[10] << 18) | (mask_p[9] << 16) | |
423 | | (mask_p[8] << 14) | (mask_p[7] << 12) | |
424 | | (mask_p[6] << 10) | (mask_p[5] << 8) | |
425 | | (mask_p[4] << 6) | (mask_p[3] << 4) | |
426 | | (mask_p[2] << 2) | (mask_p[1] << 0); | |
427 | REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); | |
428 | REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); | |
429 | ||
430 | tmp_mask = (mask_p[30] << 28) | |
431 | | (mask_p[29] << 26) | (mask_p[28] << 24) | |
432 | | (mask_p[27] << 22) | (mask_p[26] << 20) | |
433 | | (mask_p[25] << 18) | (mask_p[24] << 16) | |
434 | | (mask_p[23] << 14) | (mask_p[22] << 12) | |
435 | | (mask_p[21] << 10) | (mask_p[20] << 8) | |
436 | | (mask_p[19] << 6) | (mask_p[18] << 4) | |
437 | | (mask_p[17] << 2) | (mask_p[16] << 0); | |
438 | REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); | |
439 | REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); | |
440 | ||
441 | tmp_mask = (mask_p[45] << 28) | |
442 | | (mask_p[44] << 26) | (mask_p[43] << 24) | |
443 | | (mask_p[42] << 22) | (mask_p[41] << 20) | |
444 | | (mask_p[40] << 18) | (mask_p[39] << 16) | |
445 | | (mask_p[38] << 14) | (mask_p[37] << 12) | |
446 | | (mask_p[36] << 10) | (mask_p[35] << 8) | |
447 | | (mask_p[34] << 6) | (mask_p[33] << 4) | |
448 | | (mask_p[32] << 2) | (mask_p[31] << 0); | |
449 | REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); | |
450 | REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); | |
451 | ||
452 | tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) | |
453 | | (mask_p[59] << 26) | (mask_p[58] << 24) | |
454 | | (mask_p[57] << 22) | (mask_p[56] << 20) | |
455 | | (mask_p[55] << 18) | (mask_p[54] << 16) | |
456 | | (mask_p[53] << 14) | (mask_p[52] << 12) | |
457 | | (mask_p[51] << 10) | (mask_p[50] << 8) | |
458 | | (mask_p[49] << 6) | (mask_p[48] << 4) | |
459 | | (mask_p[47] << 2) | (mask_p[46] << 0); | |
460 | REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); | |
461 | REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); | |
462 | } | |
463 | ||
464 | /** | |
8fe65368 | 465 | * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming |
e16393bb LR |
466 | * @ah: atheros hardware structure |
467 | * | |
468 | * Only required for older devices with external AR2133/AR5133 radios. | |
469 | */ | |
8fe65368 | 470 | static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) |
e16393bb LR |
471 | { |
472 | #define ATH_ALLOC_BANK(bank, size) do { \ | |
473 | bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \ | |
474 | if (!bank) { \ | |
3800276a | 475 | ath_err(common, "Cannot allocate RF banks\n"); \ |
e16393bb LR |
476 | return -ENOMEM; \ |
477 | } \ | |
478 | } while (0); | |
479 | ||
480 | struct ath_common *common = ath9k_hw_common(ah); | |
481 | ||
7a37081e | 482 | BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); |
e16393bb LR |
483 | |
484 | ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows); | |
485 | ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows); | |
486 | ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows); | |
487 | ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows); | |
488 | ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows); | |
489 | ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows); | |
490 | ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows); | |
e16393bb LR |
491 | ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows); |
492 | ||
493 | return 0; | |
494 | #undef ATH_ALLOC_BANK | |
495 | } | |
496 | ||
497 | ||
498 | /** | |
8fe65368 | 499 | * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers |
e16393bb LR |
500 | * @ah: atheros hardware struture |
501 | * For the external AR2133/AR5133 radios banks. | |
502 | */ | |
8fe65368 | 503 | static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah) |
e16393bb LR |
504 | { |
505 | #define ATH_FREE_BANK(bank) do { \ | |
506 | kfree(bank); \ | |
507 | bank = NULL; \ | |
508 | } while (0); | |
509 | ||
7a37081e | 510 | BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); |
e16393bb LR |
511 | |
512 | ATH_FREE_BANK(ah->analogBank0Data); | |
513 | ATH_FREE_BANK(ah->analogBank1Data); | |
514 | ATH_FREE_BANK(ah->analogBank2Data); | |
515 | ATH_FREE_BANK(ah->analogBank3Data); | |
516 | ATH_FREE_BANK(ah->analogBank6Data); | |
517 | ATH_FREE_BANK(ah->analogBank6TPCData); | |
518 | ATH_FREE_BANK(ah->analogBank7Data); | |
e16393bb LR |
519 | ATH_FREE_BANK(ah->bank6Temp); |
520 | ||
521 | #undef ATH_FREE_BANK | |
522 | } | |
523 | ||
131d1d03 | 524 | /* * |
8fe65368 | 525 | * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM |
131d1d03 LR |
526 | * @ah: atheros hardware structure |
527 | * @chan: | |
528 | * @modesIndex: | |
529 | * | |
530 | * Used for the external AR2133/AR5133 radios. | |
531 | * | |
532 | * Reads the EEPROM header info from the device structure and programs | |
533 | * all rf registers. This routine requires access to the analog | |
534 | * rf device. This is not required for single-chip devices. | |
535 | */ | |
8fe65368 LR |
536 | static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, |
537 | struct ath9k_channel *chan, | |
538 | u16 modesIndex) | |
f078f209 | 539 | { |
f078f209 LR |
540 | u32 eepMinorRev; |
541 | u32 ob5GHz = 0, db5GHz = 0; | |
542 | u32 ob2GHz = 0, db2GHz = 0; | |
543 | int regWrites = 0; | |
544 | ||
131d1d03 LR |
545 | /* |
546 | * Software does not need to program bank data | |
547 | * for single chip devices, that is AR9280 or anything | |
548 | * after that. | |
549 | */ | |
7a37081e | 550 | if (AR_SREV_9280_20_OR_LATER(ah)) |
f078f209 LR |
551 | return true; |
552 | ||
131d1d03 | 553 | /* Setup rf parameters */ |
f74df6fb | 554 | eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); |
f078f209 | 555 | |
131d1d03 | 556 | /* Setup Bank 0 Write */ |
a9b6b256 | 557 | ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1); |
f078f209 | 558 | |
131d1d03 | 559 | /* Setup Bank 1 Write */ |
a9b6b256 | 560 | ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1); |
f078f209 | 561 | |
131d1d03 | 562 | /* Setup Bank 2 Write */ |
a9b6b256 | 563 | ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1); |
f078f209 | 564 | |
131d1d03 | 565 | /* Setup Bank 6 Write */ |
a9b6b256 | 566 | ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3, |
f078f209 LR |
567 | modesIndex); |
568 | { | |
569 | int i; | |
2660b81a S |
570 | for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) { |
571 | ah->analogBank6Data[i] = | |
572 | INI_RA(&ah->iniBank6TPC, i, modesIndex); | |
f078f209 LR |
573 | } |
574 | } | |
575 | ||
131d1d03 | 576 | /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ |
f078f209 LR |
577 | if (eepMinorRev >= 2) { |
578 | if (IS_CHAN_2GHZ(chan)) { | |
f74df6fb S |
579 | ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); |
580 | db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); | |
8fe65368 LR |
581 | ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, |
582 | ob2GHz, 3, 197, 0); | |
583 | ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, | |
584 | db2GHz, 3, 194, 0); | |
f078f209 | 585 | } else { |
f74df6fb S |
586 | ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); |
587 | db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); | |
8fe65368 LR |
588 | ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, |
589 | ob5GHz, 3, 203, 0); | |
590 | ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, | |
591 | db5GHz, 3, 200, 0); | |
f078f209 LR |
592 | } |
593 | } | |
594 | ||
131d1d03 | 595 | /* Setup Bank 7 Setup */ |
a9b6b256 | 596 | ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1); |
f078f209 | 597 | |
131d1d03 | 598 | /* Write Analog registers */ |
2660b81a | 599 | REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, |
f078f209 | 600 | regWrites); |
2660b81a | 601 | REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, |
f078f209 | 602 | regWrites); |
2660b81a | 603 | REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data, |
f078f209 | 604 | regWrites); |
2660b81a | 605 | REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data, |
f078f209 | 606 | regWrites); |
2660b81a | 607 | REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data, |
f078f209 | 608 | regWrites); |
2660b81a | 609 | REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data, |
f078f209 LR |
610 | regWrites); |
611 | ||
612 | return true; | |
613 | } | |
8fe65368 LR |
614 | |
615 | static void ar5008_hw_init_bb(struct ath_hw *ah, | |
616 | struct ath9k_channel *chan) | |
617 | { | |
618 | u32 synthDelay; | |
619 | ||
620 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; | |
7d865c70 | 621 | |
8fe65368 LR |
622 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); |
623 | ||
7c5adc8d | 624 | ath9k_hw_synth_delay(ah, chan, synthDelay); |
8fe65368 LR |
625 | } |
626 | ||
627 | static void ar5008_hw_init_chain_masks(struct ath_hw *ah) | |
628 | { | |
629 | int rx_chainmask, tx_chainmask; | |
630 | ||
631 | rx_chainmask = ah->rxchainmask; | |
632 | tx_chainmask = ah->txchainmask; | |
633 | ||
7d0d0df0 | 634 | |
8fe65368 LR |
635 | switch (rx_chainmask) { |
636 | case 0x5: | |
637 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | |
638 | AR_PHY_SWAP_ALT_CHAIN); | |
639 | case 0x3: | |
640 | if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { | |
641 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); | |
642 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); | |
643 | break; | |
644 | } | |
645 | case 0x1: | |
646 | case 0x2: | |
647 | case 0x7: | |
435c1610 | 648 | ENABLE_REGWRITE_BUFFER(ah); |
8fe65368 LR |
649 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); |
650 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); | |
651 | break; | |
652 | default: | |
435c1610 | 653 | ENABLE_REGWRITE_BUFFER(ah); |
8fe65368 LR |
654 | break; |
655 | } | |
656 | ||
657 | REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); | |
7d0d0df0 S |
658 | |
659 | REGWRITE_BUFFER_FLUSH(ah); | |
7d0d0df0 | 660 | |
8fe65368 LR |
661 | if (tx_chainmask == 0x5) { |
662 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | |
663 | AR_PHY_SWAP_ALT_CHAIN); | |
664 | } | |
665 | if (AR_SREV_9100(ah)) | |
666 | REG_WRITE(ah, AR_PHY_ANALOG_SWAP, | |
667 | REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); | |
668 | } | |
669 | ||
670 | static void ar5008_hw_override_ini(struct ath_hw *ah, | |
671 | struct ath9k_channel *chan) | |
672 | { | |
673 | u32 val; | |
674 | ||
675 | /* | |
676 | * Set the RX_ABORT and RX_DIS and clear if off only after | |
677 | * RXE is set for MAC. This prevents frames with corrupted | |
678 | * descriptor status. | |
679 | */ | |
680 | REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); | |
681 | ||
7a37081e | 682 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
8fe65368 LR |
683 | val = REG_READ(ah, AR_PCU_MISC_MODE2); |
684 | ||
685 | if (!AR_SREV_9271(ah)) | |
686 | val &= ~AR_PCU_MISC_MODE2_HWWAR1; | |
687 | ||
a42acef0 | 688 | if (AR_SREV_9287_11_OR_LATER(ah)) |
8fe65368 LR |
689 | val = val & (~AR_PCU_MISC_MODE2_HWWAR2); |
690 | ||
691 | REG_WRITE(ah, AR_PCU_MISC_MODE2, val); | |
692 | } | |
693 | ||
bf3f204b FF |
694 | REG_SET_BIT(ah, AR_PHY_CCK_DETECT, |
695 | AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); | |
696 | ||
1b8714f7 | 697 | if (AR_SREV_9280_20_OR_LATER(ah)) |
8fe65368 LR |
698 | return; |
699 | /* | |
700 | * Disable BB clock gating | |
701 | * Necessary to avoid issues on AR5416 2.0 | |
702 | */ | |
703 | REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); | |
704 | ||
705 | /* | |
706 | * Disable RIFS search on some chips to avoid baseband | |
707 | * hang issues. | |
708 | */ | |
709 | if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { | |
710 | val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); | |
711 | val &= ~AR_PHY_RIFS_INIT_DELAY; | |
712 | REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); | |
713 | } | |
714 | } | |
715 | ||
716 | static void ar5008_hw_set_channel_regs(struct ath_hw *ah, | |
717 | struct ath9k_channel *chan) | |
718 | { | |
719 | u32 phymode; | |
720 | u32 enableDacFifo = 0; | |
721 | ||
e17f83ea | 722 | if (AR_SREV_9285_12_OR_LATER(ah)) |
8fe65368 LR |
723 | enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & |
724 | AR_PHY_FC_ENABLE_DAC_FIFO); | |
725 | ||
726 | phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 | |
727 | | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; | |
728 | ||
729 | if (IS_CHAN_HT40(chan)) { | |
730 | phymode |= AR_PHY_FC_DYN2040_EN; | |
731 | ||
732 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || | |
733 | (chan->chanmode == CHANNEL_G_HT40PLUS)) | |
734 | phymode |= AR_PHY_FC_DYN2040_PRI_CH; | |
735 | ||
736 | } | |
737 | REG_WRITE(ah, AR_PHY_TURBO, phymode); | |
738 | ||
739 | ath9k_hw_set11nmac2040(ah); | |
740 | ||
7d0d0df0 S |
741 | ENABLE_REGWRITE_BUFFER(ah); |
742 | ||
8fe65368 LR |
743 | REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); |
744 | REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); | |
7d0d0df0 S |
745 | |
746 | REGWRITE_BUFFER_FLUSH(ah); | |
8fe65368 LR |
747 | } |
748 | ||
749 | ||
750 | static int ar5008_hw_process_ini(struct ath_hw *ah, | |
751 | struct ath9k_channel *chan) | |
752 | { | |
e7fc6338 | 753 | struct ath_common *common = ath9k_hw_common(ah); |
8fe65368 | 754 | int i, regWrites = 0; |
8fe65368 LR |
755 | u32 modesIndex, freqIndex; |
756 | ||
757 | switch (chan->chanmode) { | |
758 | case CHANNEL_A: | |
759 | case CHANNEL_A_HT20: | |
760 | modesIndex = 1; | |
761 | freqIndex = 1; | |
762 | break; | |
763 | case CHANNEL_A_HT40PLUS: | |
764 | case CHANNEL_A_HT40MINUS: | |
765 | modesIndex = 2; | |
766 | freqIndex = 1; | |
767 | break; | |
768 | case CHANNEL_G: | |
769 | case CHANNEL_G_HT20: | |
770 | case CHANNEL_B: | |
771 | modesIndex = 4; | |
772 | freqIndex = 2; | |
773 | break; | |
774 | case CHANNEL_G_HT40PLUS: | |
775 | case CHANNEL_G_HT40MINUS: | |
776 | modesIndex = 3; | |
777 | freqIndex = 2; | |
778 | break; | |
779 | ||
780 | default: | |
781 | return -EINVAL; | |
782 | } | |
783 | ||
8fe65368 LR |
784 | /* |
785 | * Set correct baseband to analog shift setting to | |
786 | * access analog chips. | |
787 | */ | |
788 | REG_WRITE(ah, AR_PHY(0), 0x00000007); | |
789 | ||
790 | /* Write ADDAC shifts */ | |
791 | REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); | |
d7084da0 FF |
792 | if (ah->eep_ops->set_addac) |
793 | ah->eep_ops->set_addac(ah, chan); | |
8fe65368 | 794 | |
9bbb8168 | 795 | REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); |
8fe65368 LR |
796 | REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); |
797 | ||
7d0d0df0 S |
798 | ENABLE_REGWRITE_BUFFER(ah); |
799 | ||
8fe65368 LR |
800 | for (i = 0; i < ah->iniModes.ia_rows; i++) { |
801 | u32 reg = INI_RA(&ah->iniModes, i, 0); | |
802 | u32 val = INI_RA(&ah->iniModes, i, modesIndex); | |
803 | ||
804 | if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) | |
805 | val &= ~AR_AN_TOP2_PWDCLKIND; | |
806 | ||
807 | REG_WRITE(ah, reg, val); | |
808 | ||
809 | if (reg >= 0x7800 && reg < 0x78a0 | |
e7fc6338 RM |
810 | && ah->config.analog_shiftreg |
811 | && (common->bus_ops->ath_bus_type != ATH_USB)) { | |
8fe65368 LR |
812 | udelay(100); |
813 | } | |
814 | ||
815 | DO_DELAY(regWrites); | |
816 | } | |
817 | ||
7d0d0df0 | 818 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 819 | |
a42acef0 | 820 | if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) |
8fe65368 LR |
821 | REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); |
822 | ||
823 | if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || | |
a42acef0 | 824 | AR_SREV_9287_11_OR_LATER(ah)) |
8fe65368 LR |
825 | REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); |
826 | ||
c7effd35 FF |
827 | if (AR_SREV_9271_10(ah)) { |
828 | REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); | |
829 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); | |
830 | } | |
8fe65368 | 831 | |
7d0d0df0 S |
832 | ENABLE_REGWRITE_BUFFER(ah); |
833 | ||
8fe65368 LR |
834 | /* Write common array parameters */ |
835 | for (i = 0; i < ah->iniCommon.ia_rows; i++) { | |
836 | u32 reg = INI_RA(&ah->iniCommon, i, 0); | |
837 | u32 val = INI_RA(&ah->iniCommon, i, 1); | |
838 | ||
839 | REG_WRITE(ah, reg, val); | |
840 | ||
841 | if (reg >= 0x7800 && reg < 0x78a0 | |
e7fc6338 RM |
842 | && ah->config.analog_shiftreg |
843 | && (common->bus_ops->ath_bus_type != ATH_USB)) { | |
8fe65368 LR |
844 | udelay(100); |
845 | } | |
846 | ||
847 | DO_DELAY(regWrites); | |
848 | } | |
849 | ||
7d0d0df0 | 850 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 851 | |
8fe65368 LR |
852 | REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); |
853 | ||
c7d36f9f FF |
854 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
855 | REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, | |
8fe65368 | 856 | regWrites); |
8fe65368 LR |
857 | |
858 | ar5008_hw_override_ini(ah, chan); | |
859 | ar5008_hw_set_channel_regs(ah, chan); | |
860 | ar5008_hw_init_chain_masks(ah); | |
861 | ath9k_olc_init(ah); | |
64ea57d0 | 862 | ath9k_hw_apply_txpower(ah, chan, false); |
8fe65368 LR |
863 | |
864 | /* Write analog registers */ | |
865 | if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { | |
3800276a | 866 | ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); |
8fe65368 LR |
867 | return -EIO; |
868 | } | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
873 | static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) | |
874 | { | |
875 | u32 rfMode = 0; | |
876 | ||
877 | if (chan == NULL) | |
878 | return; | |
879 | ||
880 | rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) | |
881 | ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; | |
882 | ||
7a37081e | 883 | if (!AR_SREV_9280_20_OR_LATER(ah)) |
8fe65368 LR |
884 | rfMode |= (IS_CHAN_5GHZ(chan)) ? |
885 | AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; | |
886 | ||
6b42e8d0 | 887 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
8fe65368 LR |
888 | rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); |
889 | ||
890 | REG_WRITE(ah, AR_PHY_MODE, rfMode); | |
891 | } | |
892 | ||
893 | static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) | |
894 | { | |
895 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); | |
896 | } | |
897 | ||
898 | static void ar5008_hw_set_delta_slope(struct ath_hw *ah, | |
899 | struct ath9k_channel *chan) | |
900 | { | |
901 | u32 coef_scaled, ds_coef_exp, ds_coef_man; | |
902 | u32 clockMhzScaled = 0x64000000; | |
903 | struct chan_centers centers; | |
904 | ||
905 | if (IS_CHAN_HALF_RATE(chan)) | |
906 | clockMhzScaled = clockMhzScaled >> 1; | |
907 | else if (IS_CHAN_QUARTER_RATE(chan)) | |
908 | clockMhzScaled = clockMhzScaled >> 2; | |
909 | ||
910 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
911 | coef_scaled = clockMhzScaled / centers.synth_center; | |
912 | ||
913 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | |
914 | &ds_coef_exp); | |
915 | ||
916 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | |
917 | AR_PHY_TIMING3_DSC_MAN, ds_coef_man); | |
918 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | |
919 | AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); | |
920 | ||
921 | coef_scaled = (9 * coef_scaled) / 10; | |
922 | ||
923 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | |
924 | &ds_coef_exp); | |
925 | ||
926 | REG_RMW_FIELD(ah, AR_PHY_HALFGI, | |
927 | AR_PHY_HALFGI_DSC_MAN, ds_coef_man); | |
928 | REG_RMW_FIELD(ah, AR_PHY_HALFGI, | |
929 | AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); | |
930 | } | |
931 | ||
932 | static bool ar5008_hw_rfbus_req(struct ath_hw *ah) | |
933 | { | |
934 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); | |
935 | return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, | |
936 | AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); | |
937 | } | |
938 | ||
939 | static void ar5008_hw_rfbus_done(struct ath_hw *ah) | |
940 | { | |
941 | u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; | |
8fe65368 | 942 | |
7c5adc8d | 943 | ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); |
8fe65368 LR |
944 | |
945 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); | |
946 | } | |
947 | ||
8fe65368 LR |
948 | static void ar5008_restore_chainmask(struct ath_hw *ah) |
949 | { | |
950 | int rx_chainmask = ah->rxchainmask; | |
951 | ||
952 | if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { | |
953 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); | |
954 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); | |
955 | } | |
956 | } | |
957 | ||
64773964 LR |
958 | static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, |
959 | struct ath9k_channel *chan) | |
960 | { | |
961 | u32 pll; | |
962 | ||
963 | pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); | |
964 | ||
965 | if (chan && IS_CHAN_HALF_RATE(chan)) | |
966 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); | |
967 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
968 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); | |
969 | ||
970 | if (chan && IS_CHAN_5GHZ(chan)) | |
971 | pll |= SM(0x50, AR_RTC_9160_PLL_DIV); | |
972 | else | |
973 | pll |= SM(0x58, AR_RTC_9160_PLL_DIV); | |
974 | ||
975 | return pll; | |
976 | } | |
977 | ||
978 | static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, | |
979 | struct ath9k_channel *chan) | |
980 | { | |
981 | u32 pll; | |
982 | ||
983 | pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; | |
984 | ||
985 | if (chan && IS_CHAN_HALF_RATE(chan)) | |
986 | pll |= SM(0x1, AR_RTC_PLL_CLKSEL); | |
987 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
988 | pll |= SM(0x2, AR_RTC_PLL_CLKSEL); | |
989 | ||
990 | if (chan && IS_CHAN_5GHZ(chan)) | |
991 | pll |= SM(0xa, AR_RTC_PLL_DIV); | |
992 | else | |
993 | pll |= SM(0xb, AR_RTC_PLL_DIV); | |
994 | ||
995 | return pll; | |
996 | } | |
997 | ||
e36b27af LR |
998 | static bool ar5008_hw_ani_control_new(struct ath_hw *ah, |
999 | enum ath9k_ani_cmd cmd, | |
1000 | int param) | |
1001 | { | |
e36b27af LR |
1002 | struct ath_common *common = ath9k_hw_common(ah); |
1003 | struct ath9k_channel *chan = ah->curchan; | |
093115b7 | 1004 | struct ar5416AniState *aniState = &chan->ani; |
e36b27af LR |
1005 | s32 value, value2; |
1006 | ||
1007 | switch (cmd & ah->ani_function) { | |
1008 | case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ | |
1009 | /* | |
1010 | * on == 1 means ofdm weak signal detection is ON | |
1011 | * on == 1 is the default, for less noise immunity | |
1012 | * | |
1013 | * on == 0 means ofdm weak signal detection is OFF | |
1014 | * on == 0 means more noise imm | |
1015 | */ | |
1016 | u32 on = param ? 1 : 0; | |
1017 | /* | |
1018 | * make register setting for default | |
1019 | * (weak sig detect ON) come from INI file | |
1020 | */ | |
1021 | int m1ThreshLow = on ? | |
1022 | aniState->iniDef.m1ThreshLow : m1ThreshLow_off; | |
1023 | int m2ThreshLow = on ? | |
1024 | aniState->iniDef.m2ThreshLow : m2ThreshLow_off; | |
1025 | int m1Thresh = on ? | |
1026 | aniState->iniDef.m1Thresh : m1Thresh_off; | |
1027 | int m2Thresh = on ? | |
1028 | aniState->iniDef.m2Thresh : m2Thresh_off; | |
1029 | int m2CountThr = on ? | |
1030 | aniState->iniDef.m2CountThr : m2CountThr_off; | |
1031 | int m2CountThrLow = on ? | |
1032 | aniState->iniDef.m2CountThrLow : m2CountThrLow_off; | |
1033 | int m1ThreshLowExt = on ? | |
1034 | aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; | |
1035 | int m2ThreshLowExt = on ? | |
1036 | aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; | |
1037 | int m1ThreshExt = on ? | |
1038 | aniState->iniDef.m1ThreshExt : m1ThreshExt_off; | |
1039 | int m2ThreshExt = on ? | |
1040 | aniState->iniDef.m2ThreshExt : m2ThreshExt_off; | |
1041 | ||
1042 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | |
1043 | AR_PHY_SFCORR_LOW_M1_THRESH_LOW, | |
1044 | m1ThreshLow); | |
1045 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | |
1046 | AR_PHY_SFCORR_LOW_M2_THRESH_LOW, | |
1047 | m2ThreshLow); | |
1048 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, | |
1049 | AR_PHY_SFCORR_M1_THRESH, m1Thresh); | |
1050 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, | |
1051 | AR_PHY_SFCORR_M2_THRESH, m2Thresh); | |
1052 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, | |
1053 | AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); | |
1054 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | |
1055 | AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, | |
1056 | m2CountThrLow); | |
1057 | ||
1058 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | |
1059 | AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); | |
1060 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | |
1061 | AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); | |
1062 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | |
1063 | AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); | |
1064 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | |
1065 | AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); | |
1066 | ||
1067 | if (on) | |
1068 | REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, | |
1069 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | |
1070 | else | |
1071 | REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, | |
1072 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | |
1073 | ||
7067e701 | 1074 | if (on != aniState->ofdmWeakSigDetect) { |
d2182b69 | 1075 | ath_dbg(common, ANI, |
226afe68 JP |
1076 | "** ch %d: ofdm weak signal: %s=>%s\n", |
1077 | chan->channel, | |
7067e701 | 1078 | aniState->ofdmWeakSigDetect ? |
226afe68 JP |
1079 | "on" : "off", |
1080 | on ? "on" : "off"); | |
e36b27af LR |
1081 | if (on) |
1082 | ah->stats.ast_ani_ofdmon++; | |
1083 | else | |
1084 | ah->stats.ast_ani_ofdmoff++; | |
7067e701 | 1085 | aniState->ofdmWeakSigDetect = on; |
e36b27af LR |
1086 | } |
1087 | break; | |
1088 | } | |
1089 | case ATH9K_ANI_FIRSTEP_LEVEL:{ | |
1090 | u32 level = param; | |
1091 | ||
1092 | if (level >= ARRAY_SIZE(firstep_table)) { | |
d2182b69 | 1093 | ath_dbg(common, ANI, |
226afe68 JP |
1094 | "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", |
1095 | level, ARRAY_SIZE(firstep_table)); | |
e36b27af LR |
1096 | return false; |
1097 | } | |
1098 | ||
1099 | /* | |
1100 | * make register setting relative to default | |
1101 | * from INI file & cap value | |
1102 | */ | |
1103 | value = firstep_table[level] - | |
465dce62 | 1104 | firstep_table[ATH9K_ANI_FIRSTEP_LVL] + |
e36b27af LR |
1105 | aniState->iniDef.firstep; |
1106 | if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) | |
1107 | value = ATH9K_SIG_FIRSTEP_SETTING_MIN; | |
1108 | if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) | |
1109 | value = ATH9K_SIG_FIRSTEP_SETTING_MAX; | |
1110 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, | |
1111 | AR_PHY_FIND_SIG_FIRSTEP, | |
1112 | value); | |
1113 | /* | |
1114 | * we need to set first step low register too | |
1115 | * make register setting relative to default | |
1116 | * from INI file & cap value | |
1117 | */ | |
1118 | value2 = firstep_table[level] - | |
465dce62 | 1119 | firstep_table[ATH9K_ANI_FIRSTEP_LVL] + |
e36b27af LR |
1120 | aniState->iniDef.firstepLow; |
1121 | if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) | |
1122 | value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; | |
1123 | if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) | |
1124 | value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; | |
1125 | ||
1126 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, | |
1127 | AR_PHY_FIND_SIG_FIRSTEP_LOW, value2); | |
1128 | ||
1129 | if (level != aniState->firstepLevel) { | |
d2182b69 | 1130 | ath_dbg(common, ANI, |
226afe68 JP |
1131 | "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", |
1132 | chan->channel, | |
1133 | aniState->firstepLevel, | |
1134 | level, | |
465dce62 | 1135 | ATH9K_ANI_FIRSTEP_LVL, |
226afe68 JP |
1136 | value, |
1137 | aniState->iniDef.firstep); | |
d2182b69 | 1138 | ath_dbg(common, ANI, |
226afe68 JP |
1139 | "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", |
1140 | chan->channel, | |
1141 | aniState->firstepLevel, | |
1142 | level, | |
465dce62 | 1143 | ATH9K_ANI_FIRSTEP_LVL, |
226afe68 JP |
1144 | value2, |
1145 | aniState->iniDef.firstepLow); | |
e36b27af LR |
1146 | if (level > aniState->firstepLevel) |
1147 | ah->stats.ast_ani_stepup++; | |
1148 | else if (level < aniState->firstepLevel) | |
1149 | ah->stats.ast_ani_stepdown++; | |
1150 | aniState->firstepLevel = level; | |
1151 | } | |
1152 | break; | |
1153 | } | |
1154 | case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ | |
1155 | u32 level = param; | |
1156 | ||
1157 | if (level >= ARRAY_SIZE(cycpwrThr1_table)) { | |
d2182b69 | 1158 | ath_dbg(common, ANI, |
226afe68 JP |
1159 | "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", |
1160 | level, ARRAY_SIZE(cycpwrThr1_table)); | |
e36b27af LR |
1161 | return false; |
1162 | } | |
1163 | /* | |
1164 | * make register setting relative to default | |
1165 | * from INI file & cap value | |
1166 | */ | |
1167 | value = cycpwrThr1_table[level] - | |
465dce62 | 1168 | cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + |
e36b27af LR |
1169 | aniState->iniDef.cycpwrThr1; |
1170 | if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) | |
1171 | value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; | |
1172 | if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) | |
1173 | value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; | |
1174 | REG_RMW_FIELD(ah, AR_PHY_TIMING5, | |
1175 | AR_PHY_TIMING5_CYCPWR_THR1, | |
1176 | value); | |
1177 | ||
1178 | /* | |
1179 | * set AR_PHY_EXT_CCA for extension channel | |
1180 | * make register setting relative to default | |
1181 | * from INI file & cap value | |
1182 | */ | |
1183 | value2 = cycpwrThr1_table[level] - | |
465dce62 | 1184 | cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + |
e36b27af LR |
1185 | aniState->iniDef.cycpwrThr1Ext; |
1186 | if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) | |
1187 | value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; | |
1188 | if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) | |
1189 | value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; | |
1190 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, | |
1191 | AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2); | |
1192 | ||
1193 | if (level != aniState->spurImmunityLevel) { | |
d2182b69 | 1194 | ath_dbg(common, ANI, |
226afe68 JP |
1195 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", |
1196 | chan->channel, | |
1197 | aniState->spurImmunityLevel, | |
1198 | level, | |
465dce62 | 1199 | ATH9K_ANI_SPUR_IMMUNE_LVL, |
226afe68 JP |
1200 | value, |
1201 | aniState->iniDef.cycpwrThr1); | |
d2182b69 | 1202 | ath_dbg(common, ANI, |
226afe68 JP |
1203 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", |
1204 | chan->channel, | |
1205 | aniState->spurImmunityLevel, | |
1206 | level, | |
465dce62 | 1207 | ATH9K_ANI_SPUR_IMMUNE_LVL, |
226afe68 JP |
1208 | value2, |
1209 | aniState->iniDef.cycpwrThr1Ext); | |
e36b27af LR |
1210 | if (level > aniState->spurImmunityLevel) |
1211 | ah->stats.ast_ani_spurup++; | |
1212 | else if (level < aniState->spurImmunityLevel) | |
1213 | ah->stats.ast_ani_spurdown++; | |
1214 | aniState->spurImmunityLevel = level; | |
1215 | } | |
1216 | break; | |
1217 | } | |
1218 | case ATH9K_ANI_MRC_CCK: | |
1219 | /* | |
1220 | * You should not see this as AR5008, AR9001, AR9002 | |
1221 | * does not have hardware support for MRC CCK. | |
1222 | */ | |
1223 | WARN_ON(1); | |
1224 | break; | |
1225 | case ATH9K_ANI_PRESENT: | |
1226 | break; | |
1227 | default: | |
d2182b69 | 1228 | ath_dbg(common, ANI, "invalid cmd %u\n", cmd); |
e36b27af LR |
1229 | return false; |
1230 | } | |
1231 | ||
d2182b69 | 1232 | ath_dbg(common, ANI, |
226afe68 JP |
1233 | "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", |
1234 | aniState->spurImmunityLevel, | |
7067e701 | 1235 | aniState->ofdmWeakSigDetect ? "on" : "off", |
226afe68 | 1236 | aniState->firstepLevel, |
81b67fd6 | 1237 | aniState->mrcCCK ? "on" : "off", |
226afe68 JP |
1238 | aniState->listenTime, |
1239 | aniState->ofdmPhyErrCount, | |
1240 | aniState->cckPhyErrCount); | |
e36b27af LR |
1241 | return true; |
1242 | } | |
1243 | ||
641d9921 FF |
1244 | static void ar5008_hw_do_getnf(struct ath_hw *ah, |
1245 | int16_t nfarray[NUM_NF_READINGS]) | |
1246 | { | |
641d9921 FF |
1247 | int16_t nf; |
1248 | ||
1249 | nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); | |
7919a57b | 1250 | nfarray[0] = sign_extend32(nf, 8); |
641d9921 FF |
1251 | |
1252 | nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); | |
7919a57b | 1253 | nfarray[1] = sign_extend32(nf, 8); |
641d9921 FF |
1254 | |
1255 | nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); | |
7919a57b | 1256 | nfarray[2] = sign_extend32(nf, 8); |
641d9921 | 1257 | |
866b7780 FF |
1258 | if (!IS_CHAN_HT40(ah->curchan)) |
1259 | return; | |
1260 | ||
641d9921 | 1261 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); |
7919a57b | 1262 | nfarray[3] = sign_extend32(nf, 8); |
641d9921 FF |
1263 | |
1264 | nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); | |
7919a57b | 1265 | nfarray[4] = sign_extend32(nf, 8); |
641d9921 FF |
1266 | |
1267 | nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); | |
7919a57b | 1268 | nfarray[5] = sign_extend32(nf, 8); |
641d9921 FF |
1269 | } |
1270 | ||
e36b27af LR |
1271 | /* |
1272 | * Initialize the ANI register values with default (ini) values. | |
1273 | * This routine is called during a (full) hardware reset after | |
1274 | * all the registers are initialised from the INI. | |
1275 | */ | |
1276 | static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) | |
1277 | { | |
e36b27af LR |
1278 | struct ath_common *common = ath9k_hw_common(ah); |
1279 | struct ath9k_channel *chan = ah->curchan; | |
093115b7 | 1280 | struct ar5416AniState *aniState = &chan->ani; |
e36b27af | 1281 | struct ath9k_ani_default *iniDef; |
e36b27af LR |
1282 | u32 val; |
1283 | ||
e36b27af LR |
1284 | iniDef = &aniState->iniDef; |
1285 | ||
d2182b69 | 1286 | ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n", |
226afe68 JP |
1287 | ah->hw_version.macVersion, |
1288 | ah->hw_version.macRev, | |
1289 | ah->opmode, | |
1290 | chan->channel, | |
1291 | chan->channelFlags); | |
e36b27af LR |
1292 | |
1293 | val = REG_READ(ah, AR_PHY_SFCORR); | |
1294 | iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); | |
1295 | iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); | |
1296 | iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); | |
1297 | ||
1298 | val = REG_READ(ah, AR_PHY_SFCORR_LOW); | |
1299 | iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); | |
1300 | iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); | |
1301 | iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); | |
1302 | ||
1303 | val = REG_READ(ah, AR_PHY_SFCORR_EXT); | |
1304 | iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); | |
1305 | iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); | |
1306 | iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); | |
1307 | iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); | |
1308 | iniDef->firstep = REG_READ_FIELD(ah, | |
1309 | AR_PHY_FIND_SIG, | |
1310 | AR_PHY_FIND_SIG_FIRSTEP); | |
1311 | iniDef->firstepLow = REG_READ_FIELD(ah, | |
1312 | AR_PHY_FIND_SIG_LOW, | |
1313 | AR_PHY_FIND_SIG_FIRSTEP_LOW); | |
1314 | iniDef->cycpwrThr1 = REG_READ_FIELD(ah, | |
1315 | AR_PHY_TIMING5, | |
1316 | AR_PHY_TIMING5_CYCPWR_THR1); | |
1317 | iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, | |
1318 | AR_PHY_EXT_CCA, | |
1319 | AR_PHY_EXT_TIMING5_CYCPWR_THR1); | |
1320 | ||
1321 | /* these levels just got reset to defaults by the INI */ | |
465dce62 FF |
1322 | aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; |
1323 | aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; | |
7067e701 | 1324 | aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG; |
81b67fd6 | 1325 | aniState->mrcCCK = false; /* not available on pre AR9003 */ |
e36b27af LR |
1326 | } |
1327 | ||
f2552e28 FF |
1328 | static void ar5008_hw_set_nf_limits(struct ath_hw *ah) |
1329 | { | |
1330 | ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; | |
1331 | ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; | |
1332 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; | |
1333 | ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; | |
1334 | ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; | |
1335 | ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; | |
1336 | } | |
e36b27af | 1337 | |
4e8c14e9 FF |
1338 | static void ar5008_hw_set_radar_params(struct ath_hw *ah, |
1339 | struct ath_hw_radar_conf *conf) | |
1340 | { | |
1341 | u32 radar_0 = 0, radar_1 = 0; | |
1342 | ||
1343 | if (!conf) { | |
1344 | REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); | |
1345 | return; | |
1346 | } | |
1347 | ||
1348 | radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; | |
1349 | radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); | |
1350 | radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); | |
1351 | radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); | |
1352 | radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); | |
1353 | radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); | |
1354 | ||
1355 | radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; | |
1356 | radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; | |
1357 | radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); | |
1358 | radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); | |
1359 | radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); | |
1360 | ||
1361 | REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); | |
1362 | REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); | |
1363 | if (conf->ext_channel) | |
1364 | REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); | |
1365 | else | |
1366 | REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); | |
1367 | } | |
1368 | ||
c5d0855a FF |
1369 | static void ar5008_hw_set_radar_conf(struct ath_hw *ah) |
1370 | { | |
1371 | struct ath_hw_radar_conf *conf = &ah->radar_conf; | |
1372 | ||
1373 | conf->fir_power = -33; | |
1374 | conf->radar_rssi = 20; | |
1375 | conf->pulse_height = 10; | |
1376 | conf->pulse_rssi = 24; | |
1377 | conf->pulse_inband = 15; | |
1378 | conf->pulse_maxlen = 255; | |
1379 | conf->pulse_inband_step = 12; | |
1380 | conf->radar_inband = 8; | |
1381 | } | |
1382 | ||
8fe65368 LR |
1383 | void ar5008_hw_attach_phy_ops(struct ath_hw *ah) |
1384 | { | |
1385 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | |
07b2fa5a | 1386 | static const u32 ar5416_cca_regs[6] = { |
bbacee13 FF |
1387 | AR_PHY_CCA, |
1388 | AR_PHY_CH1_CCA, | |
1389 | AR_PHY_CH2_CCA, | |
1390 | AR_PHY_EXT_CCA, | |
1391 | AR_PHY_CH1_EXT_CCA, | |
1392 | AR_PHY_CH2_EXT_CCA | |
1393 | }; | |
8fe65368 LR |
1394 | |
1395 | priv_ops->rf_set_freq = ar5008_hw_set_channel; | |
1396 | priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate; | |
1397 | ||
1398 | priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks; | |
1399 | priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks; | |
1400 | priv_ops->set_rf_regs = ar5008_hw_set_rf_regs; | |
1401 | priv_ops->set_channel_regs = ar5008_hw_set_channel_regs; | |
1402 | priv_ops->init_bb = ar5008_hw_init_bb; | |
1403 | priv_ops->process_ini = ar5008_hw_process_ini; | |
1404 | priv_ops->set_rfmode = ar5008_hw_set_rfmode; | |
1405 | priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive; | |
1406 | priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; | |
1407 | priv_ops->rfbus_req = ar5008_hw_rfbus_req; | |
1408 | priv_ops->rfbus_done = ar5008_hw_rfbus_done; | |
8fe65368 | 1409 | priv_ops->restore_chainmask = ar5008_restore_chainmask; |
641d9921 | 1410 | priv_ops->do_getnf = ar5008_hw_do_getnf; |
4e8c14e9 | 1411 | priv_ops->set_radar_params = ar5008_hw_set_radar_params; |
64773964 | 1412 | |
6790ae7a FF |
1413 | priv_ops->ani_control = ar5008_hw_ani_control_new; |
1414 | priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs; | |
e36b27af | 1415 | |
491b209d | 1416 | if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) |
64773964 LR |
1417 | priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; |
1418 | else | |
1419 | priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; | |
f2552e28 FF |
1420 | |
1421 | ar5008_hw_set_nf_limits(ah); | |
c5d0855a | 1422 | ar5008_hw_set_radar_conf(ah); |
bbacee13 | 1423 | memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); |
8fe65368 | 1424 | } |