Commit | Line | Data |
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fa1c114f JS |
1 | /* |
2 | * PHY functions | |
3 | * | |
c6e387a2 | 4 | * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> |
33a31826 | 5 | * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> |
c6e387a2 | 6 | * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> |
8f655dde | 7 | * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> |
fa1c114f JS |
8 | * |
9 | * Permission to use, copy, modify, and distribute this software for any | |
10 | * purpose with or without fee is hereby granted, provided that the above | |
11 | * copyright notice and this permission notice appear in all copies. | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
14 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
15 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
16 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
17 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
18 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
19 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
20 | * | |
21 | */ | |
22 | ||
c6e387a2 NK |
23 | #define _ATH5K_PHY |
24 | ||
fa1c114f | 25 | #include <linux/delay.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
fa1c114f JS |
27 | |
28 | #include "ath5k.h" | |
29 | #include "reg.h" | |
30 | #include "base.h" | |
33a31826 NK |
31 | #include "rfbuffer.h" |
32 | #include "rfgain.h" | |
fa1c114f JS |
33 | |
34 | /* | |
35 | * Used to modify RF Banks before writing them to AR5K_RF_BUFFER | |
36 | */ | |
8892e4ec NK |
37 | static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, |
38 | const struct ath5k_rf_reg *rf_regs, | |
39 | u32 val, u8 reg_id, bool set) | |
fa1c114f | 40 | { |
8892e4ec NK |
41 | const struct ath5k_rf_reg *rfreg = NULL; |
42 | u8 offset, bank, num_bits, col, position; | |
43 | u16 entry; | |
44 | u32 mask, data, last_bit, bits_shifted, first_bit; | |
45 | u32 *rfb; | |
46 | s32 bits_left; | |
fa1c114f JS |
47 | int i; |
48 | ||
49 | data = 0; | |
8892e4ec | 50 | rfb = ah->ah_rf_banks; |
fa1c114f | 51 | |
8892e4ec NK |
52 | for (i = 0; i < ah->ah_rf_regs_count; i++) { |
53 | if (rf_regs[i].index == reg_id) { | |
54 | rfreg = &rf_regs[i]; | |
55 | break; | |
56 | } | |
57 | } | |
58 | ||
59 | if (rfb == NULL || rfreg == NULL) { | |
60 | ATH5K_PRINTF("Rf register not found!\n"); | |
fa1c114f JS |
61 | /* should not happen */ |
62 | return 0; | |
8892e4ec NK |
63 | } |
64 | ||
65 | bank = rfreg->bank; | |
66 | num_bits = rfreg->field.len; | |
67 | first_bit = rfreg->field.pos; | |
68 | col = rfreg->field.col; | |
69 | ||
70 | /* first_bit is an offset from bank's | |
71 | * start. Since we have all banks on | |
72 | * the same array, we use this offset | |
73 | * to mark each bank's start */ | |
74 | offset = ah->ah_offset[bank]; | |
fa1c114f | 75 | |
8892e4ec NK |
76 | /* Boundary check */ |
77 | if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { | |
fa1c114f JS |
78 | ATH5K_PRINTF("invalid values at offset %u\n", offset); |
79 | return 0; | |
80 | } | |
81 | ||
8892e4ec NK |
82 | entry = ((first_bit - 1) / 8) + offset; |
83 | position = (first_bit - 1) % 8; | |
fa1c114f | 84 | |
e9010e2f | 85 | if (set) |
8892e4ec | 86 | data = ath5k_hw_bitswap(val, num_bits); |
fa1c114f | 87 | |
8892e4ec NK |
88 | for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; |
89 | position = 0, entry++) { | |
90 | ||
91 | last_bit = (position + bits_left > 8) ? 8 : | |
92 | position + bits_left; | |
93 | ||
94 | mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << | |
95 | (col * 8); | |
fa1c114f | 96 | |
e9010e2f | 97 | if (set) { |
8892e4ec NK |
98 | rfb[entry] &= ~mask; |
99 | rfb[entry] |= ((data << position) << (col * 8)) & mask; | |
fa1c114f JS |
100 | data >>= (8 - position); |
101 | } else { | |
8892e4ec NK |
102 | data |= (((rfb[entry] & mask) >> (col * 8)) >> position) |
103 | << bits_shifted; | |
104 | bits_shifted += last_bit - position; | |
fa1c114f JS |
105 | } |
106 | ||
8892e4ec | 107 | bits_left -= 8 - position; |
fa1c114f JS |
108 | } |
109 | ||
8892e4ec | 110 | data = set ? 1 : ath5k_hw_bitswap(data, num_bits); |
fa1c114f JS |
111 | |
112 | return data; | |
113 | } | |
114 | ||
6f3b414a NK |
115 | /**********************\ |
116 | * RF Gain optimization * | |
117 | \**********************/ | |
118 | ||
119 | /* | |
120 | * This code is used to optimize rf gain on different environments | |
af901ca1 | 121 | * (temperature mostly) based on feedback from a power detector. |
6f3b414a NK |
122 | * |
123 | * It's only used on RF5111 and RF5112, later RF chips seem to have | |
124 | * auto adjustment on hw -notice they have a much smaller BANK 7 and | |
125 | * no gain optimization ladder-. | |
126 | * | |
127 | * For more infos check out this patent doc | |
128 | * http://www.freepatentsonline.com/7400691.html | |
129 | * | |
130 | * This paper describes power drops as seen on the receiver due to | |
131 | * probe packets | |
132 | * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues | |
133 | * %20of%20Power%20Control.pdf | |
134 | * | |
135 | * And this is the MadWiFi bug entry related to the above | |
136 | * http://madwifi-project.org/ticket/1659 | |
137 | * with various measurements and diagrams | |
138 | * | |
139 | * TODO: Deal with power drops due to probes by setting an apropriate | |
140 | * tx power on the probe packets ! Make this part of the calibration process. | |
141 | */ | |
142 | ||
143 | /* Initialize ah_gain durring attach */ | |
144 | int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) | |
145 | { | |
146 | /* Initialize the gain optimization values */ | |
147 | switch (ah->ah_radio) { | |
148 | case AR5K_RF5111: | |
149 | ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; | |
150 | ah->ah_gain.g_low = 20; | |
151 | ah->ah_gain.g_high = 35; | |
152 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; | |
153 | break; | |
154 | case AR5K_RF5112: | |
155 | ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; | |
156 | ah->ah_gain.g_low = 20; | |
157 | ah->ah_gain.g_high = 85; | |
158 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; | |
159 | break; | |
160 | default: | |
161 | return -EINVAL; | |
162 | } | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
167 | /* Schedule a gain probe check on the next transmited packet. | |
168 | * That means our next packet is going to be sent with lower | |
169 | * tx power and a Peak to Average Power Detector (PAPD) will try | |
170 | * to measure the gain. | |
171 | * | |
6f3b414a NK |
172 | * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) |
173 | * just after we enable the probe so that we don't mess with | |
174 | * standard traffic ? Maybe it's time to use sw interrupts and | |
175 | * a probe tasklet !!! | |
176 | */ | |
177 | static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) | |
178 | { | |
179 | ||
180 | /* Skip if gain calibration is inactive or | |
181 | * we already handle a probe request */ | |
182 | if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) | |
183 | return; | |
184 | ||
8f655dde NK |
185 | /* Send the packet with 2dB below max power as |
186 | * patent doc suggest */ | |
a0823810 | 187 | ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, |
6f3b414a NK |
188 | AR5K_PHY_PAPD_PROBE_TXPOWER) | |
189 | AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); | |
190 | ||
191 | ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; | |
192 | ||
193 | } | |
194 | ||
195 | /* Calculate gain_F measurement correction | |
196 | * based on the current step for RF5112 rev. 2 */ | |
197 | static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) | |
fa1c114f JS |
198 | { |
199 | u32 mix, step; | |
200 | u32 *rf; | |
6f3b414a NK |
201 | const struct ath5k_gain_opt *go; |
202 | const struct ath5k_gain_opt_step *g_step; | |
8892e4ec | 203 | const struct ath5k_rf_reg *rf_regs; |
6f3b414a NK |
204 | |
205 | /* Only RF5112 Rev. 2 supports it */ | |
206 | if ((ah->ah_radio != AR5K_RF5112) || | |
207 | (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) | |
208 | return 0; | |
209 | ||
210 | go = &rfgain_opt_5112; | |
8892e4ec NK |
211 | rf_regs = rf_regs_5112a; |
212 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); | |
6f3b414a NK |
213 | |
214 | g_step = &go->go_step[ah->ah_gain.g_step_idx]; | |
fa1c114f JS |
215 | |
216 | if (ah->ah_rf_banks == NULL) | |
217 | return 0; | |
218 | ||
219 | rf = ah->ah_rf_banks; | |
220 | ah->ah_gain.g_f_corr = 0; | |
221 | ||
6f3b414a | 222 | /* No VGA (Variable Gain Amplifier) override, skip */ |
8892e4ec | 223 | if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) |
fa1c114f JS |
224 | return 0; |
225 | ||
6f3b414a | 226 | /* Mix gain stepping */ |
8892e4ec | 227 | step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); |
6f3b414a NK |
228 | |
229 | /* Mix gain override */ | |
230 | mix = g_step->gos_param[0]; | |
fa1c114f JS |
231 | |
232 | switch (mix) { | |
233 | case 3: | |
234 | ah->ah_gain.g_f_corr = step * 2; | |
235 | break; | |
236 | case 2: | |
237 | ah->ah_gain.g_f_corr = (step - 5) * 2; | |
238 | break; | |
239 | case 1: | |
240 | ah->ah_gain.g_f_corr = step; | |
241 | break; | |
242 | default: | |
243 | ah->ah_gain.g_f_corr = 0; | |
244 | break; | |
245 | } | |
246 | ||
247 | return ah->ah_gain.g_f_corr; | |
248 | } | |
249 | ||
6f3b414a NK |
250 | /* Check if current gain_F measurement is in the range of our |
251 | * power detector windows. If we get a measurement outside range | |
252 | * we know it's not accurate (detectors can't measure anything outside | |
253 | * their detection window) so we must ignore it */ | |
254 | static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) | |
fa1c114f | 255 | { |
8892e4ec | 256 | const struct ath5k_rf_reg *rf_regs; |
6f3b414a | 257 | u32 step, mix_ovr, level[4]; |
fa1c114f JS |
258 | u32 *rf; |
259 | ||
260 | if (ah->ah_rf_banks == NULL) | |
261 | return false; | |
262 | ||
263 | rf = ah->ah_rf_banks; | |
264 | ||
265 | if (ah->ah_radio == AR5K_RF5111) { | |
8892e4ec NK |
266 | |
267 | rf_regs = rf_regs_5111; | |
268 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); | |
269 | ||
270 | step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, | |
271 | false); | |
272 | ||
fa1c114f | 273 | level[0] = 0; |
6f3b414a NK |
274 | level[1] = (step == 63) ? 50 : step + 4; |
275 | level[2] = (step != 63) ? 64 : level[0]; | |
276 | level[3] = level[2] + 50 ; | |
fa1c114f JS |
277 | |
278 | ah->ah_gain.g_high = level[3] - | |
6f3b414a | 279 | (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); |
fa1c114f | 280 | ah->ah_gain.g_low = level[0] + |
6f3b414a | 281 | (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); |
fa1c114f | 282 | } else { |
8892e4ec NK |
283 | |
284 | rf_regs = rf_regs_5112; | |
285 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); | |
286 | ||
287 | mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, | |
288 | false); | |
289 | ||
fa1c114f JS |
290 | level[0] = level[2] = 0; |
291 | ||
6f3b414a | 292 | if (mix_ovr == 1) { |
fa1c114f JS |
293 | level[1] = level[3] = 83; |
294 | } else { | |
295 | level[1] = level[3] = 107; | |
296 | ah->ah_gain.g_high = 55; | |
297 | } | |
298 | } | |
299 | ||
300 | return (ah->ah_gain.g_current >= level[0] && | |
301 | ah->ah_gain.g_current <= level[1]) || | |
302 | (ah->ah_gain.g_current >= level[2] && | |
303 | ah->ah_gain.g_current <= level[3]); | |
304 | } | |
305 | ||
6f3b414a NK |
306 | /* Perform gain_F adjustment by choosing the right set |
307 | * of parameters from rf gain optimization ladder */ | |
308 | static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) | |
fa1c114f JS |
309 | { |
310 | const struct ath5k_gain_opt *go; | |
6f3b414a | 311 | const struct ath5k_gain_opt_step *g_step; |
fa1c114f JS |
312 | int ret = 0; |
313 | ||
314 | switch (ah->ah_radio) { | |
315 | case AR5K_RF5111: | |
316 | go = &rfgain_opt_5111; | |
317 | break; | |
318 | case AR5K_RF5112: | |
fa1c114f JS |
319 | go = &rfgain_opt_5112; |
320 | break; | |
321 | default: | |
322 | return 0; | |
323 | } | |
324 | ||
6f3b414a | 325 | g_step = &go->go_step[ah->ah_gain.g_step_idx]; |
fa1c114f JS |
326 | |
327 | if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { | |
6f3b414a NK |
328 | |
329 | /* Reached maximum */ | |
fa1c114f JS |
330 | if (ah->ah_gain.g_step_idx == 0) |
331 | return -1; | |
6f3b414a | 332 | |
fa1c114f JS |
333 | for (ah->ah_gain.g_target = ah->ah_gain.g_current; |
334 | ah->ah_gain.g_target >= ah->ah_gain.g_high && | |
335 | ah->ah_gain.g_step_idx > 0; | |
6f3b414a | 336 | g_step = &go->go_step[ah->ah_gain.g_step_idx]) |
fa1c114f JS |
337 | ah->ah_gain.g_target -= 2 * |
338 | (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - | |
6f3b414a | 339 | g_step->gos_gain); |
fa1c114f JS |
340 | |
341 | ret = 1; | |
342 | goto done; | |
343 | } | |
344 | ||
345 | if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { | |
6f3b414a NK |
346 | |
347 | /* Reached minimum */ | |
fa1c114f JS |
348 | if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) |
349 | return -2; | |
6f3b414a | 350 | |
fa1c114f JS |
351 | for (ah->ah_gain.g_target = ah->ah_gain.g_current; |
352 | ah->ah_gain.g_target <= ah->ah_gain.g_low && | |
353 | ah->ah_gain.g_step_idx < go->go_steps_count-1; | |
6f3b414a | 354 | g_step = &go->go_step[ah->ah_gain.g_step_idx]) |
fa1c114f JS |
355 | ah->ah_gain.g_target -= 2 * |
356 | (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - | |
6f3b414a | 357 | g_step->gos_gain); |
fa1c114f JS |
358 | |
359 | ret = 2; | |
360 | goto done; | |
361 | } | |
362 | ||
363 | done: | |
364 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, | |
365 | "ret %d, gain step %u, current gain %u, target gain %u\n", | |
366 | ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, | |
367 | ah->ah_gain.g_target); | |
368 | ||
369 | return ret; | |
370 | } | |
371 | ||
6f3b414a NK |
372 | /* Main callback for thermal rf gain calibration engine |
373 | * Check for a new gain reading and schedule an adjustment | |
374 | * if needed. | |
375 | * | |
376 | * TODO: Use sw interrupt to schedule reset if gain_F needs | |
377 | * adjustment */ | |
378 | enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) | |
379 | { | |
380 | u32 data, type; | |
381 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; | |
382 | ||
383 | ATH5K_TRACE(ah->ah_sc); | |
384 | ||
385 | if (ah->ah_rf_banks == NULL || | |
386 | ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) | |
387 | return AR5K_RFGAIN_INACTIVE; | |
388 | ||
389 | /* No check requested, either engine is inactive | |
390 | * or an adjustment is already requested */ | |
391 | if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) | |
392 | goto done; | |
393 | ||
394 | /* Read the PAPD (Peak to Average Power Detector) | |
395 | * register */ | |
396 | data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); | |
397 | ||
398 | /* No probe is scheduled, read gain_F measurement */ | |
399 | if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { | |
400 | ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; | |
401 | type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); | |
402 | ||
403 | /* If tx packet is CCK correct the gain_F measurement | |
404 | * by cck ofdm gain delta */ | |
405 | if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { | |
406 | if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) | |
407 | ah->ah_gain.g_current += | |
408 | ee->ee_cck_ofdm_gain_delta; | |
409 | else | |
410 | ah->ah_gain.g_current += | |
411 | AR5K_GAIN_CCK_PROBE_CORR; | |
412 | } | |
413 | ||
414 | /* Further correct gain_F measurement for | |
415 | * RF5112A radios */ | |
416 | if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { | |
417 | ath5k_hw_rf_gainf_corr(ah); | |
418 | ah->ah_gain.g_current = | |
419 | ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? | |
420 | (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : | |
421 | 0; | |
422 | } | |
423 | ||
424 | /* Check if measurement is ok and if we need | |
425 | * to adjust gain, schedule a gain adjustment, | |
426 | * else switch back to the acive state */ | |
427 | if (ath5k_hw_rf_check_gainf_readback(ah) && | |
428 | AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && | |
429 | ath5k_hw_rf_gainf_adjust(ah)) { | |
430 | ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; | |
431 | } else { | |
432 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; | |
433 | } | |
434 | } | |
435 | ||
436 | done: | |
437 | return ah->ah_gain.g_state; | |
438 | } | |
439 | ||
440 | /* Write initial rf gain table to set the RF sensitivity | |
441 | * this one works on all RF chips and has nothing to do | |
442 | * with gain_F calibration */ | |
443 | int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq) | |
444 | { | |
445 | const struct ath5k_ini_rfgain *ath5k_rfg; | |
446 | unsigned int i, size; | |
447 | ||
448 | switch (ah->ah_radio) { | |
449 | case AR5K_RF5111: | |
450 | ath5k_rfg = rfgain_5111; | |
451 | size = ARRAY_SIZE(rfgain_5111); | |
452 | break; | |
453 | case AR5K_RF5112: | |
454 | ath5k_rfg = rfgain_5112; | |
455 | size = ARRAY_SIZE(rfgain_5112); | |
456 | break; | |
457 | case AR5K_RF2413: | |
458 | ath5k_rfg = rfgain_2413; | |
459 | size = ARRAY_SIZE(rfgain_2413); | |
460 | break; | |
461 | case AR5K_RF2316: | |
462 | ath5k_rfg = rfgain_2316; | |
463 | size = ARRAY_SIZE(rfgain_2316); | |
464 | break; | |
465 | case AR5K_RF5413: | |
466 | ath5k_rfg = rfgain_5413; | |
467 | size = ARRAY_SIZE(rfgain_5413); | |
468 | break; | |
469 | case AR5K_RF2317: | |
470 | case AR5K_RF2425: | |
471 | ath5k_rfg = rfgain_2425; | |
472 | size = ARRAY_SIZE(rfgain_2425); | |
473 | break; | |
474 | default: | |
475 | return -EINVAL; | |
476 | } | |
477 | ||
478 | switch (freq) { | |
479 | case AR5K_INI_RFGAIN_2GHZ: | |
480 | case AR5K_INI_RFGAIN_5GHZ: | |
481 | break; | |
482 | default: | |
483 | return -EINVAL; | |
484 | } | |
485 | ||
486 | for (i = 0; i < size; i++) { | |
487 | AR5K_REG_WAIT(i); | |
488 | ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], | |
489 | (u32)ath5k_rfg[i].rfg_register); | |
490 | } | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
495 | ||
496 | ||
497 | /********************\ | |
498 | * RF Registers setup * | |
499 | \********************/ | |
500 | ||
8892e4ec | 501 | |
fa1c114f | 502 | /* |
8892e4ec | 503 | * Setup RF registers by writing rf buffer on hw |
fa1c114f | 504 | */ |
8892e4ec NK |
505 | int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, |
506 | unsigned int mode) | |
fa1c114f | 507 | { |
8892e4ec NK |
508 | const struct ath5k_rf_reg *rf_regs; |
509 | const struct ath5k_ini_rfbuffer *ini_rfb; | |
510 | const struct ath5k_gain_opt *go = NULL; | |
511 | const struct ath5k_gain_opt_step *g_step; | |
fa1c114f | 512 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
8892e4ec NK |
513 | u8 ee_mode = 0; |
514 | u32 *rfb; | |
515 | int i, obdb = -1, bank = -1; | |
fa1c114f | 516 | |
8892e4ec NK |
517 | switch (ah->ah_radio) { |
518 | case AR5K_RF5111: | |
519 | rf_regs = rf_regs_5111; | |
520 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); | |
521 | ini_rfb = rfb_5111; | |
522 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); | |
523 | go = &rfgain_opt_5111; | |
524 | break; | |
525 | case AR5K_RF5112: | |
526 | if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { | |
527 | rf_regs = rf_regs_5112a; | |
528 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); | |
529 | ini_rfb = rfb_5112a; | |
530 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); | |
531 | } else { | |
532 | rf_regs = rf_regs_5112; | |
533 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); | |
534 | ini_rfb = rfb_5112; | |
535 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); | |
536 | } | |
537 | go = &rfgain_opt_5112; | |
538 | break; | |
539 | case AR5K_RF2413: | |
540 | rf_regs = rf_regs_2413; | |
541 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); | |
542 | ini_rfb = rfb_2413; | |
543 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); | |
544 | break; | |
545 | case AR5K_RF2316: | |
546 | rf_regs = rf_regs_2316; | |
547 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); | |
548 | ini_rfb = rfb_2316; | |
549 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); | |
550 | break; | |
551 | case AR5K_RF5413: | |
552 | rf_regs = rf_regs_5413; | |
553 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); | |
554 | ini_rfb = rfb_5413; | |
555 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); | |
556 | break; | |
557 | case AR5K_RF2317: | |
558 | rf_regs = rf_regs_2425; | |
559 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); | |
560 | ini_rfb = rfb_2317; | |
561 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); | |
562 | break; | |
563 | case AR5K_RF2425: | |
564 | rf_regs = rf_regs_2425; | |
565 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); | |
566 | if (ah->ah_mac_srev < AR5K_SREV_AR2417) { | |
567 | ini_rfb = rfb_2425; | |
568 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); | |
569 | } else { | |
570 | ini_rfb = rfb_2417; | |
571 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); | |
572 | } | |
573 | break; | |
574 | default: | |
575 | return -EINVAL; | |
576 | } | |
fa1c114f | 577 | |
8892e4ec NK |
578 | /* If it's the first time we set rf buffer, allocate |
579 | * ah->ah_rf_banks based on ah->ah_rf_banks_size | |
580 | * we set above */ | |
581 | if (ah->ah_rf_banks == NULL) { | |
582 | ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, | |
583 | GFP_KERNEL); | |
584 | if (ah->ah_rf_banks == NULL) { | |
585 | ATH5K_ERR(ah->ah_sc, "out of memory\n"); | |
586 | return -ENOMEM; | |
587 | } | |
588 | } | |
fa1c114f JS |
589 | |
590 | /* Copy values to modify them */ | |
8892e4ec NK |
591 | rfb = ah->ah_rf_banks; |
592 | ||
593 | for (i = 0; i < ah->ah_rf_banks_size; i++) { | |
594 | if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { | |
fa1c114f JS |
595 | ATH5K_ERR(ah->ah_sc, "invalid bank\n"); |
596 | return -EINVAL; | |
597 | } | |
598 | ||
8892e4ec NK |
599 | /* Bank changed, write down the offset */ |
600 | if (bank != ini_rfb[i].rfb_bank) { | |
601 | bank = ini_rfb[i].rfb_bank; | |
fa1c114f JS |
602 | ah->ah_offset[bank] = i; |
603 | } | |
604 | ||
8892e4ec | 605 | rfb[i] = ini_rfb[i].rfb_mode_data[mode]; |
fa1c114f JS |
606 | } |
607 | ||
8892e4ec | 608 | /* Set Output and Driver bias current (OB/DB) */ |
d8ee398d | 609 | if (channel->hw_value & CHANNEL_2GHZ) { |
8892e4ec | 610 | |
d8ee398d | 611 | if (channel->hw_value & CHANNEL_CCK) |
fa1c114f JS |
612 | ee_mode = AR5K_EEPROM_MODE_11B; |
613 | else | |
614 | ee_mode = AR5K_EEPROM_MODE_11G; | |
fa1c114f | 615 | |
8892e4ec NK |
616 | /* For RF511X/RF211X combination we |
617 | * use b_OB and b_DB parameters stored | |
618 | * in eeprom on ee->ee_ob[ee_mode][0] | |
619 | * | |
620 | * For all other chips we use OB/DB for 2Ghz | |
621 | * stored in the b/g modal section just like | |
622 | * 802.11a on ee->ee_ob[ee_mode][1] */ | |
623 | if ((ah->ah_radio == AR5K_RF5111) || | |
624 | (ah->ah_radio == AR5K_RF5112)) | |
625 | obdb = 0; | |
626 | else | |
627 | obdb = 1; | |
fa1c114f | 628 | |
8892e4ec NK |
629 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], |
630 | AR5K_RF_OB_2GHZ, true); | |
fa1c114f | 631 | |
8892e4ec NK |
632 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], |
633 | AR5K_RF_DB_2GHZ, true); | |
634 | ||
635 | /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ | |
636 | } else if ((channel->hw_value & CHANNEL_5GHZ) || | |
637 | (ah->ah_radio == AR5K_RF5111)) { | |
638 | ||
639 | /* For 11a, Turbo and XR we need to choose | |
640 | * OB/DB based on frequency range */ | |
fa1c114f | 641 | ee_mode = AR5K_EEPROM_MODE_11A; |
d8ee398d LR |
642 | obdb = channel->center_freq >= 5725 ? 3 : |
643 | (channel->center_freq >= 5500 ? 2 : | |
644 | (channel->center_freq >= 5260 ? 1 : | |
645 | (channel->center_freq > 4000 ? 0 : -1))); | |
fa1c114f | 646 | |
8892e4ec | 647 | if (obdb < 0) |
fa1c114f JS |
648 | return -EINVAL; |
649 | ||
8892e4ec NK |
650 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], |
651 | AR5K_RF_OB_5GHZ, true); | |
652 | ||
653 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], | |
654 | AR5K_RF_DB_5GHZ, true); | |
fa1c114f JS |
655 | } |
656 | ||
8892e4ec | 657 | g_step = &go->go_step[ah->ah_gain.g_step_idx]; |
fa1c114f | 658 | |
8892e4ec NK |
659 | /* Bank Modifications (chip-specific) */ |
660 | if (ah->ah_radio == AR5K_RF5111) { | |
fa1c114f | 661 | |
8892e4ec NK |
662 | /* Set gain_F settings according to current step */ |
663 | if (channel->hw_value & CHANNEL_OFDM) { | |
fa1c114f | 664 | |
8892e4ec NK |
665 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, |
666 | AR5K_PHY_FRAME_CTL_TX_CLIP, | |
667 | g_step->gos_param[0]); | |
fa1c114f | 668 | |
8892e4ec NK |
669 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], |
670 | AR5K_RF_PWD_90, true); | |
fa1c114f | 671 | |
8892e4ec NK |
672 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], |
673 | AR5K_RF_PWD_84, true); | |
fa1c114f | 674 | |
8892e4ec NK |
675 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], |
676 | AR5K_RF_RFGAIN_SEL, true); | |
fa1c114f | 677 | |
8892e4ec NK |
678 | /* We programmed gain_F parameters, switch back |
679 | * to active state */ | |
680 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; | |
6f3b414a | 681 | |
8892e4ec | 682 | } |
fa1c114f | 683 | |
8892e4ec | 684 | /* Bank 6/7 setup */ |
fa1c114f | 685 | |
8892e4ec NK |
686 | ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], |
687 | AR5K_RF_PWD_XPD, true); | |
fa1c114f | 688 | |
8892e4ec NK |
689 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], |
690 | AR5K_RF_XPD_GAIN, true); | |
fa1c114f | 691 | |
8892e4ec NK |
692 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], |
693 | AR5K_RF_GAIN_I, true); | |
fa1c114f | 694 | |
8892e4ec NK |
695 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], |
696 | AR5K_RF_PLO_SEL, true); | |
fa1c114f | 697 | |
8892e4ec | 698 | /* TODO: Half/quarter channel support */ |
fa1c114f JS |
699 | } |
700 | ||
8892e4ec | 701 | if (ah->ah_radio == AR5K_RF5112) { |
fa1c114f | 702 | |
8892e4ec NK |
703 | /* Set gain_F settings according to current step */ |
704 | if (channel->hw_value & CHANNEL_OFDM) { | |
fa1c114f | 705 | |
8892e4ec NK |
706 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], |
707 | AR5K_RF_MIXGAIN_OVR, true); | |
fa1c114f | 708 | |
8892e4ec NK |
709 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], |
710 | AR5K_RF_PWD_138, true); | |
e71c9fac | 711 | |
8892e4ec NK |
712 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], |
713 | AR5K_RF_PWD_137, true); | |
fa1c114f | 714 | |
8892e4ec NK |
715 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], |
716 | AR5K_RF_PWD_136, true); | |
fa1c114f | 717 | |
8892e4ec NK |
718 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], |
719 | AR5K_RF_PWD_132, true); | |
fa1c114f | 720 | |
8892e4ec NK |
721 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], |
722 | AR5K_RF_PWD_131, true); | |
fa1c114f | 723 | |
8892e4ec NK |
724 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], |
725 | AR5K_RF_PWD_130, true); | |
fa1c114f | 726 | |
8892e4ec NK |
727 | /* We programmed gain_F parameters, switch back |
728 | * to active state */ | |
729 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; | |
730 | } | |
fa1c114f | 731 | |
8892e4ec | 732 | /* Bank 6/7 setup */ |
6f3b414a | 733 | |
8892e4ec NK |
734 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], |
735 | AR5K_RF_XPD_SEL, true); | |
6f3b414a | 736 | |
8892e4ec NK |
737 | if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { |
738 | /* Rev. 1 supports only one xpd */ | |
739 | ath5k_hw_rfb_op(ah, rf_regs, | |
740 | ee->ee_x_gain[ee_mode], | |
741 | AR5K_RF_XPD_GAIN, true); | |
fa1c114f | 742 | |
8892e4ec | 743 | } else { |
d1cb0bda NK |
744 | u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; |
745 | if (ee->ee_pd_gains[ee_mode] > 1) { | |
746 | ath5k_hw_rfb_op(ah, rf_regs, | |
747 | pdg_curve_to_idx[0], | |
8892e4ec | 748 | AR5K_RF_PD_GAIN_LO, true); |
d1cb0bda NK |
749 | ath5k_hw_rfb_op(ah, rf_regs, |
750 | pdg_curve_to_idx[1], | |
8892e4ec | 751 | AR5K_RF_PD_GAIN_HI, true); |
d1cb0bda NK |
752 | } else { |
753 | ath5k_hw_rfb_op(ah, rf_regs, | |
754 | pdg_curve_to_idx[0], | |
755 | AR5K_RF_PD_GAIN_LO, true); | |
756 | ath5k_hw_rfb_op(ah, rf_regs, | |
757 | pdg_curve_to_idx[0], | |
758 | AR5K_RF_PD_GAIN_HI, true); | |
759 | } | |
fa1c114f | 760 | |
8892e4ec NK |
761 | /* Lower synth voltage on Rev 2 */ |
762 | ath5k_hw_rfb_op(ah, rf_regs, 2, | |
763 | AR5K_RF_HIGH_VC_CP, true); | |
fa1c114f | 764 | |
8892e4ec NK |
765 | ath5k_hw_rfb_op(ah, rf_regs, 2, |
766 | AR5K_RF_MID_VC_CP, true); | |
fa1c114f | 767 | |
8892e4ec NK |
768 | ath5k_hw_rfb_op(ah, rf_regs, 2, |
769 | AR5K_RF_LOW_VC_CP, true); | |
136bfc79 | 770 | |
8892e4ec NK |
771 | ath5k_hw_rfb_op(ah, rf_regs, 2, |
772 | AR5K_RF_PUSH_UP, true); | |
136bfc79 | 773 | |
8892e4ec NK |
774 | /* Decrease power consumption on 5213+ BaseBand */ |
775 | if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { | |
776 | ath5k_hw_rfb_op(ah, rf_regs, 1, | |
777 | AR5K_RF_PAD2GND, true); | |
136bfc79 | 778 | |
8892e4ec NK |
779 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
780 | AR5K_RF_XB2_LVL, true); | |
136bfc79 | 781 | |
8892e4ec NK |
782 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
783 | AR5K_RF_XB5_LVL, true); | |
fa1c114f | 784 | |
8892e4ec NK |
785 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
786 | AR5K_RF_PWD_167, true); | |
fa1c114f | 787 | |
8892e4ec NK |
788 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
789 | AR5K_RF_PWD_166, true); | |
790 | } | |
fa1c114f JS |
791 | } |
792 | ||
8892e4ec NK |
793 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], |
794 | AR5K_RF_GAIN_I, true); | |
fa1c114f | 795 | |
8892e4ec | 796 | /* TODO: Half/quarter channel support */ |
fa1c114f | 797 | |
8892e4ec | 798 | } |
fa1c114f | 799 | |
8892e4ec NK |
800 | if (ah->ah_radio == AR5K_RF5413 && |
801 | channel->hw_value & CHANNEL_2GHZ) { | |
fa1c114f | 802 | |
8892e4ec NK |
803 | ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, |
804 | true); | |
fa1c114f | 805 | |
8892e4ec NK |
806 | /* Set optimum value for early revisions (on pci-e chips) */ |
807 | if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && | |
808 | ah->ah_mac_srev < AR5K_SREV_AR5413) | |
809 | ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), | |
810 | AR5K_RF_PWD_ICLOBUF_2G, true); | |
fa1c114f | 811 | |
fa1c114f JS |
812 | } |
813 | ||
8892e4ec NK |
814 | /* Write RF banks on hw */ |
815 | for (i = 0; i < ah->ah_rf_banks_size; i++) { | |
816 | AR5K_REG_WAIT(i); | |
817 | ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); | |
818 | } | |
fa1c114f | 819 | |
8892e4ec | 820 | return 0; |
fa1c114f JS |
821 | } |
822 | ||
fa1c114f | 823 | |
fa1c114f JS |
824 | /**************************\ |
825 | PHY/RF channel functions | |
826 | \**************************/ | |
827 | ||
828 | /* | |
829 | * Check if a channel is supported | |
830 | */ | |
831 | bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) | |
832 | { | |
833 | /* Check if the channel is in our supported range */ | |
834 | if (flags & CHANNEL_2GHZ) { | |
835 | if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && | |
836 | (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) | |
837 | return true; | |
838 | } else if (flags & CHANNEL_5GHZ) | |
839 | if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && | |
840 | (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) | |
841 | return true; | |
842 | ||
843 | return false; | |
844 | } | |
845 | ||
846 | /* | |
847 | * Convertion needed for RF5110 | |
848 | */ | |
849 | static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) | |
850 | { | |
851 | u32 athchan; | |
852 | ||
853 | /* | |
854 | * Convert IEEE channel/MHz to an internal channel value used | |
855 | * by the AR5210 chipset. This has not been verified with | |
856 | * newer chipsets like the AR5212A who have a completely | |
857 | * different RF/PHY part. | |
858 | */ | |
400ec45a LR |
859 | athchan = (ath5k_hw_bitswap( |
860 | (ieee80211_frequency_to_channel( | |
861 | channel->center_freq) - 24) / 2, 5) | |
862 | << 1) | (1 << 6) | 0x1; | |
fa1c114f JS |
863 | return athchan; |
864 | } | |
865 | ||
866 | /* | |
867 | * Set channel on RF5110 | |
868 | */ | |
869 | static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, | |
870 | struct ieee80211_channel *channel) | |
871 | { | |
872 | u32 data; | |
873 | ||
874 | /* | |
875 | * Set the channel and wait | |
876 | */ | |
877 | data = ath5k_hw_rf5110_chan2athchan(channel); | |
878 | ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); | |
879 | ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); | |
880 | mdelay(1); | |
881 | ||
882 | return 0; | |
883 | } | |
884 | ||
885 | /* | |
886 | * Convertion needed for 5111 | |
887 | */ | |
888 | static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, | |
889 | struct ath5k_athchan_2ghz *athchan) | |
890 | { | |
891 | int channel; | |
892 | ||
893 | /* Cast this value to catch negative channel numbers (>= -19) */ | |
894 | channel = (int)ieee; | |
895 | ||
896 | /* | |
897 | * Map 2GHz IEEE channel to 5GHz Atheros channel | |
898 | */ | |
899 | if (channel <= 13) { | |
900 | athchan->a2_athchan = 115 + channel; | |
901 | athchan->a2_flags = 0x46; | |
902 | } else if (channel == 14) { | |
903 | athchan->a2_athchan = 124; | |
904 | athchan->a2_flags = 0x44; | |
905 | } else if (channel >= 15 && channel <= 26) { | |
906 | athchan->a2_athchan = ((channel - 14) * 4) + 132; | |
907 | athchan->a2_flags = 0x46; | |
908 | } else | |
909 | return -EINVAL; | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
914 | /* | |
915 | * Set channel on 5111 | |
916 | */ | |
917 | static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, | |
918 | struct ieee80211_channel *channel) | |
919 | { | |
920 | struct ath5k_athchan_2ghz ath5k_channel_2ghz; | |
400ec45a LR |
921 | unsigned int ath5k_channel = |
922 | ieee80211_frequency_to_channel(channel->center_freq); | |
fa1c114f JS |
923 | u32 data0, data1, clock; |
924 | int ret; | |
925 | ||
926 | /* | |
927 | * Set the channel on the RF5111 radio | |
928 | */ | |
929 | data0 = data1 = 0; | |
930 | ||
d8ee398d | 931 | if (channel->hw_value & CHANNEL_2GHZ) { |
fa1c114f | 932 | /* Map 2GHz channel to 5GHz Atheros channel ID */ |
400ec45a LR |
933 | ret = ath5k_hw_rf5111_chan2athchan( |
934 | ieee80211_frequency_to_channel(channel->center_freq), | |
935 | &ath5k_channel_2ghz); | |
fa1c114f JS |
936 | if (ret) |
937 | return ret; | |
938 | ||
939 | ath5k_channel = ath5k_channel_2ghz.a2_athchan; | |
940 | data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) | |
941 | << 5) | (1 << 4); | |
942 | } | |
943 | ||
944 | if (ath5k_channel < 145 || !(ath5k_channel & 1)) { | |
945 | clock = 1; | |
946 | data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | | |
947 | (clock << 1) | (1 << 10) | 1; | |
948 | } else { | |
949 | clock = 0; | |
950 | data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) | |
951 | << 2) | (clock << 1) | (1 << 10) | 1; | |
952 | } | |
953 | ||
954 | ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), | |
955 | AR5K_RF_BUFFER); | |
956 | ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), | |
957 | AR5K_RF_BUFFER_CONTROL_3); | |
958 | ||
959 | return 0; | |
960 | } | |
961 | ||
962 | /* | |
963 | * Set channel on 5112 and newer | |
964 | */ | |
965 | static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, | |
966 | struct ieee80211_channel *channel) | |
967 | { | |
968 | u32 data, data0, data1, data2; | |
969 | u16 c; | |
970 | ||
971 | data = data0 = data1 = data2 = 0; | |
d8ee398d | 972 | c = channel->center_freq; |
fa1c114f | 973 | |
fa1c114f JS |
974 | if (c < 4800) { |
975 | if (!((c - 2224) % 5)) { | |
976 | data0 = ((2 * (c - 704)) - 3040) / 10; | |
977 | data1 = 1; | |
978 | } else if (!((c - 2192) % 5)) { | |
979 | data0 = ((2 * (c - 672)) - 3040) / 10; | |
980 | data1 = 0; | |
981 | } else | |
982 | return -EINVAL; | |
983 | ||
984 | data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); | |
cc6323c7 | 985 | } else if ((c - (c % 5)) != 2 || c > 5435) { |
fa1c114f JS |
986 | if (!(c % 20) && c >= 5120) { |
987 | data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); | |
988 | data2 = ath5k_hw_bitswap(3, 2); | |
989 | } else if (!(c % 10)) { | |
990 | data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); | |
991 | data2 = ath5k_hw_bitswap(2, 2); | |
992 | } else if (!(c % 5)) { | |
993 | data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); | |
994 | data2 = ath5k_hw_bitswap(1, 2); | |
995 | } else | |
996 | return -EINVAL; | |
cc6323c7 NK |
997 | } else { |
998 | data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); | |
999 | data2 = ath5k_hw_bitswap(0, 2); | |
fa1c114f JS |
1000 | } |
1001 | ||
1002 | data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; | |
1003 | ||
1004 | ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); | |
1005 | ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
cc6323c7 NK |
1010 | /* |
1011 | * Set the channel on the RF2425 | |
1012 | */ | |
1013 | static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, | |
1014 | struct ieee80211_channel *channel) | |
1015 | { | |
1016 | u32 data, data0, data2; | |
1017 | u16 c; | |
1018 | ||
1019 | data = data0 = data2 = 0; | |
1020 | c = channel->center_freq; | |
1021 | ||
1022 | if (c < 4800) { | |
1023 | data0 = ath5k_hw_bitswap((c - 2272), 8); | |
1024 | data2 = 0; | |
1025 | /* ? 5GHz ? */ | |
1026 | } else if ((c - (c % 5)) != 2 || c > 5435) { | |
1027 | if (!(c % 20) && c < 5120) | |
1028 | data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); | |
1029 | else if (!(c % 10)) | |
1030 | data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); | |
1031 | else if (!(c % 5)) | |
1032 | data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); | |
1033 | else | |
1034 | return -EINVAL; | |
1035 | data2 = ath5k_hw_bitswap(1, 2); | |
1036 | } else { | |
1037 | data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); | |
1038 | data2 = ath5k_hw_bitswap(0, 2); | |
1039 | } | |
1040 | ||
1041 | data = (data0 << 4) | data2 << 2 | 0x1001; | |
1042 | ||
1043 | ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); | |
1044 | ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
fa1c114f JS |
1049 | /* |
1050 | * Set a channel on the radio chip | |
1051 | */ | |
1052 | int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) | |
1053 | { | |
1054 | int ret; | |
fa1c114f | 1055 | /* |
400ec45a LR |
1056 | * Check bounds supported by the PHY (we don't care about regultory |
1057 | * restrictions at this point). Note: hw_value already has the band | |
1058 | * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() | |
1059 | * of the band by that */ | |
1060 | if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { | |
fa1c114f | 1061 | ATH5K_ERR(ah->ah_sc, |
400ec45a LR |
1062 | "channel frequency (%u MHz) out of supported " |
1063 | "band range\n", | |
d8ee398d | 1064 | channel->center_freq); |
400ec45a | 1065 | return -EINVAL; |
fa1c114f JS |
1066 | } |
1067 | ||
1068 | /* | |
1069 | * Set the channel and wait | |
1070 | */ | |
1071 | switch (ah->ah_radio) { | |
1072 | case AR5K_RF5110: | |
1073 | ret = ath5k_hw_rf5110_channel(ah, channel); | |
1074 | break; | |
1075 | case AR5K_RF5111: | |
1076 | ret = ath5k_hw_rf5111_channel(ah, channel); | |
1077 | break; | |
cc6323c7 NK |
1078 | case AR5K_RF2425: |
1079 | ret = ath5k_hw_rf2425_channel(ah, channel); | |
1080 | break; | |
fa1c114f JS |
1081 | default: |
1082 | ret = ath5k_hw_rf5112_channel(ah, channel); | |
1083 | break; | |
1084 | } | |
1085 | ||
1086 | if (ret) | |
1087 | return ret; | |
1088 | ||
cc6323c7 NK |
1089 | /* Set JAPAN setting for channel 14 */ |
1090 | if (channel->center_freq == 2484) { | |
1091 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, | |
1092 | AR5K_PHY_CCKTXCTL_JAPAN); | |
1093 | } else { | |
1094 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, | |
1095 | AR5K_PHY_CCKTXCTL_WORLD); | |
1096 | } | |
1097 | ||
46026e8f | 1098 | ah->ah_current_channel = channel; |
d8ee398d | 1099 | ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false; |
fa1c114f JS |
1100 | |
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | /*****************\ | |
1105 | PHY calibration | |
1106 | \*****************/ | |
1107 | ||
6e220662 NK |
1108 | void |
1109 | ath5k_hw_calibration_poll(struct ath5k_hw *ah) | |
1110 | { | |
1111 | /* Calibration interval in jiffies */ | |
1112 | unsigned long cal_intval; | |
1113 | ||
1114 | cal_intval = msecs_to_jiffies(ah->ah_cal_intval * 1000); | |
1115 | ||
1116 | /* Initialize timestamp if needed */ | |
1117 | if (!ah->ah_cal_tstamp) | |
1118 | ah->ah_cal_tstamp = jiffies; | |
1119 | ||
1120 | /* For now we always do full calibration | |
1121 | * Mark software interrupt mask and fire software | |
1122 | * interrupt (bit gets auto-cleared) */ | |
1123 | if (time_is_before_eq_jiffies(ah->ah_cal_tstamp + cal_intval)) { | |
1124 | ah->ah_cal_tstamp = jiffies; | |
1125 | ah->ah_swi_mask = AR5K_SWI_FULL_CALIBRATION; | |
1126 | AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); | |
1127 | } | |
e5e2647f | 1128 | } |
6e220662 | 1129 | |
e5e2647f BC |
1130 | static int sign_extend(int val, const int nbits) |
1131 | { | |
1132 | int order = BIT(nbits-1); | |
1133 | return (val ^ order) - order; | |
6e220662 NK |
1134 | } |
1135 | ||
e5e2647f BC |
1136 | static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) |
1137 | { | |
1138 | s32 val; | |
1139 | ||
1140 | val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); | |
1141 | return sign_extend(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 9); | |
1142 | } | |
1143 | ||
1144 | void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) | |
1145 | { | |
1146 | int i; | |
1147 | ||
1148 | ah->ah_nfcal_hist.index = 0; | |
1149 | for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) | |
1150 | ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; | |
1151 | } | |
1152 | ||
1153 | static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) | |
1154 | { | |
1155 | struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; | |
1156 | hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1); | |
1157 | hist->nfval[hist->index] = noise_floor; | |
1158 | } | |
1159 | ||
1160 | static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) | |
1161 | { | |
1162 | s16 sort[ATH5K_NF_CAL_HIST_MAX]; | |
1163 | s16 tmp; | |
1164 | int i, j; | |
1165 | ||
1166 | memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); | |
1167 | for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { | |
1168 | for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { | |
1169 | if (sort[j] > sort[j-1]) { | |
1170 | tmp = sort[j]; | |
1171 | sort[j] = sort[j-1]; | |
1172 | sort[j-1] = tmp; | |
1173 | } | |
1174 | } | |
1175 | } | |
1176 | for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { | |
1177 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, | |
1178 | "cal %d:%d\n", i, sort[i]); | |
1179 | } | |
1180 | return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2]; | |
1181 | } | |
1182 | ||
1183 | /* | |
1184 | * When we tell the hardware to perform a noise floor calibration | |
1185 | * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically | |
1186 | * sample-and-hold the minimum noise level seen at the antennas. | |
1187 | * This value is then stored in a ring buffer of recently measured | |
1188 | * noise floor values so we have a moving window of the last few | |
1189 | * samples. | |
fa1c114f | 1190 | * |
e5e2647f BC |
1191 | * The median of the values in the history is then loaded into the |
1192 | * hardware for its own use for RSSI and CCA measurements. | |
fa1c114f | 1193 | */ |
e5e2647f | 1194 | void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) |
fa1c114f | 1195 | { |
e5e2647f BC |
1196 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
1197 | u32 val; | |
1198 | s16 nf, threshold; | |
1199 | u8 ee_mode; | |
fa1c114f | 1200 | |
e5e2647f BC |
1201 | /* keep last value if calibration hasn't completed */ |
1202 | if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { | |
1203 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, | |
1204 | "NF did not complete in calibration window\n"); | |
fa1c114f | 1205 | |
e5e2647f | 1206 | return; |
fa1c114f JS |
1207 | } |
1208 | ||
e5e2647f BC |
1209 | switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) { |
1210 | case CHANNEL_A: | |
1211 | case CHANNEL_T: | |
1212 | case CHANNEL_XR: | |
1213 | ee_mode = AR5K_EEPROM_MODE_11A; | |
1214 | break; | |
1215 | case CHANNEL_G: | |
1216 | case CHANNEL_TG: | |
1217 | ee_mode = AR5K_EEPROM_MODE_11G; | |
1218 | break; | |
1219 | default: | |
1220 | case CHANNEL_B: | |
1221 | ee_mode = AR5K_EEPROM_MODE_11B; | |
1222 | break; | |
fa1c114f JS |
1223 | } |
1224 | ||
fa1c114f | 1225 | |
e5e2647f BC |
1226 | /* completed NF calibration, test threshold */ |
1227 | nf = ath5k_hw_read_measured_noise_floor(ah); | |
1228 | threshold = ee->ee_noise_floor_thr[ee_mode]; | |
1229 | ||
1230 | if (nf > threshold) { | |
1231 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, | |
1232 | "noise floor failure detected; " | |
1233 | "read %d, threshold %d\n", | |
1234 | nf, threshold); | |
1235 | ||
1236 | nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE; | |
fa1c114f JS |
1237 | } |
1238 | ||
e5e2647f BC |
1239 | ath5k_hw_update_nfcal_hist(ah, nf); |
1240 | nf = ath5k_hw_get_median_noise_floor(ah); | |
fa1c114f | 1241 | |
e5e2647f BC |
1242 | /* load noise floor (in .5 dBm) so the hardware will use it */ |
1243 | val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; | |
1244 | val |= (nf * 2) & AR5K_PHY_NF_M; | |
1245 | ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); | |
1246 | ||
1247 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, | |
1248 | ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE)); | |
1249 | ||
1250 | ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, | |
1251 | 0, false); | |
1252 | ||
1253 | /* | |
1254 | * Load a high max CCA Power value (-50 dBm in .5 dBm units) | |
1255 | * so that we're not capped by the median we just loaded. | |
1256 | * This will be used as the initial value for the next noise | |
1257 | * floor calibration. | |
1258 | */ | |
1259 | val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); | |
1260 | ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); | |
1261 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, | |
1262 | AR5K_PHY_AGCCTL_NF_EN | | |
1263 | AR5K_PHY_AGCCTL_NF_NOUPDATE | | |
1264 | AR5K_PHY_AGCCTL_NF); | |
1265 | ||
1266 | ah->ah_noise_floor = nf; | |
1267 | ||
1268 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, | |
1269 | "noise floor calibrated: %d\n", nf); | |
fa1c114f JS |
1270 | } |
1271 | ||
1272 | /* | |
1273 | * Perform a PHY calibration on RF5110 | |
1274 | * -Fix BPSK/QAM Constellation (I/Q correction) | |
1275 | * -Calculate Noise Floor | |
1276 | */ | |
1277 | static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, | |
1278 | struct ieee80211_channel *channel) | |
1279 | { | |
1280 | u32 phy_sig, phy_agc, phy_sat, beacon; | |
1281 | int ret; | |
1282 | ||
1283 | /* | |
1284 | * Disable beacons and RX/TX queues, wait | |
1285 | */ | |
1286 | AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, | |
1287 | AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); | |
1288 | beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); | |
1289 | ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); | |
1290 | ||
84e463fa | 1291 | mdelay(2); |
fa1c114f JS |
1292 | |
1293 | /* | |
1294 | * Set the channel (with AGC turned off) | |
1295 | */ | |
1296 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); | |
1297 | udelay(10); | |
1298 | ret = ath5k_hw_channel(ah, channel); | |
1299 | ||
1300 | /* | |
1301 | * Activate PHY and wait | |
1302 | */ | |
1303 | ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); | |
1304 | mdelay(1); | |
1305 | ||
1306 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); | |
1307 | ||
1308 | if (ret) | |
1309 | return ret; | |
1310 | ||
1311 | /* | |
1312 | * Calibrate the radio chip | |
1313 | */ | |
1314 | ||
1315 | /* Remember normal state */ | |
1316 | phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); | |
1317 | phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); | |
1318 | phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); | |
1319 | ||
1320 | /* Update radio registers */ | |
1321 | ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | | |
1322 | AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); | |
1323 | ||
1324 | ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | | |
1325 | AR5K_PHY_AGCCOARSE_LO)) | | |
1326 | AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | | |
1327 | AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); | |
1328 | ||
1329 | ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | | |
1330 | AR5K_PHY_ADCSAT_THR)) | | |
1331 | AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | | |
1332 | AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); | |
1333 | ||
1334 | udelay(20); | |
1335 | ||
1336 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); | |
1337 | udelay(10); | |
1338 | ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); | |
1339 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); | |
1340 | ||
1341 | mdelay(1); | |
1342 | ||
1343 | /* | |
1344 | * Enable calibration and wait until completion | |
1345 | */ | |
1346 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); | |
1347 | ||
1348 | ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, | |
1349 | AR5K_PHY_AGCCTL_CAL, 0, false); | |
1350 | ||
1351 | /* Reset to normal state */ | |
1352 | ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); | |
1353 | ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); | |
1354 | ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); | |
1355 | ||
1356 | if (ret) { | |
1357 | ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", | |
d8ee398d | 1358 | channel->center_freq); |
fa1c114f JS |
1359 | return ret; |
1360 | } | |
1361 | ||
e5e2647f | 1362 | ath5k_hw_update_noise_floor(ah); |
fa1c114f JS |
1363 | |
1364 | /* | |
1365 | * Re-enable RX/TX and beacons | |
1366 | */ | |
1367 | AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, | |
1368 | AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); | |
1369 | ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); | |
1370 | ||
1371 | return 0; | |
1372 | } | |
1373 | ||
1374 | /* | |
f860ee26 | 1375 | * Perform a PHY calibration on RF5111/5112 and newer chips |
fa1c114f JS |
1376 | */ |
1377 | static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, | |
1378 | struct ieee80211_channel *channel) | |
1379 | { | |
1380 | u32 i_pwr, q_pwr; | |
1381 | s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; | |
f860ee26 | 1382 | int i; |
fa1c114f JS |
1383 | ATH5K_TRACE(ah->ah_sc); |
1384 | ||
e9010e2f | 1385 | if (!ah->ah_calibration || |
f860ee26 | 1386 | ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) |
fa1c114f JS |
1387 | goto done; |
1388 | ||
f860ee26 | 1389 | /* Calibration has finished, get the results and re-run */ |
86415d43 BR |
1390 | |
1391 | /* work around empty results which can apparently happen on 5212 */ | |
f860ee26 NK |
1392 | for (i = 0; i <= 10; i++) { |
1393 | iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); | |
1394 | i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); | |
1395 | q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); | |
86415d43 BR |
1396 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, |
1397 | "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); | |
1398 | if (i_pwr && q_pwr) | |
1399 | break; | |
f860ee26 | 1400 | } |
fa1c114f | 1401 | |
fa1c114f | 1402 | i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; |
f860ee26 | 1403 | q_coffd = q_pwr >> 7; |
fa1c114f | 1404 | |
86415d43 BR |
1405 | /* protect against divide by 0 and loss of sign bits */ |
1406 | if (i_coffd == 0 || q_coffd < 2) | |
fa1c114f JS |
1407 | goto done; |
1408 | ||
86415d43 BR |
1409 | i_coff = (-iq_corr) / i_coffd; |
1410 | i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ | |
fa1c114f | 1411 | |
86415d43 BR |
1412 | q_coff = (i_pwr / q_coffd) - 128; |
1413 | q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ | |
f860ee26 | 1414 | |
86415d43 BR |
1415 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, |
1416 | "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", | |
1417 | i_coff, q_coff, i_coffd, q_coffd); | |
f860ee26 | 1418 | |
86415d43 BR |
1419 | /* Commit new I/Q values (set enable bit last to match HAL sources) */ |
1420 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); | |
1421 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); | |
1422 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); | |
fa1c114f | 1423 | |
f860ee26 NK |
1424 | /* Re-enable calibration -if we don't we'll commit |
1425 | * the same values again and again */ | |
1426 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, | |
1427 | AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); | |
1428 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); | |
1429 | ||
fa1c114f | 1430 | done: |
f860ee26 NK |
1431 | |
1432 | /* TODO: Separate noise floor calibration from I/Q calibration | |
1433 | * since noise floor calibration interrupts rx path while I/Q | |
1434 | * calibration doesn't. We don't need to run noise floor calibration | |
1435 | * as often as I/Q calibration.*/ | |
e5e2647f | 1436 | ath5k_hw_update_noise_floor(ah); |
fa1c114f | 1437 | |
6f3b414a NK |
1438 | /* Initiate a gain_F calibration */ |
1439 | ath5k_hw_request_rfgain_probe(ah); | |
fa1c114f JS |
1440 | |
1441 | return 0; | |
1442 | } | |
1443 | ||
1444 | /* | |
1445 | * Perform a PHY calibration | |
1446 | */ | |
1447 | int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, | |
1448 | struct ieee80211_channel *channel) | |
1449 | { | |
1450 | int ret; | |
1451 | ||
1452 | if (ah->ah_radio == AR5K_RF5110) | |
1453 | ret = ath5k_hw_rf5110_calibrate(ah, channel); | |
1454 | else | |
1455 | ret = ath5k_hw_rf511x_calibrate(ah, channel); | |
1456 | ||
1457 | return ret; | |
1458 | } | |
1459 | ||
57e6c56d NK |
1460 | /***************************\ |
1461 | * Spur mitigation functions * | |
1462 | \***************************/ | |
1463 | ||
1464 | bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, | |
1465 | struct ieee80211_channel *channel) | |
1466 | { | |
1467 | u8 refclk_freq; | |
1468 | ||
1469 | if ((ah->ah_radio == AR5K_RF5112) || | |
1470 | (ah->ah_radio == AR5K_RF5413) || | |
1471 | (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) | |
1472 | refclk_freq = 40; | |
1473 | else | |
1474 | refclk_freq = 32; | |
1475 | ||
1476 | if ((channel->center_freq % refclk_freq != 0) && | |
1477 | ((channel->center_freq % refclk_freq < 10) || | |
1478 | (channel->center_freq % refclk_freq > 22))) | |
1479 | return true; | |
1480 | else | |
1481 | return false; | |
1482 | } | |
1483 | ||
1484 | void | |
1485 | ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, | |
1486 | struct ieee80211_channel *channel) | |
1487 | { | |
1488 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; | |
1489 | u32 mag_mask[4] = {0, 0, 0, 0}; | |
1490 | u32 pilot_mask[2] = {0, 0}; | |
1491 | /* Note: fbin values are scaled up by 2 */ | |
1492 | u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; | |
1493 | s32 spur_delta_phase, spur_freq_sigma_delta; | |
1494 | s32 spur_offset, num_symbols_x16; | |
1495 | u8 num_symbol_offsets, i, freq_band; | |
1496 | ||
1497 | /* Convert current frequency to fbin value (the same way channels | |
1498 | * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale | |
1499 | * up by 2 so we can compare it later */ | |
1500 | if (channel->hw_value & CHANNEL_2GHZ) { | |
1501 | chan_fbin = (channel->center_freq - 2300) * 10; | |
1502 | freq_band = AR5K_EEPROM_BAND_2GHZ; | |
1503 | } else { | |
1504 | chan_fbin = (channel->center_freq - 4900) * 10; | |
1505 | freq_band = AR5K_EEPROM_BAND_5GHZ; | |
1506 | } | |
1507 | ||
1508 | /* Check if any spur_chan_fbin from EEPROM is | |
1509 | * within our current channel's spur detection range */ | |
1510 | spur_chan_fbin = AR5K_EEPROM_NO_SPUR; | |
1511 | spur_detection_window = AR5K_SPUR_CHAN_WIDTH; | |
1512 | /* XXX: Half/Quarter channels ?*/ | |
1513 | if (channel->hw_value & CHANNEL_TURBO) | |
1514 | spur_detection_window *= 2; | |
1515 | ||
1516 | for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { | |
1517 | spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; | |
1518 | ||
1519 | /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag | |
1520 | * so it's zero if we got nothing from EEPROM */ | |
1521 | if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { | |
1522 | spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; | |
1523 | break; | |
1524 | } | |
1525 | ||
1526 | if ((chan_fbin - spur_detection_window <= | |
1527 | (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && | |
1528 | (chan_fbin + spur_detection_window >= | |
1529 | (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { | |
1530 | spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; | |
1531 | break; | |
1532 | } | |
1533 | } | |
1534 | ||
1535 | /* We need to enable spur filter for this channel */ | |
1536 | if (spur_chan_fbin) { | |
1537 | spur_offset = spur_chan_fbin - chan_fbin; | |
1538 | /* | |
1539 | * Calculate deltas: | |
1540 | * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 | |
1541 | * spur_delta_phase -> spur_offset / chip_freq << 11 | |
1542 | * Note: Both values have 100KHz resolution | |
1543 | */ | |
1544 | /* XXX: Half/Quarter rate channels ? */ | |
1545 | switch (channel->hw_value) { | |
1546 | case CHANNEL_A: | |
1547 | /* Both sample_freq and chip_freq are 40MHz */ | |
1548 | spur_delta_phase = (spur_offset << 17) / 25; | |
1549 | spur_freq_sigma_delta = (spur_delta_phase >> 10); | |
1550 | symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; | |
1551 | break; | |
1552 | case CHANNEL_G: | |
1553 | /* sample_freq -> 40MHz chip_freq -> 44MHz | |
1554 | * (for b compatibility) */ | |
1555 | spur_freq_sigma_delta = (spur_offset << 8) / 55; | |
1556 | spur_delta_phase = (spur_offset << 17) / 25; | |
1557 | symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; | |
1558 | break; | |
1559 | case CHANNEL_T: | |
1560 | case CHANNEL_TG: | |
1561 | /* Both sample_freq and chip_freq are 80MHz */ | |
1562 | spur_delta_phase = (spur_offset << 16) / 25; | |
1563 | spur_freq_sigma_delta = (spur_delta_phase >> 10); | |
1564 | symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz; | |
1565 | break; | |
1566 | default: | |
1567 | return; | |
1568 | } | |
1569 | ||
1570 | /* Calculate pilot and magnitude masks */ | |
1571 | ||
1572 | /* Scale up spur_offset by 1000 to switch to 100HZ resolution | |
1573 | * and divide by symbol_width to find how many symbols we have | |
1574 | * Note: number of symbols is scaled up by 16 */ | |
1575 | num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; | |
1576 | ||
1577 | /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ | |
1578 | if (!(num_symbols_x16 & 0xF)) | |
1579 | /* _X_ */ | |
1580 | num_symbol_offsets = 3; | |
1581 | else | |
1582 | /* _xx_ */ | |
1583 | num_symbol_offsets = 4; | |
1584 | ||
1585 | for (i = 0; i < num_symbol_offsets; i++) { | |
1586 | ||
1587 | /* Calculate pilot mask */ | |
1588 | s32 curr_sym_off = | |
1589 | (num_symbols_x16 / 16) + i + 25; | |
1590 | ||
1591 | /* Pilot magnitude mask seems to be a way to | |
1592 | * declare the boundaries for our detection | |
1593 | * window or something, it's 2 for the middle | |
1594 | * value(s) where the symbol is expected to be | |
1595 | * and 1 on the boundary values */ | |
1596 | u8 plt_mag_map = | |
1597 | (i == 0 || i == (num_symbol_offsets - 1)) | |
1598 | ? 1 : 2; | |
1599 | ||
1600 | if (curr_sym_off >= 0 && curr_sym_off <= 32) { | |
1601 | if (curr_sym_off <= 25) | |
1602 | pilot_mask[0] |= 1 << curr_sym_off; | |
1603 | else if (curr_sym_off >= 27) | |
1604 | pilot_mask[0] |= 1 << (curr_sym_off - 1); | |
1605 | } else if (curr_sym_off >= 33 && curr_sym_off <= 52) | |
1606 | pilot_mask[1] |= 1 << (curr_sym_off - 33); | |
1607 | ||
1608 | /* Calculate magnitude mask (for viterbi decoder) */ | |
1609 | if (curr_sym_off >= -1 && curr_sym_off <= 14) | |
1610 | mag_mask[0] |= | |
1611 | plt_mag_map << (curr_sym_off + 1) * 2; | |
1612 | else if (curr_sym_off >= 15 && curr_sym_off <= 30) | |
1613 | mag_mask[1] |= | |
1614 | plt_mag_map << (curr_sym_off - 15) * 2; | |
1615 | else if (curr_sym_off >= 31 && curr_sym_off <= 46) | |
1616 | mag_mask[2] |= | |
1617 | plt_mag_map << (curr_sym_off - 31) * 2; | |
1618 | else if (curr_sym_off >= 46 && curr_sym_off <= 53) | |
1619 | mag_mask[3] |= | |
1620 | plt_mag_map << (curr_sym_off - 47) * 2; | |
1621 | ||
1622 | } | |
1623 | ||
1624 | /* Write settings on hw to enable spur filter */ | |
1625 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, | |
1626 | AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); | |
1627 | /* XXX: Self correlator also ? */ | |
1628 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, | |
1629 | AR5K_PHY_IQ_PILOT_MASK_EN | | |
1630 | AR5K_PHY_IQ_CHAN_MASK_EN | | |
1631 | AR5K_PHY_IQ_SPUR_FILT_EN); | |
1632 | ||
1633 | /* Set delta phase and freq sigma delta */ | |
1634 | ath5k_hw_reg_write(ah, | |
1635 | AR5K_REG_SM(spur_delta_phase, | |
1636 | AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | | |
1637 | AR5K_REG_SM(spur_freq_sigma_delta, | |
1638 | AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | | |
1639 | AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, | |
1640 | AR5K_PHY_TIMING_11); | |
1641 | ||
1642 | /* Write pilot masks */ | |
1643 | ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); | |
1644 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, | |
1645 | AR5K_PHY_TIMING_8_PILOT_MASK_2, | |
1646 | pilot_mask[1]); | |
1647 | ||
1648 | ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); | |
1649 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, | |
1650 | AR5K_PHY_TIMING_10_PILOT_MASK_2, | |
1651 | pilot_mask[1]); | |
1652 | ||
1653 | /* Write magnitude masks */ | |
1654 | ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); | |
1655 | ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); | |
1656 | ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); | |
1657 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, | |
1658 | AR5K_PHY_BIN_MASK_CTL_MASK_4, | |
1659 | mag_mask[3]); | |
1660 | ||
1661 | ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); | |
1662 | ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); | |
1663 | ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); | |
1664 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, | |
1665 | AR5K_PHY_BIN_MASK2_4_MASK_4, | |
1666 | mag_mask[3]); | |
1667 | ||
1668 | } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & | |
1669 | AR5K_PHY_IQ_SPUR_FILT_EN) { | |
1670 | /* Clean up spur mitigation settings and disable fliter */ | |
1671 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, | |
1672 | AR5K_PHY_BIN_MASK_CTL_RATE, 0); | |
1673 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, | |
1674 | AR5K_PHY_IQ_PILOT_MASK_EN | | |
1675 | AR5K_PHY_IQ_CHAN_MASK_EN | | |
1676 | AR5K_PHY_IQ_SPUR_FILT_EN); | |
1677 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); | |
1678 | ||
1679 | /* Clear pilot masks */ | |
1680 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); | |
1681 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, | |
1682 | AR5K_PHY_TIMING_8_PILOT_MASK_2, | |
1683 | 0); | |
1684 | ||
1685 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); | |
1686 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, | |
1687 | AR5K_PHY_TIMING_10_PILOT_MASK_2, | |
1688 | 0); | |
1689 | ||
1690 | /* Clear magnitude masks */ | |
1691 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); | |
1692 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); | |
1693 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); | |
1694 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, | |
1695 | AR5K_PHY_BIN_MASK_CTL_MASK_4, | |
1696 | 0); | |
1697 | ||
1698 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); | |
1699 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); | |
1700 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); | |
1701 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, | |
1702 | AR5K_PHY_BIN_MASK2_4_MASK_4, | |
1703 | 0); | |
1704 | } | |
1705 | } | |
1706 | ||
1707 | /********************\ | |
1708 | Misc PHY functions | |
1709 | \********************/ | |
1710 | ||
fa1c114f JS |
1711 | int ath5k_hw_phy_disable(struct ath5k_hw *ah) |
1712 | { | |
1713 | ATH5K_TRACE(ah->ah_sc); | |
1714 | /*Just a try M.F.*/ | |
1715 | ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); | |
1716 | ||
1717 | return 0; | |
1718 | } | |
1719 | ||
fa1c114f JS |
1720 | /* |
1721 | * Get the PHY Chip revision | |
1722 | */ | |
1723 | u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) | |
1724 | { | |
1725 | unsigned int i; | |
1726 | u32 srev; | |
1727 | u16 ret; | |
1728 | ||
1729 | ATH5K_TRACE(ah->ah_sc); | |
1730 | ||
1731 | /* | |
1732 | * Set the radio chip access register | |
1733 | */ | |
1734 | switch (chan) { | |
1735 | case CHANNEL_2GHZ: | |
1736 | ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); | |
1737 | break; | |
1738 | case CHANNEL_5GHZ: | |
1739 | ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); | |
1740 | break; | |
1741 | default: | |
1742 | return 0; | |
1743 | } | |
1744 | ||
1745 | mdelay(2); | |
1746 | ||
1747 | /* ...wait until PHY is ready and read the selected radio revision */ | |
1748 | ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); | |
1749 | ||
1750 | for (i = 0; i < 8; i++) | |
1751 | ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); | |
1752 | ||
1753 | if (ah->ah_version == AR5K_AR5210) { | |
1754 | srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; | |
1755 | ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; | |
1756 | } else { | |
1757 | srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; | |
1758 | ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | | |
1759 | ((srev & 0x0f) << 4), 8); | |
1760 | } | |
1761 | ||
1762 | /* Reset to the 5GHz mode */ | |
1763 | ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); | |
1764 | ||
1765 | return ret; | |
1766 | } | |
1767 | ||
2bed03eb NK |
1768 | /*****************\ |
1769 | * Antenna control * | |
1770 | \*****************/ | |
1771 | ||
fa1c114f | 1772 | void /*TODO:Boundary check*/ |
2bed03eb | 1773 | ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) |
fa1c114f JS |
1774 | { |
1775 | ATH5K_TRACE(ah->ah_sc); | |
2bed03eb | 1776 | |
fa1c114f | 1777 | if (ah->ah_version != AR5K_AR5210) |
2bed03eb | 1778 | ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); |
fa1c114f JS |
1779 | } |
1780 | ||
1781 | unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah) | |
1782 | { | |
1783 | ATH5K_TRACE(ah->ah_sc); | |
2bed03eb | 1784 | |
fa1c114f | 1785 | if (ah->ah_version != AR5K_AR5210) |
2bed03eb | 1786 | return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA) & 0x7; |
fa1c114f JS |
1787 | |
1788 | return false; /*XXX: What do we return for 5210 ?*/ | |
1789 | } | |
1790 | ||
2bed03eb NK |
1791 | /* |
1792 | * Enable/disable fast rx antenna diversity | |
1793 | */ | |
1794 | static void | |
1795 | ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) | |
1796 | { | |
1797 | switch (ee_mode) { | |
1798 | case AR5K_EEPROM_MODE_11G: | |
1799 | /* XXX: This is set to | |
1800 | * disabled on initvals !!! */ | |
1801 | case AR5K_EEPROM_MODE_11A: | |
1802 | if (enable) | |
1803 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, | |
1804 | AR5K_PHY_AGCCTL_OFDM_DIV_DIS); | |
1805 | else | |
1806 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, | |
1807 | AR5K_PHY_AGCCTL_OFDM_DIV_DIS); | |
1808 | break; | |
1809 | case AR5K_EEPROM_MODE_11B: | |
1810 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, | |
1811 | AR5K_PHY_AGCCTL_OFDM_DIV_DIS); | |
1812 | break; | |
1813 | default: | |
1814 | return; | |
1815 | } | |
1816 | ||
1817 | if (enable) { | |
1818 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, | |
1819 | AR5K_PHY_RESTART_DIV_GC, 0xc); | |
1820 | ||
1821 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, | |
1822 | AR5K_PHY_FAST_ANT_DIV_EN); | |
1823 | } else { | |
1824 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, | |
1825 | AR5K_PHY_RESTART_DIV_GC, 0x8); | |
1826 | ||
1827 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, | |
1828 | AR5K_PHY_FAST_ANT_DIV_EN); | |
1829 | } | |
1830 | } | |
1831 | ||
1832 | /* | |
1833 | * Set antenna operating mode | |
1834 | */ | |
1835 | void | |
1836 | ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) | |
1837 | { | |
46026e8f | 1838 | struct ieee80211_channel *channel = ah->ah_current_channel; |
2bed03eb NK |
1839 | bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; |
1840 | bool use_def_for_sg; | |
1841 | u8 def_ant, tx_ant, ee_mode; | |
1842 | u32 sta_id1 = 0; | |
1843 | ||
1844 | def_ant = ah->ah_def_ant; | |
1845 | ||
1846 | ATH5K_TRACE(ah->ah_sc); | |
1847 | ||
1848 | switch (channel->hw_value & CHANNEL_MODES) { | |
1849 | case CHANNEL_A: | |
1850 | case CHANNEL_T: | |
1851 | case CHANNEL_XR: | |
1852 | ee_mode = AR5K_EEPROM_MODE_11A; | |
1853 | break; | |
1854 | case CHANNEL_G: | |
1855 | case CHANNEL_TG: | |
1856 | ee_mode = AR5K_EEPROM_MODE_11G; | |
1857 | break; | |
1858 | case CHANNEL_B: | |
1859 | ee_mode = AR5K_EEPROM_MODE_11B; | |
1860 | break; | |
1861 | default: | |
1862 | ATH5K_ERR(ah->ah_sc, | |
1863 | "invalid channel: %d\n", channel->center_freq); | |
1864 | return; | |
1865 | } | |
1866 | ||
1867 | switch (ant_mode) { | |
1868 | case AR5K_ANTMODE_DEFAULT: | |
1869 | tx_ant = 0; | |
1870 | use_def_for_tx = false; | |
1871 | update_def_on_tx = false; | |
1872 | use_def_for_rts = false; | |
1873 | use_def_for_sg = false; | |
1874 | fast_div = true; | |
1875 | break; | |
1876 | case AR5K_ANTMODE_FIXED_A: | |
1877 | def_ant = 1; | |
8bd8beab | 1878 | tx_ant = 1; |
2bed03eb NK |
1879 | use_def_for_tx = true; |
1880 | update_def_on_tx = false; | |
1881 | use_def_for_rts = true; | |
1882 | use_def_for_sg = true; | |
1883 | fast_div = false; | |
1884 | break; | |
1885 | case AR5K_ANTMODE_FIXED_B: | |
1886 | def_ant = 2; | |
8bd8beab | 1887 | tx_ant = 2; |
2bed03eb NK |
1888 | use_def_for_tx = true; |
1889 | update_def_on_tx = false; | |
1890 | use_def_for_rts = true; | |
1891 | use_def_for_sg = true; | |
1892 | fast_div = false; | |
1893 | break; | |
1894 | case AR5K_ANTMODE_SINGLE_AP: | |
1895 | def_ant = 1; /* updated on tx */ | |
1896 | tx_ant = 0; | |
1897 | use_def_for_tx = true; | |
1898 | update_def_on_tx = true; | |
1899 | use_def_for_rts = true; | |
1900 | use_def_for_sg = true; | |
1901 | fast_div = true; | |
1902 | break; | |
1903 | case AR5K_ANTMODE_SECTOR_AP: | |
1904 | tx_ant = 1; /* variable */ | |
1905 | use_def_for_tx = false; | |
1906 | update_def_on_tx = false; | |
1907 | use_def_for_rts = true; | |
1908 | use_def_for_sg = false; | |
1909 | fast_div = false; | |
1910 | break; | |
1911 | case AR5K_ANTMODE_SECTOR_STA: | |
1912 | tx_ant = 1; /* variable */ | |
1913 | use_def_for_tx = true; | |
1914 | update_def_on_tx = false; | |
1915 | use_def_for_rts = true; | |
1916 | use_def_for_sg = false; | |
1917 | fast_div = true; | |
1918 | break; | |
1919 | case AR5K_ANTMODE_DEBUG: | |
1920 | def_ant = 1; | |
1921 | tx_ant = 2; | |
1922 | use_def_for_tx = false; | |
1923 | update_def_on_tx = false; | |
1924 | use_def_for_rts = false; | |
1925 | use_def_for_sg = false; | |
1926 | fast_div = false; | |
1927 | break; | |
1928 | default: | |
1929 | return; | |
1930 | } | |
1931 | ||
1932 | ah->ah_tx_ant = tx_ant; | |
1933 | ah->ah_ant_mode = ant_mode; | |
1934 | ||
1935 | sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; | |
1936 | sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; | |
1937 | sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; | |
1938 | sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; | |
1939 | ||
1940 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); | |
1941 | ||
1942 | if (sta_id1) | |
1943 | AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); | |
1944 | ||
1945 | /* Note: set diversity before default antenna | |
1946 | * because it won't work correctly */ | |
1947 | ath5k_hw_set_fast_div(ah, ee_mode, fast_div); | |
1948 | ath5k_hw_set_def_antenna(ah, def_ant); | |
1949 | } | |
1950 | ||
8f655dde NK |
1951 | |
1952 | /****************\ | |
1953 | * TX power setup * | |
1954 | \****************/ | |
1955 | ||
1956 | /* | |
1957 | * Helper functions | |
1958 | */ | |
1959 | ||
1960 | /* | |
1961 | * Do linear interpolation between two given (x, y) points | |
1962 | */ | |
1963 | static s16 | |
1964 | ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, | |
1965 | s16 y_left, s16 y_right) | |
1966 | { | |
1967 | s16 ratio, result; | |
1968 | ||
1969 | /* Avoid divide by zero and skip interpolation | |
1970 | * if we have the same point */ | |
1971 | if ((x_left == x_right) || (y_left == y_right)) | |
1972 | return y_left; | |
1973 | ||
1974 | /* | |
1975 | * Since we use ints and not fps, we need to scale up in | |
1976 | * order to get a sane ratio value (or else we 'll eg. get | |
1977 | * always 1 instead of 1.25, 1.75 etc). We scale up by 100 | |
1978 | * to have some accuracy both for 0.5 and 0.25 steps. | |
1979 | */ | |
1980 | ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); | |
1981 | ||
1982 | /* Now scale down to be in range */ | |
1983 | result = y_left + (ratio * (target - x_left) / 100); | |
1984 | ||
1985 | return result; | |
1986 | } | |
1987 | ||
1988 | /* | |
1989 | * Find vertical boundary (min pwr) for the linear PCDAC curve. | |
1990 | * | |
1991 | * Since we have the top of the curve and we draw the line below | |
1992 | * until we reach 1 (1 pcdac step) we need to know which point | |
1993 | * (x value) that is so that we don't go below y axis and have negative | |
1994 | * pcdac values when creating the curve, or fill the table with zeroes. | |
1995 | */ | |
1996 | static s16 | |
1997 | ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, | |
1998 | const s16 *pwrL, const s16 *pwrR) | |
1999 | { | |
2000 | s8 tmp; | |
2001 | s16 min_pwrL, min_pwrR; | |
64cdb0e3 FR |
2002 | s16 pwr_i; |
2003 | ||
d1cb0bda NK |
2004 | /* Some vendors write the same pcdac value twice !!! */ |
2005 | if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) | |
2006 | return max(pwrL[0], pwrR[0]); | |
9c8b3edd | 2007 | |
64cdb0e3 FR |
2008 | if (pwrL[0] == pwrL[1]) |
2009 | min_pwrL = pwrL[0]; | |
2010 | else { | |
2011 | pwr_i = pwrL[0]; | |
2012 | do { | |
2013 | pwr_i--; | |
2014 | tmp = (s8) ath5k_get_interpolated_value(pwr_i, | |
2015 | pwrL[0], pwrL[1], | |
2016 | stepL[0], stepL[1]); | |
2017 | } while (tmp > 1); | |
2018 | ||
2019 | min_pwrL = pwr_i; | |
2020 | } | |
8f655dde | 2021 | |
64cdb0e3 FR |
2022 | if (pwrR[0] == pwrR[1]) |
2023 | min_pwrR = pwrR[0]; | |
2024 | else { | |
2025 | pwr_i = pwrR[0]; | |
2026 | do { | |
2027 | pwr_i--; | |
2028 | tmp = (s8) ath5k_get_interpolated_value(pwr_i, | |
2029 | pwrR[0], pwrR[1], | |
2030 | stepR[0], stepR[1]); | |
2031 | } while (tmp > 1); | |
2032 | ||
2033 | min_pwrR = pwr_i; | |
2034 | } | |
8f655dde NK |
2035 | |
2036 | /* Keep the right boundary so that it works for both curves */ | |
2037 | return max(min_pwrL, min_pwrR); | |
2038 | } | |
2039 | ||
2040 | /* | |
2041 | * Interpolate (pwr,vpd) points to create a Power to PDADC or a | |
2042 | * Power to PCDAC curve. | |
2043 | * | |
2044 | * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC | |
2045 | * steps (offsets) on y axis. Power can go up to 31.5dB and max | |
2046 | * PCDAC/PDADC step for each curve is 64 but we can write more than | |
2047 | * one curves on hw so we can go up to 128 (which is the max step we | |
2048 | * can write on the final table). | |
2049 | * | |
2050 | * We write y values (PCDAC/PDADC steps) on hw. | |
2051 | */ | |
2052 | static void | |
2053 | ath5k_create_power_curve(s16 pmin, s16 pmax, | |
2054 | const s16 *pwr, const u8 *vpd, | |
2055 | u8 num_points, | |
2056 | u8 *vpd_table, u8 type) | |
2057 | { | |
2058 | u8 idx[2] = { 0, 1 }; | |
2059 | s16 pwr_i = 2*pmin; | |
2060 | int i; | |
2061 | ||
2062 | if (num_points < 2) | |
2063 | return; | |
2064 | ||
2065 | /* We want the whole line, so adjust boundaries | |
2066 | * to cover the entire power range. Note that | |
2067 | * power values are already 0.25dB so no need | |
2068 | * to multiply pwr_i by 2 */ | |
2069 | if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { | |
2070 | pwr_i = pmin; | |
2071 | pmin = 0; | |
2072 | pmax = 63; | |
2073 | } | |
2074 | ||
2075 | /* Find surrounding turning points (TPs) | |
2076 | * and interpolate between them */ | |
2077 | for (i = 0; (i <= (u16) (pmax - pmin)) && | |
2078 | (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { | |
2079 | ||
2080 | /* We passed the right TP, move to the next set of TPs | |
2081 | * if we pass the last TP, extrapolate above using the last | |
2082 | * two TPs for ratio */ | |
2083 | if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { | |
2084 | idx[0]++; | |
2085 | idx[1]++; | |
2086 | } | |
2087 | ||
2088 | vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, | |
2089 | pwr[idx[0]], pwr[idx[1]], | |
2090 | vpd[idx[0]], vpd[idx[1]]); | |
2091 | ||
2092 | /* Increase by 0.5dB | |
2093 | * (0.25 dB units) */ | |
2094 | pwr_i += 2; | |
2095 | } | |
2096 | } | |
2097 | ||
2098 | /* | |
2099 | * Get the surrounding per-channel power calibration piers | |
2100 | * for a given frequency so that we can interpolate between | |
2101 | * them and come up with an apropriate dataset for our current | |
2102 | * channel. | |
2103 | */ | |
2104 | static void | |
2105 | ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, | |
2106 | struct ieee80211_channel *channel, | |
2107 | struct ath5k_chan_pcal_info **pcinfo_l, | |
2108 | struct ath5k_chan_pcal_info **pcinfo_r) | |
2109 | { | |
2110 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; | |
2111 | struct ath5k_chan_pcal_info *pcinfo; | |
2112 | u8 idx_l, idx_r; | |
2113 | u8 mode, max, i; | |
2114 | u32 target = channel->center_freq; | |
2115 | ||
2116 | idx_l = 0; | |
2117 | idx_r = 0; | |
2118 | ||
2119 | if (!(channel->hw_value & CHANNEL_OFDM)) { | |
2120 | pcinfo = ee->ee_pwr_cal_b; | |
2121 | mode = AR5K_EEPROM_MODE_11B; | |
2122 | } else if (channel->hw_value & CHANNEL_2GHZ) { | |
2123 | pcinfo = ee->ee_pwr_cal_g; | |
2124 | mode = AR5K_EEPROM_MODE_11G; | |
2125 | } else { | |
2126 | pcinfo = ee->ee_pwr_cal_a; | |
2127 | mode = AR5K_EEPROM_MODE_11A; | |
2128 | } | |
2129 | max = ee->ee_n_piers[mode] - 1; | |
2130 | ||
2131 | /* Frequency is below our calibrated | |
2132 | * range. Use the lowest power curve | |
2133 | * we have */ | |
2134 | if (target < pcinfo[0].freq) { | |
2135 | idx_l = idx_r = 0; | |
2136 | goto done; | |
2137 | } | |
2138 | ||
2139 | /* Frequency is above our calibrated | |
2140 | * range. Use the highest power curve | |
2141 | * we have */ | |
2142 | if (target > pcinfo[max].freq) { | |
2143 | idx_l = idx_r = max; | |
2144 | goto done; | |
2145 | } | |
2146 | ||
2147 | /* Frequency is inside our calibrated | |
2148 | * channel range. Pick the surrounding | |
2149 | * calibration piers so that we can | |
2150 | * interpolate */ | |
2151 | for (i = 0; i <= max; i++) { | |
2152 | ||
2153 | /* Frequency matches one of our calibration | |
2154 | * piers, no need to interpolate, just use | |
2155 | * that calibration pier */ | |
2156 | if (pcinfo[i].freq == target) { | |
2157 | idx_l = idx_r = i; | |
2158 | goto done; | |
2159 | } | |
2160 | ||
2161 | /* We found a calibration pier that's above | |
2162 | * frequency, use this pier and the previous | |
2163 | * one to interpolate */ | |
2164 | if (target < pcinfo[i].freq) { | |
2165 | idx_r = i; | |
2166 | idx_l = idx_r - 1; | |
2167 | goto done; | |
2168 | } | |
2169 | } | |
2170 | ||
2171 | done: | |
2172 | *pcinfo_l = &pcinfo[idx_l]; | |
2173 | *pcinfo_r = &pcinfo[idx_r]; | |
2174 | ||
2175 | return; | |
2176 | } | |
2177 | ||
2178 | /* | |
2179 | * Get the surrounding per-rate power calibration data | |
2180 | * for a given frequency and interpolate between power | |
2181 | * values to set max target power supported by hw for | |
2182 | * each rate. | |
2183 | */ | |
2184 | static void | |
2185 | ath5k_get_rate_pcal_data(struct ath5k_hw *ah, | |
2186 | struct ieee80211_channel *channel, | |
2187 | struct ath5k_rate_pcal_info *rates) | |
2188 | { | |
2189 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; | |
2190 | struct ath5k_rate_pcal_info *rpinfo; | |
2191 | u8 idx_l, idx_r; | |
2192 | u8 mode, max, i; | |
2193 | u32 target = channel->center_freq; | |
2194 | ||
2195 | idx_l = 0; | |
2196 | idx_r = 0; | |
2197 | ||
2198 | if (!(channel->hw_value & CHANNEL_OFDM)) { | |
2199 | rpinfo = ee->ee_rate_tpwr_b; | |
2200 | mode = AR5K_EEPROM_MODE_11B; | |
2201 | } else if (channel->hw_value & CHANNEL_2GHZ) { | |
2202 | rpinfo = ee->ee_rate_tpwr_g; | |
2203 | mode = AR5K_EEPROM_MODE_11G; | |
2204 | } else { | |
2205 | rpinfo = ee->ee_rate_tpwr_a; | |
2206 | mode = AR5K_EEPROM_MODE_11A; | |
2207 | } | |
2208 | max = ee->ee_rate_target_pwr_num[mode] - 1; | |
2209 | ||
2210 | /* Get the surrounding calibration | |
2211 | * piers - same as above */ | |
2212 | if (target < rpinfo[0].freq) { | |
2213 | idx_l = idx_r = 0; | |
2214 | goto done; | |
2215 | } | |
2216 | ||
2217 | if (target > rpinfo[max].freq) { | |
2218 | idx_l = idx_r = max; | |
2219 | goto done; | |
2220 | } | |
2221 | ||
2222 | for (i = 0; i <= max; i++) { | |
2223 | ||
2224 | if (rpinfo[i].freq == target) { | |
2225 | idx_l = idx_r = i; | |
2226 | goto done; | |
2227 | } | |
2228 | ||
2229 | if (target < rpinfo[i].freq) { | |
2230 | idx_r = i; | |
2231 | idx_l = idx_r - 1; | |
2232 | goto done; | |
2233 | } | |
2234 | } | |
2235 | ||
2236 | done: | |
2237 | /* Now interpolate power value, based on the frequency */ | |
2238 | rates->freq = target; | |
2239 | ||
2240 | rates->target_power_6to24 = | |
2241 | ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, | |
2242 | rpinfo[idx_r].freq, | |
2243 | rpinfo[idx_l].target_power_6to24, | |
2244 | rpinfo[idx_r].target_power_6to24); | |
2245 | ||
2246 | rates->target_power_36 = | |
2247 | ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, | |
2248 | rpinfo[idx_r].freq, | |
2249 | rpinfo[idx_l].target_power_36, | |
2250 | rpinfo[idx_r].target_power_36); | |
2251 | ||
2252 | rates->target_power_48 = | |
2253 | ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, | |
2254 | rpinfo[idx_r].freq, | |
2255 | rpinfo[idx_l].target_power_48, | |
2256 | rpinfo[idx_r].target_power_48); | |
2257 | ||
2258 | rates->target_power_54 = | |
2259 | ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, | |
2260 | rpinfo[idx_r].freq, | |
2261 | rpinfo[idx_l].target_power_54, | |
2262 | rpinfo[idx_r].target_power_54); | |
2263 | } | |
2264 | ||
2265 | /* | |
2266 | * Get the max edge power for this channel if | |
2267 | * we have such data from EEPROM's Conformance Test | |
2268 | * Limits (CTL), and limit max power if needed. | |
8f655dde NK |
2269 | */ |
2270 | static void | |
2271 | ath5k_get_max_ctl_power(struct ath5k_hw *ah, | |
2272 | struct ieee80211_channel *channel) | |
2273 | { | |
608b88cb | 2274 | struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); |
8f655dde NK |
2275 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
2276 | struct ath5k_edge_power *rep = ee->ee_ctl_pwr; | |
2277 | u8 *ctl_val = ee->ee_ctl; | |
2278 | s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; | |
2279 | s16 edge_pwr = 0; | |
2280 | u8 rep_idx; | |
2281 | u8 i, ctl_mode; | |
2282 | u8 ctl_idx = 0xFF; | |
2283 | u32 target = channel->center_freq; | |
2284 | ||
608b88cb | 2285 | ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); |
6752ee90 | 2286 | |
8f655dde NK |
2287 | switch (channel->hw_value & CHANNEL_MODES) { |
2288 | case CHANNEL_A: | |
6752ee90 | 2289 | ctl_mode |= AR5K_CTL_11A; |
8f655dde NK |
2290 | break; |
2291 | case CHANNEL_G: | |
6752ee90 | 2292 | ctl_mode |= AR5K_CTL_11G; |
8f655dde NK |
2293 | break; |
2294 | case CHANNEL_B: | |
6752ee90 | 2295 | ctl_mode |= AR5K_CTL_11B; |
8f655dde NK |
2296 | break; |
2297 | case CHANNEL_T: | |
6752ee90 | 2298 | ctl_mode |= AR5K_CTL_TURBO; |
8f655dde NK |
2299 | break; |
2300 | case CHANNEL_TG: | |
6752ee90 | 2301 | ctl_mode |= AR5K_CTL_TURBOG; |
8f655dde NK |
2302 | break; |
2303 | case CHANNEL_XR: | |
2304 | /* Fall through */ | |
2305 | default: | |
2306 | return; | |
2307 | } | |
2308 | ||
2309 | for (i = 0; i < ee->ee_ctls; i++) { | |
2310 | if (ctl_val[i] == ctl_mode) { | |
2311 | ctl_idx = i; | |
2312 | break; | |
2313 | } | |
2314 | } | |
2315 | ||
2316 | /* If we have a CTL dataset available grab it and find the | |
2317 | * edge power for our frequency */ | |
2318 | if (ctl_idx == 0xFF) | |
2319 | return; | |
2320 | ||
2321 | /* Edge powers are sorted by frequency from lower | |
2322 | * to higher. Each CTL corresponds to 8 edge power | |
2323 | * measurements. */ | |
2324 | rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; | |
2325 | ||
2326 | /* Don't do boundaries check because we | |
2327 | * might have more that one bands defined | |
2328 | * for this mode */ | |
2329 | ||
2330 | /* Get the edge power that's closer to our | |
2331 | * frequency */ | |
2332 | for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { | |
2333 | rep_idx += i; | |
2334 | if (target <= rep[rep_idx].freq) | |
2335 | edge_pwr = (s16) rep[rep_idx].edge; | |
2336 | } | |
2337 | ||
2338 | if (edge_pwr) | |
2339 | ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); | |
2340 | } | |
2341 | ||
2342 | ||
2343 | /* | |
2344 | * Power to PCDAC table functions | |
2345 | */ | |
2346 | ||
fa1c114f | 2347 | /* |
8f655dde NK |
2348 | * Fill Power to PCDAC table on RF5111 |
2349 | * | |
2350 | * No further processing is needed for RF5111, the only thing we have to | |
2351 | * do is fill the values below and above calibration range since eeprom data | |
2352 | * may not cover the entire PCDAC table. | |
fa1c114f | 2353 | */ |
8f655dde NK |
2354 | static void |
2355 | ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, | |
2356 | s16 *table_max) | |
2357 | { | |
2358 | u8 *pcdac_out = ah->ah_txpower.txp_pd_table; | |
2359 | u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; | |
2360 | u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; | |
2361 | s16 min_pwr, max_pwr; | |
2362 | ||
2363 | /* Get table boundaries */ | |
2364 | min_pwr = table_min[0]; | |
2365 | pcdac_0 = pcdac_tmp[0]; | |
2366 | ||
2367 | max_pwr = table_max[0]; | |
2368 | pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; | |
2369 | ||
2370 | /* Extrapolate below minimum using pcdac_0 */ | |
2371 | pcdac_i = 0; | |
2372 | for (i = 0; i < min_pwr; i++) | |
2373 | pcdac_out[pcdac_i++] = pcdac_0; | |
2374 | ||
2375 | /* Copy values from pcdac_tmp */ | |
2376 | pwr_idx = min_pwr; | |
2377 | for (i = 0 ; pwr_idx <= max_pwr && | |
2378 | pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { | |
2379 | pcdac_out[pcdac_i++] = pcdac_tmp[i]; | |
2380 | pwr_idx++; | |
2381 | } | |
2382 | ||
2383 | /* Extrapolate above maximum */ | |
2384 | while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) | |
2385 | pcdac_out[pcdac_i++] = pcdac_n; | |
2386 | ||
2387 | } | |
fa1c114f JS |
2388 | |
2389 | /* | |
8f655dde NK |
2390 | * Combine available XPD Curves and fill Linear Power to PCDAC table |
2391 | * on RF5112 | |
2392 | * | |
2393 | * RFX112 can have up to 2 curves (one for low txpower range and one for | |
2394 | * higher txpower range). We need to put them both on pcdac_out and place | |
2395 | * them in the correct location. In case we only have one curve available | |
2396 | * just fit it on pcdac_out (it's supposed to cover the entire range of | |
2397 | * available pwr levels since it's always the higher power curve). Extrapolate | |
2398 | * below and above final table if needed. | |
fa1c114f | 2399 | */ |
8f655dde NK |
2400 | static void |
2401 | ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, | |
2402 | s16 *table_max, u8 pdcurves) | |
fa1c114f | 2403 | { |
8f655dde NK |
2404 | u8 *pcdac_out = ah->ah_txpower.txp_pd_table; |
2405 | u8 *pcdac_low_pwr; | |
2406 | u8 *pcdac_high_pwr; | |
2407 | u8 *pcdac_tmp; | |
2408 | u8 pwr; | |
2409 | s16 max_pwr_idx; | |
2410 | s16 min_pwr_idx; | |
2411 | s16 mid_pwr_idx = 0; | |
2412 | /* Edge flag turs on the 7nth bit on the PCDAC | |
2413 | * to delcare the higher power curve (force values | |
2414 | * to be greater than 64). If we only have one curve | |
2415 | * we don't need to set this, if we have 2 curves and | |
2416 | * fill the table backwards this can also be used to | |
2417 | * switch from higher power curve to lower power curve */ | |
2418 | u8 edge_flag; | |
2419 | int i; | |
2420 | ||
2421 | /* When we have only one curve available | |
2422 | * that's the higher power curve. If we have | |
2423 | * two curves the first is the high power curve | |
2424 | * and the next is the low power curve. */ | |
2425 | if (pdcurves > 1) { | |
2426 | pcdac_low_pwr = ah->ah_txpower.tmpL[1]; | |
2427 | pcdac_high_pwr = ah->ah_txpower.tmpL[0]; | |
2428 | mid_pwr_idx = table_max[1] - table_min[1] - 1; | |
2429 | max_pwr_idx = (table_max[0] - table_min[0]) / 2; | |
2430 | ||
2431 | /* If table size goes beyond 31.5dB, keep the | |
2432 | * upper 31.5dB range when setting tx power. | |
2433 | * Note: 126 = 31.5 dB in quarter dB steps */ | |
2434 | if (table_max[0] - table_min[1] > 126) | |
2435 | min_pwr_idx = table_max[0] - 126; | |
2436 | else | |
2437 | min_pwr_idx = table_min[1]; | |
2438 | ||
2439 | /* Since we fill table backwards | |
2440 | * start from high power curve */ | |
2441 | pcdac_tmp = pcdac_high_pwr; | |
2442 | ||
2443 | edge_flag = 0x40; | |
2444 | #if 0 | |
2445 | /* If both min and max power limits are in lower | |
2446 | * power curve's range, only use the low power curve. | |
2447 | * TODO: min/max levels are related to target | |
2448 | * power values requested from driver/user | |
2449 | * XXX: Is this really needed ? */ | |
2450 | if (min_pwr < table_max[1] && | |
2451 | max_pwr < table_max[1]) { | |
2452 | edge_flag = 0; | |
2453 | pcdac_tmp = pcdac_low_pwr; | |
2454 | max_pwr_idx = (table_max[1] - table_min[1])/2; | |
2455 | } | |
fa1c114f | 2456 | #endif |
8f655dde NK |
2457 | } else { |
2458 | pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ | |
2459 | pcdac_high_pwr = ah->ah_txpower.tmpL[0]; | |
2460 | min_pwr_idx = table_min[0]; | |
2461 | max_pwr_idx = (table_max[0] - table_min[0]) / 2; | |
2462 | pcdac_tmp = pcdac_high_pwr; | |
2463 | edge_flag = 0; | |
2464 | } | |
2465 | ||
2466 | /* This is used when setting tx power*/ | |
2467 | ah->ah_txpower.txp_min_idx = min_pwr_idx/2; | |
2468 | ||
2469 | /* Fill Power to PCDAC table backwards */ | |
2470 | pwr = max_pwr_idx; | |
2471 | for (i = 63; i >= 0; i--) { | |
2472 | /* Entering lower power range, reset | |
2473 | * edge flag and set pcdac_tmp to lower | |
2474 | * power curve.*/ | |
2475 | if (edge_flag == 0x40 && | |
2476 | (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { | |
2477 | edge_flag = 0x00; | |
2478 | pcdac_tmp = pcdac_low_pwr; | |
2479 | pwr = mid_pwr_idx/2; | |
2480 | } | |
2481 | ||
2482 | /* Don't go below 1, extrapolate below if we have | |
2483 | * already swithced to the lower power curve -or | |
2484 | * we only have one curve and edge_flag is zero | |
2485 | * anyway */ | |
2486 | if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { | |
2487 | while (i >= 0) { | |
2488 | pcdac_out[i] = pcdac_out[i + 1]; | |
2489 | i--; | |
2490 | } | |
2491 | break; | |
2492 | } | |
2493 | ||
2494 | pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; | |
2495 | ||
2496 | /* Extrapolate above if pcdac is greater than | |
2497 | * 126 -this can happen because we OR pcdac_out | |
2498 | * value with edge_flag on high power curve */ | |
2499 | if (pcdac_out[i] > 126) | |
2500 | pcdac_out[i] = 126; | |
2501 | ||
2502 | /* Decrease by a 0.5dB step */ | |
2503 | pwr--; | |
2504 | } | |
fa1c114f JS |
2505 | } |
2506 | ||
8f655dde NK |
2507 | /* Write PCDAC values on hw */ |
2508 | static void | |
2509 | ath5k_setup_pcdac_table(struct ath5k_hw *ah) | |
2510 | { | |
2511 | u8 *pcdac_out = ah->ah_txpower.txp_pd_table; | |
2512 | int i; | |
2513 | ||
2514 | /* | |
2515 | * Write TX power values | |
2516 | */ | |
2517 | for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { | |
2518 | ath5k_hw_reg_write(ah, | |
2519 | (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | | |
2520 | (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), | |
2521 | AR5K_PHY_PCDAC_TXPOWER(i)); | |
2522 | } | |
2523 | } | |
2524 | ||
2525 | ||
fa1c114f | 2526 | /* |
8f655dde | 2527 | * Power to PDADC table functions |
fa1c114f | 2528 | */ |
8f655dde NK |
2529 | |
2530 | /* | |
2531 | * Set the gain boundaries and create final Power to PDADC table | |
2532 | * | |
2533 | * We can have up to 4 pd curves, we need to do a simmilar process | |
2534 | * as we do for RF5112. This time we don't have an edge_flag but we | |
2535 | * set the gain boundaries on a separate register. | |
2536 | */ | |
2537 | static void | |
2538 | ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, | |
2539 | s16 *pwr_min, s16 *pwr_max, u8 pdcurves) | |
fa1c114f | 2540 | { |
8f655dde NK |
2541 | u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; |
2542 | u8 *pdadc_out = ah->ah_txpower.txp_pd_table; | |
2543 | u8 *pdadc_tmp; | |
2544 | s16 pdadc_0; | |
2545 | u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; | |
2546 | u8 pd_gain_overlap; | |
2547 | ||
2548 | /* Note: Register value is initialized on initvals | |
2549 | * there is no feedback from hw. | |
2550 | * XXX: What about pd_gain_overlap from EEPROM ? */ | |
2551 | pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & | |
2552 | AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; | |
2553 | ||
2554 | /* Create final PDADC table */ | |
2555 | for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { | |
2556 | pdadc_tmp = ah->ah_txpower.tmpL[pdg]; | |
2557 | ||
2558 | if (pdg == pdcurves - 1) | |
2559 | /* 2 dB boundary stretch for last | |
2560 | * (higher power) curve */ | |
2561 | gain_boundaries[pdg] = pwr_max[pdg] + 4; | |
2562 | else | |
2563 | /* Set gain boundary in the middle | |
2564 | * between this curve and the next one */ | |
2565 | gain_boundaries[pdg] = | |
2566 | (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; | |
2567 | ||
2568 | /* Sanity check in case our 2 db stretch got out of | |
2569 | * range. */ | |
2570 | if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) | |
2571 | gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; | |
2572 | ||
2573 | /* For the first curve (lower power) | |
2574 | * start from 0 dB */ | |
2575 | if (pdg == 0) | |
2576 | pdadc_0 = 0; | |
2577 | else | |
2578 | /* For the other curves use the gain overlap */ | |
2579 | pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - | |
2580 | pd_gain_overlap; | |
fa1c114f | 2581 | |
8f655dde NK |
2582 | /* Force each power step to be at least 0.5 dB */ |
2583 | if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) | |
2584 | pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; | |
2585 | else | |
2586 | pwr_step = 1; | |
2587 | ||
2588 | /* If pdadc_0 is negative, we need to extrapolate | |
2589 | * below this pdgain by a number of pwr_steps */ | |
2590 | while ((pdadc_0 < 0) && (pdadc_i < 128)) { | |
2591 | s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; | |
2592 | pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; | |
2593 | pdadc_0++; | |
2594 | } | |
2595 | ||
2596 | /* Set last pwr level, using gain boundaries */ | |
2597 | pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; | |
2598 | /* Limit it to be inside pwr range */ | |
2599 | table_size = pwr_max[pdg] - pwr_min[pdg]; | |
2600 | max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; | |
2601 | ||
2602 | /* Fill pdadc_out table */ | |
2603 | while (pdadc_0 < max_idx) | |
2604 | pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; | |
2605 | ||
2606 | /* Need to extrapolate above this pdgain? */ | |
2607 | if (pdadc_n <= max_idx) | |
2608 | continue; | |
2609 | ||
2610 | /* Force each power step to be at least 0.5 dB */ | |
2611 | if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) | |
2612 | pwr_step = pdadc_tmp[table_size - 1] - | |
2613 | pdadc_tmp[table_size - 2]; | |
2614 | else | |
2615 | pwr_step = 1; | |
2616 | ||
2617 | /* Extrapolate above */ | |
2618 | while ((pdadc_0 < (s16) pdadc_n) && | |
2619 | (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { | |
2620 | s16 tmp = pdadc_tmp[table_size - 1] + | |
2621 | (pdadc_0 - max_idx) * pwr_step; | |
2622 | pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; | |
2623 | pdadc_0++; | |
2624 | } | |
fa1c114f JS |
2625 | } |
2626 | ||
8f655dde NK |
2627 | while (pdg < AR5K_EEPROM_N_PD_GAINS) { |
2628 | gain_boundaries[pdg] = gain_boundaries[pdg - 1]; | |
2629 | pdg++; | |
2630 | } | |
2631 | ||
2632 | while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { | |
2633 | pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; | |
2634 | pdadc_i++; | |
2635 | } | |
2636 | ||
2637 | /* Set gain boundaries */ | |
2638 | ath5k_hw_reg_write(ah, | |
2639 | AR5K_REG_SM(pd_gain_overlap, | |
2640 | AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | | |
2641 | AR5K_REG_SM(gain_boundaries[0], | |
2642 | AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | | |
2643 | AR5K_REG_SM(gain_boundaries[1], | |
2644 | AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | | |
2645 | AR5K_REG_SM(gain_boundaries[2], | |
2646 | AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | | |
2647 | AR5K_REG_SM(gain_boundaries[3], | |
2648 | AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), | |
2649 | AR5K_PHY_TPC_RG5); | |
2650 | ||
2651 | /* Used for setting rate power table */ | |
2652 | ah->ah_txpower.txp_min_idx = pwr_min[0]; | |
2653 | ||
2654 | } | |
2655 | ||
2656 | /* Write PDADC values on hw */ | |
2657 | static void | |
2658 | ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, | |
2659 | u8 pdcurves, u8 *pdg_to_idx) | |
2660 | { | |
2661 | u8 *pdadc_out = ah->ah_txpower.txp_pd_table; | |
2662 | u32 reg; | |
2663 | u8 i; | |
2664 | ||
2665 | /* Select the right pdgain curves */ | |
2666 | ||
2667 | /* Clear current settings */ | |
2668 | reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); | |
2669 | reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | | |
2670 | AR5K_PHY_TPC_RG1_PDGAIN_2 | | |
2671 | AR5K_PHY_TPC_RG1_PDGAIN_3 | | |
2672 | AR5K_PHY_TPC_RG1_NUM_PD_GAIN); | |
2673 | ||
903b474e | 2674 | /* |
8f655dde | 2675 | * Use pd_gains curve from eeprom |
136bfc79 | 2676 | * |
8f655dde NK |
2677 | * This overrides the default setting from initvals |
2678 | * in case some vendors (e.g. Zcomax) don't use the default | |
2679 | * curves. If we don't honor their settings we 'll get a | |
2680 | * 5dB (1 * gain overlap ?) drop. | |
903b474e | 2681 | */ |
8f655dde | 2682 | reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); |
903b474e | 2683 | |
8f655dde NK |
2684 | switch (pdcurves) { |
2685 | case 3: | |
2686 | reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); | |
2687 | /* Fall through */ | |
2688 | case 2: | |
2689 | reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); | |
2690 | /* Fall through */ | |
2691 | case 1: | |
2692 | reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); | |
2693 | break; | |
2694 | } | |
2695 | ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); | |
fa1c114f JS |
2696 | |
2697 | /* | |
2698 | * Write TX power values | |
2699 | */ | |
2700 | for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { | |
2701 | ath5k_hw_reg_write(ah, | |
8f655dde NK |
2702 | ((pdadc_out[4*i + 0] & 0xff) << 0) | |
2703 | ((pdadc_out[4*i + 1] & 0xff) << 8) | | |
2704 | ((pdadc_out[4*i + 2] & 0xff) << 16) | | |
2705 | ((pdadc_out[4*i + 3] & 0xff) << 24), | |
2706 | AR5K_PHY_PDADC_TXPOWER(i)); | |
2707 | } | |
2708 | } | |
2709 | ||
2710 | ||
2711 | /* | |
2712 | * Common code for PCDAC/PDADC tables | |
2713 | */ | |
2714 | ||
2715 | /* | |
2716 | * This is the main function that uses all of the above | |
2717 | * to set PCDAC/PDADC table on hw for the current channel. | |
2718 | * This table is used for tx power calibration on the basband, | |
2719 | * without it we get weird tx power levels and in some cases | |
2720 | * distorted spectral mask | |
2721 | */ | |
2722 | static int | |
2723 | ath5k_setup_channel_powertable(struct ath5k_hw *ah, | |
2724 | struct ieee80211_channel *channel, | |
2725 | u8 ee_mode, u8 type) | |
2726 | { | |
2727 | struct ath5k_pdgain_info *pdg_L, *pdg_R; | |
2728 | struct ath5k_chan_pcal_info *pcinfo_L; | |
2729 | struct ath5k_chan_pcal_info *pcinfo_R; | |
2730 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; | |
2731 | u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; | |
2732 | s16 table_min[AR5K_EEPROM_N_PD_GAINS]; | |
2733 | s16 table_max[AR5K_EEPROM_N_PD_GAINS]; | |
2734 | u8 *tmpL; | |
2735 | u8 *tmpR; | |
2736 | u32 target = channel->center_freq; | |
2737 | int pdg, i; | |
2738 | ||
2739 | /* Get surounding freq piers for this channel */ | |
2740 | ath5k_get_chan_pcal_surrounding_piers(ah, channel, | |
2741 | &pcinfo_L, | |
2742 | &pcinfo_R); | |
2743 | ||
2744 | /* Loop over pd gain curves on | |
2745 | * surounding freq piers by index */ | |
2746 | for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { | |
2747 | ||
2748 | /* Fill curves in reverse order | |
2749 | * from lower power (max gain) | |
2750 | * to higher power. Use curve -> idx | |
af901ca1 | 2751 | * backmapping we did on eeprom init */ |
8f655dde NK |
2752 | u8 idx = pdg_curve_to_idx[pdg]; |
2753 | ||
2754 | /* Grab the needed curves by index */ | |
2755 | pdg_L = &pcinfo_L->pd_curves[idx]; | |
2756 | pdg_R = &pcinfo_R->pd_curves[idx]; | |
2757 | ||
2758 | /* Initialize the temp tables */ | |
2759 | tmpL = ah->ah_txpower.tmpL[pdg]; | |
2760 | tmpR = ah->ah_txpower.tmpR[pdg]; | |
2761 | ||
2762 | /* Set curve's x boundaries and create | |
2763 | * curves so that they cover the same | |
2764 | * range (if we don't do that one table | |
2765 | * will have values on some range and the | |
2766 | * other one won't have any so interpolation | |
2767 | * will fail) */ | |
2768 | table_min[pdg] = min(pdg_L->pd_pwr[0], | |
2769 | pdg_R->pd_pwr[0]) / 2; | |
2770 | ||
2771 | table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], | |
2772 | pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; | |
2773 | ||
2774 | /* Now create the curves on surrounding channels | |
2775 | * and interpolate if needed to get the final | |
2776 | * curve for this gain on this channel */ | |
2777 | switch (type) { | |
2778 | case AR5K_PWRTABLE_LINEAR_PCDAC: | |
2779 | /* Override min/max so that we don't loose | |
2780 | * accuracy (don't divide by 2) */ | |
2781 | table_min[pdg] = min(pdg_L->pd_pwr[0], | |
2782 | pdg_R->pd_pwr[0]); | |
2783 | ||
2784 | table_max[pdg] = | |
2785 | max(pdg_L->pd_pwr[pdg_L->pd_points - 1], | |
2786 | pdg_R->pd_pwr[pdg_R->pd_points - 1]); | |
2787 | ||
2788 | /* Override minimum so that we don't get | |
2789 | * out of bounds while extrapolating | |
2790 | * below. Don't do this when we have 2 | |
2791 | * curves and we are on the high power curve | |
2792 | * because table_min is ok in this case */ | |
2793 | if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { | |
2794 | ||
2795 | table_min[pdg] = | |
2796 | ath5k_get_linear_pcdac_min(pdg_L->pd_step, | |
2797 | pdg_R->pd_step, | |
2798 | pdg_L->pd_pwr, | |
2799 | pdg_R->pd_pwr); | |
2800 | ||
2801 | /* Don't go too low because we will | |
2802 | * miss the upper part of the curve. | |
2803 | * Note: 126 = 31.5dB (max power supported) | |
2804 | * in 0.25dB units */ | |
2805 | if (table_max[pdg] - table_min[pdg] > 126) | |
2806 | table_min[pdg] = table_max[pdg] - 126; | |
2807 | } | |
2808 | ||
2809 | /* Fall through */ | |
2810 | case AR5K_PWRTABLE_PWR_TO_PCDAC: | |
2811 | case AR5K_PWRTABLE_PWR_TO_PDADC: | |
2812 | ||
2813 | ath5k_create_power_curve(table_min[pdg], | |
2814 | table_max[pdg], | |
2815 | pdg_L->pd_pwr, | |
2816 | pdg_L->pd_step, | |
2817 | pdg_L->pd_points, tmpL, type); | |
2818 | ||
2819 | /* We are in a calibration | |
2820 | * pier, no need to interpolate | |
2821 | * between freq piers */ | |
2822 | if (pcinfo_L == pcinfo_R) | |
2823 | continue; | |
2824 | ||
2825 | ath5k_create_power_curve(table_min[pdg], | |
2826 | table_max[pdg], | |
2827 | pdg_R->pd_pwr, | |
2828 | pdg_R->pd_step, | |
2829 | pdg_R->pd_points, tmpR, type); | |
2830 | break; | |
2831 | default: | |
2832 | return -EINVAL; | |
2833 | } | |
2834 | ||
2835 | /* Interpolate between curves | |
2836 | * of surounding freq piers to | |
2837 | * get the final curve for this | |
2838 | * pd gain. Re-use tmpL for interpolation | |
2839 | * output */ | |
2840 | for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && | |
2841 | (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { | |
2842 | tmpL[i] = (u8) ath5k_get_interpolated_value(target, | |
2843 | (s16) pcinfo_L->freq, | |
2844 | (s16) pcinfo_R->freq, | |
2845 | (s16) tmpL[i], | |
2846 | (s16) tmpR[i]); | |
2847 | } | |
fa1c114f JS |
2848 | } |
2849 | ||
8f655dde NK |
2850 | /* Now we have a set of curves for this |
2851 | * channel on tmpL (x range is table_max - table_min | |
2852 | * and y values are tmpL[pdg][]) sorted in the same | |
af901ca1 | 2853 | * order as EEPROM (because we've used the backmapping). |
8f655dde NK |
2854 | * So for RF5112 it's from higher power to lower power |
2855 | * and for RF2413 it's from lower power to higher power. | |
2856 | * For RF5111 we only have one curve. */ | |
2857 | ||
2858 | /* Fill min and max power levels for this | |
2859 | * channel by interpolating the values on | |
2860 | * surounding channels to complete the dataset */ | |
2861 | ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, | |
2862 | (s16) pcinfo_L->freq, | |
2863 | (s16) pcinfo_R->freq, | |
2864 | pcinfo_L->min_pwr, pcinfo_R->min_pwr); | |
2865 | ||
2866 | ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, | |
2867 | (s16) pcinfo_L->freq, | |
2868 | (s16) pcinfo_R->freq, | |
2869 | pcinfo_L->max_pwr, pcinfo_R->max_pwr); | |
2870 | ||
2871 | /* We are ready to go, fill PCDAC/PDADC | |
2872 | * table and write settings on hardware */ | |
2873 | switch (type) { | |
2874 | case AR5K_PWRTABLE_LINEAR_PCDAC: | |
2875 | /* For RF5112 we can have one or two curves | |
2876 | * and each curve covers a certain power lvl | |
2877 | * range so we need to do some more processing */ | |
2878 | ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, | |
2879 | ee->ee_pd_gains[ee_mode]); | |
2880 | ||
2881 | /* Set txp.offset so that we can | |
2882 | * match max power value with max | |
2883 | * table index */ | |
2884 | ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); | |
2885 | ||
2886 | /* Write settings on hw */ | |
2887 | ath5k_setup_pcdac_table(ah); | |
2888 | break; | |
2889 | case AR5K_PWRTABLE_PWR_TO_PCDAC: | |
2890 | /* We are done for RF5111 since it has only | |
2891 | * one curve, just fit the curve on the table */ | |
2892 | ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); | |
2893 | ||
2894 | /* No rate powertable adjustment for RF5111 */ | |
2895 | ah->ah_txpower.txp_min_idx = 0; | |
2896 | ah->ah_txpower.txp_offset = 0; | |
2897 | ||
2898 | /* Write settings on hw */ | |
2899 | ath5k_setup_pcdac_table(ah); | |
2900 | break; | |
2901 | case AR5K_PWRTABLE_PWR_TO_PDADC: | |
2902 | /* Set PDADC boundaries and fill | |
2903 | * final PDADC table */ | |
2904 | ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, | |
2905 | ee->ee_pd_gains[ee_mode]); | |
2906 | ||
2907 | /* Write settings on hw */ | |
2908 | ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); | |
2909 | ||
2910 | /* Set txp.offset, note that table_min | |
2911 | * can be negative */ | |
2912 | ah->ah_txpower.txp_offset = table_min[0]; | |
2913 | break; | |
2914 | default: | |
2915 | return -EINVAL; | |
2916 | } | |
2917 | ||
2918 | return 0; | |
2919 | } | |
2920 | ||
2921 | ||
2922 | /* | |
2923 | * Per-rate tx power setting | |
2924 | * | |
2925 | * This is the code that sets the desired tx power (below | |
2926 | * maximum) on hw for each rate (we also have TPC that sets | |
2927 | * power per packet). We do that by providing an index on the | |
2928 | * PCDAC/PDADC table we set up. | |
2929 | */ | |
2930 | ||
2931 | /* | |
2932 | * Set rate power table | |
2933 | * | |
2934 | * For now we only limit txpower based on maximum tx power | |
2935 | * supported by hw (what's inside rate_info). We need to limit | |
2936 | * this even more, based on regulatory domain etc. | |
2937 | * | |
2938 | * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) | |
2939 | * and is indexed as follows: | |
2940 | * rates[0] - rates[7] -> OFDM rates | |
2941 | * rates[8] - rates[14] -> CCK rates | |
2942 | * rates[15] -> XR rates (they all have the same power) | |
2943 | */ | |
2944 | static void | |
2945 | ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, | |
2946 | struct ath5k_rate_pcal_info *rate_info, | |
2947 | u8 ee_mode) | |
2948 | { | |
2949 | unsigned int i; | |
2950 | u16 *rates; | |
2951 | ||
2952 | /* max_pwr is power level we got from driver/user in 0.5dB | |
2953 | * units, switch to 0.25dB units so we can compare */ | |
2954 | max_pwr *= 2; | |
2955 | max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; | |
2956 | ||
2957 | /* apply rate limits */ | |
2958 | rates = ah->ah_txpower.txp_rates_power_table; | |
2959 | ||
2960 | /* OFDM rates 6 to 24Mb/s */ | |
2961 | for (i = 0; i < 5; i++) | |
2962 | rates[i] = min(max_pwr, rate_info->target_power_6to24); | |
2963 | ||
2964 | /* Rest OFDM rates */ | |
2965 | rates[5] = min(rates[0], rate_info->target_power_36); | |
2966 | rates[6] = min(rates[0], rate_info->target_power_48); | |
2967 | rates[7] = min(rates[0], rate_info->target_power_54); | |
2968 | ||
2969 | /* CCK rates */ | |
2970 | /* 1L */ | |
2971 | rates[8] = min(rates[0], rate_info->target_power_6to24); | |
2972 | /* 2L */ | |
2973 | rates[9] = min(rates[0], rate_info->target_power_36); | |
2974 | /* 2S */ | |
2975 | rates[10] = min(rates[0], rate_info->target_power_36); | |
2976 | /* 5L */ | |
2977 | rates[11] = min(rates[0], rate_info->target_power_48); | |
2978 | /* 5S */ | |
2979 | rates[12] = min(rates[0], rate_info->target_power_48); | |
2980 | /* 11L */ | |
2981 | rates[13] = min(rates[0], rate_info->target_power_54); | |
2982 | /* 11S */ | |
2983 | rates[14] = min(rates[0], rate_info->target_power_54); | |
2984 | ||
2985 | /* XR rates */ | |
2986 | rates[15] = min(rates[0], rate_info->target_power_6to24); | |
2987 | ||
2988 | /* CCK rates have different peak to average ratio | |
2989 | * so we have to tweak their power so that gainf | |
2990 | * correction works ok. For this we use OFDM to | |
2991 | * CCK delta from eeprom */ | |
2992 | if ((ee_mode == AR5K_EEPROM_MODE_11G) && | |
2993 | (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) | |
2994 | for (i = 8; i <= 15; i++) | |
2995 | rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; | |
2996 | ||
a0823810 NK |
2997 | /* Now that we have all rates setup use table offset to |
2998 | * match the power range set by user with the power indices | |
2999 | * on PCDAC/PDADC table */ | |
3000 | for (i = 0; i < 16; i++) { | |
3001 | rates[i] += ah->ah_txpower.txp_offset; | |
3002 | /* Don't get out of bounds */ | |
3003 | if (rates[i] > 63) | |
3004 | rates[i] = 63; | |
3005 | } | |
3006 | ||
3007 | /* Min/max in 0.25dB units */ | |
3008 | ah->ah_txpower.txp_min_pwr = 2 * rates[7]; | |
3009 | ah->ah_txpower.txp_max_pwr = 2 * rates[0]; | |
8f655dde NK |
3010 | ah->ah_txpower.txp_ofdm = rates[7]; |
3011 | } | |
3012 | ||
3013 | ||
3014 | /* | |
3015 | * Set transmition power | |
3016 | */ | |
3017 | int | |
3018 | ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, | |
3019 | u8 ee_mode, u8 txpower) | |
3020 | { | |
3021 | struct ath5k_rate_pcal_info rate_info; | |
3022 | u8 type; | |
3023 | int ret; | |
3024 | ||
3025 | ATH5K_TRACE(ah->ah_sc); | |
3026 | if (txpower > AR5K_TUNE_MAX_TXPOWER) { | |
3027 | ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); | |
3028 | return -EINVAL; | |
3029 | } | |
8f655dde NK |
3030 | |
3031 | /* Reset TX power values */ | |
3032 | memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); | |
3033 | ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; | |
3034 | ah->ah_txpower.txp_min_pwr = 0; | |
3035 | ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER; | |
3036 | ||
3037 | /* Initialize TX power table */ | |
3038 | switch (ah->ah_radio) { | |
3039 | case AR5K_RF5111: | |
3040 | type = AR5K_PWRTABLE_PWR_TO_PCDAC; | |
3041 | break; | |
3042 | case AR5K_RF5112: | |
3043 | type = AR5K_PWRTABLE_LINEAR_PCDAC; | |
3044 | break; | |
3045 | case AR5K_RF2413: | |
3046 | case AR5K_RF5413: | |
3047 | case AR5K_RF2316: | |
3048 | case AR5K_RF2317: | |
3049 | case AR5K_RF2425: | |
3050 | type = AR5K_PWRTABLE_PWR_TO_PDADC; | |
3051 | break; | |
3052 | default: | |
3053 | return -EINVAL; | |
3054 | } | |
3055 | ||
3056 | /* FIXME: Only on channel/mode change */ | |
3057 | ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type); | |
3058 | if (ret) | |
3059 | return ret; | |
3060 | ||
3061 | /* Limit max power if we have a CTL available */ | |
3062 | ath5k_get_max_ctl_power(ah, channel); | |
3063 | ||
3064 | /* FIXME: Tx power limit for this regdomain | |
3065 | * XXX: Mac80211/CRDA will do that anyway ? */ | |
3066 | ||
3067 | /* FIXME: Antenna reduction stuff */ | |
3068 | ||
3069 | /* FIXME: Limit power on turbo modes */ | |
3070 | ||
3071 | /* FIXME: TPC scale reduction */ | |
3072 | ||
3073 | /* Get surounding channels for per-rate power table | |
3074 | * calibration */ | |
3075 | ath5k_get_rate_pcal_data(ah, channel, &rate_info); | |
3076 | ||
3077 | /* Setup rate power table */ | |
3078 | ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); | |
3079 | ||
3080 | /* Write rate power table on hw */ | |
fa1c114f JS |
3081 | ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | |
3082 | AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | | |
3083 | AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); | |
3084 | ||
3085 | ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | | |
3086 | AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | | |
3087 | AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); | |
3088 | ||
3089 | ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | | |
3090 | AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | | |
3091 | AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); | |
3092 | ||
3093 | ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | | |
3094 | AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | | |
3095 | AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); | |
3096 | ||
8f655dde NK |
3097 | /* FIXME: TPC support */ |
3098 | if (ah->ah_txpower.txp_tpc) { | |
fa1c114f JS |
3099 | ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | |
3100 | AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); | |
8f655dde NK |
3101 | |
3102 | ath5k_hw_reg_write(ah, | |
3103 | AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | | |
3104 | AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | | |
3105 | AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), | |
3106 | AR5K_TPC); | |
3107 | } else { | |
fa1c114f JS |
3108 | ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | |
3109 | AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); | |
8f655dde | 3110 | } |
fa1c114f JS |
3111 | |
3112 | return 0; | |
3113 | } | |
3114 | ||
a0823810 | 3115 | int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) |
fa1c114f JS |
3116 | { |
3117 | /*Just a try M.F.*/ | |
46026e8f | 3118 | struct ieee80211_channel *channel = ah->ah_current_channel; |
a0823810 | 3119 | u8 ee_mode; |
fa1c114f JS |
3120 | |
3121 | ATH5K_TRACE(ah->ah_sc); | |
a0823810 NK |
3122 | |
3123 | switch (channel->hw_value & CHANNEL_MODES) { | |
3124 | case CHANNEL_A: | |
3125 | case CHANNEL_T: | |
3126 | case CHANNEL_XR: | |
3127 | ee_mode = AR5K_EEPROM_MODE_11A; | |
3128 | break; | |
3129 | case CHANNEL_G: | |
3130 | case CHANNEL_TG: | |
3131 | ee_mode = AR5K_EEPROM_MODE_11G; | |
3132 | break; | |
3133 | case CHANNEL_B: | |
3134 | ee_mode = AR5K_EEPROM_MODE_11B; | |
3135 | break; | |
3136 | default: | |
3137 | ATH5K_ERR(ah->ah_sc, | |
3138 | "invalid channel: %d\n", channel->center_freq); | |
3139 | return -EINVAL; | |
3140 | } | |
3141 | ||
fa1c114f | 3142 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, |
8f655dde | 3143 | "changing txpower to %d\n", txpower); |
fa1c114f | 3144 | |
a0823810 | 3145 | return ath5k_hw_txpower(ah, channel, ee_mode, txpower); |
fa1c114f | 3146 | } |
c6e387a2 NK |
3147 | |
3148 | #undef _ATH5K_PHY |