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ath5k: Introduce ath5k_init_softc function as in ath9k
[linux-2.6-block.git] / drivers / net / wireless / ath / ath5k / eeprom.c
CommitLineData
c6e387a2
NK		 1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
8e218fb2
NK		 3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
c6e387a2
NK		 5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20/*************************************\
21* EEPROM access functions and helpers *
22\*************************************/
23
5a0e3ad6
TH		 24#include <linux/slab.h>
25
c6e387a2
NK		 26#include "ath5k.h"
27#include "reg.h"
28#include "debug.h"
29#include "base.h"
30
9320b5c4
NK		 31
32/******************\
33* Helper functions *
34\******************/
35
36/*
37 * Translate binary channel representation in EEPROM to frequency
38 */
39static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
40 unsigned int mode)
41{
42 u16 val;
43
44 if (bin == AR5K_EEPROM_CHANNEL_DIS)
45 return bin;
46
47 if (mode == AR5K_EEPROM_MODE_11A) {
48 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
49 val = (5 * bin) + 4800;
50 else
51 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
52 (bin * 10) + 5100;
53 } else {
54 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
55 val = bin + 2300;
56 else
57 val = bin + 2400;
58 }
59
60 return val;
61}
62
63
64/*********\
65* Parsers *
66\*********/
67
c6e387a2
NK		 68/*
69 * Read from eeprom
70 */
71static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
72{
73 u32 status, timeout;
74
c6e387a2
NK		 75 /*
76 * Initialize EEPROM access
77 */
78 if (ah->ah_version == AR5K_AR5210) {
79 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
80 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
81 } else {
82 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
83 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
84 AR5K_EEPROM_CMD_READ);
85 }
86
87 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
88 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
89 if (status & AR5K_EEPROM_STAT_RDDONE) {
90 if (status & AR5K_EEPROM_STAT_RDERR)
91 return -EIO;
92 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
93 0xffff);
94 return 0;
95 }
96 udelay(15);
97 }
98
99 return -ETIMEDOUT;
100}
101
1048643e
FF		 102/*
103 * Initialize eeprom & capabilities structs
104 */
105static int
106ath5k_eeprom_init_header(struct ath5k_hw *ah)
107{
108 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
109 int ret;
110 u16 val;
359207c6 111 u32 cksum, offset, eep_max = AR5K_EEPROM_INFO_MAX;
1048643e 112
1048643e
FF		 113 /*
114 * Read values from EEPROM and store them in the capability structure
115 */
116 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
117 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
118 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
119 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
120 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
121
122 /* Return if we have an old EEPROM */
123 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
124 return 0;
125
1048643e
FF		 126 /*
127 * Validate the checksum of the EEPROM date. There are some
128 * devices with invalid EEPROMs.
129 */
359207c6
LR		 130 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val);
131 if (val) {
132 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) <<
133 AR5K_EEPROM_SIZE_ENDLOC_SHIFT;
134 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_LOWER, val);
135 eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE;
136
137 /*
138 * Fail safe check to prevent stupid loops due
139 * to busted EEPROMs. XXX: This value is likely too
140 * big still, waiting on a better value.
141 */
142 if (eep_max > (3 * AR5K_EEPROM_INFO_MAX)) {
143 ATH5K_ERR(ah->ah_sc, "Invalid max custom EEPROM size: "
144 "%d (0x%04x) max expected: %d (0x%04x)\n",
145 eep_max, eep_max,
146 3 * AR5K_EEPROM_INFO_MAX,
147 3 * AR5K_EEPROM_INFO_MAX);
148 return -EIO;
149 }
150 }
151
152 for (cksum = 0, offset = 0; offset < eep_max; offset++) {
1048643e
FF		 153 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
154 cksum ^= val;
155 }
156 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
359207c6
LR		 157 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM "
158 "checksum: 0x%04x eep_max: 0x%04x (%s)\n",
159 cksum, eep_max,
160 eep_max == AR5K_EEPROM_INFO_MAX ?
161 "default size" : "custom size");
1048643e
FF		 162 return -EIO;
163 }
1048643e
FF		 164
165 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
166 ee_ant_gain);
167
168 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
169 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
170 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
0ea9c00c
NK		 171
172 /* XXX: Don't know which versions include these two */
173 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2);
174
175 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
176 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3);
177
178 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
179 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4);
180 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5);
181 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6);
182 }
1048643e
FF		 183 }
184
185 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
186 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
187 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
188 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
189
190 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
191 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
192 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
193 }
194
1889ba0a
NK		 195 AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
196
197 if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val)
198 ee->ee_is_hb63 = true;
199 else
200 ee->ee_is_hb63 = false;
201
202 AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val);
203 ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
204 ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
205
c38e7a93
NK		 206 /* Check if PCIE_OFFSET points to PCIE_SERDES_SECTION
207 * and enable serdes programming if needed.
208 *
209 * XXX: Serdes values seem to be fixed so
210 * no need to read them here, we write them
132b1c3e 211 * during ath5k_hw_init */
c38e7a93
NK		 212 AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val);
213 ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
214 true : false;
215
1048643e
FF		 216 return 0;
217}
218
219
c6e387a2
NK		 220/*
221 * Read antenna infos from eeprom
222 */
223static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
224 unsigned int mode)
225{
226 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
227 u32 o = *offset;
228 u16 val;
229 int ret, i = 0;
230
231 AR5K_EEPROM_READ(o++, val);
232 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
1048643e 233 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f;
c6e387a2
NK		 234 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
235
236 AR5K_EEPROM_READ(o++, val);
237 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
238 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
239 ee->ee_ant_control[mode][i++] = val & 0x3f;
240
241 AR5K_EEPROM_READ(o++, val);
242 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
243 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
244 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
245
246 AR5K_EEPROM_READ(o++, val);
247 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
248 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
249 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
250 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
251
252 AR5K_EEPROM_READ(o++, val);
253 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
254 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
255 ee->ee_ant_control[mode][i++] = val & 0x3f;
256
2bed03eb
NK		 257 /* Get antenna switch tables */
258 ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
e8f055f0 259 (ee->ee_ant_control[mode][0] << 4);
2bed03eb 260 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
c6e387a2
NK		 261 ee->ee_ant_control[mode][1] |
262 (ee->ee_ant_control[mode][2] << 6) |
263 (ee->ee_ant_control[mode][3] << 12) |
264 (ee->ee_ant_control[mode][4] << 18) |
265 (ee->ee_ant_control[mode][5] << 24);
2bed03eb 266 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
c6e387a2
NK		 267 ee->ee_ant_control[mode][6] |
268 (ee->ee_ant_control[mode][7] << 6) |
269 (ee->ee_ant_control[mode][8] << 12) |
270 (ee->ee_ant_control[mode][9] << 18) |
271 (ee->ee_ant_control[mode][10] << 24);
272
273 /* return new offset */
274 *offset = o;
275
276 return 0;
277}
278
279/*
0ea9c00c
NK		 280 * Read supported modes and some mode-specific calibration data
281 * from eeprom
c6e387a2
NK		 282 */
283static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
284 unsigned int mode)
285{
286 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
287 u32 o = *offset;
288 u16 val;
289 int ret;
290
1048643e
FF		 291 ee->ee_n_piers[mode] = 0;
292 AR5K_EEPROM_READ(o++, val);
293 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
294 switch(mode) {
295 case AR5K_EEPROM_MODE_11A:
8e218fb2
NK		 296 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
297 ee->ee_db[mode][3] = (val >> 2) & 0x7;
298 ee->ee_ob[mode][2] = (val << 1) & 0x7;
1048643e
FF		 299
300 AR5K_EEPROM_READ(o++, val);
8e218fb2
NK		 301 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
302 ee->ee_db[mode][2] = (val >> 12) & 0x7;
303 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
304 ee->ee_db[mode][1] = (val >> 6) & 0x7;
305 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
306 ee->ee_db[mode][0] = val & 0x7;
1048643e
FF		 307 break;
308 case AR5K_EEPROM_MODE_11G:
309 case AR5K_EEPROM_MODE_11B:
8e218fb2
NK		 310 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
311 ee->ee_db[mode][1] = val & 0x7;
1048643e
FF		 312 break;
313 }
314
c6e387a2
NK		 315 AR5K_EEPROM_READ(o++, val);
316 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
317 ee->ee_thr_62[mode] = val & 0xff;
318
319 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
320 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
321
322 AR5K_EEPROM_READ(o++, val);
323 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
324 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
325
326 AR5K_EEPROM_READ(o++, val);
327 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
328
329 if ((val & 0xff) & 0x80)
330 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
331 else
332 ee->ee_noise_floor_thr[mode] = val & 0xff;
333
334 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
335 ee->ee_noise_floor_thr[mode] =
336 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
337
338 AR5K_EEPROM_READ(o++, val);
339 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
340 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
341 ee->ee_xpd[mode] = val & 0x1;
342
687c8ff1
BR		 343 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
344 mode != AR5K_EEPROM_MODE_11B)
c6e387a2
NK		 345 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
346
347 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
348 AR5K_EEPROM_READ(o++, val);
349 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
350
351 if (mode == AR5K_EEPROM_MODE_11A)
352 ee->ee_xr_power[mode] = val & 0x3f;
353 else {
687c8ff1 354 /* b_DB_11[bg] and b_OB_11[bg] */
c6e387a2
NK		 355 ee->ee_ob[mode][0] = val & 0x7;
356 ee->ee_db[mode][0] = (val >> 3) & 0x7;
357 }
358 }
359
360 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
361 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
362 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
363 } else {
364 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
365
366 AR5K_EEPROM_READ(o++, val);
367 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
368
1048643e 369 if (mode == AR5K_EEPROM_MODE_11G) {
c6e387a2 370 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
1048643e
FF		 371 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
372 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
373 }
c6e387a2
NK		 374 }
375
376 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
377 mode == AR5K_EEPROM_MODE_11A) {
378 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
379 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
380 }
381
1048643e
FF		 382 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
383 goto done;
384
0ea9c00c
NK		 385 /* Note: >= v5 have bg freq piers on another location
386 * so these freq piers are ignored for >= v5 (should be 0xff
387 * anyway) */
1048643e
FF		 388 switch(mode) {
389 case AR5K_EEPROM_MODE_11A:
390 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
391 break;
392
393 AR5K_EEPROM_READ(o++, val);
394 ee->ee_margin_tx_rx[mode] = val & 0x3f;
395 break;
396 case AR5K_EEPROM_MODE_11B:
397 AR5K_EEPROM_READ(o++, val);
398
399 ee->ee_pwr_cal_b[0].freq =
400 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
401 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
402 ee->ee_n_piers[mode]++;
403
404 ee->ee_pwr_cal_b[1].freq =
405 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
406 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
407 ee->ee_n_piers[mode]++;
408
409 AR5K_EEPROM_READ(o++, val);
410 ee->ee_pwr_cal_b[2].freq =
411 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
412 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
413 ee->ee_n_piers[mode]++;
414
415 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
416 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
417 break;
418 case AR5K_EEPROM_MODE_11G:
419 AR5K_EEPROM_READ(o++, val);
420
421 ee->ee_pwr_cal_g[0].freq =
422 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
423 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
424 ee->ee_n_piers[mode]++;
425
426 ee->ee_pwr_cal_g[1].freq =
427 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
428 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
429 ee->ee_n_piers[mode]++;
430
431 AR5K_EEPROM_READ(o++, val);
432 ee->ee_turbo_max_power[mode] = val & 0x7f;
433 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
434
435 AR5K_EEPROM_READ(o++, val);
436 ee->ee_pwr_cal_g[2].freq =
437 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
438 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
439 ee->ee_n_piers[mode]++;
c6e387a2 440
1048643e
FF		 441 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
442 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
443
444 AR5K_EEPROM_READ(o++, val);
5f13bfac
BR		 445 ee->ee_i_cal[mode] = (val >> 5) & 0x3f;
446 ee->ee_q_cal[mode] = val & 0x1f;
1048643e
FF		 447
448 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
449 AR5K_EEPROM_READ(o++, val);
450 ee->ee_cck_ofdm_gain_delta = val & 0xff;
451 }
452 break;
453 }
454
3b3ee43d
PR		 455 /*
456 * Read turbo mode information on newer EEPROM versions
457 */
1048643e 458 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
3b3ee43d 459 goto done;
c6e387a2 460
1048643e
FF		 461 switch (mode){
462 case AR5K_EEPROM_MODE_11A:
463 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
c6e387a2 464
1048643e
FF		 465 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
466 AR5K_EEPROM_READ(o++, val);
467 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
468 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
469
470 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
471 AR5K_EEPROM_READ(o++, val);
472 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
473 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
474
475 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
476 ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
477 break;
478 case AR5K_EEPROM_MODE_11G:
479 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
480
481 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
482 AR5K_EEPROM_READ(o++, val);
483 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
484 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
485
486 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
487 AR5K_EEPROM_READ(o++, val);
488 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
489 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
490 break;
491 }
492
3b3ee43d 493done:
1048643e
FF		 494 /* return new offset */
495 *offset = o;
496
497 return 0;
498}
499
0ea9c00c 500/* Read mode-specific data (except power calibration data) */
1048643e
FF		 501static int
502ath5k_eeprom_init_modes(struct ath5k_hw *ah)
503{
504 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
505 u32 mode_offset[3];
506 unsigned int mode;
507 u32 offset;
508 int ret;
c6e387a2 509
c6e387a2 510 /*
1048643e 511 * Get values for all modes
c6e387a2 512 */
1048643e
FF		 513 mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
514 mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
515 mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
516
517 ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
518 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
519
520 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
521 offset = mode_offset[mode];
522
523 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
524 if (ret)
525 return ret;
526
527 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
528 if (ret)
529 return ret;
c6e387a2 530 }
1048643e
FF		 531
532 /* override for older eeprom versions for better performance */
533 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
534 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
535 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
536 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
c6e387a2 537 }
c6e387a2 538
1048643e
FF		 539 return 0;
540}
c6e387a2 541
0ea9c00c
NK		 542/* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff
543 * frequency mask) */
1048643e
FF		 544static inline int
545ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
0ea9c00c 546 struct ath5k_chan_pcal_info *pc, unsigned int mode)
1048643e 547{
0ea9c00c 548 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1048643e
FF		 549 int o = *offset;
550 int i = 0;
0ea9c00c 551 u8 freq1, freq2;
1048643e
FF		 552 int ret;
553 u16 val;
554
8e218fb2 555 ee->ee_n_piers[mode] = 0;
1048643e
FF		 556 while(i < max) {
557 AR5K_EEPROM_READ(o++, val);
558
8e218fb2
NK		 559 freq1 = val & 0xff;
560 if (!freq1)
561 break;
1048643e 562
8e218fb2
NK		 563 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
564 freq1, mode);
565 ee->ee_n_piers[mode]++;
1048643e 566
8e218fb2
NK		 567 freq2 = (val >> 8) & 0xff;
568 if (!freq2)
1048643e 569 break;
8e218fb2
NK		 570
571 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
572 freq2, mode);
573 ee->ee_n_piers[mode]++;
c6e387a2 574 }
0ea9c00c
NK		 575
576 /* return new offset */
1048643e 577 *offset = o;
c6e387a2 578
1048643e
FF		 579 return 0;
580}
581
0ea9c00c 582/* Read frequency piers for 802.11a */
1048643e
FF		 583static int
584ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
585{
586 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
587 struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
588 int i, ret;
589 u16 val;
590 u8 mask;
591
592 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
593 ath5k_eeprom_read_freq_list(ah, &offset,
594 AR5K_EEPROM_N_5GHZ_CHAN, pcal,
0ea9c00c 595 AR5K_EEPROM_MODE_11A);
1048643e
FF		 596 } else {
597 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
c6e387a2 598
c6e387a2 599 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 600 pcal[0].freq = (val >> 9) & mask;
601 pcal[1].freq = (val >> 2) & mask;
602 pcal[2].freq = (val << 5) & mask;
603
604 AR5K_EEPROM_READ(offset++, val);
605 pcal[2].freq |= (val >> 11) & 0x1f;
606 pcal[3].freq = (val >> 4) & mask;
607 pcal[4].freq = (val << 3) & mask;
608
609 AR5K_EEPROM_READ(offset++, val);
610 pcal[4].freq |= (val >> 13) & 0x7;
611 pcal[5].freq = (val >> 6) & mask;
612 pcal[6].freq = (val << 1) & mask;
613
614 AR5K_EEPROM_READ(offset++, val);
615 pcal[6].freq |= (val >> 15) & 0x1;
616 pcal[7].freq = (val >> 8) & mask;
617 pcal[8].freq = (val >> 1) & mask;
618 pcal[9].freq = (val << 6) & mask;
619
620 AR5K_EEPROM_READ(offset++, val);
621 pcal[9].freq |= (val >> 10) & 0x3f;
0ea9c00c
NK		 622
623 /* Fixed number of piers */
1048643e 624 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
c6e387a2 625
0ea9c00c
NK		 626 for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
627 pcal[i].freq = ath5k_eeprom_bin2freq(ee,
1048643e 628 pcal[i].freq, AR5K_EEPROM_MODE_11A);
0ea9c00c 629 }
1048643e 630 }
c6e387a2 631
1048643e
FF		 632 return 0;
633}
c6e387a2 634
0ea9c00c 635/* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */
1048643e
FF		 636static inline int
637ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
638{
639 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
640 struct ath5k_chan_pcal_info *pcal;
1048643e
FF		 641
642 switch(mode) {
643 case AR5K_EEPROM_MODE_11B:
644 pcal = ee->ee_pwr_cal_b;
645 break;
646 case AR5K_EEPROM_MODE_11G:
647 pcal = ee->ee_pwr_cal_g;
648 break;
649 default:
650 return -EINVAL;
651 }
c6e387a2 652
1048643e
FF		 653 ath5k_eeprom_read_freq_list(ah, &offset,
654 AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal,
0ea9c00c 655 mode);
c6e387a2 656
1048643e
FF		 657 return 0;
658}
c6e387a2 659
9320b5c4 660
8e218fb2
NK		 661/*
662 * Read power calibration for RF5111 chips
663 *
0ea9c00c 664 * For RF5111 we have an XPD -eXternal Power Detector- curve
8e218fb2
NK		 665 * for each calibrated channel. Each curve has 0,5dB Power steps
666 * on x axis and PCDAC steps (offsets) on y axis and looks like an
667 * exponential function. To recreate the curve we read 11 points
668 * here and interpolate later.
0ea9c00c 669 */
8e218fb2
NK		 670
671/* Used to match PCDAC steps with power values on RF5111 chips
672 * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
673 * steps that match with the power values we read from eeprom. On
674 * older eeprom versions (< 3.2) these steps are equaly spaced at
a180a130 675 * 10% of the pcdac curve -until the curve reaches its maximum-
8e218fb2
NK		 676 * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
677 * these 11 steps are spaced in a different way. This function returns
678 * the pcdac steps based on eeprom version and curve min/max so that we
679 * can have pcdac/pwr points.
680 */
681static inline void
682ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
683{
bbb33881 684 static const u16 intercepts3[] =
8e218fb2 685 { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
bbb33881 686 static const u16 intercepts3_2[] =
8e218fb2
NK		 687 { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
688 const u16 *ip;
689 int i;
690
691 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
692 ip = intercepts3_2;
693 else
694 ip = intercepts3;
695
696 for (i = 0; i < ARRAY_SIZE(intercepts3); i++)
697 vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100;
698}
699
700/* Convert RF5111 specific data to generic raw data
701 * used by interpolation code */
702static int
703ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
704 struct ath5k_chan_pcal_info *chinfo)
705{
706 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
707 struct ath5k_chan_pcal_info_rf5111 *pcinfo;
708 struct ath5k_pdgain_info *pd;
709 u8 pier, point, idx;
710 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
711
712 /* Fill raw data for each calibration pier */
713 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
714
715 pcinfo = &chinfo[pier].rf5111_info;
716
717 /* Allocate pd_curves for this cal pier */
718 chinfo[pier].pd_curves =
719 kcalloc(AR5K_EEPROM_N_PD_CURVES,
720 sizeof(struct ath5k_pdgain_info),
721 GFP_KERNEL);
722
723 if (!chinfo[pier].pd_curves)
724 return -ENOMEM;
725
726 /* Only one curve for RF5111
727 * find out which one and place
77c2061d 728 * in pd_curves.
8e218fb2
NK		 729 * Note: ee_x_gain is reversed here */
730 for (idx = 0; idx < AR5K_EEPROM_N_PD_CURVES; idx++) {
731
732 if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
733 pdgain_idx[0] = idx;
734 break;
735 }
736 }
737
738 ee->ee_pd_gains[mode] = 1;
739
740 pd = &chinfo[pier].pd_curves[idx];
741
742 pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111;
743
744 /* Allocate pd points for this curve */
745 pd->pd_step = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
746 sizeof(u8), GFP_KERNEL);
747 if (!pd->pd_step)
748 return -ENOMEM;
749
750 pd->pd_pwr = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
751 sizeof(s16), GFP_KERNEL);
752 if (!pd->pd_pwr)
753 return -ENOMEM;
754
755 /* Fill raw dataset
756 * (convert power to 0.25dB units
757 * for RF5112 combatibility) */
758 for (point = 0; point < pd->pd_points; point++) {
759
760 /* Absolute values */
761 pd->pd_pwr[point] = 2 * pcinfo->pwr[point];
762
763 /* Already sorted */
764 pd->pd_step[point] = pcinfo->pcdac[point];
765 }
766
767 /* Set min/max pwr */
768 chinfo[pier].min_pwr = pd->pd_pwr[0];
769 chinfo[pier].max_pwr = pd->pd_pwr[10];
770
771 }
772
773 return 0;
774}
775
776/* Parse EEPROM data */
1048643e
FF		 777static int
778ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
779{
780 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
781 struct ath5k_chan_pcal_info *pcal;
782 int offset, ret;
eaee7cc2 783 int i;
1048643e
FF		 784 u16 val;
785
786 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
787 switch(mode) {
788 case AR5K_EEPROM_MODE_11A:
789 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
790 return 0;
791
792 ret = ath5k_eeprom_init_11a_pcal_freq(ah,
793 offset + AR5K_EEPROM_GROUP1_OFFSET);
794 if (ret < 0)
795 return ret;
796
797 offset += AR5K_EEPROM_GROUP2_OFFSET;
798 pcal = ee->ee_pwr_cal_a;
799 break;
800 case AR5K_EEPROM_MODE_11B:
801 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
802 !AR5K_EEPROM_HDR_11G(ee->ee_header))
803 return 0;
804
805 pcal = ee->ee_pwr_cal_b;
806 offset += AR5K_EEPROM_GROUP3_OFFSET;
807
808 /* fixed piers */
809 pcal[0].freq = 2412;
810 pcal[1].freq = 2447;
811 pcal[2].freq = 2484;
812 ee->ee_n_piers[mode] = 3;
813 break;
814 case AR5K_EEPROM_MODE_11G:
815 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
816 return 0;
817
818 pcal = ee->ee_pwr_cal_g;
819 offset += AR5K_EEPROM_GROUP4_OFFSET;
820
821 /* fixed piers */
822 pcal[0].freq = 2312;
823 pcal[1].freq = 2412;
824 pcal[2].freq = 2484;
825 ee->ee_n_piers[mode] = 3;
826 break;
827 default:
828 return -EINVAL;
c6e387a2
NK		 829 }
830
1048643e
FF		 831 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
832 struct ath5k_chan_pcal_info_rf5111 *cdata =
833 &pcal[i].rf5111_info;
c6e387a2 834
1048643e
FF		 835 AR5K_EEPROM_READ(offset++, val);
836 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M);
837 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M);
838 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M);
c6e387a2 839
1048643e
FF		 840 AR5K_EEPROM_READ(offset++, val);
841 cdata->pwr[0] |= ((val >> 14) & 0x3);
842 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M);
843 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M);
844 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M);
c6e387a2 845
1048643e
FF		 846 AR5K_EEPROM_READ(offset++, val);
847 cdata->pwr[3] |= ((val >> 12) & 0xf);
848 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M);
849 cdata->pwr[5] = (val & AR5K_EEPROM_POWER_M);
c6e387a2 850
c6e387a2 851 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 852 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M);
853 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M);
854 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M);
c6e387a2
NK		 855
856 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 857 cdata->pwr[8] |= ((val >> 14) & 0x3);
858 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M);
859 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M);
860
861 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
862 cdata->pcdac_max, cdata->pcdac);
c6e387a2
NK		 863 }
864
8e218fb2 865 return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal);
1048643e 866}
c6e387a2 867
8e218fb2
NK		 868
869/*
870 * Read power calibration for RF5112 chips
871 *
0ea9c00c
NK		 872 * For RF5112 we have 4 XPD -eXternal Power Detector- curves
873 * for each calibrated channel on 0, -6, -12 and -18dbm but we only
8e218fb2
NK		 874 * use the higher (3) and the lower (0) curves. Each curve has 0.5dB
875 * power steps on x axis and PCDAC steps on y axis and looks like a
876 * linear function. To recreate the curve and pass the power values
877 * on hw, we read 4 points for xpd 0 (lower gain -> max power)
878 * and 3 points for xpd 3 (higher gain -> lower power) here and
879 * interpolate later.
0ea9c00c
NK		 880 *
881 * Note: Many vendors just use xpd 0 so xpd 3 is zeroed.
882 */
8e218fb2
NK		 883
884/* Convert RF5112 specific data to generic raw data
885 * used by interpolation code */
886static int
887ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
888 struct ath5k_chan_pcal_info *chinfo)
889{
890 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
891 struct ath5k_chan_pcal_info_rf5112 *pcinfo;
892 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
893 unsigned int pier, pdg, point;
894
895 /* Fill raw data for each calibration pier */
896 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
897
898 pcinfo = &chinfo[pier].rf5112_info;
899
900 /* Allocate pd_curves for this cal pier */
901 chinfo[pier].pd_curves =
902 kcalloc(AR5K_EEPROM_N_PD_CURVES,
903 sizeof(struct ath5k_pdgain_info),
904 GFP_KERNEL);
905
906 if (!chinfo[pier].pd_curves)
907 return -ENOMEM;
908
909 /* Fill pd_curves */
910 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
911
912 u8 idx = pdgain_idx[pdg];
913 struct ath5k_pdgain_info *pd =
914 &chinfo[pier].pd_curves[idx];
915
916 /* Lowest gain curve (max power) */
917 if (pdg == 0) {
918 /* One more point for better accuracy */
919 pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS;
920
921 /* Allocate pd points for this curve */
922 pd->pd_step = kcalloc(pd->pd_points,
923 sizeof(u8), GFP_KERNEL);
924
925 if (!pd->pd_step)
926 return -ENOMEM;
927
928 pd->pd_pwr = kcalloc(pd->pd_points,
929 sizeof(s16), GFP_KERNEL);
930
931 if (!pd->pd_pwr)
932 return -ENOMEM;
933
934
935 /* Fill raw dataset
936 * (all power levels are in 0.25dB units) */
937 pd->pd_step[0] = pcinfo->pcdac_x0[0];
938 pd->pd_pwr[0] = pcinfo->pwr_x0[0];
939
940 for (point = 1; point < pd->pd_points;
941 point++) {
942 /* Absolute values */
943 pd->pd_pwr[point] =
944 pcinfo->pwr_x0[point];
945
946 /* Deltas */
947 pd->pd_step[point] =
948 pd->pd_step[point - 1] +
949 pcinfo->pcdac_x0[point];
950 }
951
952 /* Set min power for this frequency */
953 chinfo[pier].min_pwr = pd->pd_pwr[0];
954
955 /* Highest gain curve (min power) */
956 } else if (pdg == 1) {
957
958 pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS;
959
960 /* Allocate pd points for this curve */
961 pd->pd_step = kcalloc(pd->pd_points,
962 sizeof(u8), GFP_KERNEL);
963
964 if (!pd->pd_step)
965 return -ENOMEM;
966
967 pd->pd_pwr = kcalloc(pd->pd_points,
968 sizeof(s16), GFP_KERNEL);
969
970 if (!pd->pd_pwr)
971 return -ENOMEM;
972
973 /* Fill raw dataset
974 * (all power levels are in 0.25dB units) */
975 for (point = 0; point < pd->pd_points;
976 point++) {
977 /* Absolute values */
978 pd->pd_pwr[point] =
979 pcinfo->pwr_x3[point];
980
981 /* Fixed points */
982 pd->pd_step[point] =
983 pcinfo->pcdac_x3[point];
984 }
985
986 /* Since we have a higher gain curve
987 * override min power */
988 chinfo[pier].min_pwr = pd->pd_pwr[0];
989 }
990 }
991 }
992
993 return 0;
994}
995
996/* Parse EEPROM data */
1048643e
FF		 997static int
998ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
999{
1000 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1001 struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
1002 struct ath5k_chan_pcal_info *gen_chan_info;
8e218fb2 1003 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1048643e 1004 u32 offset;
8e218fb2 1005 u8 i, c;
1048643e
FF		 1006 u16 val;
1007 int ret;
8e218fb2
NK		 1008 u8 pd_gains = 0;
1009
1010 /* Count how many curves we have and
1011 * identify them (which one of the 4
1012 * available curves we have on each count).
1013 * Curves are stored from lower (x0) to
1014 * higher (x3) gain */
1015 for (i = 0; i < AR5K_EEPROM_N_PD_CURVES; i++) {
1016 /* ee_x_gain[mode] is x gain mask */
1017 if ((ee->ee_x_gain[mode] >> i) & 0x1)
1018 pdgain_idx[pd_gains++] = i;
1019 }
1020 ee->ee_pd_gains[mode] = pd_gains;
1021
1022 if (pd_gains == 0 || pd_gains > 2)
1023 return -EINVAL;
c6e387a2 1024
1048643e
FF		 1025 switch (mode) {
1026 case AR5K_EEPROM_MODE_11A:
1027 /*
1028 * Read 5GHz EEPROM channels
1029 */
1030 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1031 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1032
1033 offset += AR5K_EEPROM_GROUP2_OFFSET;
1034 gen_chan_info = ee->ee_pwr_cal_a;
1035 break;
1036 case AR5K_EEPROM_MODE_11B:
1037 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1038 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1039 offset += AR5K_EEPROM_GROUP3_OFFSET;
1040
1041 /* NB: frequency piers parsed during mode init */
1042 gen_chan_info = ee->ee_pwr_cal_b;
1043 break;
1044 case AR5K_EEPROM_MODE_11G:
1045 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1046 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1047 offset += AR5K_EEPROM_GROUP4_OFFSET;
1048 else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1049 offset += AR5K_EEPROM_GROUP2_OFFSET;
1050
1051 /* NB: frequency piers parsed during mode init */
1052 gen_chan_info = ee->ee_pwr_cal_g;
1053 break;
1054 default:
1055 return -EINVAL;
1056 }
c6e387a2 1057
1048643e
FF		 1058 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1059 chan_pcal_info = &gen_chan_info[i].rf5112_info;
c6e387a2 1060
8e218fb2 1061 /* Power values in quarter dB
1048643e
FF		 1062 * for the lower xpd gain curve
1063 * (0 dBm -> higher output power) */
1064 for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
1065 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1066 chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff);
1067 chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff);
1048643e 1068 }
c6e387a2 1069
1048643e
FF		 1070 /* PCDAC steps
1071 * corresponding to the above power
1072 * measurements */
c6e387a2 1073 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 1074 chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
1075 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
1076 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);
c6e387a2 1077
8e218fb2 1078 /* Power values in quarter dB
1048643e
FF		 1079 * for the higher xpd gain curve
1080 * (18 dBm -> lower output power) */
c6e387a2 1081 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1082 chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff);
1083 chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff);
c6e387a2
NK		 1084
1085 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 1086 chan_pcal_info->pwr_x3[2] = (val & 0xff);
1087
1088 /* PCDAC steps
1089 * corresponding to the above power
0ea9c00c 1090 * measurements (fixed) */
1048643e
FF		 1091 chan_pcal_info->pcdac_x3[0] = 20;
1092 chan_pcal_info->pcdac_x3[1] = 35;
1093 chan_pcal_info->pcdac_x3[2] = 63;
1094
1095 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
8e218fb2 1096 chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f);
1048643e
FF		 1097
1098 /* Last xpd0 power level is also channel maximum */
1099 gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
1100 } else {
1101 chan_pcal_info->pcdac_x0[0] = 1;
8e218fb2 1102 gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff);
1048643e 1103 }
c6e387a2 1104
1048643e
FF		 1105 }
1106
8e218fb2 1107 return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info);
1048643e
FF		 1108}
1109
8e218fb2
NK		 1110
1111/*
1112 * Read power calibration for RF2413 chips
1113 *
1114 * For RF2413 we have a Power to PDDAC table (Power Detector)
1115 * instead of a PCDAC and 4 pd gain curves for each calibrated channel.
1116 * Each curve has power on x axis in 0.5 db steps and PDDADC steps on y
1117 * axis and looks like an exponential function like the RF5111 curve.
1118 *
1119 * To recreate the curves we read here the points and interpolate
1120 * later. Note that in most cases only 2 (higher and lower) curves are
1121 * used (like RF5112) but vendors have the oportunity to include all
1122 * 4 curves on eeprom. The final curve (higher power) has an extra
1123 * point for better accuracy like RF5112.
1124 */
1125
0ea9c00c 1126/* For RF2413 power calibration data doesn't start on a fixed location and
a180a130 1127 * if a mode is not supported, its section is missing -not zeroed-.
0ea9c00c
NK		 1128 * So we need to calculate the starting offset for each section by using
1129 * these two functions */
1130
1131/* Return the size of each section based on the mode and the number of pd
1132 * gains available (maximum 4). */
1048643e
FF		 1133static inline unsigned int
1134ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
1135{
1136 static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
1137 unsigned int sz;
1138
1139 sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
1140 sz *= ee->ee_n_piers[mode];
1141
1142 return sz;
1143}
1144
0ea9c00c
NK		 1145/* Return the starting offset for a section based on the modes supported
1146 * and each section's size. */
1048643e
FF		 1147static unsigned int
1148ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
1149{
1150 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
1151
1152 switch(mode) {
1153 case AR5K_EEPROM_MODE_11G:
1154 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
8e218fb2
NK		 1155 offset += ath5k_pdgains_size_2413(ee,
1156 AR5K_EEPROM_MODE_11B) +
1157 AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1048643e
FF		 1158 /* fall through */
1159 case AR5K_EEPROM_MODE_11B:
1160 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
8e218fb2
NK		 1161 offset += ath5k_pdgains_size_2413(ee,
1162 AR5K_EEPROM_MODE_11A) +
1163 AR5K_EEPROM_N_5GHZ_CHAN / 2;
1048643e
FF		 1164 /* fall through */
1165 case AR5K_EEPROM_MODE_11A:
1166 break;
1167 default:
1168 break;
1169 }
1170
1171 return offset;
1172}
1173
8e218fb2
NK		 1174/* Convert RF2413 specific data to generic raw data
1175 * used by interpolation code */
1176static int
1177ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
1178 struct ath5k_chan_pcal_info *chinfo)
1179{
1180 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1181 struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1182 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1183 unsigned int pier, pdg, point;
1184
1185 /* Fill raw data for each calibration pier */
1186 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1187
1188 pcinfo = &chinfo[pier].rf2413_info;
1189
1190 /* Allocate pd_curves for this cal pier */
1191 chinfo[pier].pd_curves =
1192 kcalloc(AR5K_EEPROM_N_PD_CURVES,
1193 sizeof(struct ath5k_pdgain_info),
1194 GFP_KERNEL);
1195
1196 if (!chinfo[pier].pd_curves)
1197 return -ENOMEM;
1198
1199 /* Fill pd_curves */
1200 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1201
1202 u8 idx = pdgain_idx[pdg];
1203 struct ath5k_pdgain_info *pd =
1204 &chinfo[pier].pd_curves[idx];
1205
1206 /* One more point for the highest power
1207 * curve (lowest gain) */
1208 if (pdg == ee->ee_pd_gains[mode] - 1)
1209 pd->pd_points = AR5K_EEPROM_N_PD_POINTS;
1210 else
1211 pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1;
1212
1213 /* Allocate pd points for this curve */
1214 pd->pd_step = kcalloc(pd->pd_points,
1215 sizeof(u8), GFP_KERNEL);
1216
1217 if (!pd->pd_step)
1218 return -ENOMEM;
1219
1220 pd->pd_pwr = kcalloc(pd->pd_points,
1221 sizeof(s16), GFP_KERNEL);
1222
1223 if (!pd->pd_pwr)
1224 return -ENOMEM;
1225
1226 /* Fill raw dataset
1227 * convert all pwr levels to
1228 * quarter dB for RF5112 combatibility */
1229 pd->pd_step[0] = pcinfo->pddac_i[pdg];
1230 pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg];
1231
1232 for (point = 1; point < pd->pd_points; point++) {
1233
1234 pd->pd_pwr[point] = pd->pd_pwr[point - 1] +
1235 2 * pcinfo->pwr[pdg][point - 1];
1236
1237 pd->pd_step[point] = pd->pd_step[point - 1] +
1238 pcinfo->pddac[pdg][point - 1];
1239
1240 }
1241
1242 /* Highest gain curve -> min power */
1243 if (pdg == 0)
1244 chinfo[pier].min_pwr = pd->pd_pwr[0];
1245
1246 /* Lowest gain curve -> max power */
1247 if (pdg == ee->ee_pd_gains[mode] - 1)
1248 chinfo[pier].max_pwr =
1249 pd->pd_pwr[pd->pd_points - 1];
1250 }
1251 }
1252
1253 return 0;
1254}
1255
1256/* Parse EEPROM data */
1048643e
FF		 1257static int
1258ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
1259{
1260 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
8e218fb2
NK		 1261 struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1262 struct ath5k_chan_pcal_info *chinfo;
1263 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1048643e 1264 u32 offset;
8e218fb2 1265 int idx, i, ret;
1048643e
FF		 1266 u16 val;
1267 u8 pd_gains = 0;
1268
8e218fb2
NK		 1269 /* Count how many curves we have and
1270 * identify them (which one of the 4
1271 * available curves we have on each count).
1272 * Curves are stored from higher to
1273 * lower gain so we go backwards */
1274 for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) {
1275 /* ee_x_gain[mode] is x gain mask */
1276 if ((ee->ee_x_gain[mode] >> idx) & 0x1)
1277 pdgain_idx[pd_gains++] = idx;
1278
1279 }
1048643e
FF		 1280 ee->ee_pd_gains[mode] = pd_gains;
1281
8e218fb2
NK		 1282 if (pd_gains == 0)
1283 return -EINVAL;
1284
1048643e
FF		 1285 offset = ath5k_cal_data_offset_2413(ee, mode);
1286 switch (mode) {
1287 case AR5K_EEPROM_MODE_11A:
1288 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1289 return 0;
1290
1291 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1292 offset += AR5K_EEPROM_N_5GHZ_CHAN / 2;
8e218fb2 1293 chinfo = ee->ee_pwr_cal_a;
1048643e
FF		 1294 break;
1295 case AR5K_EEPROM_MODE_11B:
1296 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1297 return 0;
c6e387a2 1298
1048643e
FF		 1299 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1300 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
8e218fb2 1301 chinfo = ee->ee_pwr_cal_b;
1048643e
FF		 1302 break;
1303 case AR5K_EEPROM_MODE_11G:
1304 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1305 return 0;
1306
1307 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1308 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
8e218fb2 1309 chinfo = ee->ee_pwr_cal_g;
1048643e
FF		 1310 break;
1311 default:
1312 return -EINVAL;
1313 }
1314
1048643e 1315 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
8e218fb2 1316 pcinfo = &chinfo[i].rf2413_info;
1048643e
FF		 1317
1318 /*
1319 * Read pwr_i, pddac_i and the first
1320 * 2 pd points (pwr, pddac)
1321 */
c6e387a2 1322 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1323 pcinfo->pwr_i[0] = val & 0x1f;
1324 pcinfo->pddac_i[0] = (val >> 5) & 0x7f;
1325 pcinfo->pwr[0][0] = (val >> 12) & 0xf;
c6e387a2 1326
1048643e 1327 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1328 pcinfo->pddac[0][0] = val & 0x3f;
1329 pcinfo->pwr[0][1] = (val >> 6) & 0xf;
1330 pcinfo->pddac[0][1] = (val >> 10) & 0x3f;
1048643e
FF		 1331
1332 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1333 pcinfo->pwr[0][2] = val & 0xf;
1334 pcinfo->pddac[0][2] = (val >> 4) & 0x3f;
1048643e 1335
8e218fb2
NK		 1336 pcinfo->pwr[0][3] = 0;
1337 pcinfo->pddac[0][3] = 0;
1048643e
FF		 1338
1339 if (pd_gains > 1) {
1340 /*
1341 * Pd gain 0 is not the last pd gain
1342 * so it only has 2 pd points.
1343 * Continue wih pd gain 1.
1344 */
8e218fb2 1345 pcinfo->pwr_i[1] = (val >> 10) & 0x1f;
1048643e 1346
8e218fb2 1347 pcinfo->pddac_i[1] = (val >> 15) & 0x1;
c6e387a2 1348 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1349 pcinfo->pddac_i[1] |= (val & 0x3F) << 1;
1048643e 1350
8e218fb2
NK		 1351 pcinfo->pwr[1][0] = (val >> 6) & 0xf;
1352 pcinfo->pddac[1][0] = (val >> 10) & 0x3f;
1048643e
FF		 1353
1354 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1355 pcinfo->pwr[1][1] = val & 0xf;
1356 pcinfo->pddac[1][1] = (val >> 4) & 0x3f;
1357 pcinfo->pwr[1][2] = (val >> 10) & 0xf;
1358
1359 pcinfo->pddac[1][2] = (val >> 14) & 0x3;
1048643e 1360 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1361 pcinfo->pddac[1][2] |= (val & 0xF) << 2;
1048643e 1362
8e218fb2
NK		 1363 pcinfo->pwr[1][3] = 0;
1364 pcinfo->pddac[1][3] = 0;
1048643e
FF		 1365 } else if (pd_gains == 1) {
1366 /*
1367 * Pd gain 0 is the last one so
1368 * read the extra point.
1369 */
8e218fb2 1370 pcinfo->pwr[0][3] = (val >> 10) & 0xf;
1048643e 1371
8e218fb2 1372 pcinfo->pddac[0][3] = (val >> 14) & 0x3;
1048643e 1373 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1374 pcinfo->pddac[0][3] |= (val & 0xF) << 2;
1048643e
FF		 1375 }
1376
1377 /*
1378 * Proceed with the other pd_gains
1379 * as above.
1380 */
1381 if (pd_gains > 2) {
8e218fb2
NK		 1382 pcinfo->pwr_i[2] = (val >> 4) & 0x1f;
1383 pcinfo->pddac_i[2] = (val >> 9) & 0x7f;
1048643e
FF		 1384
1385 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1386 pcinfo->pwr[2][0] = (val >> 0) & 0xf;
1387 pcinfo->pddac[2][0] = (val >> 4) & 0x3f;
1388 pcinfo->pwr[2][1] = (val >> 10) & 0xf;
1389
1390 pcinfo->pddac[2][1] = (val >> 14) & 0x3;
1048643e 1391 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1392 pcinfo->pddac[2][1] |= (val & 0xF) << 2;
1048643e 1393
8e218fb2
NK		 1394 pcinfo->pwr[2][2] = (val >> 4) & 0xf;
1395 pcinfo->pddac[2][2] = (val >> 8) & 0x3f;
1048643e 1396
8e218fb2
NK		 1397 pcinfo->pwr[2][3] = 0;
1398 pcinfo->pddac[2][3] = 0;
1048643e 1399 } else if (pd_gains == 2) {
8e218fb2
NK		 1400 pcinfo->pwr[1][3] = (val >> 4) & 0xf;
1401 pcinfo->pddac[1][3] = (val >> 8) & 0x3f;
1048643e
FF		 1402 }
1403
1404 if (pd_gains > 3) {
8e218fb2 1405 pcinfo->pwr_i[3] = (val >> 14) & 0x3;
1048643e 1406 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1407 pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2;
1048643e 1408
8e218fb2
NK		 1409 pcinfo->pddac_i[3] = (val >> 3) & 0x7f;
1410 pcinfo->pwr[3][0] = (val >> 10) & 0xf;
1411 pcinfo->pddac[3][0] = (val >> 14) & 0x3;
1048643e
FF		 1412
1413 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1414 pcinfo->pddac[3][0] |= (val & 0xF) << 2;
1415 pcinfo->pwr[3][1] = (val >> 4) & 0xf;
1416 pcinfo->pddac[3][1] = (val >> 8) & 0x3f;
1417
1418 pcinfo->pwr[3][2] = (val >> 14) & 0x3;
1048643e 1419 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1420 pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2;
1048643e 1421
8e218fb2
NK		 1422 pcinfo->pddac[3][2] = (val >> 2) & 0x3f;
1423 pcinfo->pwr[3][3] = (val >> 8) & 0xf;
1048643e 1424
8e218fb2 1425 pcinfo->pddac[3][3] = (val >> 12) & 0xF;
1048643e 1426 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1427 pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4;
1048643e 1428 } else if (pd_gains == 3) {
8e218fb2 1429 pcinfo->pwr[2][3] = (val >> 14) & 0x3;
1048643e 1430 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1431 pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2;
1048643e 1432
8e218fb2 1433 pcinfo->pddac[2][3] = (val >> 2) & 0x3f;
c6e387a2
NK		 1434 }
1435 }
1436
8e218fb2 1437 return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo);
1048643e
FF		 1438}
1439
8e218fb2 1440
1048643e
FF		 1441/*
1442 * Read per rate target power (this is the maximum tx power
1443 * supported by the card). This info is used when setting
1444 * tx power, no matter the channel.
1445 *
1446 * This also works for v5 EEPROMs.
1447 */
8e218fb2
NK		 1448static int
1449ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
1048643e
FF		 1450{
1451 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1452 struct ath5k_rate_pcal_info *rate_pcal_info;
8e218fb2 1453 u8 *rate_target_pwr_num;
1048643e
FF		 1454 u32 offset;
1455 u16 val;
1456 int ret, i;
1457
1458 offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
1459 rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1460 switch (mode) {
1461 case AR5K_EEPROM_MODE_11A:
1462 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
1463 rate_pcal_info = ee->ee_rate_tpwr_a;
1464 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN;
1465 break;
1466 case AR5K_EEPROM_MODE_11B:
1467 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
1468 rate_pcal_info = ee->ee_rate_tpwr_b;
1469 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1470 break;
1471 case AR5K_EEPROM_MODE_11G:
1472 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
1473 rate_pcal_info = ee->ee_rate_tpwr_g;
1474 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1475 break;
1476 default:
1477 return -EINVAL;
1478 }
1479
1480 /* Different freq mask for older eeproms (<= v3.2) */
1481 if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
1482 for (i = 0; i < (*rate_target_pwr_num); i++) {
1483 AR5K_EEPROM_READ(offset++, val);
1484 rate_pcal_info[i].freq =
1485 ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1486
1487 rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f);
1488 rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f;
1489
1490 AR5K_EEPROM_READ(offset++, val);
1491
1492 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1493 val == 0) {
1494 (*rate_target_pwr_num) = i;
1495 break;
1496 }
1497
1498 rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7);
1499 rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f);
1500 rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f);
1501 }
1502 } else {
1503 for (i = 0; i < (*rate_target_pwr_num); i++) {
1504 AR5K_EEPROM_READ(offset++, val);
1505 rate_pcal_info[i].freq =
1506 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1507
1508 rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f);
1509 rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f;
1510
1511 AR5K_EEPROM_READ(offset++, val);
1512
1513 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1514 val == 0) {
1515 (*rate_target_pwr_num) = i;
1516 break;
1517 }
1518
1519 rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf;
1520 rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f);
1521 rate_pcal_info[i].target_power_54 = (val & 0x3f);
1522 }
1523 }
1524
1525 return 0;
1526}
1527
9320b5c4 1528
0ea9c00c
NK		 1529/*
1530 * Read per channel calibration info from EEPROM
1531 *
1532 * This info is used to calibrate the baseband power table. Imagine
1533 * that for each channel there is a power curve that's hw specific
1534 * (depends on amplifier etc) and we try to "correct" this curve using
bf48aabb 1535 * offsets we pass on to phy chip (baseband -> before amplifier) so that
0ea9c00c
NK		 1536 * it can use accurate power values when setting tx power (takes amplifier's
1537 * performance on each channel into account).
1538 *
1539 * EEPROM provides us with the offsets for some pre-calibrated channels
1540 * and we have to interpolate to create the full table for these channels and
1541 * also the table for any channel.
1542 */
1048643e
FF		 1543static int
1544ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
1545{
1546 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1547 int (*read_pcal)(struct ath5k_hw *hw, int mode);
1548 int mode;
1549 int err;
1550
1551 if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
1552 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
1553 read_pcal = ath5k_eeprom_read_pcal_info_5112;
1554 else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
1555 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
1556 read_pcal = ath5k_eeprom_read_pcal_info_2413;
1557 else
1558 read_pcal = ath5k_eeprom_read_pcal_info_5111;
1559
8e218fb2
NK		 1560
1561 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G;
1562 mode++) {
1048643e
FF		 1563 err = read_pcal(ah, mode);
1564 if (err)
1565 return err;
1566
1567 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
1568 if (err < 0)
1569 return err;
1570 }
1571
1572 return 0;
1573}
1574
8e218fb2
NK		 1575static int
1576ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
1577{
1578 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1579 struct ath5k_chan_pcal_info *chinfo;
1580 u8 pier, pdg;
1581
1582 switch (mode) {
1583 case AR5K_EEPROM_MODE_11A:
1584 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1585 return 0;
1586 chinfo = ee->ee_pwr_cal_a;
1587 break;
1588 case AR5K_EEPROM_MODE_11B:
1589 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1590 return 0;
1591 chinfo = ee->ee_pwr_cal_b;
1592 break;
1593 case AR5K_EEPROM_MODE_11G:
1594 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1595 return 0;
1596 chinfo = ee->ee_pwr_cal_g;
1597 break;
1598 default:
1599 return -EINVAL;
1600 }
1601
1602 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1603 if (!chinfo[pier].pd_curves)
1604 continue;
1605
1606 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1607 struct ath5k_pdgain_info *pd =
1608 &chinfo[pier].pd_curves[pdg];
1609
1610 if (pd != NULL) {
1611 kfree(pd->pd_step);
1612 kfree(pd->pd_pwr);
1613 }
1614 }
1615
1616 kfree(chinfo[pier].pd_curves);
1617 }
1618
1619 return 0;
1620}
1621
0ea9c00c 1622/* Read conformance test limits used for regulatory control */
1048643e
FF		 1623static int
1624ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
1625{
1626 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1627 struct ath5k_edge_power *rep;
1628 unsigned int fmask, pmask;
1629 unsigned int ctl_mode;
1630 int ret, i, j;
1631 u32 offset;
1632 u16 val;
1633
1634 pmask = AR5K_EEPROM_POWER_M;
1635 fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
1636 offset = AR5K_EEPROM_CTL(ee->ee_version);
1637 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
1638 for (i = 0; i < ee->ee_ctls; i += 2) {
1639 AR5K_EEPROM_READ(offset++, val);
1640 ee->ee_ctl[i] = (val >> 8) & 0xff;
1641 ee->ee_ctl[i + 1] = val & 0xff;
1642 }
1643
1644 offset = AR5K_EEPROM_GROUP8_OFFSET;
1645 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
1646 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
1647 AR5K_EEPROM_GROUP5_OFFSET;
1648 else
1649 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1650
1651 rep = ee->ee_ctl_pwr;
1652 for(i = 0; i < ee->ee_ctls; i++) {
1653 switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1654 case AR5K_CTL_11A:
1655 case AR5K_CTL_TURBO:
1656 ctl_mode = AR5K_EEPROM_MODE_11A;
1657 break;
1658 default:
1659 ctl_mode = AR5K_EEPROM_MODE_11G;
1660 break;
1661 }
1662 if (ee->ee_ctl[i] == 0) {
1663 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
1664 offset += 8;
1665 else
1666 offset += 7;
1667 rep += AR5K_EEPROM_N_EDGES;
1668 continue;
1669 }
1670 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
1671 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1672 AR5K_EEPROM_READ(offset++, val);
1673 rep[j].freq = (val >> 8) & fmask;
1674 rep[j + 1].freq = val & fmask;
1675 }
1676 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1677 AR5K_EEPROM_READ(offset++, val);
1678 rep[j].edge = (val >> 8) & pmask;
1679 rep[j].flag = (val >> 14) & 1;
1680 rep[j + 1].edge = val & pmask;
1681 rep[j + 1].flag = (val >> 6) & 1;
1682 }
1683 } else {
1684 AR5K_EEPROM_READ(offset++, val);
1685 rep[0].freq = (val >> 9) & fmask;
1686 rep[1].freq = (val >> 2) & fmask;
1687 rep[2].freq = (val << 5) & fmask;
1688
1689 AR5K_EEPROM_READ(offset++, val);
1690 rep[2].freq |= (val >> 11) & 0x1f;
1691 rep[3].freq = (val >> 4) & fmask;
1692 rep[4].freq = (val << 3) & fmask;
1693
1694 AR5K_EEPROM_READ(offset++, val);
1695 rep[4].freq |= (val >> 13) & 0x7;
1696 rep[5].freq = (val >> 6) & fmask;
1697 rep[6].freq = (val << 1) & fmask;
1698
1699 AR5K_EEPROM_READ(offset++, val);
1700 rep[6].freq |= (val >> 15) & 0x1;
1701 rep[7].freq = (val >> 8) & fmask;
1702
1703 rep[0].edge = (val >> 2) & pmask;
1704 rep[1].edge = (val << 4) & pmask;
1705
1706 AR5K_EEPROM_READ(offset++, val);
1707 rep[1].edge |= (val >> 12) & 0xf;
1708 rep[2].edge = (val >> 6) & pmask;
1709 rep[3].edge = val & pmask;
1710
1711 AR5K_EEPROM_READ(offset++, val);
1712 rep[4].edge = (val >> 10) & pmask;
1713 rep[5].edge = (val >> 4) & pmask;
1714 rep[6].edge = (val << 2) & pmask;
1715
1716 AR5K_EEPROM_READ(offset++, val);
1717 rep[6].edge |= (val >> 14) & 0x3;
1718 rep[7].edge = (val >> 8) & pmask;
1719 }
1720 for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) {
1721 rep[j].freq = ath5k_eeprom_bin2freq(ee,
1722 rep[j].freq, ctl_mode);
1723 }
1724 rep += AR5K_EEPROM_N_EDGES;
1725 }
c6e387a2
NK		 1726
1727 return 0;
1728}
1729
cd417519
NK		 1730static int
1731ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
1732{
1733 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1734 u32 offset;
1735 u16 val;
1736 int ret = 0, i;
1737
1738 offset = AR5K_EEPROM_CTL(ee->ee_version) +
1739 AR5K_EEPROM_N_CTLS(ee->ee_version);
1740
1741 if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) {
1742 /* No spur info for 5GHz */
1743 ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR;
1744 /* 2 channels for 2GHz (2464/2420) */
1745 ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1;
1746 ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2;
1747 ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR;
1748 } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) {
1749 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1750 AR5K_EEPROM_READ(offset, val);
1751 ee->ee_spur_chans[i][0] = val;
1752 AR5K_EEPROM_READ(offset + AR5K_EEPROM_N_SPUR_CHANS,
1753 val);
1754 ee->ee_spur_chans[i][1] = val;
1755 offset++;
1756 }
1757 }
1758
1759 return ret;
1760}
1048643e 1761
9320b5c4
NK		 1762/*
1763 * Read the MAC address from eeprom
1764 */
1765int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
1766{
1767 u8 mac_d[ETH_ALEN] = {};
1768 u32 total, offset;
1769 u16 data;
1770 int octet, ret;
1771
1772 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
1773 if (ret)
1774 return ret;
1775
1776 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
1777 ret = ath5k_hw_eeprom_read(ah, offset, &data);
1778 if (ret)
1779 return ret;
1780
1781 total += data;
1782 mac_d[octet + 1] = data & 0xff;
1783 mac_d[octet] = data >> 8;
1784 octet += 2;
1785 }
1786
1787 if (!total || total == 3 * 0xffff)
1788 return -EINVAL;
1789
1790 memcpy(mac, mac_d, ETH_ALEN);
1791
1792 return 0;
1793}
1794
1795
1796/***********************\
1797* Init/Detach functions *
1798\***********************/
1799
1048643e 1800/*
cd417519 1801 * Initialize eeprom data structure
1048643e
FF		 1802 */
1803int
1804ath5k_eeprom_init(struct ath5k_hw *ah)
1805{
1806 int err;
1807
1808 err = ath5k_eeprom_init_header(ah);
1809 if (err < 0)
1810 return err;
1811
1812 err = ath5k_eeprom_init_modes(ah);
1813 if (err < 0)
1814 return err;
1815
1816 err = ath5k_eeprom_read_pcal_info(ah);
1817 if (err < 0)
1818 return err;
1819
1820 err = ath5k_eeprom_read_ctl_info(ah);
1821 if (err < 0)
1822 return err;
1823
cd417519
NK		 1824 err = ath5k_eeprom_read_spur_chans(ah);
1825 if (err < 0)
1826 return err;
1827
1048643e
FF		 1828 return 0;
1829}
e8f055f0 1830
9320b5c4
NK		 1831void
1832ath5k_eeprom_detach(struct ath5k_hw *ah)
c6e387a2 1833{
9320b5c4 1834 u8 mode;
8d6c39ef 1835
9320b5c4
NK		 1836 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
1837 ath5k_eeprom_free_pcal_info(ah, mode);
c6e387a2 1838}
Linux 6.x block layer and io_uring tree(s)