projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ath5k: Fix beaconing in mesh mode
[linux-block.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
6ccf15a1 51#include <linux/pci-aspm.h>
fa1c114f
JS		 52#include <linux/ethtool.h>
53#include <linux/uaccess.h>
5a0e3ad6 54#include <linux/slab.h>
b1ae1edf 55#include <linux/etherdevice.h>
fa1c114f
JS		 56
57#include <net/ieee80211_radiotap.h>
58
59#include <asm/unaligned.h>
60
61#include "base.h"
62#include "reg.h"
63#include "debug.h"
2111ac0d 64#include "ani.h"
62c58fb4 65#include "../debug.h"
fa1c114f 66
9ad9a26e 67static int modparam_nohwcrypt;
46802a4f 68module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 69MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 70
42639fcd 71static int modparam_all_channels;
46802a4f 72module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 73MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
74
fa1c114f
JS		 75/* Module info */
76MODULE_AUTHOR("Jiri Slaby");
77MODULE_AUTHOR("Nick Kossifidis");
78MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
79MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
80MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 81MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f 82
8a63facc
BC		 83static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
84static int ath5k_beacon_update(struct ieee80211_hw *hw,
85 struct ieee80211_vif *vif);
86static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 87
88/* Known PCI ids */
a3aa1884 89static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
97a81f5c
PR		 90 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
91 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
92 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
93 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
94 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
95 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
96 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
97 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
98 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
103 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
104 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
105 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
106 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
107 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 108 { 0 }
109};
110MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
111
112/* Known SREVs */
2c91108c 113static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 114 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
115 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
116 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
117 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
118 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
119 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
120 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
121 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
122 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
123 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
124 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
125 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
126 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
127 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
128 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
129 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
130 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
131 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
132 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 133 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
134 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 135 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 136 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
137 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
138 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 139 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 140 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
141 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 142 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
143 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
144 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
145 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
146 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
147 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 148 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
149 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
150};
151
2c91108c 152static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 153 { .bitrate = 10,
154 .hw_value = ATH5K_RATE_CODE_1M, },
155 { .bitrate = 20,
156 .hw_value = ATH5K_RATE_CODE_2M,
157 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
158 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
159 { .bitrate = 55,
160 .hw_value = ATH5K_RATE_CODE_5_5M,
161 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
162 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
163 { .bitrate = 110,
164 .hw_value = ATH5K_RATE_CODE_11M,
165 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
166 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
167 { .bitrate = 60,
168 .hw_value = ATH5K_RATE_CODE_6M,
169 .flags = 0 },
170 { .bitrate = 90,
171 .hw_value = ATH5K_RATE_CODE_9M,
172 .flags = 0 },
173 { .bitrate = 120,
174 .hw_value = ATH5K_RATE_CODE_12M,
175 .flags = 0 },
176 { .bitrate = 180,
177 .hw_value = ATH5K_RATE_CODE_18M,
178 .flags = 0 },
179 { .bitrate = 240,
180 .hw_value = ATH5K_RATE_CODE_24M,
181 .flags = 0 },
182 { .bitrate = 360,
183 .hw_value = ATH5K_RATE_CODE_36M,
184 .flags = 0 },
185 { .bitrate = 480,
186 .hw_value = ATH5K_RATE_CODE_48M,
187 .flags = 0 },
188 { .bitrate = 540,
189 .hw_value = ATH5K_RATE_CODE_54M,
190 .flags = 0 },
191 /* XR missing */
192};
193
9e4e43f2 194static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
fa1c114f
JS		 195 struct ath5k_buf *bf)
196{
197 BUG_ON(!bf);
198 if (!bf->skb)
199 return;
200 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
201 PCI_DMA_TODEVICE);
00482973 202 dev_kfree_skb_any(bf->skb);
fa1c114f 203 bf->skb = NULL;
39d63f2a
BR		 204 bf->skbaddr = 0;
205 bf->desc->ds_data = 0;
fa1c114f
JS		 206}
207
9e4e43f2 208static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
a6c8d375
FF		 209 struct ath5k_buf *bf)
210{
cc861f74
LR		 211 struct ath5k_hw *ah = sc->ah;
212 struct ath_common *common = ath5k_hw_common(ah);
213
a6c8d375
FF		 214 BUG_ON(!bf);
215 if (!bf->skb)
216 return;
cc861f74 217 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
a6c8d375
FF		 218 PCI_DMA_FROMDEVICE);
219 dev_kfree_skb_any(bf->skb);
220 bf->skb = NULL;
39d63f2a
BR		 221 bf->skbaddr = 0;
222 bf->desc->ds_data = 0;
a6c8d375
FF		 223}
224
225
fa1c114f
JS		 226static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
227{
228 u64 tsf = ath5k_hw_get_tsf64(ah);
229
230 if ((tsf & 0x7fff) < rstamp)
231 tsf -= 0x8000;
232
233 return (tsf & ~0x7fff) | rstamp;
234}
235
fa1c114f
JS		 236static const char *
237ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
238{
239 const char *name = "xxxxx";
240 unsigned int i;
241
242 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
243 if (srev_names[i].sr_type != type)
244 continue;
75d0edb8
NK		 245
246 if ((val & 0xf0) == srev_names[i].sr_val)
247 name = srev_names[i].sr_name;
248
249 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 250 name = srev_names[i].sr_name;
251 break;
252 }
253 }
254
255 return name;
256}
e5aa8474
LR		 257static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
258{
259 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
260 return ath5k_hw_reg_read(ah, reg_offset);
261}
262
263static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
264{
265 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
266 ath5k_hw_reg_write(ah, val, reg_offset);
267}
268
269static const struct ath_ops ath5k_common_ops = {
270 .read = ath5k_ioread32,
271 .write = ath5k_iowrite32,
272};
fa1c114f 273
8a63facc
BC		 274/***********************\
275* Driver Initialization *
276\***********************/
277
278static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 279{
8a63facc
BC		 280 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
281 struct ath5k_softc *sc = hw->priv;
282 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 283
8a63facc
BC		 284 return ath_reg_notifier_apply(wiphy, request, regulatory);
285}
6ccf15a1 286
8a63facc
BC		 287/********************\
288* Channel/mode setup *
289\********************/
fa1c114f 290
8a63facc
BC		 291/*
292 * Convert IEEE channel number to MHz frequency.
293 */
294static inline short
295ath5k_ieee2mhz(short chan)
296{
297 if (chan <= 14 || chan >= 27)
298 return ieee80211chan2mhz(chan);
299 else
300 return 2212 + chan * 20;
301}
fa1c114f 302
8a63facc
BC		 303/*
304 * Returns true for the channel numbers used without all_channels modparam.
305 */
306static bool ath5k_is_standard_channel(short chan)
307{
308 return ((chan <= 14) ||
309 /* UNII 1,2 */
310 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
311 /* midband */
312 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
313 /* UNII-3 */
314 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
315}
fa1c114f 316
8a63facc
BC		 317static unsigned int
318ath5k_copy_channels(struct ath5k_hw *ah,
319 struct ieee80211_channel *channels,
320 unsigned int mode,
321 unsigned int max)
322{
323 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f 324
8a63facc
BC		 325 if (!test_bit(mode, ah->ah_modes))
326 return 0;
fa1c114f 327
8a63facc
BC		 328 switch (mode) {
329 case AR5K_MODE_11A:
330 case AR5K_MODE_11A_TURBO:
331 /* 1..220, but 2GHz frequencies are filtered by check_channel */
332 size = 220 ;
333 chfreq = CHANNEL_5GHZ;
334 break;
335 case AR5K_MODE_11B:
336 case AR5K_MODE_11G:
337 case AR5K_MODE_11G_TURBO:
338 size = 26;
339 chfreq = CHANNEL_2GHZ;
340 break;
341 default:
342 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
343 return 0;
fa1c114f
JS		 344 }
345
8a63facc
BC		 346 for (i = 0, count = 0; i < size && max > 0; i++) {
347 ch = i + 1 ;
348 freq = ath5k_ieee2mhz(ch);
fa1c114f 349
8a63facc
BC		 350 /* Check if channel is supported by the chipset */
351 if (!ath5k_channel_ok(ah, freq, chfreq))
352 continue;
f59ac048 353
8a63facc
BC		 354 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
355 continue;
f59ac048 356
8a63facc
BC		 357 /* Write channel info and increment counter */
358 channels[count].center_freq = freq;
359 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
360 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
361 switch (mode) {
362 case AR5K_MODE_11A:
363 case AR5K_MODE_11G:
364 channels[count].hw_value = chfreq | CHANNEL_OFDM;
365 break;
366 case AR5K_MODE_11A_TURBO:
367 case AR5K_MODE_11G_TURBO:
368 channels[count].hw_value = chfreq |
369 CHANNEL_OFDM | CHANNEL_TURBO;
370 break;
371 case AR5K_MODE_11B:
372 channels[count].hw_value = CHANNEL_B;
373 }
fa1c114f 374
8a63facc
BC		 375 count++;
376 max--;
377 }
fa1c114f 378
8a63facc
BC		 379 return count;
380}
fa1c114f 381
8a63facc
BC		 382static void
383ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
384{
385 u8 i;
fa1c114f 386
8a63facc
BC		 387 for (i = 0; i < AR5K_MAX_RATES; i++)
388 sc->rate_idx[b->band][i] = -1;
fa1c114f 389
8a63facc
BC		 390 for (i = 0; i < b->n_bitrates; i++) {
391 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
392 if (b->bitrates[i].hw_value_short)
393 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 394 }
8a63facc 395}
fa1c114f 396
8a63facc
BC		 397static int
398ath5k_setup_bands(struct ieee80211_hw *hw)
399{
400 struct ath5k_softc *sc = hw->priv;
401 struct ath5k_hw *ah = sc->ah;
402 struct ieee80211_supported_band *sband;
403 int max_c, count_c = 0;
404 int i;
fa1c114f 405
8a63facc
BC		 406 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
407 max_c = ARRAY_SIZE(sc->channels);
db719718 408
8a63facc
BC		 409 /* 2GHz band */
410 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
411 sband->band = IEEE80211_BAND_2GHZ;
412 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 413
8a63facc
BC		 414 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
415 /* G mode */
416 memcpy(sband->bitrates, &ath5k_rates[0],
417 sizeof(struct ieee80211_rate) * 12);
418 sband->n_bitrates = 12;
2f7fe870 419
8a63facc
BC		 420 sband->channels = sc->channels;
421 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
422 AR5K_MODE_11G, max_c);
fa1c114f 423
8a63facc
BC		 424 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
425 count_c = sband->n_channels;
426 max_c -= count_c;
427 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
428 /* B mode */
429 memcpy(sband->bitrates, &ath5k_rates[0],
430 sizeof(struct ieee80211_rate) * 4);
431 sband->n_bitrates = 4;
fa1c114f 432
8a63facc
BC		 433 /* 5211 only supports B rates and uses 4bit rate codes
434 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
435 * fix them up here:
436 */
437 if (ah->ah_version == AR5K_AR5211) {
438 for (i = 0; i < 4; i++) {
439 sband->bitrates[i].hw_value =
440 sband->bitrates[i].hw_value & 0xF;
441 sband->bitrates[i].hw_value_short =
442 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 443 }
444 }
fa1c114f 445
8a63facc
BC		 446 sband->channels = sc->channels;
447 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
448 AR5K_MODE_11B, max_c);
fa1c114f 449
8a63facc
BC		 450 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
451 count_c = sband->n_channels;
452 max_c -= count_c;
453 }
454 ath5k_setup_rate_idx(sc, sband);
fa1c114f 455
8a63facc
BC		 456 /* 5GHz band, A mode */
457 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
458 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
459 sband->band = IEEE80211_BAND_5GHZ;
460 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 461
8a63facc
BC		 462 memcpy(sband->bitrates, &ath5k_rates[4],
463 sizeof(struct ieee80211_rate) * 8);
464 sband->n_bitrates = 8;
fa1c114f 465
8a63facc
BC		 466 sband->channels = &sc->channels[count_c];
467 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
468 AR5K_MODE_11A, max_c);
fa1c114f 469
8a63facc
BC		 470 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
471 }
472 ath5k_setup_rate_idx(sc, sband);
473
474 ath5k_debug_dump_bands(sc);
fa1c114f 475
fa1c114f
JS		 476 return 0;
477}
478
8a63facc
BC		 479/*
480 * Set/change channels. We always reset the chip.
481 * To accomplish this we must first cleanup any pending DMA,
482 * then restart stuff after a la ath5k_init.
483 *
484 * Called with sc->lock.
485 */
486static int
487ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
488{
489 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
490 "channel set, resetting (%u -> %u MHz)\n",
491 sc->curchan->center_freq, chan->center_freq);
492
8451d22d 493 /*
8a63facc
BC		 494 * To switch channels clear any pending DMA operations;
495 * wait long enough for the RX fifo to drain, reset the
496 * hardware at the new frequency, and then re-enable
497 * the relevant bits of the h/w.
8451d22d 498 */
8a63facc 499 return ath5k_reset(sc, chan);
fa1c114f 500}
fa1c114f 501
8a63facc
BC		 502static void
503ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
f769c36b 504{
8a63facc 505 sc->curmode = mode;
f769c36b 506
8a63facc
BC		 507 if (mode == AR5K_MODE_11A) {
508 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
509 } else {
510 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
511 }
f769c36b
BC		 512}
513
b1ae1edf
BG		 514struct ath_vif_iter_data {
515 const u8 *hw_macaddr;
516 u8 mask[ETH_ALEN];
517 u8 active_mac[ETH_ALEN]; /* first active MAC */
518 bool need_set_hw_addr;
519 bool found_active;
520 bool any_assoc;
62c58fb4 521 enum nl80211_iftype opmode;
b1ae1edf
BG		 522};
523
524static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
525{
526 struct ath_vif_iter_data *iter_data = data;
527 int i;
62c58fb4 528 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 529
530 if (iter_data->hw_macaddr)
531 for (i = 0; i < ETH_ALEN; i++)
532 iter_data->mask[i] &=
533 ~(iter_data->hw_macaddr[i] ^ mac[i]);
534
535 if (!iter_data->found_active) {
536 iter_data->found_active = true;
537 memcpy(iter_data->active_mac, mac, ETH_ALEN);
538 }
539
540 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
541 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
542 iter_data->need_set_hw_addr = false;
543
544 if (!iter_data->any_assoc) {
b1ae1edf
BG		 545 if (avf->assoc)
546 iter_data->any_assoc = true;
547 }
62c58fb4
BG		 548
549 /* Calculate combined mode - when APs are active, operate in AP mode.
550 * Otherwise use the mode of the new interface. This can currently
551 * only deal with combinations of APs and STAs. Only one ad-hoc
552 * interfaces is allowed above.
553 */
554 if (avf->opmode == NL80211_IFTYPE_AP)
555 iter_data->opmode = NL80211_IFTYPE_AP;
556 else
557 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
558 iter_data->opmode = avf->opmode;
b1ae1edf
BG		 559}
560
62c58fb4
BG		 561static void ath_do_set_opmode(struct ath5k_softc *sc)
562{
563 struct ath5k_hw *ah = sc->ah;
564 ath5k_hw_set_opmode(ah, sc->opmode);
565 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
908ebfb9 566 sc->opmode, ath_opmode_to_string(sc->opmode));
62c58fb4
BG		 567}
568
569void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
570 struct ieee80211_vif *vif)
b1ae1edf
BG		 571{
572 struct ath_common *common = ath5k_hw_common(sc->ah);
573 struct ath_vif_iter_data iter_data;
574
575 /*
576 * Use the hardware MAC address as reference, the hardware uses it
577 * together with the BSSID mask when matching addresses.
578 */
579 iter_data.hw_macaddr = common->macaddr;
580 memset(&iter_data.mask, 0xff, ETH_ALEN);
581 iter_data.found_active = false;
582 iter_data.need_set_hw_addr = true;
62c58fb4 583 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
b1ae1edf
BG		 584
585 if (vif)
586 ath_vif_iter(&iter_data, vif->addr, vif);
587
588 /* Get list of all active MAC addresses */
589 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
590 &iter_data);
591 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
592
62c58fb4
BG		 593 sc->opmode = iter_data.opmode;
594 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
595 /* Nothing active, default to station mode */
596 sc->opmode = NL80211_IFTYPE_STATION;
597
598 ath_do_set_opmode(sc);
599
b1ae1edf
BG		 600 if (iter_data.need_set_hw_addr && iter_data.found_active)
601 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
602
62c58fb4
BG		 603 if (ath5k_hw_hasbssidmask(sc->ah))
604 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
b1ae1edf
BG		 605}
606
8a63facc 607static void
b1ae1edf 608ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
fa1c114f 609{
fa1c114f 610 struct ath5k_hw *ah = sc->ah;
8a63facc 611 u32 rfilt;
fa1c114f 612
8a63facc
BC		 613 /* configure rx filter */
614 rfilt = sc->filter_flags;
615 ath5k_hw_set_rx_filter(ah, rfilt);
8a63facc 616 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
62c58fb4
BG		 617
618 ath5k_update_bssid_mask_and_opmode(sc, vif);
8a63facc 619}
fa1c114f 620
8a63facc
BC		 621static inline int
622ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
623{
624 int rix;
fa1c114f 625
8a63facc
BC		 626 /* return base rate on errors */
627 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
628 "hw_rix out of bounds: %x\n", hw_rix))
629 return 0;
630
631 rix = sc->rate_idx[sc->curband->band][hw_rix];
632 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
633 rix = 0;
634
635 return rix;
636}
637
638/***************\
639* Buffers setup *
640\***************/
641
642static
643struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
644{
645 struct ath_common *common = ath5k_hw_common(sc->ah);
646 struct sk_buff *skb;
fa1c114f
JS		 647
648 /*
8a63facc
BC		 649 * Allocate buffer with headroom_needed space for the
650 * fake physical layer header at the start.
fa1c114f 651 */
8a63facc
BC		 652 skb = ath_rxbuf_alloc(common,
653 common->rx_bufsize,
654 GFP_ATOMIC);
fa1c114f 655
8a63facc
BC		 656 if (!skb) {
657 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
658 common->rx_bufsize);
659 return NULL;
fa1c114f
JS		 660 }
661
8a63facc
BC		 662 *skb_addr = pci_map_single(sc->pdev,
663 skb->data, common->rx_bufsize,
664 PCI_DMA_FROMDEVICE);
665 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
666 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
667 dev_kfree_skb(skb);
668 return NULL;
0e149cf5 669 }
8a63facc
BC		 670 return skb;
671}
0e149cf5 672
8a63facc
BC		 673static int
674ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
675{
676 struct ath5k_hw *ah = sc->ah;
677 struct sk_buff *skb = bf->skb;
678 struct ath5k_desc *ds;
679 int ret;
fa1c114f 680
8a63facc
BC		 681 if (!skb) {
682 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
683 if (!skb)
684 return -ENOMEM;
685 bf->skb = skb;
f769c36b
BC		 686 }
687
8a63facc
BC		 688 /*
689 * Setup descriptors. For receive we always terminate
690 * the descriptor list with a self-linked entry so we'll
691 * not get overrun under high load (as can happen with a
692 * 5212 when ANI processing enables PHY error frames).
693 *
694 * To ensure the last descriptor is self-linked we create
695 * each descriptor as self-linked and add it to the end. As
696 * each additional descriptor is added the previous self-linked
697 * entry is "fixed" naturally. This should be safe even
698 * if DMA is happening. When processing RX interrupts we
699 * never remove/process the last, self-linked, entry on the
700 * descriptor list. This ensures the hardware always has
701 * someplace to write a new frame.
702 */
703 ds = bf->desc;
704 ds->ds_link = bf->daddr; /* link to self */
705 ds->ds_data = bf->skbaddr;
706 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 707 if (ret) {
8a63facc
BC		 708 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
709 return ret;
fa1c114f
JS		 710 }
711
8a63facc
BC		 712 if (sc->rxlink != NULL)
713 *sc->rxlink = bf->daddr;
714 sc->rxlink = &ds->ds_link;
fa1c114f 715 return 0;
fa1c114f
JS		 716}
717
8a63facc 718static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 719{
8a63facc
BC		 720 struct ieee80211_hdr *hdr;
721 enum ath5k_pkt_type htype;
722 __le16 fc;
fa1c114f 723
8a63facc
BC		 724 hdr = (struct ieee80211_hdr *)skb->data;
725 fc = hdr->frame_control;
fa1c114f 726
8a63facc
BC		 727 if (ieee80211_is_beacon(fc))
728 htype = AR5K_PKT_TYPE_BEACON;
729 else if (ieee80211_is_probe_resp(fc))
730 htype = AR5K_PKT_TYPE_PROBE_RESP;
731 else if (ieee80211_is_atim(fc))
732 htype = AR5K_PKT_TYPE_ATIM;
733 else if (ieee80211_is_pspoll(fc))
734 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 735 else
8a63facc 736 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 737
8a63facc 738 return htype;
42639fcd
BC		 739}
740
8a63facc
BC		 741static int
742ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
743 struct ath5k_txq *txq, int padsize)
fa1c114f 744{
8a63facc
BC		 745 struct ath5k_hw *ah = sc->ah;
746 struct ath5k_desc *ds = bf->desc;
747 struct sk_buff *skb = bf->skb;
748 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
749 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
750 struct ieee80211_rate *rate;
751 unsigned int mrr_rate[3], mrr_tries[3];
752 int i, ret;
753 u16 hw_rate;
754 u16 cts_rate = 0;
755 u16 duration = 0;
756 u8 rc_flags;
fa1c114f 757
8a63facc 758 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 759
8a63facc
BC		 760 /* XXX endianness */
761 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
762 PCI_DMA_TODEVICE);
fa1c114f 763
8a63facc 764 rate = ieee80211_get_tx_rate(sc->hw, info);
29ad2fac
JL		 765 if (!rate) {
766 ret = -EINVAL;
767 goto err_unmap;
768 }
fa1c114f 769
8a63facc
BC		 770 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
771 flags |= AR5K_TXDESC_NOACK;
fa1c114f 772
8a63facc
BC		 773 rc_flags = info->control.rates[0].flags;
774 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
775 rate->hw_value_short : rate->hw_value;
42639fcd 776
8a63facc
BC		 777 pktlen = skb->len;
778
779 /* FIXME: If we are in g mode and rate is a CCK rate
780 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
781 * from tx power (value is in dB units already) */
782 if (info->control.hw_key) {
783 keyidx = info->control.hw_key->hw_key_idx;
784 pktlen += info->control.hw_key->icv_len;
785 }
786 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
787 flags |= AR5K_TXDESC_RTSENA;
788 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
789 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
b1ae1edf 790 info->control.vif, pktlen, info));
8a63facc
BC		 791 }
792 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
793 flags |= AR5K_TXDESC_CTSENA;
794 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
795 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
b1ae1edf 796 info->control.vif, pktlen, info));
8a63facc
BC		 797 }
798 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
799 ieee80211_get_hdrlen_from_skb(skb), padsize,
800 get_hw_packet_type(skb),
801 (sc->power_level * 2),
802 hw_rate,
803 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
804 cts_rate, duration);
805 if (ret)
806 goto err_unmap;
807
808 memset(mrr_rate, 0, sizeof(mrr_rate));
809 memset(mrr_tries, 0, sizeof(mrr_tries));
810 for (i = 0; i < 3; i++) {
811 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
812 if (!rate)
400ec45a 813 break;
fa1c114f 814
8a63facc
BC		 815 mrr_rate[i] = rate->hw_value;
816 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 817 }
818
8a63facc
BC		 819 ath5k_hw_setup_mrr_tx_desc(ah, ds,
820 mrr_rate[0], mrr_tries[0],
821 mrr_rate[1], mrr_tries[1],
822 mrr_rate[2], mrr_tries[2]);
fa1c114f 823
8a63facc
BC		 824 ds->ds_link = 0;
825 ds->ds_data = bf->skbaddr;
63266a65 826
8a63facc
BC		 827 spin_lock_bh(&txq->lock);
828 list_add_tail(&bf->list, &txq->q);
925e0b06 829 txq->txq_len++;
8a63facc
BC		 830 if (txq->link == NULL) /* is this first packet? */
831 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
832 else /* no, so only link it */
833 *txq->link = bf->daddr;
63266a65 834
8a63facc
BC		 835 txq->link = &ds->ds_link;
836 ath5k_hw_start_tx_dma(ah, txq->qnum);
837 mmiowb();
838 spin_unlock_bh(&txq->lock);
839
840 return 0;
841err_unmap:
842 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
843 return ret;
63266a65
BR		 844}
845
8a63facc
BC		 846/*******************\
847* Descriptors setup *
848\*******************/
849
d8ee398d 850static int
8a63facc 851ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
fa1c114f 852{
8a63facc
BC		 853 struct ath5k_desc *ds;
854 struct ath5k_buf *bf;
855 dma_addr_t da;
856 unsigned int i;
857 int ret;
d8ee398d 858
8a63facc
BC		 859 /* allocate descriptors */
860 sc->desc_len = sizeof(struct ath5k_desc) *
861 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
862 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
863 if (sc->desc == NULL) {
864 ATH5K_ERR(sc, "can't allocate descriptors\n");
865 ret = -ENOMEM;
866 goto err;
867 }
868 ds = sc->desc;
869 da = sc->desc_daddr;
870 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
871 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 872
8a63facc
BC		 873 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
874 sizeof(struct ath5k_buf), GFP_KERNEL);
875 if (bf == NULL) {
876 ATH5K_ERR(sc, "can't allocate bufptr\n");
877 ret = -ENOMEM;
878 goto err_free;
879 }
880 sc->bufptr = bf;
fa1c114f 881
8a63facc
BC		 882 INIT_LIST_HEAD(&sc->rxbuf);
883 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
884 bf->desc = ds;
885 bf->daddr = da;
886 list_add_tail(&bf->list, &sc->rxbuf);
887 }
d8ee398d 888
8a63facc
BC		 889 INIT_LIST_HEAD(&sc->txbuf);
890 sc->txbuf_len = ATH_TXBUF;
891 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
892 da += sizeof(*ds)) {
893 bf->desc = ds;
894 bf->daddr = da;
895 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 896 }
897
b1ae1edf
BG		 898 /* beacon buffers */
899 INIT_LIST_HEAD(&sc->bcbuf);
900 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
901 bf->desc = ds;
902 bf->daddr = da;
903 list_add_tail(&bf->list, &sc->bcbuf);
904 }
fa1c114f 905
8a63facc
BC		 906 return 0;
907err_free:
908 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
909err:
910 sc->desc = NULL;
911 return ret;
912}
fa1c114f 913
8a63facc
BC		 914static void
915ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
916{
917 struct ath5k_buf *bf;
d8ee398d 918
8a63facc
BC		 919 list_for_each_entry(bf, &sc->txbuf, list)
920 ath5k_txbuf_free_skb(sc, bf);
921 list_for_each_entry(bf, &sc->rxbuf, list)
922 ath5k_rxbuf_free_skb(sc, bf);
b1ae1edf
BG		 923 list_for_each_entry(bf, &sc->bcbuf, list)
924 ath5k_txbuf_free_skb(sc, bf);
d8ee398d 925
8a63facc
BC		 926 /* Free memory associated with all descriptors */
927 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
928 sc->desc = NULL;
929 sc->desc_daddr = 0;
d8ee398d 930
8a63facc
BC		 931 kfree(sc->bufptr);
932 sc->bufptr = NULL;
fa1c114f
JS		 933}
934
8a63facc
BC		 935
936/**************\
937* Queues setup *
938\**************/
939
940static struct ath5k_txq *
941ath5k_txq_setup(struct ath5k_softc *sc,
942 int qtype, int subtype)
fa1c114f 943{
8a63facc
BC		 944 struct ath5k_hw *ah = sc->ah;
945 struct ath5k_txq *txq;
946 struct ath5k_txq_info qi = {
947 .tqi_subtype = subtype,
de8af455
BR		 948 /* XXX: default values not correct for B and XR channels,
949 * but who cares? */
950 .tqi_aifs = AR5K_TUNE_AIFS,
951 .tqi_cw_min = AR5K_TUNE_CWMIN,
952 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 953 };
954 int qnum;
d8ee398d 955
e30eb4ab 956 /*
8a63facc
BC		 957 * Enable interrupts only for EOL and DESC conditions.
958 * We mark tx descriptors to receive a DESC interrupt
959 * when a tx queue gets deep; otherwise we wait for the
960 * EOL to reap descriptors. Note that this is done to
961 * reduce interrupt load and this only defers reaping
962 * descriptors, never transmitting frames. Aside from
963 * reducing interrupts this also permits more concurrency.
964 * The only potential downside is if the tx queue backs
965 * up in which case the top half of the kernel may backup
966 * due to a lack of tx descriptors.
e30eb4ab 967 */
8a63facc
BC		 968 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
969 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
970 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
971 if (qnum < 0) {
972 /*
973 * NB: don't print a message, this happens
974 * normally on parts with too few tx queues
975 */
976 return ERR_PTR(qnum);
977 }
978 if (qnum >= ARRAY_SIZE(sc->txqs)) {
979 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
980 qnum, ARRAY_SIZE(sc->txqs));
981 ath5k_hw_release_tx_queue(ah, qnum);
982 return ERR_PTR(-EINVAL);
983 }
984 txq = &sc->txqs[qnum];
985 if (!txq->setup) {
986 txq->qnum = qnum;
987 txq->link = NULL;
988 INIT_LIST_HEAD(&txq->q);
989 spin_lock_init(&txq->lock);
990 txq->setup = true;
925e0b06 991 txq->txq_len = 0;
4edd761f 992 txq->txq_poll_mark = false;
923e5b3d 993 txq->txq_stuck = 0;
8a63facc
BC		 994 }
995 return &sc->txqs[qnum];
fa1c114f
JS		 996}
997
8a63facc
BC		 998static int
999ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 1000{
8a63facc 1001 struct ath5k_txq_info qi = {
de8af455
BR		 1002 /* XXX: default values not correct for B and XR channels,
1003 * but who cares? */
1004 .tqi_aifs = AR5K_TUNE_AIFS,
1005 .tqi_cw_min = AR5K_TUNE_CWMIN,
1006 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 1007 /* NB: for dynamic turbo, don't enable any other interrupts */
1008 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1009 };
d8ee398d 1010
8a63facc 1011 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 1012}
1013
8a63facc
BC		 1014static int
1015ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 1016{
1017 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1018 struct ath5k_txq_info qi;
1019 int ret;
fa1c114f 1020
8a63facc
BC		 1021 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1022 if (ret)
1023 goto err;
fa1c114f 1024
8a63facc
BC		 1025 if (sc->opmode == NL80211_IFTYPE_AP ||
1026 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1027 /*
1028 * Always burst out beacon and CAB traffic
1029 * (aifs = cwmin = cwmax = 0)
1030 */
1031 qi.tqi_aifs = 0;
1032 qi.tqi_cw_min = 0;
1033 qi.tqi_cw_max = 0;
1034 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1035 /*
1036 * Adhoc mode; backoff between 0 and (2 * cw_min).
1037 */
1038 qi.tqi_aifs = 0;
1039 qi.tqi_cw_min = 0;
de8af455 1040 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 1041 }
fa1c114f 1042
8a63facc
BC		 1043 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1044 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1045 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 1046
8a63facc
BC		 1047 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1048 if (ret) {
1049 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1050 "hardware queue!\n", __func__);
1051 goto err;
1052 }
1053 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1054 if (ret)
1055 goto err;
b7266047 1056
8a63facc
BC		 1057 /* reconfigure cabq with ready time to 80% of beacon_interval */
1058 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1059 if (ret)
1060 goto err;
b7266047 1061
8a63facc
BC		 1062 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1063 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1064 if (ret)
1065 goto err;
b7266047 1066
8a63facc
BC		 1067 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1068err:
1069 return ret;
d8ee398d
LR		 1070}
1071
8a63facc
BC		 1072static void
1073ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1074{
1075 struct ath5k_buf *bf, *bf0;
b6ea0356
BC		 1076
1077 /*
8a63facc
BC		 1078 * NB: this assumes output has been stopped and
1079 * we do not need to block ath5k_tx_tasklet
b6ea0356 1080 */
8a63facc
BC		 1081 spin_lock_bh(&txq->lock);
1082 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1083 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 1084
8a63facc 1085 ath5k_txbuf_free_skb(sc, bf);
b6ea0356 1086
8a63facc
BC		 1087 spin_lock_bh(&sc->txbuflock);
1088 list_move_tail(&bf->list, &sc->txbuf);
1089 sc->txbuf_len++;
925e0b06 1090 txq->txq_len--;
8a63facc 1091 spin_unlock_bh(&sc->txbuflock);
b6ea0356 1092 }
8a63facc 1093 txq->link = NULL;
4edd761f 1094 txq->txq_poll_mark = false;
8a63facc 1095 spin_unlock_bh(&txq->lock);
b6ea0356
BC		 1096}
1097
8a63facc
BC		 1098/*
1099 * Drain the transmit queues and reclaim resources.
1100 */
1101static void
1102ath5k_txq_cleanup(struct ath5k_softc *sc)
fa1c114f
JS		 1103{
1104 struct ath5k_hw *ah = sc->ah;
8a63facc 1105 unsigned int i;
fa1c114f 1106
8a63facc
BC		 1107 /* XXX return value */
1108 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1109 /* don't touch the hardware if marked invalid */
1110 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1111 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1112 ath5k_hw_get_txdp(ah, sc->bhalq));
1113 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1114 if (sc->txqs[i].setup) {
1115 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1116 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1117 "link %p\n",
1118 sc->txqs[i].qnum,
1119 ath5k_hw_get_txdp(ah,
1120 sc->txqs[i].qnum),
1121 sc->txqs[i].link);
1122 }
0452d4a5 1123 }
fa1c114f 1124
8a63facc
BC		 1125 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1126 if (sc->txqs[i].setup)
1127 ath5k_txq_drainq(sc, &sc->txqs[i]);
fa1c114f
JS		 1128}
1129
8a63facc
BC		 1130static void
1131ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1132{
8a63facc
BC		 1133 struct ath5k_txq *txq = sc->txqs;
1134 unsigned int i;
2ac2927a 1135
8a63facc
BC		 1136 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1137 if (txq->setup) {
1138 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1139 txq->setup = false;
1140 }
1141}
2ac2927a 1142
2ac2927a 1143
8a63facc
BC		 1144/*************\
1145* RX Handling *
1146\*************/
2ac2927a 1147
8a63facc
BC		 1148/*
1149 * Enable the receive h/w following a reset.
1150 */
fa1c114f 1151static int
8a63facc 1152ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1153{
1154 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1155 struct ath_common *common = ath5k_hw_common(ah);
1156 struct ath5k_buf *bf;
1157 int ret;
fa1c114f 1158
8a63facc 1159 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1160
8a63facc
BC		 1161 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1162 common->cachelsz, common->rx_bufsize);
2f7fe870 1163
8a63facc
BC		 1164 spin_lock_bh(&sc->rxbuflock);
1165 sc->rxlink = NULL;
1166 list_for_each_entry(bf, &sc->rxbuf, list) {
1167 ret = ath5k_rxbuf_setup(sc, bf);
1168 if (ret != 0) {
1169 spin_unlock_bh(&sc->rxbuflock);
1170 goto err;
1171 }
2f7fe870 1172 }
8a63facc
BC		 1173 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1174 ath5k_hw_set_rxdp(ah, bf->daddr);
1175 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1176
8a63facc 1177 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
b1ae1edf 1178 ath5k_mode_setup(sc, NULL); /* set filters, etc. */
8a63facc 1179 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1180
1181 return 0;
8a63facc 1182err:
fa1c114f
JS		 1183 return ret;
1184}
1185
8a63facc
BC		 1186/*
1187 * Disable the receive h/w in preparation for a reset.
1188 */
1189static void
1190ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1191{
8a63facc 1192 struct ath5k_hw *ah = sc->ah;
fa1c114f 1193
8a63facc
BC		 1194 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1195 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1196 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f 1197
8a63facc
BC		 1198 ath5k_debug_printrxbuffs(sc, ah);
1199}
fa1c114f 1200
8a63facc
BC		 1201static unsigned int
1202ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1203 struct ath5k_rx_status *rs)
1204{
1205 struct ath5k_hw *ah = sc->ah;
1206 struct ath_common *common = ath5k_hw_common(ah);
1207 struct ieee80211_hdr *hdr = (void *)skb->data;
1208 unsigned int keyix, hlen;
fa1c114f 1209
8a63facc
BC		 1210 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1211 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1212 return RX_FLAG_DECRYPTED;
fa1c114f 1213
8a63facc
BC		 1214 /* Apparently when a default key is used to decrypt the packet
1215 the hw does not set the index used to decrypt. In such cases
1216 get the index from the packet. */
1217 hlen = ieee80211_hdrlen(hdr->frame_control);
1218 if (ieee80211_has_protected(hdr->frame_control) &&
1219 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1220 skb->len >= hlen + 4) {
1221 keyix = skb->data[hlen + 3] >> 6;
1222
1223 if (test_bit(keyix, common->keymap))
1224 return RX_FLAG_DECRYPTED;
1225 }
fa1c114f
JS		 1226
1227 return 0;
fa1c114f
JS		 1228}
1229
8a63facc 1230
fa1c114f 1231static void
8a63facc
BC		 1232ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1233 struct ieee80211_rx_status *rxs)
fa1c114f 1234{
8a63facc
BC		 1235 struct ath_common *common = ath5k_hw_common(sc->ah);
1236 u64 tsf, bc_tstamp;
1237 u32 hw_tu;
1238 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1239
8a63facc
BC		 1240 if (ieee80211_is_beacon(mgmt->frame_control) &&
1241 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1242 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1243 /*
1244 * Received an IBSS beacon with the same BSSID. Hardware *must*
1245 * have updated the local TSF. We have to work around various
1246 * hardware bugs, though...
1247 */
1248 tsf = ath5k_hw_get_tsf64(sc->ah);
1249 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1250 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1251
8a63facc
BC		 1252 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1253 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1254 (unsigned long long)bc_tstamp,
1255 (unsigned long long)rxs->mactime,
1256 (unsigned long long)(rxs->mactime - bc_tstamp),
1257 (unsigned long long)tsf);
fa1c114f 1258
8a63facc
BC		 1259 /*
1260 * Sometimes the HW will give us a wrong tstamp in the rx
1261 * status, causing the timestamp extension to go wrong.
1262 * (This seems to happen especially with beacon frames bigger
1263 * than 78 byte (incl. FCS))
1264 * But we know that the receive timestamp must be later than the
1265 * timestamp of the beacon since HW must have synced to that.
1266 *
1267 * NOTE: here we assume mactime to be after the frame was
1268 * received, not like mac80211 which defines it at the start.
1269 */
1270 if (bc_tstamp > rxs->mactime) {
1271 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1272 "fixing mactime from %llx to %llx\n",
1273 (unsigned long long)rxs->mactime,
1274 (unsigned long long)tsf);
1275 rxs->mactime = tsf;
1276 }
fa1c114f 1277
8a63facc
BC		 1278 /*
1279 * Local TSF might have moved higher than our beacon timers,
1280 * in that case we have to update them to continue sending
1281 * beacons. This also takes care of synchronizing beacon sending
1282 * times with other stations.
1283 */
1284 if (hw_tu >= sc->nexttbtt)
1285 ath5k_beacon_update_timers(sc, bc_tstamp);
7f896126
BR		 1286
1287 /* Check if the beacon timers are still correct, because a TSF
1288 * update might have created a window between them - for a
1289 * longer description see the comment of this function: */
1290 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1291 ath5k_beacon_update_timers(sc, bc_tstamp);
1292 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1293 "fixed beacon timers after beacon receive\n");
1294 }
8a63facc
BC		 1295 }
1296}
fa1c114f 1297
8a63facc
BC		 1298static void
1299ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1300{
1301 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1302 struct ath5k_hw *ah = sc->ah;
1303 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1304
8a63facc
BC		 1305 /* only beacons from our BSSID */
1306 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1307 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1308 return;
fa1c114f 1309
8a63facc
BC		 1310 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1311 rssi);
fa1c114f 1312
8a63facc
BC		 1313 /* in IBSS mode we should keep RSSI statistics per neighbour */
1314 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1315}
fa1c114f 1316
8a63facc
BC		 1317/*
1318 * Compute padding position. skb must contain an IEEE 802.11 frame
1319 */
1320static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1321{
8a63facc
BC		 1322 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1323 __le16 frame_control = hdr->frame_control;
1324 int padpos = 24;
fa1c114f 1325
8a63facc
BC		 1326 if (ieee80211_has_a4(frame_control)) {
1327 padpos += ETH_ALEN;
fa1c114f 1328 }
8a63facc
BC		 1329 if (ieee80211_is_data_qos(frame_control)) {
1330 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1331 }
8a63facc
BC		 1332
1333 return padpos;
fa1c114f
JS		 1334}
1335
8a63facc
BC		 1336/*
1337 * This function expects an 802.11 frame and returns the number of
1338 * bytes added, or -1 if we don't have enough header room.
1339 */
1340static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1341{
8a63facc
BC		 1342 int padpos = ath5k_common_padpos(skb);
1343 int padsize = padpos & 3;
fa1c114f 1344
8a63facc 1345 if (padsize && skb->len>padpos) {
fa1c114f 1346
8a63facc
BC		 1347 if (skb_headroom(skb) < padsize)
1348 return -1;
fa1c114f 1349
8a63facc
BC		 1350 skb_push(skb, padsize);
1351 memmove(skb->data, skb->data+padsize, padpos);
1352 return padsize;
1353 }
a951ae21 1354
8a63facc
BC		 1355 return 0;
1356}
fa1c114f 1357
8a63facc
BC		 1358/*
1359 * The MAC header is padded to have 32-bit boundary if the
1360 * packet payload is non-zero. The general calculation for
1361 * padsize would take into account odd header lengths:
1362 * padsize = 4 - (hdrlen & 3); however, since only
1363 * even-length headers are used, padding can only be 0 or 2
1364 * bytes and we can optimize this a bit. We must not try to
1365 * remove padding from short control frames that do not have a
1366 * payload.
1367 *
1368 * This function expects an 802.11 frame and returns the number of
1369 * bytes removed.
1370 */
1371static int ath5k_remove_padding(struct sk_buff *skb)
1372{
1373 int padpos = ath5k_common_padpos(skb);
1374 int padsize = padpos & 3;
6d91e1d8 1375
8a63facc
BC		 1376 if (padsize && skb->len>=padpos+padsize) {
1377 memmove(skb->data + padsize, skb->data, padpos);
1378 skb_pull(skb, padsize);
1379 return padsize;
fa1c114f 1380 }
a951ae21 1381
8a63facc 1382 return 0;
fa1c114f
JS		 1383}
1384
1385static void
8a63facc
BC		 1386ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1387 struct ath5k_rx_status *rs)
fa1c114f 1388{
8a63facc
BC		 1389 struct ieee80211_rx_status *rxs;
1390
1391 ath5k_remove_padding(skb);
1392
1393 rxs = IEEE80211_SKB_RXCB(skb);
1394
1395 rxs->flag = 0;
1396 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1397 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1398
1399 /*
8a63facc
BC		 1400 * always extend the mac timestamp, since this information is
1401 * also needed for proper IBSS merging.
1402 *
1403 * XXX: it might be too late to do it here, since rs_tstamp is
1404 * 15bit only. that means TSF extension has to be done within
1405 * 32768usec (about 32ms). it might be necessary to move this to
1406 * the interrupt handler, like it is done in madwifi.
1407 *
1408 * Unfortunately we don't know when the hardware takes the rx
1409 * timestamp (beginning of phy frame, data frame, end of rx?).
1410 * The only thing we know is that it is hardware specific...
1411 * On AR5213 it seems the rx timestamp is at the end of the
1412 * frame, but i'm not sure.
1413 *
1414 * NOTE: mac80211 defines mactime at the beginning of the first
1415 * data symbol. Since we don't have any time references it's
1416 * impossible to comply to that. This affects IBSS merge only
1417 * right now, so it's not too bad...
fa1c114f 1418 */
8a63facc
BC		 1419 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1420 rxs->flag |= RX_FLAG_TSFT;
fa1c114f 1421
8a63facc
BC		 1422 rxs->freq = sc->curchan->center_freq;
1423 rxs->band = sc->curband->band;
fa1c114f 1424
8a63facc 1425 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1426
8a63facc 1427 rxs->antenna = rs->rs_antenna;
fa1c114f 1428
8a63facc
BC		 1429 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1430 sc->stats.antenna_rx[rs->rs_antenna]++;
1431 else
1432 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1433
8a63facc
BC		 1434 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1435 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1436
8a63facc
BC		 1437 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1438 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1439 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1440
8a63facc 1441 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
fa1c114f 1442
8a63facc 1443 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1444
8a63facc
BC		 1445 /* check beacons in IBSS mode */
1446 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1447 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1448
8a63facc
BC		 1449 ieee80211_rx(sc->hw, skb);
1450}
fa1c114f 1451
8a63facc
BC		 1452/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1453 *
1454 * Check if we want to further process this frame or not. Also update
1455 * statistics. Return true if we want this frame, false if not.
fa1c114f 1456 */
8a63facc
BC		 1457static bool
1458ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1459{
8a63facc 1460 sc->stats.rx_all_count++;
b72acddb 1461 sc->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1462
8a63facc
BC		 1463 if (unlikely(rs->rs_status)) {
1464 if (rs->rs_status & AR5K_RXERR_CRC)
1465 sc->stats.rxerr_crc++;
1466 if (rs->rs_status & AR5K_RXERR_FIFO)
1467 sc->stats.rxerr_fifo++;
1468 if (rs->rs_status & AR5K_RXERR_PHY) {
1469 sc->stats.rxerr_phy++;
1470 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1471 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1472 return false;
1473 }
1474 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1475 /*
1476 * Decrypt error. If the error occurred
1477 * because there was no hardware key, then
1478 * let the frame through so the upper layers
1479 * can process it. This is necessary for 5210
1480 * parts which have no way to setup a ``clear''
1481 * key cache entry.
1482 *
1483 * XXX do key cache faulting
1484 */
1485 sc->stats.rxerr_decrypt++;
1486 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1487 !(rs->rs_status & AR5K_RXERR_CRC))
1488 return true;
1489 }
1490 if (rs->rs_status & AR5K_RXERR_MIC) {
1491 sc->stats.rxerr_mic++;
1492 return true;
fa1c114f 1493 }
fa1c114f 1494
8a63facc
BC		 1495 /* reject any frames with non-crypto errors */
1496 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1497 return false;
1498 }
fa1c114f 1499
8a63facc
BC		 1500 if (unlikely(rs->rs_more)) {
1501 sc->stats.rxerr_jumbo++;
1502 return false;
1503 }
1504 return true;
fa1c114f
JS		 1505}
1506
fa1c114f 1507static void
8a63facc 1508ath5k_tasklet_rx(unsigned long data)
fa1c114f 1509{
8a63facc
BC		 1510 struct ath5k_rx_status rs = {};
1511 struct sk_buff *skb, *next_skb;
1512 dma_addr_t next_skb_addr;
1513 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1514 struct ath5k_hw *ah = sc->ah;
1515 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1516 struct ath5k_buf *bf;
1517 struct ath5k_desc *ds;
1518 int ret;
fa1c114f 1519
8a63facc
BC		 1520 spin_lock(&sc->rxbuflock);
1521 if (list_empty(&sc->rxbuf)) {
1522 ATH5K_WARN(sc, "empty rx buf pool\n");
1523 goto unlock;
1524 }
1525 do {
1526 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1527 BUG_ON(bf->skb == NULL);
1528 skb = bf->skb;
1529 ds = bf->desc;
fa1c114f 1530
8a63facc
BC		 1531 /* bail if HW is still using self-linked descriptor */
1532 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1533 break;
fa1c114f 1534
8a63facc
BC		 1535 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1536 if (unlikely(ret == -EINPROGRESS))
1537 break;
1538 else if (unlikely(ret)) {
1539 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1540 sc->stats.rxerr_proc++;
1541 break;
1542 }
fa1c114f 1543
8a63facc
BC		 1544 if (ath5k_receive_frame_ok(sc, &rs)) {
1545 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1546
8a63facc
BC		 1547 /*
1548 * If we can't replace bf->skb with a new skb under
1549 * memory pressure, just skip this packet
1550 */
1551 if (!next_skb)
1552 goto next;
036cd1ec 1553
8a63facc
BC		 1554 pci_unmap_single(sc->pdev, bf->skbaddr,
1555 common->rx_bufsize,
1556 PCI_DMA_FROMDEVICE);
036cd1ec 1557
8a63facc 1558 skb_put(skb, rs.rs_datalen);
6ba81c2c 1559
8a63facc 1560 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1561
8a63facc
BC		 1562 bf->skb = next_skb;
1563 bf->skbaddr = next_skb_addr;
036cd1ec 1564 }
8a63facc
BC		 1565next:
1566 list_move_tail(&bf->list, &sc->rxbuf);
1567 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1568unlock:
1569 spin_unlock(&sc->rxbuflock);
036cd1ec
BR		 1570}
1571
b4ea449d 1572
8a63facc
BC		 1573/*************\
1574* TX Handling *
1575\*************/
b4ea449d 1576
8a63facc
BC		 1577static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1578 struct ath5k_txq *txq)
1579{
1580 struct ath5k_softc *sc = hw->priv;
1581 struct ath5k_buf *bf;
1582 unsigned long flags;
1583 int padsize;
b4ea449d 1584
8a63facc 1585 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
b4ea449d 1586
8a63facc
BC		 1587 /*
1588 * The hardware expects the header padded to 4 byte boundaries.
1589 * If this is not the case, we add the padding after the header.
1590 */
1591 padsize = ath5k_add_padding(skb);
1592 if (padsize < 0) {
1593 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1594 " headroom to pad");
1595 goto drop_packet;
1596 }
8127fbdc 1597
925e0b06
BR		 1598 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1599 ieee80211_stop_queue(hw, txq->qnum);
1600
8a63facc
BC		 1601 spin_lock_irqsave(&sc->txbuflock, flags);
1602 if (list_empty(&sc->txbuf)) {
1603 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1604 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1605 ieee80211_stop_queues(hw);
8a63facc 1606 goto drop_packet;
8127fbdc 1607 }
8a63facc
BC		 1608 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1609 list_del(&bf->list);
1610 sc->txbuf_len--;
1611 if (list_empty(&sc->txbuf))
1612 ieee80211_stop_queues(hw);
1613 spin_unlock_irqrestore(&sc->txbuflock, flags);
1614
1615 bf->skb = skb;
1616
1617 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1618 bf->skb = NULL;
1619 spin_lock_irqsave(&sc->txbuflock, flags);
1620 list_add_tail(&bf->list, &sc->txbuf);
1621 sc->txbuf_len++;
1622 spin_unlock_irqrestore(&sc->txbuflock, flags);
1623 goto drop_packet;
8127fbdc 1624 }
8a63facc 1625 return NETDEV_TX_OK;
8127fbdc 1626
8a63facc
BC		 1627drop_packet:
1628 dev_kfree_skb_any(skb);
1629 return NETDEV_TX_OK;
8127fbdc
BP		 1630}
1631
1440401e
BR		 1632static void
1633ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1634 struct ath5k_tx_status *ts)
1635{
1636 struct ieee80211_tx_info *info;
1637 int i;
1638
1639 sc->stats.tx_all_count++;
b72acddb 1640 sc->stats.tx_bytes_count += skb->len;
1440401e
BR		 1641 info = IEEE80211_SKB_CB(skb);
1642
1643 ieee80211_tx_info_clear_status(info);
1644 for (i = 0; i < 4; i++) {
1645 struct ieee80211_tx_rate *r =
1646 &info->status.rates[i];
1647
1648 if (ts->ts_rate[i]) {
1649 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1650 r->count = ts->ts_retry[i];
1651 } else {
1652 r->idx = -1;
1653 r->count = 0;
1654 }
1655 }
1656
1657 /* count the successful attempt as well */
1658 info->status.rates[ts->ts_final_idx].count++;
1659
1660 if (unlikely(ts->ts_status)) {
1661 sc->stats.ack_fail++;
1662 if (ts->ts_status & AR5K_TXERR_FILT) {
1663 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1664 sc->stats.txerr_filt++;
1665 }
1666 if (ts->ts_status & AR5K_TXERR_XRETRY)
1667 sc->stats.txerr_retry++;
1668 if (ts->ts_status & AR5K_TXERR_FIFO)
1669 sc->stats.txerr_fifo++;
1670 } else {
1671 info->flags |= IEEE80211_TX_STAT_ACK;
1672 info->status.ack_signal = ts->ts_rssi;
1673 }
1674
1675 /*
1676 * Remove MAC header padding before giving the frame
1677 * back to mac80211.
1678 */
1679 ath5k_remove_padding(skb);
1680
1681 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1682 sc->stats.antenna_tx[ts->ts_antenna]++;
1683 else
1684 sc->stats.antenna_tx[0]++; /* invalid */
1685
1686 ieee80211_tx_status(sc->hw, skb);
1687}
8a63facc
BC		 1688
1689static void
1690ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1691{
8a63facc
BC		 1692 struct ath5k_tx_status ts = {};
1693 struct ath5k_buf *bf, *bf0;
1694 struct ath5k_desc *ds;
1695 struct sk_buff *skb;
1440401e 1696 int ret;
8127fbdc 1697
8a63facc
BC		 1698 spin_lock(&txq->lock);
1699 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1700
1701 txq->txq_poll_mark = false;
1702
1703 /* skb might already have been processed last time. */
1704 if (bf->skb != NULL) {
1705 ds = bf->desc;
1706
1707 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1708 if (unlikely(ret == -EINPROGRESS))
1709 break;
1710 else if (unlikely(ret)) {
1711 ATH5K_ERR(sc,
1712 "error %d while processing "
1713 "queue %u\n", ret, txq->qnum);
1714 break;
1715 }
1716
1717 skb = bf->skb;
1718 bf->skb = NULL;
1719 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1720 PCI_DMA_TODEVICE);
1721 ath5k_tx_frame_completed(sc, skb, &ts);
1722 }
8127fbdc 1723
8a63facc
BC		 1724 /*
1725 * It's possible that the hardware can say the buffer is
1726 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1727 * host memory and moved on.
1728 * Always keep the last descriptor to avoid HW races...
8a63facc 1729 */
23413296
BR		 1730 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1731 spin_lock(&sc->txbuflock);
1732 list_move_tail(&bf->list, &sc->txbuf);
1733 sc->txbuf_len++;
1734 txq->txq_len--;
1735 spin_unlock(&sc->txbuflock);
8a63facc 1736 }
fa1c114f 1737 }
fa1c114f 1738 spin_unlock(&txq->lock);
4198a8d0 1739 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
925e0b06 1740 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1741}
1742
1743static void
1744ath5k_tasklet_tx(unsigned long data)
1745{
8784d2ee 1746 int i;
fa1c114f
JS		 1747 struct ath5k_softc *sc = (void *)data;
1748
8784d2ee
BC		 1749 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1750 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1751 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 1752}
1753
1754
fa1c114f
JS		 1755/*****************\
1756* Beacon handling *
1757\*****************/
1758
1759/*
1760 * Setup the beacon frame for transmit.
1761 */
1762static int
e039fa4a 1763ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1764{
1765 struct sk_buff *skb = bf->skb;
a888d52d 1766 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1767 struct ath5k_hw *ah = sc->ah;
1768 struct ath5k_desc *ds;
2bed03eb
NK		 1769 int ret = 0;
1770 u8 antenna;
fa1c114f 1771 u32 flags;
8127fbdc 1772 const int padsize = 0;
fa1c114f
JS		 1773
1774 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1775 PCI_DMA_TODEVICE);
1776 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1777 "skbaddr %llx\n", skb, skb->data, skb->len,
1778 (unsigned long long)bf->skbaddr);
8d8bb39b 1779 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1780 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1781 return -EIO;
1782 }
1783
1784 ds = bf->desc;
2bed03eb 1785 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1786
1787 flags = AR5K_TXDESC_NOACK;
05c914fe 1788 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1789 ds->ds_link = bf->daddr; /* self-linked */
1790 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1791 } else
fa1c114f 1792 ds->ds_link = 0;
2bed03eb
NK		 1793
1794 /*
1795 * If we use multiple antennas on AP and use
1796 * the Sectored AP scenario, switch antenna every
1797 * 4 beacons to make sure everybody hears our AP.
1798 * When a client tries to associate, hw will keep
1799 * track of the tx antenna to be used for this client
1800 * automaticaly, based on ACKed packets.
1801 *
1802 * Note: AP still listens and transmits RTS on the
1803 * default antenna which is supposed to be an omni.
1804 *
1805 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1806 * multiple antennas (1 omni -- the default -- and 14
1807 * sectors), so if we choose to actually support this
1808 * mode, we need to allow the user to set how many antennas
1809 * we have and tweak the code below to send beacons
1810 * on all of them.
2bed03eb
NK		 1811 */
1812 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1813 antenna = sc->bsent & 4 ? 2 : 1;
1814
fa1c114f 1815
8f655dde
NK		 1816 /* FIXME: If we are in g mode and rate is a CCK rate
1817 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1818 * from tx power (value is in dB units already) */
fa1c114f 1819 ds->ds_data = bf->skbaddr;
281c56dd 1820 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1821 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1822 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1823 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1824 1, AR5K_TXKEYIX_INVALID,
400ec45a 1825 antenna, flags, 0, 0);
fa1c114f
JS		 1826 if (ret)
1827 goto err_unmap;
1828
1829 return 0;
1830err_unmap:
1831 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1832 return ret;
1833}
1834
8a63facc
BC		 1835/*
1836 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1837 * this is called only once at config_bss time, for AP we do it every
1838 * SWBA interrupt so that the TIM will reflect buffered frames.
1839 *
1840 * Called with the beacon lock.
1841 */
1842static int
1843ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1844{
1845 int ret;
1846 struct ath5k_softc *sc = hw->priv;
b1ae1edf 1847 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1848 struct sk_buff *skb;
1849
1850 if (WARN_ON(!vif)) {
1851 ret = -EINVAL;
1852 goto out;
1853 }
1854
1855 skb = ieee80211_beacon_get(hw, vif);
1856
1857 if (!skb) {
1858 ret = -ENOMEM;
1859 goto out;
1860 }
1861
1862 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1863
b1ae1edf
BG		 1864 ath5k_txbuf_free_skb(sc, avf->bbuf);
1865 avf->bbuf->skb = skb;
1866 ret = ath5k_beacon_setup(sc, avf->bbuf);
8a63facc 1867 if (ret)
b1ae1edf 1868 avf->bbuf->skb = NULL;
8a63facc
BC		 1869out:
1870 return ret;
1871}
1872
fa1c114f
JS		 1873/*
1874 * Transmit a beacon frame at SWBA. Dynamic updates to the
1875 * frame contents are done as needed and the slot time is
1876 * also adjusted based on current state.
1877 *
5faaff74
BC		 1878 * This is called from software irq context (beacontq tasklets)
1879 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1880 */
1881static void
1882ath5k_beacon_send(struct ath5k_softc *sc)
1883{
fa1c114f 1884 struct ath5k_hw *ah = sc->ah;
b1ae1edf
BG		 1885 struct ieee80211_vif *vif;
1886 struct ath5k_vif *avf;
1887 struct ath5k_buf *bf;
cec8db23 1888 struct sk_buff *skb;
fa1c114f 1889
be9b7259 1890 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1891
fa1c114f
JS		 1892 /*
1893 * Check if the previous beacon has gone out. If
a180a130 1894 * not, don't don't try to post another: skip this
fa1c114f
JS		 1895 * period and wait for the next. Missed beacons
1896 * indicate a problem and should not occur. If we
1897 * miss too many consecutive beacons reset the device.
1898 */
1899 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1900 sc->bmisscount++;
be9b7259 1901 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1902 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1903 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1904 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1905 "stuck beacon time (%u missed)\n",
1906 sc->bmisscount);
8d67a031
BR		 1907 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1908 "stuck beacon, resetting\n");
5faaff74 1909 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1910 }
1911 return;
1912 }
1913 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1914 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1915 "resume beacon xmit after %u misses\n",
1916 sc->bmisscount);
1917 sc->bmisscount = 0;
1918 }
1919
b1ae1edf
BG		 1920 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1921 u64 tsf = ath5k_hw_get_tsf64(ah);
1922 u32 tsftu = TSF_TO_TU(tsf);
1923 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1924 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1925 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1926 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1927 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1928 } else /* only one interface */
1929 vif = sc->bslot[0];
1930
1931 if (!vif)
1932 return;
1933
1934 avf = (void *)vif->drv_priv;
1935 bf = avf->bbuf;
1936 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1937 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1938 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1939 return;
1940 }
1941
fa1c114f
JS		 1942 /*
1943 * Stop any current dma and put the new frame on the queue.
1944 * This should never fail since we check above that no frames
1945 * are still pending on the queue.
1946 */
1947 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 1948 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1949 /* NB: hw still stops DMA, so proceed */
1950 }
fa1c114f 1951
d82b577b
JC		 1952 /* refresh the beacon for AP or MESH mode */
1953 if (sc->opmode == NL80211_IFTYPE_AP ||
1954 sc->opmode == NL80211_IFTYPE_MESH_POINT)
b1ae1edf 1955 ath5k_beacon_update(sc->hw, vif);
1071db86 1956
c6e387a2
NK		 1957 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1958 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1959 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1960 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1961
b1ae1edf 1962 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1963 while (skb) {
1964 ath5k_tx_queue(sc->hw, skb, sc->cabq);
b1ae1edf 1965 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1966 }
1967
fa1c114f
JS		 1968 sc->bsent++;
1969}
1970
9804b98d
BR		 1971/**
1972 * ath5k_beacon_update_timers - update beacon timers
1973 *
1974 * @sc: struct ath5k_softc pointer we are operating on
1975 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1976 * beacon timer update based on the current HW TSF.
1977 *
1978 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1979 * of a received beacon or the current local hardware TSF and write it to the
1980 * beacon timer registers.
1981 *
1982 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1983 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1984 * when we otherwise know we have to update the timers, but we keep it in this
1985 * function to have it all together in one place.
1986 */
fa1c114f 1987static void
9804b98d 1988ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1989{
1990 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1991 u32 nexttbtt, intval, hw_tu, bc_tu;
1992 u64 hw_tsf;
fa1c114f
JS		 1993
1994 intval = sc->bintval & AR5K_BEACON_PERIOD;
b1ae1edf
BG		 1995 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1996 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1997 if (intval < 15)
1998 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1999 intval);
2000 }
fa1c114f
JS		 2001 if (WARN_ON(!intval))
2002 return;
2003
9804b98d
BR		 2004 /* beacon TSF converted to TU */
2005 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2006
9804b98d
BR		 2007 /* current TSF converted to TU */
2008 hw_tsf = ath5k_hw_get_tsf64(ah);
2009 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2010
11f21df3
BR		 2011#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
2012 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
2013 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
2014 * configuration we need to make sure it is bigger than that. */
2015
9804b98d
BR		 2016 if (bc_tsf == -1) {
2017 /*
2018 * no beacons received, called internally.
2019 * just need to refresh timers based on HW TSF.
2020 */
2021 nexttbtt = roundup(hw_tu + FUDGE, intval);
2022 } else if (bc_tsf == 0) {
2023 /*
2024 * no beacon received, probably called by ath5k_reset_tsf().
2025 * reset TSF to start with 0.
2026 */
2027 nexttbtt = intval;
2028 intval |= AR5K_BEACON_RESET_TSF;
2029 } else if (bc_tsf > hw_tsf) {
2030 /*
2031 * beacon received, SW merge happend but HW TSF not yet updated.
2032 * not possible to reconfigure timers yet, but next time we
2033 * receive a beacon with the same BSSID, the hardware will
2034 * automatically update the TSF and then we need to reconfigure
2035 * the timers.
2036 */
2037 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2038 "need to wait for HW TSF sync\n");
2039 return;
2040 } else {
2041 /*
2042 * most important case for beacon synchronization between STA.
2043 *
2044 * beacon received and HW TSF has been already updated by HW.
2045 * update next TBTT based on the TSF of the beacon, but make
2046 * sure it is ahead of our local TSF timer.
2047 */
2048 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2049 }
2050#undef FUDGE
fa1c114f 2051
036cd1ec
BR		 2052 sc->nexttbtt = nexttbtt;
2053
fa1c114f 2054 intval |= AR5K_BEACON_ENA;
fa1c114f 2055 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2056
2057 /*
2058 * debugging output last in order to preserve the time critical aspect
2059 * of this function
2060 */
2061 if (bc_tsf == -1)
2062 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2063 "reconfigured timers based on HW TSF\n");
2064 else if (bc_tsf == 0)
2065 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2066 "reset HW TSF and timers\n");
2067 else
2068 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2069 "updated timers based on beacon TSF\n");
2070
2071 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2072 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2073 (unsigned long long) bc_tsf,
2074 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2075 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2076 intval & AR5K_BEACON_PERIOD,
2077 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2078 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2079}
2080
036cd1ec
BR		 2081/**
2082 * ath5k_beacon_config - Configure the beacon queues and interrupts
2083 *
2084 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2085 *
036cd1ec 2086 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2087 * interrupts to detect TSF updates only.
fa1c114f
JS		 2088 */
2089static void
2090ath5k_beacon_config(struct ath5k_softc *sc)
2091{
2092 struct ath5k_hw *ah = sc->ah;
b5f03956 2093 unsigned long flags;
fa1c114f 2094
21800491 2095 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2096 sc->bmisscount = 0;
dc1968e7 2097 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2098
21800491 2099 if (sc->enable_beacon) {
fa1c114f 2100 /*
036cd1ec
BR		 2101 * In IBSS mode we use a self-linked tx descriptor and let the
2102 * hardware send the beacons automatically. We have to load it
fa1c114f 2103 * only once here.
036cd1ec 2104 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2105 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2106 */
2107 ath5k_beaconq_config(sc);
fa1c114f 2108
036cd1ec
BR		 2109 sc->imask |= AR5K_INT_SWBA;
2110
da966bca 2111 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2112 if (ath5k_hw_hasveol(ah))
da966bca 2113 ath5k_beacon_send(sc);
da966bca
JS		 2114 } else
2115 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 2116 } else {
2117 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 2118 }
fa1c114f 2119
c6e387a2 2120 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2121 mmiowb();
2122 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2123}
2124
428cbd4f
NK		 2125static void ath5k_tasklet_beacon(unsigned long data)
2126{
2127 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2128
2129 /*
2130 * Software beacon alert--time to send a beacon.
2131 *
2132 * In IBSS mode we use this interrupt just to
2133 * keep track of the next TBTT (target beacon
2134 * transmission time) in order to detect wether
2135 * automatic TSF updates happened.
2136 */
2137 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2138 /* XXX: only if VEOL suppported */
2139 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2140 sc->nexttbtt += sc->bintval;
2141 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2142 "SWBA nexttbtt: %x hw_tu: %x "
2143 "TSF: %llx\n",
2144 sc->nexttbtt,
2145 TSF_TO_TU(tsf),
2146 (unsigned long long) tsf);
2147 } else {
2148 spin_lock(&sc->block);
2149 ath5k_beacon_send(sc);
2150 spin_unlock(&sc->block);
2151 }
2152}
2153
fa1c114f
JS		 2154
2155/********************\
2156* Interrupt handling *
2157\********************/
2158
6a8a3f6b
BR		 2159static void
2160ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2161{
2111ac0d
BR		 2162 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2163 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2164 /* run ANI only when full calibration is not active */
2165 ah->ah_cal_next_ani = jiffies +
2166 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2167 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2168
2169 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2170 ah->ah_cal_next_full = jiffies +
2171 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2172 tasklet_schedule(&ah->ah_sc->calib);
2173 }
2174 /* we could use SWI to generate enough interrupts to meet our
2175 * calibration interval requirements, if necessary:
2176 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2177}
2178
fa1c114f
JS		 2179static irqreturn_t
2180ath5k_intr(int irq, void *dev_id)
2181{
2182 struct ath5k_softc *sc = dev_id;
2183 struct ath5k_hw *ah = sc->ah;
2184 enum ath5k_int status;
2185 unsigned int counter = 1000;
2186
2187 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2188 !ath5k_hw_is_intr_pending(ah)))
2189 return IRQ_NONE;
2190
2191 do {
fa1c114f
JS		 2192 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2193 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2194 status, sc->imask);
fa1c114f
JS		 2195 if (unlikely(status & AR5K_INT_FATAL)) {
2196 /*
2197 * Fatal errors are unrecoverable.
2198 * Typically these are caused by DMA errors.
2199 */
8d67a031
BR		 2200 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2201 "fatal int, resetting\n");
5faaff74 2202 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2203 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2204 /*
2205 * Receive buffers are full. Either the bus is busy or
2206 * the CPU is not fast enough to process all received
2207 * frames.
2208 * Older chipsets need a reset to come out of this
2209 * condition, but we treat it as RX for newer chips.
2210 * We don't know exactly which versions need a reset -
2211 * this guess is copied from the HAL.
2212 */
2213 sc->stats.rxorn_intr++;
8d67a031
BR		 2214 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2215 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2216 "rx overrun, resetting\n");
5faaff74 2217 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2218 }
87d77c4e
BR		 2219 else
2220 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2221 } else {
2222 if (status & AR5K_INT_SWBA) {
56d2ac76 2223 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2224 }
2225 if (status & AR5K_INT_RXEOL) {
2226 /*
2227 * NB: the hardware should re-read the link when
2228 * RXE bit is written, but it doesn't work at
2229 * least on older hardware revs.
2230 */
b3f194e5 2231 sc->stats.rxeol_intr++;
fa1c114f
JS		 2232 }
2233 if (status & AR5K_INT_TXURN) {
2234 /* bump tx trigger level */
2235 ath5k_hw_update_tx_triglevel(ah, true);
2236 }
4c674c60 2237 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2238 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2239 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2240 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2241 tasklet_schedule(&sc->txtq);
2242 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2243 /* TODO */
fa1c114f
JS		 2244 }
2245 if (status & AR5K_INT_MIB) {
2111ac0d 2246 sc->stats.mib_intr++;
495391d7 2247 ath5k_hw_update_mib_counters(ah);
2111ac0d 2248 ath5k_ani_mib_intr(ah);
fa1c114f 2249 }
e6a3b616 2250 if (status & AR5K_INT_GPIO)
e6a3b616 2251 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2252
fa1c114f 2253 }
2516baa6 2254 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2255
2256 if (unlikely(!counter))
2257 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2258
6a8a3f6b 2259 ath5k_intr_calibration_poll(ah);
6e220662 2260
fa1c114f
JS		 2261 return IRQ_HANDLED;
2262}
2263
fa1c114f
JS		 2264/*
2265 * Periodically recalibrate the PHY to account
2266 * for temperature/environment changes.
2267 */
2268static void
6e220662 2269ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2270{
2271 struct ath5k_softc *sc = (void *)data;
2272 struct ath5k_hw *ah = sc->ah;
2273
6e220662 2274 /* Only full calibration for now */
e65e1d77 2275 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2276
fa1c114f 2277 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2278 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2279 sc->curchan->hw_value);
fa1c114f 2280
6f3b414a 2281 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2282 /*
2283 * Rfgain is out of bounds, reset the chip
2284 * to load new gain values.
2285 */
2286 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2287 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2288 }
2289 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2290 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2291 ieee80211_frequency_to_channel(
2292 sc->curchan->center_freq));
fa1c114f 2293
0e8e02dd 2294 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2295 * doesn't.
2296 * TODO: We should stop TX here, so that it doesn't interfere.
2297 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2298 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2299 ah->ah_cal_next_nf = jiffies +
2300 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2301 ath5k_hw_update_noise_floor(ah);
afe86286 2302 }
6e220662 2303
e65e1d77 2304 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2305}
2306
2307
2111ac0d
BR		 2308static void
2309ath5k_tasklet_ani(unsigned long data)
2310{
2311 struct ath5k_softc *sc = (void *)data;
2312 struct ath5k_hw *ah = sc->ah;
2313
2314 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2315 ath5k_ani_calibration(ah);
2316 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2317}
2318
2319
4edd761f
BR		 2320static void
2321ath5k_tx_complete_poll_work(struct work_struct *work)
2322{
2323 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2324 tx_complete_work.work);
2325 struct ath5k_txq *txq;
2326 int i;
2327 bool needreset = false;
2328
2329 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2330 if (sc->txqs[i].setup) {
2331 txq = &sc->txqs[i];
2332 spin_lock_bh(&txq->lock);
23413296 2333 if (txq->txq_len > 1) {
4edd761f
BR		 2334 if (txq->txq_poll_mark) {
2335 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2336 "TX queue stuck %d\n",
2337 txq->qnum);
2338 needreset = true;
923e5b3d 2339 txq->txq_stuck++;
4edd761f
BR		 2340 spin_unlock_bh(&txq->lock);
2341 break;
2342 } else {
2343 txq->txq_poll_mark = true;
2344 }
2345 }
2346 spin_unlock_bh(&txq->lock);
2347 }
2348 }
2349
2350 if (needreset) {
2351 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2352 "TX queues stuck, resetting\n");
2353 ath5k_reset(sc, sc->curchan);
2354 }
2355
2356 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2357 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2358}
2359
2360
8a63facc
BC		 2361/*************************\
2362* Initialization routines *
2363\*************************/
fa1c114f
JS		 2364
2365static int
8a63facc 2366ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2367{
8a63facc 2368 struct ath5k_hw *ah = sc->ah;
cec8db23 2369
8a63facc
BC		 2370 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2371 test_bit(ATH_STAT_INVALID, sc->status));
2372
2373 /*
2374 * Shutdown the hardware and driver:
2375 * stop output from above
2376 * disable interrupts
2377 * turn off timers
2378 * turn off the radio
2379 * clear transmit machinery
2380 * clear receive machinery
2381 * drain and release tx queues
2382 * reclaim beacon resources
2383 * power down hardware
2384 *
2385 * Note that some of this work is not possible if the
2386 * hardware is gone (invalid).
2387 */
2388 ieee80211_stop_queues(sc->hw);
2389
2390 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2391 ath5k_led_off(sc);
2392 ath5k_hw_set_imr(ah, 0);
2393 synchronize_irq(sc->pdev->irq);
2394 }
2395 ath5k_txq_cleanup(sc);
2396 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2397 ath5k_rx_stop(sc);
2398 ath5k_hw_phy_disable(ah);
2399 }
2400
2401 return 0;
cec8db23
BC		 2402}
2403
8a63facc
BC		 2404static int
2405ath5k_init(struct ath5k_softc *sc)
fa1c114f 2406{
8a63facc
BC		 2407 struct ath5k_hw *ah = sc->ah;
2408 struct ath_common *common = ath5k_hw_common(ah);
2409 int ret, i;
fa1c114f 2410
8a63facc
BC		 2411 mutex_lock(&sc->lock);
2412
2413 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2414
fa1c114f 2415 /*
8a63facc
BC		 2416 * Stop anything previously setup. This is safe
2417 * no matter this is the first time through or not.
fa1c114f 2418 */
8a63facc 2419 ath5k_stop_locked(sc);
fa1c114f 2420
8a63facc
BC		 2421 /*
2422 * The basic interface to setting the hardware in a good
2423 * state is ``reset''. On return the hardware is known to
2424 * be powered up and with interrupts disabled. This must
2425 * be followed by initialization of the appropriate bits
2426 * and then setup of the interrupt mask.
2427 */
2428 sc->curchan = sc->hw->conf.channel;
2429 sc->curband = &sc->sbands[sc->curchan->band];
2430 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2431 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2432 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2433
8a63facc
BC		 2434 ret = ath5k_reset(sc, NULL);
2435 if (ret)
2436 goto done;
fa1c114f 2437
8a63facc
BC		 2438 ath5k_rfkill_hw_start(ah);
2439
2440 /*
2441 * Reset the key cache since some parts do not reset the
2442 * contents on initial power up or resume from suspend.
2443 */
2444 for (i = 0; i < common->keymax; i++)
2445 ath_hw_keyreset(common, (u16) i);
2446
2447 ath5k_hw_set_ack_bitrate_high(ah, true);
b1ae1edf
BG		 2448
2449 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2450 sc->bslot[i] = NULL;
2451
8a63facc
BC		 2452 ret = 0;
2453done:
2454 mmiowb();
2455 mutex_unlock(&sc->lock);
4edd761f
BR		 2456
2457 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2458 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2459
8a63facc
BC		 2460 return ret;
2461}
2462
2463static void stop_tasklets(struct ath5k_softc *sc)
2464{
2465 tasklet_kill(&sc->rxtq);
2466 tasklet_kill(&sc->txtq);
2467 tasklet_kill(&sc->calib);
2468 tasklet_kill(&sc->beacontq);
2469 tasklet_kill(&sc->ani_tasklet);
2470}
2471
2472/*
2473 * Stop the device, grabbing the top-level lock to protect
2474 * against concurrent entry through ath5k_init (which can happen
2475 * if another thread does a system call and the thread doing the
2476 * stop is preempted).
2477 */
2478static int
2479ath5k_stop_hw(struct ath5k_softc *sc)
2480{
2481 int ret;
2482
2483 mutex_lock(&sc->lock);
2484 ret = ath5k_stop_locked(sc);
2485 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2486 /*
2487 * Don't set the card in full sleep mode!
2488 *
2489 * a) When the device is in this state it must be carefully
2490 * woken up or references to registers in the PCI clock
2491 * domain may freeze the bus (and system). This varies
2492 * by chip and is mostly an issue with newer parts
2493 * (madwifi sources mentioned srev >= 0x78) that go to
2494 * sleep more quickly.
2495 *
2496 * b) On older chips full sleep results a weird behaviour
2497 * during wakeup. I tested various cards with srev < 0x78
2498 * and they don't wake up after module reload, a second
2499 * module reload is needed to bring the card up again.
2500 *
2501 * Until we figure out what's going on don't enable
2502 * full chip reset on any chip (this is what Legacy HAL
2503 * and Sam's HAL do anyway). Instead Perform a full reset
2504 * on the device (same as initial state after attach) and
2505 * leave it idle (keep MAC/BB on warm reset) */
2506 ret = ath5k_hw_on_hold(sc->ah);
2507
2508 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2509 "putting device to sleep\n");
fa1c114f
JS		 2510 }
2511
8a63facc
BC		 2512 mmiowb();
2513 mutex_unlock(&sc->lock);
2514
2515 stop_tasklets(sc);
2516
4edd761f
BR		 2517 cancel_delayed_work_sync(&sc->tx_complete_work);
2518
8a63facc
BC		 2519 ath5k_rfkill_hw_stop(sc->ah);
2520
2521 return ret;
fa1c114f
JS		 2522}
2523
209d889b
BC		 2524/*
2525 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2526 * and change to the given channel.
5faaff74
BC		 2527 *
2528 * This should be called with sc->lock.
209d889b 2529 */
fa1c114f 2530static int
209d889b 2531ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2532{
fa1c114f
JS		 2533 struct ath5k_hw *ah = sc->ah;
2534 int ret;
2535
2536 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2537
450464de
BC		 2538 ath5k_hw_set_imr(ah, 0);
2539 synchronize_irq(sc->pdev->irq);
2540 stop_tasklets(sc);
2541
209d889b 2542 if (chan) {
d7dc1003
JS		 2543 ath5k_txq_cleanup(sc);
2544 ath5k_rx_stop(sc);
209d889b
BC		 2545
2546 sc->curchan = chan;
2547 sc->curband = &sc->sbands[chan->band];
d7dc1003 2548 }
3355443a 2549 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2550 if (ret) {
fa1c114f
JS		 2551 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2552 goto err;
2553 }
d7dc1003 2554
fa1c114f 2555 ret = ath5k_rx_start(sc);
d7dc1003 2556 if (ret) {
fa1c114f
JS		 2557 ATH5K_ERR(sc, "can't start recv logic\n");
2558 goto err;
2559 }
d7dc1003 2560
2111ac0d
BR		 2561 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2562
ac559526
BR		 2563 ah->ah_cal_next_full = jiffies;
2564 ah->ah_cal_next_ani = jiffies;
afe86286
BR		 2565 ah->ah_cal_next_nf = jiffies;
2566
fa1c114f 2567 /*
d7dc1003
JS		 2568 * Change channels and update the h/w rate map if we're switching;
2569 * e.g. 11a to 11b/g.
2570 *
2571 * We may be doing a reset in response to an ioctl that changes the
2572 * channel so update any state that might change as a result.
fa1c114f
JS		 2573 *
2574 * XXX needed?
2575 */
2576/* ath5k_chan_change(sc, c); */
fa1c114f 2577
d7dc1003
JS		 2578 ath5k_beacon_config(sc);
2579 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2580
397f385b
BR		 2581 ieee80211_wake_queues(sc->hw);
2582
fa1c114f
JS		 2583 return 0;
2584err:
2585 return ret;
2586}
2587
5faaff74
BC		 2588static void ath5k_reset_work(struct work_struct *work)
2589{
2590 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2591 reset_work);
2592
2593 mutex_lock(&sc->lock);
2594 ath5k_reset(sc, sc->curchan);
2595 mutex_unlock(&sc->lock);
2596}
2597
8a63facc
BC		 2598static int
2599ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
fa1c114f
JS		 2600{
2601 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2602 struct ath5k_hw *ah = sc->ah;
2603 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2604 struct ath5k_txq *txq;
8a63facc 2605 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2606 int ret;
2607
8a63facc 2608 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
fa1c114f 2609
8a63facc
BC		 2610 /*
2611 * Check if the MAC has multi-rate retry support.
2612 * We do this by trying to setup a fake extended
2613 * descriptor. MACs that don't have support will
2614 * return false w/o doing anything. MACs that do
2615 * support it will return true w/o doing anything.
2616 */
2617 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2618
8a63facc
BC		 2619 if (ret < 0)
2620 goto err;
2621 if (ret > 0)
2622 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2623
8a63facc
BC		 2624 /*
2625 * Collect the channel list. The 802.11 layer
2626 * is resposible for filtering this list based
2627 * on settings like the phy mode and regulatory
2628 * domain restrictions.
2629 */
2630 ret = ath5k_setup_bands(hw);
2631 if (ret) {
2632 ATH5K_ERR(sc, "can't get channels\n");
2633 goto err;
2634 }
67d2e2df 2635
8a63facc
BC		 2636 /* NB: setup here so ath5k_rate_update is happy */
2637 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2638 ath5k_setcurmode(sc, AR5K_MODE_11A);
2639 else
2640 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f 2641
8a63facc
BC		 2642 /*
2643 * Allocate tx+rx descriptors and populate the lists.
2644 */
2645 ret = ath5k_desc_alloc(sc, pdev);
2646 if (ret) {
2647 ATH5K_ERR(sc, "can't allocate descriptors\n");
2648 goto err;
2649 }
fa1c114f 2650
8a63facc
BC		 2651 /*
2652 * Allocate hardware transmit queues: one queue for
2653 * beacon frames and one data queue for each QoS
2654 * priority. Note that hw functions handle resetting
2655 * these queues at the needed time.
2656 */
2657 ret = ath5k_beaconq_setup(ah);
2658 if (ret < 0) {
2659 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2660 goto err_desc;
2661 }
2662 sc->bhalq = ret;
2663 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2664 if (IS_ERR(sc->cabq)) {
2665 ATH5K_ERR(sc, "can't setup cab queue\n");
2666 ret = PTR_ERR(sc->cabq);
2667 goto err_bhal;
2668 }
fa1c114f 2669
925e0b06
BR		 2670 /* This order matches mac80211's queue priority, so we can
2671 * directly use the mac80211 queue number without any mapping */
2672 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2673 if (IS_ERR(txq)) {
2674 ATH5K_ERR(sc, "can't setup xmit queue\n");
2675 ret = PTR_ERR(txq);
2676 goto err_queues;
2677 }
2678 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2679 if (IS_ERR(txq)) {
8a63facc 2680 ATH5K_ERR(sc, "can't setup xmit queue\n");
925e0b06 2681 ret = PTR_ERR(txq);
8a63facc
BC		 2682 goto err_queues;
2683 }
925e0b06
BR		 2684 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2685 if (IS_ERR(txq)) {
2686 ATH5K_ERR(sc, "can't setup xmit queue\n");
2687 ret = PTR_ERR(txq);
2688 goto err_queues;
2689 }
2690 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2691 if (IS_ERR(txq)) {
2692 ATH5K_ERR(sc, "can't setup xmit queue\n");
2693 ret = PTR_ERR(txq);
2694 goto err_queues;
2695 }
2696 hw->queues = 4;
fa1c114f 2697
8a63facc
BC		 2698 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2699 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2700 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2701 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2702 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2703
8a63facc 2704 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2705 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2706
8a63facc
BC		 2707 ret = ath5k_eeprom_read_mac(ah, mac);
2708 if (ret) {
2709 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
2710 sc->pdev->device);
2711 goto err_queues;
e30eb4ab 2712 }
2bed03eb 2713
8a63facc 2714 SET_IEEE80211_PERM_ADDR(hw, mac);
b1ae1edf 2715 memcpy(&sc->lladdr, mac, ETH_ALEN);
8a63facc 2716 /* All MAC address bits matter for ACKs */
62c58fb4 2717 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2718
2719 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2720 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2721 if (ret) {
2722 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2723 goto err_queues;
2724 }
2725
2726 ret = ieee80211_register_hw(hw);
2727 if (ret) {
2728 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2729 goto err_queues;
2730 }
2731
2732 if (!ath_is_world_regd(regulatory))
2733 regulatory_hint(hw->wiphy, regulatory->alpha2);
2734
2735 ath5k_init_leds(sc);
2736
2737 ath5k_sysfs_register(sc);
2738
2739 return 0;
2740err_queues:
2741 ath5k_txq_release(sc);
2742err_bhal:
2743 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2744err_desc:
2745 ath5k_desc_free(sc, pdev);
2746err:
2747 return ret;
2748}
2749
2750static void
2751ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
2752{
2753 struct ath5k_softc *sc = hw->priv;
2754
2755 /*
2756 * NB: the order of these is important:
2757 * o call the 802.11 layer before detaching ath5k_hw to
2758 * ensure callbacks into the driver to delete global
2759 * key cache entries can be handled
2760 * o reclaim the tx queue data structures after calling
2761 * the 802.11 layer as we'll get called back to reclaim
2762 * node state and potentially want to use them
2763 * o to cleanup the tx queues the hal is called, so detach
2764 * it last
2765 * XXX: ??? detach ath5k_hw ???
2766 * Other than that, it's straightforward...
2767 */
2768 ieee80211_unregister_hw(hw);
2769 ath5k_desc_free(sc, pdev);
2770 ath5k_txq_release(sc);
2771 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2772 ath5k_unregister_leds(sc);
2773
2774 ath5k_sysfs_unregister(sc);
2775 /*
2776 * NB: can't reclaim these until after ieee80211_ifdetach
2777 * returns because we'll get called back to reclaim node
2778 * state and potentially want to use them.
2779 */
2780}
2781
2782/********************\
2783* Mac80211 functions *
2784\********************/
2785
2786static int
2787ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2788{
2789 struct ath5k_softc *sc = hw->priv;
925e0b06
BR		 2790 u16 qnum = skb_get_queue_mapping(skb);
2791
2792 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
2793 dev_kfree_skb_any(skb);
2794 return 0;
2795 }
8a63facc 2796
925e0b06 2797 return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
8a63facc
BC		 2798}
2799
2800static int ath5k_start(struct ieee80211_hw *hw)
2801{
2802 return ath5k_init(hw->priv);
2803}
2804
2805static void ath5k_stop(struct ieee80211_hw *hw)
2806{
2807 ath5k_stop_hw(hw->priv);
2808}
2809
2810static int ath5k_add_interface(struct ieee80211_hw *hw,
2811 struct ieee80211_vif *vif)
2812{
2813 struct ath5k_softc *sc = hw->priv;
2814 int ret;
b1ae1edf 2815 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 2816
2817 mutex_lock(&sc->lock);
b1ae1edf
BG		 2818
2819 if ((vif->type == NL80211_IFTYPE_AP ||
2820 vif->type == NL80211_IFTYPE_ADHOC)
2821 && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) {
2822 ret = -ELNRNG;
8a63facc
BC		 2823 goto end;
2824 }
2825
b1ae1edf
BG		 2826 /* Don't allow other interfaces if one ad-hoc is configured.
2827 * TODO: Fix the problems with ad-hoc and multiple other interfaces.
2828 * We would need to operate the HW in ad-hoc mode to allow TSF updates
2829 * for the IBSS, but this breaks with additional AP or STA interfaces
2830 * at the moment. */
2831 if (sc->num_adhoc_vifs ||
2832 (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
2833 ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n");
2834 ret = -ELNRNG;
2835 goto end;
2836 }
8a63facc
BC		 2837
2838 switch (vif->type) {
2839 case NL80211_IFTYPE_AP:
2840 case NL80211_IFTYPE_STATION:
2841 case NL80211_IFTYPE_ADHOC:
2842 case NL80211_IFTYPE_MESH_POINT:
b1ae1edf 2843 avf->opmode = vif->type;
8a63facc
BC		 2844 break;
2845 default:
2846 ret = -EOPNOTSUPP;
2847 goto end;
2848 }
2849
b1ae1edf
BG		 2850 sc->nvifs++;
2851 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
8a63facc 2852
b1ae1edf
BG		 2853 /* Assign the vap/adhoc to a beacon xmit slot. */
2854 if ((avf->opmode == NL80211_IFTYPE_AP) ||
d82b577b
JC		 2855 (avf->opmode == NL80211_IFTYPE_ADHOC) ||
2856 (avf->opmode == NL80211_IFTYPE_MESH_POINT)) {
b1ae1edf
BG		 2857 int slot;
2858
2859 WARN_ON(list_empty(&sc->bcbuf));
2860 avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf,
2861 list);
2862 list_del(&avf->bbuf->list);
2863
2864 avf->bslot = 0;
2865 for (slot = 0; slot < ATH_BCBUF; slot++) {
2866 if (!sc->bslot[slot]) {
2867 avf->bslot = slot;
2868 break;
2869 }
2870 }
2871 BUG_ON(sc->bslot[avf->bslot] != NULL);
2872 sc->bslot[avf->bslot] = vif;
2873 if (avf->opmode == NL80211_IFTYPE_AP)
2874 sc->num_ap_vifs++;
2875 else
2876 sc->num_adhoc_vifs++;
2877 }
2878
b1ae1edf
BG		 2879 /* Any MAC address is fine, all others are included through the
2880 * filter.
2881 */
2882 memcpy(&sc->lladdr, vif->addr, ETH_ALEN);
8a63facc 2883 ath5k_hw_set_lladdr(sc->ah, vif->addr);
b1ae1edf
BG		 2884
2885 memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
2886
2887 ath5k_mode_setup(sc, vif);
8a63facc
BC		 2888
2889 ret = 0;
2890end:
2891 mutex_unlock(&sc->lock);
2892 return ret;
2893}
2894
2895static void
2896ath5k_remove_interface(struct ieee80211_hw *hw,
2897 struct ieee80211_vif *vif)
2898{
2899 struct ath5k_softc *sc = hw->priv;
b1ae1edf
BG		 2900 struct ath5k_vif *avf = (void *)vif->drv_priv;
2901 unsigned int i;
8a63facc
BC		 2902
2903 mutex_lock(&sc->lock);
b1ae1edf
BG		 2904 sc->nvifs--;
2905
2906 if (avf->bbuf) {
2907 ath5k_txbuf_free_skb(sc, avf->bbuf);
2908 list_add_tail(&avf->bbuf->list, &sc->bcbuf);
2909 for (i = 0; i < ATH_BCBUF; i++) {
2910 if (sc->bslot[i] == vif) {
2911 sc->bslot[i] = NULL;
2912 break;
2913 }
2914 }
2915 avf->bbuf = NULL;
2916 }
2917 if (avf->opmode == NL80211_IFTYPE_AP)
2918 sc->num_ap_vifs--;
2919 else if (avf->opmode == NL80211_IFTYPE_ADHOC)
2920 sc->num_adhoc_vifs--;
8a63facc 2921
62c58fb4 2922 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2923 mutex_unlock(&sc->lock);
2924}
2925
2926/*
2927 * TODO: Phy disable/diversity etc
2928 */
2929static int
2930ath5k_config(struct ieee80211_hw *hw, u32 changed)
2931{
2932 struct ath5k_softc *sc = hw->priv;
2933 struct ath5k_hw *ah = sc->ah;
2934 struct ieee80211_conf *conf = &hw->conf;
2935 int ret = 0;
2936
2937 mutex_lock(&sc->lock);
2938
2939 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2940 ret = ath5k_chan_set(sc, conf->channel);
2941 if (ret < 0)
2942 goto unlock;
2943 }
2944
2945 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2946 (sc->power_level != conf->power_level)) {
a0823810
NK		 2947 sc->power_level = conf->power_level;
2948
2949 /* Half dB steps */
2950 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2951 }
fa1c114f 2952
2bed03eb
NK		 2953 /* TODO:
2954 * 1) Move this on config_interface and handle each case
2955 * separately eg. when we have only one STA vif, use
2956 * AR5K_ANTMODE_SINGLE_AP
2957 *
2958 * 2) Allow the user to change antenna mode eg. when only
2959 * one antenna is present
2960 *
2961 * 3) Allow the user to set default/tx antenna when possible
2962 *
2963 * 4) Default mode should handle 90% of the cases, together
2964 * with fixed a/b and single AP modes we should be able to
2965 * handle 99%. Sectored modes are extreme cases and i still
2966 * haven't found a usage for them. If we decide to support them,
2967 * then we must allow the user to set how many tx antennas we
2968 * have available
2969 */
caec9112 2970 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
be009370 2971
55aa4e0f 2972unlock:
be009370 2973 mutex_unlock(&sc->lock);
55aa4e0f 2974 return ret;
fa1c114f
JS		 2975}
2976
3ac64bee 2977static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 2978 struct netdev_hw_addr_list *mc_list)
3ac64bee
JB		 2979{
2980 u32 mfilt[2], val;
3ac64bee 2981 u8 pos;
22bedad3 2982 struct netdev_hw_addr *ha;
3ac64bee
JB		 2983
2984 mfilt[0] = 0;
2985 mfilt[1] = 1;
2986
22bedad3 2987 netdev_hw_addr_list_for_each(ha, mc_list) {
3ac64bee 2988 /* calculate XOR of eight 6-bit values */
22bedad3 2989 val = get_unaligned_le32(ha->addr + 0);
3ac64bee 2990 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
22bedad3 2991 val = get_unaligned_le32(ha->addr + 3);
3ac64bee
JB		 2992 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2993 pos &= 0x3f;
2994 mfilt[pos / 32] |= (1 << (pos % 32));
2995 /* XXX: we might be able to just do this instead,
2996 * but not sure, needs testing, if we do use this we'd
2997 * neet to inform below to not reset the mcast */
2998 /* ath5k_hw_set_mcast_filterindex(ah,
22bedad3 2999 * ha->addr[5]); */
3ac64bee
JB		 3000 }
3001
3002 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3003}
3004
b1ae1edf
BG		 3005static bool ath_any_vif_assoc(struct ath5k_softc *sc)
3006{
3007 struct ath_vif_iter_data iter_data;
3008 iter_data.hw_macaddr = NULL;
3009 iter_data.any_assoc = false;
3010 iter_data.need_set_hw_addr = false;
3011 iter_data.found_active = true;
3012
3013 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
3014 &iter_data);
3015 return iter_data.any_assoc;
3016}
3017
fa1c114f
JS		 3018#define SUPPORTED_FIF_FLAGS \
3019 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3020 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3021 FIF_BCN_PRBRESP_PROMISC
3022/*
3023 * o always accept unicast, broadcast, and multicast traffic
3024 * o multicast traffic for all BSSIDs will be enabled if mac80211
3025 * says it should be
3026 * o maintain current state of phy ofdm or phy cck error reception.
3027 * If the hardware detects any of these type of errors then
3028 * ath5k_hw_get_rx_filter() will pass to us the respective
3029 * hardware filters to be able to receive these type of frames.
3030 * o probe request frames are accepted only when operating in
3031 * hostap, adhoc, or monitor modes
3032 * o enable promiscuous mode according to the interface state
3033 * o accept beacons:
3034 * - when operating in adhoc mode so the 802.11 layer creates
3035 * node table entries for peers,
3036 * - when operating in station mode for collecting rssi data when
3037 * the station is otherwise quiet, or
3038 * - when scanning
3039 */
3040static void ath5k_configure_filter(struct ieee80211_hw *hw,
3041 unsigned int changed_flags,
3042 unsigned int *new_flags,
3ac64bee 3043 u64 multicast)
fa1c114f
JS		 3044{
3045 struct ath5k_softc *sc = hw->priv;
3046 struct ath5k_hw *ah = sc->ah;
3ac64bee 3047 u32 mfilt[2], rfilt;
fa1c114f 3048
56d1de0a
BC		 3049 mutex_lock(&sc->lock);
3050
3ac64bee
JB		 3051 mfilt[0] = multicast;
3052 mfilt[1] = multicast >> 32;
fa1c114f
JS		 3053
3054 /* Only deal with supported flags */
3055 changed_flags &= SUPPORTED_FIF_FLAGS;
3056 *new_flags &= SUPPORTED_FIF_FLAGS;
3057
3058 /* If HW detects any phy or radar errors, leave those filters on.
3059 * Also, always enable Unicast, Broadcasts and Multicast
3060 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3061 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3062 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3063 AR5K_RX_FILTER_MCAST);
3064
3065 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3066 if (*new_flags & FIF_PROMISC_IN_BSS) {
fa1c114f 3067 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3068 } else {
fa1c114f 3069 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3070 }
fa1c114f
JS		 3071 }
3072
6b5dcccb
BC		 3073 if (test_bit(ATH_STAT_PROMISC, sc->status))
3074 rfilt |= AR5K_RX_FILTER_PROM;
3075
fa1c114f
JS		 3076 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3077 if (*new_flags & FIF_ALLMULTI) {
3078 mfilt[0] = ~0;
3079 mfilt[1] = ~0;
fa1c114f
JS		 3080 }
3081
3082 /* This is the best we can do */
3083 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3084 rfilt |= AR5K_RX_FILTER_PHYERR;
3085
3086 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
30bf4169 3087 * and probes for any BSSID */
b1ae1edf 3088 if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1))
30bf4169 3089 rfilt |= AR5K_RX_FILTER_BEACON;
fa1c114f
JS		 3090
3091 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3092 * set we should only pass on control frames for this
3093 * station. This needs testing. I believe right now this
3094 * enables *all* control frames, which is OK.. but
3095 * but we should see if we can improve on granularity */
3096 if (*new_flags & FIF_CONTROL)
3097 rfilt |= AR5K_RX_FILTER_CONTROL;
3098
3099 /* Additional settings per mode -- this is per ath5k */
3100
3101 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3102
56d1de0a
BC		 3103 switch (sc->opmode) {
3104 case NL80211_IFTYPE_MESH_POINT:
56d1de0a
BC		 3105 rfilt |= AR5K_RX_FILTER_CONTROL |
3106 AR5K_RX_FILTER_BEACON |
3107 AR5K_RX_FILTER_PROBEREQ |
3108 AR5K_RX_FILTER_PROM;
3109 break;
3110 case NL80211_IFTYPE_AP:
3111 case NL80211_IFTYPE_ADHOC:
3112 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3113 AR5K_RX_FILTER_BEACON;
3114 break;
3115 case NL80211_IFTYPE_STATION:
3116 if (sc->assoc)
3117 rfilt |= AR5K_RX_FILTER_BEACON;
3118 default:
3119 break;
3120 }
fa1c114f
JS		 3121
3122 /* Set filters */
0bbac08f 3123 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3124
3125 /* Set multicast bits */
3126 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
a180a130 3127 /* Set the cached hw filter flags, this will later actually
fa1c114f
JS		 3128 * be set in HW */
3129 sc->filter_flags = rfilt;
56d1de0a
BC		 3130
3131 mutex_unlock(&sc->lock);
fa1c114f
JS		 3132}
3133
3134static int
3135ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3136 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3137 struct ieee80211_key_conf *key)
fa1c114f
JS		 3138{
3139 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 3140 struct ath5k_hw *ah = sc->ah;
3141 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 3142 int ret = 0;
3143
9ad9a26e
BC		 3144 if (modparam_nohwcrypt)
3145 return -EOPNOTSUPP;
3146
97359d12
JB		 3147 switch (key->cipher) {
3148 case WLAN_CIPHER_SUITE_WEP40:
3149 case WLAN_CIPHER_SUITE_WEP104:
3150 case WLAN_CIPHER_SUITE_TKIP:
3f64b435 3151 break;
97359d12 3152 case WLAN_CIPHER_SUITE_CCMP:
781f3136 3153 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
1c818740 3154 break;
fa1c114f
JS		 3155 return -EOPNOTSUPP;
3156 default:
3157 WARN_ON(1);
3158 return -EINVAL;
3159 }
3160
3161 mutex_lock(&sc->lock);
3162
3163 switch (cmd) {
3164 case SET_KEY:
e0f8c2a9
BR		 3165 ret = ath_key_config(common, vif, sta, key);
3166 if (ret >= 0) {
3167 key->hw_key_idx = ret;
3168 /* push IV and Michael MIC generation to stack */
3169 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3170 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
3171 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3172 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
3173 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
3174 ret = 0;
fa1c114f 3175 }
fa1c114f
JS		 3176 break;
3177 case DISABLE_KEY:
e0f8c2a9 3178 ath_key_delete(common, key);
fa1c114f
JS		 3179 break;
3180 default:
3181 ret = -EINVAL;
fa1c114f
JS		 3182 }
3183
8a63facc
BC		 3184 mmiowb();
3185 mutex_unlock(&sc->lock);
3186 return ret;
3187}
3188
3189static int
3190ath5k_get_stats(struct ieee80211_hw *hw,
3191 struct ieee80211_low_level_stats *stats)
3192{
3193 struct ath5k_softc *sc = hw->priv;
3194
3195 /* Force update */
3196 ath5k_hw_update_mib_counters(sc->ah);
3197
3198 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3199 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3200 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3201 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3202
3203 return 0;
3204}
3205
3206static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3207 struct survey_info *survey)
3208{
3209 struct ath5k_softc *sc = hw->priv;
3210 struct ieee80211_conf *conf = &hw->conf;
3211
3212 if (idx != 0)
3213 return -ENOENT;
3214
3215 survey->channel = conf->channel;
3216 survey->filled = SURVEY_INFO_NOISE_DBM;
3217 survey->noise = sc->ah->ah_noise_floor;
3218
3219 return 0;
3220}
3221
3222static u64
3223ath5k_get_tsf(struct ieee80211_hw *hw)
3224{
3225 struct ath5k_softc *sc = hw->priv;
3226
3227 return ath5k_hw_get_tsf64(sc->ah);
3228}
3229
3230static void
3231ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3232{
3233 struct ath5k_softc *sc = hw->priv;
3234
3235 ath5k_hw_set_tsf64(sc->ah, tsf);
3236}
3237
3238static void
3239ath5k_reset_tsf(struct ieee80211_hw *hw)
3240{
3241 struct ath5k_softc *sc = hw->priv;
3242
3243 /*
3244 * in IBSS mode we need to update the beacon timers too.
3245 * this will also reset the TSF if we call it with 0
3246 */
3247 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3248 ath5k_beacon_update_timers(sc, 0);
3249 else
3250 ath5k_hw_reset_tsf(sc->ah);
3251}
3252
3253static void
3254set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3255{
3256 struct ath5k_softc *sc = hw->priv;
3257 struct ath5k_hw *ah = sc->ah;
3258 u32 rfilt;
3259 rfilt = ath5k_hw_get_rx_filter(ah);
3260 if (enable)
3261 rfilt |= AR5K_RX_FILTER_BEACON;
3262 else
3263 rfilt &= ~AR5K_RX_FILTER_BEACON;
3264 ath5k_hw_set_rx_filter(ah, rfilt);
3265 sc->filter_flags = rfilt;
3266}
3267
3268static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3269 struct ieee80211_vif *vif,
3270 struct ieee80211_bss_conf *bss_conf,
3271 u32 changes)
3272{
b1ae1edf 3273 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 3274 struct ath5k_softc *sc = hw->priv;
3275 struct ath5k_hw *ah = sc->ah;
3276 struct ath_common *common = ath5k_hw_common(ah);
3277 unsigned long flags;
3278
3279 mutex_lock(&sc->lock);
8a63facc
BC		 3280
3281 if (changes & BSS_CHANGED_BSSID) {
3282 /* Cache for later use during resets */
3283 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3284 common->curaid = 0;
3285 ath5k_hw_set_bssid(ah);
3286 mmiowb();
3287 }
3288
3289 if (changes & BSS_CHANGED_BEACON_INT)
3290 sc->bintval = bss_conf->beacon_int;
3291
3292 if (changes & BSS_CHANGED_ASSOC) {
b1ae1edf
BG		 3293 avf->assoc = bss_conf->assoc;
3294 if (bss_conf->assoc)
3295 sc->assoc = bss_conf->assoc;
3296 else
3297 sc->assoc = ath_any_vif_assoc(sc);
3298
8a63facc
BC		 3299 if (sc->opmode == NL80211_IFTYPE_STATION)
3300 set_beacon_filter(hw, sc->assoc);
3301 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3302 AR5K_LED_ASSOC : AR5K_LED_INIT);
3303 if (bss_conf->assoc) {
3304 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3305 "Bss Info ASSOC %d, bssid: %pM\n",
3306 bss_conf->aid, common->curbssid);
3307 common->curaid = bss_conf->aid;
3308 ath5k_hw_set_bssid(ah);
3309 /* Once ANI is available you would start it here */
3310 }
3311 }
3312
3313 if (changes & BSS_CHANGED_BEACON) {
3314 spin_lock_irqsave(&sc->block, flags);
3315 ath5k_beacon_update(hw, vif);
3316 spin_unlock_irqrestore(&sc->block, flags);
3317 }
3318
3319 if (changes & BSS_CHANGED_BEACON_ENABLED)
3320 sc->enable_beacon = bss_conf->enable_beacon;
3321
3322 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3323 BSS_CHANGED_BEACON_INT))
3324 ath5k_beacon_config(sc);
3325
8a63facc
BC		 3326 mutex_unlock(&sc->lock);
3327}
3328
3329static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3330{
3331 struct ath5k_softc *sc = hw->priv;
3332 if (!sc->assoc)
3333 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3334}
3335
3336static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3337{
3338 struct ath5k_softc *sc = hw->priv;
3339 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3340 AR5K_LED_ASSOC : AR5K_LED_INIT);
3341}
3342
3343/**
3344 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3345 *
3346 * @hw: struct ieee80211_hw pointer
3347 * @coverage_class: IEEE 802.11 coverage class number
3348 *
3349 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3350 * coverage class. The values are persistent, they are restored after device
3351 * reset.
3352 */
3353static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3354{
3355 struct ath5k_softc *sc = hw->priv;
3356
3357 mutex_lock(&sc->lock);
3358 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3359 mutex_unlock(&sc->lock);
3360}
3361
e0b1cc52
BR		 3362static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3363 const struct ieee80211_tx_queue_params *params)
3364{
3365 struct ath5k_softc *sc = hw->priv;
3366 struct ath5k_hw *ah = sc->ah;
3367 struct ath5k_txq_info qi;
3368 int ret = 0;
3369
3370 if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
3371 return 0;
3372
3373 mutex_lock(&sc->lock);
3374
3375 ath5k_hw_get_tx_queueprops(ah, queue, &qi);
3376
3377 qi.tqi_aifs = params->aifs;
3378 qi.tqi_cw_min = params->cw_min;
3379 qi.tqi_cw_max = params->cw_max;
3380 qi.tqi_burst_time = params->txop;
3381
3382 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3383 "Configure tx [queue %d], "
3384 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3385 queue, params->aifs, params->cw_min,
3386 params->cw_max, params->txop);
3387
3388 if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
3389 ATH5K_ERR(sc,
3390 "Unable to update hardware queue %u!\n", queue);
3391 ret = -EIO;
3392 } else
3393 ath5k_hw_reset_tx_queue(ah, queue);
3394
3395 mutex_unlock(&sc->lock);
3396
3397 return ret;
3398}
3399
8a63facc
BC		 3400static const struct ieee80211_ops ath5k_hw_ops = {
3401 .tx = ath5k_tx,
3402 .start = ath5k_start,
3403 .stop = ath5k_stop,
3404 .add_interface = ath5k_add_interface,
3405 .remove_interface = ath5k_remove_interface,
3406 .config = ath5k_config,
3407 .prepare_multicast = ath5k_prepare_multicast,
3408 .configure_filter = ath5k_configure_filter,
3409 .set_key = ath5k_set_key,
3410 .get_stats = ath5k_get_stats,
3411 .get_survey = ath5k_get_survey,
e0b1cc52 3412 .conf_tx = ath5k_conf_tx,
8a63facc
BC		 3413 .get_tsf = ath5k_get_tsf,
3414 .set_tsf = ath5k_set_tsf,
3415 .reset_tsf = ath5k_reset_tsf,
3416 .bss_info_changed = ath5k_bss_info_changed,
3417 .sw_scan_start = ath5k_sw_scan_start,
3418 .sw_scan_complete = ath5k_sw_scan_complete,
3419 .set_coverage_class = ath5k_set_coverage_class,
3420};
3421
3422/********************\
3423* PCI Initialization *
3424\********************/
3425
3426static int __devinit
3427ath5k_pci_probe(struct pci_dev *pdev,
3428 const struct pci_device_id *id)
3429{
3430 void __iomem *mem;
3431 struct ath5k_softc *sc;
3432 struct ath_common *common;
3433 struct ieee80211_hw *hw;
3434 int ret;
3435 u8 csz;
3436
3437 /*
3438 * L0s needs to be disabled on all ath5k cards.
3439 *
3440 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
3441 * by default in the future in 2.6.36) this will also mean both L1 and
3442 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
3443 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
3444 * though but cannot currently undue the effect of a blacklist, for
3445 * details you can read pcie_aspm_sanity_check() and see how it adjusts
3446 * the device link capability.
3447 *
3448 * It may be possible in the future to implement some PCI API to allow
3449 * drivers to override blacklists for pre 1.1 PCIe but for now it is
3450 * best to accept that both L0s and L1 will be disabled completely for
3451 * distributions shipping with CONFIG_PCIEASPM rather than having this
3452 * issue present. Motivation for adding this new API will be to help
3453 * with power consumption for some of these devices.
3454 */
3455 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
3456
3457 ret = pci_enable_device(pdev);
3458 if (ret) {
3459 dev_err(&pdev->dev, "can't enable device\n");
3460 goto err;
3461 }
3462
3463 /* XXX 32-bit addressing only */
3464 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3465 if (ret) {
3466 dev_err(&pdev->dev, "32-bit DMA not available\n");
3467 goto err_dis;
3468 }
3469
3470 /*
3471 * Cache line size is used to size and align various
3472 * structures used to communicate with the hardware.
3473 */
3474 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
3475 if (csz == 0) {
3476 /*
3477 * Linux 2.4.18 (at least) writes the cache line size
3478 * register as a 16-bit wide register which is wrong.
3479 * We must have this setup properly for rx buffer
3480 * DMA to work so force a reasonable value here if it
3481 * comes up zero.
3482 */
3483 csz = L1_CACHE_BYTES >> 2;
3484 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
3485 }
3486 /*
3487 * The default setting of latency timer yields poor results,
3488 * set it to the value used by other systems. It may be worth
3489 * tweaking this setting more.
3490 */
3491 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
3492
3493 /* Enable bus mastering */
3494 pci_set_master(pdev);
3495
3496 /*
3497 * Disable the RETRY_TIMEOUT register (0x41) to keep
3498 * PCI Tx retries from interfering with C3 CPU state.
3499 */
3500 pci_write_config_byte(pdev, 0x41, 0);
3501
3502 ret = pci_request_region(pdev, 0, "ath5k");
3503 if (ret) {
3504 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
3505 goto err_dis;
3506 }
3507
3508 mem = pci_iomap(pdev, 0, 0);
3509 if (!mem) {
3510 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
3511 ret = -EIO;
3512 goto err_reg;
3513 }
3514
3515 /*
3516 * Allocate hw (mac80211 main struct)
3517 * and hw->priv (driver private data)
3518 */
3519 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
3520 if (hw == NULL) {
3521 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
3522 ret = -ENOMEM;
3523 goto err_map;
3524 }
3525
3526 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
3527
3528 /* Initialize driver private data */
3529 SET_IEEE80211_DEV(hw, &pdev->dev);
3530 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3531 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3532 IEEE80211_HW_SIGNAL_DBM;
3533
3534 hw->wiphy->interface_modes =
3535 BIT(NL80211_IFTYPE_AP) |
3536 BIT(NL80211_IFTYPE_STATION) |
3537 BIT(NL80211_IFTYPE_ADHOC) |
3538 BIT(NL80211_IFTYPE_MESH_POINT);
3539
3540 hw->extra_tx_headroom = 2;
3541 hw->channel_change_time = 5000;
3542 sc = hw->priv;
3543 sc->hw = hw;
3544 sc->pdev = pdev;
3545
8a63facc
BC		 3546 /*
3547 * Mark the device as detached to avoid processing
3548 * interrupts until setup is complete.
3549 */
3550 __set_bit(ATH_STAT_INVALID, sc->status);
3551
3552 sc->iobase = mem; /* So we can unmap it on detach */
3553 sc->opmode = NL80211_IFTYPE_STATION;
3554 sc->bintval = 1000;
3555 mutex_init(&sc->lock);
3556 spin_lock_init(&sc->rxbuflock);
3557 spin_lock_init(&sc->txbuflock);
3558 spin_lock_init(&sc->block);
3559
3560 /* Set private data */
3561 pci_set_drvdata(pdev, sc);
3562
3563 /* Setup interrupt handler */
3564 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
3565 if (ret) {
3566 ATH5K_ERR(sc, "request_irq failed\n");
3567 goto err_free;
3568 }
3569
3570 /* If we passed the test, malloc an ath5k_hw struct */
3571 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
3572 if (!sc->ah) {
3573 ret = -ENOMEM;
3574 ATH5K_ERR(sc, "out of memory\n");
3575 goto err_irq;
3576 }
3577
3578 sc->ah->ah_sc = sc;
3579 sc->ah->ah_iobase = sc->iobase;
3580 common = ath5k_hw_common(sc->ah);
3581 common->ops = &ath5k_common_ops;
3582 common->ah = sc->ah;
3583 common->hw = hw;
3584 common->cachelsz = csz << 2; /* convert to bytes */
9192f715 3585 spin_lock_init(&common->cc_lock);
8a63facc
BC		 3586
3587 /* Initialize device */
3588 ret = ath5k_hw_attach(sc);
3589 if (ret) {
3590 goto err_free_ah;
3591 }
3592
3593 /* set up multi-rate retry capabilities */
3594 if (sc->ah->ah_version == AR5K_AR5212) {
3595 hw->max_rates = 4;
3596 hw->max_rate_tries = 11;
3597 }
3598
b1ae1edf
BG		 3599 hw->vif_data_size = sizeof(struct ath5k_vif);
3600
8a63facc
BC		 3601 /* Finish private driver data initialization */
3602 ret = ath5k_attach(pdev, hw);
3603 if (ret)
3604 goto err_ah;
3605
3606 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
3607 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
3608 sc->ah->ah_mac_srev,
3609 sc->ah->ah_phy_revision);
3610
3611 if (!sc->ah->ah_single_chip) {
3612 /* Single chip radio (!RF5111) */
3613 if (sc->ah->ah_radio_5ghz_revision &&
3614 !sc->ah->ah_radio_2ghz_revision) {
3615 /* No 5GHz support -> report 2GHz radio */
3616 if (!test_bit(AR5K_MODE_11A,
3617 sc->ah->ah_capabilities.cap_mode)) {
3618 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3619 ath5k_chip_name(AR5K_VERSION_RAD,
3620 sc->ah->ah_radio_5ghz_revision),
3621 sc->ah->ah_radio_5ghz_revision);
3622 /* No 2GHz support (5110 and some
3623 * 5Ghz only cards) -> report 5Ghz radio */
3624 } else if (!test_bit(AR5K_MODE_11B,
3625 sc->ah->ah_capabilities.cap_mode)) {
3626 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3627 ath5k_chip_name(AR5K_VERSION_RAD,
3628 sc->ah->ah_radio_5ghz_revision),
3629 sc->ah->ah_radio_5ghz_revision);
3630 /* Multiband radio */
3631 } else {
3632 ATH5K_INFO(sc, "RF%s multiband radio found"
3633 " (0x%x)\n",
3634 ath5k_chip_name(AR5K_VERSION_RAD,
3635 sc->ah->ah_radio_5ghz_revision),
3636 sc->ah->ah_radio_5ghz_revision);
3637 }
3638 }
3639 /* Multi chip radio (RF5111 - RF2111) ->
3640 * report both 2GHz/5GHz radios */
3641 else if (sc->ah->ah_radio_5ghz_revision &&
3642 sc->ah->ah_radio_2ghz_revision){
3643 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3644 ath5k_chip_name(AR5K_VERSION_RAD,
3645 sc->ah->ah_radio_5ghz_revision),
3646 sc->ah->ah_radio_5ghz_revision);
3647 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3648 ath5k_chip_name(AR5K_VERSION_RAD,
3649 sc->ah->ah_radio_2ghz_revision),
3650 sc->ah->ah_radio_2ghz_revision);
3651 }
3652 }
3653
d84a35d1 3654 ath5k_debug_init_device(sc);
55ee82b5 3655
8a63facc
BC		 3656 /* ready to process interrupts */
3657 __clear_bit(ATH_STAT_INVALID, sc->status);
55ee82b5
HS		 3658
3659 return 0;
8a63facc
BC		 3660err_ah:
3661 ath5k_hw_detach(sc->ah);
3662err_free_ah:
3663 kfree(sc->ah);
3664err_irq:
3665 free_irq(pdev->irq, sc);
3666err_free:
3667 ieee80211_free_hw(hw);
3668err_map:
3669 pci_iounmap(pdev, mem);
3670err_reg:
3671 pci_release_region(pdev, 0);
3672err_dis:
3673 pci_disable_device(pdev);
3674err:
3675 return ret;
55ee82b5
HS		 3676}
3677
8a63facc
BC		 3678static void __devexit
3679ath5k_pci_remove(struct pci_dev *pdev)
fa1c114f 3680{
8a63facc 3681 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 3682
8a63facc
BC		 3683 ath5k_debug_finish_device(sc);
3684 ath5k_detach(pdev, sc->hw);
3685 ath5k_hw_detach(sc->ah);
3686 kfree(sc->ah);
3687 free_irq(pdev->irq, sc);
3688 pci_iounmap(pdev, sc->iobase);
3689 pci_release_region(pdev, 0);
3690 pci_disable_device(pdev);
3691 ieee80211_free_hw(sc->hw);
fa1c114f
JS		 3692}
3693
8a63facc
BC		 3694#ifdef CONFIG_PM_SLEEP
3695static int ath5k_pci_suspend(struct device *dev)
3b5d665b 3696{
8a63facc 3697 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
3b5d665b 3698
8a63facc
BC		 3699 ath5k_led_off(sc);
3700 return 0;
3b5d665b
AF		 3701}
3702
8a63facc 3703static int ath5k_pci_resume(struct device *dev)
fa1c114f 3704{
8a63facc
BC		 3705 struct pci_dev *pdev = to_pci_dev(dev);
3706 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 3707
9804b98d 3708 /*
8a63facc
BC		 3709 * Suspend/Resume resets the PCI configuration space, so we have to
3710 * re-disable the RETRY_TIMEOUT register (0x41) to keep
3711 * PCI Tx retries from interfering with C3 CPU state
9804b98d 3712 */
8a63facc
BC		 3713 pci_write_config_byte(pdev, 0x41, 0);
3714
3715 ath5k_led_enable(sc);
3716 return 0;
fa1c114f
JS		 3717}
3718
8a63facc
BC		 3719static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
3720#define ATH5K_PM_OPS (&ath5k_pm_ops)
3721#else
3722#define ATH5K_PM_OPS NULL
3723#endif /* CONFIG_PM_SLEEP */
3724
3725static struct pci_driver ath5k_pci_driver = {
3726 .name = KBUILD_MODNAME,
3727 .id_table = ath5k_pci_id_table,
3728 .probe = ath5k_pci_probe,
3729 .remove = __devexit_p(ath5k_pci_remove),
3730 .driver.pm = ATH5K_PM_OPS,
3731};
3732
1071db86 3733/*
8a63facc 3734 * Module init/exit functions
1071db86 3735 */
8a63facc
BC		 3736static int __init
3737init_ath5k_pci(void)
fa1c114f 3738{
fa1c114f 3739 int ret;
57c4d7b4 3740
8a63facc
BC		 3741 ret = pci_register_driver(&ath5k_pci_driver);
3742 if (ret) {
3743 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
3744 return ret;
2d0ddec5
JB		 3745 }
3746
8a63facc 3747 return 0;
02969b38 3748}
f0f3d388 3749
8a63facc
BC		 3750static void __exit
3751exit_ath5k_pci(void)
f0f3d388 3752{
8a63facc 3753 pci_unregister_driver(&ath5k_pci_driver);
f0f3d388 3754}
6e08d228 3755
8a63facc
BC		 3756module_init(init_ath5k_pci);
3757module_exit(exit_ath5k_pci);
Linux 6.x block layer and io_uring tree(s)