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mac80211: make tx() operation return void
[linux-block.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
fa1c114f
JS		 50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
5a0e3ad6 52#include <linux/slab.h>
b1ae1edf 53#include <linux/etherdevice.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
fa1c114f 63
0e472252
BC		 64#define CREATE_TRACE_POINTS
65#include "trace.h"
66
18cb6e32
JL		 67int ath5k_modparam_nohwcrypt;
68module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 69MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 70
42639fcd 71static int modparam_all_channels;
46802a4f 72module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 73MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
74
fa1c114f
JS		 75/* Module info */
76MODULE_AUTHOR("Jiri Slaby");
77MODULE_AUTHOR("Nick Kossifidis");
78MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
79MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
80MODULE_LICENSE("Dual BSD/GPL");
fa1c114f 81
132b1c3e 82static int ath5k_init(struct ieee80211_hw *hw);
8aec7af9
NK		 83static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
84 bool skip_pcu);
cd2c5486
BR		 85int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
86void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f 87
fa1c114f 88/* Known SREVs */
2c91108c 89static const struct ath5k_srev_name srev_names[] = {
a0b907ee
FF		 90#ifdef CONFIG_ATHEROS_AR231X
91 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
92 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
93 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
94 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
95 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
96 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
97 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
98#else
1bef016a
NK		 99 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
100 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
101 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
102 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
103 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
104 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
105 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
106 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
107 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
108 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
109 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
110 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
111 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
112 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
113 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
114 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
115 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
116 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
a0b907ee 117#endif
1bef016a 118 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 119 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
120 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 121 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 122 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
123 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
124 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 125 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 126 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
127 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 128 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
129 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
130 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 131 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f 132 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
a0b907ee
FF		 133#ifdef CONFIG_ATHEROS_AR231X
134 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
135 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
136#endif
fa1c114f
JS		 137 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
138};
139
2c91108c 140static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 141 { .bitrate = 10,
142 .hw_value = ATH5K_RATE_CODE_1M, },
143 { .bitrate = 20,
144 .hw_value = ATH5K_RATE_CODE_2M,
145 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
146 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
147 { .bitrate = 55,
148 .hw_value = ATH5K_RATE_CODE_5_5M,
149 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
150 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
151 { .bitrate = 110,
152 .hw_value = ATH5K_RATE_CODE_11M,
153 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
154 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
155 { .bitrate = 60,
156 .hw_value = ATH5K_RATE_CODE_6M,
157 .flags = 0 },
158 { .bitrate = 90,
159 .hw_value = ATH5K_RATE_CODE_9M,
160 .flags = 0 },
161 { .bitrate = 120,
162 .hw_value = ATH5K_RATE_CODE_12M,
163 .flags = 0 },
164 { .bitrate = 180,
165 .hw_value = ATH5K_RATE_CODE_18M,
166 .flags = 0 },
167 { .bitrate = 240,
168 .hw_value = ATH5K_RATE_CODE_24M,
169 .flags = 0 },
170 { .bitrate = 360,
171 .hw_value = ATH5K_RATE_CODE_36M,
172 .flags = 0 },
173 { .bitrate = 480,
174 .hw_value = ATH5K_RATE_CODE_48M,
175 .flags = 0 },
176 { .bitrate = 540,
177 .hw_value = ATH5K_RATE_CODE_54M,
178 .flags = 0 },
179 /* XR missing */
180};
181
fa1c114f
JS		 182static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
183{
184 u64 tsf = ath5k_hw_get_tsf64(ah);
185
186 if ((tsf & 0x7fff) < rstamp)
187 tsf -= 0x8000;
188
189 return (tsf & ~0x7fff) | rstamp;
190}
191
e5b046d8 192const char *
fa1c114f
JS		 193ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
194{
195 const char *name = "xxxxx";
196 unsigned int i;
197
198 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
199 if (srev_names[i].sr_type != type)
200 continue;
75d0edb8
NK		 201
202 if ((val & 0xf0) == srev_names[i].sr_val)
203 name = srev_names[i].sr_name;
204
205 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 206 name = srev_names[i].sr_name;
207 break;
208 }
209 }
210
211 return name;
212}
e5aa8474
LR		 213static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
214{
215 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
216 return ath5k_hw_reg_read(ah, reg_offset);
217}
218
219static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
220{
221 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
222 ath5k_hw_reg_write(ah, val, reg_offset);
223}
224
225static const struct ath_ops ath5k_common_ops = {
226 .read = ath5k_ioread32,
227 .write = ath5k_iowrite32,
228};
fa1c114f 229
8a63facc
BC		 230/***********************\
231* Driver Initialization *
232\***********************/
233
234static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 235{
8a63facc
BC		 236 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
237 struct ath5k_softc *sc = hw->priv;
238 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 239
8a63facc
BC		 240 return ath_reg_notifier_apply(wiphy, request, regulatory);
241}
6ccf15a1 242
8a63facc
BC		 243/********************\
244* Channel/mode setup *
245\********************/
fa1c114f 246
8a63facc
BC		 247/*
248 * Returns true for the channel numbers used without all_channels modparam.
249 */
410e6120 250static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
8a63facc 251{
410e6120
BR		 252 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
253 return true;
254
255 return /* UNII 1,2 */
256 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
8a63facc
BC		 257 /* midband */
258 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
259 /* UNII-3 */
410e6120
BR		 260 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
261 /* 802.11j 5.030-5.080 GHz (20MHz) */
262 (chan == 8 || chan == 12 || chan == 16) ||
263 /* 802.11j 4.9GHz (20MHz) */
264 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
8a63facc 265}
fa1c114f 266
8a63facc 267static unsigned int
97d9c3a3
BR		 268ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
269 unsigned int mode, unsigned int max)
8a63facc 270{
2b1351a3 271 unsigned int count, size, chfreq, freq, ch;
90c02d72 272 enum ieee80211_band band;
fa1c114f 273
8a63facc
BC		 274 switch (mode) {
275 case AR5K_MODE_11A:
8a63facc 276 /* 1..220, but 2GHz frequencies are filtered by check_channel */
97d9c3a3 277 size = 220;
8a63facc 278 chfreq = CHANNEL_5GHZ;
90c02d72 279 band = IEEE80211_BAND_5GHZ;
8a63facc
BC		 280 break;
281 case AR5K_MODE_11B:
282 case AR5K_MODE_11G:
8a63facc
BC		 283 size = 26;
284 chfreq = CHANNEL_2GHZ;
90c02d72 285 band = IEEE80211_BAND_2GHZ;
8a63facc
BC		 286 break;
287 default:
288 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
289 return 0;
fa1c114f
JS		 290 }
291
2b1351a3
BR		 292 count = 0;
293 for (ch = 1; ch <= size && count < max; ch++) {
90c02d72
BR		 294 freq = ieee80211_channel_to_frequency(ch, band);
295
296 if (freq == 0) /* mapping failed - not a standard channel */
297 continue;
fa1c114f 298
8a63facc
BC		 299 /* Check if channel is supported by the chipset */
300 if (!ath5k_channel_ok(ah, freq, chfreq))
301 continue;
f59ac048 302
410e6120
BR		 303 if (!modparam_all_channels &&
304 !ath5k_is_standard_channel(ch, band))
8a63facc 305 continue;
f59ac048 306
8a63facc
BC		 307 /* Write channel info and increment counter */
308 channels[count].center_freq = freq;
90c02d72 309 channels[count].band = band;
8a63facc
BC		 310 switch (mode) {
311 case AR5K_MODE_11A:
312 case AR5K_MODE_11G:
313 channels[count].hw_value = chfreq | CHANNEL_OFDM;
314 break;
8a63facc
BC		 315 case AR5K_MODE_11B:
316 channels[count].hw_value = CHANNEL_B;
317 }
fa1c114f 318
8a63facc 319 count++;
8a63facc 320 }
fa1c114f 321
8a63facc
BC		 322 return count;
323}
fa1c114f 324
8a63facc
BC		 325static void
326ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
327{
328 u8 i;
fa1c114f 329
8a63facc
BC		 330 for (i = 0; i < AR5K_MAX_RATES; i++)
331 sc->rate_idx[b->band][i] = -1;
fa1c114f 332
8a63facc
BC		 333 for (i = 0; i < b->n_bitrates; i++) {
334 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
335 if (b->bitrates[i].hw_value_short)
336 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 337 }
8a63facc 338}
fa1c114f 339
8a63facc
BC		 340static int
341ath5k_setup_bands(struct ieee80211_hw *hw)
342{
343 struct ath5k_softc *sc = hw->priv;
344 struct ath5k_hw *ah = sc->ah;
345 struct ieee80211_supported_band *sband;
346 int max_c, count_c = 0;
347 int i;
fa1c114f 348
8a63facc
BC		 349 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
350 max_c = ARRAY_SIZE(sc->channels);
db719718 351
8a63facc
BC		 352 /* 2GHz band */
353 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
354 sband->band = IEEE80211_BAND_2GHZ;
355 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 356
8a63facc
BC		 357 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
358 /* G mode */
359 memcpy(sband->bitrates, &ath5k_rates[0],
360 sizeof(struct ieee80211_rate) * 12);
361 sband->n_bitrates = 12;
2f7fe870 362
8a63facc 363 sband->channels = sc->channels;
08105690 364 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 365 AR5K_MODE_11G, max_c);
fa1c114f 366
8a63facc
BC		 367 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
368 count_c = sband->n_channels;
369 max_c -= count_c;
370 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
371 /* B mode */
372 memcpy(sband->bitrates, &ath5k_rates[0],
373 sizeof(struct ieee80211_rate) * 4);
374 sband->n_bitrates = 4;
fa1c114f 375
8a63facc
BC		 376 /* 5211 only supports B rates and uses 4bit rate codes
377 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
378 * fix them up here:
379 */
380 if (ah->ah_version == AR5K_AR5211) {
381 for (i = 0; i < 4; i++) {
382 sband->bitrates[i].hw_value =
383 sband->bitrates[i].hw_value & 0xF;
384 sband->bitrates[i].hw_value_short =
385 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 386 }
387 }
fa1c114f 388
8a63facc 389 sband->channels = sc->channels;
08105690 390 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 391 AR5K_MODE_11B, max_c);
fa1c114f 392
8a63facc
BC		 393 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
394 count_c = sband->n_channels;
395 max_c -= count_c;
396 }
397 ath5k_setup_rate_idx(sc, sband);
fa1c114f 398
8a63facc
BC		 399 /* 5GHz band, A mode */
400 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
401 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
402 sband->band = IEEE80211_BAND_5GHZ;
403 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 404
8a63facc
BC		 405 memcpy(sband->bitrates, &ath5k_rates[4],
406 sizeof(struct ieee80211_rate) * 8);
407 sband->n_bitrates = 8;
fa1c114f 408
8a63facc 409 sband->channels = &sc->channels[count_c];
08105690 410 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 411 AR5K_MODE_11A, max_c);
fa1c114f 412
8a63facc
BC		 413 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
414 }
415 ath5k_setup_rate_idx(sc, sband);
416
417 ath5k_debug_dump_bands(sc);
fa1c114f 418
fa1c114f
JS		 419 return 0;
420}
421
8a63facc
BC		 422/*
423 * Set/change channels. We always reset the chip.
424 * To accomplish this we must first cleanup any pending DMA,
425 * then restart stuff after a la ath5k_init.
426 *
427 * Called with sc->lock.
428 */
cd2c5486 429int
8a63facc
BC		 430ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
431{
432 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
433 "channel set, resetting (%u -> %u MHz)\n",
434 sc->curchan->center_freq, chan->center_freq);
435
8451d22d 436 /*
8a63facc
BC		 437 * To switch channels clear any pending DMA operations;
438 * wait long enough for the RX fifo to drain, reset the
439 * hardware at the new frequency, and then re-enable
440 * the relevant bits of the h/w.
8451d22d 441 */
8aec7af9 442 return ath5k_reset(sc, chan, true);
fa1c114f 443}
fa1c114f 444
b1ae1edf
BG		 445struct ath_vif_iter_data {
446 const u8 *hw_macaddr;
447 u8 mask[ETH_ALEN];
448 u8 active_mac[ETH_ALEN]; /* first active MAC */
449 bool need_set_hw_addr;
450 bool found_active;
451 bool any_assoc;
62c58fb4 452 enum nl80211_iftype opmode;
b1ae1edf
BG		 453};
454
455static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
456{
457 struct ath_vif_iter_data *iter_data = data;
458 int i;
62c58fb4 459 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 460
461 if (iter_data->hw_macaddr)
462 for (i = 0; i < ETH_ALEN; i++)
463 iter_data->mask[i] &=
464 ~(iter_data->hw_macaddr[i] ^ mac[i]);
465
466 if (!iter_data->found_active) {
467 iter_data->found_active = true;
468 memcpy(iter_data->active_mac, mac, ETH_ALEN);
469 }
470
471 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
472 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
473 iter_data->need_set_hw_addr = false;
474
475 if (!iter_data->any_assoc) {
b1ae1edf
BG		 476 if (avf->assoc)
477 iter_data->any_assoc = true;
478 }
62c58fb4
BG		 479
480 /* Calculate combined mode - when APs are active, operate in AP mode.
481 * Otherwise use the mode of the new interface. This can currently
482 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 483 * interfaces is allowed.
62c58fb4
BG		 484 */
485 if (avf->opmode == NL80211_IFTYPE_AP)
486 iter_data->opmode = NL80211_IFTYPE_AP;
487 else
488 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
489 iter_data->opmode = avf->opmode;
b1ae1edf
BG		 490}
491
cd2c5486
BR		 492void
493ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
494 struct ieee80211_vif *vif)
b1ae1edf
BG		 495{
496 struct ath_common *common = ath5k_hw_common(sc->ah);
497 struct ath_vif_iter_data iter_data;
498
499 /*
500 * Use the hardware MAC address as reference, the hardware uses it
501 * together with the BSSID mask when matching addresses.
502 */
503 iter_data.hw_macaddr = common->macaddr;
504 memset(&iter_data.mask, 0xff, ETH_ALEN);
505 iter_data.found_active = false;
506 iter_data.need_set_hw_addr = true;
62c58fb4 507 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
b1ae1edf
BG		 508
509 if (vif)
510 ath_vif_iter(&iter_data, vif->addr, vif);
511
512 /* Get list of all active MAC addresses */
513 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
514 &iter_data);
515 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
516
62c58fb4
BG		 517 sc->opmode = iter_data.opmode;
518 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
519 /* Nothing active, default to station mode */
520 sc->opmode = NL80211_IFTYPE_STATION;
521
7afbb2f0
BG		 522 ath5k_hw_set_opmode(sc->ah, sc->opmode);
523 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
524 sc->opmode, ath_opmode_to_string(sc->opmode));
62c58fb4 525
b1ae1edf
BG		 526 if (iter_data.need_set_hw_addr && iter_data.found_active)
527 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
528
62c58fb4
BG		 529 if (ath5k_hw_hasbssidmask(sc->ah))
530 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
b1ae1edf
BG		 531}
532
cd2c5486 533void
b1ae1edf 534ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
fa1c114f 535{
fa1c114f 536 struct ath5k_hw *ah = sc->ah;
8a63facc 537 u32 rfilt;
fa1c114f 538
8a63facc
BC		 539 /* configure rx filter */
540 rfilt = sc->filter_flags;
541 ath5k_hw_set_rx_filter(ah, rfilt);
8a63facc 542 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
62c58fb4
BG		 543
544 ath5k_update_bssid_mask_and_opmode(sc, vif);
8a63facc 545}
fa1c114f 546
8a63facc
BC		 547static inline int
548ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
549{
550 int rix;
fa1c114f 551
8a63facc
BC		 552 /* return base rate on errors */
553 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
554 "hw_rix out of bounds: %x\n", hw_rix))
555 return 0;
556
930a7622 557 rix = sc->rate_idx[sc->curchan->band][hw_rix];
8a63facc
BC		 558 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
559 rix = 0;
560
561 return rix;
562}
563
564/***************\
565* Buffers setup *
566\***************/
567
568static
569struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
570{
571 struct ath_common *common = ath5k_hw_common(sc->ah);
572 struct sk_buff *skb;
fa1c114f
JS		 573
574 /*
8a63facc
BC		 575 * Allocate buffer with headroom_needed space for the
576 * fake physical layer header at the start.
fa1c114f 577 */
8a63facc
BC		 578 skb = ath_rxbuf_alloc(common,
579 common->rx_bufsize,
580 GFP_ATOMIC);
fa1c114f 581
8a63facc
BC		 582 if (!skb) {
583 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
584 common->rx_bufsize);
585 return NULL;
fa1c114f
JS		 586 }
587
aeae4ac9 588 *skb_addr = dma_map_single(sc->dev,
8a63facc 589 skb->data, common->rx_bufsize,
aeae4ac9
FF		 590 DMA_FROM_DEVICE);
591
592 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
8a63facc
BC		 593 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
594 dev_kfree_skb(skb);
595 return NULL;
0e149cf5 596 }
8a63facc
BC		 597 return skb;
598}
0e149cf5 599
8a63facc
BC		 600static int
601ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
602{
603 struct ath5k_hw *ah = sc->ah;
604 struct sk_buff *skb = bf->skb;
605 struct ath5k_desc *ds;
606 int ret;
fa1c114f 607
8a63facc
BC		 608 if (!skb) {
609 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
610 if (!skb)
611 return -ENOMEM;
612 bf->skb = skb;
f769c36b
BC		 613 }
614
8a63facc
BC		 615 /*
616 * Setup descriptors. For receive we always terminate
617 * the descriptor list with a self-linked entry so we'll
618 * not get overrun under high load (as can happen with a
619 * 5212 when ANI processing enables PHY error frames).
620 *
621 * To ensure the last descriptor is self-linked we create
622 * each descriptor as self-linked and add it to the end. As
623 * each additional descriptor is added the previous self-linked
624 * entry is "fixed" naturally. This should be safe even
625 * if DMA is happening. When processing RX interrupts we
626 * never remove/process the last, self-linked, entry on the
627 * descriptor list. This ensures the hardware always has
628 * someplace to write a new frame.
629 */
630 ds = bf->desc;
631 ds->ds_link = bf->daddr; /* link to self */
632 ds->ds_data = bf->skbaddr;
633 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 634 if (ret) {
8a63facc
BC		 635 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
636 return ret;
fa1c114f
JS		 637 }
638
8a63facc
BC		 639 if (sc->rxlink != NULL)
640 *sc->rxlink = bf->daddr;
641 sc->rxlink = &ds->ds_link;
fa1c114f 642 return 0;
fa1c114f
JS		 643}
644
8a63facc 645static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 646{
8a63facc
BC		 647 struct ieee80211_hdr *hdr;
648 enum ath5k_pkt_type htype;
649 __le16 fc;
fa1c114f 650
8a63facc
BC		 651 hdr = (struct ieee80211_hdr *)skb->data;
652 fc = hdr->frame_control;
fa1c114f 653
8a63facc
BC		 654 if (ieee80211_is_beacon(fc))
655 htype = AR5K_PKT_TYPE_BEACON;
656 else if (ieee80211_is_probe_resp(fc))
657 htype = AR5K_PKT_TYPE_PROBE_RESP;
658 else if (ieee80211_is_atim(fc))
659 htype = AR5K_PKT_TYPE_ATIM;
660 else if (ieee80211_is_pspoll(fc))
661 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 662 else
8a63facc 663 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 664
8a63facc 665 return htype;
42639fcd
BC		 666}
667
8a63facc
BC		 668static int
669ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
670 struct ath5k_txq *txq, int padsize)
fa1c114f 671{
8a63facc
BC		 672 struct ath5k_hw *ah = sc->ah;
673 struct ath5k_desc *ds = bf->desc;
674 struct sk_buff *skb = bf->skb;
675 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
676 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
677 struct ieee80211_rate *rate;
678 unsigned int mrr_rate[3], mrr_tries[3];
679 int i, ret;
680 u16 hw_rate;
681 u16 cts_rate = 0;
682 u16 duration = 0;
683 u8 rc_flags;
fa1c114f 684
8a63facc 685 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 686
8a63facc 687 /* XXX endianness */
aeae4ac9
FF		 688 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
689 DMA_TO_DEVICE);
fa1c114f 690
8a63facc 691 rate = ieee80211_get_tx_rate(sc->hw, info);
29ad2fac
JL		 692 if (!rate) {
693 ret = -EINVAL;
694 goto err_unmap;
695 }
fa1c114f 696
8a63facc
BC		 697 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
698 flags |= AR5K_TXDESC_NOACK;
fa1c114f 699
8a63facc
BC		 700 rc_flags = info->control.rates[0].flags;
701 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
702 rate->hw_value_short : rate->hw_value;
42639fcd 703
8a63facc
BC		 704 pktlen = skb->len;
705
706 /* FIXME: If we are in g mode and rate is a CCK rate
707 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
708 * from tx power (value is in dB units already) */
709 if (info->control.hw_key) {
710 keyidx = info->control.hw_key->hw_key_idx;
711 pktlen += info->control.hw_key->icv_len;
712 }
713 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
714 flags |= AR5K_TXDESC_RTSENA;
715 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
716 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
b1ae1edf 717 info->control.vif, pktlen, info));
8a63facc
BC		 718 }
719 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
720 flags |= AR5K_TXDESC_CTSENA;
721 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
722 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
b1ae1edf 723 info->control.vif, pktlen, info));
8a63facc
BC		 724 }
725 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
726 ieee80211_get_hdrlen_from_skb(skb), padsize,
727 get_hw_packet_type(skb),
728 (sc->power_level * 2),
729 hw_rate,
730 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
731 cts_rate, duration);
732 if (ret)
733 goto err_unmap;
734
735 memset(mrr_rate, 0, sizeof(mrr_rate));
736 memset(mrr_tries, 0, sizeof(mrr_tries));
737 for (i = 0; i < 3; i++) {
738 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
739 if (!rate)
400ec45a 740 break;
fa1c114f 741
8a63facc
BC		 742 mrr_rate[i] = rate->hw_value;
743 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 744 }
745
8a63facc
BC		 746 ath5k_hw_setup_mrr_tx_desc(ah, ds,
747 mrr_rate[0], mrr_tries[0],
748 mrr_rate[1], mrr_tries[1],
749 mrr_rate[2], mrr_tries[2]);
fa1c114f 750
8a63facc
BC		 751 ds->ds_link = 0;
752 ds->ds_data = bf->skbaddr;
63266a65 753
8a63facc
BC		 754 spin_lock_bh(&txq->lock);
755 list_add_tail(&bf->list, &txq->q);
925e0b06 756 txq->txq_len++;
8a63facc
BC		 757 if (txq->link == NULL) /* is this first packet? */
758 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
759 else /* no, so only link it */
760 *txq->link = bf->daddr;
63266a65 761
8a63facc
BC		 762 txq->link = &ds->ds_link;
763 ath5k_hw_start_tx_dma(ah, txq->qnum);
764 mmiowb();
765 spin_unlock_bh(&txq->lock);
766
767 return 0;
768err_unmap:
aeae4ac9 769 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 770 return ret;
63266a65
BR		 771}
772
8a63facc
BC		 773/*******************\
774* Descriptors setup *
775\*******************/
776
d8ee398d 777static int
aeae4ac9 778ath5k_desc_alloc(struct ath5k_softc *sc)
fa1c114f 779{
8a63facc
BC		 780 struct ath5k_desc *ds;
781 struct ath5k_buf *bf;
782 dma_addr_t da;
783 unsigned int i;
784 int ret;
d8ee398d 785
8a63facc
BC		 786 /* allocate descriptors */
787 sc->desc_len = sizeof(struct ath5k_desc) *
788 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9
FF		 789
790 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
791 &sc->desc_daddr, GFP_KERNEL);
8a63facc
BC		 792 if (sc->desc == NULL) {
793 ATH5K_ERR(sc, "can't allocate descriptors\n");
794 ret = -ENOMEM;
795 goto err;
796 }
797 ds = sc->desc;
798 da = sc->desc_daddr;
799 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
800 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 801
8a63facc
BC		 802 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
803 sizeof(struct ath5k_buf), GFP_KERNEL);
804 if (bf == NULL) {
805 ATH5K_ERR(sc, "can't allocate bufptr\n");
806 ret = -ENOMEM;
807 goto err_free;
808 }
809 sc->bufptr = bf;
fa1c114f 810
8a63facc
BC		 811 INIT_LIST_HEAD(&sc->rxbuf);
812 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
813 bf->desc = ds;
814 bf->daddr = da;
815 list_add_tail(&bf->list, &sc->rxbuf);
816 }
d8ee398d 817
8a63facc
BC		 818 INIT_LIST_HEAD(&sc->txbuf);
819 sc->txbuf_len = ATH_TXBUF;
820 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
821 da += sizeof(*ds)) {
822 bf->desc = ds;
823 bf->daddr = da;
824 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 825 }
826
b1ae1edf
BG		 827 /* beacon buffers */
828 INIT_LIST_HEAD(&sc->bcbuf);
829 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
830 bf->desc = ds;
831 bf->daddr = da;
832 list_add_tail(&bf->list, &sc->bcbuf);
833 }
fa1c114f 834
8a63facc
BC		 835 return 0;
836err_free:
aeae4ac9 837 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 838err:
839 sc->desc = NULL;
840 return ret;
841}
fa1c114f 842
cd2c5486
BR		 843void
844ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
845{
846 BUG_ON(!bf);
847 if (!bf->skb)
848 return;
849 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
850 DMA_TO_DEVICE);
851 dev_kfree_skb_any(bf->skb);
852 bf->skb = NULL;
853 bf->skbaddr = 0;
854 bf->desc->ds_data = 0;
855}
856
857void
858ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
859{
860 struct ath5k_hw *ah = sc->ah;
861 struct ath_common *common = ath5k_hw_common(ah);
862
863 BUG_ON(!bf);
864 if (!bf->skb)
865 return;
866 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
867 DMA_FROM_DEVICE);
868 dev_kfree_skb_any(bf->skb);
869 bf->skb = NULL;
870 bf->skbaddr = 0;
871 bf->desc->ds_data = 0;
872}
873
8a63facc 874static void
aeae4ac9 875ath5k_desc_free(struct ath5k_softc *sc)
8a63facc
BC		 876{
877 struct ath5k_buf *bf;
d8ee398d 878
8a63facc
BC		 879 list_for_each_entry(bf, &sc->txbuf, list)
880 ath5k_txbuf_free_skb(sc, bf);
881 list_for_each_entry(bf, &sc->rxbuf, list)
882 ath5k_rxbuf_free_skb(sc, bf);
b1ae1edf
BG		 883 list_for_each_entry(bf, &sc->bcbuf, list)
884 ath5k_txbuf_free_skb(sc, bf);
d8ee398d 885
8a63facc 886 /* Free memory associated with all descriptors */
aeae4ac9 887 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 888 sc->desc = NULL;
889 sc->desc_daddr = 0;
d8ee398d 890
8a63facc
BC		 891 kfree(sc->bufptr);
892 sc->bufptr = NULL;
fa1c114f
JS		 893}
894
8a63facc
BC		 895
896/**************\
897* Queues setup *
898\**************/
899
900static struct ath5k_txq *
901ath5k_txq_setup(struct ath5k_softc *sc,
902 int qtype, int subtype)
fa1c114f 903{
8a63facc
BC		 904 struct ath5k_hw *ah = sc->ah;
905 struct ath5k_txq *txq;
906 struct ath5k_txq_info qi = {
907 .tqi_subtype = subtype,
de8af455
BR		 908 /* XXX: default values not correct for B and XR channels,
909 * but who cares? */
910 .tqi_aifs = AR5K_TUNE_AIFS,
911 .tqi_cw_min = AR5K_TUNE_CWMIN,
912 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 913 };
914 int qnum;
d8ee398d 915
e30eb4ab 916 /*
8a63facc
BC		 917 * Enable interrupts only for EOL and DESC conditions.
918 * We mark tx descriptors to receive a DESC interrupt
919 * when a tx queue gets deep; otherwise we wait for the
920 * EOL to reap descriptors. Note that this is done to
921 * reduce interrupt load and this only defers reaping
922 * descriptors, never transmitting frames. Aside from
923 * reducing interrupts this also permits more concurrency.
924 * The only potential downside is if the tx queue backs
925 * up in which case the top half of the kernel may backup
926 * due to a lack of tx descriptors.
e30eb4ab 927 */
8a63facc
BC		 928 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
929 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
930 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
931 if (qnum < 0) {
932 /*
933 * NB: don't print a message, this happens
934 * normally on parts with too few tx queues
935 */
936 return ERR_PTR(qnum);
937 }
938 if (qnum >= ARRAY_SIZE(sc->txqs)) {
939 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
940 qnum, ARRAY_SIZE(sc->txqs));
941 ath5k_hw_release_tx_queue(ah, qnum);
942 return ERR_PTR(-EINVAL);
943 }
944 txq = &sc->txqs[qnum];
945 if (!txq->setup) {
946 txq->qnum = qnum;
947 txq->link = NULL;
948 INIT_LIST_HEAD(&txq->q);
949 spin_lock_init(&txq->lock);
950 txq->setup = true;
925e0b06 951 txq->txq_len = 0;
4edd761f 952 txq->txq_poll_mark = false;
923e5b3d 953 txq->txq_stuck = 0;
8a63facc
BC		 954 }
955 return &sc->txqs[qnum];
fa1c114f
JS		 956}
957
8a63facc
BC		 958static int
959ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 960{
8a63facc 961 struct ath5k_txq_info qi = {
de8af455
BR		 962 /* XXX: default values not correct for B and XR channels,
963 * but who cares? */
964 .tqi_aifs = AR5K_TUNE_AIFS,
965 .tqi_cw_min = AR5K_TUNE_CWMIN,
966 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 967 /* NB: for dynamic turbo, don't enable any other interrupts */
968 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
969 };
d8ee398d 970
8a63facc 971 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 972}
973
8a63facc
BC		 974static int
975ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 976{
977 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 978 struct ath5k_txq_info qi;
979 int ret;
fa1c114f 980
8a63facc
BC		 981 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
982 if (ret)
983 goto err;
fa1c114f 984
8a63facc
BC		 985 if (sc->opmode == NL80211_IFTYPE_AP ||
986 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
987 /*
988 * Always burst out beacon and CAB traffic
989 * (aifs = cwmin = cwmax = 0)
990 */
991 qi.tqi_aifs = 0;
992 qi.tqi_cw_min = 0;
993 qi.tqi_cw_max = 0;
994 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
995 /*
996 * Adhoc mode; backoff between 0 and (2 * cw_min).
997 */
998 qi.tqi_aifs = 0;
999 qi.tqi_cw_min = 0;
de8af455 1000 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 1001 }
fa1c114f 1002
8a63facc
BC		 1003 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1004 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1005 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 1006
8a63facc
BC		 1007 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1008 if (ret) {
1009 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1010 "hardware queue!\n", __func__);
1011 goto err;
1012 }
1013 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1014 if (ret)
1015 goto err;
b7266047 1016
8a63facc
BC		 1017 /* reconfigure cabq with ready time to 80% of beacon_interval */
1018 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1019 if (ret)
1020 goto err;
b7266047 1021
8a63facc
BC		 1022 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1023 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1024 if (ret)
1025 goto err;
b7266047 1026
8a63facc
BC		 1027 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1028err:
1029 return ret;
d8ee398d
LR		 1030}
1031
80dac9ee
NK		 1032/**
1033 * ath5k_drain_tx_buffs - Empty tx buffers
1034 *
1035 * @sc The &struct ath5k_softc
1036 *
1037 * Empty tx buffers from all queues in preparation
1038 * of a reset or during shutdown.
1039 *
1040 * NB: this assumes output has been stopped and
1041 * we do not need to block ath5k_tx_tasklet
1042 */
8a63facc 1043static void
80dac9ee 1044ath5k_drain_tx_buffs(struct ath5k_softc *sc)
8a63facc 1045{
80dac9ee 1046 struct ath5k_txq *txq;
8a63facc 1047 struct ath5k_buf *bf, *bf0;
80dac9ee 1048 int i;
b6ea0356 1049
80dac9ee
NK		 1050 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1051 if (sc->txqs[i].setup) {
1052 txq = &sc->txqs[i];
1053 spin_lock_bh(&txq->lock);
1054 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1055 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 1056
80dac9ee 1057 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1058
80dac9ee
NK		 1059 spin_lock_bh(&sc->txbuflock);
1060 list_move_tail(&bf->list, &sc->txbuf);
1061 sc->txbuf_len++;
1062 txq->txq_len--;
1063 spin_unlock_bh(&sc->txbuflock);
8a63facc 1064 }
80dac9ee
NK		 1065 txq->link = NULL;
1066 txq->txq_poll_mark = false;
1067 spin_unlock_bh(&txq->lock);
1068 }
0452d4a5 1069 }
fa1c114f
JS		 1070}
1071
8a63facc
BC		 1072static void
1073ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1074{
8a63facc
BC		 1075 struct ath5k_txq *txq = sc->txqs;
1076 unsigned int i;
2ac2927a 1077
8a63facc
BC		 1078 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1079 if (txq->setup) {
1080 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1081 txq->setup = false;
1082 }
1083}
2ac2927a 1084
2ac2927a 1085
8a63facc
BC		 1086/*************\
1087* RX Handling *
1088\*************/
2ac2927a 1089
8a63facc
BC		 1090/*
1091 * Enable the receive h/w following a reset.
1092 */
fa1c114f 1093static int
8a63facc 1094ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1095{
1096 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1097 struct ath_common *common = ath5k_hw_common(ah);
1098 struct ath5k_buf *bf;
1099 int ret;
fa1c114f 1100
8a63facc 1101 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1102
8a63facc
BC		 1103 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1104 common->cachelsz, common->rx_bufsize);
2f7fe870 1105
8a63facc
BC		 1106 spin_lock_bh(&sc->rxbuflock);
1107 sc->rxlink = NULL;
1108 list_for_each_entry(bf, &sc->rxbuf, list) {
1109 ret = ath5k_rxbuf_setup(sc, bf);
1110 if (ret != 0) {
1111 spin_unlock_bh(&sc->rxbuflock);
1112 goto err;
1113 }
2f7fe870 1114 }
8a63facc
BC		 1115 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1116 ath5k_hw_set_rxdp(ah, bf->daddr);
1117 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1118
8a63facc 1119 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
b1ae1edf 1120 ath5k_mode_setup(sc, NULL); /* set filters, etc. */
8a63facc 1121 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1122
1123 return 0;
8a63facc 1124err:
fa1c114f
JS		 1125 return ret;
1126}
1127
8a63facc 1128/*
80dac9ee
NK		 1129 * Disable the receive logic on PCU (DRU)
1130 * In preparation for a shutdown.
1131 *
1132 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1133 * does.
8a63facc
BC		 1134 */
1135static void
1136ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1137{
8a63facc 1138 struct ath5k_hw *ah = sc->ah;
fa1c114f 1139
8a63facc 1140 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1141 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1142
8a63facc
BC		 1143 ath5k_debug_printrxbuffs(sc, ah);
1144}
fa1c114f 1145
8a63facc
BC		 1146static unsigned int
1147ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1148 struct ath5k_rx_status *rs)
1149{
1150 struct ath5k_hw *ah = sc->ah;
1151 struct ath_common *common = ath5k_hw_common(ah);
1152 struct ieee80211_hdr *hdr = (void *)skb->data;
1153 unsigned int keyix, hlen;
fa1c114f 1154
8a63facc
BC		 1155 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1156 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1157 return RX_FLAG_DECRYPTED;
fa1c114f 1158
8a63facc
BC		 1159 /* Apparently when a default key is used to decrypt the packet
1160 the hw does not set the index used to decrypt. In such cases
1161 get the index from the packet. */
1162 hlen = ieee80211_hdrlen(hdr->frame_control);
1163 if (ieee80211_has_protected(hdr->frame_control) &&
1164 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1165 skb->len >= hlen + 4) {
1166 keyix = skb->data[hlen + 3] >> 6;
1167
1168 if (test_bit(keyix, common->keymap))
1169 return RX_FLAG_DECRYPTED;
1170 }
fa1c114f
JS		 1171
1172 return 0;
fa1c114f
JS		 1173}
1174
8a63facc 1175
fa1c114f 1176static void
8a63facc
BC		 1177ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1178 struct ieee80211_rx_status *rxs)
fa1c114f 1179{
8a63facc
BC		 1180 struct ath_common *common = ath5k_hw_common(sc->ah);
1181 u64 tsf, bc_tstamp;
1182 u32 hw_tu;
1183 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1184
8a63facc
BC		 1185 if (ieee80211_is_beacon(mgmt->frame_control) &&
1186 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1187 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1188 /*
1189 * Received an IBSS beacon with the same BSSID. Hardware *must*
1190 * have updated the local TSF. We have to work around various
1191 * hardware bugs, though...
1192 */
1193 tsf = ath5k_hw_get_tsf64(sc->ah);
1194 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1195 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1196
8a63facc
BC		 1197 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1198 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1199 (unsigned long long)bc_tstamp,
1200 (unsigned long long)rxs->mactime,
1201 (unsigned long long)(rxs->mactime - bc_tstamp),
1202 (unsigned long long)tsf);
fa1c114f 1203
8a63facc
BC		 1204 /*
1205 * Sometimes the HW will give us a wrong tstamp in the rx
1206 * status, causing the timestamp extension to go wrong.
1207 * (This seems to happen especially with beacon frames bigger
1208 * than 78 byte (incl. FCS))
1209 * But we know that the receive timestamp must be later than the
1210 * timestamp of the beacon since HW must have synced to that.
1211 *
1212 * NOTE: here we assume mactime to be after the frame was
1213 * received, not like mac80211 which defines it at the start.
1214 */
1215 if (bc_tstamp > rxs->mactime) {
1216 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1217 "fixing mactime from %llx to %llx\n",
1218 (unsigned long long)rxs->mactime,
1219 (unsigned long long)tsf);
1220 rxs->mactime = tsf;
1221 }
fa1c114f 1222
8a63facc
BC		 1223 /*
1224 * Local TSF might have moved higher than our beacon timers,
1225 * in that case we have to update them to continue sending
1226 * beacons. This also takes care of synchronizing beacon sending
1227 * times with other stations.
1228 */
1229 if (hw_tu >= sc->nexttbtt)
1230 ath5k_beacon_update_timers(sc, bc_tstamp);
7f896126
BR		 1231
1232 /* Check if the beacon timers are still correct, because a TSF
1233 * update might have created a window between them - for a
1234 * longer description see the comment of this function: */
1235 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1236 ath5k_beacon_update_timers(sc, bc_tstamp);
1237 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1238 "fixed beacon timers after beacon receive\n");
1239 }
8a63facc
BC		 1240 }
1241}
fa1c114f 1242
8a63facc
BC		 1243static void
1244ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1245{
1246 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1247 struct ath5k_hw *ah = sc->ah;
1248 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1249
8a63facc
BC		 1250 /* only beacons from our BSSID */
1251 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1252 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1253 return;
fa1c114f 1254
eef39bef 1255 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1256
8a63facc
BC		 1257 /* in IBSS mode we should keep RSSI statistics per neighbour */
1258 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1259}
fa1c114f 1260
8a63facc
BC		 1261/*
1262 * Compute padding position. skb must contain an IEEE 802.11 frame
1263 */
1264static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1265{
8a63facc
BC		 1266 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1267 __le16 frame_control = hdr->frame_control;
1268 int padpos = 24;
fa1c114f 1269
8a63facc
BC		 1270 if (ieee80211_has_a4(frame_control)) {
1271 padpos += ETH_ALEN;
fa1c114f 1272 }
8a63facc
BC		 1273 if (ieee80211_is_data_qos(frame_control)) {
1274 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1275 }
8a63facc
BC		 1276
1277 return padpos;
fa1c114f
JS		 1278}
1279
8a63facc
BC		 1280/*
1281 * This function expects an 802.11 frame and returns the number of
1282 * bytes added, or -1 if we don't have enough header room.
1283 */
1284static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1285{
8a63facc
BC		 1286 int padpos = ath5k_common_padpos(skb);
1287 int padsize = padpos & 3;
fa1c114f 1288
8a63facc 1289 if (padsize && skb->len>padpos) {
fa1c114f 1290
8a63facc
BC		 1291 if (skb_headroom(skb) < padsize)
1292 return -1;
fa1c114f 1293
8a63facc
BC		 1294 skb_push(skb, padsize);
1295 memmove(skb->data, skb->data+padsize, padpos);
1296 return padsize;
1297 }
a951ae21 1298
8a63facc
BC		 1299 return 0;
1300}
fa1c114f 1301
8a63facc
BC		 1302/*
1303 * The MAC header is padded to have 32-bit boundary if the
1304 * packet payload is non-zero. The general calculation for
1305 * padsize would take into account odd header lengths:
1306 * padsize = 4 - (hdrlen & 3); however, since only
1307 * even-length headers are used, padding can only be 0 or 2
1308 * bytes and we can optimize this a bit. We must not try to
1309 * remove padding from short control frames that do not have a
1310 * payload.
1311 *
1312 * This function expects an 802.11 frame and returns the number of
1313 * bytes removed.
1314 */
1315static int ath5k_remove_padding(struct sk_buff *skb)
1316{
1317 int padpos = ath5k_common_padpos(skb);
1318 int padsize = padpos & 3;
6d91e1d8 1319
8a63facc
BC		 1320 if (padsize && skb->len>=padpos+padsize) {
1321 memmove(skb->data + padsize, skb->data, padpos);
1322 skb_pull(skb, padsize);
1323 return padsize;
fa1c114f 1324 }
a951ae21 1325
8a63facc 1326 return 0;
fa1c114f
JS		 1327}
1328
1329static void
8a63facc
BC		 1330ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1331 struct ath5k_rx_status *rs)
fa1c114f 1332{
8a63facc
BC		 1333 struct ieee80211_rx_status *rxs;
1334
1335 ath5k_remove_padding(skb);
1336
1337 rxs = IEEE80211_SKB_RXCB(skb);
1338
1339 rxs->flag = 0;
1340 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1341 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1342
1343 /*
8a63facc
BC		 1344 * always extend the mac timestamp, since this information is
1345 * also needed for proper IBSS merging.
1346 *
1347 * XXX: it might be too late to do it here, since rs_tstamp is
1348 * 15bit only. that means TSF extension has to be done within
1349 * 32768usec (about 32ms). it might be necessary to move this to
1350 * the interrupt handler, like it is done in madwifi.
1351 *
1352 * Unfortunately we don't know when the hardware takes the rx
1353 * timestamp (beginning of phy frame, data frame, end of rx?).
1354 * The only thing we know is that it is hardware specific...
1355 * On AR5213 it seems the rx timestamp is at the end of the
1356 * frame, but i'm not sure.
1357 *
1358 * NOTE: mac80211 defines mactime at the beginning of the first
1359 * data symbol. Since we don't have any time references it's
1360 * impossible to comply to that. This affects IBSS merge only
1361 * right now, so it's not too bad...
fa1c114f 1362 */
8a63facc 1363 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
6ebacbb7 1364 rxs->flag |= RX_FLAG_MACTIME_MPDU;
fa1c114f 1365
8a63facc 1366 rxs->freq = sc->curchan->center_freq;
930a7622 1367 rxs->band = sc->curchan->band;
fa1c114f 1368
8a63facc 1369 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1370
8a63facc 1371 rxs->antenna = rs->rs_antenna;
fa1c114f 1372
8a63facc
BC		 1373 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1374 sc->stats.antenna_rx[rs->rs_antenna]++;
1375 else
1376 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1377
8a63facc
BC		 1378 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1379 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1380
8a63facc 1381 if (rxs->rate_idx >= 0 && rs->rs_rate ==
930a7622 1382 sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
8a63facc 1383 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1384
0e472252 1385 trace_ath5k_rx(sc, skb);
fa1c114f 1386
8a63facc 1387 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1388
8a63facc
BC		 1389 /* check beacons in IBSS mode */
1390 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1391 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1392
8a63facc
BC		 1393 ieee80211_rx(sc->hw, skb);
1394}
fa1c114f 1395
8a63facc
BC		 1396/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1397 *
1398 * Check if we want to further process this frame or not. Also update
1399 * statistics. Return true if we want this frame, false if not.
fa1c114f 1400 */
8a63facc
BC		 1401static bool
1402ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1403{
8a63facc 1404 sc->stats.rx_all_count++;
b72acddb 1405 sc->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1406
8a63facc
BC		 1407 if (unlikely(rs->rs_status)) {
1408 if (rs->rs_status & AR5K_RXERR_CRC)
1409 sc->stats.rxerr_crc++;
1410 if (rs->rs_status & AR5K_RXERR_FIFO)
1411 sc->stats.rxerr_fifo++;
1412 if (rs->rs_status & AR5K_RXERR_PHY) {
1413 sc->stats.rxerr_phy++;
1414 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1415 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1416 return false;
1417 }
1418 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1419 /*
1420 * Decrypt error. If the error occurred
1421 * because there was no hardware key, then
1422 * let the frame through so the upper layers
1423 * can process it. This is necessary for 5210
1424 * parts which have no way to setup a ``clear''
1425 * key cache entry.
1426 *
1427 * XXX do key cache faulting
1428 */
1429 sc->stats.rxerr_decrypt++;
1430 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1431 !(rs->rs_status & AR5K_RXERR_CRC))
1432 return true;
1433 }
1434 if (rs->rs_status & AR5K_RXERR_MIC) {
1435 sc->stats.rxerr_mic++;
1436 return true;
fa1c114f 1437 }
fa1c114f 1438
8a63facc
BC		 1439 /* reject any frames with non-crypto errors */
1440 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1441 return false;
1442 }
fa1c114f 1443
8a63facc
BC		 1444 if (unlikely(rs->rs_more)) {
1445 sc->stats.rxerr_jumbo++;
1446 return false;
1447 }
1448 return true;
fa1c114f
JS		 1449}
1450
fa1c114f 1451static void
8a63facc 1452ath5k_tasklet_rx(unsigned long data)
fa1c114f 1453{
8a63facc
BC		 1454 struct ath5k_rx_status rs = {};
1455 struct sk_buff *skb, *next_skb;
1456 dma_addr_t next_skb_addr;
1457 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1458 struct ath5k_hw *ah = sc->ah;
1459 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1460 struct ath5k_buf *bf;
1461 struct ath5k_desc *ds;
1462 int ret;
fa1c114f 1463
8a63facc
BC		 1464 spin_lock(&sc->rxbuflock);
1465 if (list_empty(&sc->rxbuf)) {
1466 ATH5K_WARN(sc, "empty rx buf pool\n");
1467 goto unlock;
1468 }
1469 do {
1470 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1471 BUG_ON(bf->skb == NULL);
1472 skb = bf->skb;
1473 ds = bf->desc;
fa1c114f 1474
8a63facc
BC		 1475 /* bail if HW is still using self-linked descriptor */
1476 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1477 break;
fa1c114f 1478
8a63facc
BC		 1479 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1480 if (unlikely(ret == -EINPROGRESS))
1481 break;
1482 else if (unlikely(ret)) {
1483 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1484 sc->stats.rxerr_proc++;
1485 break;
1486 }
fa1c114f 1487
8a63facc
BC		 1488 if (ath5k_receive_frame_ok(sc, &rs)) {
1489 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1490
8a63facc
BC		 1491 /*
1492 * If we can't replace bf->skb with a new skb under
1493 * memory pressure, just skip this packet
1494 */
1495 if (!next_skb)
1496 goto next;
036cd1ec 1497
aeae4ac9 1498 dma_unmap_single(sc->dev, bf->skbaddr,
8a63facc 1499 common->rx_bufsize,
aeae4ac9 1500 DMA_FROM_DEVICE);
036cd1ec 1501
8a63facc 1502 skb_put(skb, rs.rs_datalen);
6ba81c2c 1503
8a63facc 1504 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1505
8a63facc
BC		 1506 bf->skb = next_skb;
1507 bf->skbaddr = next_skb_addr;
036cd1ec 1508 }
8a63facc
BC		 1509next:
1510 list_move_tail(&bf->list, &sc->rxbuf);
1511 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1512unlock:
1513 spin_unlock(&sc->rxbuflock);
036cd1ec
BR		 1514}
1515
b4ea449d 1516
8a63facc
BC		 1517/*************\
1518* TX Handling *
1519\*************/
b4ea449d 1520
7bb45683 1521void
cd2c5486
BR		 1522ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1523 struct ath5k_txq *txq)
8a63facc
BC		 1524{
1525 struct ath5k_softc *sc = hw->priv;
1526 struct ath5k_buf *bf;
1527 unsigned long flags;
1528 int padsize;
b4ea449d 1529
0e472252 1530 trace_ath5k_tx(sc, skb, txq);
b4ea449d 1531
8a63facc
BC		 1532 /*
1533 * The hardware expects the header padded to 4 byte boundaries.
1534 * If this is not the case, we add the padding after the header.
1535 */
1536 padsize = ath5k_add_padding(skb);
1537 if (padsize < 0) {
1538 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1539 " headroom to pad");
1540 goto drop_packet;
1541 }
8127fbdc 1542
925e0b06
BR		 1543 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1544 ieee80211_stop_queue(hw, txq->qnum);
1545
8a63facc
BC		 1546 spin_lock_irqsave(&sc->txbuflock, flags);
1547 if (list_empty(&sc->txbuf)) {
1548 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1549 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1550 ieee80211_stop_queues(hw);
8a63facc 1551 goto drop_packet;
8127fbdc 1552 }
8a63facc
BC		 1553 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1554 list_del(&bf->list);
1555 sc->txbuf_len--;
1556 if (list_empty(&sc->txbuf))
1557 ieee80211_stop_queues(hw);
1558 spin_unlock_irqrestore(&sc->txbuflock, flags);
1559
1560 bf->skb = skb;
1561
1562 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1563 bf->skb = NULL;
1564 spin_lock_irqsave(&sc->txbuflock, flags);
1565 list_add_tail(&bf->list, &sc->txbuf);
1566 sc->txbuf_len++;
1567 spin_unlock_irqrestore(&sc->txbuflock, flags);
1568 goto drop_packet;
8127fbdc 1569 }
7bb45683 1570 return;
8127fbdc 1571
8a63facc
BC		 1572drop_packet:
1573 dev_kfree_skb_any(skb);
8127fbdc
BP		 1574}
1575
1440401e
BR		 1576static void
1577ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
0e472252 1578 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1440401e
BR		 1579{
1580 struct ieee80211_tx_info *info;
1581 int i;
1582
1583 sc->stats.tx_all_count++;
b72acddb 1584 sc->stats.tx_bytes_count += skb->len;
1440401e
BR		 1585 info = IEEE80211_SKB_CB(skb);
1586
1587 ieee80211_tx_info_clear_status(info);
1588 for (i = 0; i < 4; i++) {
1589 struct ieee80211_tx_rate *r =
1590 &info->status.rates[i];
1591
1592 if (ts->ts_rate[i]) {
1593 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1594 r->count = ts->ts_retry[i];
1595 } else {
1596 r->idx = -1;
1597 r->count = 0;
1598 }
1599 }
1600
1601 /* count the successful attempt as well */
1602 info->status.rates[ts->ts_final_idx].count++;
1603
1604 if (unlikely(ts->ts_status)) {
1605 sc->stats.ack_fail++;
1606 if (ts->ts_status & AR5K_TXERR_FILT) {
1607 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1608 sc->stats.txerr_filt++;
1609 }
1610 if (ts->ts_status & AR5K_TXERR_XRETRY)
1611 sc->stats.txerr_retry++;
1612 if (ts->ts_status & AR5K_TXERR_FIFO)
1613 sc->stats.txerr_fifo++;
1614 } else {
1615 info->flags |= IEEE80211_TX_STAT_ACK;
1616 info->status.ack_signal = ts->ts_rssi;
1617 }
1618
1619 /*
1620 * Remove MAC header padding before giving the frame
1621 * back to mac80211.
1622 */
1623 ath5k_remove_padding(skb);
1624
1625 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1626 sc->stats.antenna_tx[ts->ts_antenna]++;
1627 else
1628 sc->stats.antenna_tx[0]++; /* invalid */
1629
0e472252 1630 trace_ath5k_tx_complete(sc, skb, txq, ts);
1440401e
BR		 1631 ieee80211_tx_status(sc->hw, skb);
1632}
8a63facc
BC		 1633
1634static void
1635ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1636{
8a63facc
BC		 1637 struct ath5k_tx_status ts = {};
1638 struct ath5k_buf *bf, *bf0;
1639 struct ath5k_desc *ds;
1640 struct sk_buff *skb;
1440401e 1641 int ret;
8127fbdc 1642
8a63facc
BC		 1643 spin_lock(&txq->lock);
1644 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1645
1646 txq->txq_poll_mark = false;
1647
1648 /* skb might already have been processed last time. */
1649 if (bf->skb != NULL) {
1650 ds = bf->desc;
1651
1652 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1653 if (unlikely(ret == -EINPROGRESS))
1654 break;
1655 else if (unlikely(ret)) {
1656 ATH5K_ERR(sc,
1657 "error %d while processing "
1658 "queue %u\n", ret, txq->qnum);
1659 break;
1660 }
1661
1662 skb = bf->skb;
1663 bf->skb = NULL;
aeae4ac9
FF		 1664
1665 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1666 DMA_TO_DEVICE);
0e472252 1667 ath5k_tx_frame_completed(sc, skb, txq, &ts);
23413296 1668 }
8127fbdc 1669
8a63facc
BC		 1670 /*
1671 * It's possible that the hardware can say the buffer is
1672 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1673 * host memory and moved on.
1674 * Always keep the last descriptor to avoid HW races...
8a63facc 1675 */
23413296
BR		 1676 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1677 spin_lock(&sc->txbuflock);
1678 list_move_tail(&bf->list, &sc->txbuf);
1679 sc->txbuf_len++;
1680 txq->txq_len--;
1681 spin_unlock(&sc->txbuflock);
8a63facc 1682 }
fa1c114f 1683 }
fa1c114f 1684 spin_unlock(&txq->lock);
4198a8d0 1685 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
925e0b06 1686 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1687}
1688
1689static void
1690ath5k_tasklet_tx(unsigned long data)
1691{
8784d2ee 1692 int i;
fa1c114f
JS		 1693 struct ath5k_softc *sc = (void *)data;
1694
8784d2ee
BC		 1695 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1696 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1697 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 1698}
1699
1700
fa1c114f
JS		 1701/*****************\
1702* Beacon handling *
1703\*****************/
1704
1705/*
1706 * Setup the beacon frame for transmit.
1707 */
1708static int
e039fa4a 1709ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1710{
1711 struct sk_buff *skb = bf->skb;
a888d52d 1712 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1713 struct ath5k_hw *ah = sc->ah;
1714 struct ath5k_desc *ds;
2bed03eb
NK		 1715 int ret = 0;
1716 u8 antenna;
fa1c114f 1717 u32 flags;
8127fbdc 1718 const int padsize = 0;
fa1c114f 1719
aeae4ac9
FF		 1720 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1721 DMA_TO_DEVICE);
fa1c114f
JS		 1722 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1723 "skbaddr %llx\n", skb, skb->data, skb->len,
1724 (unsigned long long)bf->skbaddr);
aeae4ac9
FF		 1725
1726 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
fa1c114f
JS		 1727 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1728 return -EIO;
1729 }
1730
1731 ds = bf->desc;
2bed03eb 1732 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1733
1734 flags = AR5K_TXDESC_NOACK;
05c914fe 1735 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1736 ds->ds_link = bf->daddr; /* self-linked */
1737 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1738 } else
fa1c114f 1739 ds->ds_link = 0;
2bed03eb
NK		 1740
1741 /*
1742 * If we use multiple antennas on AP and use
1743 * the Sectored AP scenario, switch antenna every
1744 * 4 beacons to make sure everybody hears our AP.
1745 * When a client tries to associate, hw will keep
1746 * track of the tx antenna to be used for this client
1747 * automaticaly, based on ACKed packets.
1748 *
1749 * Note: AP still listens and transmits RTS on the
1750 * default antenna which is supposed to be an omni.
1751 *
1752 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1753 * multiple antennas (1 omni -- the default -- and 14
1754 * sectors), so if we choose to actually support this
1755 * mode, we need to allow the user to set how many antennas
1756 * we have and tweak the code below to send beacons
1757 * on all of them.
2bed03eb
NK		 1758 */
1759 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1760 antenna = sc->bsent & 4 ? 2 : 1;
1761
fa1c114f 1762
8f655dde
NK		 1763 /* FIXME: If we are in g mode and rate is a CCK rate
1764 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1765 * from tx power (value is in dB units already) */
fa1c114f 1766 ds->ds_data = bf->skbaddr;
281c56dd 1767 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1768 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1769 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1770 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1771 1, AR5K_TXKEYIX_INVALID,
400ec45a 1772 antenna, flags, 0, 0);
fa1c114f
JS		 1773 if (ret)
1774 goto err_unmap;
1775
1776 return 0;
1777err_unmap:
aeae4ac9 1778 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1779 return ret;
1780}
1781
8a63facc
BC		 1782/*
1783 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1784 * this is called only once at config_bss time, for AP we do it every
1785 * SWBA interrupt so that the TIM will reflect buffered frames.
1786 *
1787 * Called with the beacon lock.
1788 */
cd2c5486 1789int
8a63facc
BC		 1790ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1791{
1792 int ret;
1793 struct ath5k_softc *sc = hw->priv;
b1ae1edf 1794 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1795 struct sk_buff *skb;
1796
1797 if (WARN_ON(!vif)) {
1798 ret = -EINVAL;
1799 goto out;
1800 }
1801
1802 skb = ieee80211_beacon_get(hw, vif);
1803
1804 if (!skb) {
1805 ret = -ENOMEM;
1806 goto out;
1807 }
1808
b1ae1edf
BG		 1809 ath5k_txbuf_free_skb(sc, avf->bbuf);
1810 avf->bbuf->skb = skb;
1811 ret = ath5k_beacon_setup(sc, avf->bbuf);
8a63facc 1812 if (ret)
b1ae1edf 1813 avf->bbuf->skb = NULL;
8a63facc
BC		 1814out:
1815 return ret;
1816}
1817
fa1c114f
JS		 1818/*
1819 * Transmit a beacon frame at SWBA. Dynamic updates to the
1820 * frame contents are done as needed and the slot time is
1821 * also adjusted based on current state.
1822 *
5faaff74
BC		 1823 * This is called from software irq context (beacontq tasklets)
1824 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1825 */
1826static void
1827ath5k_beacon_send(struct ath5k_softc *sc)
1828{
fa1c114f 1829 struct ath5k_hw *ah = sc->ah;
b1ae1edf
BG		 1830 struct ieee80211_vif *vif;
1831 struct ath5k_vif *avf;
1832 struct ath5k_buf *bf;
cec8db23 1833 struct sk_buff *skb;
fa1c114f 1834
be9b7259 1835 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1836
fa1c114f
JS		 1837 /*
1838 * Check if the previous beacon has gone out. If
a180a130 1839 * not, don't don't try to post another: skip this
fa1c114f
JS		 1840 * period and wait for the next. Missed beacons
1841 * indicate a problem and should not occur. If we
1842 * miss too many consecutive beacons reset the device.
1843 */
1844 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1845 sc->bmisscount++;
be9b7259 1846 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1847 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1848 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1849 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1850 "stuck beacon time (%u missed)\n",
1851 sc->bmisscount);
8d67a031
BR		 1852 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1853 "stuck beacon, resetting\n");
5faaff74 1854 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1855 }
1856 return;
1857 }
1858 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1859 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1860 "resume beacon xmit after %u misses\n",
1861 sc->bmisscount);
1862 sc->bmisscount = 0;
1863 }
1864
b93996cf
JC		 1865 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
1866 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
b1ae1edf
BG		 1867 u64 tsf = ath5k_hw_get_tsf64(ah);
1868 u32 tsftu = TSF_TO_TU(tsf);
1869 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1870 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1871 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1872 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1873 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1874 } else /* only one interface */
1875 vif = sc->bslot[0];
1876
1877 if (!vif)
1878 return;
1879
1880 avf = (void *)vif->drv_priv;
1881 bf = avf->bbuf;
1882 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1883 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1884 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1885 return;
1886 }
1887
fa1c114f
JS		 1888 /*
1889 * Stop any current dma and put the new frame on the queue.
1890 * This should never fail since we check above that no frames
1891 * are still pending on the queue.
1892 */
14fae2d4 1893 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
428cbd4f 1894 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1895 /* NB: hw still stops DMA, so proceed */
1896 }
fa1c114f 1897
d82b577b
JC		 1898 /* refresh the beacon for AP or MESH mode */
1899 if (sc->opmode == NL80211_IFTYPE_AP ||
1900 sc->opmode == NL80211_IFTYPE_MESH_POINT)
b1ae1edf 1901 ath5k_beacon_update(sc->hw, vif);
1071db86 1902
0e472252
BC		 1903 trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]);
1904
c6e387a2
NK		 1905 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1906 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1907 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1908 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1909
b1ae1edf 1910 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1911 while (skb) {
1912 ath5k_tx_queue(sc->hw, skb, sc->cabq);
b1ae1edf 1913 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1914 }
1915
fa1c114f
JS		 1916 sc->bsent++;
1917}
1918
9804b98d
BR		 1919/**
1920 * ath5k_beacon_update_timers - update beacon timers
1921 *
1922 * @sc: struct ath5k_softc pointer we are operating on
1923 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1924 * beacon timer update based on the current HW TSF.
1925 *
1926 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1927 * of a received beacon or the current local hardware TSF and write it to the
1928 * beacon timer registers.
1929 *
1930 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1931 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1932 * when we otherwise know we have to update the timers, but we keep it in this
1933 * function to have it all together in one place.
1934 */
cd2c5486 1935void
9804b98d 1936ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1937{
1938 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1939 u32 nexttbtt, intval, hw_tu, bc_tu;
1940 u64 hw_tsf;
fa1c114f
JS		 1941
1942 intval = sc->bintval & AR5K_BEACON_PERIOD;
b1ae1edf
BG		 1943 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1944 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1945 if (intval < 15)
1946 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1947 intval);
1948 }
fa1c114f
JS		 1949 if (WARN_ON(!intval))
1950 return;
1951
9804b98d
BR		 1952 /* beacon TSF converted to TU */
1953 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1954
9804b98d
BR		 1955 /* current TSF converted to TU */
1956 hw_tsf = ath5k_hw_get_tsf64(ah);
1957 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1958
11f21df3
BR		 1959#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1960 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1961 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1962 * configuration we need to make sure it is bigger than that. */
1963
9804b98d
BR		 1964 if (bc_tsf == -1) {
1965 /*
1966 * no beacons received, called internally.
1967 * just need to refresh timers based on HW TSF.
1968 */
1969 nexttbtt = roundup(hw_tu + FUDGE, intval);
1970 } else if (bc_tsf == 0) {
1971 /*
1972 * no beacon received, probably called by ath5k_reset_tsf().
1973 * reset TSF to start with 0.
1974 */
1975 nexttbtt = intval;
1976 intval |= AR5K_BEACON_RESET_TSF;
1977 } else if (bc_tsf > hw_tsf) {
1978 /*
1979 * beacon received, SW merge happend but HW TSF not yet updated.
1980 * not possible to reconfigure timers yet, but next time we
1981 * receive a beacon with the same BSSID, the hardware will
1982 * automatically update the TSF and then we need to reconfigure
1983 * the timers.
1984 */
1985 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1986 "need to wait for HW TSF sync\n");
1987 return;
1988 } else {
1989 /*
1990 * most important case for beacon synchronization between STA.
1991 *
1992 * beacon received and HW TSF has been already updated by HW.
1993 * update next TBTT based on the TSF of the beacon, but make
1994 * sure it is ahead of our local TSF timer.
1995 */
1996 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
1997 }
1998#undef FUDGE
fa1c114f 1999
036cd1ec
BR		 2000 sc->nexttbtt = nexttbtt;
2001
fa1c114f 2002 intval |= AR5K_BEACON_ENA;
fa1c114f 2003 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2004
2005 /*
2006 * debugging output last in order to preserve the time critical aspect
2007 * of this function
2008 */
2009 if (bc_tsf == -1)
2010 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2011 "reconfigured timers based on HW TSF\n");
2012 else if (bc_tsf == 0)
2013 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2014 "reset HW TSF and timers\n");
2015 else
2016 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2017 "updated timers based on beacon TSF\n");
2018
2019 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2020 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2021 (unsigned long long) bc_tsf,
2022 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2023 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2024 intval & AR5K_BEACON_PERIOD,
2025 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2026 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2027}
2028
036cd1ec
BR		 2029/**
2030 * ath5k_beacon_config - Configure the beacon queues and interrupts
2031 *
2032 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2033 *
036cd1ec 2034 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2035 * interrupts to detect TSF updates only.
fa1c114f 2036 */
cd2c5486 2037void
fa1c114f
JS		 2038ath5k_beacon_config(struct ath5k_softc *sc)
2039{
2040 struct ath5k_hw *ah = sc->ah;
b5f03956 2041 unsigned long flags;
fa1c114f 2042
21800491 2043 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2044 sc->bmisscount = 0;
dc1968e7 2045 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2046
21800491 2047 if (sc->enable_beacon) {
fa1c114f 2048 /*
036cd1ec
BR		 2049 * In IBSS mode we use a self-linked tx descriptor and let the
2050 * hardware send the beacons automatically. We have to load it
fa1c114f 2051 * only once here.
036cd1ec 2052 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2053 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2054 */
2055 ath5k_beaconq_config(sc);
fa1c114f 2056
036cd1ec
BR		 2057 sc->imask |= AR5K_INT_SWBA;
2058
da966bca 2059 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2060 if (ath5k_hw_hasveol(ah))
da966bca 2061 ath5k_beacon_send(sc);
da966bca
JS		 2062 } else
2063 ath5k_beacon_update_timers(sc, -1);
21800491 2064 } else {
14fae2d4 2065 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
fa1c114f 2066 }
fa1c114f 2067
c6e387a2 2068 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2069 mmiowb();
2070 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2071}
2072
428cbd4f
NK		 2073static void ath5k_tasklet_beacon(unsigned long data)
2074{
2075 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2076
2077 /*
2078 * Software beacon alert--time to send a beacon.
2079 *
2080 * In IBSS mode we use this interrupt just to
2081 * keep track of the next TBTT (target beacon
2082 * transmission time) in order to detect wether
2083 * automatic TSF updates happened.
2084 */
2085 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2086 /* XXX: only if VEOL suppported */
2087 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2088 sc->nexttbtt += sc->bintval;
2089 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2090 "SWBA nexttbtt: %x hw_tu: %x "
2091 "TSF: %llx\n",
2092 sc->nexttbtt,
2093 TSF_TO_TU(tsf),
2094 (unsigned long long) tsf);
2095 } else {
2096 spin_lock(&sc->block);
2097 ath5k_beacon_send(sc);
2098 spin_unlock(&sc->block);
2099 }
2100}
2101
fa1c114f
JS		 2102
2103/********************\
2104* Interrupt handling *
2105\********************/
2106
6a8a3f6b
BR		 2107static void
2108ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2109{
2111ac0d
BR		 2110 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2111 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2112 /* run ANI only when full calibration is not active */
2113 ah->ah_cal_next_ani = jiffies +
2114 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2115 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2116
2117 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2118 ah->ah_cal_next_full = jiffies +
2119 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2120 tasklet_schedule(&ah->ah_sc->calib);
2121 }
2122 /* we could use SWI to generate enough interrupts to meet our
2123 * calibration interval requirements, if necessary:
2124 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2125}
2126
132b1c3e 2127irqreturn_t
fa1c114f
JS		 2128ath5k_intr(int irq, void *dev_id)
2129{
2130 struct ath5k_softc *sc = dev_id;
2131 struct ath5k_hw *ah = sc->ah;
2132 enum ath5k_int status;
2133 unsigned int counter = 1000;
2134
2135 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
4cebb34c
FF		 2136 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2137 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2138 return IRQ_NONE;
2139
2140 do {
fa1c114f
JS		 2141 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2142 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2143 status, sc->imask);
fa1c114f
JS		 2144 if (unlikely(status & AR5K_INT_FATAL)) {
2145 /*
2146 * Fatal errors are unrecoverable.
2147 * Typically these are caused by DMA errors.
2148 */
8d67a031
BR		 2149 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2150 "fatal int, resetting\n");
5faaff74 2151 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2152 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2153 /*
2154 * Receive buffers are full. Either the bus is busy or
2155 * the CPU is not fast enough to process all received
2156 * frames.
2157 * Older chipsets need a reset to come out of this
2158 * condition, but we treat it as RX for newer chips.
2159 * We don't know exactly which versions need a reset -
2160 * this guess is copied from the HAL.
2161 */
2162 sc->stats.rxorn_intr++;
8d67a031
BR		 2163 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2164 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2165 "rx overrun, resetting\n");
5faaff74 2166 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2167 }
87d77c4e
BR		 2168 else
2169 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2170 } else {
2171 if (status & AR5K_INT_SWBA) {
56d2ac76 2172 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2173 }
2174 if (status & AR5K_INT_RXEOL) {
2175 /*
2176 * NB: the hardware should re-read the link when
2177 * RXE bit is written, but it doesn't work at
2178 * least on older hardware revs.
2179 */
b3f194e5 2180 sc->stats.rxeol_intr++;
fa1c114f
JS		 2181 }
2182 if (status & AR5K_INT_TXURN) {
2183 /* bump tx trigger level */
2184 ath5k_hw_update_tx_triglevel(ah, true);
2185 }
4c674c60 2186 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2187 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2188 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2189 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2190 tasklet_schedule(&sc->txtq);
2191 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2192 /* TODO */
fa1c114f
JS		 2193 }
2194 if (status & AR5K_INT_MIB) {
2111ac0d 2195 sc->stats.mib_intr++;
495391d7 2196 ath5k_hw_update_mib_counters(ah);
2111ac0d 2197 ath5k_ani_mib_intr(ah);
fa1c114f 2198 }
e6a3b616 2199 if (status & AR5K_INT_GPIO)
e6a3b616 2200 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2201
fa1c114f 2202 }
4cebb34c
FF		 2203
2204 if (ath5k_get_bus_type(ah) == ATH_AHB)
2205 break;
2206
2516baa6 2207 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2208
2209 if (unlikely(!counter))
2210 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2211
6a8a3f6b 2212 ath5k_intr_calibration_poll(ah);
6e220662 2213
fa1c114f
JS		 2214 return IRQ_HANDLED;
2215}
2216
fa1c114f
JS		 2217/*
2218 * Periodically recalibrate the PHY to account
2219 * for temperature/environment changes.
2220 */
2221static void
6e220662 2222ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2223{
2224 struct ath5k_softc *sc = (void *)data;
2225 struct ath5k_hw *ah = sc->ah;
2226
6e220662 2227 /* Only full calibration for now */
e65e1d77 2228 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2229
fa1c114f 2230 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2231 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2232 sc->curchan->hw_value);
fa1c114f 2233
6f3b414a 2234 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2235 /*
2236 * Rfgain is out of bounds, reset the chip
2237 * to load new gain values.
2238 */
2239 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2240 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2241 }
2242 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2243 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2244 ieee80211_frequency_to_channel(
2245 sc->curchan->center_freq));
fa1c114f 2246
0e8e02dd 2247 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2248 * doesn't.
2249 * TODO: We should stop TX here, so that it doesn't interfere.
2250 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2251 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2252 ah->ah_cal_next_nf = jiffies +
2253 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2254 ath5k_hw_update_noise_floor(ah);
afe86286 2255 }
6e220662 2256
e65e1d77 2257 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2258}
2259
2260
2111ac0d
BR		 2261static void
2262ath5k_tasklet_ani(unsigned long data)
2263{
2264 struct ath5k_softc *sc = (void *)data;
2265 struct ath5k_hw *ah = sc->ah;
2266
2267 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2268 ath5k_ani_calibration(ah);
2269 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2270}
2271
2272
4edd761f
BR		 2273static void
2274ath5k_tx_complete_poll_work(struct work_struct *work)
2275{
2276 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2277 tx_complete_work.work);
2278 struct ath5k_txq *txq;
2279 int i;
2280 bool needreset = false;
2281
599b13ad
BC		 2282 mutex_lock(&sc->lock);
2283
4edd761f
BR		 2284 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2285 if (sc->txqs[i].setup) {
2286 txq = &sc->txqs[i];
2287 spin_lock_bh(&txq->lock);
23413296 2288 if (txq->txq_len > 1) {
4edd761f
BR		 2289 if (txq->txq_poll_mark) {
2290 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2291 "TX queue stuck %d\n",
2292 txq->qnum);
2293 needreset = true;
923e5b3d 2294 txq->txq_stuck++;
4edd761f
BR		 2295 spin_unlock_bh(&txq->lock);
2296 break;
2297 } else {
2298 txq->txq_poll_mark = true;
2299 }
2300 }
2301 spin_unlock_bh(&txq->lock);
2302 }
2303 }
2304
2305 if (needreset) {
2306 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2307 "TX queues stuck, resetting\n");
8aec7af9 2308 ath5k_reset(sc, NULL, true);
4edd761f
BR		 2309 }
2310
599b13ad
BC		 2311 mutex_unlock(&sc->lock);
2312
4edd761f
BR		 2313 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2314 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2315}
2316
2317
8a63facc
BC		 2318/*************************\
2319* Initialization routines *
2320\*************************/
fa1c114f 2321
132b1c3e
FF		 2322int
2323ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2324{
2325 struct ieee80211_hw *hw = sc->hw;
2326 struct ath_common *common;
2327 int ret;
2328 int csz;
2329
2330 /* Initialize driver private data */
2331 SET_IEEE80211_DEV(hw, sc->dev);
2332 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
b9e61f11
NK		 2333 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2334 IEEE80211_HW_SIGNAL_DBM |
2335 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
132b1c3e
FF		 2336
2337 hw->wiphy->interface_modes =
2338 BIT(NL80211_IFTYPE_AP) |
2339 BIT(NL80211_IFTYPE_STATION) |
2340 BIT(NL80211_IFTYPE_ADHOC) |
2341 BIT(NL80211_IFTYPE_MESH_POINT);
2342
3de135db
BR		 2343 /* both antennas can be configured as RX or TX */
2344 hw->wiphy->available_antennas_tx = 0x3;
2345 hw->wiphy->available_antennas_rx = 0x3;
2346
132b1c3e
FF		 2347 hw->extra_tx_headroom = 2;
2348 hw->channel_change_time = 5000;
2349
2350 /*
2351 * Mark the device as detached to avoid processing
2352 * interrupts until setup is complete.
2353 */
2354 __set_bit(ATH_STAT_INVALID, sc->status);
2355
2356 sc->opmode = NL80211_IFTYPE_STATION;
2357 sc->bintval = 1000;
2358 mutex_init(&sc->lock);
2359 spin_lock_init(&sc->rxbuflock);
2360 spin_lock_init(&sc->txbuflock);
2361 spin_lock_init(&sc->block);
2362
2363
2364 /* Setup interrupt handler */
2365 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2366 if (ret) {
2367 ATH5K_ERR(sc, "request_irq failed\n");
2368 goto err;
2369 }
2370
2371 /* If we passed the test, malloc an ath5k_hw struct */
2372 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2373 if (!sc->ah) {
2374 ret = -ENOMEM;
2375 ATH5K_ERR(sc, "out of memory\n");
2376 goto err_irq;
2377 }
2378
2379 sc->ah->ah_sc = sc;
2380 sc->ah->ah_iobase = sc->iobase;
2381 common = ath5k_hw_common(sc->ah);
2382 common->ops = &ath5k_common_ops;
2383 common->bus_ops = bus_ops;
2384 common->ah = sc->ah;
2385 common->hw = hw;
2386 common->priv = sc;
2387
2388 /*
2389 * Cache line size is used to size and align various
2390 * structures used to communicate with the hardware.
2391 */
2392 ath5k_read_cachesize(common, &csz);
2393 common->cachelsz = csz << 2; /* convert to bytes */
2394
2395 spin_lock_init(&common->cc_lock);
2396
2397 /* Initialize device */
2398 ret = ath5k_hw_init(sc);
2399 if (ret)
2400 goto err_free_ah;
2401
2402 /* set up multi-rate retry capabilities */
2403 if (sc->ah->ah_version == AR5K_AR5212) {
2404 hw->max_rates = 4;
76a9f6fd
BR		 2405 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2406 AR5K_INIT_RETRY_LONG);
132b1c3e
FF		 2407 }
2408
2409 hw->vif_data_size = sizeof(struct ath5k_vif);
2410
2411 /* Finish private driver data initialization */
2412 ret = ath5k_init(hw);
2413 if (ret)
2414 goto err_ah;
2415
2416 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2417 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2418 sc->ah->ah_mac_srev,
2419 sc->ah->ah_phy_revision);
2420
2421 if (!sc->ah->ah_single_chip) {
2422 /* Single chip radio (!RF5111) */
2423 if (sc->ah->ah_radio_5ghz_revision &&
2424 !sc->ah->ah_radio_2ghz_revision) {
2425 /* No 5GHz support -> report 2GHz radio */
2426 if (!test_bit(AR5K_MODE_11A,
2427 sc->ah->ah_capabilities.cap_mode)) {
2428 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2429 ath5k_chip_name(AR5K_VERSION_RAD,
2430 sc->ah->ah_radio_5ghz_revision),
2431 sc->ah->ah_radio_5ghz_revision);
2432 /* No 2GHz support (5110 and some
2433 * 5Ghz only cards) -> report 5Ghz radio */
2434 } else if (!test_bit(AR5K_MODE_11B,
2435 sc->ah->ah_capabilities.cap_mode)) {
2436 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2437 ath5k_chip_name(AR5K_VERSION_RAD,
2438 sc->ah->ah_radio_5ghz_revision),
2439 sc->ah->ah_radio_5ghz_revision);
2440 /* Multiband radio */
2441 } else {
2442 ATH5K_INFO(sc, "RF%s multiband radio found"
2443 " (0x%x)\n",
2444 ath5k_chip_name(AR5K_VERSION_RAD,
2445 sc->ah->ah_radio_5ghz_revision),
2446 sc->ah->ah_radio_5ghz_revision);
2447 }
2448 }
2449 /* Multi chip radio (RF5111 - RF2111) ->
2450 * report both 2GHz/5GHz radios */
2451 else if (sc->ah->ah_radio_5ghz_revision &&
2452 sc->ah->ah_radio_2ghz_revision){
2453 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2454 ath5k_chip_name(AR5K_VERSION_RAD,
2455 sc->ah->ah_radio_5ghz_revision),
2456 sc->ah->ah_radio_5ghz_revision);
2457 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2458 ath5k_chip_name(AR5K_VERSION_RAD,
2459 sc->ah->ah_radio_2ghz_revision),
2460 sc->ah->ah_radio_2ghz_revision);
2461 }
2462 }
2463
2464 ath5k_debug_init_device(sc);
2465
2466 /* ready to process interrupts */
2467 __clear_bit(ATH_STAT_INVALID, sc->status);
2468
2469 return 0;
2470err_ah:
2471 ath5k_hw_deinit(sc->ah);
2472err_free_ah:
2473 kfree(sc->ah);
2474err_irq:
2475 free_irq(sc->irq, sc);
2476err:
2477 return ret;
2478}
2479
fa1c114f 2480static int
8a63facc 2481ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2482{
8a63facc 2483 struct ath5k_hw *ah = sc->ah;
cec8db23 2484
8a63facc
BC		 2485 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2486 test_bit(ATH_STAT_INVALID, sc->status));
2487
2488 /*
2489 * Shutdown the hardware and driver:
2490 * stop output from above
2491 * disable interrupts
2492 * turn off timers
2493 * turn off the radio
2494 * clear transmit machinery
2495 * clear receive machinery
2496 * drain and release tx queues
2497 * reclaim beacon resources
2498 * power down hardware
2499 *
2500 * Note that some of this work is not possible if the
2501 * hardware is gone (invalid).
2502 */
2503 ieee80211_stop_queues(sc->hw);
2504
2505 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2506 ath5k_led_off(sc);
2507 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2508 synchronize_irq(sc->irq);
8a63facc 2509 ath5k_rx_stop(sc);
80dac9ee
NK		 2510 ath5k_hw_dma_stop(ah);
2511 ath5k_drain_tx_buffs(sc);
8a63facc
BC		 2512 ath5k_hw_phy_disable(ah);
2513 }
2514
2515 return 0;
cec8db23
BC		 2516}
2517
cd2c5486 2518int
132b1c3e 2519ath5k_init_hw(struct ath5k_softc *sc)
fa1c114f 2520{
8a63facc
BC		 2521 struct ath5k_hw *ah = sc->ah;
2522 struct ath_common *common = ath5k_hw_common(ah);
2523 int ret, i;
fa1c114f 2524
8a63facc
BC		 2525 mutex_lock(&sc->lock);
2526
2527 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2528
fa1c114f 2529 /*
8a63facc
BC		 2530 * Stop anything previously setup. This is safe
2531 * no matter this is the first time through or not.
fa1c114f 2532 */
8a63facc 2533 ath5k_stop_locked(sc);
fa1c114f 2534
8a63facc
BC		 2535 /*
2536 * The basic interface to setting the hardware in a good
2537 * state is ``reset''. On return the hardware is known to
2538 * be powered up and with interrupts disabled. This must
2539 * be followed by initialization of the appropriate bits
2540 * and then setup of the interrupt mask.
2541 */
2542 sc->curchan = sc->hw->conf.channel;
8a63facc
BC		 2543 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2544 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2545 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2546
8aec7af9 2547 ret = ath5k_reset(sc, NULL, false);
8a63facc
BC		 2548 if (ret)
2549 goto done;
fa1c114f 2550
8a63facc
BC		 2551 ath5k_rfkill_hw_start(ah);
2552
2553 /*
2554 * Reset the key cache since some parts do not reset the
2555 * contents on initial power up or resume from suspend.
2556 */
2557 for (i = 0; i < common->keymax; i++)
2558 ath_hw_keyreset(common, (u16) i);
2559
61cde037
NK		 2560 /* Use higher rates for acks instead of base
2561 * rate */
2562 ah->ah_ack_bitrate_high = true;
b1ae1edf
BG		 2563
2564 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2565 sc->bslot[i] = NULL;
2566
8a63facc
BC		 2567 ret = 0;
2568done:
2569 mmiowb();
2570 mutex_unlock(&sc->lock);
4edd761f
BR		 2571
2572 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2573 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2574
8a63facc
BC		 2575 return ret;
2576}
2577
2578static void stop_tasklets(struct ath5k_softc *sc)
2579{
2580 tasklet_kill(&sc->rxtq);
2581 tasklet_kill(&sc->txtq);
2582 tasklet_kill(&sc->calib);
2583 tasklet_kill(&sc->beacontq);
2584 tasklet_kill(&sc->ani_tasklet);
2585}
2586
2587/*
2588 * Stop the device, grabbing the top-level lock to protect
2589 * against concurrent entry through ath5k_init (which can happen
2590 * if another thread does a system call and the thread doing the
2591 * stop is preempted).
2592 */
cd2c5486 2593int
8a63facc
BC		 2594ath5k_stop_hw(struct ath5k_softc *sc)
2595{
2596 int ret;
2597
2598 mutex_lock(&sc->lock);
2599 ret = ath5k_stop_locked(sc);
2600 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2601 /*
2602 * Don't set the card in full sleep mode!
2603 *
2604 * a) When the device is in this state it must be carefully
2605 * woken up or references to registers in the PCI clock
2606 * domain may freeze the bus (and system). This varies
2607 * by chip and is mostly an issue with newer parts
2608 * (madwifi sources mentioned srev >= 0x78) that go to
2609 * sleep more quickly.
2610 *
2611 * b) On older chips full sleep results a weird behaviour
2612 * during wakeup. I tested various cards with srev < 0x78
2613 * and they don't wake up after module reload, a second
2614 * module reload is needed to bring the card up again.
2615 *
2616 * Until we figure out what's going on don't enable
2617 * full chip reset on any chip (this is what Legacy HAL
2618 * and Sam's HAL do anyway). Instead Perform a full reset
2619 * on the device (same as initial state after attach) and
2620 * leave it idle (keep MAC/BB on warm reset) */
2621 ret = ath5k_hw_on_hold(sc->ah);
2622
2623 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2624 "putting device to sleep\n");
fa1c114f
JS		 2625 }
2626
8a63facc
BC		 2627 mmiowb();
2628 mutex_unlock(&sc->lock);
2629
2630 stop_tasklets(sc);
2631
4edd761f
BR		 2632 cancel_delayed_work_sync(&sc->tx_complete_work);
2633
8a63facc
BC		 2634 ath5k_rfkill_hw_stop(sc->ah);
2635
2636 return ret;
fa1c114f
JS		 2637}
2638
209d889b
BC		 2639/*
2640 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2641 * and change to the given channel.
5faaff74
BC		 2642 *
2643 * This should be called with sc->lock.
209d889b 2644 */
fa1c114f 2645static int
8aec7af9
NK		 2646ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2647 bool skip_pcu)
fa1c114f 2648{
fa1c114f 2649 struct ath5k_hw *ah = sc->ah;
f15a4bb2 2650 struct ath_common *common = ath5k_hw_common(ah);
344b54b9 2651 int ret, ani_mode;
fa1c114f
JS		 2652
2653 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2654
450464de 2655 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2656 synchronize_irq(sc->irq);
450464de
BC		 2657 stop_tasklets(sc);
2658
344b54b9
NK		 2659 /* Save ani mode and disable ANI durring
2660 * reset. If we don't we might get false
2661 * PHY error interrupts. */
2662 ani_mode = ah->ah_sc->ani_state.ani_mode;
2663 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2664
19252ecb
NK		 2665 /* We are going to empty hw queues
2666 * so we should also free any remaining
2667 * tx buffers */
2668 ath5k_drain_tx_buffs(sc);
930a7622 2669 if (chan)
209d889b 2670 sc->curchan = chan;
8aec7af9
NK		 2671 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
2672 skip_pcu);
d7dc1003 2673 if (ret) {
fa1c114f
JS		 2674 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2675 goto err;
2676 }
d7dc1003 2677
fa1c114f 2678 ret = ath5k_rx_start(sc);
d7dc1003 2679 if (ret) {
fa1c114f
JS		 2680 ATH5K_ERR(sc, "can't start recv logic\n");
2681 goto err;
2682 }
d7dc1003 2683
344b54b9 2684 ath5k_ani_init(ah, ani_mode);
2111ac0d 2685
ac559526
BR		 2686 ah->ah_cal_next_full = jiffies;
2687 ah->ah_cal_next_ani = jiffies;
afe86286 2688 ah->ah_cal_next_nf = jiffies;
5dcc03fe 2689 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2690
f15a4bb2
BR		 2691 /* clear survey data and cycle counters */
2692 memset(&sc->survey, 0, sizeof(sc->survey));
bb007554 2693 spin_lock_bh(&common->cc_lock);
f15a4bb2
BR		 2694 ath_hw_cycle_counters_update(common);
2695 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2696 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
bb007554 2697 spin_unlock_bh(&common->cc_lock);
f15a4bb2 2698
fa1c114f 2699 /*
d7dc1003
JS		 2700 * Change channels and update the h/w rate map if we're switching;
2701 * e.g. 11a to 11b/g.
2702 *
2703 * We may be doing a reset in response to an ioctl that changes the
2704 * channel so update any state that might change as a result.
fa1c114f
JS		 2705 *
2706 * XXX needed?
2707 */
2708/* ath5k_chan_change(sc, c); */
fa1c114f 2709
d7dc1003
JS		 2710 ath5k_beacon_config(sc);
2711 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2712
397f385b
BR		 2713 ieee80211_wake_queues(sc->hw);
2714
fa1c114f
JS		 2715 return 0;
2716err:
2717 return ret;
2718}
2719
5faaff74
BC		 2720static void ath5k_reset_work(struct work_struct *work)
2721{
2722 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2723 reset_work);
2724
2725 mutex_lock(&sc->lock);
8aec7af9 2726 ath5k_reset(sc, NULL, true);
5faaff74
BC		 2727 mutex_unlock(&sc->lock);
2728}
2729
8a63facc 2730static int
132b1c3e 2731ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2732{
132b1c3e 2733
fa1c114f 2734 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2735 struct ath5k_hw *ah = sc->ah;
2736 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2737 struct ath5k_txq *txq;
8a63facc 2738 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2739 int ret;
2740
fa1c114f 2741
8a63facc
BC		 2742 /*
2743 * Check if the MAC has multi-rate retry support.
2744 * We do this by trying to setup a fake extended
2745 * descriptor. MACs that don't have support will
2746 * return false w/o doing anything. MACs that do
2747 * support it will return true w/o doing anything.
2748 */
2749 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2750
8a63facc
BC		 2751 if (ret < 0)
2752 goto err;
2753 if (ret > 0)
2754 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2755
8a63facc
BC		 2756 /*
2757 * Collect the channel list. The 802.11 layer
2758 * is resposible for filtering this list based
2759 * on settings like the phy mode and regulatory
2760 * domain restrictions.
2761 */
2762 ret = ath5k_setup_bands(hw);
2763 if (ret) {
2764 ATH5K_ERR(sc, "can't get channels\n");
2765 goto err;
2766 }
67d2e2df 2767
8a63facc
BC		 2768 /*
2769 * Allocate tx+rx descriptors and populate the lists.
2770 */
aeae4ac9 2771 ret = ath5k_desc_alloc(sc);
8a63facc
BC		 2772 if (ret) {
2773 ATH5K_ERR(sc, "can't allocate descriptors\n");
2774 goto err;
2775 }
fa1c114f 2776
8a63facc
BC		 2777 /*
2778 * Allocate hardware transmit queues: one queue for
2779 * beacon frames and one data queue for each QoS
2780 * priority. Note that hw functions handle resetting
2781 * these queues at the needed time.
2782 */
2783 ret = ath5k_beaconq_setup(ah);
2784 if (ret < 0) {
2785 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2786 goto err_desc;
2787 }
2788 sc->bhalq = ret;
2789 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2790 if (IS_ERR(sc->cabq)) {
2791 ATH5K_ERR(sc, "can't setup cab queue\n");
2792 ret = PTR_ERR(sc->cabq);
2793 goto err_bhal;
2794 }
fa1c114f 2795
22d8d9f8
BR		 2796 /* 5211 and 5212 usually support 10 queues but we better rely on the
2797 * capability information */
2798 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2799 /* This order matches mac80211's queue priority, so we can
2800 * directly use the mac80211 queue number without any mapping */
2801 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2802 if (IS_ERR(txq)) {
2803 ATH5K_ERR(sc, "can't setup xmit queue\n");
2804 ret = PTR_ERR(txq);
2805 goto err_queues;
2806 }
2807 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2808 if (IS_ERR(txq)) {
2809 ATH5K_ERR(sc, "can't setup xmit queue\n");
2810 ret = PTR_ERR(txq);
2811 goto err_queues;
2812 }
2813 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2814 if (IS_ERR(txq)) {
2815 ATH5K_ERR(sc, "can't setup xmit queue\n");
2816 ret = PTR_ERR(txq);
2817 goto err_queues;
2818 }
2819 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2820 if (IS_ERR(txq)) {
2821 ATH5K_ERR(sc, "can't setup xmit queue\n");
2822 ret = PTR_ERR(txq);
2823 goto err_queues;
2824 }
2825 hw->queues = 4;
2826 } else {
2827 /* older hardware (5210) can only support one data queue */
2828 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2829 if (IS_ERR(txq)) {
2830 ATH5K_ERR(sc, "can't setup xmit queue\n");
2831 ret = PTR_ERR(txq);
2832 goto err_queues;
2833 }
2834 hw->queues = 1;
2835 }
fa1c114f 2836
8a63facc
BC		 2837 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2838 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2839 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2840 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2841 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2842
8a63facc 2843 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2844 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2845
8a63facc
BC		 2846 ret = ath5k_eeprom_read_mac(ah, mac);
2847 if (ret) {
aeae4ac9 2848 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
8a63facc 2849 goto err_queues;
e30eb4ab 2850 }
2bed03eb 2851
8a63facc 2852 SET_IEEE80211_PERM_ADDR(hw, mac);
b1ae1edf 2853 memcpy(&sc->lladdr, mac, ETH_ALEN);
8a63facc 2854 /* All MAC address bits matter for ACKs */
62c58fb4 2855 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2856
2857 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2858 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2859 if (ret) {
2860 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2861 goto err_queues;
2862 }
2863
2864 ret = ieee80211_register_hw(hw);
2865 if (ret) {
2866 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2867 goto err_queues;
2868 }
2869
2870 if (!ath_is_world_regd(regulatory))
2871 regulatory_hint(hw->wiphy, regulatory->alpha2);
2872
2873 ath5k_init_leds(sc);
2874
2875 ath5k_sysfs_register(sc);
2876
2877 return 0;
2878err_queues:
2879 ath5k_txq_release(sc);
2880err_bhal:
2881 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2882err_desc:
aeae4ac9 2883 ath5k_desc_free(sc);
8a63facc
BC		 2884err:
2885 return ret;
2886}
2887
132b1c3e
FF		 2888void
2889ath5k_deinit_softc(struct ath5k_softc *sc)
8a63facc 2890{
132b1c3e 2891 struct ieee80211_hw *hw = sc->hw;
8a63facc
BC		 2892
2893 /*
2894 * NB: the order of these is important:
2895 * o call the 802.11 layer before detaching ath5k_hw to
2896 * ensure callbacks into the driver to delete global
2897 * key cache entries can be handled
2898 * o reclaim the tx queue data structures after calling
2899 * the 802.11 layer as we'll get called back to reclaim
2900 * node state and potentially want to use them
2901 * o to cleanup the tx queues the hal is called, so detach
2902 * it last
2903 * XXX: ??? detach ath5k_hw ???
2904 * Other than that, it's straightforward...
2905 */
132b1c3e 2906 ath5k_debug_finish_device(sc);
8a63facc 2907 ieee80211_unregister_hw(hw);
aeae4ac9 2908 ath5k_desc_free(sc);
8a63facc
BC		 2909 ath5k_txq_release(sc);
2910 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2911 ath5k_unregister_leds(sc);
2912
2913 ath5k_sysfs_unregister(sc);
2914 /*
2915 * NB: can't reclaim these until after ieee80211_ifdetach
2916 * returns because we'll get called back to reclaim node
2917 * state and potentially want to use them.
2918 */
132b1c3e
FF		 2919 ath5k_hw_deinit(sc->ah);
2920 free_irq(sc->irq, sc);
8a63facc
BC		 2921}
2922
cd2c5486
BR		 2923bool
2924ath_any_vif_assoc(struct ath5k_softc *sc)
b1ae1edf
BG		 2925{
2926 struct ath_vif_iter_data iter_data;
2927 iter_data.hw_macaddr = NULL;
2928 iter_data.any_assoc = false;
2929 iter_data.need_set_hw_addr = false;
2930 iter_data.found_active = true;
2931
2932 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
2933 &iter_data);
2934 return iter_data.any_assoc;
2935}
2936
cd2c5486 2937void
8a63facc
BC		 2938set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2939{
2940 struct ath5k_softc *sc = hw->priv;
2941 struct ath5k_hw *ah = sc->ah;
2942 u32 rfilt;
2943 rfilt = ath5k_hw_get_rx_filter(ah);
2944 if (enable)
2945 rfilt |= AR5K_RX_FILTER_BEACON;
2946 else
2947 rfilt &= ~AR5K_RX_FILTER_BEACON;
2948 ath5k_hw_set_rx_filter(ah, rfilt);
2949 sc->filter_flags = rfilt;
2950}
Linux 6.x block layer and io_uring tree(s)