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rndis_wlan: increase assocbuf size and validate association info offsets from driver
[linux-block.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
5a0e3ad6 53#include <linux/slab.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
fa1c114f 63
9ad9a26e 64static int modparam_nohwcrypt;
46802a4f 65module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 66MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 67
42639fcd 68static int modparam_all_channels;
46802a4f 69module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 70MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
71
fa1c114f
JS		 72
73/******************\
74* Internal defines *
75\******************/
76
77/* Module info */
78MODULE_AUTHOR("Jiri Slaby");
79MODULE_AUTHOR("Nick Kossifidis");
80MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 83MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 84
85
86/* Known PCI ids */
a3aa1884 87static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
97a81f5c
PR		 88 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
105 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 106 { 0 }
107};
108MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
109
110/* Known SREVs */
2c91108c 111static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 112 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
113 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
114 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
115 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
116 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
117 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
118 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
119 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
120 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
121 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
122 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
123 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
124 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
125 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
126 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
127 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
128 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
129 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
144 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
145 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 146 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
148};
149
2c91108c 150static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 151 { .bitrate = 10,
152 .hw_value = ATH5K_RATE_CODE_1M, },
153 { .bitrate = 20,
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 55,
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 { .bitrate = 110,
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 { .bitrate = 60,
166 .hw_value = ATH5K_RATE_CODE_6M,
167 .flags = 0 },
168 { .bitrate = 90,
169 .hw_value = ATH5K_RATE_CODE_9M,
170 .flags = 0 },
171 { .bitrate = 120,
172 .hw_value = ATH5K_RATE_CODE_12M,
173 .flags = 0 },
174 { .bitrate = 180,
175 .hw_value = ATH5K_RATE_CODE_18M,
176 .flags = 0 },
177 { .bitrate = 240,
178 .hw_value = ATH5K_RATE_CODE_24M,
179 .flags = 0 },
180 { .bitrate = 360,
181 .hw_value = ATH5K_RATE_CODE_36M,
182 .flags = 0 },
183 { .bitrate = 480,
184 .hw_value = ATH5K_RATE_CODE_48M,
185 .flags = 0 },
186 { .bitrate = 540,
187 .hw_value = ATH5K_RATE_CODE_54M,
188 .flags = 0 },
189 /* XR missing */
190};
191
fa1c114f
JS		 192/*
193 * Prototypes - PCI stack related functions
194 */
195static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
196 const struct pci_device_id *id);
197static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198#ifdef CONFIG_PM
baee1f3c
RW		 199static int ath5k_pci_suspend(struct device *dev);
200static int ath5k_pci_resume(struct device *dev);
201
626ede6b 202static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
baee1f3c 203#define ATH5K_PM_OPS (&ath5k_pm_ops)
fa1c114f 204#else
baee1f3c 205#define ATH5K_PM_OPS NULL
fa1c114f
JS		 206#endif /* CONFIG_PM */
207
04a9e451 208static struct pci_driver ath5k_pci_driver = {
9764f3f9 209 .name = KBUILD_MODNAME,
fa1c114f
JS		 210 .id_table = ath5k_pci_id_table,
211 .probe = ath5k_pci_probe,
212 .remove = __devexit_p(ath5k_pci_remove),
baee1f3c 213 .driver.pm = ATH5K_PM_OPS,
fa1c114f
JS		 214};
215
216
217
218/*
219 * Prototypes - MAC 802.11 stack related functions
220 */
e039fa4a 221static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
cec8db23
BC		 222static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
223 struct ath5k_txq *txq);
209d889b 224static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
d7dc1003 225static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 226static int ath5k_start(struct ieee80211_hw *hw);
227static void ath5k_stop(struct ieee80211_hw *hw);
228static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 229 struct ieee80211_vif *vif);
fa1c114f 230static void ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 231 struct ieee80211_vif *vif);
e8975581 232static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
3ac64bee 233static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 234 struct netdev_hw_addr_list *mc_list);
fa1c114f
JS		 235static void ath5k_configure_filter(struct ieee80211_hw *hw,
236 unsigned int changed_flags,
237 unsigned int *new_flags,
3ac64bee 238 u64 multicast);
fa1c114f
JS		 239static int ath5k_set_key(struct ieee80211_hw *hw,
240 enum set_key_cmd cmd,
dc822b5d 241 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 242 struct ieee80211_key_conf *key);
243static int ath5k_get_stats(struct ieee80211_hw *hw,
244 struct ieee80211_low_level_stats *stats);
55ee82b5
HS		 245static int ath5k_get_survey(struct ieee80211_hw *hw,
246 int idx, struct survey_info *survey);
fa1c114f 247static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 248static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 249static void ath5k_reset_tsf(struct ieee80211_hw *hw);
1071db86
BC		 250static int ath5k_beacon_update(struct ieee80211_hw *hw,
251 struct ieee80211_vif *vif);
02969b38
MX		 252static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
253 struct ieee80211_vif *vif,
254 struct ieee80211_bss_conf *bss_conf,
255 u32 changes);
f0f3d388
BC		 256static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
257static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
6e08d228
LT		 258static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
259 u8 coverage_class);
fa1c114f 260
2c91108c 261static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 262 .tx = ath5k_tx,
263 .start = ath5k_start,
264 .stop = ath5k_stop,
265 .add_interface = ath5k_add_interface,
266 .remove_interface = ath5k_remove_interface,
267 .config = ath5k_config,
3ac64bee 268 .prepare_multicast = ath5k_prepare_multicast,
fa1c114f
JS		 269 .configure_filter = ath5k_configure_filter,
270 .set_key = ath5k_set_key,
271 .get_stats = ath5k_get_stats,
55ee82b5 272 .get_survey = ath5k_get_survey,
fa1c114f 273 .conf_tx = NULL,
fa1c114f 274 .get_tsf = ath5k_get_tsf,
3b5d665b 275 .set_tsf = ath5k_set_tsf,
fa1c114f 276 .reset_tsf = ath5k_reset_tsf,
02969b38 277 .bss_info_changed = ath5k_bss_info_changed,
f0f3d388
BC		 278 .sw_scan_start = ath5k_sw_scan_start,
279 .sw_scan_complete = ath5k_sw_scan_complete,
6e08d228 280 .set_coverage_class = ath5k_set_coverage_class,
fa1c114f
JS		 281};
282
283/*
284 * Prototypes - Internal functions
285 */
286/* Attach detach */
287static int ath5k_attach(struct pci_dev *pdev,
288 struct ieee80211_hw *hw);
289static void ath5k_detach(struct pci_dev *pdev,
290 struct ieee80211_hw *hw);
291/* Channel/mode setup */
292static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 293static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
294 struct ieee80211_channel *channels,
295 unsigned int mode,
296 unsigned int max);
63266a65 297static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 298static int ath5k_chan_set(struct ath5k_softc *sc,
299 struct ieee80211_channel *chan);
300static void ath5k_setcurmode(struct ath5k_softc *sc,
301 unsigned int mode);
302static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 303
fa1c114f
JS		 304/* Descriptor setup */
305static int ath5k_desc_alloc(struct ath5k_softc *sc,
306 struct pci_dev *pdev);
307static void ath5k_desc_free(struct ath5k_softc *sc,
308 struct pci_dev *pdev);
309/* Buffers setup */
310static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
311 struct ath5k_buf *bf);
312static int ath5k_txbuf_setup(struct ath5k_softc *sc,
cec8db23 313 struct ath5k_buf *bf,
8127fbdc 314 struct ath5k_txq *txq, int padsize);
fa1c114f
JS		 315static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
316 struct ath5k_buf *bf)
317{
318 BUG_ON(!bf);
319 if (!bf->skb)
320 return;
321 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
322 PCI_DMA_TODEVICE);
00482973 323 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 324 bf->skb = NULL;
325}
326
a6c8d375
FF		 327static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
328 struct ath5k_buf *bf)
329{
cc861f74
LR		 330 struct ath5k_hw *ah = sc->ah;
331 struct ath_common *common = ath5k_hw_common(ah);
332
a6c8d375
FF		 333 BUG_ON(!bf);
334 if (!bf->skb)
335 return;
cc861f74 336 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
a6c8d375
FF		 337 PCI_DMA_FROMDEVICE);
338 dev_kfree_skb_any(bf->skb);
339 bf->skb = NULL;
340}
341
342
fa1c114f
JS		 343/* Queues setup */
344static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
345 int qtype, int subtype);
346static int ath5k_beaconq_setup(struct ath5k_hw *ah);
347static int ath5k_beaconq_config(struct ath5k_softc *sc);
348static void ath5k_txq_drainq(struct ath5k_softc *sc,
349 struct ath5k_txq *txq);
350static void ath5k_txq_cleanup(struct ath5k_softc *sc);
351static void ath5k_txq_release(struct ath5k_softc *sc);
352/* Rx handling */
353static int ath5k_rx_start(struct ath5k_softc *sc);
354static void ath5k_rx_stop(struct ath5k_softc *sc);
355static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
356 struct ath5k_desc *ds,
b47f407b
BR		 357 struct sk_buff *skb,
358 struct ath5k_rx_status *rs);
fa1c114f
JS		 359static void ath5k_tasklet_rx(unsigned long data);
360/* Tx handling */
361static void ath5k_tx_processq(struct ath5k_softc *sc,
362 struct ath5k_txq *txq);
363static void ath5k_tasklet_tx(unsigned long data);
364/* Beacon handling */
365static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 366 struct ath5k_buf *bf);
fa1c114f
JS		 367static void ath5k_beacon_send(struct ath5k_softc *sc);
368static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 369static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 370static void ath5k_tasklet_beacon(unsigned long data);
2111ac0d 371static void ath5k_tasklet_ani(unsigned long data);
fa1c114f
JS		 372
373static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
374{
375 u64 tsf = ath5k_hw_get_tsf64(ah);
376
377 if ((tsf & 0x7fff) < rstamp)
378 tsf -= 0x8000;
379
380 return (tsf & ~0x7fff) | rstamp;
381}
382
383/* Interrupt handling */
bb2becac 384static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 385static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 386static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 387static irqreturn_t ath5k_intr(int irq, void *dev_id);
388static void ath5k_tasklet_reset(unsigned long data);
389
6e220662 390static void ath5k_tasklet_calibrate(unsigned long data);
fa1c114f
JS		 391
392/*
393 * Module init/exit functions
394 */
395static int __init
396init_ath5k_pci(void)
397{
398 int ret;
399
400 ath5k_debug_init();
401
04a9e451 402 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 403 if (ret) {
404 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
405 return ret;
406 }
407
408 return 0;
409}
410
411static void __exit
412exit_ath5k_pci(void)
413{
04a9e451 414 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 415
416 ath5k_debug_finish();
417}
418
419module_init(init_ath5k_pci);
420module_exit(exit_ath5k_pci);
421
422
423/********************\
424* PCI Initialization *
425\********************/
426
427static const char *
428ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
429{
430 const char *name = "xxxxx";
431 unsigned int i;
432
433 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
434 if (srev_names[i].sr_type != type)
435 continue;
75d0edb8
NK		 436
437 if ((val & 0xf0) == srev_names[i].sr_val)
438 name = srev_names[i].sr_name;
439
440 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 441 name = srev_names[i].sr_name;
442 break;
443 }
444 }
445
446 return name;
447}
e5aa8474
LR		 448static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
449{
450 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
451 return ath5k_hw_reg_read(ah, reg_offset);
452}
453
454static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
455{
456 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
457 ath5k_hw_reg_write(ah, val, reg_offset);
458}
459
460static const struct ath_ops ath5k_common_ops = {
461 .read = ath5k_ioread32,
462 .write = ath5k_iowrite32,
463};
fa1c114f
JS		 464
465static int __devinit
466ath5k_pci_probe(struct pci_dev *pdev,
467 const struct pci_device_id *id)
468{
469 void __iomem *mem;
470 struct ath5k_softc *sc;
db719718 471 struct ath_common *common;
fa1c114f
JS		 472 struct ieee80211_hw *hw;
473 int ret;
474 u8 csz;
475
476 ret = pci_enable_device(pdev);
477 if (ret) {
478 dev_err(&pdev->dev, "can't enable device\n");
479 goto err;
480 }
481
482 /* XXX 32-bit addressing only */
284901a9 483 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 484 if (ret) {
485 dev_err(&pdev->dev, "32-bit DMA not available\n");
486 goto err_dis;
487 }
488
489 /*
490 * Cache line size is used to size and align various
491 * structures used to communicate with the hardware.
492 */
493 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
494 if (csz == 0) {
495 /*
496 * Linux 2.4.18 (at least) writes the cache line size
497 * register as a 16-bit wide register which is wrong.
498 * We must have this setup properly for rx buffer
499 * DMA to work so force a reasonable value here if it
500 * comes up zero.
501 */
13311b00 502 csz = L1_CACHE_BYTES >> 2;
fa1c114f
JS		 503 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
504 }
505 /*
506 * The default setting of latency timer yields poor results,
507 * set it to the value used by other systems. It may be worth
508 * tweaking this setting more.
509 */
510 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
511
512 /* Enable bus mastering */
513 pci_set_master(pdev);
514
515 /*
516 * Disable the RETRY_TIMEOUT register (0x41) to keep
517 * PCI Tx retries from interfering with C3 CPU state.
518 */
519 pci_write_config_byte(pdev, 0x41, 0);
520
521 ret = pci_request_region(pdev, 0, "ath5k");
522 if (ret) {
523 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
524 goto err_dis;
525 }
526
527 mem = pci_iomap(pdev, 0, 0);
528 if (!mem) {
529 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
530 ret = -EIO;
531 goto err_reg;
532 }
533
534 /*
535 * Allocate hw (mac80211 main struct)
536 * and hw->priv (driver private data)
537 */
538 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
539 if (hw == NULL) {
540 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
541 ret = -ENOMEM;
542 goto err_map;
543 }
544
545 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
546
547 /* Initialize driver private data */
548 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a 549 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cec8db23 550 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
f5c044e5 551 IEEE80211_HW_SIGNAL_DBM;
f59ac048
LR		 552
553 hw->wiphy->interface_modes =
6f5f39c9 554 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 555 BIT(NL80211_IFTYPE_STATION) |
556 BIT(NL80211_IFTYPE_ADHOC) |
557 BIT(NL80211_IFTYPE_MESH_POINT);
558
fa1c114f
JS		 559 hw->extra_tx_headroom = 2;
560 hw->channel_change_time = 5000;
fa1c114f
JS		 561 sc = hw->priv;
562 sc->hw = hw;
563 sc->pdev = pdev;
564
565 ath5k_debug_init_device(sc);
566
567 /*
568 * Mark the device as detached to avoid processing
569 * interrupts until setup is complete.
570 */
571 __set_bit(ATH_STAT_INVALID, sc->status);
572
573 sc->iobase = mem; /* So we can unmap it on detach */
05c914fe 574 sc->opmode = NL80211_IFTYPE_STATION;
eab0cd49 575 sc->bintval = 1000;
fa1c114f
JS		 576 mutex_init(&sc->lock);
577 spin_lock_init(&sc->rxbuflock);
578 spin_lock_init(&sc->txbuflock);
00482973 579 spin_lock_init(&sc->block);
fa1c114f
JS		 580
581 /* Set private data */
582 pci_set_drvdata(pdev, hw);
583
fa1c114f
JS		 584 /* Setup interrupt handler */
585 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
586 if (ret) {
587 ATH5K_ERR(sc, "request_irq failed\n");
588 goto err_free;
589 }
590
9adca126
LR		 591 /*If we passed the test malloc a ath5k_hw struct*/
592 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
593 if (!sc->ah) {
594 ret = -ENOMEM;
595 ATH5K_ERR(sc, "out of memory\n");
fa1c114f
JS		 596 goto err_irq;
597 }
598
9adca126
LR		 599 sc->ah->ah_sc = sc;
600 sc->ah->ah_iobase = sc->iobase;
db719718 601 common = ath5k_hw_common(sc->ah);
e5aa8474 602 common->ops = &ath5k_common_ops;
13b81559 603 common->ah = sc->ah;
b002a4a9 604 common->hw = hw;
db719718
LR		 605 common->cachelsz = csz << 2; /* convert to bytes */
606
9adca126
LR		 607 /* Initialize device */
608 ret = ath5k_hw_attach(sc);
609 if (ret) {
610 goto err_free_ah;
611 }
612
2f7fe870
FF		 613 /* set up multi-rate retry capabilities */
614 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 615 hw->max_rates = 4;
616 hw->max_rate_tries = 11;
2f7fe870
FF		 617 }
618
fa1c114f
JS		 619 /* Finish private driver data initialization */
620 ret = ath5k_attach(pdev, hw);
621 if (ret)
622 goto err_ah;
623
624 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 625 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 626 sc->ah->ah_mac_srev,
627 sc->ah->ah_phy_revision);
628
400ec45a 629 if (!sc->ah->ah_single_chip) {
fa1c114f 630 /* Single chip radio (!RF5111) */
400ec45a
LR		 631 if (sc->ah->ah_radio_5ghz_revision &&
632 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 633 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 634 if (!test_bit(AR5K_MODE_11A,
635 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 636 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 637 ath5k_chip_name(AR5K_VERSION_RAD,
638 sc->ah->ah_radio_5ghz_revision),
639 sc->ah->ah_radio_5ghz_revision);
640 /* No 2GHz support (5110 and some
641 * 5Ghz only cards) -> report 5Ghz radio */
642 } else if (!test_bit(AR5K_MODE_11B,
643 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 644 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 645 ath5k_chip_name(AR5K_VERSION_RAD,
646 sc->ah->ah_radio_5ghz_revision),
647 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 648 /* Multiband radio */
649 } else {
650 ATH5K_INFO(sc, "RF%s multiband radio found"
651 " (0x%x)\n",
400ec45a
LR		 652 ath5k_chip_name(AR5K_VERSION_RAD,
653 sc->ah->ah_radio_5ghz_revision),
654 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 655 }
656 }
400ec45a
LR		 657 /* Multi chip radio (RF5111 - RF2111) ->
658 * report both 2GHz/5GHz radios */
659 else if (sc->ah->ah_radio_5ghz_revision &&
660 sc->ah->ah_radio_2ghz_revision){
fa1c114f 661 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 662 ath5k_chip_name(AR5K_VERSION_RAD,
663 sc->ah->ah_radio_5ghz_revision),
664 sc->ah->ah_radio_5ghz_revision);
fa1c114f 665 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 666 ath5k_chip_name(AR5K_VERSION_RAD,
667 sc->ah->ah_radio_2ghz_revision),
668 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 669 }
670 }
671
672
673 /* ready to process interrupts */
674 __clear_bit(ATH_STAT_INVALID, sc->status);
675
676 return 0;
677err_ah:
678 ath5k_hw_detach(sc->ah);
679err_irq:
680 free_irq(pdev->irq, sc);
9adca126
LR		 681err_free_ah:
682 kfree(sc->ah);
fa1c114f 683err_free:
fa1c114f
JS		 684 ieee80211_free_hw(hw);
685err_map:
686 pci_iounmap(pdev, mem);
687err_reg:
688 pci_release_region(pdev, 0);
689err_dis:
690 pci_disable_device(pdev);
691err:
692 return ret;
693}
694
695static void __devexit
696ath5k_pci_remove(struct pci_dev *pdev)
697{
698 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
699 struct ath5k_softc *sc = hw->priv;
700
701 ath5k_debug_finish_device(sc);
702 ath5k_detach(pdev, hw);
703 ath5k_hw_detach(sc->ah);
9adca126 704 kfree(sc->ah);
fa1c114f 705 free_irq(pdev->irq, sc);
fa1c114f
JS		 706 pci_iounmap(pdev, sc->iobase);
707 pci_release_region(pdev, 0);
708 pci_disable_device(pdev);
709 ieee80211_free_hw(hw);
710}
711
712#ifdef CONFIG_PM
baee1f3c 713static int ath5k_pci_suspend(struct device *dev)
fa1c114f 714{
baee1f3c 715 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
fa1c114f
JS		 716 struct ath5k_softc *sc = hw->priv;
717
3a078876 718 ath5k_led_off(sc);
fa1c114f
JS		 719 return 0;
720}
721
baee1f3c 722static int ath5k_pci_resume(struct device *dev)
fa1c114f 723{
baee1f3c 724 struct pci_dev *pdev = to_pci_dev(dev);
fa1c114f
JS		 725 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
726 struct ath5k_softc *sc = hw->priv;
fa1c114f 727
8451d22d
JM		 728 /*
729 * Suspend/Resume resets the PCI configuration space, so we have to
730 * re-disable the RETRY_TIMEOUT register (0x41) to keep
731 * PCI Tx retries from interfering with C3 CPU state
732 */
733 pci_write_config_byte(pdev, 0x41, 0);
734
3a078876 735 ath5k_led_enable(sc);
fa1c114f
JS		 736 return 0;
737}
738#endif /* CONFIG_PM */
739
740
fa1c114f
JS		 741/***********************\
742* Driver Initialization *
743\***********************/
744
f769c36b
BC		 745static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
746{
747 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
748 struct ath5k_softc *sc = hw->priv;
db719718 749 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
f769c36b 750
608b88cb 751 return ath_reg_notifier_apply(wiphy, request, regulatory);
f769c36b
BC		 752}
753
fa1c114f
JS		 754static int
755ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
756{
757 struct ath5k_softc *sc = hw->priv;
758 struct ath5k_hw *ah = sc->ah;
db719718 759 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
0e149cf5 760 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 761 int ret;
762
763 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
764
765 /*
766 * Check if the MAC has multi-rate retry support.
767 * We do this by trying to setup a fake extended
768 * descriptor. MAC's that don't have support will
769 * return false w/o doing anything. MAC's that do
770 * support it will return true w/o doing anything.
771 */
c6e387a2 772 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 773 if (ret < 0)
774 goto err;
775 if (ret > 0)
fa1c114f
JS		 776 __set_bit(ATH_STAT_MRRETRY, sc->status);
777
fa1c114f
JS		 778 /*
779 * Collect the channel list. The 802.11 layer
780 * is resposible for filtering this list based
781 * on settings like the phy mode and regulatory
782 * domain restrictions.
783 */
63266a65 784 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 785 if (ret) {
786 ATH5K_ERR(sc, "can't get channels\n");
787 goto err;
788 }
789
790 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 791 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
792 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 793 else
d8ee398d 794 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 795
796 /*
797 * Allocate tx+rx descriptors and populate the lists.
798 */
799 ret = ath5k_desc_alloc(sc, pdev);
800 if (ret) {
801 ATH5K_ERR(sc, "can't allocate descriptors\n");
802 goto err;
803 }
804
805 /*
806 * Allocate hardware transmit queues: one queue for
807 * beacon frames and one data queue for each QoS
808 * priority. Note that hw functions handle reseting
809 * these queues at the needed time.
810 */
811 ret = ath5k_beaconq_setup(ah);
812 if (ret < 0) {
813 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
814 goto err_desc;
815 }
816 sc->bhalq = ret;
cec8db23
BC		 817 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
818 if (IS_ERR(sc->cabq)) {
819 ATH5K_ERR(sc, "can't setup cab queue\n");
820 ret = PTR_ERR(sc->cabq);
821 goto err_bhal;
822 }
fa1c114f
JS		 823
824 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
825 if (IS_ERR(sc->txq)) {
826 ATH5K_ERR(sc, "can't setup xmit queue\n");
827 ret = PTR_ERR(sc->txq);
cec8db23 828 goto err_queues;
fa1c114f
JS		 829 }
830
831 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
832 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
833 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
6e220662 834 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
acf3c1a5 835 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2111ac0d 836 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
fa1c114f 837
0e149cf5
BC		 838 ret = ath5k_eeprom_read_mac(ah, mac);
839 if (ret) {
840 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
841 sc->pdev->device);
842 goto err_queues;
843 }
844
fa1c114f
JS		 845 SET_IEEE80211_PERM_ADDR(hw, mac);
846 /* All MAC address bits matter for ACKs */
17753748 847 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
fa1c114f
JS		 848 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
849
608b88cb
LR		 850 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
851 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
f769c36b
BC		 852 if (ret) {
853 ATH5K_ERR(sc, "can't initialize regulatory system\n");
854 goto err_queues;
855 }
856
fa1c114f
JS		 857 ret = ieee80211_register_hw(hw);
858 if (ret) {
859 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
860 goto err_queues;
861 }
862
608b88cb
LR		 863 if (!ath_is_world_regd(regulatory))
864 regulatory_hint(hw->wiphy, regulatory->alpha2);
f769c36b 865
3a078876
BC		 866 ath5k_init_leds(sc);
867
fa1c114f
JS		 868 return 0;
869err_queues:
870 ath5k_txq_release(sc);
871err_bhal:
872 ath5k_hw_release_tx_queue(ah, sc->bhalq);
873err_desc:
874 ath5k_desc_free(sc, pdev);
875err:
876 return ret;
877}
878
879static void
880ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
881{
882 struct ath5k_softc *sc = hw->priv;
883
884 /*
885 * NB: the order of these is important:
886 * o call the 802.11 layer before detaching ath5k_hw to
887 * insure callbacks into the driver to delete global
888 * key cache entries can be handled
889 * o reclaim the tx queue data structures after calling
890 * the 802.11 layer as we'll get called back to reclaim
891 * node state and potentially want to use them
892 * o to cleanup the tx queues the hal is called, so detach
893 * it last
894 * XXX: ??? detach ath5k_hw ???
895 * Other than that, it's straightforward...
896 */
897 ieee80211_unregister_hw(hw);
898 ath5k_desc_free(sc, pdev);
899 ath5k_txq_release(sc);
900 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 901 ath5k_unregister_leds(sc);
fa1c114f
JS		 902
903 /*
904 * NB: can't reclaim these until after ieee80211_ifdetach
905 * returns because we'll get called back to reclaim node
906 * state and potentially want to use them.
907 */
908}
909
910
911
912
913/********************\
914* Channel/mode setup *
915\********************/
916
917/*
918 * Convert IEEE channel number to MHz frequency.
919 */
920static inline short
921ath5k_ieee2mhz(short chan)
922{
923 if (chan <= 14 || chan >= 27)
924 return ieee80211chan2mhz(chan);
925 else
926 return 2212 + chan * 20;
927}
928
42639fcd
BC		 929/*
930 * Returns true for the channel numbers used without all_channels modparam.
931 */
932static bool ath5k_is_standard_channel(short chan)
933{
934 return ((chan <= 14) ||
935 /* UNII 1,2 */
936 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
937 /* midband */
938 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
939 /* UNII-3 */
940 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
941}
942
fa1c114f
JS		 943static unsigned int
944ath5k_copy_channels(struct ath5k_hw *ah,
945 struct ieee80211_channel *channels,
946 unsigned int mode,
947 unsigned int max)
948{
d8ee398d 949 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 950
951 if (!test_bit(mode, ah->ah_modes))
952 return 0;
953
fa1c114f 954 switch (mode) {
d8ee398d
LR		 955 case AR5K_MODE_11A:
956 case AR5K_MODE_11A_TURBO:
fa1c114f 957 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 958 size = 220 ;
fa1c114f
JS		 959 chfreq = CHANNEL_5GHZ;
960 break;
d8ee398d
LR		 961 case AR5K_MODE_11B:
962 case AR5K_MODE_11G:
963 case AR5K_MODE_11G_TURBO:
964 size = 26;
fa1c114f
JS		 965 chfreq = CHANNEL_2GHZ;
966 break;
967 default:
968 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
969 return 0;
970 }
971
972 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 973 ch = i + 1 ;
974 freq = ath5k_ieee2mhz(ch);
fa1c114f 975
d8ee398d
LR		 976 /* Check if channel is supported by the chipset */
977 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 978 continue;
979
42639fcd
BC		 980 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
981 continue;
982
d8ee398d
LR		 983 /* Write channel info and increment counter */
984 channels[count].center_freq = freq;
a3f4b914
LR		 985 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
986 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 987 switch (mode) {
988 case AR5K_MODE_11A:
989 case AR5K_MODE_11G:
990 channels[count].hw_value = chfreq | CHANNEL_OFDM;
991 break;
992 case AR5K_MODE_11A_TURBO:
993 case AR5K_MODE_11G_TURBO:
994 channels[count].hw_value = chfreq |
995 CHANNEL_OFDM | CHANNEL_TURBO;
996 break;
997 case AR5K_MODE_11B:
d8ee398d
LR		 998 channels[count].hw_value = CHANNEL_B;
999 }
fa1c114f 1000
fa1c114f
JS		 1001 count++;
1002 max--;
1003 }
1004
1005 return count;
1006}
1007
63266a65
BR		 1008static void
1009ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1010{
1011 u8 i;
1012
1013 for (i = 0; i < AR5K_MAX_RATES; i++)
1014 sc->rate_idx[b->band][i] = -1;
1015
1016 for (i = 0; i < b->n_bitrates; i++) {
1017 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1018 if (b->bitrates[i].hw_value_short)
1019 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1020 }
1021}
1022
d8ee398d 1023static int
63266a65 1024ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 1025{
1026 struct ath5k_softc *sc = hw->priv;
d8ee398d 1027 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 1028 struct ieee80211_supported_band *sband;
1029 int max_c, count_c = 0;
1030 int i;
fa1c114f 1031
d8ee398d 1032 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 1033 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 1034
1035 /* 2GHz band */
63266a65
BR		 1036 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1037 sband->band = IEEE80211_BAND_2GHZ;
1038 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 1039
63266a65
BR		 1040 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1041 /* G mode */
1042 memcpy(sband->bitrates, &ath5k_rates[0],
1043 sizeof(struct ieee80211_rate) * 12);
1044 sband->n_bitrates = 12;
fa1c114f 1045
d8ee398d 1046 sband->channels = sc->channels;
d8ee398d 1047 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1048 AR5K_MODE_11G, max_c);
fa1c114f 1049
63266a65 1050 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1051 count_c = sband->n_channels;
63266a65
BR		 1052 max_c -= count_c;
1053 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1054 /* B mode */
1055 memcpy(sband->bitrates, &ath5k_rates[0],
1056 sizeof(struct ieee80211_rate) * 4);
1057 sband->n_bitrates = 4;
1058
1059 /* 5211 only supports B rates and uses 4bit rate codes
1060 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1061 * fix them up here:
1062 */
1063 if (ah->ah_version == AR5K_AR5211) {
1064 for (i = 0; i < 4; i++) {
1065 sband->bitrates[i].hw_value =
1066 sband->bitrates[i].hw_value & 0xF;
1067 sband->bitrates[i].hw_value_short =
1068 sband->bitrates[i].hw_value_short & 0xF;
1069 }
1070 }
fa1c114f 1071
63266a65
BR		 1072 sband->channels = sc->channels;
1073 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1074 AR5K_MODE_11B, max_c);
d8ee398d 1075
63266a65
BR		 1076 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1077 count_c = sband->n_channels;
d8ee398d 1078 max_c -= count_c;
fa1c114f 1079 }
63266a65 1080 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1081
63266a65 1082 /* 5GHz band, A mode */
400ec45a 1083 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1084 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1085 sband->band = IEEE80211_BAND_5GHZ;
1086 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1087
63266a65
BR		 1088 memcpy(sband->bitrates, &ath5k_rates[4],
1089 sizeof(struct ieee80211_rate) * 8);
1090 sband->n_bitrates = 8;
fa1c114f 1091
63266a65 1092 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1093 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1094 AR5K_MODE_11A, max_c);
1095
d8ee398d
LR		 1096 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1097 }
63266a65 1098 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1099
b446197c 1100 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1101
1102 return 0;
fa1c114f
JS		 1103}
1104
1105/*
e30eb4ab
JA		 1106 * Set/change channels. We always reset the chip.
1107 * To accomplish this we must first cleanup any pending DMA,
1108 * then restart stuff after a la ath5k_init.
be009370
BC		 1109 *
1110 * Called with sc->lock.
fa1c114f
JS		 1111 */
1112static int
1113ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1114{
d8ee398d
LR		 1115 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1116 sc->curchan->center_freq, chan->center_freq);
1117
e30eb4ab
JA		 1118 /*
1119 * To switch channels clear any pending DMA operations;
1120 * wait long enough for the RX fifo to drain, reset the
1121 * hardware at the new frequency, and then re-enable
1122 * the relevant bits of the h/w.
1123 */
1124 return ath5k_reset(sc, chan);
fa1c114f
JS		 1125}
1126
1127static void
1128ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1129{
fa1c114f 1130 sc->curmode = mode;
d8ee398d 1131
400ec45a 1132 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1133 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1134 } else {
1135 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1136 }
fa1c114f
JS		 1137}
1138
1139static void
1140ath5k_mode_setup(struct ath5k_softc *sc)
1141{
1142 struct ath5k_hw *ah = sc->ah;
1143 u32 rfilt;
1144
1145 /* configure rx filter */
1146 rfilt = sc->filter_flags;
1147 ath5k_hw_set_rx_filter(ah, rfilt);
1148
1149 if (ath5k_hw_hasbssidmask(ah))
1150 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1151
1152 /* configure operational mode */
ccfe5552 1153 ath5k_hw_set_opmode(ah, sc->opmode);
fa1c114f 1154
ccfe5552 1155 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
fa1c114f
JS		 1156 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1157}
1158
d8ee398d 1159static inline int
63266a65
BR		 1160ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1161{
b7266047
BC		 1162 int rix;
1163
1164 /* return base rate on errors */
1165 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1166 "hw_rix out of bounds: %x\n", hw_rix))
1167 return 0;
1168
1169 rix = sc->rate_idx[sc->curband->band][hw_rix];
1170 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1171 rix = 0;
1172
1173 return rix;
d8ee398d
LR		 1174}
1175
fa1c114f
JS		 1176/***************\
1177* Buffers setup *
1178\***************/
1179
b6ea0356
BC		 1180static
1181struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1182{
db719718 1183 struct ath_common *common = ath5k_hw_common(sc->ah);
b6ea0356 1184 struct sk_buff *skb;
b6ea0356
BC		 1185
1186 /*
1187 * Allocate buffer with headroom_needed space for the
1188 * fake physical layer header at the start.
1189 */
db719718 1190 skb = ath_rxbuf_alloc(common,
dd849782 1191 common->rx_bufsize,
aeb63cfd 1192 GFP_ATOMIC);
b6ea0356
BC		 1193
1194 if (!skb) {
1195 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
dd849782 1196 common->rx_bufsize);
b6ea0356
BC		 1197 return NULL;
1198 }
b6ea0356
BC		 1199
1200 *skb_addr = pci_map_single(sc->pdev,
cc861f74
LR		 1201 skb->data, common->rx_bufsize,
1202 PCI_DMA_FROMDEVICE);
b6ea0356
BC		 1203 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1204 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1205 dev_kfree_skb(skb);
1206 return NULL;
1207 }
1208 return skb;
1209}
1210
fa1c114f
JS		 1211static int
1212ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1213{
1214 struct ath5k_hw *ah = sc->ah;
1215 struct sk_buff *skb = bf->skb;
1216 struct ath5k_desc *ds;
b5eae9ff 1217 int ret;
fa1c114f 1218
b6ea0356
BC		 1219 if (!skb) {
1220 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1221 if (!skb)
fa1c114f 1222 return -ENOMEM;
fa1c114f 1223 bf->skb = skb;
fa1c114f
JS		 1224 }
1225
1226 /*
1227 * Setup descriptors. For receive we always terminate
1228 * the descriptor list with a self-linked entry so we'll
1229 * not get overrun under high load (as can happen with a
1230 * 5212 when ANI processing enables PHY error frames).
1231 *
1232 * To insure the last descriptor is self-linked we create
1233 * each descriptor as self-linked and add it to the end. As
1234 * each additional descriptor is added the previous self-linked
1235 * entry is ``fixed'' naturally. This should be safe even
1236 * if DMA is happening. When processing RX interrupts we
1237 * never remove/process the last, self-linked, entry on the
1238 * descriptor list. This insures the hardware always has
1239 * someplace to write a new frame.
1240 */
1241 ds = bf->desc;
1242 ds->ds_link = bf->daddr; /* link to self */
1243 ds->ds_data = bf->skbaddr;
b5eae9ff
BR		 1244 ret = ah->ah_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
1245 if (ret)
1246 return ret;
fa1c114f
JS		 1247
1248 if (sc->rxlink != NULL)
1249 *sc->rxlink = bf->daddr;
1250 sc->rxlink = &ds->ds_link;
1251 return 0;
1252}
1253
2ac2927a
BC		 1254static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1255{
1256 struct ieee80211_hdr *hdr;
1257 enum ath5k_pkt_type htype;
1258 __le16 fc;
1259
1260 hdr = (struct ieee80211_hdr *)skb->data;
1261 fc = hdr->frame_control;
1262
1263 if (ieee80211_is_beacon(fc))
1264 htype = AR5K_PKT_TYPE_BEACON;
1265 else if (ieee80211_is_probe_resp(fc))
1266 htype = AR5K_PKT_TYPE_PROBE_RESP;
1267 else if (ieee80211_is_atim(fc))
1268 htype = AR5K_PKT_TYPE_ATIM;
1269 else if (ieee80211_is_pspoll(fc))
1270 htype = AR5K_PKT_TYPE_PSPOLL;
1271 else
1272 htype = AR5K_PKT_TYPE_NORMAL;
1273
1274 return htype;
1275}
1276
fa1c114f 1277static int
cec8db23 1278ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
8127fbdc 1279 struct ath5k_txq *txq, int padsize)
fa1c114f
JS		 1280{
1281 struct ath5k_hw *ah = sc->ah;
fa1c114f
JS		 1282 struct ath5k_desc *ds = bf->desc;
1283 struct sk_buff *skb = bf->skb;
a888d52d 1284 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1285 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1286 struct ieee80211_rate *rate;
1287 unsigned int mrr_rate[3], mrr_tries[3];
1288 int i, ret;
8902ff4e 1289 u16 hw_rate;
07c1e852
BC		 1290 u16 cts_rate = 0;
1291 u16 duration = 0;
8902ff4e 1292 u8 rc_flags;
fa1c114f
JS		 1293
1294 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1295
fa1c114f
JS		 1296 /* XXX endianness */
1297 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1298 PCI_DMA_TODEVICE);
1299
8902ff4e
BC		 1300 rate = ieee80211_get_tx_rate(sc->hw, info);
1301
e039fa4a 1302 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1303 flags |= AR5K_TXDESC_NOACK;
1304
8902ff4e
BC		 1305 rc_flags = info->control.rates[0].flags;
1306 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1307 rate->hw_value_short : rate->hw_value;
1308
281c56dd 1309 pktlen = skb->len;
fa1c114f 1310
8f655dde
NK		 1311 /* FIXME: If we are in g mode and rate is a CCK rate
1312 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1313 * from tx power (value is in dB units already) */
362695e1
BC		 1314 if (info->control.hw_key) {
1315 keyidx = info->control.hw_key->hw_key_idx;
1316 pktlen += info->control.hw_key->icv_len;
1317 }
07c1e852
BC		 1318 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1319 flags |= AR5K_TXDESC_RTSENA;
1320 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1321 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1322 sc->vif, pktlen, info));
1323 }
1324 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1325 flags |= AR5K_TXDESC_CTSENA;
1326 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1327 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1328 sc->vif, pktlen, info));
1329 }
fa1c114f 1330 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
8127fbdc 1331 ieee80211_get_hdrlen_from_skb(skb), padsize,
2ac2927a 1332 get_hw_packet_type(skb),
2e92e6f2 1333 (sc->power_level * 2),
8902ff4e 1334 hw_rate,
2bed03eb 1335 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
07c1e852 1336 cts_rate, duration);
fa1c114f
JS		 1337 if (ret)
1338 goto err_unmap;
1339
2f7fe870
FF		 1340 memset(mrr_rate, 0, sizeof(mrr_rate));
1341 memset(mrr_tries, 0, sizeof(mrr_tries));
1342 for (i = 0; i < 3; i++) {
1343 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1344 if (!rate)
1345 break;
1346
1347 mrr_rate[i] = rate->hw_value;
e6a9854b 1348 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1349 }
1350
1351 ah->ah_setup_mrr_tx_desc(ah, ds,
1352 mrr_rate[0], mrr_tries[0],
1353 mrr_rate[1], mrr_tries[1],
1354 mrr_rate[2], mrr_tries[2]);
1355
fa1c114f
JS		 1356 ds->ds_link = 0;
1357 ds->ds_data = bf->skbaddr;
1358
1359 spin_lock_bh(&txq->lock);
1360 list_add_tail(&bf->list, &txq->q);
fa1c114f 1361 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1362 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1363 else /* no, so only link it */
1364 *txq->link = bf->daddr;
1365
1366 txq->link = &ds->ds_link;
c6e387a2 1367 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1368 mmiowb();
fa1c114f
JS		 1369 spin_unlock_bh(&txq->lock);
1370
1371 return 0;
1372err_unmap:
1373 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1374 return ret;
1375}
1376
1377/*******************\
1378* Descriptors setup *
1379\*******************/
1380
1381static int
1382ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1383{
1384 struct ath5k_desc *ds;
1385 struct ath5k_buf *bf;
1386 dma_addr_t da;
1387 unsigned int i;
1388 int ret;
1389
1390 /* allocate descriptors */
1391 sc->desc_len = sizeof(struct ath5k_desc) *
1392 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1393 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1394 if (sc->desc == NULL) {
1395 ATH5K_ERR(sc, "can't allocate descriptors\n");
1396 ret = -ENOMEM;
1397 goto err;
1398 }
1399 ds = sc->desc;
1400 da = sc->desc_daddr;
1401 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1402 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1403
1404 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1405 sizeof(struct ath5k_buf), GFP_KERNEL);
1406 if (bf == NULL) {
1407 ATH5K_ERR(sc, "can't allocate bufptr\n");
1408 ret = -ENOMEM;
1409 goto err_free;
1410 }
1411 sc->bufptr = bf;
1412
1413 INIT_LIST_HEAD(&sc->rxbuf);
1414 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1415 bf->desc = ds;
1416 bf->daddr = da;
1417 list_add_tail(&bf->list, &sc->rxbuf);
1418 }
1419
1420 INIT_LIST_HEAD(&sc->txbuf);
1421 sc->txbuf_len = ATH_TXBUF;
1422 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1423 da += sizeof(*ds)) {
1424 bf->desc = ds;
1425 bf->daddr = da;
1426 list_add_tail(&bf->list, &sc->txbuf);
1427 }
1428
1429 /* beacon buffer */
1430 bf->desc = ds;
1431 bf->daddr = da;
1432 sc->bbuf = bf;
1433
1434 return 0;
1435err_free:
1436 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1437err:
1438 sc->desc = NULL;
1439 return ret;
1440}
1441
1442static void
1443ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1444{
1445 struct ath5k_buf *bf;
1446
1447 ath5k_txbuf_free(sc, sc->bbuf);
1448 list_for_each_entry(bf, &sc->txbuf, list)
1449 ath5k_txbuf_free(sc, bf);
1450 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1451 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1452
1453 /* Free memory associated with all descriptors */
1454 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1455
1456 kfree(sc->bufptr);
1457 sc->bufptr = NULL;
1458}
1459
1460
1461
1462
1463
1464/**************\
1465* Queues setup *
1466\**************/
1467
1468static struct ath5k_txq *
1469ath5k_txq_setup(struct ath5k_softc *sc,
1470 int qtype, int subtype)
1471{
1472 struct ath5k_hw *ah = sc->ah;
1473 struct ath5k_txq *txq;
1474 struct ath5k_txq_info qi = {
1475 .tqi_subtype = subtype,
1476 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1477 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1478 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1479 };
1480 int qnum;
1481
1482 /*
1483 * Enable interrupts only for EOL and DESC conditions.
1484 * We mark tx descriptors to receive a DESC interrupt
1485 * when a tx queue gets deep; otherwise waiting for the
1486 * EOL to reap descriptors. Note that this is done to
1487 * reduce interrupt load and this only defers reaping
1488 * descriptors, never transmitting frames. Aside from
1489 * reducing interrupts this also permits more concurrency.
1490 * The only potential downside is if the tx queue backs
1491 * up in which case the top half of the kernel may backup
1492 * due to a lack of tx descriptors.
1493 */
1494 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1495 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1496 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1497 if (qnum < 0) {
1498 /*
1499 * NB: don't print a message, this happens
1500 * normally on parts with too few tx queues
1501 */
1502 return ERR_PTR(qnum);
1503 }
1504 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1505 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1506 qnum, ARRAY_SIZE(sc->txqs));
1507 ath5k_hw_release_tx_queue(ah, qnum);
1508 return ERR_PTR(-EINVAL);
1509 }
1510 txq = &sc->txqs[qnum];
1511 if (!txq->setup) {
1512 txq->qnum = qnum;
1513 txq->link = NULL;
1514 INIT_LIST_HEAD(&txq->q);
1515 spin_lock_init(&txq->lock);
1516 txq->setup = true;
1517 }
1518 return &sc->txqs[qnum];
1519}
1520
1521static int
1522ath5k_beaconq_setup(struct ath5k_hw *ah)
1523{
1524 struct ath5k_txq_info qi = {
1525 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1526 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1527 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1528 /* NB: for dynamic turbo, don't enable any other interrupts */
1529 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1530 };
1531
1532 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1533}
1534
1535static int
1536ath5k_beaconq_config(struct ath5k_softc *sc)
1537{
1538 struct ath5k_hw *ah = sc->ah;
1539 struct ath5k_txq_info qi;
1540 int ret;
1541
1542 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1543 if (ret)
a951ae21
BC		 1544 goto err;
1545
05c914fe
JB		 1546 if (sc->opmode == NL80211_IFTYPE_AP ||
1547 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1548 /*
1549 * Always burst out beacon and CAB traffic
1550 * (aifs = cwmin = cwmax = 0)
1551 */
1552 qi.tqi_aifs = 0;
1553 qi.tqi_cw_min = 0;
1554 qi.tqi_cw_max = 0;
05c914fe 1555 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1556 /*
1557 * Adhoc mode; backoff between 0 and (2 * cw_min).
1558 */
1559 qi.tqi_aifs = 0;
1560 qi.tqi_cw_min = 0;
1561 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1562 }
1563
6d91e1d8
BR		 1564 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1565 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1566 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1567
c6e387a2 1568 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1569 if (ret) {
1570 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1571 "hardware queue!\n", __func__);
a951ae21 1572 goto err;
fa1c114f 1573 }
a951ae21
BC		 1574 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1575 if (ret)
1576 goto err;
fa1c114f 1577
a951ae21
BC		 1578 /* reconfigure cabq with ready time to 80% of beacon_interval */
1579 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1580 if (ret)
1581 goto err;
1582
1583 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1584 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1585 if (ret)
1586 goto err;
1587
1588 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1589err:
1590 return ret;
fa1c114f
JS		 1591}
1592
1593static void
1594ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1595{
1596 struct ath5k_buf *bf, *bf0;
1597
1598 /*
1599 * NB: this assumes output has been stopped and
1600 * we do not need to block ath5k_tx_tasklet
1601 */
1602 spin_lock_bh(&txq->lock);
1603 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1604 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1605
1606 ath5k_txbuf_free(sc, bf);
1607
1608 spin_lock_bh(&sc->txbuflock);
fa1c114f
JS		 1609 list_move_tail(&bf->list, &sc->txbuf);
1610 sc->txbuf_len++;
1611 spin_unlock_bh(&sc->txbuflock);
1612 }
1613 txq->link = NULL;
1614 spin_unlock_bh(&txq->lock);
1615}
1616
1617/*
1618 * Drain the transmit queues and reclaim resources.
1619 */
1620static void
1621ath5k_txq_cleanup(struct ath5k_softc *sc)
1622{
1623 struct ath5k_hw *ah = sc->ah;
1624 unsigned int i;
1625
1626 /* XXX return value */
1627 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1628 /* don't touch the hardware if marked invalid */
1629 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1630 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1631 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1632 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1633 if (sc->txqs[i].setup) {
1634 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1635 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1636 "link %p\n",
1637 sc->txqs[i].qnum,
c6e387a2 1638 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1639 sc->txqs[i].qnum),
1640 sc->txqs[i].link);
1641 }
1642 }
fa1c114f
JS		 1643
1644 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1645 if (sc->txqs[i].setup)
1646 ath5k_txq_drainq(sc, &sc->txqs[i]);
1647}
1648
1649static void
1650ath5k_txq_release(struct ath5k_softc *sc)
1651{
1652 struct ath5k_txq *txq = sc->txqs;
1653 unsigned int i;
1654
1655 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1656 if (txq->setup) {
1657 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1658 txq->setup = false;
1659 }
1660}
1661
1662
1663
1664
1665/*************\
1666* RX Handling *
1667\*************/
1668
1669/*
1670 * Enable the receive h/w following a reset.
1671 */
1672static int
1673ath5k_rx_start(struct ath5k_softc *sc)
1674{
1675 struct ath5k_hw *ah = sc->ah;
db719718 1676 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 1677 struct ath5k_buf *bf;
1678 int ret;
1679
cc861f74 1680 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
fa1c114f 1681
cc861f74
LR		 1682 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1683 common->cachelsz, common->rx_bufsize);
fa1c114f 1684
fa1c114f 1685 spin_lock_bh(&sc->rxbuflock);
26925042 1686 sc->rxlink = NULL;
fa1c114f
JS		 1687 list_for_each_entry(bf, &sc->rxbuf, list) {
1688 ret = ath5k_rxbuf_setup(sc, bf);
1689 if (ret != 0) {
1690 spin_unlock_bh(&sc->rxbuflock);
1691 goto err;
1692 }
1693 }
1694 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1695 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1696 spin_unlock_bh(&sc->rxbuflock);
1697
c6e387a2 1698 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1699 ath5k_mode_setup(sc); /* set filters, etc. */
1700 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1701
1702 return 0;
1703err:
1704 return ret;
1705}
1706
1707/*
1708 * Disable the receive h/w in preparation for a reset.
1709 */
1710static void
1711ath5k_rx_stop(struct ath5k_softc *sc)
1712{
1713 struct ath5k_hw *ah = sc->ah;
1714
c6e387a2 1715 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1716 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1717 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1718
1719 ath5k_debug_printrxbuffs(sc, ah);
1720
1721 sc->rxlink = NULL; /* just in case */
1722}
1723
1724static unsigned int
1725ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1726 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f 1727{
dc1e001b
LR		 1728 struct ath5k_hw *ah = sc->ah;
1729 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1730 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1731 unsigned int keyix, hlen;
fa1c114f 1732
b47f407b
BR		 1733 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1734 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1735 return RX_FLAG_DECRYPTED;
1736
1737 /* Apparently when a default key is used to decrypt the packet
1738 the hw does not set the index used to decrypt. In such cases
1739 get the index from the packet. */
798ee985 1740 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1741 if (ieee80211_has_protected(hdr->frame_control) &&
1742 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1743 skb->len >= hlen + 4) {
fa1c114f
JS		 1744 keyix = skb->data[hlen + 3] >> 6;
1745
dc1e001b 1746 if (test_bit(keyix, common->keymap))
fa1c114f
JS		 1747 return RX_FLAG_DECRYPTED;
1748 }
1749
1750 return 0;
1751}
1752
036cd1ec
BR		 1753
1754static void
6ba81c2c
BR		 1755ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1756 struct ieee80211_rx_status *rxs)
036cd1ec 1757{
954fecea 1758 struct ath_common *common = ath5k_hw_common(sc->ah);
6ba81c2c 1759 u64 tsf, bc_tstamp;
036cd1ec
BR		 1760 u32 hw_tu;
1761 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1762
24b56e70 1763 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1764 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
954fecea 1765 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
036cd1ec 1766 /*
6ba81c2c
BR		 1767 * Received an IBSS beacon with the same BSSID. Hardware *must*
1768 * have updated the local TSF. We have to work around various
1769 * hardware bugs, though...
036cd1ec 1770 */
6ba81c2c
BR		 1771 tsf = ath5k_hw_get_tsf64(sc->ah);
1772 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1773 hw_tu = TSF_TO_TU(tsf);
1774
1775 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1776 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1777 (unsigned long long)bc_tstamp,
1778 (unsigned long long)rxs->mactime,
1779 (unsigned long long)(rxs->mactime - bc_tstamp),
1780 (unsigned long long)tsf);
6ba81c2c
BR		 1781
1782 /*
1783 * Sometimes the HW will give us a wrong tstamp in the rx
1784 * status, causing the timestamp extension to go wrong.
1785 * (This seems to happen especially with beacon frames bigger
1786 * than 78 byte (incl. FCS))
1787 * But we know that the receive timestamp must be later than the
1788 * timestamp of the beacon since HW must have synced to that.
1789 *
1790 * NOTE: here we assume mactime to be after the frame was
1791 * received, not like mac80211 which defines it at the start.
1792 */
1793 if (bc_tstamp > rxs->mactime) {
036cd1ec 1794 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1795 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1796 (unsigned long long)rxs->mactime,
1797 (unsigned long long)tsf);
6ba81c2c 1798 rxs->mactime = tsf;
036cd1ec 1799 }
6ba81c2c
BR		 1800
1801 /*
1802 * Local TSF might have moved higher than our beacon timers,
1803 * in that case we have to update them to continue sending
1804 * beacons. This also takes care of synchronizing beacon sending
1805 * times with other stations.
1806 */
1807 if (hw_tu >= sc->nexttbtt)
1808 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1809 }
1810}
1811
b4ea449d
BR		 1812static void
1813ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1814{
1815 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1816 struct ath5k_hw *ah = sc->ah;
1817 struct ath_common *common = ath5k_hw_common(ah);
1818
1819 /* only beacons from our BSSID */
1820 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1821 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1822 return;
1823
1824 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1825 rssi);
1826
1827 /* in IBSS mode we should keep RSSI statistics per neighbour */
1828 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1829}
1830
8127fbdc
BP		 1831/*
1832 * Compute padding position. skb must contains an IEEE 802.11 frame
1833 */
1834static int ath5k_common_padpos(struct sk_buff *skb)
1835{
1836 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1837 __le16 frame_control = hdr->frame_control;
1838 int padpos = 24;
1839
1840 if (ieee80211_has_a4(frame_control)) {
1841 padpos += ETH_ALEN;
1842 }
1843 if (ieee80211_is_data_qos(frame_control)) {
1844 padpos += IEEE80211_QOS_CTL_LEN;
1845 }
1846
1847 return padpos;
1848}
1849
1850/*
1851 * This function expects a 802.11 frame and returns the number of
1852 * bytes added, or -1 if we don't have enought header room.
1853 */
1854
1855static int ath5k_add_padding(struct sk_buff *skb)
1856{
1857 int padpos = ath5k_common_padpos(skb);
1858 int padsize = padpos & 3;
1859
1860 if (padsize && skb->len>padpos) {
1861
1862 if (skb_headroom(skb) < padsize)
1863 return -1;
1864
1865 skb_push(skb, padsize);
1866 memmove(skb->data, skb->data+padsize, padpos);
1867 return padsize;
1868 }
1869
1870 return 0;
1871}
1872
1873/*
1874 * This function expects a 802.11 frame and returns the number of
1875 * bytes removed
1876 */
1877
1878static int ath5k_remove_padding(struct sk_buff *skb)
1879{
1880 int padpos = ath5k_common_padpos(skb);
1881 int padsize = padpos & 3;
1882
1883 if (padsize && skb->len>=padpos+padsize) {
1884 memmove(skb->data + padsize, skb->data, padpos);
1885 skb_pull(skb, padsize);
1886 return padsize;
1887 }
1888
1889 return 0;
1890}
1891
fa1c114f
JS		 1892static void
1893ath5k_tasklet_rx(unsigned long data)
1894{
1c5256bb 1895 struct ieee80211_rx_status *rxs;
b47f407b 1896 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1897 struct sk_buff *skb, *next_skb;
1898 dma_addr_t next_skb_addr;
fa1c114f 1899 struct ath5k_softc *sc = (void *)data;
cc861f74
LR		 1900 struct ath5k_hw *ah = sc->ah;
1901 struct ath_common *common = ath5k_hw_common(ah);
c57ca815 1902 struct ath5k_buf *bf;
fa1c114f 1903 struct ath5k_desc *ds;
fa1c114f 1904 int ret;
1c5256bb 1905 int rx_flag;
fa1c114f
JS		 1906
1907 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1908 if (list_empty(&sc->rxbuf)) {
1909 ATH5K_WARN(sc, "empty rx buf pool\n");
1910 goto unlock;
1911 }
fa1c114f 1912 do {
1c5256bb 1913 rx_flag = 0;
d6894b5b 1914
fa1c114f
JS		 1915 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1916 BUG_ON(bf->skb == NULL);
1917 skb = bf->skb;
1918 ds = bf->desc;
1919
c57ca815
BC		 1920 /* bail if HW is still using self-linked descriptor */
1921 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1922 break;
fa1c114f 1923
b47f407b 1924 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1925 if (unlikely(ret == -EINPROGRESS))
1926 break;
1927 else if (unlikely(ret)) {
1928 ATH5K_ERR(sc, "error in processing rx descriptor\n");
7644395f 1929 sc->stats.rxerr_proc++;
65872e6b 1930 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1931 return;
1932 }
1933
7644395f
BR		 1934 sc->stats.rx_all_count++;
1935
b47f407b 1936 if (unlikely(rs.rs_status)) {
7644395f
BR		 1937 if (rs.rs_status & AR5K_RXERR_CRC)
1938 sc->stats.rxerr_crc++;
1939 if (rs.rs_status & AR5K_RXERR_FIFO)
1940 sc->stats.rxerr_fifo++;
1941 if (rs.rs_status & AR5K_RXERR_PHY) {
1942 sc->stats.rxerr_phy++;
da35111a
BR		 1943 if (rs.rs_phyerr > 0 && rs.rs_phyerr < 32)
1944 sc->stats.rxerr_phy_code[rs.rs_phyerr]++;
fa1c114f 1945 goto next;
7644395f 1946 }
b47f407b 1947 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1948 /*
1949 * Decrypt error. If the error occurred
1950 * because there was no hardware key, then
1951 * let the frame through so the upper layers
1952 * can process it. This is necessary for 5210
1953 * parts which have no way to setup a ``clear''
1954 * key cache entry.
1955 *
1956 * XXX do key cache faulting
1957 */
7644395f 1958 sc->stats.rxerr_decrypt++;
b47f407b
BR		 1959 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1960 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1961 goto accept;
1962 }
b47f407b 1963 if (rs.rs_status & AR5K_RXERR_MIC) {
1c5256bb 1964 rx_flag |= RX_FLAG_MMIC_ERROR;
7644395f 1965 sc->stats.rxerr_mic++;
fa1c114f
JS		 1966 goto accept;
1967 }
1968
1969 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1970 if ((rs.rs_status &
1971 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1972 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1973 goto next;
1974 }
9637e516
LR		 1975
1976 if (unlikely(rs.rs_more)) {
1977 sc->stats.rxerr_jumbo++;
1978 goto next;
1979
1980 }
fa1c114f 1981accept:
b6ea0356
BC		 1982 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1983
1984 /*
1985 * If we can't replace bf->skb with a new skb under memory
1986 * pressure, just skip this packet
1987 */
1988 if (!next_skb)
1989 goto next;
1990
cc861f74 1991 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
fa1c114f 1992 PCI_DMA_FROMDEVICE);
b47f407b 1993 skb_put(skb, rs.rs_datalen);
fa1c114f 1994
0fe45b1d
BP		 1995 /* The MAC header is padded to have 32-bit boundary if the
1996 * packet payload is non-zero. The general calculation for
1997 * padsize would take into account odd header lengths:
1998 * padsize = (4 - hdrlen % 4) % 4; However, since only
1999 * even-length headers are used, padding can only be 0 or 2
2000 * bytes and we can optimize this a bit. In addition, we must
2001 * not try to remove padding from short control frames that do
2002 * not have payload. */
8127fbdc
BP		 2003 ath5k_remove_padding(skb);
2004
1c5256bb 2005 rxs = IEEE80211_SKB_RXCB(skb);
fa1c114f 2006
c0e1899b
BR		 2007 /*
2008 * always extend the mac timestamp, since this information is
2009 * also needed for proper IBSS merging.
2010 *
2011 * XXX: it might be too late to do it here, since rs_tstamp is
2012 * 15bit only. that means TSF extension has to be done within
2013 * 32768usec (about 32ms). it might be necessary to move this to
2014 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 2015 *
2016 * Unfortunately we don't know when the hardware takes the rx
2017 * timestamp (beginning of phy frame, data frame, end of rx?).
2018 * The only thing we know is that it is hardware specific...
2019 * On AR5213 it seems the rx timestamp is at the end of the
2020 * frame, but i'm not sure.
2021 *
2022 * NOTE: mac80211 defines mactime at the beginning of the first
2023 * data symbol. Since we don't have any time references it's
2024 * impossible to comply to that. This affects IBSS merge only
2025 * right now, so it's not too bad...
c0e1899b 2026 */
1c5256bb
BC		 2027 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
2028 rxs->flag = rx_flag | RX_FLAG_TSFT;
c0e1899b 2029
1c5256bb
BC		 2030 rxs->freq = sc->curchan->center_freq;
2031 rxs->band = sc->curband->band;
fa1c114f 2032
54c7c91e 2033 rxs->signal = sc->ah->ah_noise_floor + rs.rs_rssi;
6e0e0bf8 2034
1c5256bb 2035 rxs->antenna = rs.rs_antenna;
604eeadd
BR		 2036
2037 if (rs.rs_antenna > 0 && rs.rs_antenna < 5)
2038 sc->stats.antenna_rx[rs.rs_antenna]++;
2039 else
2040 sc->stats.antenna_rx[0]++; /* invalid */
2041
1c5256bb
BC		 2042 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
2043 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 2044
1c5256bb
BC		 2045 if (rxs->rate_idx >= 0 && rs.rs_rate ==
2046 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
2047 rxs->flag |= RX_FLAG_SHORTPRE;
06303352 2048
fa1c114f
JS		 2049 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
2050
b4ea449d
BR		 2051 ath5k_update_beacon_rssi(sc, skb, rs.rs_rssi);
2052
036cd1ec 2053 /* check beacons in IBSS mode */
05c914fe 2054 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1c5256bb 2055 ath5k_check_ibss_tsf(sc, skb, rxs);
036cd1ec 2056
f1d58c25 2057 ieee80211_rx(sc->hw, skb);
b6ea0356
BC		 2058
2059 bf->skb = next_skb;
2060 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 2061next:
2062 list_move_tail(&bf->list, &sc->rxbuf);
2063 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 2064unlock:
fa1c114f
JS		 2065 spin_unlock(&sc->rxbuflock);
2066}
2067
2068
2069
2070
2071/*************\
2072* TX Handling *
2073\*************/
2074
2075static void
2076ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2077{
b47f407b 2078 struct ath5k_tx_status ts = {};
fa1c114f
JS		 2079 struct ath5k_buf *bf, *bf0;
2080 struct ath5k_desc *ds;
2081 struct sk_buff *skb;
e039fa4a 2082 struct ieee80211_tx_info *info;
2f7fe870 2083 int i, ret;
fa1c114f
JS		 2084
2085 spin_lock(&txq->lock);
2086 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
2087 ds = bf->desc;
2088
a05988bb
BC		 2089 /*
2090 * It's possible that the hardware can say the buffer is
2091 * completed when it hasn't yet loaded the ds_link from
2092 * host memory and moved on. If there are more TX
2093 * descriptors in the queue, wait for TXDP to change
2094 * before processing this one.
2095 */
2096 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
2097 !list_is_last(&bf->list, &txq->q))
2098 break;
2099
b47f407b 2100 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 2101 if (unlikely(ret == -EINPROGRESS))
2102 break;
2103 else if (unlikely(ret)) {
2104 ATH5K_ERR(sc, "error %d while processing queue %u\n",
2105 ret, txq->qnum);
2106 break;
2107 }
2108
7644395f 2109 sc->stats.tx_all_count++;
fa1c114f 2110 skb = bf->skb;
a888d52d 2111 info = IEEE80211_SKB_CB(skb);
fa1c114f 2112 bf->skb = NULL;
e039fa4a 2113
fa1c114f
JS		 2114 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2115 PCI_DMA_TODEVICE);
2116
e6a9854b 2117 ieee80211_tx_info_clear_status(info);
2f7fe870 2118 for (i = 0; i < 4; i++) {
e6a9854b
JB		 2119 struct ieee80211_tx_rate *r =
2120 &info->status.rates[i];
2f7fe870
FF		 2121
2122 if (ts.ts_rate[i]) {
e6a9854b
JB		 2123 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2124 r->count = ts.ts_retry[i];
2f7fe870 2125 } else {
e6a9854b
JB		 2126 r->idx = -1;
2127 r->count = 0;
2f7fe870
FF		 2128 }
2129 }
2130
e6a9854b
JB		 2131 /* count the successful attempt as well */
2132 info->status.rates[ts.ts_final_idx].count++;
2133
b47f407b 2134 if (unlikely(ts.ts_status)) {
495391d7 2135 sc->stats.ack_fail++;
7644395f 2136 if (ts.ts_status & AR5K_TXERR_FILT) {
e039fa4a 2137 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
7644395f
BR		 2138 sc->stats.txerr_filt++;
2139 }
2140 if (ts.ts_status & AR5K_TXERR_XRETRY)
2141 sc->stats.txerr_retry++;
2142 if (ts.ts_status & AR5K_TXERR_FIFO)
2143 sc->stats.txerr_fifo++;
fa1c114f 2144 } else {
e039fa4a
JB		 2145 info->flags |= IEEE80211_TX_STAT_ACK;
2146 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 2147 }
2148
8127fbdc
BP		 2149 /*
2150 * Remove MAC header padding before giving the frame
2151 * back to mac80211.
2152 */
2153 ath5k_remove_padding(skb);
2154
604eeadd
BR		 2155 if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2156 sc->stats.antenna_tx[ts.ts_antenna]++;
2157 else
2158 sc->stats.antenna_tx[0]++; /* invalid */
2159
e039fa4a 2160 ieee80211_tx_status(sc->hw, skb);
fa1c114f
JS		 2161
2162 spin_lock(&sc->txbuflock);
fa1c114f
JS		 2163 list_move_tail(&bf->list, &sc->txbuf);
2164 sc->txbuf_len++;
2165 spin_unlock(&sc->txbuflock);
2166 }
2167 if (likely(list_empty(&txq->q)))
2168 txq->link = NULL;
2169 spin_unlock(&txq->lock);
2170 if (sc->txbuf_len > ATH_TXBUF / 5)
2171 ieee80211_wake_queues(sc->hw);
2172}
2173
2174static void
2175ath5k_tasklet_tx(unsigned long data)
2176{
8784d2ee 2177 int i;
fa1c114f
JS		 2178 struct ath5k_softc *sc = (void *)data;
2179
8784d2ee
BC		 2180 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2181 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2182 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 2183}
2184
2185
fa1c114f
JS		 2186/*****************\
2187* Beacon handling *
2188\*****************/
2189
2190/*
2191 * Setup the beacon frame for transmit.
2192 */
2193static int
e039fa4a 2194ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2195{
2196 struct sk_buff *skb = bf->skb;
a888d52d 2197 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2198 struct ath5k_hw *ah = sc->ah;
2199 struct ath5k_desc *ds;
2bed03eb
NK		 2200 int ret = 0;
2201 u8 antenna;
fa1c114f 2202 u32 flags;
8127fbdc 2203 const int padsize = 0;
fa1c114f
JS		 2204
2205 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2206 PCI_DMA_TODEVICE);
2207 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2208 "skbaddr %llx\n", skb, skb->data, skb->len,
2209 (unsigned long long)bf->skbaddr);
8d8bb39b 2210 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2211 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2212 return -EIO;
2213 }
2214
2215 ds = bf->desc;
2bed03eb 2216 antenna = ah->ah_tx_ant;
fa1c114f
JS		 2217
2218 flags = AR5K_TXDESC_NOACK;
05c914fe 2219 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2220 ds->ds_link = bf->daddr; /* self-linked */
2221 flags |= AR5K_TXDESC_VEOL;
2bed03eb 2222 } else
fa1c114f 2223 ds->ds_link = 0;
2bed03eb
NK		 2224
2225 /*
2226 * If we use multiple antennas on AP and use
2227 * the Sectored AP scenario, switch antenna every
2228 * 4 beacons to make sure everybody hears our AP.
2229 * When a client tries to associate, hw will keep
2230 * track of the tx antenna to be used for this client
2231 * automaticaly, based on ACKed packets.
2232 *
2233 * Note: AP still listens and transmits RTS on the
2234 * default antenna which is supposed to be an omni.
2235 *
2236 * Note2: On sectored scenarios it's possible to have
2237 * multiple antennas (1omni -the default- and 14 sectors)
2238 * so if we choose to actually support this mode we need
2239 * to allow user to set how many antennas we have and tweak
2240 * the code below to send beacons on all of them.
2241 */
2242 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2243 antenna = sc->bsent & 4 ? 2 : 1;
2244
fa1c114f 2245
8f655dde
NK		 2246 /* FIXME: If we are in g mode and rate is a CCK rate
2247 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2248 * from tx power (value is in dB units already) */
fa1c114f 2249 ds->ds_data = bf->skbaddr;
281c56dd 2250 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 2251 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 2252 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2253 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2254 1, AR5K_TXKEYIX_INVALID,
400ec45a 2255 antenna, flags, 0, 0);
fa1c114f
JS		 2256 if (ret)
2257 goto err_unmap;
2258
2259 return 0;
2260err_unmap:
2261 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2262 return ret;
2263}
2264
2265/*
2266 * Transmit a beacon frame at SWBA. Dynamic updates to the
2267 * frame contents are done as needed and the slot time is
2268 * also adjusted based on current state.
2269 *
acf3c1a5
BC		 2270 * This is called from software irq context (beacontq or restq
2271 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2272 */
2273static void
2274ath5k_beacon_send(struct ath5k_softc *sc)
2275{
2276 struct ath5k_buf *bf = sc->bbuf;
2277 struct ath5k_hw *ah = sc->ah;
cec8db23 2278 struct sk_buff *skb;
fa1c114f 2279
be9b7259 2280 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2281
05c914fe
JB		 2282 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2283 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2284 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2285 return;
2286 }
2287 /*
2288 * Check if the previous beacon has gone out. If
2289 * not don't don't try to post another, skip this
2290 * period and wait for the next. Missed beacons
2291 * indicate a problem and should not occur. If we
2292 * miss too many consecutive beacons reset the device.
2293 */
2294 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2295 sc->bmisscount++;
be9b7259 2296 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2297 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2298 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2299 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2300 "stuck beacon time (%u missed)\n",
2301 sc->bmisscount);
2302 tasklet_schedule(&sc->restq);
2303 }
2304 return;
2305 }
2306 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2307 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2308 "resume beacon xmit after %u misses\n",
2309 sc->bmisscount);
2310 sc->bmisscount = 0;
2311 }
2312
2313 /*
2314 * Stop any current dma and put the new frame on the queue.
2315 * This should never fail since we check above that no frames
2316 * are still pending on the queue.
2317 */
2318 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2319 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2320 /* NB: hw still stops DMA, so proceed */
2321 }
fa1c114f 2322
1071db86
BC		 2323 /* refresh the beacon for AP mode */
2324 if (sc->opmode == NL80211_IFTYPE_AP)
2325 ath5k_beacon_update(sc->hw, sc->vif);
2326
c6e387a2
NK		 2327 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2328 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2329 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2330 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2331
cec8db23
BC		 2332 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2333 while (skb) {
2334 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2335 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2336 }
2337
fa1c114f
JS		 2338 sc->bsent++;
2339}
2340
2341
9804b98d
BR		 2342/**
2343 * ath5k_beacon_update_timers - update beacon timers
2344 *
2345 * @sc: struct ath5k_softc pointer we are operating on
2346 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2347 * beacon timer update based on the current HW TSF.
2348 *
2349 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2350 * of a received beacon or the current local hardware TSF and write it to the
2351 * beacon timer registers.
2352 *
2353 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2354 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2355 * when we otherwise know we have to update the timers, but we keep it in this
2356 * function to have it all together in one place.
2357 */
fa1c114f 2358static void
9804b98d 2359ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2360{
2361 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2362 u32 nexttbtt, intval, hw_tu, bc_tu;
2363 u64 hw_tsf;
fa1c114f
JS		 2364
2365 intval = sc->bintval & AR5K_BEACON_PERIOD;
2366 if (WARN_ON(!intval))
2367 return;
2368
9804b98d
BR		 2369 /* beacon TSF converted to TU */
2370 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2371
9804b98d
BR		 2372 /* current TSF converted to TU */
2373 hw_tsf = ath5k_hw_get_tsf64(ah);
2374 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2375
9804b98d
BR		 2376#define FUDGE 3
2377 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2378 if (bc_tsf == -1) {
2379 /*
2380 * no beacons received, called internally.
2381 * just need to refresh timers based on HW TSF.
2382 */
2383 nexttbtt = roundup(hw_tu + FUDGE, intval);
2384 } else if (bc_tsf == 0) {
2385 /*
2386 * no beacon received, probably called by ath5k_reset_tsf().
2387 * reset TSF to start with 0.
2388 */
2389 nexttbtt = intval;
2390 intval |= AR5K_BEACON_RESET_TSF;
2391 } else if (bc_tsf > hw_tsf) {
2392 /*
2393 * beacon received, SW merge happend but HW TSF not yet updated.
2394 * not possible to reconfigure timers yet, but next time we
2395 * receive a beacon with the same BSSID, the hardware will
2396 * automatically update the TSF and then we need to reconfigure
2397 * the timers.
2398 */
2399 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2400 "need to wait for HW TSF sync\n");
2401 return;
2402 } else {
2403 /*
2404 * most important case for beacon synchronization between STA.
2405 *
2406 * beacon received and HW TSF has been already updated by HW.
2407 * update next TBTT based on the TSF of the beacon, but make
2408 * sure it is ahead of our local TSF timer.
2409 */
2410 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2411 }
2412#undef FUDGE
fa1c114f 2413
036cd1ec
BR		 2414 sc->nexttbtt = nexttbtt;
2415
fa1c114f 2416 intval |= AR5K_BEACON_ENA;
fa1c114f 2417 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2418
2419 /*
2420 * debugging output last in order to preserve the time critical aspect
2421 * of this function
2422 */
2423 if (bc_tsf == -1)
2424 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2425 "reconfigured timers based on HW TSF\n");
2426 else if (bc_tsf == 0)
2427 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2428 "reset HW TSF and timers\n");
2429 else
2430 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2431 "updated timers based on beacon TSF\n");
2432
2433 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2434 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2435 (unsigned long long) bc_tsf,
2436 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2437 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2438 intval & AR5K_BEACON_PERIOD,
2439 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2440 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2441}
2442
2443
036cd1ec
BR		 2444/**
2445 * ath5k_beacon_config - Configure the beacon queues and interrupts
2446 *
2447 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2448 *
036cd1ec 2449 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2450 * interrupts to detect TSF updates only.
fa1c114f
JS		 2451 */
2452static void
2453ath5k_beacon_config(struct ath5k_softc *sc)
2454{
2455 struct ath5k_hw *ah = sc->ah;
b5f03956 2456 unsigned long flags;
fa1c114f 2457
21800491 2458 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2459 sc->bmisscount = 0;
dc1968e7 2460 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2461
21800491 2462 if (sc->enable_beacon) {
fa1c114f 2463 /*
036cd1ec
BR		 2464 * In IBSS mode we use a self-linked tx descriptor and let the
2465 * hardware send the beacons automatically. We have to load it
fa1c114f 2466 * only once here.
036cd1ec 2467 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2468 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2469 */
2470 ath5k_beaconq_config(sc);
fa1c114f 2471
036cd1ec
BR		 2472 sc->imask |= AR5K_INT_SWBA;
2473
da966bca 2474 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2475 if (ath5k_hw_hasveol(ah))
da966bca 2476 ath5k_beacon_send(sc);
da966bca
JS		 2477 } else
2478 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 2479 } else {
2480 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 2481 }
fa1c114f 2482
c6e387a2 2483 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2484 mmiowb();
2485 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2486}
2487
428cbd4f
NK		 2488static void ath5k_tasklet_beacon(unsigned long data)
2489{
2490 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2491
2492 /*
2493 * Software beacon alert--time to send a beacon.
2494 *
2495 * In IBSS mode we use this interrupt just to
2496 * keep track of the next TBTT (target beacon
2497 * transmission time) in order to detect wether
2498 * automatic TSF updates happened.
2499 */
2500 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2501 /* XXX: only if VEOL suppported */
2502 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2503 sc->nexttbtt += sc->bintval;
2504 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2505 "SWBA nexttbtt: %x hw_tu: %x "
2506 "TSF: %llx\n",
2507 sc->nexttbtt,
2508 TSF_TO_TU(tsf),
2509 (unsigned long long) tsf);
2510 } else {
2511 spin_lock(&sc->block);
2512 ath5k_beacon_send(sc);
2513 spin_unlock(&sc->block);
2514 }
2515}
2516
fa1c114f
JS		 2517
2518/********************\
2519* Interrupt handling *
2520\********************/
2521
2522static int
bb2becac 2523ath5k_init(struct ath5k_softc *sc)
fa1c114f 2524{
bc1b32d6
EO		 2525 struct ath5k_hw *ah = sc->ah;
2526 int ret, i;
fa1c114f
JS		 2527
2528 mutex_lock(&sc->lock);
2529
2530 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2531
2532 /*
2533 * Stop anything previously setup. This is safe
2534 * no matter this is the first time through or not.
2535 */
2536 ath5k_stop_locked(sc);
2537
2538 /*
2539 * The basic interface to setting the hardware in a good
2540 * state is ``reset''. On return the hardware is known to
2541 * be powered up and with interrupts disabled. This must
2542 * be followed by initialization of the appropriate bits
2543 * and then setup of the interrupt mask.
2544 */
d8ee398d
LR		 2545 sc->curchan = sc->hw->conf.channel;
2546 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2547 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2548 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2111ac0d
BR		 2549 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2550
209d889b 2551 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2552 if (ret)
2553 goto done;
fa1c114f 2554
e6a3b616
TD		 2555 ath5k_rfkill_hw_start(ah);
2556
bc1b32d6
EO		 2557 /*
2558 * Reset the key cache since some parts do not reset the
2559 * contents on initial power up or resume from suspend.
2560 */
2561 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2562 ath5k_hw_reset_key(ah, i);
2563
0edc9a67 2564 ath5k_hw_set_ack_bitrate_high(ah, true);
fa1c114f
JS		 2565 ret = 0;
2566done:
274c7c36 2567 mmiowb();
fa1c114f
JS		 2568 mutex_unlock(&sc->lock);
2569 return ret;
2570}
2571
2572static int
2573ath5k_stop_locked(struct ath5k_softc *sc)
2574{
2575 struct ath5k_hw *ah = sc->ah;
2576
2577 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2578 test_bit(ATH_STAT_INVALID, sc->status));
2579
2580 /*
2581 * Shutdown the hardware and driver:
2582 * stop output from above
2583 * disable interrupts
2584 * turn off timers
2585 * turn off the radio
2586 * clear transmit machinery
2587 * clear receive machinery
2588 * drain and release tx queues
2589 * reclaim beacon resources
2590 * power down hardware
2591 *
2592 * Note that some of this work is not possible if the
2593 * hardware is gone (invalid).
2594 */
2595 ieee80211_stop_queues(sc->hw);
2596
2597 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2598 ath5k_led_off(sc);
c6e387a2 2599 ath5k_hw_set_imr(ah, 0);
274c7c36 2600 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2601 }
2602 ath5k_txq_cleanup(sc);
2603 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2604 ath5k_rx_stop(sc);
2605 ath5k_hw_phy_disable(ah);
2606 } else
2607 sc->rxlink = NULL;
2608
2609 return 0;
2610}
2611
2612/*
2613 * Stop the device, grabbing the top-level lock to protect
2614 * against concurrent entry through ath5k_init (which can happen
2615 * if another thread does a system call and the thread doing the
2616 * stop is preempted).
2617 */
2618static int
bb2becac 2619ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2620{
2621 int ret;
2622
2623 mutex_lock(&sc->lock);
2624 ret = ath5k_stop_locked(sc);
2625 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2626 /*
edd7fc70
NK		 2627 * Don't set the card in full sleep mode!
2628 *
2629 * a) When the device is in this state it must be carefully
2630 * woken up or references to registers in the PCI clock
2631 * domain may freeze the bus (and system). This varies
2632 * by chip and is mostly an issue with newer parts
2633 * (madwifi sources mentioned srev >= 0x78) that go to
2634 * sleep more quickly.
2635 *
2636 * b) On older chips full sleep results a weird behaviour
2637 * during wakeup. I tested various cards with srev < 0x78
2638 * and they don't wake up after module reload, a second
2639 * module reload is needed to bring the card up again.
2640 *
2641 * Until we figure out what's going on don't enable
2642 * full chip reset on any chip (this is what Legacy HAL
2643 * and Sam's HAL do anyway). Instead Perform a full reset
2644 * on the device (same as initial state after attach) and
2645 * leave it idle (keep MAC/BB on warm reset) */
2646 ret = ath5k_hw_on_hold(sc->ah);
2647
2648 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2649 "putting device to sleep\n");
fa1c114f
JS		 2650 }
2651 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2652
274c7c36 2653 mmiowb();
fa1c114f
JS		 2654 mutex_unlock(&sc->lock);
2655
10488f8a
JS		 2656 tasklet_kill(&sc->rxtq);
2657 tasklet_kill(&sc->txtq);
2658 tasklet_kill(&sc->restq);
6e220662 2659 tasklet_kill(&sc->calib);
acf3c1a5 2660 tasklet_kill(&sc->beacontq);
2111ac0d 2661 tasklet_kill(&sc->ani_tasklet);
fa1c114f 2662
e6a3b616
TD		 2663 ath5k_rfkill_hw_stop(sc->ah);
2664
fa1c114f
JS		 2665 return ret;
2666}
2667
6a8a3f6b
BR		 2668static void
2669ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2670{
2111ac0d
BR		 2671 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2672 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2673 /* run ANI only when full calibration is not active */
2674 ah->ah_cal_next_ani = jiffies +
2675 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2676 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2677
2678 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2679 ah->ah_cal_next_full = jiffies +
2680 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2681 tasklet_schedule(&ah->ah_sc->calib);
2682 }
2683 /* we could use SWI to generate enough interrupts to meet our
2684 * calibration interval requirements, if necessary:
2685 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2686}
2687
fa1c114f
JS		 2688static irqreturn_t
2689ath5k_intr(int irq, void *dev_id)
2690{
2691 struct ath5k_softc *sc = dev_id;
2692 struct ath5k_hw *ah = sc->ah;
2693 enum ath5k_int status;
2694 unsigned int counter = 1000;
2695
2696 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2697 !ath5k_hw_is_intr_pending(ah)))
2698 return IRQ_NONE;
2699
2700 do {
fa1c114f
JS		 2701 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2702 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2703 status, sc->imask);
fa1c114f
JS		 2704 if (unlikely(status & AR5K_INT_FATAL)) {
2705 /*
2706 * Fatal errors are unrecoverable.
2707 * Typically these are caused by DMA errors.
2708 */
2709 tasklet_schedule(&sc->restq);
2710 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2711 /*
2712 * Receive buffers are full. Either the bus is busy or
2713 * the CPU is not fast enough to process all received
2714 * frames.
2715 * Older chipsets need a reset to come out of this
2716 * condition, but we treat it as RX for newer chips.
2717 * We don't know exactly which versions need a reset -
2718 * this guess is copied from the HAL.
2719 */
2720 sc->stats.rxorn_intr++;
2721 if (ah->ah_mac_srev < AR5K_SREV_AR5212)
2722 tasklet_schedule(&sc->restq);
2723 else
2724 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2725 } else {
2726 if (status & AR5K_INT_SWBA) {
56d2ac76 2727 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2728 }
2729 if (status & AR5K_INT_RXEOL) {
2730 /*
2731 * NB: the hardware should re-read the link when
2732 * RXE bit is written, but it doesn't work at
2733 * least on older hardware revs.
2734 */
2735 sc->rxlink = NULL;
2736 }
2737 if (status & AR5K_INT_TXURN) {
2738 /* bump tx trigger level */
2739 ath5k_hw_update_tx_triglevel(ah, true);
2740 }
4c674c60 2741 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2742 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2743 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2744 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2745 tasklet_schedule(&sc->txtq);
2746 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2747 /* TODO */
fa1c114f
JS		 2748 }
2749 if (status & AR5K_INT_MIB) {
2111ac0d 2750 sc->stats.mib_intr++;
495391d7 2751 ath5k_hw_update_mib_counters(ah);
2111ac0d 2752 ath5k_ani_mib_intr(ah);
fa1c114f 2753 }
e6a3b616 2754 if (status & AR5K_INT_GPIO)
e6a3b616 2755 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2756
fa1c114f 2757 }
2516baa6 2758 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2759
2760 if (unlikely(!counter))
2761 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2762
6a8a3f6b 2763 ath5k_intr_calibration_poll(ah);
6e220662 2764
fa1c114f
JS		 2765 return IRQ_HANDLED;
2766}
2767
2768static void
2769ath5k_tasklet_reset(unsigned long data)
2770{
2771 struct ath5k_softc *sc = (void *)data;
2772
d7dc1003 2773 ath5k_reset_wake(sc);
fa1c114f
JS		 2774}
2775
2776/*
2777 * Periodically recalibrate the PHY to account
2778 * for temperature/environment changes.
2779 */
2780static void
6e220662 2781ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2782{
2783 struct ath5k_softc *sc = (void *)data;
2784 struct ath5k_hw *ah = sc->ah;
2785
6e220662 2786 /* Only full calibration for now */
e65e1d77 2787 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662
NK		 2788
2789 /* Stop queues so that calibration
2790 * doesn't interfere with tx */
2791 ieee80211_stop_queues(sc->hw);
2792
fa1c114f 2793 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2794 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2795 sc->curchan->hw_value);
fa1c114f 2796
6f3b414a 2797 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2798 /*
2799 * Rfgain is out of bounds, reset the chip
2800 * to load new gain values.
2801 */
2802 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
6b5d117e 2803 ath5k_reset(sc, sc->curchan);
fa1c114f
JS		 2804 }
2805 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2806 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2807 ieee80211_frequency_to_channel(
2808 sc->curchan->center_freq));
fa1c114f 2809
6e220662
NK		 2810 /* Wake queues */
2811 ieee80211_wake_queues(sc->hw);
2812
e65e1d77 2813 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2814}
2815
2816
2111ac0d
BR		 2817static void
2818ath5k_tasklet_ani(unsigned long data)
2819{
2820 struct ath5k_softc *sc = (void *)data;
2821 struct ath5k_hw *ah = sc->ah;
2822
2823 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2824 ath5k_ani_calibration(ah);
2825 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2826}
2827
2828
fa1c114f
JS		 2829/********************\
2830* Mac80211 functions *
2831\********************/
2832
2833static int
e039fa4a 2834ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
cec8db23
BC		 2835{
2836 struct ath5k_softc *sc = hw->priv;
2837
2838 return ath5k_tx_queue(hw, skb, sc->txq);
2839}
2840
2841static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2842 struct ath5k_txq *txq)
fa1c114f
JS		 2843{
2844 struct ath5k_softc *sc = hw->priv;
2845 struct ath5k_buf *bf;
2846 unsigned long flags;
0fe45b1d 2847 int padsize;
fa1c114f
JS		 2848
2849 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2850
05c914fe 2851 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2852 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2853
2854 /*
2855 * the hardware expects the header padded to 4 byte boundaries
2856 * if this is not the case we add the padding after the header
2857 */
8127fbdc
BP		 2858 padsize = ath5k_add_padding(skb);
2859 if (padsize < 0) {
2860 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2861 " headroom to pad");
2862 goto drop_packet;
fa1c114f
JS		 2863 }
2864
fa1c114f
JS		 2865 spin_lock_irqsave(&sc->txbuflock, flags);
2866 if (list_empty(&sc->txbuf)) {
2867 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2868 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2869 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2870 goto drop_packet;
fa1c114f
JS		 2871 }
2872 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2873 list_del(&bf->list);
2874 sc->txbuf_len--;
2875 if (list_empty(&sc->txbuf))
2876 ieee80211_stop_queues(hw);
2877 spin_unlock_irqrestore(&sc->txbuflock, flags);
2878
2879 bf->skb = skb;
2880
8127fbdc 2881 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
fa1c114f
JS		 2882 bf->skb = NULL;
2883 spin_lock_irqsave(&sc->txbuflock, flags);
2884 list_add_tail(&bf->list, &sc->txbuf);
2885 sc->txbuf_len++;
2886 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2887 goto drop_packet;
fa1c114f 2888 }
5a0fe8ac 2889 return NETDEV_TX_OK;
fa1c114f 2890
5a0fe8ac
BC		 2891drop_packet:
2892 dev_kfree_skb_any(skb);
71ef99c8 2893 return NETDEV_TX_OK;
fa1c114f
JS		 2894}
2895
209d889b
BC		 2896/*
2897 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2898 * and change to the given channel.
2899 */
fa1c114f 2900static int
209d889b 2901ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2902{
fa1c114f
JS		 2903 struct ath5k_hw *ah = sc->ah;
2904 int ret;
2905
2906 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2907
209d889b 2908 if (chan) {
c6e387a2 2909 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2910 ath5k_txq_cleanup(sc);
2911 ath5k_rx_stop(sc);
209d889b
BC		 2912
2913 sc->curchan = chan;
2914 sc->curband = &sc->sbands[chan->band];
d7dc1003 2915 }
3355443a 2916 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2917 if (ret) {
fa1c114f
JS		 2918 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2919 goto err;
2920 }
d7dc1003 2921
fa1c114f 2922 ret = ath5k_rx_start(sc);
d7dc1003 2923 if (ret) {
fa1c114f
JS		 2924 ATH5K_ERR(sc, "can't start recv logic\n");
2925 goto err;
2926 }
d7dc1003 2927
2111ac0d
BR		 2928 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2929
fa1c114f 2930 /*
d7dc1003
JS		 2931 * Change channels and update the h/w rate map if we're switching;
2932 * e.g. 11a to 11b/g.
2933 *
2934 * We may be doing a reset in response to an ioctl that changes the
2935 * channel so update any state that might change as a result.
fa1c114f
JS		 2936 *
2937 * XXX needed?
2938 */
2939/* ath5k_chan_change(sc, c); */
fa1c114f 2940
d7dc1003
JS		 2941 ath5k_beacon_config(sc);
2942 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2943
2944 return 0;
2945err:
2946 return ret;
2947}
2948
d7dc1003
JS		 2949static int
2950ath5k_reset_wake(struct ath5k_softc *sc)
2951{
2952 int ret;
2953
209d889b 2954 ret = ath5k_reset(sc, sc->curchan);
d7dc1003
JS		 2955 if (!ret)
2956 ieee80211_wake_queues(sc->hw);
2957
2958 return ret;
2959}
2960
fa1c114f
JS		 2961static int ath5k_start(struct ieee80211_hw *hw)
2962{
bb2becac 2963 return ath5k_init(hw->priv);
fa1c114f
JS		 2964}
2965
2966static void ath5k_stop(struct ieee80211_hw *hw)
2967{
bb2becac 2968 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2969}
2970
2971static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 2972 struct ieee80211_vif *vif)
fa1c114f
JS		 2973{
2974 struct ath5k_softc *sc = hw->priv;
2975 int ret;
2976
2977 mutex_lock(&sc->lock);
32bfd35d 2978 if (sc->vif) {
fa1c114f
JS		 2979 ret = 0;
2980 goto end;
2981 }
2982
1ed32e4f 2983 sc->vif = vif;
fa1c114f 2984
1ed32e4f 2985 switch (vif->type) {
da966bca 2986 case NL80211_IFTYPE_AP:
05c914fe
JB		 2987 case NL80211_IFTYPE_STATION:
2988 case NL80211_IFTYPE_ADHOC:
b706e65b 2989 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2990 case NL80211_IFTYPE_MONITOR:
1ed32e4f 2991 sc->opmode = vif->type;
fa1c114f
JS		 2992 break;
2993 default:
2994 ret = -EOPNOTSUPP;
2995 goto end;
2996 }
67d2e2df 2997
ccfe5552
BR		 2998 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
2999
1ed32e4f 3000 ath5k_hw_set_lladdr(sc->ah, vif->addr);
ae6f53f2 3001 ath5k_mode_setup(sc);
67d2e2df 3002
fa1c114f
JS		 3003 ret = 0;
3004end:
3005 mutex_unlock(&sc->lock);
3006 return ret;
3007}
3008
3009static void
3010ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3011 struct ieee80211_vif *vif)
fa1c114f
JS		 3012{
3013 struct ath5k_softc *sc = hw->priv;
0e149cf5 3014 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 3015
3016 mutex_lock(&sc->lock);
1ed32e4f 3017 if (sc->vif != vif)
fa1c114f
JS		 3018 goto end;
3019
0e149cf5 3020 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 3021 sc->vif = NULL;
fa1c114f
JS		 3022end:
3023 mutex_unlock(&sc->lock);
3024}
3025
d8ee398d
LR		 3026/*
3027 * TODO: Phy disable/diversity etc
3028 */
fa1c114f 3029static int
e8975581 3030ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 3031{
3032 struct ath5k_softc *sc = hw->priv;
a0823810 3033 struct ath5k_hw *ah = sc->ah;
e8975581 3034 struct ieee80211_conf *conf = &hw->conf;
2bed03eb 3035 int ret = 0;
be009370
BC		 3036
3037 mutex_lock(&sc->lock);
fa1c114f 3038
e30eb4ab
JA		 3039 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3040 ret = ath5k_chan_set(sc, conf->channel);
3041 if (ret < 0)
3042 goto unlock;
3043 }
2bed03eb 3044
a0823810
NK		 3045 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3046 (sc->power_level != conf->power_level)) {
3047 sc->power_level = conf->power_level;
3048
3049 /* Half dB steps */
3050 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3051 }
fa1c114f 3052
2bed03eb
NK		 3053 /* TODO:
3054 * 1) Move this on config_interface and handle each case
3055 * separately eg. when we have only one STA vif, use
3056 * AR5K_ANTMODE_SINGLE_AP
3057 *
3058 * 2) Allow the user to change antenna mode eg. when only
3059 * one antenna is present
3060 *
3061 * 3) Allow the user to set default/tx antenna when possible
3062 *
3063 * 4) Default mode should handle 90% of the cases, together
3064 * with fixed a/b and single AP modes we should be able to
3065 * handle 99%. Sectored modes are extreme cases and i still
3066 * haven't found a usage for them. If we decide to support them,
3067 * then we must allow the user to set how many tx antennas we
3068 * have available
3069 */
caec9112 3070 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
be009370 3071
55aa4e0f 3072unlock:
be009370 3073 mutex_unlock(&sc->lock);
55aa4e0f 3074 return ret;
fa1c114f
JS		 3075}
3076
3ac64bee 3077static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 3078 struct netdev_hw_addr_list *mc_list)
3ac64bee
JB		 3079{
3080 u32 mfilt[2], val;
3ac64bee 3081 u8 pos;
22bedad3 3082 struct netdev_hw_addr *ha;
3ac64bee
JB		 3083
3084 mfilt[0] = 0;
3085 mfilt[1] = 1;
3086
22bedad3 3087 netdev_hw_addr_list_for_each(ha, mc_list) {
3ac64bee 3088 /* calculate XOR of eight 6-bit values */
22bedad3 3089 val = get_unaligned_le32(ha->addr + 0);
3ac64bee 3090 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
22bedad3 3091 val = get_unaligned_le32(ha->addr + 3);
3ac64bee
JB		 3092 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3093 pos &= 0x3f;
3094 mfilt[pos / 32] |= (1 << (pos % 32));
3095 /* XXX: we might be able to just do this instead,
3096 * but not sure, needs testing, if we do use this we'd
3097 * neet to inform below to not reset the mcast */
3098 /* ath5k_hw_set_mcast_filterindex(ah,
22bedad3 3099 * ha->addr[5]); */
3ac64bee
JB		 3100 }
3101
3102 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3103}
3104
fa1c114f
JS		 3105#define SUPPORTED_FIF_FLAGS \
3106 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3107 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3108 FIF_BCN_PRBRESP_PROMISC
3109/*
3110 * o always accept unicast, broadcast, and multicast traffic
3111 * o multicast traffic for all BSSIDs will be enabled if mac80211
3112 * says it should be
3113 * o maintain current state of phy ofdm or phy cck error reception.
3114 * If the hardware detects any of these type of errors then
3115 * ath5k_hw_get_rx_filter() will pass to us the respective
3116 * hardware filters to be able to receive these type of frames.
3117 * o probe request frames are accepted only when operating in
3118 * hostap, adhoc, or monitor modes
3119 * o enable promiscuous mode according to the interface state
3120 * o accept beacons:
3121 * - when operating in adhoc mode so the 802.11 layer creates
3122 * node table entries for peers,
3123 * - when operating in station mode for collecting rssi data when
3124 * the station is otherwise quiet, or
3125 * - when scanning
3126 */
3127static void ath5k_configure_filter(struct ieee80211_hw *hw,
3128 unsigned int changed_flags,
3129 unsigned int *new_flags,
3ac64bee 3130 u64 multicast)
fa1c114f
JS		 3131{
3132 struct ath5k_softc *sc = hw->priv;
3133 struct ath5k_hw *ah = sc->ah;
3ac64bee 3134 u32 mfilt[2], rfilt;
fa1c114f 3135
56d1de0a
BC		 3136 mutex_lock(&sc->lock);
3137
3ac64bee
JB		 3138 mfilt[0] = multicast;
3139 mfilt[1] = multicast >> 32;
fa1c114f
JS		 3140
3141 /* Only deal with supported flags */
3142 changed_flags &= SUPPORTED_FIF_FLAGS;
3143 *new_flags &= SUPPORTED_FIF_FLAGS;
3144
3145 /* If HW detects any phy or radar errors, leave those filters on.
3146 * Also, always enable Unicast, Broadcasts and Multicast
3147 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3148 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3149 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3150 AR5K_RX_FILTER_MCAST);
3151
3152 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3153 if (*new_flags & FIF_PROMISC_IN_BSS) {
3154 rfilt |= AR5K_RX_FILTER_PROM;
3155 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3156 } else {
fa1c114f 3157 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3158 }
fa1c114f
JS		 3159 }
3160
3161 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3162 if (*new_flags & FIF_ALLMULTI) {
3163 mfilt[0] = ~0;
3164 mfilt[1] = ~0;
fa1c114f
JS		 3165 }
3166
3167 /* This is the best we can do */
3168 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3169 rfilt |= AR5K_RX_FILTER_PHYERR;
3170
3171 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3172 * and probes for any BSSID, this needs testing */
3173 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3174 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3175
3176 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3177 * set we should only pass on control frames for this
3178 * station. This needs testing. I believe right now this
3179 * enables *all* control frames, which is OK.. but
3180 * but we should see if we can improve on granularity */
3181 if (*new_flags & FIF_CONTROL)
3182 rfilt |= AR5K_RX_FILTER_CONTROL;
3183
3184 /* Additional settings per mode -- this is per ath5k */
3185
3186 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3187
56d1de0a
BC		 3188 switch (sc->opmode) {
3189 case NL80211_IFTYPE_MESH_POINT:
3190 case NL80211_IFTYPE_MONITOR:
3191 rfilt |= AR5K_RX_FILTER_CONTROL |
3192 AR5K_RX_FILTER_BEACON |
3193 AR5K_RX_FILTER_PROBEREQ |
3194 AR5K_RX_FILTER_PROM;
3195 break;
3196 case NL80211_IFTYPE_AP:
3197 case NL80211_IFTYPE_ADHOC:
3198 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3199 AR5K_RX_FILTER_BEACON;
3200 break;
3201 case NL80211_IFTYPE_STATION:
3202 if (sc->assoc)
3203 rfilt |= AR5K_RX_FILTER_BEACON;
3204 default:
3205 break;
3206 }
fa1c114f
JS		 3207
3208 /* Set filters */
0bbac08f 3209 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3210
3211 /* Set multicast bits */
3212 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3213 /* Set the cached hw filter flags, this will alter actually
3214 * be set in HW */
3215 sc->filter_flags = rfilt;
56d1de0a
BC		 3216
3217 mutex_unlock(&sc->lock);
fa1c114f
JS		 3218}
3219
3220static int
3221ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3222 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3223 struct ieee80211_key_conf *key)
fa1c114f
JS		 3224{
3225 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 3226 struct ath5k_hw *ah = sc->ah;
3227 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 3228 int ret = 0;
3229
9ad9a26e
BC		 3230 if (modparam_nohwcrypt)
3231 return -EOPNOTSUPP;
3232
65b5a698
BC		 3233 if (sc->opmode == NL80211_IFTYPE_AP)
3234 return -EOPNOTSUPP;
3235
0bbac08f 3236 switch (key->alg) {
fa1c114f 3237 case ALG_WEP:
fa1c114f 3238 case ALG_TKIP:
3f64b435 3239 break;
fa1c114f 3240 case ALG_CCMP:
1c818740
BC		 3241 if (sc->ah->ah_aes_support)
3242 break;
3243
fa1c114f
JS		 3244 return -EOPNOTSUPP;
3245 default:
3246 WARN_ON(1);
3247 return -EINVAL;
3248 }
3249
3250 mutex_lock(&sc->lock);
3251
3252 switch (cmd) {
3253 case SET_KEY:
dc822b5d
JB		 3254 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3255 sta ? sta->addr : NULL);
fa1c114f
JS		 3256 if (ret) {
3257 ATH5K_ERR(sc, "can't set the key\n");
3258 goto unlock;
3259 }
dc1e001b 3260 __set_bit(key->keyidx, common->keymap);
fa1c114f 3261 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3262 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3263 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3264 break;
3265 case DISABLE_KEY:
3266 ath5k_hw_reset_key(sc->ah, key->keyidx);
dc1e001b 3267 __clear_bit(key->keyidx, common->keymap);
fa1c114f
JS		 3268 break;
3269 default:
3270 ret = -EINVAL;
3271 goto unlock;
3272 }
3273
3274unlock:
274c7c36 3275 mmiowb();
fa1c114f
JS		 3276 mutex_unlock(&sc->lock);
3277 return ret;
3278}
3279
3280static int
3281ath5k_get_stats(struct ieee80211_hw *hw,
3282 struct ieee80211_low_level_stats *stats)
3283{
3284 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3285
3286 /* Force update */
495391d7 3287 ath5k_hw_update_mib_counters(sc->ah);
fa1c114f 3288
495391d7
BR		 3289 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3290 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3291 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3292 stats->dot11FCSErrorCount = sc->stats.fcs_error;
fa1c114f
JS		 3293
3294 return 0;
3295}
3296
55ee82b5
HS		 3297static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3298 struct survey_info *survey)
3299{
3300 struct ath5k_softc *sc = hw->priv;
3301 struct ieee80211_conf *conf = &hw->conf;
3302
3303 if (idx != 0)
3304 return -ENOENT;
3305
3306 survey->channel = conf->channel;
3307 survey->filled = SURVEY_INFO_NOISE_DBM;
3308 survey->noise = sc->ah->ah_noise_floor;
3309
3310 return 0;
3311}
3312
fa1c114f
JS		 3313static u64
3314ath5k_get_tsf(struct ieee80211_hw *hw)
3315{
3316 struct ath5k_softc *sc = hw->priv;
3317
3318 return ath5k_hw_get_tsf64(sc->ah);
3319}
3320
3b5d665b
AF		 3321static void
3322ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3323{
3324 struct ath5k_softc *sc = hw->priv;
3325
3326 ath5k_hw_set_tsf64(sc->ah, tsf);
3327}
3328
fa1c114f
JS		 3329static void
3330ath5k_reset_tsf(struct ieee80211_hw *hw)
3331{
3332 struct ath5k_softc *sc = hw->priv;
3333
9804b98d
BR		 3334 /*
3335 * in IBSS mode we need to update the beacon timers too.
3336 * this will also reset the TSF if we call it with 0
3337 */
05c914fe 3338 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3339 ath5k_beacon_update_timers(sc, 0);
3340 else
3341 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3342}
3343
1071db86
BC		 3344/*
3345 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3346 * this is called only once at config_bss time, for AP we do it every
3347 * SWBA interrupt so that the TIM will reflect buffered frames.
3348 *
3349 * Called with the beacon lock.
3350 */
fa1c114f 3351static int
1071db86 3352ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
fa1c114f 3353{
fa1c114f 3354 int ret;
1071db86 3355 struct ath5k_softc *sc = hw->priv;
72828b1b
BC		 3356 struct sk_buff *skb;
3357
3358 if (WARN_ON(!vif)) {
3359 ret = -EINVAL;
3360 goto out;
3361 }
3362
3363 skb = ieee80211_beacon_get(hw, vif);
1071db86
BC		 3364
3365 if (!skb) {
3366 ret = -ENOMEM;
3367 goto out;
3368 }
fa1c114f
JS		 3369
3370 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3371
fa1c114f
JS		 3372 ath5k_txbuf_free(sc, sc->bbuf);
3373 sc->bbuf->skb = skb;
e039fa4a 3374 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3375 if (ret)
3376 sc->bbuf->skb = NULL;
1071db86
BC		 3377out:
3378 return ret;
3379}
3380
02969b38
MX		 3381static void
3382set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3383{
3384 struct ath5k_softc *sc = hw->priv;
3385 struct ath5k_hw *ah = sc->ah;
3386 u32 rfilt;
3387 rfilt = ath5k_hw_get_rx_filter(ah);
3388 if (enable)
3389 rfilt |= AR5K_RX_FILTER_BEACON;
3390 else
3391 rfilt &= ~AR5K_RX_FILTER_BEACON;
3392 ath5k_hw_set_rx_filter(ah, rfilt);
3393 sc->filter_flags = rfilt;
3394}
fa1c114f 3395
02969b38
MX		 3396static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3397 struct ieee80211_vif *vif,
3398 struct ieee80211_bss_conf *bss_conf,
3399 u32 changes)
3400{
3401 struct ath5k_softc *sc = hw->priv;
2d0ddec5 3402 struct ath5k_hw *ah = sc->ah;
954fecea 3403 struct ath_common *common = ath5k_hw_common(ah);
21800491 3404 unsigned long flags;
2d0ddec5
JB		 3405
3406 mutex_lock(&sc->lock);
3407 if (WARN_ON(sc->vif != vif))
3408 goto unlock;
3409
3410 if (changes & BSS_CHANGED_BSSID) {
3411 /* Cache for later use during resets */
954fecea 3412 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
8ce54c5a 3413 common->curaid = 0;
be5d6b75 3414 ath5k_hw_set_associd(ah);
2d0ddec5
JB		 3415 mmiowb();
3416 }
57c4d7b4
JB		 3417
3418 if (changes & BSS_CHANGED_BEACON_INT)
3419 sc->bintval = bss_conf->beacon_int;
3420
02969b38 3421 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3422 sc->assoc = bss_conf->assoc;
3423 if (sc->opmode == NL80211_IFTYPE_STATION)
3424 set_beacon_filter(hw, sc->assoc);
f0f3d388
BC		 3425 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3426 AR5K_LED_ASSOC : AR5K_LED_INIT);
8ce54c5a
LR		 3427 if (bss_conf->assoc) {
3428 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3429 "Bss Info ASSOC %d, bssid: %pM\n",
3430 bss_conf->aid, common->curbssid);
3431 common->curaid = bss_conf->aid;
3432 ath5k_hw_set_associd(ah);
3433 /* Once ANI is available you would start it here */
3434 }
02969b38 3435 }
2d0ddec5 3436
21800491
BC		 3437 if (changes & BSS_CHANGED_BEACON) {
3438 spin_lock_irqsave(&sc->block, flags);
3439 ath5k_beacon_update(hw, vif);
3440 spin_unlock_irqrestore(&sc->block, flags);
2d0ddec5
JB		 3441 }
3442
21800491
BC		 3443 if (changes & BSS_CHANGED_BEACON_ENABLED)
3444 sc->enable_beacon = bss_conf->enable_beacon;
3445
3446 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3447 BSS_CHANGED_BEACON_INT))
3448 ath5k_beacon_config(sc);
3449
2d0ddec5
JB		 3450 unlock:
3451 mutex_unlock(&sc->lock);
02969b38 3452}
f0f3d388
BC		 3453
3454static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3455{
3456 struct ath5k_softc *sc = hw->priv;
3457 if (!sc->assoc)
3458 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3459}
3460
3461static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3462{
3463 struct ath5k_softc *sc = hw->priv;
3464 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3465 AR5K_LED_ASSOC : AR5K_LED_INIT);
3466}
6e08d228
LT		 3467
3468/**
3469 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3470 *
3471 * @hw: struct ieee80211_hw pointer
3472 * @coverage_class: IEEE 802.11 coverage class number
3473 *
3474 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3475 * coverage class. The values are persistent, they are restored after device
3476 * reset.
3477 */
3478static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3479{
3480 struct ath5k_softc *sc = hw->priv;
3481
3482 mutex_lock(&sc->lock);
3483 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3484 mutex_unlock(&sc->lock);
3485}
Linux 6.x block layer and io_uring tree(s)