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c6e387a2 NK |
1 | /* |
2 | * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> | |
3 | * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> | |
4 | * | |
5 | * Permission to use, copy, modify, and distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | * | |
17 | */ | |
18 | ||
19 | /*************************************\ | |
20 | * Attach/Detach Functions and helpers * | |
21 | \*************************************/ | |
22 | ||
23 | #include <linux/pci.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c6e387a2 NK |
25 | #include "ath5k.h" |
26 | #include "reg.h" | |
27 | #include "debug.h" | |
28 | #include "base.h" | |
29 | ||
30 | /** | |
31 | * ath5k_hw_post - Power On Self Test helper function | |
32 | * | |
33 | * @ah: The &struct ath5k_hw | |
34 | */ | |
35 | static int ath5k_hw_post(struct ath5k_hw *ah) | |
36 | { | |
37 | ||
2c91108c | 38 | static const u32 static_pattern[4] = { |
c6e387a2 NK |
39 | 0x55555555, 0xaaaaaaaa, |
40 | 0x66666666, 0x99999999 | |
41 | }; | |
2c91108c JS |
42 | static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) }; |
43 | int i, c; | |
44 | u16 cur_reg; | |
45 | u32 var_pattern; | |
c6e387a2 NK |
46 | u32 init_val; |
47 | u32 cur_val; | |
48 | ||
49 | for (c = 0; c < 2; c++) { | |
50 | ||
51 | cur_reg = regs[c]; | |
52 | ||
53 | /* Save previous value */ | |
54 | init_val = ath5k_hw_reg_read(ah, cur_reg); | |
55 | ||
56 | for (i = 0; i < 256; i++) { | |
57 | var_pattern = i << 16 | i; | |
58 | ath5k_hw_reg_write(ah, var_pattern, cur_reg); | |
59 | cur_val = ath5k_hw_reg_read(ah, cur_reg); | |
60 | ||
61 | if (cur_val != var_pattern) { | |
62 | ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n"); | |
63 | return -EAGAIN; | |
64 | } | |
65 | ||
66 | /* Found on ndiswrapper dumps */ | |
67 | var_pattern = 0x0039080f; | |
68 | ath5k_hw_reg_write(ah, var_pattern, cur_reg); | |
69 | } | |
70 | ||
71 | for (i = 0; i < 4; i++) { | |
72 | var_pattern = static_pattern[i]; | |
73 | ath5k_hw_reg_write(ah, var_pattern, cur_reg); | |
74 | cur_val = ath5k_hw_reg_read(ah, cur_reg); | |
75 | ||
76 | if (cur_val != var_pattern) { | |
77 | ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n"); | |
78 | return -EAGAIN; | |
79 | } | |
80 | ||
81 | /* Found on ndiswrapper dumps */ | |
82 | var_pattern = 0x003b080f; | |
83 | ath5k_hw_reg_write(ah, var_pattern, cur_reg); | |
84 | } | |
85 | ||
86 | /* Restore previous value */ | |
87 | ath5k_hw_reg_write(ah, init_val, cur_reg); | |
88 | ||
89 | } | |
90 | ||
91 | return 0; | |
92 | ||
93 | } | |
94 | ||
95 | /** | |
96 | * ath5k_hw_attach - Check if hw is supported and init the needed structs | |
97 | * | |
98 | * @sc: The &struct ath5k_softc we got from the driver's attach function | |
c6e387a2 NK |
99 | * |
100 | * Check if the device is supported, perform a POST and initialize the needed | |
101 | * structs. Returns -ENOMEM if we don't have memory for the needed structs, | |
102 | * -ENODEV if the device is not supported or prints an error msg if something | |
103 | * else went wrong. | |
104 | */ | |
9adca126 | 105 | int ath5k_hw_attach(struct ath5k_softc *sc) |
c6e387a2 | 106 | { |
9adca126 | 107 | struct ath5k_hw *ah = sc->ah; |
13b81559 | 108 | struct ath_common *common = ath5k_hw_common(ah); |
c6e387a2 | 109 | struct pci_dev *pdev = sc->pdev; |
1c818740 | 110 | struct ath5k_eeprom_info *ee; |
c6e387a2 NK |
111 | int ret; |
112 | u32 srev; | |
113 | ||
c6e387a2 NK |
114 | /* |
115 | * HW information | |
116 | */ | |
05c914fe | 117 | ah->ah_op_mode = NL80211_IFTYPE_STATION; |
c6e387a2 NK |
118 | ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; |
119 | ah->ah_turbo = false; | |
120 | ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; | |
121 | ah->ah_imr = 0; | |
122 | ah->ah_atim_window = 0; | |
123 | ah->ah_aifs = AR5K_TUNE_AIFS; | |
124 | ah->ah_cw_min = AR5K_TUNE_CWMIN; | |
125 | ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; | |
126 | ah->ah_software_retry = false; | |
c6e387a2 NK |
127 | |
128 | /* | |
97a81f5c | 129 | * Find the mac version |
c6e387a2 | 130 | */ |
97a81f5c PR |
131 | srev = ath5k_hw_reg_read(ah, AR5K_SREV); |
132 | if (srev < AR5K_SREV_AR5311) | |
133 | ah->ah_version = AR5K_AR5210; | |
134 | else if (srev < AR5K_SREV_AR5212) | |
135 | ah->ah_version = AR5K_AR5211; | |
136 | else | |
137 | ah->ah_version = AR5K_AR5212; | |
c6e387a2 NK |
138 | |
139 | /*Fill the ath5k_hw struct with the needed functions*/ | |
140 | ret = ath5k_hw_init_desc_functions(ah); | |
141 | if (ret) | |
142 | goto err_free; | |
143 | ||
144 | /* Bring device out of sleep and reset it's units */ | |
edd7fc70 | 145 | ret = ath5k_hw_nic_wakeup(ah, 0, true); |
c6e387a2 NK |
146 | if (ret) |
147 | goto err_free; | |
148 | ||
149 | /* Get MAC, PHY and RADIO revisions */ | |
c6e387a2 NK |
150 | ah->ah_mac_srev = srev; |
151 | ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); | |
152 | ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); | |
153 | ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) & | |
154 | 0xffffffff; | |
155 | ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, | |
156 | CHANNEL_5GHZ); | |
ee81c554 | 157 | ah->ah_phy = AR5K_PHY(0); |
c6e387a2 | 158 | |
ee81c554 NK |
159 | /* Try to identify radio chip based on it's srev */ |
160 | switch (ah->ah_radio_5ghz_revision & 0xf0) { | |
161 | case AR5K_SREV_RAD_5111: | |
c6e387a2 | 162 | ah->ah_radio = AR5K_RF5111; |
ee81c554 NK |
163 | ah->ah_single_chip = false; |
164 | ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, | |
165 | CHANNEL_2GHZ); | |
ee81c554 NK |
166 | break; |
167 | case AR5K_SREV_RAD_5112: | |
168 | case AR5K_SREV_RAD_2112: | |
c6e387a2 | 169 | ah->ah_radio = AR5K_RF5112; |
ee81c554 NK |
170 | ah->ah_single_chip = false; |
171 | ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, | |
172 | CHANNEL_2GHZ); | |
ee81c554 NK |
173 | break; |
174 | case AR5K_SREV_RAD_2413: | |
c6e387a2 | 175 | ah->ah_radio = AR5K_RF2413; |
ee81c554 | 176 | ah->ah_single_chip = true; |
ee81c554 NK |
177 | break; |
178 | case AR5K_SREV_RAD_5413: | |
c6e387a2 | 179 | ah->ah_radio = AR5K_RF5413; |
ee81c554 | 180 | ah->ah_single_chip = true; |
ee81c554 NK |
181 | break; |
182 | case AR5K_SREV_RAD_2316: | |
183 | ah->ah_radio = AR5K_RF2316; | |
184 | ah->ah_single_chip = true; | |
ee81c554 NK |
185 | break; |
186 | case AR5K_SREV_RAD_2317: | |
187 | ah->ah_radio = AR5K_RF2317; | |
188 | ah->ah_single_chip = true; | |
ee81c554 NK |
189 | break; |
190 | case AR5K_SREV_RAD_5424: | |
191 | if (ah->ah_mac_version == AR5K_SREV_AR2425 || | |
192 | ah->ah_mac_version == AR5K_SREV_AR2417){ | |
193 | ah->ah_radio = AR5K_RF2425; | |
194 | ah->ah_single_chip = true; | |
ee81c554 | 195 | } else { |
c6e387a2 | 196 | ah->ah_radio = AR5K_RF5413; |
ee81c554 | 197 | ah->ah_single_chip = true; |
ee81c554 NK |
198 | } |
199 | break; | |
200 | default: | |
201 | /* Identify radio based on mac/phy srev */ | |
202 | if (ah->ah_version == AR5K_AR5210) { | |
203 | ah->ah_radio = AR5K_RF5110; | |
204 | ah->ah_single_chip = false; | |
205 | } else if (ah->ah_version == AR5K_AR5211) { | |
206 | ah->ah_radio = AR5K_RF5111; | |
207 | ah->ah_single_chip = false; | |
208 | ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, | |
209 | CHANNEL_2GHZ); | |
210 | } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) || | |
211 | ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) || | |
212 | ah->ah_phy_revision == AR5K_SREV_PHY_2425) { | |
213 | ah->ah_radio = AR5K_RF2425; | |
214 | ah->ah_single_chip = true; | |
215 | ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425; | |
ee81c554 | 216 | } else if (srev == AR5K_SREV_AR5213A && |
e8f055f0 | 217 | ah->ah_phy_revision == AR5K_SREV_PHY_5212B) { |
ee81c554 NK |
218 | ah->ah_radio = AR5K_RF5112; |
219 | ah->ah_single_chip = false; | |
e8f055f0 | 220 | ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B; |
ee81c554 NK |
221 | } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) { |
222 | ah->ah_radio = AR5K_RF2316; | |
223 | ah->ah_single_chip = true; | |
224 | ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316; | |
ee81c554 NK |
225 | } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) || |
226 | ah->ah_phy_revision == AR5K_SREV_PHY_5413) { | |
227 | ah->ah_radio = AR5K_RF5413; | |
228 | ah->ah_single_chip = true; | |
229 | ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413; | |
ee81c554 NK |
230 | } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) || |
231 | ah->ah_phy_revision == AR5K_SREV_PHY_2413) { | |
232 | ah->ah_radio = AR5K_RF2413; | |
233 | ah->ah_single_chip = true; | |
234 | ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413; | |
ee81c554 NK |
235 | } else { |
236 | ATH5K_ERR(sc, "Couldn't identify radio revision.\n"); | |
237 | ret = -ENODEV; | |
238 | goto err_free; | |
c6e387a2 NK |
239 | } |
240 | } | |
ee81c554 NK |
241 | |
242 | ||
243 | /* Return on unsuported chips (unsupported eeprom etc) */ | |
244 | if ((srev >= AR5K_SREV_AR5416) && | |
245 | (srev < AR5K_SREV_AR2425)) { | |
246 | ATH5K_ERR(sc, "Device not yet supported.\n"); | |
247 | ret = -ENODEV; | |
248 | goto err_free; | |
249 | } | |
c6e387a2 | 250 | |
c6e387a2 NK |
251 | /* |
252 | * POST | |
253 | */ | |
254 | ret = ath5k_hw_post(ah); | |
255 | if (ret) | |
256 | goto err_free; | |
257 | ||
ee81c554 NK |
258 | /* Enable pci core retry fix on Hainan (5213A) and later chips */ |
259 | if (srev >= AR5K_SREV_AR5213A) | |
b55a5de1 | 260 | AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX); |
c6e387a2 NK |
261 | |
262 | /* | |
ee81c554 NK |
263 | * Get card capabilities, calibration values etc |
264 | * TODO: EEPROM work | |
c6e387a2 NK |
265 | */ |
266 | ret = ath5k_eeprom_init(ah); | |
267 | if (ret) { | |
268 | ATH5K_ERR(sc, "unable to init EEPROM\n"); | |
269 | goto err_free; | |
270 | } | |
271 | ||
394317fc LR |
272 | ee = &ah->ah_capabilities.cap_eeprom; |
273 | ||
c38e7a93 NK |
274 | /* |
275 | * Write PCI-E power save settings | |
276 | */ | |
277 | if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) { | |
c38e7a93 NK |
278 | ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES); |
279 | ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES); | |
280 | ||
281 | /* Shut off RX when elecidle is asserted */ | |
282 | ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES); | |
283 | ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES); | |
284 | ||
285 | /* If serdes programing is enabled, increase PCI-E | |
286 | * tx power for systems with long trace from host | |
287 | * to minicard connector. */ | |
288 | if (ee->ee_serdes) | |
289 | ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES); | |
290 | else | |
291 | ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES); | |
292 | ||
293 | /* Shut off PLL and CLKREQ active in L1 */ | |
294 | ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES); | |
295 | ||
296 | /* Preserve other settings */ | |
297 | ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES); | |
298 | ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES); | |
299 | ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES); | |
300 | ||
301 | /* Reset SERDES to load new settings */ | |
302 | ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET); | |
303 | mdelay(1); | |
304 | } | |
305 | ||
c6e387a2 NK |
306 | /* Get misc capabilities */ |
307 | ret = ath5k_hw_set_capabilities(ah); | |
308 | if (ret) { | |
309 | ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n", | |
310 | sc->pdev->device); | |
311 | goto err_free; | |
312 | } | |
313 | ||
1c818740 | 314 | /* Crypto settings */ |
ca5efbe2 | 315 | ah->ah_aes_support = srev >= AR5K_SREV_AR5212_V4 && |
1c818740 | 316 | (ee->ee_version >= AR5K_EEPROM_VERSION_5_0 && |
ca5efbe2 | 317 | !AR5K_EEPROM_AES_DIS(ee->ee_misc5)); |
1c818740 | 318 | |
f650470a BC |
319 | if (srev >= AR5K_SREV_AR2414) { |
320 | ah->ah_combined_mic = true; | |
321 | AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE, | |
322 | AR5K_MISC_MODE_COMBINED_MIC); | |
323 | } | |
324 | ||
0e149cf5 | 325 | /* MAC address is cleared until add_interface */ |
2c91108c | 326 | ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){}); |
0e149cf5 | 327 | |
c6e387a2 | 328 | /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */ |
954fecea | 329 | memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN); |
be5d6b75 | 330 | ath5k_hw_set_associd(ah); |
c6e387a2 NK |
331 | ath5k_hw_set_opmode(ah); |
332 | ||
6f3b414a | 333 | ath5k_hw_rfgain_opt_init(ah); |
c6e387a2 | 334 | |
e5e2647f BC |
335 | ath5k_hw_init_nfcal_hist(ah); |
336 | ||
f0f3d388 BC |
337 | /* turn on HW LEDs */ |
338 | ath5k_hw_set_ledstate(ah, AR5K_LED_INIT); | |
339 | ||
9adca126 | 340 | return 0; |
c6e387a2 NK |
341 | err_free: |
342 | kfree(ah); | |
9adca126 | 343 | return ret; |
c6e387a2 NK |
344 | } |
345 | ||
346 | /** | |
347 | * ath5k_hw_detach - Free the ath5k_hw struct | |
348 | * | |
349 | * @ah: The &struct ath5k_hw | |
350 | */ | |
351 | void ath5k_hw_detach(struct ath5k_hw *ah) | |
352 | { | |
353 | ATH5K_TRACE(ah->ah_sc); | |
354 | ||
355 | __set_bit(ATH_STAT_INVALID, ah->ah_sc->status); | |
356 | ||
357 | if (ah->ah_rf_banks != NULL) | |
358 | kfree(ah->ah_rf_banks); | |
359 | ||
8f655dde NK |
360 | ath5k_eeprom_detach(ah); |
361 | ||
c6e387a2 | 362 | /* assume interrupts are down */ |
c6e387a2 | 363 | } |