[linux-block.git] / drivers / net / wireless / ath / ath5k / attach.c

/*
 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

/*************************************\
* Attach/Detach Functions and helpers *
\*************************************/

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/pci.h>
#include <linux/slab.h>
#include "ath5k.h"
#include "reg.h"
#include "debug.h"

/**
 * ath5k_hw_post() - Power On Self Test helper function
 * @ah: The &struct ath5k_hw
 */
static int ath5k_hw_post(struct ath5k_hw *ah)
{

	static const u32 static_pattern[4] = {
		0x55555555,	0xaaaaaaaa,
		0x66666666,	0x99999999
	};
	static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
	int i, c;
	u16 cur_reg;
	u32 var_pattern;
	u32 init_val;
	u32 cur_val;

	for (c = 0; c < 2; c++) {

		cur_reg = regs[c];

		/* Save previous value */
		init_val = ath5k_hw_reg_read(ah, cur_reg);

		for (i = 0; i < 256; i++) {
			var_pattern = i << 16 | i;
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
			cur_val = ath5k_hw_reg_read(ah, cur_reg);

			if (cur_val != var_pattern) {
				ATH5K_ERR(ah, "POST Failed !!!\n");
				return -EAGAIN;
			}

			/* Found on ndiswrapper dumps */
			var_pattern = 0x0039080f;
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
		}

		for (i = 0; i < 4; i++) {
			var_pattern = static_pattern[i];
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
			cur_val = ath5k_hw_reg_read(ah, cur_reg);

			if (cur_val != var_pattern) {
				ATH5K_ERR(ah, "POST Failed !!!\n");
				return -EAGAIN;
			}

			/* Found on ndiswrapper dumps */
			var_pattern = 0x003b080f;
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
		}

		/* Restore previous value */
		ath5k_hw_reg_write(ah, init_val, cur_reg);

	}

	return 0;

}

/**
 * ath5k_hw_init() - Check if hw is supported and init the needed structs
 * @ah: The &struct ath5k_hw associated with the device
 *
 * Check if the device is supported, perform a POST and initialize the needed
 * structs. Returns -ENOMEM if we don't have memory for the needed structs,
 * -ENODEV if the device is not supported or prints an error msg if something
 * else went wrong.
 */
int ath5k_hw_init(struct ath5k_hw *ah)
{
	static const u8 zero_mac[ETH_ALEN] = { };
	struct ath_common *common = ath5k_hw_common(ah);
	struct pci_dev *pdev = ah->pdev;
	struct ath5k_eeprom_info *ee;
	int ret;
	u32 srev;

	/*
	 * HW information
	 */
	ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
	ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
	ah->ah_imr = 0;
	ah->ah_retry_short = AR5K_INIT_RETRY_SHORT;
	ah->ah_retry_long = AR5K_INIT_RETRY_LONG;
	ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
	ah->ah_noise_floor = -95;	/* until first NF calibration is run */
	ah->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
	ah->ah_current_channel = &ah->channels[0];

	/*
	 * Find the mac version
	 */
	ath5k_hw_read_srev(ah);
	srev = ah->ah_mac_srev;
	if (srev < AR5K_SREV_AR5311)
		ah->ah_version = AR5K_AR5210;
	else if (srev < AR5K_SREV_AR5212)
		ah->ah_version = AR5K_AR5211;
	else
		ah->ah_version = AR5K_AR5212;

	/* Get the MAC version */
	ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);

	/* Fill the ath5k_hw struct with the needed functions */
	ret = ath5k_hw_init_desc_functions(ah);
	if (ret)
		goto err;

	/* Bring device out of sleep and reset its units */
	ret = ath5k_hw_nic_wakeup(ah, NULL);
	if (ret)
		goto err;

	/* Get PHY and RADIO revisions */
	ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
			0xffffffff;
	ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
			NL80211_BAND_5GHZ);

	/* Try to identify radio chip based on its srev */
	switch (ah->ah_radio_5ghz_revision & 0xf0) {
	case AR5K_SREV_RAD_5111:
		ah->ah_radio = AR5K_RF5111;
		ah->ah_single_chip = false;
		ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
							NL80211_BAND_2GHZ);
		break;
	case AR5K_SREV_RAD_5112:
	case AR5K_SREV_RAD_2112:
		ah->ah_radio = AR5K_RF5112;
		ah->ah_single_chip = false;
		ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
							NL80211_BAND_2GHZ);
		break;
	case AR5K_SREV_RAD_2413:
		ah->ah_radio = AR5K_RF2413;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_5413:
		ah->ah_radio = AR5K_RF5413;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_2316:
		ah->ah_radio = AR5K_RF2316;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_2317:
		ah->ah_radio = AR5K_RF2317;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_5424:
		if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
		    ah->ah_mac_version == AR5K_SREV_AR2417) {
			ah->ah_radio = AR5K_RF2425;
			ah->ah_single_chip = true;
		} else {
			ah->ah_radio = AR5K_RF5413;
			ah->ah_single_chip = true;
		}
		break;
	default:
		/* Identify radio based on mac/phy srev */
		if (ah->ah_version == AR5K_AR5210) {
			ah->ah_radio = AR5K_RF5110;
			ah->ah_single_chip = false;
		} else if (ah->ah_version == AR5K_AR5211) {
			ah->ah_radio = AR5K_RF5111;
			ah->ah_single_chip = false;
			ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
							NL80211_BAND_2GHZ);
		} else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
			   ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
			   ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
			ah->ah_radio = AR5K_RF2425;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
		} else if (srev == AR5K_SREV_AR5213A &&
			   ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
			ah->ah_radio = AR5K_RF5112;
			ah->ah_single_chip = false;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
		} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) ||
			   ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
			ah->ah_radio = AR5K_RF2316;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
		} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
			   ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
			ah->ah_radio = AR5K_RF5413;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
		} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
			   ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
			ah->ah_radio = AR5K_RF2413;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
		} else {
			ATH5K_ERR(ah, "Couldn't identify radio revision.\n");
			ret = -ENODEV;
			goto err;
		}
	}


	/* Return on unsupported chips (unsupported eeprom etc) */
	if ((srev >= AR5K_SREV_AR5416) && (srev < AR5K_SREV_AR2425)) {
		ATH5K_ERR(ah, "Device not yet supported.\n");
		ret = -ENODEV;
		goto err;
	}

	/*
	 * POST
	 */
	ret = ath5k_hw_post(ah);
	if (ret)
		goto err;

	/* Enable pci core retry fix on Hainan (5213A) and later chips */
	if (srev >= AR5K_SREV_AR5213A)
		AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);

	/*
	 * Get card capabilities, calibration values etc
	 * TODO: EEPROM work
	 */
	ret = ath5k_eeprom_init(ah);
	if (ret) {
		ATH5K_ERR(ah, "unable to init EEPROM\n");
		goto err;
	}

	ee = &ah->ah_capabilities.cap_eeprom;

	/*
	 * Write PCI-E power save settings
	 */
	if ((ah->ah_version == AR5K_AR5212) && pdev && (pci_is_pcie(pdev))) {
		ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);

		/* Shut off RX when elecidle is asserted */
		ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);

		/* If serdes programming is enabled, increase PCI-E
		 * tx power for systems with long trace from host
		 * to minicard connector. */
		if (ee->ee_serdes)
			ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
		else
			ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);

		/* Shut off PLL and CLKREQ active in L1 */
		ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);

		/* Preserve other settings */
		ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);

		/* Reset SERDES to load new settings */
		ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
		usleep_range(1000, 1500);
	}

	/* Get misc capabilities */
	ret = ath5k_hw_set_capabilities(ah);
	if (ret) {
		ATH5K_ERR(ah, "unable to get device capabilities\n");
		goto err;
	}

	/* Crypto settings */
	common->keymax = (ah->ah_version == AR5K_AR5210 ?
			  AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);

	if (srev >= AR5K_SREV_AR5212_V4 &&
	    (ee->ee_version < AR5K_EEPROM_VERSION_5_0 ||
	    !AR5K_EEPROM_AES_DIS(ee->ee_misc5)))
		common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;

	if (srev >= AR5K_SREV_AR2414) {
		common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
		AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
			AR5K_MISC_MODE_COMBINED_MIC);
	}

	/* MAC address is cleared until add_interface */
	ath5k_hw_set_lladdr(ah, zero_mac);

	/* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
	memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
	ath5k_hw_set_bssid(ah);
	ath5k_hw_set_opmode(ah, ah->opmode);

	ath5k_hw_rfgain_opt_init(ah);

	ath5k_hw_init_nfcal_hist(ah);

	/* turn on HW LEDs */
	ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);

	return 0;
err:
	return ret;
}

/**
 * ath5k_hw_deinit() - Free the &struct ath5k_hw
 * @ah: The &struct ath5k_hw
 */
void ath5k_hw_deinit(struct ath5k_hw *ah)
{
	__set_bit(ATH_STAT_INVALID, ah->status);

	kfree(ah->ah_rf_banks);

	ath5k_eeprom_detach(ah);

	/* assume interrupts are down */
}
Commit	Line	Data
c6e387a2 NK	1	/*
	2	* Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
	3	* Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
	4	*
	5	* Permission to use, copy, modify, and distribute this software for any
	6	* purpose with or without fee is hereby granted, provided that the above
	7	* copyright notice and this permission notice appear in all copies.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	10	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	11	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	12	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	13	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	14	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	15	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	16	*
	17	*/
	18
	19	/*************************************\
	20	* Attach/Detach Functions and helpers *
	21	\*************************************/
	22
516304b0 JP	23	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
516304b0 JP	24
c6e387a2	25	#include <linux/pci.h>
5a0e3ad6	26	#include <linux/slab.h>
c6e387a2 NK	27	#include "ath5k.h"
	28	#include "reg.h"
	29	#include "debug.h"
c6e387a2 NK	30
c6e387a2 NK	31	/**
c47faa36	32	* ath5k_hw_post() - Power On Self Test helper function
c6e387a2 NK	33	* @ah: The &struct ath5k_hw
	34	*/
	35	static int ath5k_hw_post(struct ath5k_hw *ah)
	36	{
	37
2c91108c	38	static const u32 static_pattern[4] = {
c6e387a2 NK	39	0x55555555, 0xaaaaaaaa,
	40	0x66666666, 0x99999999
	41	};
2c91108c JS	42	static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
	43	int i, c;
	44	u16 cur_reg;
	45	u32 var_pattern;
c6e387a2 NK	46	u32 init_val;
	47	u32 cur_val;
	48
	49	for (c = 0; c < 2; c++) {
	50
	51	cur_reg = regs[c];
	52
	53	/* Save previous value */
	54	init_val = ath5k_hw_reg_read(ah, cur_reg);
	55
	56	for (i = 0; i < 256; i++) {
	57	var_pattern = i << 16 \| i;
	58	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	59	cur_val = ath5k_hw_reg_read(ah, cur_reg);
	60
	61	if (cur_val != var_pattern) {
e0d687bd	62	ATH5K_ERR(ah, "POST Failed !!!\n");
c6e387a2 NK	63	return -EAGAIN;
	64	}
	65
	66	/* Found on ndiswrapper dumps */
	67	var_pattern = 0x0039080f;
	68	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	69	}
	70
	71	for (i = 0; i < 4; i++) {
	72	var_pattern = static_pattern[i];
	73	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	74	cur_val = ath5k_hw_reg_read(ah, cur_reg);
	75
	76	if (cur_val != var_pattern) {
e0d687bd	77	ATH5K_ERR(ah, "POST Failed !!!\n");
c6e387a2 NK	78	return -EAGAIN;
	79	}
	80
	81	/* Found on ndiswrapper dumps */
	82	var_pattern = 0x003b080f;
	83	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	84	}
	85
	86	/* Restore previous value */
	87	ath5k_hw_reg_write(ah, init_val, cur_reg);
	88
	89	}
	90
	91	return 0;
	92
	93	}
	94
	95	/**
c47faa36	96	* ath5k_hw_init() - Check if hw is supported and init the needed structs
bb1f3ad9	97	* @ah: The &struct ath5k_hw associated with the device
c6e387a2 NK	98	*
	99	* Check if the device is supported, perform a POST and initialize the needed
	100	* structs. Returns -ENOMEM if we don't have memory for the needed structs,
	101	* -ENODEV if the device is not supported or prints an error msg if something
	102	* else went wrong.
	103	*/
e0d687bd	104	int ath5k_hw_init(struct ath5k_hw *ah)
c6e387a2	105	{
2724a74a	106	static const u8 zero_mac[ETH_ALEN] = { };
13b81559	107	struct ath_common *common = ath5k_hw_common(ah);
e0d687bd	108	struct pci_dev *pdev = ah->pdev;
1c818740	109	struct ath5k_eeprom_info *ee;
c6e387a2 NK	110	int ret;
	111	u32 srev;
	112
c6e387a2 NK	113	/*
	114	* HW information
	115	*/
fa3d2fee	116	ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
c6e387a2 NK	117	ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
c6e387a2 NK	118	ah->ah_imr = 0;
76a9f6fd BR	119	ah->ah_retry_short = AR5K_INIT_RETRY_SHORT;
76a9f6fd BR	120	ah->ah_retry_long = AR5K_INIT_RETRY_LONG;
caec9112	121	ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
9d332c82	122	ah->ah_noise_floor = -95; /* until first NF calibration is run */
e0d687bd PR	123	ah->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
e0d687bd PR	124	ah->ah_current_channel = &ah->channels[0];
c6e387a2 NK	125
c6e387a2 NK	126	/*
97a81f5c	127	* Find the mac version
c6e387a2	128	*/
e7aecd32 FF	129	ath5k_hw_read_srev(ah);
e7aecd32 FF	130	srev = ah->ah_mac_srev;
97a81f5c PR	131	if (srev < AR5K_SREV_AR5311)
	132	ah->ah_version = AR5K_AR5210;
	133	else if (srev < AR5K_SREV_AR5212)
	134	ah->ah_version = AR5K_AR5211;
	135	else
	136	ah->ah_version = AR5K_AR5212;
c6e387a2	137
2972cc18	138	/* Get the MAC version */
e7aecd32	139	ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
e7aecd32	140
a180a130	141	/* Fill the ath5k_hw struct with the needed functions */
c6e387a2 NK	142	ret = ath5k_hw_init_desc_functions(ah);
c6e387a2 NK	143	if (ret)
3d435ad7	144	goto err;
c6e387a2	145
a180a130	146	/* Bring device out of sleep and reset its units */
32c25464	147	ret = ath5k_hw_nic_wakeup(ah, NULL);
c6e387a2	148	if (ret)
3d435ad7	149	goto err;
c6e387a2	150
e7aecd32	151	/* Get PHY and RADIO revisions */
c6e387a2 NK	152	ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
	153	0xffffffff;
	154	ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
57fbcce3	155	NL80211_BAND_5GHZ);
c6e387a2	156
a180a130	157	/* Try to identify radio chip based on its srev */
ee81c554 NK	158	switch (ah->ah_radio_5ghz_revision & 0xf0) {
ee81c554 NK	159	case AR5K_SREV_RAD_5111:
c6e387a2	160	ah->ah_radio = AR5K_RF5111;
ee81c554 NK	161	ah->ah_single_chip = false;
ee81c554 NK	162	ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
57fbcce3	163	NL80211_BAND_2GHZ);
ee81c554 NK	164	break;
	165	case AR5K_SREV_RAD_5112:
	166	case AR5K_SREV_RAD_2112:
c6e387a2	167	ah->ah_radio = AR5K_RF5112;
ee81c554 NK	168	ah->ah_single_chip = false;
ee81c554 NK	169	ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
57fbcce3	170	NL80211_BAND_2GHZ);
ee81c554 NK	171	break;
ee81c554 NK	172	case AR5K_SREV_RAD_2413:
c6e387a2	173	ah->ah_radio = AR5K_RF2413;
ee81c554	174	ah->ah_single_chip = true;
ee81c554 NK	175	break;
ee81c554 NK	176	case AR5K_SREV_RAD_5413:
c6e387a2	177	ah->ah_radio = AR5K_RF5413;
ee81c554	178	ah->ah_single_chip = true;
ee81c554 NK	179	break;
	180	case AR5K_SREV_RAD_2316:
	181	ah->ah_radio = AR5K_RF2316;
	182	ah->ah_single_chip = true;
ee81c554 NK	183	break;
	184	case AR5K_SREV_RAD_2317:
	185	ah->ah_radio = AR5K_RF2317;
	186	ah->ah_single_chip = true;
ee81c554 NK	187	break;
	188	case AR5K_SREV_RAD_5424:
	189	if (ah->ah_mac_version == AR5K_SREV_AR2425 \|\|
e4bbf2f5	190	ah->ah_mac_version == AR5K_SREV_AR2417) {
ee81c554 NK	191	ah->ah_radio = AR5K_RF2425;
ee81c554 NK	192	ah->ah_single_chip = true;
ee81c554	193	} else {
c6e387a2	194	ah->ah_radio = AR5K_RF5413;
ee81c554	195	ah->ah_single_chip = true;
ee81c554 NK	196	}
	197	break;
	198	default:
	199	/* Identify radio based on mac/phy srev */
	200	if (ah->ah_version == AR5K_AR5210) {
	201	ah->ah_radio = AR5K_RF5110;
	202	ah->ah_single_chip = false;
	203	} else if (ah->ah_version == AR5K_AR5211) {
	204	ah->ah_radio = AR5K_RF5111;
	205	ah->ah_single_chip = false;
	206	ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
57fbcce3	207	NL80211_BAND_2GHZ);
ee81c554	208	} else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) \|\|
e4bbf2f5 PR	209	ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) \|\|
e4bbf2f5 PR	210	ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
ee81c554 NK	211	ah->ah_radio = AR5K_RF2425;
	212	ah->ah_single_chip = true;
	213	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
ee81c554	214	} else if (srev == AR5K_SREV_AR5213A &&
e4bbf2f5	215	ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
ee81c554 NK	216	ah->ah_radio = AR5K_RF5112;
ee81c554 NK	217	ah->ah_single_chip = false;
e8f055f0	218	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
d985255e	219	} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) \|\|
e4bbf2f5	220	ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
ee81c554 NK	221	ah->ah_radio = AR5K_RF2316;
	222	ah->ah_single_chip = true;
	223	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
ee81c554	224	} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) \|\|
e4bbf2f5	225	ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
ee81c554 NK	226	ah->ah_radio = AR5K_RF5413;
	227	ah->ah_single_chip = true;
	228	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
ee81c554	229	} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) \|\|
e4bbf2f5	230	ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
ee81c554 NK	231	ah->ah_radio = AR5K_RF2413;
	232	ah->ah_single_chip = true;
	233	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
ee81c554	234	} else {
e0d687bd	235	ATH5K_ERR(ah, "Couldn't identify radio revision.\n");
ee81c554	236	ret = -ENODEV;
3d435ad7	237	goto err;
c6e387a2 NK	238	}
c6e387a2 NK	239	}
ee81c554 NK	240
ee81c554 NK	241
6a2a0e73	242	/* Return on unsupported chips (unsupported eeprom etc) */
e4bbf2f5	243	if ((srev >= AR5K_SREV_AR5416) && (srev < AR5K_SREV_AR2425)) {
e0d687bd	244	ATH5K_ERR(ah, "Device not yet supported.\n");
ee81c554	245	ret = -ENODEV;
3d435ad7	246	goto err;
ee81c554	247	}
c6e387a2	248
c6e387a2 NK	249	/*
	250	* POST
	251	*/
	252	ret = ath5k_hw_post(ah);
	253	if (ret)
3d435ad7	254	goto err;
c6e387a2	255
ee81c554 NK	256	/* Enable pci core retry fix on Hainan (5213A) and later chips */
ee81c554 NK	257	if (srev >= AR5K_SREV_AR5213A)
b55a5de1	258	AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
c6e387a2 NK	259
c6e387a2 NK	260	/*
ee81c554 NK	261	* Get card capabilities, calibration values etc
ee81c554 NK	262	* TODO: EEPROM work
c6e387a2 NK	263	*/
	264	ret = ath5k_eeprom_init(ah);
	265	if (ret) {
e0d687bd	266	ATH5K_ERR(ah, "unable to init EEPROM\n");
3d435ad7	267	goto err;
c6e387a2 NK	268	}
c6e387a2 NK	269
394317fc LR	270	ee = &ah->ah_capabilities.cap_eeprom;
394317fc LR	271
c38e7a93 NK	272	/*
	273	* Write PCI-E power save settings
	274	*/
e98b06b0	275	if ((ah->ah_version == AR5K_AR5212) && pdev && (pci_is_pcie(pdev))) {
c38e7a93 NK	276	ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
	277	ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
	278
	279	/* Shut off RX when elecidle is asserted */
	280	ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
	281	ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
	282
6a2a0e73	283	/* If serdes programming is enabled, increase PCI-E
c38e7a93 NK	284	* tx power for systems with long trace from host
	285	* to minicard connector. */
	286	if (ee->ee_serdes)
	287	ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
	288	else
	289	ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
	290
	291	/* Shut off PLL and CLKREQ active in L1 */
	292	ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
	293
	294	/* Preserve other settings */
	295	ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
	296	ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
	297	ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
	298
	299	/* Reset SERDES to load new settings */
	300	ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
1846ac3d	301	usleep_range(1000, 1500);
c38e7a93 NK	302	}
c38e7a93 NK	303
c6e387a2 NK	304	/* Get misc capabilities */
	305	ret = ath5k_hw_set_capabilities(ah);
	306	if (ret) {
e0d687bd	307	ATH5K_ERR(ah, "unable to get device capabilities\n");
3d435ad7	308	goto err;
c6e387a2 NK	309	}
c6e387a2 NK	310
1c818740	311	/* Crypto settings */
e0d687bd	312	common->keymax = (ah->ah_version == AR5K_AR5210 ?
e0f8c2a9 BR	313	AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);
e0f8c2a9 BR	314
781f3136	315	if (srev >= AR5K_SREV_AR5212_V4 &&
32377b6c	316	(ee->ee_version < AR5K_EEPROM_VERSION_5_0 \|\|
781f3136	317	!AR5K_EEPROM_AES_DIS(ee->ee_misc5)))
ce2220d1	318	common->crypt_caps \|= ATH_CRYPT_CAP_CIPHER_AESCCM;
1c818740	319
f650470a	320	if (srev >= AR5K_SREV_AR2414) {
781f3136	321	common->crypt_caps \|= ATH_CRYPT_CAP_MIC_COMBINED;
f650470a BC	322	AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
	323	AR5K_MISC_MODE_COMBINED_MIC);
	324	}
	325
0e149cf5	326	/* MAC address is cleared until add_interface */
2724a74a	327	ath5k_hw_set_lladdr(ah, zero_mac);
0e149cf5	328
c6e387a2	329	/* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
954fecea	330	memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
418de6d9	331	ath5k_hw_set_bssid(ah);
e0d687bd	332	ath5k_hw_set_opmode(ah, ah->opmode);
c6e387a2	333
6f3b414a	334	ath5k_hw_rfgain_opt_init(ah);
c6e387a2	335
e5e2647f BC	336	ath5k_hw_init_nfcal_hist(ah);
e5e2647f BC	337
f0f3d388 BC	338	/* turn on HW LEDs */
	339	ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
	340
9adca126	341	return 0;
3d435ad7	342	err:
9adca126	343	return ret;
c6e387a2 NK	344	}
	345
	346	/**
c47faa36	347	* ath5k_hw_deinit() - Free the &struct ath5k_hw
c6e387a2 NK	348	* @ah: The &struct ath5k_hw
c6e387a2 NK	349	*/
132b1c3e	350	void ath5k_hw_deinit(struct ath5k_hw *ah)
c6e387a2	351	{
e0d687bd	352	__set_bit(ATH_STAT_INVALID, ah->status);
c6e387a2	353
dcb78405	354	kfree(ah->ah_rf_banks);
c6e387a2	355
8f655dde NK	356	ath5k_eeprom_detach(ah);
8f655dde NK	357
c6e387a2	358	/* assume interrupts are down */
c6e387a2	359	}