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wifi: ath: work around false-positive stringop-overread warning
[linux-2.6-block.git] / drivers / net / wireless / ath / ath11k / hw.c
CommitLineData
d547ca4c
AK		 1// SPDX-License-Identifier: BSD-3-Clause-Clear
2/*
3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.
49890d9c 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
d547ca4c
AK		 5 */
6
6976433c
CH		 7#include <linux/types.h>
8#include <linux/bitops.h>
9#include <linux/bitfield.h>
10
d547ca4c 11#include "core.h"
e3396b8b 12#include "ce.h"
0d55b76f 13#include "hif.h"
734223d7
BQ		 14#include "hal.h"
15#include "hw.h"
d547ca4c
AK		 16
17/* Map from pdev index to hw mac index */
18static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx)
19{
20 switch (pdev_idx) {
21 case 0:
22 return 0;
23 case 1:
24 return 2;
25 case 2:
26 return 1;
27 default:
28 return ATH11K_INVALID_HW_MAC_ID;
29 }
30}
31
32static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx)
33{
34 return pdev_idx;
35}
36
6fe6f68f
KP		 37static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab,
38 struct hal_tcl_data_cmd *tcl_cmd)
39{
40 tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE,
41 true);
42}
43
44static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab,
45 struct hal_tcl_data_cmd *tcl_cmd)
46{
47 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE,
48 true);
49}
50
e4073430
BQ		 51static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab,
52 struct hal_tcl_data_cmd *tcl_cmd)
53{
54 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE,
55 true);
56}
57
2d4bcbed
CH		 58static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
59 struct target_resource_config *config)
60{
61 config->num_vdevs = 4;
62 config->num_peers = 16;
63 config->num_tids = 32;
64
65 config->num_offload_peers = 3;
66 config->num_offload_reorder_buffs = 3;
67 config->num_peer_keys = TARGET_NUM_PEER_KEYS;
68 config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
69 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
70 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
71 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
72 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
73 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
74 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
75 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
76 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
77 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
78 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
79 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
80 config->num_mcast_groups = 0;
81 config->num_mcast_table_elems = 0;
82 config->mcast2ucast_mode = 0;
83 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
84 config->num_wds_entries = 0;
85 config->dma_burst_size = 0;
86 config->rx_skip_defrag_timeout_dup_detection_check = 0;
87 config->vow_config = TARGET_VOW_CONFIG;
88 config->gtk_offload_max_vdev = 2;
89 config->num_msdu_desc = 0x400;
90 config->beacon_tx_offload_max_vdev = 2;
91 config->rx_batchmode = TARGET_RX_BATCHMODE;
92
93 config->peer_map_unmap_v2_support = 0;
94 config->use_pdev_id = 1;
95 config->max_frag_entries = 0xa;
96 config->num_tdls_vdevs = 0x1;
97 config->num_tdls_conn_table_entries = 8;
98 config->beacon_tx_offload_max_vdev = 0x2;
99 config->num_multicast_filter_entries = 0x20;
100 config->num_wow_filters = 0x16;
2d4bcbed 101 config->num_keep_alive_pattern = 0;
9b4dd38b 102 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64;
2d4bcbed
CH		 103}
104
0d55b76f
BQ		 105static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab)
106{
107 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
108 u32 val;
109 /* Each hash entry uses three bits to map to a particular ring. */
110 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
111 HAL_HASH_ROUTING_RING_SW2 << 3 |
112 HAL_HASH_ROUTING_RING_SW3 << 6 |
113 HAL_HASH_ROUTING_RING_SW4 << 9 |
114 HAL_HASH_ROUTING_RING_SW1 << 12 |
115 HAL_HASH_ROUTING_RING_SW2 << 15 |
116 HAL_HASH_ROUTING_RING_SW3 << 18 |
117 HAL_HASH_ROUTING_RING_SW4 << 21;
118
119 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
120
121 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
122 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
123 HAL_SRNG_RING_ID_REO2SW1) |
124 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
125 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
126 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
127
128 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
129 HAL_DEFAULT_REO_TIMEOUT_USEC);
130 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
131 HAL_DEFAULT_REO_TIMEOUT_USEC);
132 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
133 HAL_DEFAULT_REO_TIMEOUT_USEC);
134 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
135 HAL_DEFAULT_REO_TIMEOUT_USEC);
136
137 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
138 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
139 ring_hash_map));
140 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
141 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
142 ring_hash_map));
143 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
144 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
145 ring_hash_map));
146 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
147 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
148 ring_hash_map));
149}
150
2d4bcbed
CH		 151static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab,
152 struct target_resource_config *config)
153{
523aafd0 154 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS(ab);
2d4bcbed
CH		 155
156 if (ab->num_radios == 2) {
523aafd0
KV		 157 config->num_peers = TARGET_NUM_PEERS(ab, DBS);
158 config->num_tids = TARGET_NUM_TIDS(ab, DBS);
2d4bcbed 159 } else if (ab->num_radios == 3) {
523aafd0
KV		 160 config->num_peers = TARGET_NUM_PEERS(ab, DBS_SBS);
161 config->num_tids = TARGET_NUM_TIDS(ab, DBS_SBS);
2d4bcbed
CH		 162 } else {
163 /* Control should not reach here */
523aafd0
KV		 164 config->num_peers = TARGET_NUM_PEERS(ab, SINGLE);
165 config->num_tids = TARGET_NUM_TIDS(ab, SINGLE);
2d4bcbed
CH		 166 }
167 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS;
168 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS;
169 config->num_peer_keys = TARGET_NUM_PEER_KEYS;
170 config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
171 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
172 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
173 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
174 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
175 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
176 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
c695faf7
KV		 177
178 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags))
179 config->rx_decap_mode = TARGET_DECAP_MODE_RAW;
180 else
181 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
182
2d4bcbed
CH		 183 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
184 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
185 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
186 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
187 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS;
188 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS;
189 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE;
190 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
191 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES;
192 config->dma_burst_size = TARGET_DMA_BURST_SIZE;
193 config->rx_skip_defrag_timeout_dup_detection_check =
194 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
195 config->vow_config = TARGET_VOW_CONFIG;
196 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV;
197 config->num_msdu_desc = TARGET_NUM_MSDU_DESC;
198 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD;
199 config->rx_batchmode = TARGET_RX_BATCHMODE;
200 config->peer_map_unmap_v2_support = 1;
36c7c640 201 config->twt_ap_pdev_count = ab->num_radios;
2d4bcbed 202 config->twt_ap_sta_count = 1000;
9b4dd38b 203 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64;
01c6c9fc 204 config->flag1 |= WMI_RSRC_CFG_FLAG1_ACK_RSSI;
2d4bcbed
CH		 205}
206
4152e420
CH		 207static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw,
208 int mac_id)
209{
210 return mac_id;
211}
212
213static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw,
214 int mac_id)
215{
216 return 0;
217}
218
219static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw,
220 int mac_id)
221{
222 return 0;
223}
224
225static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw,
226 int mac_id)
227{
228 return mac_id;
229}
230
e678fbd4
KP		 231static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
232{
233 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU,
234 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
235}
236
237static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
238{
239 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU,
240 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
241}
242
243static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
244{
245 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
246 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
247}
248
249static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
250{
251 return desc->u.ipq8074.hdr_status;
252}
253
254static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
255{
256 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) &
257 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID;
258}
259
260static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
261{
262 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
263 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2));
264}
265
266static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc)
267{
268 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
269 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
270}
271
272static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
273{
274 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
275 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
276}
277
b3febdcc
P		 278static bool ath11k_hw_ipq8074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc)
279{
280 return FIELD_GET(RX_MSDU_START_INFO2_LDPC,
281 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
282}
283
e678fbd4
KP		 284static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
285{
286 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
287 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
288}
289
290static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
291{
292 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
293 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
294}
295
296static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
297{
298 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
299 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
300}
301
302static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
303{
304 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
305 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1));
306}
307
308static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
309{
310 return FIELD_GET(RX_MSDU_START_INFO3_SGI,
311 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
312}
313
314static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
315{
316 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
317 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
318}
319
320static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
321{
322 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
323 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
324}
325
326static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
327{
328 return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data);
329}
330
331static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
332{
333 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
334 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
335}
336
337static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
338{
339 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
340 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
341}
342
343static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
344{
345 return FIELD_GET(RX_MPDU_START_INFO2_TID,
346 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2));
347}
348
349static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
350{
351 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id);
352}
353
354static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
355 struct hal_rx_desc *ldesc)
356{
357 memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end,
358 sizeof(struct rx_msdu_end_ipq8074));
359 memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention,
360 sizeof(struct rx_attention));
361 memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end,
362 sizeof(struct rx_mpdu_end));
363}
364
365static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
366{
367 return FIELD_GET(HAL_TLV_HDR_TAG,
368 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag));
369}
370
371static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
372{
373 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id);
374}
375
376static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
377{
378 u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1);
379
380 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
381 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
382
383 desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info);
384}
385
2167fa60
S		 386static bool ath11k_hw_ipq8074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc)
387{
388 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) &
389 RX_MPDU_START_INFO1_MAC_ADDR2_VALID;
390}
391
392static u8 *ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc)
393{
394 return desc->u.ipq8074.mpdu_start.addr2;
395}
396
e678fbd4
KP		 397static
398struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc)
399{
400 return &desc->u.ipq8074.attention;
401}
402
403static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
404{
405 return &desc->u.ipq8074.msdu_payload[0];
406}
407
408static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
409{
410 return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU,
411 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
412}
413
414static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
415{
416 return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU,
417 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
418}
419
420static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
421{
422 return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING,
423 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
424}
425
426static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
427{
428 return desc->u.qcn9074.hdr_status;
429}
430
431static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
432{
433 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) &
434 RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID;
435}
436
437static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
438{
439 return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE,
440 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9));
441}
442
443static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc)
444{
445 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
446 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
447}
448
449static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
450{
451 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
452 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
453}
454
b3febdcc
P		 455static bool ath11k_hw_qcn9074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc)
456{
457 return FIELD_GET(RX_MSDU_START_INFO2_LDPC,
458 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
459}
460
e678fbd4
KP		 461static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
462{
463 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID,
464 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
465}
466
467static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
468{
469 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID,
470 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
471}
472
473static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
474{
475 return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM,
476 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
477}
478
479static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
480{
481 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
482 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1));
483}
484
485static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
486{
487 return FIELD_GET(RX_MSDU_START_INFO3_SGI,
488 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
489}
490
491static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
492{
493 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
494 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
495}
496
497static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
498{
499 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
500 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
501}
502
503static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
504{
505 return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data);
506}
507
508static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
509{
510 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
511 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
512}
513
514static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
515{
516 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
517 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
518}
519
520static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
521{
522 return FIELD_GET(RX_MPDU_START_INFO9_TID,
523 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9));
524}
525
526static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
527{
528 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id);
529}
530
531static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
532 struct hal_rx_desc *ldesc)
533{
534 memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end,
535 sizeof(struct rx_msdu_end_qcn9074));
536 memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention,
537 sizeof(struct rx_attention));
538 memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end,
539 sizeof(struct rx_mpdu_end));
540}
541
542static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
543{
544 return FIELD_GET(HAL_TLV_HDR_TAG,
545 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag));
546}
547
548static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
549{
550 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id);
551}
552
553static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
554{
555 u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1);
556
557 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
558 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
559
560 desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info);
561}
562
563static
564struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc)
565{
566 return &desc->u.qcn9074.attention;
567}
568
569static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
570{
571 return &desc->u.qcn9074.msdu_payload[0];
572}
573
2167fa60
S		 574static bool ath11k_hw_ipq9074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc)
575{
576 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) &
577 RX_MPDU_START_INFO11_MAC_ADDR2_VALID;
578}
579
580static u8 *ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc)
581{
582 return desc->u.qcn9074.mpdu_start.addr2;
583}
584
e4073430
BQ		 585static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
586{
587 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855,
588 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
589}
590
591static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
592{
593 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855,
594 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
595}
596
597static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
598{
599 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
600 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
601}
602
603static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
604{
605 return desc->u.wcn6855.hdr_status;
606}
607
608static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
609{
610 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) &
611 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID;
612}
613
614static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
615{
616 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
617 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
618}
619
620static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc)
621{
622 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
623 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
624}
625
626static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
627{
628 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
629 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
630}
631
632static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
633{
634 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
635 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
636}
637
638static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
639{
640 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
641 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
642}
643
644static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
645{
646 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
647 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
648}
649
650static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
651{
652 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
653 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1));
654}
655
656static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
657{
658 return FIELD_GET(RX_MSDU_START_INFO3_SGI,
659 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
660}
661
662static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
663{
664 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
665 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
666}
667
668static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
669{
670 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
671 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
672}
673
674static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
675{
676 return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data);
677}
678
679static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
680{
681 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
682 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
683}
684
685static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
686{
687 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
688 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
689}
690
691static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
692{
693 return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855,
694 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
695}
696
697static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
698{
699 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id);
700}
701
702static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
703 struct hal_rx_desc *ldesc)
704{
705 memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end,
706 sizeof(struct rx_msdu_end_wcn6855));
707 memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention,
708 sizeof(struct rx_attention));
709 memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end,
710 sizeof(struct rx_mpdu_end));
711}
712
713static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
714{
715 return FIELD_GET(HAL_TLV_HDR_TAG,
716 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag));
717}
718
719static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
720{
721 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id);
722}
723
724static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
725{
726 u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1);
727
728 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
729 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
730
731 desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info);
732}
733
734static
735struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc)
736{
737 return &desc->u.wcn6855.attention;
738}
739
740static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
741{
742 return &desc->u.wcn6855.msdu_payload[0];
743}
744
2167fa60
S		 745static bool ath11k_hw_wcn6855_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc)
746{
747 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) &
748 RX_MPDU_START_INFO1_MAC_ADDR2_VALID;
749}
750
751static u8 *ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc)
752{
753 return desc->u.wcn6855.mpdu_start.addr2;
754}
755
0d55b76f
BQ		 756static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab)
757{
758 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
759 u32 val;
760 /* Each hash entry uses four bits to map to a particular ring. */
761 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
762 HAL_HASH_ROUTING_RING_SW2 << 4 |
763 HAL_HASH_ROUTING_RING_SW3 << 8 |
764 HAL_HASH_ROUTING_RING_SW4 << 12 |
765 HAL_HASH_ROUTING_RING_SW1 << 16 |
766 HAL_HASH_ROUTING_RING_SW2 << 20 |
767 HAL_HASH_ROUTING_RING_SW3 << 24 |
768 HAL_HASH_ROUTING_RING_SW4 << 28;
769
770 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
771 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
772 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
773 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
774
22cc6873 775 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL(ab));
0d55b76f
BQ		 776 val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING;
777 val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1);
22cc6873 778 ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL(ab), val);
0d55b76f
BQ		 779
780 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
781 HAL_DEFAULT_REO_TIMEOUT_USEC);
782 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
783 HAL_DEFAULT_REO_TIMEOUT_USEC);
784 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
785 HAL_DEFAULT_REO_TIMEOUT_USEC);
786 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
787 HAL_DEFAULT_REO_TIMEOUT_USEC);
788
789 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
790 ring_hash_map);
791 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
792 ring_hash_map);
793}
794
69968f88
S		 795static void ath11k_hw_ipq5018_reo_setup(struct ath11k_base *ab)
796{
797 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
798 u32 val;
799
800 /* Each hash entry uses three bits to map to a particular ring. */
801 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
802 HAL_HASH_ROUTING_RING_SW2 << 4 |
803 HAL_HASH_ROUTING_RING_SW3 << 8 |
804 HAL_HASH_ROUTING_RING_SW4 << 12 |
805 HAL_HASH_ROUTING_RING_SW1 << 16 |
806 HAL_HASH_ROUTING_RING_SW2 << 20 |
807 HAL_HASH_ROUTING_RING_SW3 << 24 |
808 HAL_HASH_ROUTING_RING_SW4 << 28;
809
810 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
811
812 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
813 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
814 HAL_SRNG_RING_ID_REO2SW1) |
815 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
816 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
817 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
818
819 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
820 HAL_DEFAULT_REO_TIMEOUT_USEC);
821 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
822 HAL_DEFAULT_REO_TIMEOUT_USEC);
823 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
824 HAL_DEFAULT_REO_TIMEOUT_USEC);
825 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
826 HAL_DEFAULT_REO_TIMEOUT_USEC);
827
828 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
829 ring_hash_map);
830 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
831 ring_hash_map);
832 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
833 ring_hash_map);
834 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
835 ring_hash_map);
836}
837
031ffa6c
P		 838static u16
839ath11k_hw_ipq8074_mpdu_info_get_peerid(struct hal_rx_mpdu_info *mpdu_info)
8845fed1
BQ		 840{
841 u16 peer_id = 0;
8845fed1
BQ		 842
843 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID,
031ffa6c 844 __le32_to_cpu(mpdu_info->u.ipq8074.info0));
8845fed1
BQ		 845
846 return peer_id;
847}
848
031ffa6c
P		 849static u16
850ath11k_hw_qcn9074_mpdu_info_get_peerid(struct hal_rx_mpdu_info *mpdu_info)
851{
852 u16 peer_id = 0;
853
854 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID,
855 __le32_to_cpu(mpdu_info->u.qcn9074.info0));
856
857 return peer_id;
858}
859
860static u16
861ath11k_hw_wcn6855_mpdu_info_get_peerid(struct hal_rx_mpdu_info *mpdu_info)
8845fed1
BQ		 862{
863 u16 peer_id = 0;
8845fed1
BQ		 864
865 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855,
031ffa6c 866 __le32_to_cpu(mpdu_info->u.wcn6855.info0));
8845fed1
BQ		 867 return peer_id;
868}
869
648ab472
BQ		 870static bool ath11k_hw_wcn6855_rx_desc_get_ldpc_support(struct hal_rx_desc *desc)
871{
872 return FIELD_GET(RX_MSDU_START_INFO2_LDPC,
873 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
874}
875
7636c9a6
MP		 876static u32 ath11k_hw_ipq8074_get_tcl_ring_selector(struct sk_buff *skb)
877{
878 /* Let the default ring selection be based on current processor
879 * number, where one of the 3 tcl rings are selected based on
880 * the smp_processor_id(). In case that ring
881 * is full/busy, we resort to other available rings.
882 * If all rings are full, we drop the packet.
883 *
884 * TODO: Add throttling logic when all rings are full
885 */
886 return smp_processor_id();
887}
888
889static u32 ath11k_hw_wcn6750_get_tcl_ring_selector(struct sk_buff *skb)
890{
891 /* Select the TCL ring based on the flow hash of the SKB instead
892 * of CPU ID. Since applications pumping the traffic can be scheduled
893 * on multiple CPUs, there is a chance that packets of the same flow
894 * could end on different TCL rings, this could sometimes results in
895 * an out of order arrival of the packets at the receiver.
896 */
897 return skb_get_hash(skb);
898}
899
d547ca4c
AK		 900const struct ath11k_hw_ops ipq8074_ops = {
901 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
36c7c640 902 .wmi_init_config = ath11k_init_wmi_config_ipq8074,
4152e420
CH		 903 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
904 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
6fe6f68f 905 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
e678fbd4
KP		 906 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
907 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
908 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
909 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
910 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
911 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
912 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
913 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
b3febdcc 914 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support,
e678fbd4
KP		 915 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
916 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
917 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
918 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
919 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
920 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
921 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
922 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
923 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
924 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
925 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
926 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
927 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
928 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
929 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
930 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
931 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
932 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
0d55b76f 933 .reo_setup = ath11k_hw_ipq8074_reo_setup,
8845fed1 934 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
2167fa60
S		 935 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid,
936 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2,
7636c9a6 937 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
d547ca4c
AK		 938};
939
940const struct ath11k_hw_ops ipq6018_ops = {
941 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
2d4bcbed 942 .wmi_init_config = ath11k_init_wmi_config_ipq8074,
4152e420
CH		 943 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
944 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
6fe6f68f 945 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
e678fbd4
KP		 946 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
947 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
948 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
949 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
950 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
951 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
952 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
953 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
b3febdcc 954 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support,
e678fbd4
KP		 955 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
956 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
957 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
958 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
959 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
960 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
961 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
962 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
963 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
964 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
965 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
966 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
967 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
968 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
969 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
970 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
971 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
972 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
0d55b76f 973 .reo_setup = ath11k_hw_ipq8074_reo_setup,
8845fed1 974 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
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S		 975 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid,
976 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2,
7636c9a6 977 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
d547ca4c 978};
9de2ad43
CH		 979
980const struct ath11k_hw_ops qca6390_ops = {
981 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
4152e420
CH		 982 .wmi_init_config = ath11k_init_wmi_config_qca6390,
983 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
984 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
6fe6f68f 985 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
e678fbd4
KP		 986 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
987 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
988 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
989 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
990 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
991 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
992 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
993 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
b3febdcc 994 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support,
e678fbd4
KP		 995 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
996 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
997 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
998 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
999 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
1000 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
1001 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
1002 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
1003 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
1004 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
1005 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
1006 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
1007 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
1008 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
1009 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
1010 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
1011 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
1012 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
0d55b76f 1013 .reo_setup = ath11k_hw_ipq8074_reo_setup,
8845fed1 1014 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
2167fa60
S		 1015 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid,
1016 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2,
7636c9a6 1017 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
6fe6f68f
KP		 1018};
1019
1020const struct ath11k_hw_ops qcn9074_ops = {
1021 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
1022 .wmi_init_config = ath11k_init_wmi_config_ipq8074,
1023 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
1024 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
1025 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable,
e678fbd4
KP		 1026 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu,
1027 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu,
1028 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes,
1029 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status,
1030 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid,
1031 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type,
1032 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type,
1033 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl,
b3febdcc 1034 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support,
e678fbd4
KP		 1035 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld,
1036 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid,
1037 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no,
1038 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len,
1039 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi,
1040 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs,
1041 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw,
1042 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq,
1043 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type,
1044 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss,
1045 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid,
1046 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id,
1047 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end,
1048 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag,
1049 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
1050 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
1051 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
1052 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
0d55b76f 1053 .reo_setup = ath11k_hw_ipq8074_reo_setup,
031ffa6c 1054 .mpdu_info_get_peerid = ath11k_hw_qcn9074_mpdu_info_get_peerid,
2167fa60
S		 1055 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid,
1056 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2,
7636c9a6 1057 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
9de2ad43 1058};
34d5a3a8 1059
e4073430
BQ		 1060const struct ath11k_hw_ops wcn6855_ops = {
1061 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
1062 .wmi_init_config = ath11k_init_wmi_config_qca6390,
1063 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
1064 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
1065 .tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable,
1066 .rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu,
1067 .rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu,
1068 .rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes,
1069 .rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status,
1070 .rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid,
1071 .rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type,
1072 .rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type,
1073 .rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl,
648ab472 1074 .rx_desc_get_ldpc_support = ath11k_hw_wcn6855_rx_desc_get_ldpc_support,
e4073430
BQ		 1075 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld,
1076 .rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid,
1077 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no,
1078 .rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len,
1079 .rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi,
1080 .rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs,
1081 .rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw,
1082 .rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq,
1083 .rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type,
1084 .rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss,
1085 .rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid,
1086 .rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id,
1087 .rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end,
1088 .rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag,
1089 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id,
1090 .rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len,
1091 .rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention,
1092 .rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload,
0d55b76f 1093 .reo_setup = ath11k_hw_wcn6855_reo_setup,
8845fed1 1094 .mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid,
2167fa60
S		 1095 .rx_desc_mac_addr2_valid = ath11k_hw_wcn6855_rx_desc_mac_addr2_valid,
1096 .rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2,
7636c9a6 1097 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
e4073430
BQ		 1098};
1099
49890d9c
MP		 1100const struct ath11k_hw_ops wcn6750_ops = {
1101 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
1102 .wmi_init_config = ath11k_init_wmi_config_qca6390,
1103 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
1104 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
e67ba197
MP		 1105 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable,
1106 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu,
1107 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu,
1108 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes,
1109 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status,
1110 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid,
1111 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type,
1112 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type,
1113 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl,
1114 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support,
1115 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld,
1116 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid,
1117 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no,
1118 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len,
1119 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi,
1120 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs,
1121 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw,
1122 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq,
1123 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type,
1124 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss,
1125 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid,
1126 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id,
1127 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end,
1128 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag,
1129 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
1130 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
1131 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
1132 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
1133 .reo_setup = ath11k_hw_wcn6855_reo_setup,
1134 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
1135 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid,
1136 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2,
7636c9a6 1137 .get_ring_selector = ath11k_hw_wcn6750_get_tcl_ring_selector,
49890d9c
MP		 1138};
1139
ba60f279
S		 1140/* IPQ5018 hw ops is similar to QCN9074 except for the dest ring remap */
1141const struct ath11k_hw_ops ipq5018_ops = {
1142 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
1143 .wmi_init_config = ath11k_init_wmi_config_ipq8074,
1144 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
1145 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
1146 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable,
1147 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu,
1148 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu,
1149 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes,
1150 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status,
1151 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid,
1152 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type,
1153 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type,
1154 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl,
1155 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support,
1156 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld,
1157 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid,
1158 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no,
1159 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len,
1160 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi,
1161 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs,
1162 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw,
1163 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq,
1164 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type,
1165 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss,
1166 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid,
1167 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id,
1168 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end,
1169 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag,
1170 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
1171 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
1172 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
69968f88 1173 .reo_setup = ath11k_hw_ipq5018_reo_setup,
ba60f279
S		 1174 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
1175 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
1176 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid,
1177 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2,
1178
1179};
1180
7636c9a6
MP		 1181#define ATH11K_TX_RING_MASK_0 BIT(0)
1182#define ATH11K_TX_RING_MASK_1 BIT(1)
1183#define ATH11K_TX_RING_MASK_2 BIT(2)
1184#define ATH11K_TX_RING_MASK_3 BIT(3)
1185#define ATH11K_TX_RING_MASK_4 BIT(4)
34d5a3a8
KV		 1186
1187#define ATH11K_RX_RING_MASK_0 0x1
1188#define ATH11K_RX_RING_MASK_1 0x2
1189#define ATH11K_RX_RING_MASK_2 0x4
1190#define ATH11K_RX_RING_MASK_3 0x8
1191
1192#define ATH11K_RX_ERR_RING_MASK_0 0x1
1193
1194#define ATH11K_RX_WBM_REL_RING_MASK_0 0x1
1195
1196#define ATH11K_REO_STATUS_RING_MASK_0 0x1
1197
1198#define ATH11K_RXDMA2HOST_RING_MASK_0 0x1
1199#define ATH11K_RXDMA2HOST_RING_MASK_1 0x2
1200#define ATH11K_RXDMA2HOST_RING_MASK_2 0x4
1201
1202#define ATH11K_HOST2RXDMA_RING_MASK_0 0x1
1203#define ATH11K_HOST2RXDMA_RING_MASK_1 0x2
1204#define ATH11K_HOST2RXDMA_RING_MASK_2 0x4
1205
1206#define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1
1207#define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2
1208#define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4
1209
1210const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = {
1211 .tx = {
1212 ATH11K_TX_RING_MASK_0,
1213 ATH11K_TX_RING_MASK_1,
1214 ATH11K_TX_RING_MASK_2,
1215 },
1216 .rx_mon_status = {
1217 0, 0, 0, 0,
1218 ATH11K_RX_MON_STATUS_RING_MASK_0,
1219 ATH11K_RX_MON_STATUS_RING_MASK_1,
1220 ATH11K_RX_MON_STATUS_RING_MASK_2,
1221 },
1222 .rx = {
1223 0, 0, 0, 0, 0, 0, 0,
1224 ATH11K_RX_RING_MASK_0,
1225 ATH11K_RX_RING_MASK_1,
1226 ATH11K_RX_RING_MASK_2,
1227 ATH11K_RX_RING_MASK_3,
1228 },
1229 .rx_err = {
1230 ATH11K_RX_ERR_RING_MASK_0,
1231 },
1232 .rx_wbm_rel = {
1233 ATH11K_RX_WBM_REL_RING_MASK_0,
1234 },
1235 .reo_status = {
a8ae8336 1236 0, 0, 0,
34d5a3a8
KV		 1237 ATH11K_REO_STATUS_RING_MASK_0,
1238 },
1239 .rxdma2host = {
1240 ATH11K_RXDMA2HOST_RING_MASK_0,
1241 ATH11K_RXDMA2HOST_RING_MASK_1,
1242 ATH11K_RXDMA2HOST_RING_MASK_2,
1243 },
1244 .host2rxdma = {
1245 ATH11K_HOST2RXDMA_RING_MASK_0,
1246 ATH11K_HOST2RXDMA_RING_MASK_1,
1247 ATH11K_HOST2RXDMA_RING_MASK_2,
1248 },
1249};
1250
d4ecb90b
CH		 1251const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = {
1252 .tx = {
1253 ATH11K_TX_RING_MASK_0,
d4ecb90b
CH		 1254 },
1255 .rx_mon_status = {
1256 0, 0, 0, 0,
1257 ATH11K_RX_MON_STATUS_RING_MASK_0,
1258 ATH11K_RX_MON_STATUS_RING_MASK_1,
1259 ATH11K_RX_MON_STATUS_RING_MASK_2,
1260 },
1261 .rx = {
1262 0, 0, 0, 0, 0, 0, 0,
1263 ATH11K_RX_RING_MASK_0,
1264 ATH11K_RX_RING_MASK_1,
1265 ATH11K_RX_RING_MASK_2,
1266 ATH11K_RX_RING_MASK_3,
1267 },
1268 .rx_err = {
1269 ATH11K_RX_ERR_RING_MASK_0,
1270 },
1271 .rx_wbm_rel = {
1272 ATH11K_RX_WBM_REL_RING_MASK_0,
1273 },
1274 .reo_status = {
1275 ATH11K_REO_STATUS_RING_MASK_0,
1276 },
1277 .rxdma2host = {
1278 ATH11K_RXDMA2HOST_RING_MASK_0,
1279 ATH11K_RXDMA2HOST_RING_MASK_1,
1280 ATH11K_RXDMA2HOST_RING_MASK_2,
1281 },
1282 .host2rxdma = {
1283 },
1284};
1285
967c1d11
AK		 1286/* Target firmware's Copy Engine configuration. */
1287const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = {
1288 /* CE0: host->target HTC control and raw streams */
1289 {
1290 .pipenum = __cpu_to_le32(0),
1291 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1292 .nentries = __cpu_to_le32(32),
1293 .nbytes_max = __cpu_to_le32(2048),
1294 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1295 .reserved = __cpu_to_le32(0),
1296 },
1297
1298 /* CE1: target->host HTT + HTC control */
1299 {
1300 .pipenum = __cpu_to_le32(1),
1301 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1302 .nentries = __cpu_to_le32(32),
1303 .nbytes_max = __cpu_to_le32(2048),
1304 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1305 .reserved = __cpu_to_le32(0),
1306 },
1307
1308 /* CE2: target->host WMI */
1309 {
1310 .pipenum = __cpu_to_le32(2),
1311 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1312 .nentries = __cpu_to_le32(32),
1313 .nbytes_max = __cpu_to_le32(2048),
1314 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1315 .reserved = __cpu_to_le32(0),
1316 },
1317
1318 /* CE3: host->target WMI */
1319 {
1320 .pipenum = __cpu_to_le32(3),
1321 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1322 .nentries = __cpu_to_le32(32),
1323 .nbytes_max = __cpu_to_le32(2048),
1324 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1325 .reserved = __cpu_to_le32(0),
1326 },
1327
1328 /* CE4: host->target HTT */
1329 {
1330 .pipenum = __cpu_to_le32(4),
1331 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1332 .nentries = __cpu_to_le32(256),
1333 .nbytes_max = __cpu_to_le32(256),
1334 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1335 .reserved = __cpu_to_le32(0),
1336 },
1337
1338 /* CE5: target->host Pktlog */
1339 {
1340 .pipenum = __cpu_to_le32(5),
1341 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1342 .nentries = __cpu_to_le32(32),
1343 .nbytes_max = __cpu_to_le32(2048),
1344 .flags = __cpu_to_le32(0),
1345 .reserved = __cpu_to_le32(0),
1346 },
1347
1348 /* CE6: Reserved for target autonomous hif_memcpy */
1349 {
1350 .pipenum = __cpu_to_le32(6),
1351 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1352 .nentries = __cpu_to_le32(32),
1353 .nbytes_max = __cpu_to_le32(65535),
1354 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1355 .reserved = __cpu_to_le32(0),
1356 },
1357
1358 /* CE7 used only by Host */
1359 {
1360 .pipenum = __cpu_to_le32(7),
1361 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1362 .nentries = __cpu_to_le32(32),
1363 .nbytes_max = __cpu_to_le32(2048),
1364 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1365 .reserved = __cpu_to_le32(0),
1366 },
1367
1368 /* CE8 target->host used only by IPA */
1369 {
1370 .pipenum = __cpu_to_le32(8),
1371 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1372 .nentries = __cpu_to_le32(32),
1373 .nbytes_max = __cpu_to_le32(65535),
1374 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1375 .reserved = __cpu_to_le32(0),
1376 },
1377
1378 /* CE9 host->target HTT */
1379 {
1380 .pipenum = __cpu_to_le32(9),
1381 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1382 .nentries = __cpu_to_le32(32),
1383 .nbytes_max = __cpu_to_le32(2048),
1384 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1385 .reserved = __cpu_to_le32(0),
1386 },
1387
1388 /* CE10 target->host HTT */
1389 {
1390 .pipenum = __cpu_to_le32(10),
1391 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
1392 .nentries = __cpu_to_le32(0),
1393 .nbytes_max = __cpu_to_le32(0),
1394 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1395 .reserved = __cpu_to_le32(0),
1396 },
1397
1398 /* CE11 Not used */
1399};
1400
1401/* Map from service/endpoint to Copy Engine.
1402 * This table is derived from the CE_PCI TABLE, above.
1403 * It is passed to the Target at startup for use by firmware.
1404 */
1405const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = {
1406 {
1407 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1408 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1409 .pipenum = __cpu_to_le32(3),
1410 },
1411 {
1412 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1413 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1414 .pipenum = __cpu_to_le32(2),
1415 },
1416 {
1417 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1418 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1419 .pipenum = __cpu_to_le32(3),
1420 },
1421 {
1422 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1423 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1424 .pipenum = __cpu_to_le32(2),
1425 },
1426 {
1427 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1428 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1429 .pipenum = __cpu_to_le32(3),
1430 },
1431 {
1432 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1433 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1434 .pipenum = __cpu_to_le32(2),
1435 },
1436 {
1437 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1438 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1439 .pipenum = __cpu_to_le32(3),
1440 },
1441 {
1442 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1443 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1444 .pipenum = __cpu_to_le32(2),
1445 },
1446 {
1447 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1448 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1449 .pipenum = __cpu_to_le32(3),
1450 },
1451 {
1452 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1453 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1454 .pipenum = __cpu_to_le32(2),
1455 },
1456 {
1457 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
1458 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1459 .pipenum = __cpu_to_le32(7),
1460 },
1461 {
1462 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
1463 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1464 .pipenum = __cpu_to_le32(2),
1465 },
1466 {
1467 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2),
1468 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1469 .pipenum = __cpu_to_le32(9),
1470 },
1471 {
1472 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2),
1473 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1474 .pipenum = __cpu_to_le32(2),
1475 },
1476 {
1477 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1478 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1479 .pipenum = __cpu_to_le32(0),
1480 },
1481 {
1482 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1483 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1484 .pipenum = __cpu_to_le32(1),
1485 },
1486 { /* not used */
1487 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1488 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
b129699a
AK		 1489 .pipenum = __cpu_to_le32(0),
1490 },
1491 { /* not used */
1492 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1493 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1494 .pipenum = __cpu_to_le32(1),
1495 },
1496 {
1497 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1498 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1499 .pipenum = __cpu_to_le32(4),
1500 },
1501 {
1502 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1503 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1504 .pipenum = __cpu_to_le32(1),
1505 },
1506 {
1507 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
1508 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1509 .pipenum = __cpu_to_le32(5),
1510 },
1511
1512 /* (Additions here) */
1513
1514 { /* terminator entry */ }
1515};
1516
1517const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = {
1518 {
1519 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1520 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1521 .pipenum = __cpu_to_le32(3),
1522 },
1523 {
1524 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1525 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1526 .pipenum = __cpu_to_le32(2),
1527 },
1528 {
1529 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1530 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1531 .pipenum = __cpu_to_le32(3),
1532 },
1533 {
1534 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1535 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1536 .pipenum = __cpu_to_le32(2),
1537 },
1538 {
1539 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1540 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1541 .pipenum = __cpu_to_le32(3),
1542 },
1543 {
1544 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1545 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1546 .pipenum = __cpu_to_le32(2),
1547 },
1548 {
1549 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1550 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1551 .pipenum = __cpu_to_le32(3),
1552 },
1553 {
1554 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1555 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1556 .pipenum = __cpu_to_le32(2),
1557 },
1558 {
1559 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1560 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1561 .pipenum = __cpu_to_le32(3),
1562 },
1563 {
1564 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1565 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1566 .pipenum = __cpu_to_le32(2),
1567 },
1568 {
1569 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
1570 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1571 .pipenum = __cpu_to_le32(7),
1572 },
1573 {
1574 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
1575 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1576 .pipenum = __cpu_to_le32(2),
1577 },
1578 {
1579 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1580 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1581 .pipenum = __cpu_to_le32(0),
1582 },
1583 {
1584 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1585 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1586 .pipenum = __cpu_to_le32(1),
1587 },
1588 { /* not used */
1589 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1590 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
967c1d11
AK		 1591 .pipenum = __cpu_to_le32(0),
1592 },
1593 { /* not used */
1594 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1595 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1596 .pipenum = __cpu_to_le32(1),
1597 },
1598 {
1599 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1600 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1601 .pipenum = __cpu_to_le32(4),
1602 },
1603 {
1604 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1605 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1606 .pipenum = __cpu_to_le32(1),
1607 },
1608 {
1609 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
1610 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1611 .pipenum = __cpu_to_le32(5),
1612 },
1613
1614 /* (Additions here) */
1615
1616 { /* terminator entry */ }
1617};
1618
1619/* Target firmware's Copy Engine configuration. */
1620const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = {
1621 /* CE0: host->target HTC control and raw streams */
1622 {
1623 .pipenum = __cpu_to_le32(0),
1624 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1625 .nentries = __cpu_to_le32(32),
1626 .nbytes_max = __cpu_to_le32(2048),
1627 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1628 .reserved = __cpu_to_le32(0),
1629 },
1630
1631 /* CE1: target->host HTT + HTC control */
1632 {
1633 .pipenum = __cpu_to_le32(1),
1634 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1635 .nentries = __cpu_to_le32(32),
1636 .nbytes_max = __cpu_to_le32(2048),
1637 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1638 .reserved = __cpu_to_le32(0),
1639 },
1640
1641 /* CE2: target->host WMI */
1642 {
1643 .pipenum = __cpu_to_le32(2),
1644 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1645 .nentries = __cpu_to_le32(32),
1646 .nbytes_max = __cpu_to_le32(2048),
1647 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1648 .reserved = __cpu_to_le32(0),
1649 },
1650
1651 /* CE3: host->target WMI */
1652 {
1653 .pipenum = __cpu_to_le32(3),
1654 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1655 .nentries = __cpu_to_le32(32),
1656 .nbytes_max = __cpu_to_le32(2048),
1657 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1658 .reserved = __cpu_to_le32(0),
1659 },
1660
1661 /* CE4: host->target HTT */
1662 {
1663 .pipenum = __cpu_to_le32(4),
1664 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1665 .nentries = __cpu_to_le32(256),
1666 .nbytes_max = __cpu_to_le32(256),
1667 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1668 .reserved = __cpu_to_le32(0),
1669 },
1670
1671 /* CE5: target->host Pktlog */
1672 {
1673 .pipenum = __cpu_to_le32(5),
1674 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1675 .nentries = __cpu_to_le32(32),
1676 .nbytes_max = __cpu_to_le32(2048),
1677 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1678 .reserved = __cpu_to_le32(0),
1679 },
1680
1681 /* CE6: Reserved for target autonomous hif_memcpy */
1682 {
1683 .pipenum = __cpu_to_le32(6),
1684 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1685 .nentries = __cpu_to_le32(32),
1686 .nbytes_max = __cpu_to_le32(16384),
1687 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1688 .reserved = __cpu_to_le32(0),
1689 },
1690
1691 /* CE7 used only by Host */
1692 {
1693 .pipenum = __cpu_to_le32(7),
1694 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
1695 .nentries = __cpu_to_le32(0),
1696 .nbytes_max = __cpu_to_le32(0),
1697 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1698 .reserved = __cpu_to_le32(0),
1699 },
1700
1701 /* CE8 target->host used only by IPA */
1702 {
1703 .pipenum = __cpu_to_le32(8),
1704 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1705 .nentries = __cpu_to_le32(32),
1706 .nbytes_max = __cpu_to_le32(16384),
1707 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1708 .reserved = __cpu_to_le32(0),
1709 },
1710 /* CE 9, 10, 11 are used by MHI driver */
1711};
1712
1713/* Map from service/endpoint to Copy Engine.
1714 * This table is derived from the CE_PCI TABLE, above.
1715 * It is passed to the Target at startup for use by firmware.
1716 */
1717const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = {
1718 {
1719 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1720 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1721 __cpu_to_le32(3),
1722 },
1723 {
1724 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1725 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1726 __cpu_to_le32(2),
1727 },
1728 {
1729 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1730 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1731 __cpu_to_le32(3),
1732 },
1733 {
1734 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1735 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1736 __cpu_to_le32(2),
1737 },
1738 {
1739 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1740 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1741 __cpu_to_le32(3),
1742 },
1743 {
1744 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1745 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1746 __cpu_to_le32(2),
1747 },
1748 {
1749 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1750 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1751 __cpu_to_le32(3),
1752 },
1753 {
1754 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1755 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1756 __cpu_to_le32(2),
1757 },
1758 {
1759 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1760 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1761 __cpu_to_le32(3),
1762 },
1763 {
1764 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1765 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1766 __cpu_to_le32(2),
1767 },
1768 {
1769 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1770 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1771 __cpu_to_le32(0),
1772 },
1773 {
1774 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1775 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1776 __cpu_to_le32(2),
1777 },
1778 {
1779 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1780 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1781 __cpu_to_le32(4),
1782 },
1783 {
1784 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1785 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1786 __cpu_to_le32(1),
1787 },
1788
1789 /* (Additions here) */
1790
1791 { /* must be last */
1792 __cpu_to_le32(0),
1793 __cpu_to_le32(0),
1794 __cpu_to_le32(0),
1795 },
1796};
1797
6289ac2b
KP		 1798/* Target firmware's Copy Engine configuration. */
1799const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = {
1800 /* CE0: host->target HTC control and raw streams */
1801 {
1802 .pipenum = __cpu_to_le32(0),
1803 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1804 .nentries = __cpu_to_le32(32),
1805 .nbytes_max = __cpu_to_le32(2048),
1806 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1807 .reserved = __cpu_to_le32(0),
1808 },
1809
1810 /* CE1: target->host HTT + HTC control */
1811 {
1812 .pipenum = __cpu_to_le32(1),
1813 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1814 .nentries = __cpu_to_le32(32),
1815 .nbytes_max = __cpu_to_le32(2048),
1816 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1817 .reserved = __cpu_to_le32(0),
1818 },
1819
1820 /* CE2: target->host WMI */
1821 {
1822 .pipenum = __cpu_to_le32(2),
1823 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1824 .nentries = __cpu_to_le32(32),
1825 .nbytes_max = __cpu_to_le32(2048),
1826 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1827 .reserved = __cpu_to_le32(0),
1828 },
1829
1830 /* CE3: host->target WMI */
1831 {
1832 .pipenum = __cpu_to_le32(3),
1833 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1834 .nentries = __cpu_to_le32(32),
1835 .nbytes_max = __cpu_to_le32(2048),
1836 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1837 .reserved = __cpu_to_le32(0),
1838 },
1839
1840 /* CE4: host->target HTT */
1841 {
1842 .pipenum = __cpu_to_le32(4),
1843 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1844 .nentries = __cpu_to_le32(256),
1845 .nbytes_max = __cpu_to_le32(256),
1846 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1847 .reserved = __cpu_to_le32(0),
1848 },
1849
1850 /* CE5: target->host Pktlog */
1851 {
1852 .pipenum = __cpu_to_le32(5),
1853 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1854 .nentries = __cpu_to_le32(32),
1855 .nbytes_max = __cpu_to_le32(2048),
1856 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1857 .reserved = __cpu_to_le32(0),
1858 },
1859
1860 /* CE6: Reserved for target autonomous hif_memcpy */
1861 {
1862 .pipenum = __cpu_to_le32(6),
1863 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1864 .nentries = __cpu_to_le32(32),
1865 .nbytes_max = __cpu_to_le32(16384),
1866 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1867 .reserved = __cpu_to_le32(0),
1868 },
1869
1870 /* CE7 used only by Host */
1871 {
1872 .pipenum = __cpu_to_le32(7),
1873 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
1874 .nentries = __cpu_to_le32(0),
1875 .nbytes_max = __cpu_to_le32(0),
1876 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1877 .reserved = __cpu_to_le32(0),
1878 },
1879
1880 /* CE8 target->host used only by IPA */
1881 {
1882 .pipenum = __cpu_to_le32(8),
1883 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1884 .nentries = __cpu_to_le32(32),
1885 .nbytes_max = __cpu_to_le32(16384),
1886 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1887 .reserved = __cpu_to_le32(0),
1888 },
1889 /* CE 9, 10, 11 are used by MHI driver */
1890};
1891
1892/* Map from service/endpoint to Copy Engine.
1893 * This table is derived from the CE_PCI TABLE, above.
1894 * It is passed to the Target at startup for use by firmware.
1895 */
1896const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = {
1897 {
1898 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1899 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1900 __cpu_to_le32(3),
1901 },
1902 {
1903 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1904 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1905 __cpu_to_le32(2),
1906 },
1907 {
1908 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1909 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1910 __cpu_to_le32(3),
1911 },
1912 {
1913 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1914 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1915 __cpu_to_le32(2),
1916 },
1917 {
1918 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1919 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1920 __cpu_to_le32(3),
1921 },
1922 {
1923 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1924 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1925 __cpu_to_le32(2),
1926 },
1927 {
1928 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1929 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1930 __cpu_to_le32(3),
1931 },
1932 {
1933 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1934 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1935 __cpu_to_le32(2),
1936 },
1937 {
1938 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1939 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1940 __cpu_to_le32(3),
1941 },
1942 {
1943 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1944 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1945 __cpu_to_le32(2),
1946 },
1947 {
1948 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1949 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1950 __cpu_to_le32(0),
1951 },
1952 {
1953 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1954 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1955 __cpu_to_le32(1),
1956 },
1957 {
1958 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1959 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1960 __cpu_to_le32(0),
1961 },
1962 {
1963 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1964 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1965 __cpu_to_le32(1),
1966 },
1967 {
1968 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1969 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1970 __cpu_to_le32(4),
1971 },
1972 {
1973 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1974 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1975 __cpu_to_le32(1),
1976 },
1977 {
1978 __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
1979 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1980 __cpu_to_le32(5),
1981 },
1982
1983 /* (Additions here) */
1984
1985 { /* must be last */
1986 __cpu_to_le32(0),
1987 __cpu_to_le32(0),
1988 __cpu_to_le32(0),
1989 },
1990};
1991
7dc67af0
KP		 1992const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = {
1993 .tx = {
1994 ATH11K_TX_RING_MASK_0,
1995 ATH11K_TX_RING_MASK_1,
1996 ATH11K_TX_RING_MASK_2,
1997 },
1998 .rx_mon_status = {
1999 0, 0, 0,
2000 ATH11K_RX_MON_STATUS_RING_MASK_0,
2001 ATH11K_RX_MON_STATUS_RING_MASK_1,
2002 ATH11K_RX_MON_STATUS_RING_MASK_2,
2003 },
2004 .rx = {
2005 0, 0, 0, 0,
2006 ATH11K_RX_RING_MASK_0,
2007 ATH11K_RX_RING_MASK_1,
2008 ATH11K_RX_RING_MASK_2,
2009 ATH11K_RX_RING_MASK_3,
2010 },
2011 .rx_err = {
2012 0, 0, 0,
2013 ATH11K_RX_ERR_RING_MASK_0,
2014 },
2015 .rx_wbm_rel = {
2016 0, 0, 0,
2017 ATH11K_RX_WBM_REL_RING_MASK_0,
2018 },
2019 .reo_status = {
2020 0, 0, 0,
2021 ATH11K_REO_STATUS_RING_MASK_0,
2022 },
2023 .rxdma2host = {
2024 0, 0, 0,
2025 ATH11K_RXDMA2HOST_RING_MASK_0,
2026 },
2027 .host2rxdma = {
2028 0, 0, 0,
2029 ATH11K_HOST2RXDMA_RING_MASK_0,
2030 },
2031};
2032
7636c9a6
MP		 2033const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_wcn6750 = {
2034 .tx = {
2035 ATH11K_TX_RING_MASK_0,
2036 0,
2037 ATH11K_TX_RING_MASK_2,
2038 0,
2039 ATH11K_TX_RING_MASK_4,
2040 },
2041 .rx_mon_status = {
2042 0, 0, 0, 0, 0, 0,
2043 ATH11K_RX_MON_STATUS_RING_MASK_0,
2044 },
2045 .rx = {
2046 0, 0, 0, 0, 0, 0, 0,
2047 ATH11K_RX_RING_MASK_0,
2048 ATH11K_RX_RING_MASK_1,
2049 ATH11K_RX_RING_MASK_2,
2050 ATH11K_RX_RING_MASK_3,
2051 },
2052 .rx_err = {
2053 0, ATH11K_RX_ERR_RING_MASK_0,
2054 },
2055 .rx_wbm_rel = {
2056 0, ATH11K_RX_WBM_REL_RING_MASK_0,
2057 },
2058 .reo_status = {
2059 0, ATH11K_REO_STATUS_RING_MASK_0,
2060 },
2061 .rxdma2host = {
2062 ATH11K_RXDMA2HOST_RING_MASK_0,
2063 ATH11K_RXDMA2HOST_RING_MASK_1,
2064 ATH11K_RXDMA2HOST_RING_MASK_2,
2065 },
2066 .host2rxdma = {
2067 },
2068};
2069
26af7aab
S		 2070/* Target firmware's Copy Engine configuration for IPQ5018 */
2071const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[] = {
2072 /* CE0: host->target HTC control and raw streams */
2073 {
2074 .pipenum = __cpu_to_le32(0),
2075 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
2076 .nentries = __cpu_to_le32(32),
2077 .nbytes_max = __cpu_to_le32(2048),
2078 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
2079 .reserved = __cpu_to_le32(0),
2080 },
2081
2082 /* CE1: target->host HTT + HTC control */
2083 {
2084 .pipenum = __cpu_to_le32(1),
2085 .pipedir = __cpu_to_le32(PIPEDIR_IN),
2086 .nentries = __cpu_to_le32(32),
2087 .nbytes_max = __cpu_to_le32(2048),
2088 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
2089 .reserved = __cpu_to_le32(0),
2090 },
2091
2092 /* CE2: target->host WMI */
2093 {
2094 .pipenum = __cpu_to_le32(2),
2095 .pipedir = __cpu_to_le32(PIPEDIR_IN),
2096 .nentries = __cpu_to_le32(32),
2097 .nbytes_max = __cpu_to_le32(2048),
2098 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
2099 .reserved = __cpu_to_le32(0),
2100 },
2101
2102 /* CE3: host->target WMI */
2103 {
2104 .pipenum = __cpu_to_le32(3),
2105 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
2106 .nentries = __cpu_to_le32(32),
2107 .nbytes_max = __cpu_to_le32(2048),
2108 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
2109 .reserved = __cpu_to_le32(0),
2110 },
2111
2112 /* CE4: host->target HTT */
2113 {
2114 .pipenum = __cpu_to_le32(4),
2115 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
2116 .nentries = __cpu_to_le32(256),
2117 .nbytes_max = __cpu_to_le32(256),
2118 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
2119 .reserved = __cpu_to_le32(0),
2120 },
2121
2122 /* CE5: target->host Pktlog */
2123 {
2124 .pipenum = __cpu_to_le32(5),
2125 .pipedir = __cpu_to_le32(PIPEDIR_IN),
2126 .nentries = __cpu_to_le32(32),
2127 .nbytes_max = __cpu_to_le32(2048),
2128 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
2129 .reserved = __cpu_to_le32(0),
2130 },
2131
2132 /* CE6: Reserved for target autonomous hif_memcpy */
2133 {
2134 .pipenum = __cpu_to_le32(6),
2135 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
2136 .nentries = __cpu_to_le32(32),
2137 .nbytes_max = __cpu_to_le32(16384),
2138 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
2139 .reserved = __cpu_to_le32(0),
2140 },
2141
2142 /* CE7 used only by Host */
2143 {
2144 .pipenum = __cpu_to_le32(7),
2145 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
2146 .nentries = __cpu_to_le32(32),
2147 .nbytes_max = __cpu_to_le32(2048),
2148 .flags = __cpu_to_le32(0x2000),
2149 .reserved = __cpu_to_le32(0),
2150 },
2151
2152 /* CE8 target->host used only by IPA */
2153 {
2154 .pipenum = __cpu_to_le32(8),
2155 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
2156 .nentries = __cpu_to_le32(32),
2157 .nbytes_max = __cpu_to_le32(16384),
2158 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
2159 .reserved = __cpu_to_le32(0),
2160 },
2161};
2162
2163/* Map from service/endpoint to Copy Engine for IPQ5018.
2164 * This table is derived from the CE TABLE, above.
2165 * It is passed to the Target at startup for use by firmware.
2166 */
2167const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[] = {
2168 {
2169 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
2170 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
2171 .pipenum = __cpu_to_le32(3),
2172 },
2173 {
2174 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
2175 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
2176 .pipenum = __cpu_to_le32(2),
2177 },
2178 {
2179 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
2180 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
2181 .pipenum = __cpu_to_le32(3),
2182 },
2183 {
2184 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
2185 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
2186 .pipenum = __cpu_to_le32(2),
2187 },
2188 {
2189 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
2190 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
2191 .pipenum = __cpu_to_le32(3),
2192 },
2193 {
2194 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
2195 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
2196 .pipenum = __cpu_to_le32(2),
2197 },
2198 {
2199 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
2200 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
2201 .pipenum = __cpu_to_le32(3),
2202 },
2203 {
2204 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
2205 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
2206 .pipenum = __cpu_to_le32(2),
2207 },
2208 {
2209 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
2210 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
2211 .pipenum = __cpu_to_le32(3),
2212 },
2213 {
2214 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
2215 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
2216 .pipenum = __cpu_to_le32(2),
2217 },
2218
2219 {
2220 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
2221 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
2222 .pipenum = __cpu_to_le32(0),
2223 },
2224 {
2225 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
2226 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
2227 .pipenum = __cpu_to_le32(1),
2228 },
2229
2230 {
2231 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
2232 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
2233 .pipenum = __cpu_to_le32(0),
2234 },
2235 {
2236 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
2237 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
2238 .pipenum = __cpu_to_le32(1),
2239 },
2240 {
2241 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
2242 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
2243 .pipenum = __cpu_to_le32(4),
2244 },
2245 {
2246 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
2247 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
2248 .pipenum = __cpu_to_le32(1),
2249 },
2250 {
2251 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
2252 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
2253 .pipenum = __cpu_to_le32(5),
2254 },
2255
2256 /* (Additions here) */
2257
2258 { /* terminator entry */ }
2259};
2260
b42b3678
S		 2261const struct ce_ie_addr ath11k_ce_ie_addr_ipq8074 = {
2262 .ie1_reg_addr = CE_HOST_IE_ADDRESS,
2263 .ie2_reg_addr = CE_HOST_IE_2_ADDRESS,
2264 .ie3_reg_addr = CE_HOST_IE_3_ADDRESS,
2265};
2266
2267const struct ce_ie_addr ath11k_ce_ie_addr_ipq5018 = {
2268 .ie1_reg_addr = CE_HOST_IPQ5018_IE_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE,
2269 .ie2_reg_addr = CE_HOST_IPQ5018_IE_2_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE,
2270 .ie3_reg_addr = CE_HOST_IPQ5018_IE_3_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE,
2271};
2272
2273const struct ce_remap ath11k_ce_remap_ipq5018 = {
2274 .base = HAL_IPQ5018_CE_WFSS_REG_BASE,
2275 .size = HAL_IPQ5018_CE_SIZE,
2276};
2277
6976433c
CH		 2278const struct ath11k_hw_regs ipq8074_regs = {
2279 /* SW2TCL(x) R0 ring configuration address */
2280 .hal_tcl1_ring_base_lsb = 0x00000510,
2281 .hal_tcl1_ring_base_msb = 0x00000514,
2282 .hal_tcl1_ring_id = 0x00000518,
2283 .hal_tcl1_ring_misc = 0x00000520,
2284 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c,
2285 .hal_tcl1_ring_tp_addr_msb = 0x00000530,
2286 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540,
2287 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544,
2288 .hal_tcl1_ring_msi1_base_lsb = 0x00000558,
2289 .hal_tcl1_ring_msi1_base_msb = 0x0000055c,
2290 .hal_tcl1_ring_msi1_data = 0x00000560,
2291 .hal_tcl2_ring_base_lsb = 0x00000568,
2292 .hal_tcl_ring_base_lsb = 0x00000618,
2293
2294 /* TCL STATUS ring address */
2295 .hal_tcl_status_ring_base_lsb = 0x00000720,
2296
2297 /* REO2SW(x) R0 ring configuration address */
2298 .hal_reo1_ring_base_lsb = 0x0000029c,
2299 .hal_reo1_ring_base_msb = 0x000002a0,
2300 .hal_reo1_ring_id = 0x000002a4,
2301 .hal_reo1_ring_misc = 0x000002ac,
2302 .hal_reo1_ring_hp_addr_lsb = 0x000002b0,
2303 .hal_reo1_ring_hp_addr_msb = 0x000002b4,
2304 .hal_reo1_ring_producer_int_setup = 0x000002c0,
2305 .hal_reo1_ring_msi1_base_lsb = 0x000002e4,
2306 .hal_reo1_ring_msi1_base_msb = 0x000002e8,
2307 .hal_reo1_ring_msi1_data = 0x000002ec,
2308 .hal_reo2_ring_base_lsb = 0x000002f4,
2309 .hal_reo1_aging_thresh_ix_0 = 0x00000564,
2310 .hal_reo1_aging_thresh_ix_1 = 0x00000568,
2311 .hal_reo1_aging_thresh_ix_2 = 0x0000056c,
2312 .hal_reo1_aging_thresh_ix_3 = 0x00000570,
2313
2314 /* REO2SW(x) R2 ring pointers (head/tail) address */
2315 .hal_reo1_ring_hp = 0x00003038,
2316 .hal_reo1_ring_tp = 0x0000303c,
2317 .hal_reo2_ring_hp = 0x00003040,
2318
2319 /* REO2TCL R0 ring configuration address */
2320 .hal_reo_tcl_ring_base_lsb = 0x000003fc,
2321 .hal_reo_tcl_ring_hp = 0x00003058,
2322
49890d9c
MP		 2323 /* REO CMD ring address */
2324 .hal_reo_cmd_ring_base_lsb = 0x00000194,
2325 .hal_reo_cmd_ring_hp = 0x00003020,
2326
6976433c
CH		 2327 /* REO status address */
2328 .hal_reo_status_ring_base_lsb = 0x00000504,
2329 .hal_reo_status_hp = 0x00003070,
2330
49890d9c
MP		 2331 /* SW2REO ring address */
2332 .hal_sw2reo_ring_base_lsb = 0x000001ec,
2333 .hal_sw2reo_ring_hp = 0x00003028,
2334
6fe6f68f
KP		 2335 /* WCSS relative address */
2336 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
2337 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
2338 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000,
2339 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000,
2340
2341 /* WBM Idle address */
2342 .hal_wbm_idle_link_ring_base_lsb = 0x00000860,
2343 .hal_wbm_idle_link_ring_misc = 0x00000870,
2344
2345 /* SW2WBM release address */
2346 .hal_wbm_release_ring_base_lsb = 0x000001d8,
2347
2348 /* WBM2SW release address */
2349 .hal_wbm0_release_ring_base_lsb = 0x00000910,
2350 .hal_wbm1_release_ring_base_lsb = 0x00000968,
2351
2352 /* PCIe base address */
2353 .pcie_qserdes_sysclk_en_sel = 0x0,
2354 .pcie_pcs_osc_dtct_config_base = 0x0,
49890d9c
MP		 2355
2356 /* Shadow register area */
2357 .hal_shadow_base_addr = 0x0,
22cc6873
MP		 2358
2359 /* REO misc control register, not used in IPQ8074 */
2360 .hal_reo1_misc_ctl = 0x0,
6976433c
CH		 2361};
2362
2363const struct ath11k_hw_regs qca6390_regs = {
2364 /* SW2TCL(x) R0 ring configuration address */
2365 .hal_tcl1_ring_base_lsb = 0x00000684,
2366 .hal_tcl1_ring_base_msb = 0x00000688,
2367 .hal_tcl1_ring_id = 0x0000068c,
2368 .hal_tcl1_ring_misc = 0x00000694,
2369 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0,
2370 .hal_tcl1_ring_tp_addr_msb = 0x000006a4,
2371 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4,
2372 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8,
2373 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc,
2374 .hal_tcl1_ring_msi1_base_msb = 0x000006d0,
2375 .hal_tcl1_ring_msi1_data = 0x000006d4,
2376 .hal_tcl2_ring_base_lsb = 0x000006dc,
2377 .hal_tcl_ring_base_lsb = 0x0000078c,
2378
2379 /* TCL STATUS ring address */
2380 .hal_tcl_status_ring_base_lsb = 0x00000894,
2381
2382 /* REO2SW(x) R0 ring configuration address */
2383 .hal_reo1_ring_base_lsb = 0x00000244,
2384 .hal_reo1_ring_base_msb = 0x00000248,
2385 .hal_reo1_ring_id = 0x0000024c,
2386 .hal_reo1_ring_misc = 0x00000254,
2387 .hal_reo1_ring_hp_addr_lsb = 0x00000258,
2388 .hal_reo1_ring_hp_addr_msb = 0x0000025c,
2389 .hal_reo1_ring_producer_int_setup = 0x00000268,
2390 .hal_reo1_ring_msi1_base_lsb = 0x0000028c,
2391 .hal_reo1_ring_msi1_base_msb = 0x00000290,
2392 .hal_reo1_ring_msi1_data = 0x00000294,
2393 .hal_reo2_ring_base_lsb = 0x0000029c,
2394 .hal_reo1_aging_thresh_ix_0 = 0x0000050c,
2395 .hal_reo1_aging_thresh_ix_1 = 0x00000510,
2396 .hal_reo1_aging_thresh_ix_2 = 0x00000514,
2397 .hal_reo1_aging_thresh_ix_3 = 0x00000518,
2398
2399 /* REO2SW(x) R2 ring pointers (head/tail) address */
2400 .hal_reo1_ring_hp = 0x00003030,
2401 .hal_reo1_ring_tp = 0x00003034,
2402 .hal_reo2_ring_hp = 0x00003038,
2403
2404 /* REO2TCL R0 ring configuration address */
2405 .hal_reo_tcl_ring_base_lsb = 0x000003a4,
2406 .hal_reo_tcl_ring_hp = 0x00003050,
2407
49890d9c
MP		 2408 /* REO CMD ring address */
2409 .hal_reo_cmd_ring_base_lsb = 0x00000194,
2410 .hal_reo_cmd_ring_hp = 0x00003020,
2411
6976433c
CH		 2412 /* REO status address */
2413 .hal_reo_status_ring_base_lsb = 0x000004ac,
2414 .hal_reo_status_hp = 0x00003068,
6fe6f68f 2415
49890d9c
MP		 2416 /* SW2REO ring address */
2417 .hal_sw2reo_ring_base_lsb = 0x000001ec,
2418 .hal_sw2reo_ring_hp = 0x00003028,
2419
6fe6f68f
KP		 2420 /* WCSS relative address */
2421 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
2422 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
2423 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000,
2424 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000,
2425
2426 /* WBM Idle address */
2427 .hal_wbm_idle_link_ring_base_lsb = 0x00000860,
2428 .hal_wbm_idle_link_ring_misc = 0x00000870,
2429
2430 /* SW2WBM release address */
2431 .hal_wbm_release_ring_base_lsb = 0x000001d8,
2432
2433 /* WBM2SW release address */
2434 .hal_wbm0_release_ring_base_lsb = 0x00000910,
2435 .hal_wbm1_release_ring_base_lsb = 0x00000968,
2436
2437 /* PCIe base address */
2438 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
2439 .pcie_pcs_osc_dtct_config_base = 0x01e0c628,
49890d9c
MP		 2440
2441 /* Shadow register area */
2442 .hal_shadow_base_addr = 0x000008fc,
22cc6873
MP		 2443
2444 /* REO misc control register, not used in QCA6390 */
2445 .hal_reo1_misc_ctl = 0x0,
6fe6f68f
KP		 2446};
2447
2448const struct ath11k_hw_regs qcn9074_regs = {
2449 /* SW2TCL(x) R0 ring configuration address */
2450 .hal_tcl1_ring_base_lsb = 0x000004f0,
2451 .hal_tcl1_ring_base_msb = 0x000004f4,
2452 .hal_tcl1_ring_id = 0x000004f8,
2453 .hal_tcl1_ring_misc = 0x00000500,
2454 .hal_tcl1_ring_tp_addr_lsb = 0x0000050c,
2455 .hal_tcl1_ring_tp_addr_msb = 0x00000510,
2456 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520,
2457 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524,
2458 .hal_tcl1_ring_msi1_base_lsb = 0x00000538,
2459 .hal_tcl1_ring_msi1_base_msb = 0x0000053c,
2460 .hal_tcl1_ring_msi1_data = 0x00000540,
2461 .hal_tcl2_ring_base_lsb = 0x00000548,
2462 .hal_tcl_ring_base_lsb = 0x000005f8,
2463
2464 /* TCL STATUS ring address */
2465 .hal_tcl_status_ring_base_lsb = 0x00000700,
2466
2467 /* REO2SW(x) R0 ring configuration address */
2468 .hal_reo1_ring_base_lsb = 0x0000029c,
2469 .hal_reo1_ring_base_msb = 0x000002a0,
2470 .hal_reo1_ring_id = 0x000002a4,
2471 .hal_reo1_ring_misc = 0x000002ac,
2472 .hal_reo1_ring_hp_addr_lsb = 0x000002b0,
2473 .hal_reo1_ring_hp_addr_msb = 0x000002b4,
2474 .hal_reo1_ring_producer_int_setup = 0x000002c0,
2475 .hal_reo1_ring_msi1_base_lsb = 0x000002e4,
2476 .hal_reo1_ring_msi1_base_msb = 0x000002e8,
2477 .hal_reo1_ring_msi1_data = 0x000002ec,
2478 .hal_reo2_ring_base_lsb = 0x000002f4,
2479 .hal_reo1_aging_thresh_ix_0 = 0x00000564,
2480 .hal_reo1_aging_thresh_ix_1 = 0x00000568,
2481 .hal_reo1_aging_thresh_ix_2 = 0x0000056c,
2482 .hal_reo1_aging_thresh_ix_3 = 0x00000570,
2483
2484 /* REO2SW(x) R2 ring pointers (head/tail) address */
2485 .hal_reo1_ring_hp = 0x00003038,
2486 .hal_reo1_ring_tp = 0x0000303c,
2487 .hal_reo2_ring_hp = 0x00003040,
2488
2489 /* REO2TCL R0 ring configuration address */
2490 .hal_reo_tcl_ring_base_lsb = 0x000003fc,
2491 .hal_reo_tcl_ring_hp = 0x00003058,
2492
49890d9c
MP		 2493 /* REO CMD ring address */
2494 .hal_reo_cmd_ring_base_lsb = 0x00000194,
2495 .hal_reo_cmd_ring_hp = 0x00003020,
2496
6fe6f68f
KP		 2497 /* REO status address */
2498 .hal_reo_status_ring_base_lsb = 0x00000504,
2499 .hal_reo_status_hp = 0x00003070,
2500
49890d9c
MP		 2501 /* SW2REO ring address */
2502 .hal_sw2reo_ring_base_lsb = 0x000001ec,
2503 .hal_sw2reo_ring_hp = 0x00003028,
2504
6fe6f68f
KP		 2505 /* WCSS relative address */
2506 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
2507 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
2508 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,
2509 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,
2510
2511 /* WBM Idle address */
2512 .hal_wbm_idle_link_ring_base_lsb = 0x00000874,
2513 .hal_wbm_idle_link_ring_misc = 0x00000884,
2514
2515 /* SW2WBM release address */
2516 .hal_wbm_release_ring_base_lsb = 0x000001ec,
2517
2518 /* WBM2SW release address */
2519 .hal_wbm0_release_ring_base_lsb = 0x00000924,
2520 .hal_wbm1_release_ring_base_lsb = 0x0000097c,
2521
2522 /* PCIe base address */
2523 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
2524 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
49890d9c
MP		 2525
2526 /* Shadow register area */
2527 .hal_shadow_base_addr = 0x0,
22cc6873
MP		 2528
2529 /* REO misc control register, not used in QCN9074 */
2530 .hal_reo1_misc_ctl = 0x0,
6976433c 2531};
755b1f73
BQ		 2532
2533const struct ath11k_hw_regs wcn6855_regs = {
2534 /* SW2TCL(x) R0 ring configuration address */
2535 .hal_tcl1_ring_base_lsb = 0x00000690,
2536 .hal_tcl1_ring_base_msb = 0x00000694,
2537 .hal_tcl1_ring_id = 0x00000698,
2538 .hal_tcl1_ring_misc = 0x000006a0,
2539 .hal_tcl1_ring_tp_addr_lsb = 0x000006ac,
2540 .hal_tcl1_ring_tp_addr_msb = 0x000006b0,
2541 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0,
2542 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4,
2543 .hal_tcl1_ring_msi1_base_lsb = 0x000006d8,
2544 .hal_tcl1_ring_msi1_base_msb = 0x000006dc,
2545 .hal_tcl1_ring_msi1_data = 0x000006e0,
2546 .hal_tcl2_ring_base_lsb = 0x000006e8,
2547 .hal_tcl_ring_base_lsb = 0x00000798,
2548
2549 /* TCL STATUS ring address */
2550 .hal_tcl_status_ring_base_lsb = 0x000008a0,
2551
2552 /* REO2SW(x) R0 ring configuration address */
2553 .hal_reo1_ring_base_lsb = 0x00000244,
2554 .hal_reo1_ring_base_msb = 0x00000248,
2555 .hal_reo1_ring_id = 0x0000024c,
2556 .hal_reo1_ring_misc = 0x00000254,
2557 .hal_reo1_ring_hp_addr_lsb = 0x00000258,
2558 .hal_reo1_ring_hp_addr_msb = 0x0000025c,
2559 .hal_reo1_ring_producer_int_setup = 0x00000268,
2560 .hal_reo1_ring_msi1_base_lsb = 0x0000028c,
2561 .hal_reo1_ring_msi1_base_msb = 0x00000290,
2562 .hal_reo1_ring_msi1_data = 0x00000294,
2563 .hal_reo2_ring_base_lsb = 0x0000029c,
2564 .hal_reo1_aging_thresh_ix_0 = 0x000005bc,
2565 .hal_reo1_aging_thresh_ix_1 = 0x000005c0,
2566 .hal_reo1_aging_thresh_ix_2 = 0x000005c4,
2567 .hal_reo1_aging_thresh_ix_3 = 0x000005c8,
2568
2569 /* REO2SW(x) R2 ring pointers (head/tail) address */
2570 .hal_reo1_ring_hp = 0x00003030,
2571 .hal_reo1_ring_tp = 0x00003034,
2572 .hal_reo2_ring_hp = 0x00003038,
2573
2574 /* REO2TCL R0 ring configuration address */
2575 .hal_reo_tcl_ring_base_lsb = 0x00000454,
2576 .hal_reo_tcl_ring_hp = 0x00003060,
2577
49890d9c
MP		 2578 /* REO CMD ring address */
2579 .hal_reo_cmd_ring_base_lsb = 0x00000194,
2580 .hal_reo_cmd_ring_hp = 0x00003020,
2581
755b1f73
BQ		 2582 /* REO status address */
2583 .hal_reo_status_ring_base_lsb = 0x0000055c,
2584 .hal_reo_status_hp = 0x00003078,
2585
49890d9c
MP		 2586 /* SW2REO ring address */
2587 .hal_sw2reo_ring_base_lsb = 0x000001ec,
2588 .hal_sw2reo_ring_hp = 0x00003028,
2589
755b1f73
BQ		 2590 /* WCSS relative address */
2591 .hal_seq_wcss_umac_ce0_src_reg = 0x1b80000,
2592 .hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000,
2593 .hal_seq_wcss_umac_ce1_src_reg = 0x1b82000,
2594 .hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000,
2595
2596 /* WBM Idle address */
2597 .hal_wbm_idle_link_ring_base_lsb = 0x00000870,
2598 .hal_wbm_idle_link_ring_misc = 0x00000880,
2599
2600 /* SW2WBM release address */
2601 .hal_wbm_release_ring_base_lsb = 0x000001e8,
2602
2603 /* WBM2SW release address */
2604 .hal_wbm0_release_ring_base_lsb = 0x00000920,
2605 .hal_wbm1_release_ring_base_lsb = 0x00000978,
2606
2607 /* PCIe base address */
2608 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
2609 .pcie_pcs_osc_dtct_config_base = 0x01e0c628,
49890d9c
MP		 2610
2611 /* Shadow register area */
2612 .hal_shadow_base_addr = 0x000008fc,
22cc6873
MP		 2613
2614 /* REO misc control register, used for fragment
2615 * destination ring config in WCN6855.
2616 */
2617 .hal_reo1_misc_ctl = 0x00000630,
49890d9c
MP		 2618};
2619
2620const struct ath11k_hw_regs wcn6750_regs = {
2621 /* SW2TCL(x) R0 ring configuration address */
2622 .hal_tcl1_ring_base_lsb = 0x00000694,
2623 .hal_tcl1_ring_base_msb = 0x00000698,
2624 .hal_tcl1_ring_id = 0x0000069c,
2625 .hal_tcl1_ring_misc = 0x000006a4,
2626 .hal_tcl1_ring_tp_addr_lsb = 0x000006b0,
2627 .hal_tcl1_ring_tp_addr_msb = 0x000006b4,
2628 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4,
2629 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8,
2630 .hal_tcl1_ring_msi1_base_lsb = 0x000006dc,
2631 .hal_tcl1_ring_msi1_base_msb = 0x000006e0,
2632 .hal_tcl1_ring_msi1_data = 0x000006e4,
2633 .hal_tcl2_ring_base_lsb = 0x000006ec,
2634 .hal_tcl_ring_base_lsb = 0x0000079c,
2635
2636 /* TCL STATUS ring address */
2637 .hal_tcl_status_ring_base_lsb = 0x000008a4,
2638
2639 /* REO2SW(x) R0 ring configuration address */
2640 .hal_reo1_ring_base_lsb = 0x000001ec,
2641 .hal_reo1_ring_base_msb = 0x000001f0,
2642 .hal_reo1_ring_id = 0x000001f4,
2643 .hal_reo1_ring_misc = 0x000001fc,
2644 .hal_reo1_ring_hp_addr_lsb = 0x00000200,
2645 .hal_reo1_ring_hp_addr_msb = 0x00000204,
2646 .hal_reo1_ring_producer_int_setup = 0x00000210,
2647 .hal_reo1_ring_msi1_base_lsb = 0x00000234,
2648 .hal_reo1_ring_msi1_base_msb = 0x00000238,
2649 .hal_reo1_ring_msi1_data = 0x0000023c,
2650 .hal_reo2_ring_base_lsb = 0x00000244,
2651 .hal_reo1_aging_thresh_ix_0 = 0x00000564,
2652 .hal_reo1_aging_thresh_ix_1 = 0x00000568,
2653 .hal_reo1_aging_thresh_ix_2 = 0x0000056c,
2654 .hal_reo1_aging_thresh_ix_3 = 0x00000570,
2655
2656 /* REO2SW(x) R2 ring pointers (head/tail) address */
2657 .hal_reo1_ring_hp = 0x00003028,
2658 .hal_reo1_ring_tp = 0x0000302c,
2659 .hal_reo2_ring_hp = 0x00003030,
2660
2661 /* REO2TCL R0 ring configuration address */
2662 .hal_reo_tcl_ring_base_lsb = 0x000003fc,
2663 .hal_reo_tcl_ring_hp = 0x00003058,
2664
2665 /* REO CMD ring address */
2666 .hal_reo_cmd_ring_base_lsb = 0x000000e4,
2667 .hal_reo_cmd_ring_hp = 0x00003010,
2668
2669 /* REO status address */
2670 .hal_reo_status_ring_base_lsb = 0x00000504,
2671 .hal_reo_status_hp = 0x00003070,
2672
2673 /* SW2REO ring address */
2674 .hal_sw2reo_ring_base_lsb = 0x0000013c,
2675 .hal_sw2reo_ring_hp = 0x00003018,
2676
2677 /* WCSS relative address */
2678 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
2679 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
2680 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,
2681 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,
2682
2683 /* WBM Idle address */
2684 .hal_wbm_idle_link_ring_base_lsb = 0x00000874,
2685 .hal_wbm_idle_link_ring_misc = 0x00000884,
2686
2687 /* SW2WBM release address */
2688 .hal_wbm_release_ring_base_lsb = 0x000001ec,
2689
2690 /* WBM2SW release address */
2691 .hal_wbm0_release_ring_base_lsb = 0x00000924,
2692 .hal_wbm1_release_ring_base_lsb = 0x0000097c,
2693
2694 /* PCIe base address */
2695 .pcie_qserdes_sysclk_en_sel = 0x0,
2696 .pcie_pcs_osc_dtct_config_base = 0x0,
2697
2698 /* Shadow register area */
2699 .hal_shadow_base_addr = 0x00000504,
22cc6873
MP		 2700
2701 /* REO misc control register, used for fragment
2702 * destination ring config in WCN6750.
2703 */
2704 .hal_reo1_misc_ctl = 0x000005d8,
755b1f73 2705};
734223d7 2706
7636c9a6
MP		 2707static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_ipq8074[] = {
2708 {
2709 .tcl_ring_num = 0,
2710 .wbm_ring_num = 0,
2711 .rbm_id = HAL_RX_BUF_RBM_SW0_BM,
2712 },
2713 {
2714 .tcl_ring_num = 1,
2715 .wbm_ring_num = 1,
2716 .rbm_id = HAL_RX_BUF_RBM_SW1_BM,
2717 },
2718 {
2719 .tcl_ring_num = 2,
2720 .wbm_ring_num = 2,
2721 .rbm_id = HAL_RX_BUF_RBM_SW2_BM,
2722 },
2723};
2724
2725static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_wcn6750[] = {
2726 {
2727 .tcl_ring_num = 0,
2728 .wbm_ring_num = 0,
2729 .rbm_id = HAL_RX_BUF_RBM_SW0_BM,
2730 },
2731 {
2732 .tcl_ring_num = 1,
2733 .wbm_ring_num = 4,
2734 .rbm_id = HAL_RX_BUF_RBM_SW4_BM,
2735 },
2736 {
2737 .tcl_ring_num = 2,
2738 .wbm_ring_num = 2,
2739 .rbm_id = HAL_RX_BUF_RBM_SW2_BM,
2740 },
2741};
2742
711b80ac
S		 2743const struct ath11k_hw_regs ipq5018_regs = {
2744 /* SW2TCL(x) R0 ring configuration address */
2745 .hal_tcl1_ring_base_lsb = 0x00000694,
2746 .hal_tcl1_ring_base_msb = 0x00000698,
2747 .hal_tcl1_ring_id = 0x0000069c,
2748 .hal_tcl1_ring_misc = 0x000006a4,
2749 .hal_tcl1_ring_tp_addr_lsb = 0x000006b0,
2750 .hal_tcl1_ring_tp_addr_msb = 0x000006b4,
2751 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4,
2752 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8,
2753 .hal_tcl1_ring_msi1_base_lsb = 0x000006dc,
2754 .hal_tcl1_ring_msi1_base_msb = 0x000006e0,
2755 .hal_tcl1_ring_msi1_data = 0x000006e4,
2756 .hal_tcl2_ring_base_lsb = 0x000006ec,
2757 .hal_tcl_ring_base_lsb = 0x0000079c,
2758
2759 /* TCL STATUS ring address */
2760 .hal_tcl_status_ring_base_lsb = 0x000008a4,
2761
2762 /* REO2SW(x) R0 ring configuration address */
2763 .hal_reo1_ring_base_lsb = 0x000001ec,
2764 .hal_reo1_ring_base_msb = 0x000001f0,
2765 .hal_reo1_ring_id = 0x000001f4,
2766 .hal_reo1_ring_misc = 0x000001fc,
2767 .hal_reo1_ring_hp_addr_lsb = 0x00000200,
2768 .hal_reo1_ring_hp_addr_msb = 0x00000204,
2769 .hal_reo1_ring_producer_int_setup = 0x00000210,
2770 .hal_reo1_ring_msi1_base_lsb = 0x00000234,
2771 .hal_reo1_ring_msi1_base_msb = 0x00000238,
2772 .hal_reo1_ring_msi1_data = 0x0000023c,
2773 .hal_reo2_ring_base_lsb = 0x00000244,
2774 .hal_reo1_aging_thresh_ix_0 = 0x00000564,
2775 .hal_reo1_aging_thresh_ix_1 = 0x00000568,
2776 .hal_reo1_aging_thresh_ix_2 = 0x0000056c,
2777 .hal_reo1_aging_thresh_ix_3 = 0x00000570,
2778
2779 /* REO2SW(x) R2 ring pointers (head/tail) address */
2780 .hal_reo1_ring_hp = 0x00003028,
2781 .hal_reo1_ring_tp = 0x0000302c,
2782 .hal_reo2_ring_hp = 0x00003030,
2783
2784 /* REO2TCL R0 ring configuration address */
2785 .hal_reo_tcl_ring_base_lsb = 0x000003fc,
2786 .hal_reo_tcl_ring_hp = 0x00003058,
2787
2788 /* SW2REO ring address */
2789 .hal_sw2reo_ring_base_lsb = 0x0000013c,
2790 .hal_sw2reo_ring_hp = 0x00003018,
2791
2792 /* REO CMD ring address */
2793 .hal_reo_cmd_ring_base_lsb = 0x000000e4,
2794 .hal_reo_cmd_ring_hp = 0x00003010,
2795
2796 /* REO status address */
2797 .hal_reo_status_ring_base_lsb = 0x00000504,
2798 .hal_reo_status_hp = 0x00003070,
2799
2800 /* WCSS relative address */
2801 .hal_seq_wcss_umac_ce0_src_reg = 0x08400000
2802 - HAL_IPQ5018_CE_WFSS_REG_BASE,
2803 .hal_seq_wcss_umac_ce0_dst_reg = 0x08401000
2804 - HAL_IPQ5018_CE_WFSS_REG_BASE,
2805 .hal_seq_wcss_umac_ce1_src_reg = 0x08402000
2806 - HAL_IPQ5018_CE_WFSS_REG_BASE,
2807 .hal_seq_wcss_umac_ce1_dst_reg = 0x08403000
2808 - HAL_IPQ5018_CE_WFSS_REG_BASE,
2809
2810 /* WBM Idle address */
2811 .hal_wbm_idle_link_ring_base_lsb = 0x00000874,
2812 .hal_wbm_idle_link_ring_misc = 0x00000884,
2813
2814 /* SW2WBM release address */
2815 .hal_wbm_release_ring_base_lsb = 0x000001ec,
2816
2817 /* WBM2SW release address */
2818 .hal_wbm0_release_ring_base_lsb = 0x00000924,
2819 .hal_wbm1_release_ring_base_lsb = 0x0000097c,
2820};
2821
734223d7
BQ		 2822const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = {
2823 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM,
7636c9a6 2824 .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074,
734223d7
BQ		 2825};
2826
2827const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390 = {
2828 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM,
7636c9a6
MP		 2829 .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074,
2830};
2831
2832const struct ath11k_hw_hal_params ath11k_hw_hal_params_wcn6750 = {
2833 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM,
2834 .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_wcn6750,
734223d7 2835};
652f69ed
BQ		 2836
2837static const struct cfg80211_sar_freq_ranges ath11k_hw_sar_freq_ranges_wcn6855[] = {
2838 {.start_freq = 2402, .end_freq = 2482 }, /* 2G ch1~ch13 */
2839 {.start_freq = 5150, .end_freq = 5250 }, /* 5G UNII-1 ch32~ch48 */
2840 {.start_freq = 5250, .end_freq = 5725 }, /* 5G UNII-2 ch50~ch144 */
2841 {.start_freq = 5725, .end_freq = 5810 }, /* 5G UNII-3 ch149~ch161 */
2842 {.start_freq = 5815, .end_freq = 5895 }, /* 5G UNII-4 ch163~ch177 */
2843 {.start_freq = 5925, .end_freq = 6165 }, /* 6G UNII-5 Ch1, Ch2 ~ Ch41 */
2844 {.start_freq = 6165, .end_freq = 6425 }, /* 6G UNII-5 ch45~ch93 */
2845 {.start_freq = 6425, .end_freq = 6525 }, /* 6G UNII-6 ch97~ch113 */
2846 {.start_freq = 6525, .end_freq = 6705 }, /* 6G UNII-7 ch117~ch149 */
2847 {.start_freq = 6705, .end_freq = 6875 }, /* 6G UNII-7 ch153~ch185 */
2848 {.start_freq = 6875, .end_freq = 7125 }, /* 6G UNII-8 ch189~ch233 */
2849};
2850
2851const struct cfg80211_sar_capa ath11k_hw_sar_capa_wcn6855 = {
2852 .type = NL80211_SAR_TYPE_POWER,
2853 .num_freq_ranges = (ARRAY_SIZE(ath11k_hw_sar_freq_ranges_wcn6855)),
2854 .freq_ranges = ath11k_hw_sar_freq_ranges_wcn6855,
2855};
Linux 6.x block layer and io_uring tree(s)