[linux-2.6-block.git] / drivers / net / wireless / ath / ath11k / hal_rx.h

/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
 */

#ifndef ATH11K_HAL_RX_H
#define ATH11K_HAL_RX_H

struct hal_rx_wbm_rel_info {
	u32 cookie;
	enum hal_wbm_rel_src_module err_rel_src;
	enum hal_reo_dest_ring_push_reason push_reason;
	u32 err_code;
	bool first_msdu;
	bool last_msdu;
};

#define HAL_INVALID_PEERID 0xffff
#define VHT_SIG_SU_NSS_MASK 0x7

#define HAL_RX_MAX_MCS 12
#define HAL_RX_MAX_NSS 8

struct hal_rx_mon_status_tlv_hdr {
	u32 hdr;
	u8 value[];
};

enum hal_rx_su_mu_coding {
	HAL_RX_SU_MU_CODING_BCC,
	HAL_RX_SU_MU_CODING_LDPC,
	HAL_RX_SU_MU_CODING_MAX,
};

enum hal_rx_gi {
	HAL_RX_GI_0_8_US,
	HAL_RX_GI_0_4_US,
	HAL_RX_GI_1_6_US,
	HAL_RX_GI_3_2_US,
	HAL_RX_GI_MAX,
};

enum hal_rx_bw {
	HAL_RX_BW_20MHZ,
	HAL_RX_BW_40MHZ,
	HAL_RX_BW_80MHZ,
	HAL_RX_BW_160MHZ,
	HAL_RX_BW_MAX,
};

enum hal_rx_preamble {
	HAL_RX_PREAMBLE_11A,
	HAL_RX_PREAMBLE_11B,
	HAL_RX_PREAMBLE_11N,
	HAL_RX_PREAMBLE_11AC,
	HAL_RX_PREAMBLE_11AX,
	HAL_RX_PREAMBLE_MAX,
};

enum hal_rx_reception_type {
	HAL_RX_RECEPTION_TYPE_SU,
	HAL_RX_RECEPTION_TYPE_MU_MIMO,
	HAL_RX_RECEPTION_TYPE_MU_OFDMA,
	HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
	HAL_RX_RECEPTION_TYPE_MAX,
};

#define HAL_RX_FCS_LEN                          4

enum hal_rx_mon_status {
	HAL_RX_MON_STATUS_PPDU_NOT_DONE,
	HAL_RX_MON_STATUS_PPDU_DONE,
	HAL_RX_MON_STATUS_BUF_DONE,
};

struct hal_rx_user_status {
	u32 mcs:4,
	nss:3,
	ofdma_info_valid:1,
	dl_ofdma_ru_start_index:7,
	dl_ofdma_ru_width:7,
	dl_ofdma_ru_size:8;
	u32 ul_ofdma_user_v0_word0;
	u32 ul_ofdma_user_v0_word1;
	u32 ast_index;
	u32 tid;
	u16 tcp_msdu_count;
	u16 udp_msdu_count;
	u16 other_msdu_count;
	u16 frame_control;
	u8 frame_control_info_valid;
	u8 data_sequence_control_info_valid;
	u16 first_data_seq_ctrl;
	u32 preamble_type;
	u16 ht_flags;
	u16 vht_flags;
	u16 he_flags;
	u8 rs_flags;
	u32 mpdu_cnt_fcs_ok;
	u32 mpdu_cnt_fcs_err;
	u32 mpdu_fcs_ok_bitmap[8];
	u32 mpdu_ok_byte_count;
	u32 mpdu_err_byte_count;
};

#define HAL_TLV_STATUS_PPDU_NOT_DONE    HAL_RX_MON_STATUS_PPDU_NOT_DONE
#define HAL_TLV_STATUS_PPDU_DONE        HAL_RX_MON_STATUS_PPDU_DONE
#define HAL_TLV_STATUS_BUF_DONE         HAL_RX_MON_STATUS_BUF_DONE

struct hal_sw_mon_ring_entries {
	dma_addr_t mon_dst_paddr;
	dma_addr_t mon_status_paddr;
	u32 mon_dst_sw_cookie;
	u32 mon_status_sw_cookie;
	void *dst_buf_addr_info;
	void *status_buf_addr_info;
	u16 ppdu_id;
	u8 status_buf_count;
	u8 msdu_cnt;
	bool end_of_ppdu;
	bool drop_ppdu;
};

struct hal_rx_mon_ppdu_info {
	u32 ppdu_id;
	u32 ppdu_ts;
	u32 num_mpdu_fcs_ok;
	u32 num_mpdu_fcs_err;
	u32 preamble_type;
	u16 chan_num;
	u16 tcp_msdu_count;
	u16 tcp_ack_msdu_count;
	u16 udp_msdu_count;
	u16 other_msdu_count;
	u16 peer_id;
	u8 rate;
	u8 mcs;
	u8 nss;
	u8 bw;
	u8 vht_flag_values1;
	u8 vht_flag_values2;
	u8 vht_flag_values3[4];
	u8 vht_flag_values4;
	u8 vht_flag_values5;
	u16 vht_flag_values6;
	u8 is_stbc;
	u8 gi;
	u8 ldpc;
	u8 beamformed;
	u8 rssi_comb;
	u8 rssi_chain_pri20[HAL_RX_MAX_NSS];
	u16 tid;
	u16 ht_flags;
	u16 vht_flags;
	u16 he_flags;
	u16 he_mu_flags;
	u8 dcm;
	u8 ru_alloc;
	u8 reception_type;
	u64 tsft;
	u64 rx_duration;
	u16 frame_control;
	u32 ast_index;
	u8 rs_fcs_err;
	u8 rs_flags;
	u8 cck_flag;
	u8 ofdm_flag;
	u8 ulofdma_flag;
	u8 frame_control_info_valid;
	u16 he_per_user_1;
	u16 he_per_user_2;
	u8 he_per_user_position;
	u8 he_per_user_known;
	u16 he_flags1;
	u16 he_flags2;
	u8 he_RU[4];
	u16 he_data1;
	u16 he_data2;
	u16 he_data3;
	u16 he_data4;
	u16 he_data5;
	u16 he_data6;
	u32 ppdu_len;
	u32 prev_ppdu_id;
	u32 device_id;
	u16 first_data_seq_ctrl;
	u8 monitor_direct_used;
	u8 data_sequence_control_info_valid;
	u8 ltf_size;
	u8 rxpcu_filter_pass;
	char rssi_chain[8][8];
	struct hal_rx_user_status userstats;
};

#define HAL_RX_PPDU_START_INFO0_PPDU_ID		GENMASK(15, 0)

struct hal_rx_ppdu_start {
	__le32 info0;
	__le32 chan_num;
	__le32 ppdu_start_ts;
} __packed;

#define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR	GENMASK(25, 16)

#define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK	GENMASK(8, 0)
#define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID		BIT(9)
#define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID		BIT(10)
#define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID		BIT(11)
#define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE		GENMASK(23, 20)

#define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX		GENMASK(15, 0)
#define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL		GENMASK(31, 16)

#define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL		GENMASK(31, 16)

#define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT		GENMASK(15, 0)
#define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT		GENMASK(31, 16)

#define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT		GENMASK(15, 0)
#define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT	GENMASK(31, 16)

#define HAL_RX_PPDU_END_USER_STATS_INFO7_TID_BITMAP		GENMASK(15, 0)
#define HAL_RX_PPDU_END_USER_STATS_INFO7_TID_EOSP_BITMAP	GENMASK(31, 16)

#define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_OK_BYTE_COUNT	GENMASK(24, 0)
#define HAL_RX_PPDU_END_USER_STATS_INFO9_MPDU_ERR_BYTE_COUNT	GENMASK(24, 0)

struct hal_rx_ppdu_end_user_stats {
	__le32 rsvd0[2];
	__le32 info0;
	__le32 info1;
	__le32 info2;
	__le32 info3;
	__le32 ht_ctrl;
	__le32 rsvd1[2];
	__le32 info4;
	__le32 info5;
	__le32 info6;
	__le32 info7;
	__le32 rsvd2[4];
	__le32 info8;
	__le32 rsvd3;
	__le32 info9;
	__le32 rsvd4[2];
	__le32 info10;
} __packed;

struct hal_rx_ppdu_end_user_stats_ext {
	u32 info0;
	u32 info1;
	u32 info2;
	u32 info3;
	u32 info4;
	u32 info5;
	u32 info6;
} __packed;

#define HAL_RX_HT_SIG_INFO_INFO0_MCS		GENMASK(6, 0)
#define HAL_RX_HT_SIG_INFO_INFO0_BW		BIT(7)

#define HAL_RX_HT_SIG_INFO_INFO1_STBC		GENMASK(5, 4)
#define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING	BIT(6)
#define HAL_RX_HT_SIG_INFO_INFO1_GI		BIT(7)

struct hal_rx_ht_sig_info {
	__le32 info0;
	__le32 info1;
} __packed;

#define HAL_RX_LSIG_B_INFO_INFO0_RATE	GENMASK(3, 0)
#define HAL_RX_LSIG_B_INFO_INFO0_LEN	GENMASK(15, 4)

struct hal_rx_lsig_b_info {
	__le32 info0;
} __packed;

#define HAL_RX_LSIG_A_INFO_INFO0_RATE		GENMASK(3, 0)
#define HAL_RX_LSIG_A_INFO_INFO0_LEN		GENMASK(16, 5)
#define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE	GENMASK(27, 24)

struct hal_rx_lsig_a_info {
	__le32 info0;
} __packed;

#define HAL_RX_VHT_SIG_A_INFO_INFO0_BW		GENMASK(1, 0)
#define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC	BIT(3)
#define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID	GENMASK(9, 4)
#define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS	GENMASK(21, 10)

#define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING		GENMASK(1, 0)
#define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING	BIT(2)
#define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS			GENMASK(7, 4)
#define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED		BIT(8)

struct hal_rx_vht_sig_a_info {
	__le32 info0;
	__le32 info1;
} __packed;

enum hal_rx_vht_sig_a_gi_setting {
	HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
	HAL_RX_VHT_SIG_A_SHORT_GI = 1,
	HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
};

#define HAL_RX_SU_MU_CODING_LDPC 0x01

#define HE_GI_0_8 0
#define HE_GI_0_4 1
#define HE_GI_1_6 2
#define HE_GI_3_2 3

#define HE_LTF_1_X 0
#define HE_LTF_2_X 1
#define HE_LTF_4_X 2
#define HE_LTF_UNKNOWN 3

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS	GENMASK(6, 3)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM		BIT(7)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW	GENMASK(20, 19)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE	GENMASK(22, 21)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS		GENMASK(25, 23)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR		GENMASK(13, 8)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE	GENMASK(18, 15)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND	BIT(0)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE	BIT(1)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG	BIT(2)

#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION	GENMASK(6, 0)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING		BIT(7)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA	BIT(8)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC		BIT(9)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF		BIT(10)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR	GENMASK(12, 11)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM	BIT(13)
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND	BIT(15)

struct hal_rx_he_sig_a_su_info {
	__le32 info0;
	__le32 info1;
} __packed;

#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_UL_FLAG		BIT(1)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB		GENMASK(3, 1)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DCM_OF_SIGB		BIT(4)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR		GENMASK(10, 5)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE	GENMASK(14, 11)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW		GENMASK(17, 15)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB	GENMASK(21, 18)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_COMP_MODE_SIGB	BIT(22)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE		GENMASK(24, 23)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DOPPLER_INDICATION	BIT(25)

#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXOP_DURATION	GENMASK(6, 0)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_CODING		BIT(7)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_NUM_LTF_SYMB	GENMASK(10, 8)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_LDPC_EXTRA		BIT(11)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC		BIT(12)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXBF		BIT(10)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_FACTOR	GENMASK(14, 13)
#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_PE_DISAM	BIT(15)

struct hal_rx_he_sig_a_mu_dl_info {
	__le32 info0;
	__le32 info1;
} __packed;

#define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION	GENMASK(7, 0)

struct hal_rx_he_sig_b1_mu_info {
	__le32 info0;
} __packed;

#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID		GENMASK(10, 0)
#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS		GENMASK(18, 15)
#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING	BIT(20)
#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS		GENMASK(31, 29)

struct hal_rx_he_sig_b2_mu_info {
	__le32 info0;
} __packed;

#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID	GENMASK(10, 0)
#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS	GENMASK(13, 11)
#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF	BIT(19)
#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS	GENMASK(18, 15)
#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM	BIT(19)
#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING	BIT(20)

struct hal_rx_he_sig_b2_ofdma_info {
	__le32 info0;
} __packed;

#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB	GENMASK(15, 8)

#define HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20	GENMASK(7, 0)

struct hal_rx_phyrx_chain_rssi {
	__le32 rssi_2040;
	__le32 rssi_80;
} __packed;

struct hal_rx_phyrx_rssi_legacy_info {
	__le32 rsvd[3];
	struct hal_rx_phyrx_chain_rssi pre_rssi[HAL_RX_MAX_NSS];
	struct hal_rx_phyrx_chain_rssi preamble[HAL_RX_MAX_NSS];
	__le32 info0;
} __packed;

#define HAL_RX_MPDU_INFO_INFO0_PEERID	GENMASK(31, 16)
#define HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855	GENMASK(15, 0)
#define HAL_RX_MPDU_INFO_INFO1_MPDU_LEN		GENMASK(13, 0)

struct hal_rx_mpdu_info_ipq8074 {
	__le32 rsvd0;
	__le32 info0;
	__le32 rsvd1[11];
	__le32 info1;
	__le32 rsvd2[9];
} __packed;

struct hal_rx_mpdu_info_qcn9074 {
	__le32 rsvd0[10];
	__le32 info0;
	__le32 rsvd1[2];
	__le32 info1;
	__le32 rsvd2[9];
} __packed;

struct hal_rx_mpdu_info_wcn6855 {
	__le32 rsvd0[8];
	__le32 info0;
	__le32 rsvd1[14];
} __packed;

struct hal_rx_mpdu_info {
	union {
		struct hal_rx_mpdu_info_ipq8074 ipq8074;
		struct hal_rx_mpdu_info_qcn9074 qcn9074;
		struct hal_rx_mpdu_info_wcn6855 wcn6855;
	} u;
} __packed;

#define HAL_RX_PPDU_END_DURATION	GENMASK(23, 0)
struct hal_rx_ppdu_end_duration {
	__le32 rsvd0[9];
	__le32 info0;
	__le32 rsvd1[4];
} __packed;

struct hal_rx_rxpcu_classification_overview {
	u32 rsvd0;
} __packed;

struct hal_rx_msdu_desc_info {
	u32 msdu_flags;
	u16 msdu_len; /* 14 bits for length */
};

#define HAL_RX_NUM_MSDU_DESC 6
struct hal_rx_msdu_list {
	struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
	u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
	u8 rbm[HAL_RX_NUM_MSDU_DESC];
};

void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc,
				       struct hal_reo_status *status);
void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc,
				       struct hal_reo_status *status);
void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
				       struct hal_reo_status *status);
void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
				       struct hal_reo_status *status);
void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc,
				       struct hal_reo_status *status);
void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab,
					      u32 *reo_desc,
					      struct hal_reo_status *status);
void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab,
					       u32 *reo_desc,
					       struct hal_reo_status *status);
void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab,
					       u32 *reo_desc,
					       struct hal_reo_status *status);
int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status);
void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus,
				      u32 *msdu_cookies,
				      enum hal_rx_buf_return_buf_manager *rbm);
void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc,
				      void *link_desc,
				      enum hal_wbm_rel_bm_act action);
void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr,
				     u32 cookie, u8 manager);
void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr,
				     u32 *cookie, u8 *rbm);
int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc,
				  dma_addr_t *paddr, u32 *desc_bank);
int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc,
				  struct hal_rx_wbm_rel_info *rel_info);
void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc,
				     dma_addr_t *paddr, u32 *desc_bank);
void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
					 dma_addr_t *paddr, u32 *sw_cookie,
					 void **pp_buf_addr_info, u8 *rbm,
					 u32 *msdu_cnt);
void
ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc,
					struct hal_sw_mon_ring_entries *sw_mon_ent);
enum hal_rx_mon_status
ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab,
			       struct hal_rx_mon_ppdu_info *ppdu_info,
			       struct sk_buff *skb);

#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
#endif
Commit	Line	Data
d5c65159 KV	1	/* SPDX-License-Identifier: BSD-3-Clause-Clear */
	2	/*
	3	* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
	4	*/
	5
	6	#ifndef ATH11K_HAL_RX_H
	7	#define ATH11K_HAL_RX_H
	8
d5c65159 KV	9	struct hal_rx_wbm_rel_info {
	10	u32 cookie;
	11	enum hal_wbm_rel_src_module err_rel_src;
	12	enum hal_reo_dest_ring_push_reason push_reason;
	13	u32 err_code;
	14	bool first_msdu;
	15	bool last_msdu;
	16	};
	17
	18	#define HAL_INVALID_PEERID 0xffff
	19	#define VHT_SIG_SU_NSS_MASK 0x7
	20
	21	#define HAL_RX_MAX_MCS 12
	22	#define HAL_RX_MAX_NSS 8
	23
	24	struct hal_rx_mon_status_tlv_hdr {
	25	u32 hdr;
14dd3a71	26	u8 value[];
d5c65159 KV	27	};
	28
	29	enum hal_rx_su_mu_coding {
	30	HAL_RX_SU_MU_CODING_BCC,
	31	HAL_RX_SU_MU_CODING_LDPC,
	32	HAL_RX_SU_MU_CODING_MAX,
	33	};
	34
	35	enum hal_rx_gi {
	36	HAL_RX_GI_0_8_US,
	37	HAL_RX_GI_0_4_US,
	38	HAL_RX_GI_1_6_US,
	39	HAL_RX_GI_3_2_US,
	40	HAL_RX_GI_MAX,
	41	};
	42
	43	enum hal_rx_bw {
	44	HAL_RX_BW_20MHZ,
	45	HAL_RX_BW_40MHZ,
	46	HAL_RX_BW_80MHZ,
	47	HAL_RX_BW_160MHZ,
	48	HAL_RX_BW_MAX,
	49	};
	50
	51	enum hal_rx_preamble {
	52	HAL_RX_PREAMBLE_11A,
	53	HAL_RX_PREAMBLE_11B,
	54	HAL_RX_PREAMBLE_11N,
	55	HAL_RX_PREAMBLE_11AC,
	56	HAL_RX_PREAMBLE_11AX,
	57	HAL_RX_PREAMBLE_MAX,
	58	};
	59
	60	enum hal_rx_reception_type {
	61	HAL_RX_RECEPTION_TYPE_SU,
	62	HAL_RX_RECEPTION_TYPE_MU_MIMO,
	63	HAL_RX_RECEPTION_TYPE_MU_OFDMA,
	64	HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
	65	HAL_RX_RECEPTION_TYPE_MAX,
	66	};
	67
d5c65159 KV	68	#define HAL_RX_FCS_LEN 4
	69
	70	enum hal_rx_mon_status {
	71	HAL_RX_MON_STATUS_PPDU_NOT_DONE,
	72	HAL_RX_MON_STATUS_PPDU_DONE,
	73	HAL_RX_MON_STATUS_BUF_DONE,
	74	};
	75
01d2f285 PKC	76	struct hal_rx_user_status {
	77	u32 mcs:4,
	78	nss:3,
	79	ofdma_info_valid:1,
	80	dl_ofdma_ru_start_index:7,
	81	dl_ofdma_ru_width:7,
	82	dl_ofdma_ru_size:8;
	83	u32 ul_ofdma_user_v0_word0;
	84	u32 ul_ofdma_user_v0_word1;
	85	u32 ast_index;
	86	u32 tid;
	87	u16 tcp_msdu_count;
	88	u16 udp_msdu_count;
	89	u16 other_msdu_count;
	90	u16 frame_control;
	91	u8 frame_control_info_valid;
	92	u8 data_sequence_control_info_valid;
	93	u16 first_data_seq_ctrl;
	94	u32 preamble_type;
	95	u16 ht_flags;
	96	u16 vht_flags;
	97	u16 he_flags;
	98	u8 rs_flags;
	99	u32 mpdu_cnt_fcs_ok;
	100	u32 mpdu_cnt_fcs_err;
	101	u32 mpdu_fcs_ok_bitmap[8];
	102	u32 mpdu_ok_byte_count;
	103	u32 mpdu_err_byte_count;
	104	};
	105
67a9d399 MH	106	#define HAL_TLV_STATUS_PPDU_NOT_DONE HAL_RX_MON_STATUS_PPDU_NOT_DONE
	107	#define HAL_TLV_STATUS_PPDU_DONE HAL_RX_MON_STATUS_PPDU_DONE
	108	#define HAL_TLV_STATUS_BUF_DONE HAL_RX_MON_STATUS_BUF_DONE
	109
88ee00d1 AK	110	struct hal_sw_mon_ring_entries {
	111	dma_addr_t mon_dst_paddr;
	112	dma_addr_t mon_status_paddr;
	113	u32 mon_dst_sw_cookie;
	114	u32 mon_status_sw_cookie;
	115	void *dst_buf_addr_info;
	116	void *status_buf_addr_info;
	117	u16 ppdu_id;
	118	u8 status_buf_count;
	119	u8 msdu_cnt;
	120	bool end_of_ppdu;
	121	bool drop_ppdu;
	122	};
	123
d5c65159 KV	124	struct hal_rx_mon_ppdu_info {
	125	u32 ppdu_id;
	126	u32 ppdu_ts;
	127	u32 num_mpdu_fcs_ok;
	128	u32 num_mpdu_fcs_err;
	129	u32 preamble_type;
	130	u16 chan_num;
	131	u16 tcp_msdu_count;
	132	u16 tcp_ack_msdu_count;
	133	u16 udp_msdu_count;
	134	u16 other_msdu_count;
	135	u16 peer_id;
	136	u8 rate;
	137	u8 mcs;
	138	u8 nss;
	139	u8 bw;
01d2f285 PKC	140	u8 vht_flag_values1;
	141	u8 vht_flag_values2;
	142	u8 vht_flag_values3[4];
	143	u8 vht_flag_values4;
	144	u8 vht_flag_values5;
	145	u16 vht_flag_values6;
d5c65159 KV	146	u8 is_stbc;
	147	u8 gi;
	148	u8 ldpc;
	149	u8 beamformed;
	150	u8 rssi_comb;
b488c766	151	u8 rssi_chain_pri20[HAL_RX_MAX_NSS];
7791487c	152	u16 tid;
01d2f285 PKC	153	u16 ht_flags;
	154	u16 vht_flags;
	155	u16 he_flags;
	156	u16 he_mu_flags;
6a0c3702 JC	157	u8 dcm;
6a0c3702 JC	158	u8 ru_alloc;
d5c65159	159	u8 reception_type;
01d2f285	160	u64 tsft;
d5c65159	161	u64 rx_duration;
01d2f285 PKC	162	u16 frame_control;
	163	u32 ast_index;
	164	u8 rs_fcs_err;
	165	u8 rs_flags;
	166	u8 cck_flag;
	167	u8 ofdm_flag;
	168	u8 ulofdma_flag;
	169	u8 frame_control_info_valid;
	170	u16 he_per_user_1;
	171	u16 he_per_user_2;
	172	u8 he_per_user_position;
	173	u8 he_per_user_known;
	174	u16 he_flags1;
	175	u16 he_flags2;
	176	u8 he_RU[4];
	177	u16 he_data1;
	178	u16 he_data2;
	179	u16 he_data3;
	180	u16 he_data4;
	181	u16 he_data5;
	182	u16 he_data6;
	183	u32 ppdu_len;
	184	u32 prev_ppdu_id;
	185	u32 device_id;
	186	u16 first_data_seq_ctrl;
	187	u8 monitor_direct_used;
	188	u8 data_sequence_control_info_valid;
	189	u8 ltf_size;
	190	u8 rxpcu_filter_pass;
	191	char rssi_chain[8][8];
	192	struct hal_rx_user_status userstats;
d5c65159 KV	193	};
	194
	195	#define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)
	196
	197	struct hal_rx_ppdu_start {
	198	__le32 info0;
	199	__le32 chan_num;
	200	__le32 ppdu_start_ts;
	201	} __packed;
	202
	203	#define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(25, 16)
	204
	205	#define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(8, 0)
	206	#define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(9)
	207	#define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(10)
	208	#define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(11)
	209	#define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(23, 20)
	210
	211	#define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0)
	212	#define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16)
	213
	214	#define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16)
	215
	216	#define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0)
	217	#define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16)
	218
	219	#define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0)
	220	#define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16)
	221
7791487c MS	222	#define HAL_RX_PPDU_END_USER_STATS_INFO7_TID_BITMAP GENMASK(15, 0)
7791487c MS	223	#define HAL_RX_PPDU_END_USER_STATS_INFO7_TID_EOSP_BITMAP GENMASK(31, 16)
d5c65159	224
7791487c MS	225	#define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_OK_BYTE_COUNT GENMASK(24, 0)
7791487c MS	226	#define HAL_RX_PPDU_END_USER_STATS_INFO9_MPDU_ERR_BYTE_COUNT GENMASK(24, 0)
01d2f285	227
d5c65159 KV	228	struct hal_rx_ppdu_end_user_stats {
	229	__le32 rsvd0[2];
	230	__le32 info0;
	231	__le32 info1;
	232	__le32 info2;
	233	__le32 info3;
	234	__le32 ht_ctrl;
	235	__le32 rsvd1[2];
	236	__le32 info4;
	237	__le32 info5;
	238	__le32 info6;
5bd2ced0	239	__le32 info7;
7791487c	240	__le32 rsvd2[4];
5bd2ced0	241	__le32 info8;
7791487c	242	__le32 rsvd3;
5bd2ced0	243	__le32 info9;
7791487c MS	244	__le32 rsvd4[2];
7791487c MS	245	__le32 info10;
d5c65159 KV	246	} __packed;
d5c65159 KV	247
01d2f285 PKC	248	struct hal_rx_ppdu_end_user_stats_ext {
	249	u32 info0;
	250	u32 info1;
	251	u32 info2;
	252	u32 info3;
	253	u32 info4;
	254	u32 info5;
	255	u32 info6;
	256	} __packed;
	257
d5c65159 KV	258	#define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)
	259	#define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7)
	260
	261	#define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4)
	262	#define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6)
	263	#define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7)
	264
	265	struct hal_rx_ht_sig_info {
	266	__le32 info0;
	267	__le32 info1;
	268	} __packed;
	269
	270	#define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0)
	271	#define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4)
	272
	273	struct hal_rx_lsig_b_info {
	274	__le32 info0;
	275	} __packed;
	276
	277	#define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0)
	278	#define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5)
	279	#define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24)
	280
	281	struct hal_rx_lsig_a_info {
	282	__le32 info0;
	283	} __packed;
	284
	285	#define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0)
	286	#define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3)
	287	#define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4)
	288	#define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10)
	289
	290	#define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0)
	291	#define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2)
	292	#define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4)
	293	#define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8)
	294
	295	struct hal_rx_vht_sig_a_info {
	296	__le32 info0;
	297	__le32 info1;
	298	} __packed;
	299
28dee8ef MP	300	enum hal_rx_vht_sig_a_gi_setting {
	301	HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
	302	HAL_RX_VHT_SIG_A_SHORT_GI = 1,
	303	HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
	304	};
	305
01d2f285 PKC	306	#define HAL_RX_SU_MU_CODING_LDPC 0x01
	307
	308	#define HE_GI_0_8 0
	309	#define HE_GI_0_4 1
	310	#define HE_GI_1_6 2
	311	#define HE_GI_3_2 3
	312
	313	#define HE_LTF_1_X 0
	314	#define HE_LTF_2_X 1
	315	#define HE_LTF_4_X 2
	316	#define HE_LTF_UNKNOWN 3
	317
d5c65159 KV	318	#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3)
	319	#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7)
	320	#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19)
	321	#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21)
	322	#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23)
01d2f285 PKC	323	#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8)
	324	#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15)
	325	#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0)
	326	#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1)
	327	#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2)
d5c65159	328
01d2f285	329	#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)
d5c65159	330	#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7)
01d2f285	331	#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA BIT(8)
d5c65159 KV	332	#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9)
d5c65159 KV	333	#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10)
01d2f285 PKC	334	#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11)
	335	#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13)
	336	#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15)
d5c65159 KV	337
	338	struct hal_rx_he_sig_a_su_info {
	339	__le32 info0;
	340	__le32 info1;
	341	} __packed;
	342
01d2f285 PKC	343	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_UL_FLAG BIT(1)
	344	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB GENMASK(3, 1)
	345	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DCM_OF_SIGB BIT(4)
	346	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR GENMASK(10, 5)
	347	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE GENMASK(14, 11)
	348	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW GENMASK(17, 15)
	349	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB GENMASK(21, 18)
	350	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_COMP_MODE_SIGB BIT(22)
	351	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE GENMASK(24, 23)
	352	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DOPPLER_INDICATION BIT(25)
	353
	354	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)
	355	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_CODING BIT(7)
	356	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_NUM_LTF_SYMB GENMASK(10, 8)
	357	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_LDPC_EXTRA BIT(11)
d5c65159	358	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC BIT(12)
01d2f285 PKC	359	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXBF BIT(10)
	360	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_FACTOR GENMASK(14, 13)
	361	#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_PE_DISAM BIT(15)
d5c65159 KV	362
	363	struct hal_rx_he_sig_a_mu_dl_info {
	364	__le32 info0;
	365	__le32 info1;
	366	} __packed;
	367
	368	#define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0)
	369
	370	struct hal_rx_he_sig_b1_mu_info {
	371	__le32 info0;
	372	} __packed;
	373
01d2f285	374	#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0)
d5c65159 KV	375	#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15)
	376	#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20)
	377	#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29)
	378
	379	struct hal_rx_he_sig_b2_mu_info {
	380	__le32 info0;
	381	} __packed;
	382
01d2f285	383	#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0)
d5c65159 KV	384	#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11)
	385	#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(19)
	386	#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15)
	387	#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19)
	388	#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20)
	389
	390	struct hal_rx_he_sig_b2_ofdma_info {
	391	__le32 info0;
	392	} __packed;
	393
2f0c9ac8	394	#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB GENMASK(15, 8)
d5c65159	395
b488c766 WG	396	#define HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20 GENMASK(7, 0)
	397
	398	struct hal_rx_phyrx_chain_rssi {
	399	__le32 rssi_2040;
	400	__le32 rssi_80;
	401	} __packed;
	402
d5c65159	403	struct hal_rx_phyrx_rssi_legacy_info {
b488c766 WG	404	__le32 rsvd[3];
	405	struct hal_rx_phyrx_chain_rssi pre_rssi[HAL_RX_MAX_NSS];
	406	struct hal_rx_phyrx_chain_rssi preamble[HAL_RX_MAX_NSS];
d5c65159 KV	407	__le32 info0;
	408	} __packed;
	409
	410	#define HAL_RX_MPDU_INFO_INFO0_PEERID GENMASK(31, 16)
8845fed1	411	#define HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855 GENMASK(15, 0)
01d2f285	412	#define HAL_RX_MPDU_INFO_INFO1_MPDU_LEN GENMASK(13, 0)
8845fed1	413
031ffa6c	414	struct hal_rx_mpdu_info_ipq8074 {
d5c65159 KV	415	__le32 rsvd0;
d5c65159 KV	416	__le32 info0;
01d2f285 PKC	417	__le32 rsvd1[11];
	418	__le32 info1;
	419	__le32 rsvd2[9];
d5c65159 KV	420	} __packed;
d5c65159 KV	421
031ffa6c P	422	struct hal_rx_mpdu_info_qcn9074 {
	423	__le32 rsvd0[10];
	424	__le32 info0;
	425	__le32 rsvd1[2];
	426	__le32 info1;
	427	__le32 rsvd2[9];
	428	} __packed;
	429
8845fed1 BQ	430	struct hal_rx_mpdu_info_wcn6855 {
	431	__le32 rsvd0[8];
	432	__le32 info0;
	433	__le32 rsvd1[14];
	434	} __packed;
	435
031ffa6c P	436	struct hal_rx_mpdu_info {
	437	union {
	438	struct hal_rx_mpdu_info_ipq8074 ipq8074;
	439	struct hal_rx_mpdu_info_qcn9074 qcn9074;
	440	struct hal_rx_mpdu_info_wcn6855 wcn6855;
	441	} u;
	442	} __packed;
	443
d5c65159 KV	444	#define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)
	445	struct hal_rx_ppdu_end_duration {
	446	__le32 rsvd0[9];
	447	__le32 info0;
	448	__le32 rsvd1[4];
	449	} __packed;
	450
	451	struct hal_rx_rxpcu_classification_overview {
	452	u32 rsvd0;
	453	} __packed;
	454
	455	struct hal_rx_msdu_desc_info {
	456	u32 msdu_flags;
	457	u16 msdu_len; /* 14 bits for length */
	458	};
	459
	460	#define HAL_RX_NUM_MSDU_DESC 6
	461	struct hal_rx_msdu_list {
	462	struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
	463	u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
	464	u8 rbm[HAL_RX_NUM_MSDU_DESC];
	465	};
	466
	467	void ath11k_hal_reo_status_queue_stats(struct ath11k_base ab, u32 reo_desc,
	468	struct hal_reo_status *status);
	469	void ath11k_hal_reo_flush_queue_status(struct ath11k_base ab, u32 reo_desc,
	470	struct hal_reo_status *status);
	471	void ath11k_hal_reo_flush_cache_status(struct ath11k_base ab, u32 reo_desc,
	472	struct hal_reo_status *status);
	473	void ath11k_hal_reo_flush_cache_status(struct ath11k_base ab, u32 reo_desc,
	474	struct hal_reo_status *status);
	475	void ath11k_hal_reo_unblk_cache_status(struct ath11k_base ab, u32 reo_desc,
	476	struct hal_reo_status *status);
	477	void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab,
	478	u32 *reo_desc,
	479	struct hal_reo_status *status);
	480	void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab,
	481	u32 *reo_desc,
	482	struct hal_reo_status *status);
	483	void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab,
	484	u32 *reo_desc,
	485	struct hal_reo_status *status);
	486	int ath11k_hal_reo_process_status(u8 reo_desc, u8 status);
	487	void ath11k_hal_rx_msdu_link_info_get(void link_desc, u32 num_msdus,
293cb583	488	u32 *msdu_cookies,
d5c65159 KV	489	enum hal_rx_buf_return_buf_manager *rbm);
	490	void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base ab, void desc,
	491	void *link_desc,
	492	enum hal_wbm_rel_bm_act action);
	493	void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr,
	494	u32 cookie, u8 manager);
	495	void ath11k_hal_rx_buf_addr_info_get(void desc, dma_addr_t paddr,
	496	u32 cookie, u8 rbm);
	497	int ath11k_hal_desc_reo_parse_err(struct ath11k_base ab, u32 rx_desc,
	498	dma_addr_t paddr, u32 desc_bank);
d5c65159 KV	499	int ath11k_hal_wbm_desc_parse_err(struct ath11k_base ab, void desc,
	500	struct hal_rx_wbm_rel_info *rel_info);
	501	void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base ab, void desc,
	502	dma_addr_t paddr, u32 desc_bank);
	503	void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
	504	dma_addr_t paddr, u32 sw_cookie,
701e48a4	505	void *pp_buf_addr_info, u8 rbm,
d5c65159	506	u32 *msdu_cnt);
88ee00d1 AK	507	void
	508	ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc,
	509	struct hal_sw_mon_ring_entries *sw_mon_ent);
d5c65159 KV	510	enum hal_rx_mon_status
	511	ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab,
	512	struct hal_rx_mon_ppdu_info *ppdu_info,
	513	struct sk_buff *skb);
6a0c3702	514
d5c65159 KV	515	#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
	516	#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
	517	#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
	518	#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
	519	#endif