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5e3dd157 KV |
1 | /* |
2 | * Copyright (c) 2005-2011 Atheros Communications Inc. | |
3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. | |
4 | * | |
5 | * Permission to use, copy, modify, and/or distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | */ | |
17 | ||
18 | #ifndef _HW_H_ | |
19 | #define _HW_H_ | |
20 | ||
21 | #include "targaddrs.h" | |
22 | ||
e01ae68c KV |
23 | /* QCA988X 1.0 definitions (unsupported) */ |
24 | #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 | |
25 | ||
5e3dd157 KV |
26 | /* QCA988X 2.0 definitions */ |
27 | #define QCA988X_HW_2_0_VERSION 0x4100016c | |
e01ae68c | 28 | #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 |
5e3dd157 KV |
29 | #define QCA988X_HW_2_0_FW_DIR "ath10k/QCA988X/hw2.0" |
30 | #define QCA988X_HW_2_0_FW_FILE "firmware.bin" | |
31 | #define QCA988X_HW_2_0_OTP_FILE "otp.bin" | |
32 | #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" | |
33 | #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 | |
34 | ||
1a222435 KV |
35 | #define ATH10K_FW_API2_FILE "firmware-2.bin" |
36 | ||
37 | /* includes also the null byte */ | |
38 | #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" | |
39 | ||
40 | struct ath10k_fw_ie { | |
41 | __le32 id; | |
42 | __le32 len; | |
43 | u8 data[0]; | |
44 | }; | |
45 | ||
46 | enum ath10k_fw_ie_type { | |
47 | ATH10K_FW_IE_FW_VERSION = 0, | |
48 | ATH10K_FW_IE_TIMESTAMP = 1, | |
49 | ATH10K_FW_IE_FEATURES = 2, | |
50 | ATH10K_FW_IE_FW_IMAGE = 3, | |
51 | ATH10K_FW_IE_OTP_IMAGE = 4, | |
52 | }; | |
53 | ||
5e3dd157 KV |
54 | /* Known pecularities: |
55 | * - current FW doesn't support raw rx mode (last tested v599) | |
56 | * - current FW dumps upon raw tx mode (last tested v599) | |
57 | * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap | |
58 | * - raw have FCS, nwifi doesn't | |
59 | * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher | |
60 | * param, llc/snap) are aligned to 4byte boundaries each */ | |
61 | enum ath10k_hw_txrx_mode { | |
62 | ATH10K_HW_TXRX_RAW = 0, | |
63 | ATH10K_HW_TXRX_NATIVE_WIFI = 1, | |
64 | ATH10K_HW_TXRX_ETHERNET = 2, | |
961d4c38 MK |
65 | |
66 | /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ | |
67 | ATH10K_HW_TXRX_MGMT = 3, | |
5e3dd157 KV |
68 | }; |
69 | ||
70 | enum ath10k_mcast2ucast_mode { | |
71 | ATH10K_MCAST2UCAST_DISABLED = 0, | |
72 | ATH10K_MCAST2UCAST_ENABLED = 1, | |
73 | }; | |
74 | ||
ec6a73f0 | 75 | /* Target specific defines for MAIN firmware */ |
5e3dd157 KV |
76 | #define TARGET_NUM_VDEVS 8 |
77 | #define TARGET_NUM_PEER_AST 2 | |
78 | #define TARGET_NUM_WDS_ENTRIES 32 | |
79 | #define TARGET_DMA_BURST_SIZE 0 | |
80 | #define TARGET_MAC_AGGR_DELIM 0 | |
81 | #define TARGET_AST_SKID_LIMIT 16 | |
82 | #define TARGET_NUM_PEERS 16 | |
83 | #define TARGET_NUM_OFFLOAD_PEERS 0 | |
84 | #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 | |
85 | #define TARGET_NUM_PEER_KEYS 2 | |
86 | #define TARGET_NUM_TIDS (2 * ((TARGET_NUM_PEERS) + (TARGET_NUM_VDEVS))) | |
87 | #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) | |
88 | #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) | |
89 | #define TARGET_RX_TIMEOUT_LO_PRI 100 | |
90 | #define TARGET_RX_TIMEOUT_HI_PRI 40 | |
4d316c79 MK |
91 | |
92 | /* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and | |
93 | * avoid a very expensive re-alignment in mac80211. */ | |
94 | #define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI | |
95 | ||
5e3dd157 KV |
96 | #define TARGET_SCAN_MAX_PENDING_REQS 4 |
97 | #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 | |
98 | #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 | |
99 | #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 | |
100 | #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 | |
101 | #define TARGET_NUM_MCAST_GROUPS 0 | |
102 | #define TARGET_NUM_MCAST_TABLE_ELEMS 0 | |
103 | #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED | |
104 | #define TARGET_TX_DBG_LOG_SIZE 1024 | |
105 | #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 | |
106 | #define TARGET_VOW_CONFIG 0 | |
107 | #define TARGET_NUM_MSDU_DESC (1024 + 400) | |
108 | #define TARGET_MAX_FRAG_ENTRIES 0 | |
109 | ||
ec6a73f0 BM |
110 | /* Target specific defines for 10.X firmware */ |
111 | #define TARGET_10X_NUM_VDEVS 16 | |
112 | #define TARGET_10X_NUM_PEER_AST 2 | |
113 | #define TARGET_10X_NUM_WDS_ENTRIES 32 | |
114 | #define TARGET_10X_DMA_BURST_SIZE 0 | |
115 | #define TARGET_10X_MAC_AGGR_DELIM 0 | |
116 | #define TARGET_10X_AST_SKID_LIMIT 16 | |
117 | #define TARGET_10X_NUM_PEERS (128 + (TARGET_10X_NUM_VDEVS)) | |
0e759f36 | 118 | #define TARGET_10X_NUM_PEERS_MAX 128 |
ec6a73f0 BM |
119 | #define TARGET_10X_NUM_OFFLOAD_PEERS 0 |
120 | #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 | |
121 | #define TARGET_10X_NUM_PEER_KEYS 2 | |
122 | #define TARGET_10X_NUM_TIDS 256 | |
123 | #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) | |
124 | #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) | |
125 | #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 | |
126 | #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 | |
0d1a28f2 | 127 | #define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI |
ec6a73f0 BM |
128 | #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 |
129 | #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 | |
130 | #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 | |
131 | #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 | |
132 | #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 | |
133 | #define TARGET_10X_NUM_MCAST_GROUPS 0 | |
134 | #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 | |
135 | #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED | |
136 | #define TARGET_10X_TX_DBG_LOG_SIZE 1024 | |
137 | #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 | |
138 | #define TARGET_10X_VOW_CONFIG 0 | |
139 | #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) | |
140 | #define TARGET_10X_MAX_FRAG_ENTRIES 0 | |
5e3dd157 KV |
141 | |
142 | /* Number of Copy Engines supported */ | |
143 | #define CE_COUNT 8 | |
144 | ||
145 | /* | |
146 | * Total number of PCIe MSI interrupts requested for all interrupt sources. | |
147 | * PCIe standard forces this to be a power of 2. | |
148 | * Some Host OS's limit MSI requests that can be granted to 8 | |
149 | * so for now we abide by this limit and avoid requesting more | |
150 | * than that. | |
151 | */ | |
152 | #define MSI_NUM_REQUEST_LOG2 3 | |
153 | #define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2) | |
154 | ||
155 | /* | |
156 | * Granted MSIs are assigned as follows: | |
157 | * Firmware uses the first | |
158 | * Remaining MSIs, if any, are used by Copy Engines | |
159 | * This mapping is known to both Target firmware and Host software. | |
160 | * It may be changed as long as Host and Target are kept in sync. | |
161 | */ | |
162 | /* MSI for firmware (errors, etc.) */ | |
163 | #define MSI_ASSIGN_FW 0 | |
164 | ||
165 | /* MSIs for Copy Engines */ | |
166 | #define MSI_ASSIGN_CE_INITIAL 1 | |
167 | #define MSI_ASSIGN_CE_MAX 7 | |
168 | ||
169 | /* as of IP3.7.1 */ | |
170 | #define RTC_STATE_V_ON 3 | |
171 | ||
172 | #define RTC_STATE_COLD_RESET_MASK 0x00000400 | |
173 | #define RTC_STATE_V_LSB 0 | |
174 | #define RTC_STATE_V_MASK 0x00000007 | |
175 | #define RTC_STATE_ADDRESS 0x0000 | |
176 | #define PCIE_SOC_WAKE_V_MASK 0x00000001 | |
177 | #define PCIE_SOC_WAKE_ADDRESS 0x0004 | |
178 | #define PCIE_SOC_WAKE_RESET 0x00000000 | |
179 | #define SOC_GLOBAL_RESET_ADDRESS 0x0008 | |
180 | ||
181 | #define RTC_SOC_BASE_ADDRESS 0x00004000 | |
182 | #define RTC_WMAC_BASE_ADDRESS 0x00005000 | |
183 | #define MAC_COEX_BASE_ADDRESS 0x00006000 | |
184 | #define BT_COEX_BASE_ADDRESS 0x00007000 | |
185 | #define SOC_PCIE_BASE_ADDRESS 0x00008000 | |
186 | #define SOC_CORE_BASE_ADDRESS 0x00009000 | |
187 | #define WLAN_UART_BASE_ADDRESS 0x0000c000 | |
188 | #define WLAN_SI_BASE_ADDRESS 0x00010000 | |
189 | #define WLAN_GPIO_BASE_ADDRESS 0x00014000 | |
190 | #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 | |
191 | #define WLAN_MAC_BASE_ADDRESS 0x00020000 | |
192 | #define EFUSE_BASE_ADDRESS 0x00030000 | |
193 | #define FPGA_REG_BASE_ADDRESS 0x00039000 | |
194 | #define WLAN_UART2_BASE_ADDRESS 0x00054c00 | |
195 | #define CE_WRAPPER_BASE_ADDRESS 0x00057000 | |
196 | #define CE0_BASE_ADDRESS 0x00057400 | |
197 | #define CE1_BASE_ADDRESS 0x00057800 | |
198 | #define CE2_BASE_ADDRESS 0x00057c00 | |
199 | #define CE3_BASE_ADDRESS 0x00058000 | |
200 | #define CE4_BASE_ADDRESS 0x00058400 | |
201 | #define CE5_BASE_ADDRESS 0x00058800 | |
202 | #define CE6_BASE_ADDRESS 0x00058c00 | |
203 | #define CE7_BASE_ADDRESS 0x00059000 | |
204 | #define DBI_BASE_ADDRESS 0x00060000 | |
205 | #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 | |
206 | #define PCIE_LOCAL_BASE_ADDRESS 0x00080000 | |
207 | ||
fc36e3ff | 208 | #define SOC_RESET_CONTROL_ADDRESS 0x00000000 |
5e3dd157 KV |
209 | #define SOC_RESET_CONTROL_OFFSET 0x00000000 |
210 | #define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001 | |
fc36e3ff MK |
211 | #define SOC_RESET_CONTROL_CE_RST_MASK 0x00040000 |
212 | #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 | |
5e3dd157 KV |
213 | #define SOC_CPU_CLOCK_OFFSET 0x00000020 |
214 | #define SOC_CPU_CLOCK_STANDARD_LSB 0 | |
215 | #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 | |
216 | #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 | |
217 | #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 | |
218 | #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 | |
219 | #define SOC_LPO_CAL_OFFSET 0x000000e0 | |
220 | #define SOC_LPO_CAL_ENABLE_LSB 20 | |
221 | #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 | |
fc36e3ff MK |
222 | #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 |
223 | #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 | |
5e3dd157 | 224 | |
e01ae68c KV |
225 | #define SOC_CHIP_ID_ADDRESS 0x000000ec |
226 | #define SOC_CHIP_ID_REV_LSB 8 | |
227 | #define SOC_CHIP_ID_REV_MASK 0x00000f00 | |
228 | ||
5e3dd157 KV |
229 | #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 |
230 | #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 | |
231 | #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 | |
232 | #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 | |
233 | ||
234 | #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 | |
235 | #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 | |
236 | #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c | |
237 | #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 | |
238 | #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 | |
239 | #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 | |
240 | #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 | |
241 | #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c | |
242 | ||
243 | #define CLOCK_GPIO_OFFSET 0xffffffff | |
244 | #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 | |
245 | #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 | |
246 | ||
247 | #define SI_CONFIG_OFFSET 0x00000000 | |
248 | #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 | |
249 | #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 | |
250 | #define SI_CONFIG_I2C_LSB 16 | |
251 | #define SI_CONFIG_I2C_MASK 0x00010000 | |
252 | #define SI_CONFIG_POS_SAMPLE_LSB 7 | |
253 | #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 | |
254 | #define SI_CONFIG_INACTIVE_DATA_LSB 5 | |
255 | #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 | |
256 | #define SI_CONFIG_INACTIVE_CLK_LSB 4 | |
257 | #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 | |
258 | #define SI_CONFIG_DIVIDER_LSB 0 | |
259 | #define SI_CONFIG_DIVIDER_MASK 0x0000000f | |
260 | #define SI_CS_OFFSET 0x00000004 | |
261 | #define SI_CS_DONE_ERR_MASK 0x00000400 | |
262 | #define SI_CS_DONE_INT_MASK 0x00000200 | |
263 | #define SI_CS_START_LSB 8 | |
264 | #define SI_CS_START_MASK 0x00000100 | |
265 | #define SI_CS_RX_CNT_LSB 4 | |
266 | #define SI_CS_RX_CNT_MASK 0x000000f0 | |
267 | #define SI_CS_TX_CNT_LSB 0 | |
268 | #define SI_CS_TX_CNT_MASK 0x0000000f | |
269 | ||
270 | #define SI_TX_DATA0_OFFSET 0x00000008 | |
271 | #define SI_TX_DATA1_OFFSET 0x0000000c | |
272 | #define SI_RX_DATA0_OFFSET 0x00000010 | |
273 | #define SI_RX_DATA1_OFFSET 0x00000014 | |
274 | ||
275 | #define CORE_CTRL_CPU_INTR_MASK 0x00002000 | |
276 | #define CORE_CTRL_ADDRESS 0x0000 | |
277 | #define PCIE_INTR_ENABLE_ADDRESS 0x0008 | |
e539887b | 278 | #define PCIE_INTR_CAUSE_ADDRESS 0x000c |
5e3dd157 KV |
279 | #define PCIE_INTR_CLR_ADDRESS 0x0014 |
280 | #define SCRATCH_3_ADDRESS 0x0030 | |
fc36e3ff | 281 | #define CPU_INTR_ADDRESS 0x0010 |
5e3dd157 KV |
282 | |
283 | /* Firmware indications to the Host via SCRATCH_3 register. */ | |
284 | #define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS) | |
285 | #define FW_IND_EVENT_PENDING 1 | |
286 | #define FW_IND_INITIALIZED 2 | |
287 | ||
288 | /* HOST_REG interrupt from firmware */ | |
289 | #define PCIE_INTR_FIRMWARE_MASK 0x00000400 | |
290 | #define PCIE_INTR_CE_MASK_ALL 0x0007f800 | |
291 | ||
292 | #define DRAM_BASE_ADDRESS 0x00400000 | |
293 | ||
294 | #define MISSING 0 | |
295 | ||
296 | #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET | |
297 | #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET | |
298 | #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET | |
299 | #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET | |
300 | #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK | |
301 | #define RESET_CONTROL_MBOX_RST_MASK MISSING | |
302 | #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK | |
303 | #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS | |
304 | #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS | |
305 | #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS | |
306 | #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK | |
307 | #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK | |
308 | #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS | |
309 | #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS | |
310 | #define LOCAL_SCRATCH_OFFSET 0x18 | |
311 | #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET | |
312 | #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET | |
313 | #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS | |
314 | #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS | |
315 | #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS | |
316 | #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS | |
317 | #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB | |
318 | #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK | |
319 | #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB | |
320 | #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK | |
321 | #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS | |
322 | #define MBOX_BASE_ADDRESS MISSING | |
323 | #define INT_STATUS_ENABLE_ERROR_LSB MISSING | |
324 | #define INT_STATUS_ENABLE_ERROR_MASK MISSING | |
325 | #define INT_STATUS_ENABLE_CPU_LSB MISSING | |
326 | #define INT_STATUS_ENABLE_CPU_MASK MISSING | |
327 | #define INT_STATUS_ENABLE_COUNTER_LSB MISSING | |
328 | #define INT_STATUS_ENABLE_COUNTER_MASK MISSING | |
329 | #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING | |
330 | #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING | |
331 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING | |
332 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING | |
333 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING | |
334 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING | |
335 | #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING | |
336 | #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING | |
337 | #define INT_STATUS_ENABLE_ADDRESS MISSING | |
338 | #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING | |
339 | #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING | |
340 | #define HOST_INT_STATUS_ADDRESS MISSING | |
341 | #define CPU_INT_STATUS_ADDRESS MISSING | |
342 | #define ERROR_INT_STATUS_ADDRESS MISSING | |
343 | #define ERROR_INT_STATUS_WAKEUP_MASK MISSING | |
344 | #define ERROR_INT_STATUS_WAKEUP_LSB MISSING | |
345 | #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING | |
346 | #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING | |
347 | #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING | |
348 | #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING | |
349 | #define COUNT_DEC_ADDRESS MISSING | |
350 | #define HOST_INT_STATUS_CPU_MASK MISSING | |
351 | #define HOST_INT_STATUS_CPU_LSB MISSING | |
352 | #define HOST_INT_STATUS_ERROR_MASK MISSING | |
353 | #define HOST_INT_STATUS_ERROR_LSB MISSING | |
354 | #define HOST_INT_STATUS_COUNTER_MASK MISSING | |
355 | #define HOST_INT_STATUS_COUNTER_LSB MISSING | |
356 | #define RX_LOOKAHEAD_VALID_ADDRESS MISSING | |
357 | #define WINDOW_DATA_ADDRESS MISSING | |
358 | #define WINDOW_READ_ADDR_ADDRESS MISSING | |
359 | #define WINDOW_WRITE_ADDR_ADDRESS MISSING | |
360 | ||
361 | #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) | |
362 | ||
363 | #endif /* _HW_H_ */ |