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d63955b3 MK |
1 | /* |
2 | * Copyright (c) 2014-2015 Qualcomm Atheros, Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/types.h> | |
587f7031 | 18 | #include "core.h" |
d63955b3 MK |
19 | #include "hw.h" |
20 | ||
21 | const struct ath10k_hw_regs qca988x_regs = { | |
d63955b3 MK |
22 | .rtc_soc_base_address = 0x00004000, |
23 | .rtc_wmac_base_address = 0x00005000, | |
24 | .soc_core_base_address = 0x00009000, | |
25 | .ce_wrapper_base_address = 0x00057000, | |
26 | .ce0_base_address = 0x00057400, | |
27 | .ce1_base_address = 0x00057800, | |
28 | .ce2_base_address = 0x00057c00, | |
29 | .ce3_base_address = 0x00058000, | |
30 | .ce4_base_address = 0x00058400, | |
31 | .ce5_base_address = 0x00058800, | |
32 | .ce6_base_address = 0x00058c00, | |
33 | .ce7_base_address = 0x00059000, | |
34 | .soc_reset_control_si0_rst_mask = 0x00000001, | |
35 | .soc_reset_control_ce_rst_mask = 0x00040000, | |
a521ee98 VT |
36 | .soc_chip_id_address = 0x000000ec, |
37 | .scratch_3_address = 0x00000030, | |
38 | .fw_indicator_address = 0x00009030, | |
39 | .pcie_local_base_address = 0x00080000, | |
40 | .ce_wrap_intr_sum_host_msi_lsb = 0x00000008, | |
41 | .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00, | |
42 | .pcie_intr_fw_mask = 0x00000400, | |
43 | .pcie_intr_ce_mask_all = 0x0007f800, | |
44 | .pcie_intr_clr_address = 0x00000014, | |
d63955b3 MK |
45 | }; |
46 | ||
47 | const struct ath10k_hw_regs qca6174_regs = { | |
d63955b3 MK |
48 | .rtc_soc_base_address = 0x00000800, |
49 | .rtc_wmac_base_address = 0x00001000, | |
50 | .soc_core_base_address = 0x0003a000, | |
51 | .ce_wrapper_base_address = 0x00034000, | |
52 | .ce0_base_address = 0x00034400, | |
53 | .ce1_base_address = 0x00034800, | |
54 | .ce2_base_address = 0x00034c00, | |
55 | .ce3_base_address = 0x00035000, | |
56 | .ce4_base_address = 0x00035400, | |
57 | .ce5_base_address = 0x00035800, | |
58 | .ce6_base_address = 0x00035c00, | |
59 | .ce7_base_address = 0x00036000, | |
60 | .soc_reset_control_si0_rst_mask = 0x00000000, | |
61 | .soc_reset_control_ce_rst_mask = 0x00000001, | |
a521ee98 VT |
62 | .soc_chip_id_address = 0x000000f0, |
63 | .scratch_3_address = 0x00000028, | |
a052158a | 64 | .fw_indicator_address = 0x0003a028, |
a521ee98 VT |
65 | .pcie_local_base_address = 0x00080000, |
66 | .ce_wrap_intr_sum_host_msi_lsb = 0x00000008, | |
67 | .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00, | |
68 | .pcie_intr_fw_mask = 0x00000400, | |
69 | .pcie_intr_ce_mask_all = 0x0007f800, | |
70 | .pcie_intr_clr_address = 0x00000014, | |
d63955b3 | 71 | }; |
587f7031 | 72 | |
8bd47021 | 73 | const struct ath10k_hw_regs qca99x0_regs = { |
8bd47021 VT |
74 | .rtc_soc_base_address = 0x00080000, |
75 | .rtc_wmac_base_address = 0x00000000, | |
76 | .soc_core_base_address = 0x00082000, | |
77 | .ce_wrapper_base_address = 0x0004d000, | |
78 | .ce0_base_address = 0x0004a000, | |
79 | .ce1_base_address = 0x0004a400, | |
80 | .ce2_base_address = 0x0004a800, | |
81 | .ce3_base_address = 0x0004ac00, | |
82 | .ce4_base_address = 0x0004b000, | |
83 | .ce5_base_address = 0x0004b400, | |
84 | .ce6_base_address = 0x0004b800, | |
85 | .ce7_base_address = 0x0004bc00, | |
86 | /* Note: qca99x0 supports upto 12 Copy Engines. Other than address of | |
87 | * CE0 and CE1 no other copy engine is directly referred in the code. | |
e13dbead | 88 | * It is not really necessary to assign address for newly supported |
8bd47021 VT |
89 | * CEs in this address table. |
90 | * Copy Engine Address | |
91 | * CE8 0x0004c000 | |
92 | * CE9 0x0004c400 | |
93 | * CE10 0x0004c800 | |
94 | * CE11 0x0004cc00 | |
95 | */ | |
96 | .soc_reset_control_si0_rst_mask = 0x00000001, | |
97 | .soc_reset_control_ce_rst_mask = 0x00000100, | |
98 | .soc_chip_id_address = 0x000000ec, | |
99 | .scratch_3_address = 0x00040050, | |
100 | .fw_indicator_address = 0x00040050, | |
101 | .pcie_local_base_address = 0x00000000, | |
102 | .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c, | |
103 | .ce_wrap_intr_sum_host_msi_mask = 0x00fff000, | |
104 | .pcie_intr_fw_mask = 0x00100000, | |
105 | .pcie_intr_ce_mask_all = 0x000fff00, | |
106 | .pcie_intr_clr_address = 0x00000010, | |
107 | }; | |
108 | ||
37a219a5 RM |
109 | const struct ath10k_hw_regs qca4019_regs = { |
110 | .rtc_soc_base_address = 0x00080000, | |
111 | .soc_core_base_address = 0x00082000, | |
112 | .ce_wrapper_base_address = 0x0004d000, | |
113 | .ce0_base_address = 0x0004a000, | |
114 | .ce1_base_address = 0x0004a400, | |
115 | .ce2_base_address = 0x0004a800, | |
116 | .ce3_base_address = 0x0004ac00, | |
117 | .ce4_base_address = 0x0004b000, | |
118 | .ce5_base_address = 0x0004b400, | |
119 | .ce6_base_address = 0x0004b800, | |
120 | .ce7_base_address = 0x0004bc00, | |
121 | /* qca4019 supports upto 12 copy engines. Since base address | |
122 | * of ce8 to ce11 are not directly referred in the code, | |
123 | * no need have them in separate members in this table. | |
124 | * Copy Engine Address | |
125 | * CE8 0x0004c000 | |
126 | * CE9 0x0004c400 | |
127 | * CE10 0x0004c800 | |
128 | * CE11 0x0004cc00 | |
129 | */ | |
130 | .soc_reset_control_si0_rst_mask = 0x00000001, | |
131 | .soc_reset_control_ce_rst_mask = 0x00000100, | |
132 | .soc_chip_id_address = 0x000000ec, | |
133 | .fw_indicator_address = 0x0004f00c, | |
134 | .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c, | |
135 | .ce_wrap_intr_sum_host_msi_mask = 0x00fff000, | |
136 | .pcie_intr_fw_mask = 0x00100000, | |
137 | .pcie_intr_ce_mask_all = 0x000fff00, | |
138 | .pcie_intr_clr_address = 0x00000010, | |
139 | }; | |
140 | ||
2f2cfc4a VT |
141 | const struct ath10k_hw_values qca988x_values = { |
142 | .rtc_state_val_on = 3, | |
143 | .ce_count = 8, | |
144 | .msi_assign_ce_max = 7, | |
145 | .num_target_ce_config_wlan = 7, | |
2adf99ca VT |
146 | .ce_desc_meta_data_mask = 0xFFFC, |
147 | .ce_desc_meta_data_lsb = 2, | |
2f2cfc4a VT |
148 | }; |
149 | ||
150 | const struct ath10k_hw_values qca6174_values = { | |
151 | .rtc_state_val_on = 3, | |
152 | .ce_count = 8, | |
153 | .msi_assign_ce_max = 7, | |
154 | .num_target_ce_config_wlan = 7, | |
2adf99ca VT |
155 | .ce_desc_meta_data_mask = 0xFFFC, |
156 | .ce_desc_meta_data_lsb = 2, | |
2f2cfc4a VT |
157 | }; |
158 | ||
8bd47021 VT |
159 | const struct ath10k_hw_values qca99x0_values = { |
160 | .rtc_state_val_on = 5, | |
161 | .ce_count = 12, | |
162 | .msi_assign_ce_max = 12, | |
163 | .num_target_ce_config_wlan = 10, | |
2adf99ca VT |
164 | .ce_desc_meta_data_mask = 0xFFF0, |
165 | .ce_desc_meta_data_lsb = 4, | |
8bd47021 VT |
166 | }; |
167 | ||
e565c312 AK |
168 | const struct ath10k_hw_values qca9888_values = { |
169 | .rtc_state_val_on = 3, | |
170 | .ce_count = 12, | |
171 | .msi_assign_ce_max = 12, | |
172 | .num_target_ce_config_wlan = 10, | |
173 | .ce_desc_meta_data_mask = 0xFFF0, | |
174 | .ce_desc_meta_data_lsb = 4, | |
175 | }; | |
176 | ||
37a219a5 RM |
177 | const struct ath10k_hw_values qca4019_values = { |
178 | .ce_count = 12, | |
179 | .num_target_ce_config_wlan = 10, | |
180 | .ce_desc_meta_data_mask = 0xFFF0, | |
181 | .ce_desc_meta_data_lsb = 4, | |
182 | }; | |
183 | ||
587f7031 MK |
184 | void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, |
185 | u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev) | |
186 | { | |
187 | u32 cc_fix = 0; | |
8e100354 | 188 | u32 rcc_fix = 0; |
26c19760 | 189 | enum ath10k_hw_cc_wraparound_type wraparound_type; |
587f7031 MK |
190 | |
191 | survey->filled |= SURVEY_INFO_TIME | | |
192 | SURVEY_INFO_TIME_BUSY; | |
193 | ||
26c19760 | 194 | wraparound_type = ar->hw_params.cc_wraparound_type; |
8e100354 VT |
195 | |
196 | if (cc < cc_prev || rcc < rcc_prev) { | |
197 | switch (wraparound_type) { | |
198 | case ATH10K_HW_CC_WRAP_SHIFTED_ALL: | |
199 | if (cc < cc_prev) { | |
200 | cc_fix = 0x7fffffff; | |
201 | survey->filled &= ~SURVEY_INFO_TIME_BUSY; | |
202 | } | |
203 | break; | |
204 | case ATH10K_HW_CC_WRAP_SHIFTED_EACH: | |
205 | if (cc < cc_prev) | |
206 | cc_fix = 0x7fffffff; | |
c11e9939 VT |
207 | |
208 | if (rcc < rcc_prev) | |
8e100354 VT |
209 | rcc_fix = 0x7fffffff; |
210 | break; | |
211 | case ATH10K_HW_CC_WRAP_DISABLED: | |
212 | break; | |
213 | } | |
587f7031 MK |
214 | } |
215 | ||
216 | cc -= cc_prev - cc_fix; | |
8e100354 | 217 | rcc -= rcc_prev - rcc_fix; |
587f7031 | 218 | |
9c8fb548 VT |
219 | survey->time = CCNT_TO_MSEC(ar, cc); |
220 | survey->time_busy = CCNT_TO_MSEC(ar, rcc); | |
587f7031 | 221 | } |
ae02c871 VT |
222 | |
223 | const struct ath10k_hw_ops qca988x_ops = { | |
224 | }; | |
225 | ||
226 | static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd) | |
227 | { | |
228 | return MS(__le32_to_cpu(rxd->msdu_end.qca99x0.info1), | |
229 | RX_MSDU_END_INFO1_L3_HDR_PAD); | |
230 | } | |
231 | ||
232 | const struct ath10k_hw_ops qca99x0_ops = { | |
233 | .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes, | |
234 | }; |