Commit | Line | Data |
---|---|---|
5e3dd157 KV |
1 | /* |
2 | * Copyright (c) 2005-2011 Atheros Communications Inc. | |
3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. | |
4 | * | |
5 | * Permission to use, copy, modify, and/or distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | */ | |
17 | ||
edb8236d | 18 | #include "core.h" |
5e3dd157 KV |
19 | #include "htc.h" |
20 | #include "htt.h" | |
21 | #include "txrx.h" | |
22 | #include "debug.h" | |
a9bf0506 | 23 | #include "trace.h" |
aa5b4fbc | 24 | #include "mac.h" |
5e3dd157 KV |
25 | |
26 | #include <linux/log2.h> | |
27 | ||
28 | /* slightly larger than one large A-MPDU */ | |
29 | #define HTT_RX_RING_SIZE_MIN 128 | |
30 | ||
31 | /* roughly 20 ms @ 1 Gbps of 1500B MSDUs */ | |
32 | #define HTT_RX_RING_SIZE_MAX 2048 | |
33 | ||
34 | #define HTT_RX_AVG_FRM_BYTES 1000 | |
35 | ||
36 | /* ms, very conservative */ | |
37 | #define HTT_RX_HOST_LATENCY_MAX_MS 20 | |
38 | ||
39 | /* ms, conservative */ | |
40 | #define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10 | |
41 | ||
42 | /* when under memory pressure rx ring refill may fail and needs a retry */ | |
43 | #define HTT_RX_RING_REFILL_RETRY_MS 50 | |
44 | ||
f6dc2095 | 45 | static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb); |
6c5151a9 | 46 | static void ath10k_htt_txrx_compl_task(unsigned long ptr); |
f6dc2095 | 47 | |
5e3dd157 KV |
48 | static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt) |
49 | { | |
50 | int size; | |
51 | ||
52 | /* | |
53 | * It is expected that the host CPU will typically be able to | |
54 | * service the rx indication from one A-MPDU before the rx | |
55 | * indication from the subsequent A-MPDU happens, roughly 1-2 ms | |
56 | * later. However, the rx ring should be sized very conservatively, | |
57 | * to accomodate the worst reasonable delay before the host CPU | |
58 | * services a rx indication interrupt. | |
59 | * | |
60 | * The rx ring need not be kept full of empty buffers. In theory, | |
61 | * the htt host SW can dynamically track the low-water mark in the | |
62 | * rx ring, and dynamically adjust the level to which the rx ring | |
63 | * is filled with empty buffers, to dynamically meet the desired | |
64 | * low-water mark. | |
65 | * | |
66 | * In contrast, it's difficult to resize the rx ring itself, once | |
67 | * it's in use. Thus, the ring itself should be sized very | |
68 | * conservatively, while the degree to which the ring is filled | |
69 | * with empty buffers should be sized moderately conservatively. | |
70 | */ | |
71 | ||
72 | /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */ | |
73 | size = | |
74 | htt->max_throughput_mbps + | |
75 | 1000 / | |
76 | (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS; | |
77 | ||
78 | if (size < HTT_RX_RING_SIZE_MIN) | |
79 | size = HTT_RX_RING_SIZE_MIN; | |
80 | ||
81 | if (size > HTT_RX_RING_SIZE_MAX) | |
82 | size = HTT_RX_RING_SIZE_MAX; | |
83 | ||
84 | size = roundup_pow_of_two(size); | |
85 | ||
86 | return size; | |
87 | } | |
88 | ||
89 | static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt) | |
90 | { | |
91 | int size; | |
92 | ||
93 | /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */ | |
94 | size = | |
95 | htt->max_throughput_mbps * | |
96 | 1000 / | |
97 | (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS; | |
98 | ||
99 | /* | |
100 | * Make sure the fill level is at least 1 less than the ring size. | |
101 | * Leaving 1 element empty allows the SW to easily distinguish | |
102 | * between a full ring vs. an empty ring. | |
103 | */ | |
104 | if (size >= htt->rx_ring.size) | |
105 | size = htt->rx_ring.size - 1; | |
106 | ||
107 | return size; | |
108 | } | |
109 | ||
110 | static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt) | |
111 | { | |
112 | struct sk_buff *skb; | |
113 | struct ath10k_skb_cb *cb; | |
114 | int i; | |
115 | ||
116 | for (i = 0; i < htt->rx_ring.fill_cnt; i++) { | |
117 | skb = htt->rx_ring.netbufs_ring[i]; | |
118 | cb = ATH10K_SKB_CB(skb); | |
119 | dma_unmap_single(htt->ar->dev, cb->paddr, | |
120 | skb->len + skb_tailroom(skb), | |
121 | DMA_FROM_DEVICE); | |
122 | dev_kfree_skb_any(skb); | |
123 | } | |
124 | ||
125 | htt->rx_ring.fill_cnt = 0; | |
126 | } | |
127 | ||
128 | static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num) | |
129 | { | |
130 | struct htt_rx_desc *rx_desc; | |
131 | struct sk_buff *skb; | |
132 | dma_addr_t paddr; | |
133 | int ret = 0, idx; | |
134 | ||
8cc7f26c | 135 | idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); |
5e3dd157 KV |
136 | while (num > 0) { |
137 | skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN); | |
138 | if (!skb) { | |
139 | ret = -ENOMEM; | |
140 | goto fail; | |
141 | } | |
142 | ||
143 | if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN)) | |
144 | skb_pull(skb, | |
145 | PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) - | |
146 | skb->data); | |
147 | ||
148 | /* Clear rx_desc attention word before posting to Rx ring */ | |
149 | rx_desc = (struct htt_rx_desc *)skb->data; | |
150 | rx_desc->attention.flags = __cpu_to_le32(0); | |
151 | ||
152 | paddr = dma_map_single(htt->ar->dev, skb->data, | |
153 | skb->len + skb_tailroom(skb), | |
154 | DMA_FROM_DEVICE); | |
155 | ||
156 | if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) { | |
157 | dev_kfree_skb_any(skb); | |
158 | ret = -ENOMEM; | |
159 | goto fail; | |
160 | } | |
161 | ||
162 | ATH10K_SKB_CB(skb)->paddr = paddr; | |
163 | htt->rx_ring.netbufs_ring[idx] = skb; | |
164 | htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr); | |
165 | htt->rx_ring.fill_cnt++; | |
166 | ||
167 | num--; | |
168 | idx++; | |
169 | idx &= htt->rx_ring.size_mask; | |
170 | } | |
171 | ||
172 | fail: | |
8cc7f26c | 173 | *htt->rx_ring.alloc_idx.vaddr = __cpu_to_le32(idx); |
5e3dd157 KV |
174 | return ret; |
175 | } | |
176 | ||
177 | static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num) | |
178 | { | |
179 | lockdep_assert_held(&htt->rx_ring.lock); | |
180 | return __ath10k_htt_rx_ring_fill_n(htt, num); | |
181 | } | |
182 | ||
183 | static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt) | |
184 | { | |
6e712d42 | 185 | int ret, num_deficit, num_to_fill; |
5e3dd157 | 186 | |
6e712d42 MK |
187 | /* Refilling the whole RX ring buffer proves to be a bad idea. The |
188 | * reason is RX may take up significant amount of CPU cycles and starve | |
189 | * other tasks, e.g. TX on an ethernet device while acting as a bridge | |
190 | * with ath10k wlan interface. This ended up with very poor performance | |
191 | * once CPU the host system was overwhelmed with RX on ath10k. | |
192 | * | |
193 | * By limiting the number of refills the replenishing occurs | |
194 | * progressively. This in turns makes use of the fact tasklets are | |
195 | * processed in FIFO order. This means actual RX processing can starve | |
196 | * out refilling. If there's not enough buffers on RX ring FW will not | |
197 | * report RX until it is refilled with enough buffers. This | |
198 | * automatically balances load wrt to CPU power. | |
199 | * | |
200 | * This probably comes at a cost of lower maximum throughput but | |
201 | * improves the avarage and stability. */ | |
5e3dd157 | 202 | spin_lock_bh(&htt->rx_ring.lock); |
6e712d42 MK |
203 | num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt; |
204 | num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit); | |
205 | num_deficit -= num_to_fill; | |
5e3dd157 KV |
206 | ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill); |
207 | if (ret == -ENOMEM) { | |
208 | /* | |
209 | * Failed to fill it to the desired level - | |
210 | * we'll start a timer and try again next time. | |
211 | * As long as enough buffers are left in the ring for | |
212 | * another A-MPDU rx, no special recovery is needed. | |
213 | */ | |
214 | mod_timer(&htt->rx_ring.refill_retry_timer, jiffies + | |
215 | msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS)); | |
6e712d42 MK |
216 | } else if (num_deficit > 0) { |
217 | tasklet_schedule(&htt->rx_replenish_task); | |
5e3dd157 KV |
218 | } |
219 | spin_unlock_bh(&htt->rx_ring.lock); | |
220 | } | |
221 | ||
222 | static void ath10k_htt_rx_ring_refill_retry(unsigned long arg) | |
223 | { | |
224 | struct ath10k_htt *htt = (struct ath10k_htt *)arg; | |
af762c0b | 225 | |
5e3dd157 KV |
226 | ath10k_htt_rx_msdu_buff_replenish(htt); |
227 | } | |
228 | ||
3e841fd0 | 229 | static void ath10k_htt_rx_ring_clean_up(struct ath10k_htt *htt) |
5e3dd157 | 230 | { |
3e841fd0 MK |
231 | struct sk_buff *skb; |
232 | int i; | |
233 | ||
234 | for (i = 0; i < htt->rx_ring.size; i++) { | |
235 | skb = htt->rx_ring.netbufs_ring[i]; | |
236 | if (!skb) | |
237 | continue; | |
238 | ||
239 | dma_unmap_single(htt->ar->dev, ATH10K_SKB_CB(skb)->paddr, | |
240 | skb->len + skb_tailroom(skb), | |
241 | DMA_FROM_DEVICE); | |
242 | dev_kfree_skb_any(skb); | |
243 | htt->rx_ring.netbufs_ring[i] = NULL; | |
244 | } | |
245 | } | |
5e3dd157 | 246 | |
95bf21f9 | 247 | void ath10k_htt_rx_free(struct ath10k_htt *htt) |
3e841fd0 | 248 | { |
5e3dd157 | 249 | del_timer_sync(&htt->rx_ring.refill_retry_timer); |
6e712d42 | 250 | tasklet_kill(&htt->rx_replenish_task); |
6c5151a9 MK |
251 | tasklet_kill(&htt->txrx_compl_task); |
252 | ||
253 | skb_queue_purge(&htt->tx_compl_q); | |
254 | skb_queue_purge(&htt->rx_compl_q); | |
5e3dd157 | 255 | |
3e841fd0 | 256 | ath10k_htt_rx_ring_clean_up(htt); |
5e3dd157 KV |
257 | |
258 | dma_free_coherent(htt->ar->dev, | |
259 | (htt->rx_ring.size * | |
260 | sizeof(htt->rx_ring.paddrs_ring)), | |
261 | htt->rx_ring.paddrs_ring, | |
262 | htt->rx_ring.base_paddr); | |
263 | ||
264 | dma_free_coherent(htt->ar->dev, | |
265 | sizeof(*htt->rx_ring.alloc_idx.vaddr), | |
266 | htt->rx_ring.alloc_idx.vaddr, | |
267 | htt->rx_ring.alloc_idx.paddr); | |
268 | ||
269 | kfree(htt->rx_ring.netbufs_ring); | |
270 | } | |
271 | ||
272 | static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt) | |
273 | { | |
7aa7a72a | 274 | struct ath10k *ar = htt->ar; |
5e3dd157 KV |
275 | int idx; |
276 | struct sk_buff *msdu; | |
277 | ||
45967089 | 278 | lockdep_assert_held(&htt->rx_ring.lock); |
5e3dd157 | 279 | |
8d60ee87 | 280 | if (htt->rx_ring.fill_cnt == 0) { |
7aa7a72a | 281 | ath10k_warn(ar, "tried to pop sk_buff from an empty rx ring\n"); |
8d60ee87 MK |
282 | return NULL; |
283 | } | |
5e3dd157 KV |
284 | |
285 | idx = htt->rx_ring.sw_rd_idx.msdu_payld; | |
286 | msdu = htt->rx_ring.netbufs_ring[idx]; | |
3e841fd0 | 287 | htt->rx_ring.netbufs_ring[idx] = NULL; |
5e3dd157 KV |
288 | |
289 | idx++; | |
290 | idx &= htt->rx_ring.size_mask; | |
291 | htt->rx_ring.sw_rd_idx.msdu_payld = idx; | |
292 | htt->rx_ring.fill_cnt--; | |
293 | ||
9b57f88f RM |
294 | trace_ath10k_htt_rx_pop_msdu(ar, msdu->data, msdu->len + |
295 | skb_tailroom(msdu)); | |
296 | ||
5e3dd157 KV |
297 | return msdu; |
298 | } | |
299 | ||
300 | static void ath10k_htt_rx_free_msdu_chain(struct sk_buff *skb) | |
301 | { | |
302 | struct sk_buff *next; | |
303 | ||
304 | while (skb) { | |
305 | next = skb->next; | |
306 | dev_kfree_skb_any(skb); | |
307 | skb = next; | |
308 | } | |
309 | } | |
310 | ||
d84dd60f | 311 | /* return: < 0 fatal error, 0 - non chained msdu, 1 chained msdu */ |
5e3dd157 KV |
312 | static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt, |
313 | u8 **fw_desc, int *fw_desc_len, | |
314 | struct sk_buff **head_msdu, | |
0ccb7a34 JD |
315 | struct sk_buff **tail_msdu, |
316 | u32 *attention) | |
5e3dd157 | 317 | { |
7aa7a72a | 318 | struct ath10k *ar = htt->ar; |
5e3dd157 | 319 | int msdu_len, msdu_chaining = 0; |
af762c0b | 320 | struct sk_buff *msdu, *next; |
5e3dd157 | 321 | struct htt_rx_desc *rx_desc; |
a0883cf7 | 322 | u32 tsf; |
5e3dd157 | 323 | |
45967089 MK |
324 | lockdep_assert_held(&htt->rx_ring.lock); |
325 | ||
5e3dd157 | 326 | if (htt->rx_confused) { |
7aa7a72a | 327 | ath10k_warn(ar, "htt is confused. refusing rx\n"); |
d84dd60f | 328 | return -1; |
5e3dd157 KV |
329 | } |
330 | ||
331 | msdu = *head_msdu = ath10k_htt_rx_netbuf_pop(htt); | |
332 | while (msdu) { | |
333 | int last_msdu, msdu_len_invalid, msdu_chained; | |
334 | ||
335 | dma_unmap_single(htt->ar->dev, | |
336 | ATH10K_SKB_CB(msdu)->paddr, | |
337 | msdu->len + skb_tailroom(msdu), | |
338 | DMA_FROM_DEVICE); | |
339 | ||
7aa7a72a | 340 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx pop: ", |
5e3dd157 KV |
341 | msdu->data, msdu->len + skb_tailroom(msdu)); |
342 | ||
343 | rx_desc = (struct htt_rx_desc *)msdu->data; | |
344 | ||
345 | /* FIXME: we must report msdu payload since this is what caller | |
346 | * expects now */ | |
347 | skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload)); | |
348 | skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload)); | |
349 | ||
350 | /* | |
351 | * Sanity check - confirm the HW is finished filling in the | |
352 | * rx data. | |
353 | * If the HW and SW are working correctly, then it's guaranteed | |
354 | * that the HW's MAC DMA is done before this point in the SW. | |
355 | * To prevent the case that we handle a stale Rx descriptor, | |
356 | * just assert for now until we have a way to recover. | |
357 | */ | |
358 | if (!(__le32_to_cpu(rx_desc->attention.flags) | |
359 | & RX_ATTENTION_FLAGS_MSDU_DONE)) { | |
360 | ath10k_htt_rx_free_msdu_chain(*head_msdu); | |
361 | *head_msdu = NULL; | |
362 | msdu = NULL; | |
7aa7a72a | 363 | ath10k_err(ar, "htt rx stopped. cannot recover\n"); |
5e3dd157 KV |
364 | htt->rx_confused = true; |
365 | break; | |
366 | } | |
367 | ||
0ccb7a34 JD |
368 | *attention |= __le32_to_cpu(rx_desc->attention.flags) & |
369 | (RX_ATTENTION_FLAGS_TKIP_MIC_ERR | | |
370 | RX_ATTENTION_FLAGS_DECRYPT_ERR | | |
371 | RX_ATTENTION_FLAGS_FCS_ERR | | |
372 | RX_ATTENTION_FLAGS_MGMT_TYPE); | |
5e3dd157 KV |
373 | /* |
374 | * Copy the FW rx descriptor for this MSDU from the rx | |
375 | * indication message into the MSDU's netbuf. HL uses the | |
376 | * same rx indication message definition as LL, and simply | |
377 | * appends new info (fields from the HW rx desc, and the | |
378 | * MSDU payload itself). So, the offset into the rx | |
379 | * indication message only has to account for the standard | |
380 | * offset of the per-MSDU FW rx desc info within the | |
381 | * message, and how many bytes of the per-MSDU FW rx desc | |
382 | * info have already been consumed. (And the endianness of | |
383 | * the host, since for a big-endian host, the rx ind | |
384 | * message contents, including the per-MSDU rx desc bytes, | |
385 | * were byteswapped during upload.) | |
386 | */ | |
387 | if (*fw_desc_len > 0) { | |
388 | rx_desc->fw_desc.info0 = **fw_desc; | |
389 | /* | |
390 | * The target is expected to only provide the basic | |
391 | * per-MSDU rx descriptors. Just to be sure, verify | |
392 | * that the target has not attached extension data | |
393 | * (e.g. LRO flow ID). | |
394 | */ | |
395 | ||
396 | /* or more, if there's extension data */ | |
397 | (*fw_desc)++; | |
398 | (*fw_desc_len)--; | |
399 | } else { | |
400 | /* | |
401 | * When an oversized AMSDU happened, FW will lost | |
402 | * some of MSDU status - in this case, the FW | |
403 | * descriptors provided will be less than the | |
404 | * actual MSDUs inside this MPDU. Mark the FW | |
405 | * descriptors so that it will still deliver to | |
406 | * upper stack, if no CRC error for this MPDU. | |
407 | * | |
408 | * FIX THIS - the FW descriptors are actually for | |
409 | * MSDUs in the end of this A-MSDU instead of the | |
410 | * beginning. | |
411 | */ | |
412 | rx_desc->fw_desc.info0 = 0; | |
413 | } | |
414 | ||
415 | msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags) | |
416 | & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR | | |
417 | RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR)); | |
418 | msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0), | |
419 | RX_MSDU_START_INFO0_MSDU_LENGTH); | |
420 | msdu_chained = rx_desc->frag_info.ring2_more_count; | |
421 | ||
422 | if (msdu_len_invalid) | |
423 | msdu_len = 0; | |
424 | ||
425 | skb_trim(msdu, 0); | |
426 | skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE)); | |
427 | msdu_len -= msdu->len; | |
428 | ||
429 | /* FIXME: Do chained buffers include htt_rx_desc or not? */ | |
430 | while (msdu_chained--) { | |
431 | struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt); | |
432 | ||
433 | dma_unmap_single(htt->ar->dev, | |
434 | ATH10K_SKB_CB(next)->paddr, | |
435 | next->len + skb_tailroom(next), | |
436 | DMA_FROM_DEVICE); | |
437 | ||
7aa7a72a | 438 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, |
75fb2f94 | 439 | "htt rx chained: ", next->data, |
5e3dd157 KV |
440 | next->len + skb_tailroom(next)); |
441 | ||
442 | skb_trim(next, 0); | |
443 | skb_put(next, min(msdu_len, HTT_RX_BUF_SIZE)); | |
444 | msdu_len -= next->len; | |
445 | ||
446 | msdu->next = next; | |
447 | msdu = next; | |
ede9c8e0 | 448 | msdu_chaining = 1; |
5e3dd157 KV |
449 | } |
450 | ||
5e3dd157 KV |
451 | last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) & |
452 | RX_MSDU_END_INFO0_LAST_MSDU; | |
453 | ||
a0883cf7 RM |
454 | tsf = __le32_to_cpu(rx_desc->ppdu_end.tsf_timestamp); |
455 | trace_ath10k_htt_rx_desc(ar, tsf, &rx_desc->attention, | |
456 | sizeof(*rx_desc) - sizeof(u32)); | |
5e3dd157 KV |
457 | if (last_msdu) { |
458 | msdu->next = NULL; | |
459 | break; | |
5e3dd157 | 460 | } |
d8bb26b9 KV |
461 | |
462 | next = ath10k_htt_rx_netbuf_pop(htt); | |
463 | msdu->next = next; | |
464 | msdu = next; | |
5e3dd157 KV |
465 | } |
466 | *tail_msdu = msdu; | |
467 | ||
d84dd60f JD |
468 | if (*head_msdu == NULL) |
469 | msdu_chaining = -1; | |
470 | ||
5e3dd157 KV |
471 | /* |
472 | * Don't refill the ring yet. | |
473 | * | |
474 | * First, the elements popped here are still in use - it is not | |
475 | * safe to overwrite them until the matching call to | |
476 | * mpdu_desc_list_next. Second, for efficiency it is preferable to | |
477 | * refill the rx ring with 1 PPDU's worth of rx buffers (something | |
478 | * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers | |
479 | * (something like 3 buffers). Consequently, we'll rely on the txrx | |
480 | * SW to tell us when it is done pulling all the PPDU's rx buffers | |
481 | * out of the rx ring, and then refill it just once. | |
482 | */ | |
483 | ||
484 | return msdu_chaining; | |
485 | } | |
486 | ||
6e712d42 MK |
487 | static void ath10k_htt_rx_replenish_task(unsigned long ptr) |
488 | { | |
489 | struct ath10k_htt *htt = (struct ath10k_htt *)ptr; | |
af762c0b | 490 | |
6e712d42 MK |
491 | ath10k_htt_rx_msdu_buff_replenish(htt); |
492 | } | |
493 | ||
95bf21f9 | 494 | int ath10k_htt_rx_alloc(struct ath10k_htt *htt) |
5e3dd157 | 495 | { |
7aa7a72a | 496 | struct ath10k *ar = htt->ar; |
5e3dd157 KV |
497 | dma_addr_t paddr; |
498 | void *vaddr; | |
bd8bdbb6 | 499 | size_t size; |
5e3dd157 KV |
500 | struct timer_list *timer = &htt->rx_ring.refill_retry_timer; |
501 | ||
502 | htt->rx_ring.size = ath10k_htt_rx_ring_size(htt); | |
503 | if (!is_power_of_2(htt->rx_ring.size)) { | |
7aa7a72a | 504 | ath10k_warn(ar, "htt rx ring size is not power of 2\n"); |
5e3dd157 KV |
505 | return -EINVAL; |
506 | } | |
507 | ||
508 | htt->rx_ring.size_mask = htt->rx_ring.size - 1; | |
509 | ||
510 | /* | |
511 | * Set the initial value for the level to which the rx ring | |
512 | * should be filled, based on the max throughput and the | |
513 | * worst likely latency for the host to fill the rx ring | |
514 | * with new buffers. In theory, this fill level can be | |
515 | * dynamically adjusted from the initial value set here, to | |
516 | * reflect the actual host latency rather than a | |
517 | * conservative assumption about the host latency. | |
518 | */ | |
519 | htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt); | |
520 | ||
521 | htt->rx_ring.netbufs_ring = | |
3e841fd0 | 522 | kzalloc(htt->rx_ring.size * sizeof(struct sk_buff *), |
5e3dd157 KV |
523 | GFP_KERNEL); |
524 | if (!htt->rx_ring.netbufs_ring) | |
525 | goto err_netbuf; | |
526 | ||
bd8bdbb6 KV |
527 | size = htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring); |
528 | ||
529 | vaddr = dma_alloc_coherent(htt->ar->dev, size, &paddr, GFP_DMA); | |
5e3dd157 KV |
530 | if (!vaddr) |
531 | goto err_dma_ring; | |
532 | ||
533 | htt->rx_ring.paddrs_ring = vaddr; | |
534 | htt->rx_ring.base_paddr = paddr; | |
535 | ||
536 | vaddr = dma_alloc_coherent(htt->ar->dev, | |
537 | sizeof(*htt->rx_ring.alloc_idx.vaddr), | |
538 | &paddr, GFP_DMA); | |
539 | if (!vaddr) | |
540 | goto err_dma_idx; | |
541 | ||
542 | htt->rx_ring.alloc_idx.vaddr = vaddr; | |
543 | htt->rx_ring.alloc_idx.paddr = paddr; | |
544 | htt->rx_ring.sw_rd_idx.msdu_payld = 0; | |
545 | *htt->rx_ring.alloc_idx.vaddr = 0; | |
546 | ||
547 | /* Initialize the Rx refill retry timer */ | |
548 | setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt); | |
549 | ||
550 | spin_lock_init(&htt->rx_ring.lock); | |
551 | ||
552 | htt->rx_ring.fill_cnt = 0; | |
553 | if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level)) | |
554 | goto err_fill_ring; | |
555 | ||
6e712d42 MK |
556 | tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task, |
557 | (unsigned long)htt); | |
558 | ||
6c5151a9 MK |
559 | skb_queue_head_init(&htt->tx_compl_q); |
560 | skb_queue_head_init(&htt->rx_compl_q); | |
561 | ||
562 | tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task, | |
563 | (unsigned long)htt); | |
564 | ||
7aa7a72a | 565 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n", |
5e3dd157 KV |
566 | htt->rx_ring.size, htt->rx_ring.fill_level); |
567 | return 0; | |
568 | ||
569 | err_fill_ring: | |
570 | ath10k_htt_rx_ring_free(htt); | |
571 | dma_free_coherent(htt->ar->dev, | |
572 | sizeof(*htt->rx_ring.alloc_idx.vaddr), | |
573 | htt->rx_ring.alloc_idx.vaddr, | |
574 | htt->rx_ring.alloc_idx.paddr); | |
575 | err_dma_idx: | |
576 | dma_free_coherent(htt->ar->dev, | |
577 | (htt->rx_ring.size * | |
578 | sizeof(htt->rx_ring.paddrs_ring)), | |
579 | htt->rx_ring.paddrs_ring, | |
580 | htt->rx_ring.base_paddr); | |
581 | err_dma_ring: | |
582 | kfree(htt->rx_ring.netbufs_ring); | |
583 | err_netbuf: | |
584 | return -ENOMEM; | |
585 | } | |
586 | ||
7aa7a72a MK |
587 | static int ath10k_htt_rx_crypto_param_len(struct ath10k *ar, |
588 | enum htt_rx_mpdu_encrypt_type type) | |
5e3dd157 KV |
589 | { |
590 | switch (type) { | |
591 | case HTT_RX_MPDU_ENCRYPT_WEP40: | |
592 | case HTT_RX_MPDU_ENCRYPT_WEP104: | |
593 | return 4; | |
594 | case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC: | |
595 | case HTT_RX_MPDU_ENCRYPT_WEP128: /* not tested */ | |
596 | case HTT_RX_MPDU_ENCRYPT_TKIP_WPA: | |
597 | case HTT_RX_MPDU_ENCRYPT_WAPI: /* not tested */ | |
598 | case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2: | |
599 | return 8; | |
600 | case HTT_RX_MPDU_ENCRYPT_NONE: | |
601 | return 0; | |
602 | } | |
603 | ||
7aa7a72a | 604 | ath10k_warn(ar, "unknown encryption type %d\n", type); |
5e3dd157 KV |
605 | return 0; |
606 | } | |
607 | ||
7aa7a72a MK |
608 | static int ath10k_htt_rx_crypto_tail_len(struct ath10k *ar, |
609 | enum htt_rx_mpdu_encrypt_type type) | |
5e3dd157 KV |
610 | { |
611 | switch (type) { | |
612 | case HTT_RX_MPDU_ENCRYPT_NONE: | |
613 | case HTT_RX_MPDU_ENCRYPT_WEP40: | |
614 | case HTT_RX_MPDU_ENCRYPT_WEP104: | |
615 | case HTT_RX_MPDU_ENCRYPT_WEP128: | |
616 | case HTT_RX_MPDU_ENCRYPT_WAPI: | |
617 | return 0; | |
618 | case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC: | |
619 | case HTT_RX_MPDU_ENCRYPT_TKIP_WPA: | |
620 | return 4; | |
621 | case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2: | |
622 | return 8; | |
623 | } | |
624 | ||
7aa7a72a | 625 | ath10k_warn(ar, "unknown encryption type %d\n", type); |
5e3dd157 KV |
626 | return 0; |
627 | } | |
628 | ||
629 | /* Applies for first msdu in chain, before altering it. */ | |
630 | static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb) | |
631 | { | |
632 | struct htt_rx_desc *rxd; | |
633 | enum rx_msdu_decap_format fmt; | |
634 | ||
635 | rxd = (void *)skb->data - sizeof(*rxd); | |
636 | fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), | |
5b07e07f | 637 | RX_MSDU_START_INFO1_DECAP_FORMAT); |
5e3dd157 KV |
638 | |
639 | if (fmt == RX_MSDU_DECAP_RAW) | |
640 | return (void *)skb->data; | |
d8bb26b9 KV |
641 | |
642 | return (void *)skb->data - RX_HTT_HDR_STATUS_LEN; | |
5e3dd157 KV |
643 | } |
644 | ||
645 | /* This function only applies for first msdu in an msdu chain */ | |
646 | static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr) | |
647 | { | |
af762c0b KV |
648 | u8 *qc; |
649 | ||
5e3dd157 | 650 | if (ieee80211_is_data_qos(hdr->frame_control)) { |
af762c0b | 651 | qc = ieee80211_get_qos_ctl(hdr); |
5e3dd157 KV |
652 | if (qc[0] & 0x80) |
653 | return true; | |
654 | } | |
655 | return false; | |
656 | } | |
657 | ||
f6dc2095 MK |
658 | struct rfc1042_hdr { |
659 | u8 llc_dsap; | |
660 | u8 llc_ssap; | |
661 | u8 llc_ctrl; | |
662 | u8 snap_oui[3]; | |
663 | __be16 snap_type; | |
664 | } __packed; | |
665 | ||
666 | struct amsdu_subframe_hdr { | |
667 | u8 dst[ETH_ALEN]; | |
668 | u8 src[ETH_ALEN]; | |
669 | __be16 len; | |
670 | } __packed; | |
671 | ||
73539b40 JD |
672 | static const u8 rx_legacy_rate_idx[] = { |
673 | 3, /* 0x00 - 11Mbps */ | |
674 | 2, /* 0x01 - 5.5Mbps */ | |
675 | 1, /* 0x02 - 2Mbps */ | |
676 | 0, /* 0x03 - 1Mbps */ | |
677 | 3, /* 0x04 - 11Mbps */ | |
678 | 2, /* 0x05 - 5.5Mbps */ | |
679 | 1, /* 0x06 - 2Mbps */ | |
680 | 0, /* 0x07 - 1Mbps */ | |
681 | 10, /* 0x08 - 48Mbps */ | |
682 | 8, /* 0x09 - 24Mbps */ | |
683 | 6, /* 0x0A - 12Mbps */ | |
684 | 4, /* 0x0B - 6Mbps */ | |
685 | 11, /* 0x0C - 54Mbps */ | |
686 | 9, /* 0x0D - 36Mbps */ | |
687 | 7, /* 0x0E - 18Mbps */ | |
688 | 5, /* 0x0F - 9Mbps */ | |
689 | }; | |
690 | ||
87326c97 | 691 | static void ath10k_htt_rx_h_rates(struct ath10k *ar, |
cfadd9ba | 692 | enum ieee80211_band band, |
87326c97 | 693 | u8 info0, u32 info1, u32 info2, |
cfadd9ba | 694 | struct ieee80211_rx_status *status) |
73539b40 JD |
695 | { |
696 | u8 cck, rate, rate_idx, bw, sgi, mcs, nss; | |
73539b40 JD |
697 | u8 preamble = 0; |
698 | ||
699 | /* Check if valid fields */ | |
700 | if (!(info0 & HTT_RX_INDICATION_INFO0_START_VALID)) | |
701 | return; | |
702 | ||
703 | preamble = MS(info1, HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE); | |
704 | ||
705 | switch (preamble) { | |
706 | case HTT_RX_LEGACY: | |
707 | cck = info0 & HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK; | |
708 | rate = MS(info0, HTT_RX_INDICATION_INFO0_LEGACY_RATE); | |
709 | rate_idx = 0; | |
710 | ||
711 | if (rate < 0x08 || rate > 0x0F) | |
712 | break; | |
713 | ||
714 | switch (band) { | |
715 | case IEEE80211_BAND_2GHZ: | |
716 | if (cck) | |
717 | rate &= ~BIT(3); | |
718 | rate_idx = rx_legacy_rate_idx[rate]; | |
719 | break; | |
720 | case IEEE80211_BAND_5GHZ: | |
721 | rate_idx = rx_legacy_rate_idx[rate]; | |
722 | /* We are using same rate table registering | |
723 | HW - ath10k_rates[]. In case of 5GHz skip | |
724 | CCK rates, so -4 here */ | |
725 | rate_idx -= 4; | |
726 | break; | |
727 | default: | |
728 | break; | |
729 | } | |
730 | ||
731 | status->rate_idx = rate_idx; | |
732 | break; | |
733 | case HTT_RX_HT: | |
734 | case HTT_RX_HT_WITH_TXBF: | |
735 | /* HT-SIG - Table 20-11 in info1 and info2 */ | |
736 | mcs = info1 & 0x1F; | |
737 | nss = mcs >> 3; | |
738 | bw = (info1 >> 7) & 1; | |
739 | sgi = (info2 >> 7) & 1; | |
740 | ||
741 | status->rate_idx = mcs; | |
742 | status->flag |= RX_FLAG_HT; | |
743 | if (sgi) | |
744 | status->flag |= RX_FLAG_SHORT_GI; | |
745 | if (bw) | |
746 | status->flag |= RX_FLAG_40MHZ; | |
747 | break; | |
748 | case HTT_RX_VHT: | |
749 | case HTT_RX_VHT_WITH_TXBF: | |
750 | /* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2 | |
751 | TODO check this */ | |
752 | mcs = (info2 >> 4) & 0x0F; | |
753 | nss = ((info1 >> 10) & 0x07) + 1; | |
754 | bw = info1 & 3; | |
755 | sgi = info2 & 1; | |
756 | ||
757 | status->rate_idx = mcs; | |
758 | status->vht_nss = nss; | |
759 | ||
760 | if (sgi) | |
761 | status->flag |= RX_FLAG_SHORT_GI; | |
762 | ||
763 | switch (bw) { | |
764 | /* 20MHZ */ | |
765 | case 0: | |
766 | break; | |
767 | /* 40MHZ */ | |
768 | case 1: | |
769 | status->flag |= RX_FLAG_40MHZ; | |
770 | break; | |
771 | /* 80MHZ */ | |
772 | case 2: | |
773 | status->vht_flag |= RX_VHT_FLAG_80MHZ; | |
774 | } | |
775 | ||
776 | status->flag |= RX_FLAG_VHT; | |
777 | break; | |
778 | default: | |
779 | break; | |
780 | } | |
781 | } | |
782 | ||
87326c97 | 783 | static void ath10k_htt_rx_h_protected(struct ath10k_htt *htt, |
85f6d7cf JD |
784 | struct ieee80211_rx_status *rx_status, |
785 | struct sk_buff *skb, | |
c071dcb2 MK |
786 | enum htt_rx_mpdu_encrypt_type enctype, |
787 | enum rx_msdu_decap_format fmt, | |
788 | bool dot11frag) | |
87326c97 | 789 | { |
85f6d7cf | 790 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
87326c97 | 791 | |
c071dcb2 MK |
792 | rx_status->flag &= ~(RX_FLAG_DECRYPTED | |
793 | RX_FLAG_IV_STRIPPED | | |
794 | RX_FLAG_MMIC_STRIPPED); | |
87326c97 | 795 | |
c071dcb2 MK |
796 | if (enctype == HTT_RX_MPDU_ENCRYPT_NONE) |
797 | return; | |
798 | ||
799 | /* | |
800 | * There's no explicit rx descriptor flag to indicate whether a given | |
801 | * frame has been decrypted or not. We're forced to use the decap | |
802 | * format as an implicit indication. However fragmentation rx is always | |
803 | * raw and it probably never reports undecrypted raws. | |
804 | * | |
805 | * This makes sure sniffed frames are reported as-is without stripping | |
806 | * the protected flag. | |
807 | */ | |
808 | if (fmt == RX_MSDU_DECAP_RAW && !dot11frag) | |
87326c97 | 809 | return; |
87326c97 | 810 | |
85f6d7cf JD |
811 | rx_status->flag |= RX_FLAG_DECRYPTED | |
812 | RX_FLAG_IV_STRIPPED | | |
813 | RX_FLAG_MMIC_STRIPPED; | |
87326c97 JD |
814 | hdr->frame_control = __cpu_to_le16(__le16_to_cpu(hdr->frame_control) & |
815 | ~IEEE80211_FCTL_PROTECTED); | |
816 | } | |
817 | ||
36653f05 JD |
818 | static bool ath10k_htt_rx_h_channel(struct ath10k *ar, |
819 | struct ieee80211_rx_status *status) | |
820 | { | |
821 | struct ieee80211_channel *ch; | |
822 | ||
823 | spin_lock_bh(&ar->data_lock); | |
824 | ch = ar->scan_channel; | |
825 | if (!ch) | |
826 | ch = ar->rx_channel; | |
827 | spin_unlock_bh(&ar->data_lock); | |
828 | ||
829 | if (!ch) | |
830 | return false; | |
831 | ||
832 | status->band = ch->band; | |
833 | status->freq = ch->center_freq; | |
834 | ||
835 | return true; | |
836 | } | |
837 | ||
76f5329a JD |
838 | static const char * const tid_to_ac[] = { |
839 | "BE", | |
840 | "BK", | |
841 | "BK", | |
842 | "BE", | |
843 | "VI", | |
844 | "VI", | |
845 | "VO", | |
846 | "VO", | |
847 | }; | |
848 | ||
849 | static char *ath10k_get_tid(struct ieee80211_hdr *hdr, char *out, size_t size) | |
850 | { | |
851 | u8 *qc; | |
852 | int tid; | |
853 | ||
854 | if (!ieee80211_is_data_qos(hdr->frame_control)) | |
855 | return ""; | |
856 | ||
857 | qc = ieee80211_get_qos_ctl(hdr); | |
858 | tid = *qc & IEEE80211_QOS_CTL_TID_MASK; | |
859 | if (tid < 8) | |
860 | snprintf(out, size, "tid %d (%s)", tid, tid_to_ac[tid]); | |
861 | else | |
862 | snprintf(out, size, "tid %d", tid); | |
863 | ||
864 | return out; | |
865 | } | |
866 | ||
85f6d7cf JD |
867 | static void ath10k_process_rx(struct ath10k *ar, |
868 | struct ieee80211_rx_status *rx_status, | |
869 | struct sk_buff *skb) | |
73539b40 JD |
870 | { |
871 | struct ieee80211_rx_status *status; | |
76f5329a JD |
872 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
873 | char tid[32]; | |
73539b40 | 874 | |
85f6d7cf JD |
875 | status = IEEE80211_SKB_RXCB(skb); |
876 | *status = *rx_status; | |
73539b40 | 877 | |
7aa7a72a | 878 | ath10k_dbg(ar, ATH10K_DBG_DATA, |
76f5329a | 879 | "rx skb %p len %u peer %pM %s %s sn %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", |
85f6d7cf JD |
880 | skb, |
881 | skb->len, | |
76f5329a JD |
882 | ieee80211_get_SA(hdr), |
883 | ath10k_get_tid(hdr, tid, sizeof(tid)), | |
884 | is_multicast_ether_addr(ieee80211_get_DA(hdr)) ? | |
885 | "mcast" : "ucast", | |
886 | (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4, | |
73539b40 JD |
887 | status->flag == 0 ? "legacy" : "", |
888 | status->flag & RX_FLAG_HT ? "ht" : "", | |
889 | status->flag & RX_FLAG_VHT ? "vht" : "", | |
890 | status->flag & RX_FLAG_40MHZ ? "40" : "", | |
891 | status->vht_flag & RX_VHT_FLAG_80MHZ ? "80" : "", | |
892 | status->flag & RX_FLAG_SHORT_GI ? "sgi " : "", | |
893 | status->rate_idx, | |
894 | status->vht_nss, | |
895 | status->freq, | |
87326c97 | 896 | status->band, status->flag, |
78433f96 | 897 | !!(status->flag & RX_FLAG_FAILED_FCS_CRC), |
76f5329a JD |
898 | !!(status->flag & RX_FLAG_MMIC_ERROR), |
899 | !!(status->flag & RX_FLAG_AMSDU_MORE)); | |
7aa7a72a | 900 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ", |
85f6d7cf | 901 | skb->data, skb->len); |
73539b40 | 902 | |
85f6d7cf | 903 | ieee80211_rx(ar->hw, skb); |
73539b40 JD |
904 | } |
905 | ||
d960c369 MK |
906 | static int ath10k_htt_rx_nwifi_hdrlen(struct ieee80211_hdr *hdr) |
907 | { | |
908 | /* nwifi header is padded to 4 bytes. this fixes 4addr rx */ | |
909 | return round_up(ieee80211_hdrlen(hdr->frame_control), 4); | |
910 | } | |
911 | ||
f6dc2095 | 912 | static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt, |
85f6d7cf JD |
913 | struct ieee80211_rx_status *rx_status, |
914 | struct sk_buff *skb_in) | |
5e3dd157 | 915 | { |
7aa7a72a | 916 | struct ath10k *ar = htt->ar; |
5e3dd157 | 917 | struct htt_rx_desc *rxd; |
85f6d7cf | 918 | struct sk_buff *skb = skb_in; |
5e3dd157 | 919 | struct sk_buff *first; |
5e3dd157 KV |
920 | enum rx_msdu_decap_format fmt; |
921 | enum htt_rx_mpdu_encrypt_type enctype; | |
f6dc2095 | 922 | struct ieee80211_hdr *hdr; |
72bdeb86 | 923 | u8 hdr_buf[64], da[ETH_ALEN], sa[ETH_ALEN], *qos; |
5e3dd157 | 924 | unsigned int hdr_len; |
5e3dd157 KV |
925 | |
926 | rxd = (void *)skb->data - sizeof(*rxd); | |
5e3dd157 | 927 | enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), |
5b07e07f | 928 | RX_MPDU_START_INFO0_ENCRYPT_TYPE); |
5e3dd157 | 929 | |
f6dc2095 MK |
930 | hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status; |
931 | hdr_len = ieee80211_hdrlen(hdr->frame_control); | |
932 | memcpy(hdr_buf, hdr, hdr_len); | |
933 | hdr = (struct ieee80211_hdr *)hdr_buf; | |
5e3dd157 | 934 | |
5e3dd157 KV |
935 | first = skb; |
936 | while (skb) { | |
937 | void *decap_hdr; | |
f6dc2095 | 938 | int len; |
5e3dd157 KV |
939 | |
940 | rxd = (void *)skb->data - sizeof(*rxd); | |
941 | fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), | |
f6dc2095 | 942 | RX_MSDU_START_INFO1_DECAP_FORMAT); |
5e3dd157 KV |
943 | decap_hdr = (void *)rxd->rx_hdr_status; |
944 | ||
f6dc2095 | 945 | skb->ip_summed = ath10k_htt_rx_get_csum_state(skb); |
5e3dd157 | 946 | |
f6dc2095 MK |
947 | /* First frame in an A-MSDU chain has more decapped data. */ |
948 | if (skb == first) { | |
949 | len = round_up(ieee80211_hdrlen(hdr->frame_control), 4); | |
7aa7a72a MK |
950 | len += round_up(ath10k_htt_rx_crypto_param_len(ar, |
951 | enctype), 4); | |
f6dc2095 | 952 | decap_hdr += len; |
5e3dd157 KV |
953 | } |
954 | ||
f6dc2095 MK |
955 | switch (fmt) { |
956 | case RX_MSDU_DECAP_RAW: | |
e3fbf8d2 | 957 | /* remove trailing FCS */ |
f6dc2095 MK |
958 | skb_trim(skb, skb->len - FCS_LEN); |
959 | break; | |
960 | case RX_MSDU_DECAP_NATIVE_WIFI: | |
72bdeb86 | 961 | /* pull decapped header and copy SA & DA */ |
784f69d3 | 962 | hdr = (struct ieee80211_hdr *)skb->data; |
d960c369 | 963 | hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr); |
b25f32cb KV |
964 | ether_addr_copy(da, ieee80211_get_DA(hdr)); |
965 | ether_addr_copy(sa, ieee80211_get_SA(hdr)); | |
784f69d3 MK |
966 | skb_pull(skb, hdr_len); |
967 | ||
968 | /* push original 802.11 header */ | |
969 | hdr = (struct ieee80211_hdr *)hdr_buf; | |
970 | hdr_len = ieee80211_hdrlen(hdr->frame_control); | |
971 | memcpy(skb_push(skb, hdr_len), hdr, hdr_len); | |
972 | ||
973 | /* original A-MSDU header has the bit set but we're | |
974 | * not including A-MSDU subframe header */ | |
975 | hdr = (struct ieee80211_hdr *)skb->data; | |
976 | qos = ieee80211_get_qos_ctl(hdr); | |
977 | qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; | |
978 | ||
72bdeb86 MK |
979 | /* original 802.11 header has a different DA and in |
980 | * case of 4addr it may also have different SA | |
981 | */ | |
b25f32cb KV |
982 | ether_addr_copy(ieee80211_get_DA(hdr), da); |
983 | ether_addr_copy(ieee80211_get_SA(hdr), sa); | |
f6dc2095 MK |
984 | break; |
985 | case RX_MSDU_DECAP_ETHERNET2_DIX: | |
e3fbf8d2 MK |
986 | /* strip ethernet header and insert decapped 802.11 |
987 | * header, amsdu subframe header and rfc1042 header */ | |
988 | ||
f6dc2095 MK |
989 | len = 0; |
990 | len += sizeof(struct rfc1042_hdr); | |
991 | len += sizeof(struct amsdu_subframe_hdr); | |
992 | ||
993 | skb_pull(skb, sizeof(struct ethhdr)); | |
994 | memcpy(skb_push(skb, len), decap_hdr, len); | |
995 | memcpy(skb_push(skb, hdr_len), hdr, hdr_len); | |
996 | break; | |
997 | case RX_MSDU_DECAP_8023_SNAP_LLC: | |
e3fbf8d2 MK |
998 | /* insert decapped 802.11 header making a singly |
999 | * A-MSDU */ | |
f6dc2095 MK |
1000 | memcpy(skb_push(skb, hdr_len), hdr, hdr_len); |
1001 | break; | |
5e3dd157 KV |
1002 | } |
1003 | ||
85f6d7cf | 1004 | skb_in = skb; |
c071dcb2 MK |
1005 | ath10k_htt_rx_h_protected(htt, rx_status, skb_in, enctype, fmt, |
1006 | false); | |
5e3dd157 | 1007 | skb = skb->next; |
85f6d7cf | 1008 | skb_in->next = NULL; |
5e3dd157 | 1009 | |
652de35e | 1010 | if (skb) |
85f6d7cf | 1011 | rx_status->flag |= RX_FLAG_AMSDU_MORE; |
87326c97 | 1012 | else |
85f6d7cf | 1013 | rx_status->flag &= ~RX_FLAG_AMSDU_MORE; |
652de35e | 1014 | |
85f6d7cf | 1015 | ath10k_process_rx(htt->ar, rx_status, skb_in); |
f6dc2095 | 1016 | } |
5e3dd157 | 1017 | |
f6dc2095 MK |
1018 | /* FIXME: It might be nice to re-assemble the A-MSDU when there's a |
1019 | * monitor interface active for sniffing purposes. */ | |
5e3dd157 KV |
1020 | } |
1021 | ||
85f6d7cf JD |
1022 | static void ath10k_htt_rx_msdu(struct ath10k_htt *htt, |
1023 | struct ieee80211_rx_status *rx_status, | |
1024 | struct sk_buff *skb) | |
5e3dd157 | 1025 | { |
7aa7a72a | 1026 | struct ath10k *ar = htt->ar; |
5e3dd157 KV |
1027 | struct htt_rx_desc *rxd; |
1028 | struct ieee80211_hdr *hdr; | |
1029 | enum rx_msdu_decap_format fmt; | |
1030 | enum htt_rx_mpdu_encrypt_type enctype; | |
e3fbf8d2 MK |
1031 | int hdr_len; |
1032 | void *rfc1042; | |
5e3dd157 KV |
1033 | |
1034 | /* This shouldn't happen. If it does than it may be a FW bug. */ | |
1035 | if (skb->next) { | |
7aa7a72a | 1036 | ath10k_warn(ar, "htt rx received chained non A-MSDU frame\n"); |
5e3dd157 KV |
1037 | ath10k_htt_rx_free_msdu_chain(skb->next); |
1038 | skb->next = NULL; | |
1039 | } | |
1040 | ||
1041 | rxd = (void *)skb->data - sizeof(*rxd); | |
1042 | fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), | |
5b07e07f | 1043 | RX_MSDU_START_INFO1_DECAP_FORMAT); |
5e3dd157 | 1044 | enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), |
5b07e07f | 1045 | RX_MPDU_START_INFO0_ENCRYPT_TYPE); |
e3fbf8d2 MK |
1046 | hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status; |
1047 | hdr_len = ieee80211_hdrlen(hdr->frame_control); | |
5e3dd157 | 1048 | |
f6dc2095 MK |
1049 | skb->ip_summed = ath10k_htt_rx_get_csum_state(skb); |
1050 | ||
5e3dd157 KV |
1051 | switch (fmt) { |
1052 | case RX_MSDU_DECAP_RAW: | |
1053 | /* remove trailing FCS */ | |
e3fbf8d2 | 1054 | skb_trim(skb, skb->len - FCS_LEN); |
5e3dd157 KV |
1055 | break; |
1056 | case RX_MSDU_DECAP_NATIVE_WIFI: | |
784f69d3 MK |
1057 | /* Pull decapped header */ |
1058 | hdr = (struct ieee80211_hdr *)skb->data; | |
d960c369 | 1059 | hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr); |
784f69d3 MK |
1060 | skb_pull(skb, hdr_len); |
1061 | ||
1062 | /* Push original header */ | |
1063 | hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status; | |
1064 | hdr_len = ieee80211_hdrlen(hdr->frame_control); | |
1065 | memcpy(skb_push(skb, hdr_len), hdr, hdr_len); | |
5e3dd157 KV |
1066 | break; |
1067 | case RX_MSDU_DECAP_ETHERNET2_DIX: | |
e3fbf8d2 MK |
1068 | /* strip ethernet header and insert decapped 802.11 header and |
1069 | * rfc1042 header */ | |
5e3dd157 | 1070 | |
e3fbf8d2 MK |
1071 | rfc1042 = hdr; |
1072 | rfc1042 += roundup(hdr_len, 4); | |
7aa7a72a MK |
1073 | rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(ar, |
1074 | enctype), 4); | |
5e3dd157 | 1075 | |
e3fbf8d2 MK |
1076 | skb_pull(skb, sizeof(struct ethhdr)); |
1077 | memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)), | |
1078 | rfc1042, sizeof(struct rfc1042_hdr)); | |
1079 | memcpy(skb_push(skb, hdr_len), hdr, hdr_len); | |
1080 | break; | |
1081 | case RX_MSDU_DECAP_8023_SNAP_LLC: | |
1082 | /* remove A-MSDU subframe header and insert | |
1083 | * decapped 802.11 header. rfc1042 header is already there */ | |
5e3dd157 | 1084 | |
e3fbf8d2 MK |
1085 | skb_pull(skb, sizeof(struct amsdu_subframe_hdr)); |
1086 | memcpy(skb_push(skb, hdr_len), hdr, hdr_len); | |
1087 | break; | |
5e3dd157 KV |
1088 | } |
1089 | ||
c071dcb2 | 1090 | ath10k_htt_rx_h_protected(htt, rx_status, skb, enctype, fmt, false); |
f6dc2095 | 1091 | |
85f6d7cf | 1092 | ath10k_process_rx(htt->ar, rx_status, skb); |
5e3dd157 KV |
1093 | } |
1094 | ||
605f81aa MK |
1095 | static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb) |
1096 | { | |
1097 | struct htt_rx_desc *rxd; | |
1098 | u32 flags, info; | |
1099 | bool is_ip4, is_ip6; | |
1100 | bool is_tcp, is_udp; | |
1101 | bool ip_csum_ok, tcpudp_csum_ok; | |
1102 | ||
1103 | rxd = (void *)skb->data - sizeof(*rxd); | |
1104 | flags = __le32_to_cpu(rxd->attention.flags); | |
1105 | info = __le32_to_cpu(rxd->msdu_start.info1); | |
1106 | ||
1107 | is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO); | |
1108 | is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO); | |
1109 | is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO); | |
1110 | is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO); | |
1111 | ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL); | |
1112 | tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL); | |
1113 | ||
1114 | if (!is_ip4 && !is_ip6) | |
1115 | return CHECKSUM_NONE; | |
1116 | if (!is_tcp && !is_udp) | |
1117 | return CHECKSUM_NONE; | |
1118 | if (!ip_csum_ok) | |
1119 | return CHECKSUM_NONE; | |
1120 | if (!tcpudp_csum_ok) | |
1121 | return CHECKSUM_NONE; | |
1122 | ||
1123 | return CHECKSUM_UNNECESSARY; | |
1124 | } | |
1125 | ||
bfa35368 BG |
1126 | static int ath10k_unchain_msdu(struct sk_buff *msdu_head) |
1127 | { | |
1128 | struct sk_buff *next = msdu_head->next; | |
1129 | struct sk_buff *to_free = next; | |
1130 | int space; | |
1131 | int total_len = 0; | |
1132 | ||
1133 | /* TODO: Might could optimize this by using | |
1134 | * skb_try_coalesce or similar method to | |
1135 | * decrease copying, or maybe get mac80211 to | |
1136 | * provide a way to just receive a list of | |
1137 | * skb? | |
1138 | */ | |
1139 | ||
1140 | msdu_head->next = NULL; | |
1141 | ||
1142 | /* Allocate total length all at once. */ | |
1143 | while (next) { | |
1144 | total_len += next->len; | |
1145 | next = next->next; | |
1146 | } | |
1147 | ||
1148 | space = total_len - skb_tailroom(msdu_head); | |
1149 | if ((space > 0) && | |
1150 | (pskb_expand_head(msdu_head, 0, space, GFP_ATOMIC) < 0)) { | |
1151 | /* TODO: bump some rx-oom error stat */ | |
1152 | /* put it back together so we can free the | |
1153 | * whole list at once. | |
1154 | */ | |
1155 | msdu_head->next = to_free; | |
1156 | return -1; | |
1157 | } | |
1158 | ||
1159 | /* Walk list again, copying contents into | |
1160 | * msdu_head | |
1161 | */ | |
1162 | next = to_free; | |
1163 | while (next) { | |
1164 | skb_copy_from_linear_data(next, skb_put(msdu_head, next->len), | |
1165 | next->len); | |
1166 | next = next->next; | |
1167 | } | |
1168 | ||
1169 | /* If here, we have consolidated skb. Free the | |
1170 | * fragments and pass the main skb on up the | |
1171 | * stack. | |
1172 | */ | |
1173 | ath10k_htt_rx_free_msdu_chain(to_free); | |
1174 | return 0; | |
1175 | } | |
1176 | ||
2acc4eb2 JD |
1177 | static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt, |
1178 | struct sk_buff *head, | |
87326c97 | 1179 | enum htt_rx_mpdu_status status, |
78433f96 JD |
1180 | bool channel_set, |
1181 | u32 attention) | |
2acc4eb2 | 1182 | { |
7aa7a72a MK |
1183 | struct ath10k *ar = htt->ar; |
1184 | ||
2acc4eb2 | 1185 | if (head->len == 0) { |
7aa7a72a | 1186 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
2acc4eb2 JD |
1187 | "htt rx dropping due to zero-len\n"); |
1188 | return false; | |
1189 | } | |
1190 | ||
78433f96 | 1191 | if (attention & RX_ATTENTION_FLAGS_DECRYPT_ERR) { |
7aa7a72a | 1192 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
2acc4eb2 JD |
1193 | "htt rx dropping due to decrypt-err\n"); |
1194 | return false; | |
1195 | } | |
1196 | ||
36653f05 | 1197 | if (!channel_set) { |
7aa7a72a | 1198 | ath10k_warn(ar, "no channel configured; ignoring frame!\n"); |
36653f05 JD |
1199 | return false; |
1200 | } | |
1201 | ||
2acc4eb2 JD |
1202 | /* Skip mgmt frames while we handle this in WMI */ |
1203 | if (status == HTT_RX_IND_MPDU_STATUS_MGMT_CTRL || | |
78433f96 | 1204 | attention & RX_ATTENTION_FLAGS_MGMT_TYPE) { |
7aa7a72a | 1205 | ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx mgmt ctrl\n"); |
2acc4eb2 JD |
1206 | return false; |
1207 | } | |
1208 | ||
1209 | if (status != HTT_RX_IND_MPDU_STATUS_OK && | |
1210 | status != HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR && | |
1211 | status != HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER && | |
1bbc0975 | 1212 | !htt->ar->monitor_started) { |
7aa7a72a | 1213 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
2acc4eb2 JD |
1214 | "htt rx ignoring frame w/ status %d\n", |
1215 | status); | |
1216 | return false; | |
1217 | } | |
1218 | ||
1219 | if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) { | |
7aa7a72a | 1220 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
2acc4eb2 JD |
1221 | "htt rx CAC running\n"); |
1222 | return false; | |
1223 | } | |
1224 | ||
1225 | return true; | |
1226 | } | |
1227 | ||
5e3dd157 KV |
1228 | static void ath10k_htt_rx_handler(struct ath10k_htt *htt, |
1229 | struct htt_rx_indication *rx) | |
1230 | { | |
7aa7a72a | 1231 | struct ath10k *ar = htt->ar; |
6df92a3d | 1232 | struct ieee80211_rx_status *rx_status = &htt->rx_status; |
5e3dd157 | 1233 | struct htt_rx_indication_mpdu_range *mpdu_ranges; |
78433f96 | 1234 | struct htt_rx_desc *rxd; |
87326c97 | 1235 | enum htt_rx_mpdu_status status; |
5e3dd157 KV |
1236 | struct ieee80211_hdr *hdr; |
1237 | int num_mpdu_ranges; | |
78433f96 | 1238 | u32 attention; |
5e3dd157 KV |
1239 | int fw_desc_len; |
1240 | u8 *fw_desc; | |
78433f96 | 1241 | bool channel_set; |
5e3dd157 | 1242 | int i, j; |
d84dd60f | 1243 | int ret; |
5e3dd157 | 1244 | |
45967089 MK |
1245 | lockdep_assert_held(&htt->rx_ring.lock); |
1246 | ||
5e3dd157 KV |
1247 | fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes); |
1248 | fw_desc = (u8 *)&rx->fw_desc; | |
1249 | ||
1250 | num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1), | |
1251 | HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES); | |
1252 | mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx); | |
1253 | ||
e8dc1a96 | 1254 | /* Fill this once, while this is per-ppdu */ |
2289188c JD |
1255 | if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_START_VALID) { |
1256 | memset(rx_status, 0, sizeof(*rx_status)); | |
1257 | rx_status->signal = ATH10K_DEFAULT_NOISE_FLOOR + | |
1258 | rx->ppdu.combined_rssi; | |
1259 | } | |
87326c97 JD |
1260 | |
1261 | if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_END_VALID) { | |
1262 | /* TSF available only in 32-bit */ | |
6df92a3d JD |
1263 | rx_status->mactime = __le32_to_cpu(rx->ppdu.tsf) & 0xffffffff; |
1264 | rx_status->flag |= RX_FLAG_MACTIME_END; | |
87326c97 | 1265 | } |
e8dc1a96 | 1266 | |
6df92a3d | 1267 | channel_set = ath10k_htt_rx_h_channel(htt->ar, rx_status); |
36653f05 | 1268 | |
87326c97 | 1269 | if (channel_set) { |
6df92a3d | 1270 | ath10k_htt_rx_h_rates(htt->ar, rx_status->band, |
87326c97 JD |
1271 | rx->ppdu.info0, |
1272 | __le32_to_cpu(rx->ppdu.info1), | |
1273 | __le32_to_cpu(rx->ppdu.info2), | |
6df92a3d | 1274 | rx_status); |
87326c97 | 1275 | } |
e8dc1a96 | 1276 | |
7aa7a72a | 1277 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ", |
5e3dd157 KV |
1278 | rx, sizeof(*rx) + |
1279 | (sizeof(struct htt_rx_indication_mpdu_range) * | |
1280 | num_mpdu_ranges)); | |
1281 | ||
1282 | for (i = 0; i < num_mpdu_ranges; i++) { | |
87326c97 | 1283 | status = mpdu_ranges[i].mpdu_range_status; |
5e3dd157 KV |
1284 | |
1285 | for (j = 0; j < mpdu_ranges[i].mpdu_count; j++) { | |
1286 | struct sk_buff *msdu_head, *msdu_tail; | |
5e3dd157 | 1287 | |
0ccb7a34 | 1288 | attention = 0; |
5e3dd157 KV |
1289 | msdu_head = NULL; |
1290 | msdu_tail = NULL; | |
d84dd60f JD |
1291 | ret = ath10k_htt_rx_amsdu_pop(htt, |
1292 | &fw_desc, | |
1293 | &fw_desc_len, | |
1294 | &msdu_head, | |
0ccb7a34 JD |
1295 | &msdu_tail, |
1296 | &attention); | |
d84dd60f JD |
1297 | |
1298 | if (ret < 0) { | |
7aa7a72a | 1299 | ath10k_warn(ar, "failed to pop amsdu from htt rx ring %d\n", |
d84dd60f JD |
1300 | ret); |
1301 | ath10k_htt_rx_free_msdu_chain(msdu_head); | |
1302 | continue; | |
1303 | } | |
5e3dd157 | 1304 | |
78433f96 JD |
1305 | rxd = container_of((void *)msdu_head->data, |
1306 | struct htt_rx_desc, | |
1307 | msdu_payload); | |
78433f96 | 1308 | |
2acc4eb2 | 1309 | if (!ath10k_htt_rx_amsdu_allowed(htt, msdu_head, |
87326c97 | 1310 | status, |
78433f96 JD |
1311 | channel_set, |
1312 | attention)) { | |
e8a50f8b MP |
1313 | ath10k_htt_rx_free_msdu_chain(msdu_head); |
1314 | continue; | |
1315 | } | |
1316 | ||
d84dd60f JD |
1317 | if (ret > 0 && |
1318 | ath10k_unchain_msdu(msdu_head) < 0) { | |
5e3dd157 KV |
1319 | ath10k_htt_rx_free_msdu_chain(msdu_head); |
1320 | continue; | |
1321 | } | |
1322 | ||
78433f96 | 1323 | if (attention & RX_ATTENTION_FLAGS_FCS_ERR) |
6df92a3d | 1324 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; |
87326c97 | 1325 | else |
6df92a3d | 1326 | rx_status->flag &= ~RX_FLAG_FAILED_FCS_CRC; |
87326c97 | 1327 | |
78433f96 | 1328 | if (attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR) |
6df92a3d | 1329 | rx_status->flag |= RX_FLAG_MMIC_ERROR; |
87326c97 | 1330 | else |
6df92a3d | 1331 | rx_status->flag &= ~RX_FLAG_MMIC_ERROR; |
87326c97 | 1332 | |
5e3dd157 KV |
1333 | hdr = ath10k_htt_rx_skb_get_hdr(msdu_head); |
1334 | ||
1335 | if (ath10k_htt_rx_hdr_is_amsdu(hdr)) | |
6df92a3d | 1336 | ath10k_htt_rx_amsdu(htt, rx_status, msdu_head); |
5e3dd157 | 1337 | else |
6df92a3d | 1338 | ath10k_htt_rx_msdu(htt, rx_status, msdu_head); |
5e3dd157 KV |
1339 | } |
1340 | } | |
1341 | ||
6e712d42 | 1342 | tasklet_schedule(&htt->rx_replenish_task); |
5e3dd157 KV |
1343 | } |
1344 | ||
1345 | static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt, | |
5b07e07f | 1346 | struct htt_rx_fragment_indication *frag) |
5e3dd157 | 1347 | { |
7aa7a72a | 1348 | struct ath10k *ar = htt->ar; |
5e3dd157 | 1349 | struct sk_buff *msdu_head, *msdu_tail; |
87326c97 | 1350 | enum htt_rx_mpdu_encrypt_type enctype; |
5e3dd157 KV |
1351 | struct htt_rx_desc *rxd; |
1352 | enum rx_msdu_decap_format fmt; | |
6df92a3d | 1353 | struct ieee80211_rx_status *rx_status = &htt->rx_status; |
5e3dd157 | 1354 | struct ieee80211_hdr *hdr; |
d84dd60f | 1355 | int ret; |
5e3dd157 KV |
1356 | bool tkip_mic_err; |
1357 | bool decrypt_err; | |
1358 | u8 *fw_desc; | |
1359 | int fw_desc_len, hdrlen, paramlen; | |
1360 | int trim; | |
0ccb7a34 | 1361 | u32 attention = 0; |
5e3dd157 KV |
1362 | |
1363 | fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes); | |
1364 | fw_desc = (u8 *)frag->fw_msdu_rx_desc; | |
1365 | ||
1366 | msdu_head = NULL; | |
1367 | msdu_tail = NULL; | |
45967089 MK |
1368 | |
1369 | spin_lock_bh(&htt->rx_ring.lock); | |
d84dd60f | 1370 | ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len, |
0ccb7a34 JD |
1371 | &msdu_head, &msdu_tail, |
1372 | &attention); | |
45967089 | 1373 | spin_unlock_bh(&htt->rx_ring.lock); |
5e3dd157 | 1374 | |
7aa7a72a | 1375 | ath10k_dbg(ar, ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n"); |
5e3dd157 | 1376 | |
d84dd60f | 1377 | if (ret) { |
7aa7a72a | 1378 | ath10k_warn(ar, "failed to pop amsdu from httr rx ring for fragmented rx %d\n", |
d84dd60f | 1379 | ret); |
5e3dd157 KV |
1380 | ath10k_htt_rx_free_msdu_chain(msdu_head); |
1381 | return; | |
1382 | } | |
1383 | ||
1384 | /* FIXME: implement signal strength */ | |
4b81d177 | 1385 | rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; |
5e3dd157 KV |
1386 | |
1387 | hdr = (struct ieee80211_hdr *)msdu_head->data; | |
1388 | rxd = (void *)msdu_head->data - sizeof(*rxd); | |
0ccb7a34 JD |
1389 | tkip_mic_err = !!(attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR); |
1390 | decrypt_err = !!(attention & RX_ATTENTION_FLAGS_DECRYPT_ERR); | |
5e3dd157 | 1391 | fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), |
5b07e07f | 1392 | RX_MSDU_START_INFO1_DECAP_FORMAT); |
5e3dd157 KV |
1393 | |
1394 | if (fmt != RX_MSDU_DECAP_RAW) { | |
7aa7a72a | 1395 | ath10k_warn(ar, "we dont support non-raw fragmented rx yet\n"); |
5e3dd157 KV |
1396 | dev_kfree_skb_any(msdu_head); |
1397 | goto end; | |
1398 | } | |
1399 | ||
87326c97 JD |
1400 | enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), |
1401 | RX_MPDU_START_INFO0_ENCRYPT_TYPE); | |
c071dcb2 MK |
1402 | ath10k_htt_rx_h_protected(htt, rx_status, msdu_head, enctype, fmt, |
1403 | true); | |
85f6d7cf | 1404 | msdu_head->ip_summed = ath10k_htt_rx_get_csum_state(msdu_head); |
5e3dd157 | 1405 | |
87326c97 | 1406 | if (tkip_mic_err) |
7aa7a72a | 1407 | ath10k_warn(ar, "tkip mic error\n"); |
5e3dd157 KV |
1408 | |
1409 | if (decrypt_err) { | |
7aa7a72a | 1410 | ath10k_warn(ar, "decryption err in fragmented rx\n"); |
85f6d7cf | 1411 | dev_kfree_skb_any(msdu_head); |
5e3dd157 KV |
1412 | goto end; |
1413 | } | |
1414 | ||
87326c97 | 1415 | if (enctype != HTT_RX_MPDU_ENCRYPT_NONE) { |
5e3dd157 | 1416 | hdrlen = ieee80211_hdrlen(hdr->frame_control); |
7aa7a72a | 1417 | paramlen = ath10k_htt_rx_crypto_param_len(ar, enctype); |
5e3dd157 KV |
1418 | |
1419 | /* It is more efficient to move the header than the payload */ | |
85f6d7cf JD |
1420 | memmove((void *)msdu_head->data + paramlen, |
1421 | (void *)msdu_head->data, | |
5e3dd157 | 1422 | hdrlen); |
85f6d7cf JD |
1423 | skb_pull(msdu_head, paramlen); |
1424 | hdr = (struct ieee80211_hdr *)msdu_head->data; | |
5e3dd157 KV |
1425 | } |
1426 | ||
1427 | /* remove trailing FCS */ | |
1428 | trim = 4; | |
1429 | ||
1430 | /* remove crypto trailer */ | |
7aa7a72a | 1431 | trim += ath10k_htt_rx_crypto_tail_len(ar, enctype); |
5e3dd157 KV |
1432 | |
1433 | /* last fragment of TKIP frags has MIC */ | |
1434 | if (!ieee80211_has_morefrags(hdr->frame_control) && | |
87326c97 | 1435 | enctype == HTT_RX_MPDU_ENCRYPT_TKIP_WPA) |
5e3dd157 KV |
1436 | trim += 8; |
1437 | ||
85f6d7cf | 1438 | if (trim > msdu_head->len) { |
7aa7a72a | 1439 | ath10k_warn(ar, "htt rx fragment: trailer longer than the frame itself? drop\n"); |
85f6d7cf | 1440 | dev_kfree_skb_any(msdu_head); |
5e3dd157 KV |
1441 | goto end; |
1442 | } | |
1443 | ||
85f6d7cf | 1444 | skb_trim(msdu_head, msdu_head->len - trim); |
5e3dd157 | 1445 | |
7aa7a72a | 1446 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ", |
85f6d7cf | 1447 | msdu_head->data, msdu_head->len); |
6df92a3d | 1448 | ath10k_process_rx(htt->ar, rx_status, msdu_head); |
5e3dd157 KV |
1449 | |
1450 | end: | |
1451 | if (fw_desc_len > 0) { | |
7aa7a72a | 1452 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
5e3dd157 KV |
1453 | "expecting more fragmented rx in one indication %d\n", |
1454 | fw_desc_len); | |
1455 | } | |
1456 | } | |
1457 | ||
6c5151a9 MK |
1458 | static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar, |
1459 | struct sk_buff *skb) | |
1460 | { | |
1461 | struct ath10k_htt *htt = &ar->htt; | |
1462 | struct htt_resp *resp = (struct htt_resp *)skb->data; | |
1463 | struct htt_tx_done tx_done = {}; | |
1464 | int status = MS(resp->data_tx_completion.flags, HTT_DATA_TX_STATUS); | |
1465 | __le16 msdu_id; | |
1466 | int i; | |
1467 | ||
45967089 MK |
1468 | lockdep_assert_held(&htt->tx_lock); |
1469 | ||
6c5151a9 MK |
1470 | switch (status) { |
1471 | case HTT_DATA_TX_STATUS_NO_ACK: | |
1472 | tx_done.no_ack = true; | |
1473 | break; | |
1474 | case HTT_DATA_TX_STATUS_OK: | |
1475 | break; | |
1476 | case HTT_DATA_TX_STATUS_DISCARD: | |
1477 | case HTT_DATA_TX_STATUS_POSTPONE: | |
1478 | case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL: | |
1479 | tx_done.discard = true; | |
1480 | break; | |
1481 | default: | |
7aa7a72a | 1482 | ath10k_warn(ar, "unhandled tx completion status %d\n", status); |
6c5151a9 MK |
1483 | tx_done.discard = true; |
1484 | break; | |
1485 | } | |
1486 | ||
7aa7a72a | 1487 | ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n", |
6c5151a9 MK |
1488 | resp->data_tx_completion.num_msdus); |
1489 | ||
1490 | for (i = 0; i < resp->data_tx_completion.num_msdus; i++) { | |
1491 | msdu_id = resp->data_tx_completion.msdus[i]; | |
1492 | tx_done.msdu_id = __le16_to_cpu(msdu_id); | |
1493 | ath10k_txrx_tx_unref(htt, &tx_done); | |
1494 | } | |
1495 | } | |
1496 | ||
aa5b4fbc MK |
1497 | static void ath10k_htt_rx_addba(struct ath10k *ar, struct htt_resp *resp) |
1498 | { | |
1499 | struct htt_rx_addba *ev = &resp->rx_addba; | |
1500 | struct ath10k_peer *peer; | |
1501 | struct ath10k_vif *arvif; | |
1502 | u16 info0, tid, peer_id; | |
1503 | ||
1504 | info0 = __le16_to_cpu(ev->info0); | |
1505 | tid = MS(info0, HTT_RX_BA_INFO0_TID); | |
1506 | peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID); | |
1507 | ||
7aa7a72a | 1508 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
aa5b4fbc MK |
1509 | "htt rx addba tid %hu peer_id %hu size %hhu\n", |
1510 | tid, peer_id, ev->window_size); | |
1511 | ||
1512 | spin_lock_bh(&ar->data_lock); | |
1513 | peer = ath10k_peer_find_by_id(ar, peer_id); | |
1514 | if (!peer) { | |
7aa7a72a | 1515 | ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n", |
aa5b4fbc MK |
1516 | peer_id); |
1517 | spin_unlock_bh(&ar->data_lock); | |
1518 | return; | |
1519 | } | |
1520 | ||
1521 | arvif = ath10k_get_arvif(ar, peer->vdev_id); | |
1522 | if (!arvif) { | |
7aa7a72a | 1523 | ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n", |
aa5b4fbc MK |
1524 | peer->vdev_id); |
1525 | spin_unlock_bh(&ar->data_lock); | |
1526 | return; | |
1527 | } | |
1528 | ||
7aa7a72a | 1529 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
aa5b4fbc MK |
1530 | "htt rx start rx ba session sta %pM tid %hu size %hhu\n", |
1531 | peer->addr, tid, ev->window_size); | |
1532 | ||
1533 | ieee80211_start_rx_ba_session_offl(arvif->vif, peer->addr, tid); | |
1534 | spin_unlock_bh(&ar->data_lock); | |
1535 | } | |
1536 | ||
1537 | static void ath10k_htt_rx_delba(struct ath10k *ar, struct htt_resp *resp) | |
1538 | { | |
1539 | struct htt_rx_delba *ev = &resp->rx_delba; | |
1540 | struct ath10k_peer *peer; | |
1541 | struct ath10k_vif *arvif; | |
1542 | u16 info0, tid, peer_id; | |
1543 | ||
1544 | info0 = __le16_to_cpu(ev->info0); | |
1545 | tid = MS(info0, HTT_RX_BA_INFO0_TID); | |
1546 | peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID); | |
1547 | ||
7aa7a72a | 1548 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
aa5b4fbc MK |
1549 | "htt rx delba tid %hu peer_id %hu\n", |
1550 | tid, peer_id); | |
1551 | ||
1552 | spin_lock_bh(&ar->data_lock); | |
1553 | peer = ath10k_peer_find_by_id(ar, peer_id); | |
1554 | if (!peer) { | |
7aa7a72a | 1555 | ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n", |
aa5b4fbc MK |
1556 | peer_id); |
1557 | spin_unlock_bh(&ar->data_lock); | |
1558 | return; | |
1559 | } | |
1560 | ||
1561 | arvif = ath10k_get_arvif(ar, peer->vdev_id); | |
1562 | if (!arvif) { | |
7aa7a72a | 1563 | ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n", |
aa5b4fbc MK |
1564 | peer->vdev_id); |
1565 | spin_unlock_bh(&ar->data_lock); | |
1566 | return; | |
1567 | } | |
1568 | ||
7aa7a72a | 1569 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
aa5b4fbc MK |
1570 | "htt rx stop rx ba session sta %pM tid %hu\n", |
1571 | peer->addr, tid); | |
1572 | ||
1573 | ieee80211_stop_rx_ba_session_offl(arvif->vif, peer->addr, tid); | |
1574 | spin_unlock_bh(&ar->data_lock); | |
1575 | } | |
1576 | ||
5e3dd157 KV |
1577 | void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb) |
1578 | { | |
edb8236d | 1579 | struct ath10k_htt *htt = &ar->htt; |
5e3dd157 KV |
1580 | struct htt_resp *resp = (struct htt_resp *)skb->data; |
1581 | ||
1582 | /* confirm alignment */ | |
1583 | if (!IS_ALIGNED((unsigned long)skb->data, 4)) | |
7aa7a72a | 1584 | ath10k_warn(ar, "unaligned htt message, expect trouble\n"); |
5e3dd157 | 1585 | |
7aa7a72a | 1586 | ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n", |
5e3dd157 KV |
1587 | resp->hdr.msg_type); |
1588 | switch (resp->hdr.msg_type) { | |
1589 | case HTT_T2H_MSG_TYPE_VERSION_CONF: { | |
1590 | htt->target_version_major = resp->ver_resp.major; | |
1591 | htt->target_version_minor = resp->ver_resp.minor; | |
1592 | complete(&htt->target_version_received); | |
1593 | break; | |
1594 | } | |
6c5151a9 | 1595 | case HTT_T2H_MSG_TYPE_RX_IND: |
45967089 MK |
1596 | spin_lock_bh(&htt->rx_ring.lock); |
1597 | __skb_queue_tail(&htt->rx_compl_q, skb); | |
1598 | spin_unlock_bh(&htt->rx_ring.lock); | |
6c5151a9 MK |
1599 | tasklet_schedule(&htt->txrx_compl_task); |
1600 | return; | |
5e3dd157 KV |
1601 | case HTT_T2H_MSG_TYPE_PEER_MAP: { |
1602 | struct htt_peer_map_event ev = { | |
1603 | .vdev_id = resp->peer_map.vdev_id, | |
1604 | .peer_id = __le16_to_cpu(resp->peer_map.peer_id), | |
1605 | }; | |
1606 | memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr)); | |
1607 | ath10k_peer_map_event(htt, &ev); | |
1608 | break; | |
1609 | } | |
1610 | case HTT_T2H_MSG_TYPE_PEER_UNMAP: { | |
1611 | struct htt_peer_unmap_event ev = { | |
1612 | .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id), | |
1613 | }; | |
1614 | ath10k_peer_unmap_event(htt, &ev); | |
1615 | break; | |
1616 | } | |
1617 | case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: { | |
1618 | struct htt_tx_done tx_done = {}; | |
1619 | int status = __le32_to_cpu(resp->mgmt_tx_completion.status); | |
1620 | ||
1621 | tx_done.msdu_id = | |
1622 | __le32_to_cpu(resp->mgmt_tx_completion.desc_id); | |
1623 | ||
1624 | switch (status) { | |
1625 | case HTT_MGMT_TX_STATUS_OK: | |
1626 | break; | |
1627 | case HTT_MGMT_TX_STATUS_RETRY: | |
1628 | tx_done.no_ack = true; | |
1629 | break; | |
1630 | case HTT_MGMT_TX_STATUS_DROP: | |
1631 | tx_done.discard = true; | |
1632 | break; | |
1633 | } | |
1634 | ||
6c5151a9 | 1635 | spin_lock_bh(&htt->tx_lock); |
0a89f8a0 | 1636 | ath10k_txrx_tx_unref(htt, &tx_done); |
6c5151a9 | 1637 | spin_unlock_bh(&htt->tx_lock); |
5e3dd157 KV |
1638 | break; |
1639 | } | |
6c5151a9 MK |
1640 | case HTT_T2H_MSG_TYPE_TX_COMPL_IND: |
1641 | spin_lock_bh(&htt->tx_lock); | |
1642 | __skb_queue_tail(&htt->tx_compl_q, skb); | |
1643 | spin_unlock_bh(&htt->tx_lock); | |
1644 | tasklet_schedule(&htt->txrx_compl_task); | |
1645 | return; | |
5e3dd157 KV |
1646 | case HTT_T2H_MSG_TYPE_SEC_IND: { |
1647 | struct ath10k *ar = htt->ar; | |
1648 | struct htt_security_indication *ev = &resp->security_indication; | |
1649 | ||
7aa7a72a | 1650 | ath10k_dbg(ar, ATH10K_DBG_HTT, |
5e3dd157 KV |
1651 | "sec ind peer_id %d unicast %d type %d\n", |
1652 | __le16_to_cpu(ev->peer_id), | |
1653 | !!(ev->flags & HTT_SECURITY_IS_UNICAST), | |
1654 | MS(ev->flags, HTT_SECURITY_TYPE)); | |
1655 | complete(&ar->install_key_done); | |
1656 | break; | |
1657 | } | |
1658 | case HTT_T2H_MSG_TYPE_RX_FRAG_IND: { | |
7aa7a72a | 1659 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ", |
5e3dd157 KV |
1660 | skb->data, skb->len); |
1661 | ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind); | |
1662 | break; | |
1663 | } | |
1664 | case HTT_T2H_MSG_TYPE_TEST: | |
1665 | /* FIX THIS */ | |
1666 | break; | |
5e3dd157 | 1667 | case HTT_T2H_MSG_TYPE_STATS_CONF: |
d35a6c18 | 1668 | trace_ath10k_htt_stats(ar, skb->data, skb->len); |
a9bf0506 KV |
1669 | break; |
1670 | case HTT_T2H_MSG_TYPE_TX_INSPECT_IND: | |
708b9bde MK |
1671 | /* Firmware can return tx frames if it's unable to fully |
1672 | * process them and suspects host may be able to fix it. ath10k | |
1673 | * sends all tx frames as already inspected so this shouldn't | |
1674 | * happen unless fw has a bug. | |
1675 | */ | |
7aa7a72a | 1676 | ath10k_warn(ar, "received an unexpected htt tx inspect event\n"); |
708b9bde | 1677 | break; |
5e3dd157 | 1678 | case HTT_T2H_MSG_TYPE_RX_ADDBA: |
aa5b4fbc MK |
1679 | ath10k_htt_rx_addba(ar, resp); |
1680 | break; | |
5e3dd157 | 1681 | case HTT_T2H_MSG_TYPE_RX_DELBA: |
aa5b4fbc MK |
1682 | ath10k_htt_rx_delba(ar, resp); |
1683 | break; | |
bfdd7937 RM |
1684 | case HTT_T2H_MSG_TYPE_PKTLOG: { |
1685 | struct ath10k_pktlog_hdr *hdr = | |
1686 | (struct ath10k_pktlog_hdr *)resp->pktlog_msg.payload; | |
1687 | ||
1688 | trace_ath10k_htt_pktlog(ar, resp->pktlog_msg.payload, | |
1689 | sizeof(*hdr) + | |
1690 | __le16_to_cpu(hdr->size)); | |
1691 | break; | |
1692 | } | |
aa5b4fbc MK |
1693 | case HTT_T2H_MSG_TYPE_RX_FLUSH: { |
1694 | /* Ignore this event because mac80211 takes care of Rx | |
1695 | * aggregation reordering. | |
1696 | */ | |
1697 | break; | |
1698 | } | |
5e3dd157 | 1699 | default: |
2358a544 MK |
1700 | ath10k_warn(ar, "htt event (%d) not handled\n", |
1701 | resp->hdr.msg_type); | |
7aa7a72a | 1702 | ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ", |
5e3dd157 KV |
1703 | skb->data, skb->len); |
1704 | break; | |
1705 | }; | |
1706 | ||
1707 | /* Free the indication buffer */ | |
1708 | dev_kfree_skb_any(skb); | |
1709 | } | |
6c5151a9 MK |
1710 | |
1711 | static void ath10k_htt_txrx_compl_task(unsigned long ptr) | |
1712 | { | |
1713 | struct ath10k_htt *htt = (struct ath10k_htt *)ptr; | |
1714 | struct htt_resp *resp; | |
1715 | struct sk_buff *skb; | |
1716 | ||
45967089 MK |
1717 | spin_lock_bh(&htt->tx_lock); |
1718 | while ((skb = __skb_dequeue(&htt->tx_compl_q))) { | |
6c5151a9 MK |
1719 | ath10k_htt_rx_frm_tx_compl(htt->ar, skb); |
1720 | dev_kfree_skb_any(skb); | |
1721 | } | |
45967089 | 1722 | spin_unlock_bh(&htt->tx_lock); |
6c5151a9 | 1723 | |
45967089 MK |
1724 | spin_lock_bh(&htt->rx_ring.lock); |
1725 | while ((skb = __skb_dequeue(&htt->rx_compl_q))) { | |
6c5151a9 MK |
1726 | resp = (struct htt_resp *)skb->data; |
1727 | ath10k_htt_rx_handler(htt, &resp->rx_ind); | |
1728 | dev_kfree_skb_any(skb); | |
1729 | } | |
45967089 | 1730 | spin_unlock_bh(&htt->rx_ring.lock); |
6c5151a9 | 1731 | } |