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Merge tag 'ath-next-20240130' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath
[linux-2.6-block.git] / drivers / net / wireless / ath / ath10k / core.c
CommitLineData
f0553ca9 1// SPDX-License-Identifier: ISC
5e3dd157
KV		 2/*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
8b1083d6 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
fe36e70f 5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
bc2ef649 6 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5e3dd157
KV		 7 */
8
9#include <linux/module.h>
10#include <linux/firmware.h>
5aabff05 11#include <linux/of.h>
9d580466 12#include <linux/property.h>
1657b8f8
WR		 13#include <linux/dmi.h>
14#include <linux/ctype.h>
3b58d6a5 15#include <linux/pm_qos.h>
27deb0f1 16#include <linux/nvmem-consumer.h>
6847f967 17#include <asm/byteorder.h>
5e3dd157
KV		 18
19#include "core.h"
20#include "mac.h"
21#include "htc.h"
22#include "hif.h"
23#include "wmi.h"
24#include "bmi.h"
25#include "debug.h"
26#include "htt.h"
43d2a30f 27#include "testmode.h"
d7579d12 28#include "wmi-ops.h"
f25b9f28 29#include "coredump.h"
5e3dd157
KV		 30
31unsigned int ath10k_debug_mask;
9d740d63
VN		 32EXPORT_SYMBOL(ath10k_debug_mask);
33
ccec9038 34static unsigned int ath10k_cryptmode_param;
5e3dd157 35static bool uart_print;
8868b12c 36static bool skip_otp;
d9e47698 37static bool fw_diag_log;
8868b12c 38
a0974054
SR		 39/* frame mode values are mapped as per enum ath10k_hw_txrx_mode */
40unsigned int ath10k_frame_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
41
7f8f72d8
BN		 42unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) |
43 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA);
5c9d0a20
KV		 44
45/* FIXME: most of these should be readonly */
5e3dd157 46module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
ccec9038 47module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
5e3dd157 48module_param(uart_print, bool, 0644);
8868b12c 49module_param(skip_otp, bool, 0644);
d9e47698 50module_param(fw_diag_log, bool, 0644);
a0974054 51module_param_named(frame_mode, ath10k_frame_mode, uint, 0644);
5c9d0a20 52module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444);
8868b12c 53
5e3dd157
KV		 54MODULE_PARM_DESC(debug_mask, "Debugging mask");
55MODULE_PARM_DESC(uart_print, "Uart target debugging");
8868b12c 56MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
ccec9038 57MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
a0974054 58MODULE_PARM_DESC(frame_mode,
af6d8265 59 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
5c9d0a20 60MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file");
d9e47698 61MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging");
5e3dd157
KV		 62
63static const struct ath10k_hw_params ath10k_hw_params_list[] = {
5e3dd157
KV		 64 {
65 .id = QCA988X_HW_2_0_VERSION,
079a0490 66 .dev_id = QCA988X_2_0_DEVICE_ID,
367c899f 67 .bus = ATH10K_BUS_PCI,
5e3dd157
KV		 68 .name = "qca988x hw2.0",
69 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
3a8200b2 70 .uart_pin = 7,
26c19760 71 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
d772703e 72 .otp_exe_param = 0,
9c8fb548 73 .channel_counters_freq_hz = 88000,
7b7da0a0 74 .max_probe_resp_desc_thres = 0,
0b8e3c4c 75 .cal_data_len = 2116,
5e3dd157
KV		 76 .fw = {
77 .dir = QCA988X_HW_2_0_FW_DIR,
5e3dd157 78 .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
9764a2af
MK		 79 .board_size = QCA988X_BOARD_DATA_SZ,
80 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
5e3dd157 81 },
6bae9de6 82 .rx_desc_ops = &qca988x_rx_desc_ops,
ae02c871 83 .hw_ops = &qca988x_ops,
2f38c3c0 84 .decap_align_bytes = 4,
a4aab099 85 .spectral_bin_discard = 0,
2e9bcd0d 86 .spectral_bin_offset = 0,
cc914a55
BG		 87 .vht160_mcs_rx_highest = 0,
88 .vht160_mcs_tx_highest = 0,
2ea9f12c 89 .n_cipher_suites = 8,
9f2992fe
RP		 90 .ast_skid_limit = 0x10,
91 .num_wds_entries = 0x20,
34f1cb33
TS		 92 .target_64bit = false,
93 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 94 .shadow_reg_support = false,
4945af5b 95 .rri_on_ddr = false,
58da3b42 96 .hw_filter_reset_required = true,
39501ea6 97 .fw_diag_ce_download = false,
09b8cd69 98 .credit_size_workaround = false,
4fa42ade 99 .tx_stats_over_pktlog = true,
442545ba 100 .dynamic_sar_support = false,
2c3fc505 101 .hw_restart_disconnect = false,
d81bbb68 102 .use_fw_tx_credits = true,
acd4324e 103 .delay_unmap_buffer = false,
63b89662 104 .mcast_frame_registration = false,
34f1cb33
TS		 105 },
106 {
107 .id = QCA988X_HW_2_0_VERSION,
108 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT,
109 .name = "qca988x hw2.0 ubiquiti",
110 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
111 .uart_pin = 7,
112 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
113 .otp_exe_param = 0,
114 .channel_counters_freq_hz = 88000,
115 .max_probe_resp_desc_thres = 0,
116 .cal_data_len = 2116,
117 .fw = {
118 .dir = QCA988X_HW_2_0_FW_DIR,
119 .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
120 .board_size = QCA988X_BOARD_DATA_SZ,
121 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
122 },
6bae9de6 123 .rx_desc_ops = &qca988x_rx_desc_ops,
34f1cb33
TS		 124 .hw_ops = &qca988x_ops,
125 .decap_align_bytes = 4,
126 .spectral_bin_discard = 0,
2e9bcd0d 127 .spectral_bin_offset = 0,
34f1cb33
TS		 128 .vht160_mcs_rx_highest = 0,
129 .vht160_mcs_tx_highest = 0,
130 .n_cipher_suites = 8,
34f1cb33
TS		 131 .ast_skid_limit = 0x10,
132 .num_wds_entries = 0x20,
f13cc6bd 133 .target_64bit = false,
bb8d0d15 134 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 135 .shadow_reg_support = false,
4945af5b 136 .rri_on_ddr = false,
58da3b42 137 .hw_filter_reset_required = true,
39501ea6 138 .fw_diag_ce_download = false,
09b8cd69 139 .credit_size_workaround = false,
4fa42ade 140 .tx_stats_over_pktlog = true,
442545ba 141 .dynamic_sar_support = false,
2c3fc505 142 .hw_restart_disconnect = false,
d81bbb68 143 .use_fw_tx_credits = true,
acd4324e 144 .delay_unmap_buffer = false,
63b89662 145 .mcast_frame_registration = false,
5e3dd157 146 },
6fd3dd71
SE		 147 {
148 .id = QCA9887_HW_1_0_VERSION,
149 .dev_id = QCA9887_1_0_DEVICE_ID,
367c899f 150 .bus = ATH10K_BUS_PCI,
6fd3dd71
SE		 151 .name = "qca9887 hw1.0",
152 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
153 .uart_pin = 7,
26c19760 154 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
6fd3dd71
SE		 155 .otp_exe_param = 0,
156 .channel_counters_freq_hz = 88000,
157 .max_probe_resp_desc_thres = 0,
6fd3dd71
SE		 158 .cal_data_len = 2116,
159 .fw = {
160 .dir = QCA9887_HW_1_0_FW_DIR,
161 .board = QCA9887_HW_1_0_BOARD_DATA_FILE,
162 .board_size = QCA9887_BOARD_DATA_SZ,
163 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ,
164 },
6bae9de6 165 .rx_desc_ops = &qca988x_rx_desc_ops,
ae02c871 166 .hw_ops = &qca988x_ops,
2f38c3c0 167 .decap_align_bytes = 4,
a4aab099 168 .spectral_bin_discard = 0,
2e9bcd0d 169 .spectral_bin_offset = 0,
cc914a55
BG		 170 .vht160_mcs_rx_highest = 0,
171 .vht160_mcs_tx_highest = 0,
2ea9f12c 172 .n_cipher_suites = 8,
9f2992fe
RP		 173 .ast_skid_limit = 0x10,
174 .num_wds_entries = 0x20,
f13cc6bd 175 .target_64bit = false,
bb8d0d15 176 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 177 .shadow_reg_support = false,
4945af5b 178 .rri_on_ddr = false,
58da3b42 179 .hw_filter_reset_required = true,
39501ea6 180 .fw_diag_ce_download = false,
09b8cd69 181 .credit_size_workaround = false,
4fa42ade 182 .tx_stats_over_pktlog = false,
442545ba 183 .dynamic_sar_support = false,
2c3fc505 184 .hw_restart_disconnect = false,
d81bbb68 185 .use_fw_tx_credits = true,
acd4324e 186 .delay_unmap_buffer = false,
63b89662 187 .mcast_frame_registration = false,
6fd3dd71 188 },
a8b10da0
WG		 189 {
190 .id = QCA6174_HW_3_2_VERSION,
191 .dev_id = QCA6174_3_2_DEVICE_ID,
192 .bus = ATH10K_BUS_SDIO,
193 .name = "qca6174 hw3.2 sdio",
194 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
195 .uart_pin = 19,
196 .otp_exe_param = 0,
197 .channel_counters_freq_hz = 88000,
198 .max_probe_resp_desc_thres = 0,
199 .cal_data_len = 0,
200 .fw = {
201 .dir = QCA6174_HW_3_0_FW_DIR,
202 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
203 .board_size = QCA6174_BOARD_DATA_SZ,
204 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
205 },
6bae9de6 206 .rx_desc_ops = &qca988x_rx_desc_ops,
6b4021de 207 .hw_ops = &qca6174_sdio_ops,
a8b10da0
WG		 208 .hw_clk = qca6174_clk,
209 .target_cpu_freq = 176000000,
210 .decap_align_bytes = 4,
211 .n_cipher_suites = 8,
212 .num_peers = 10,
213 .ast_skid_limit = 0x10,
214 .num_wds_entries = 0x20,
215 .uart_pin_workaround = true,
4fa42ade 216 .tx_stats_over_pktlog = false,
09b8cd69 217 .credit_size_workaround = false,
d58f466a 218 .bmi_large_size_download = true,
0f7cb268 219 .supports_peer_stats_info = true,
442545ba 220 .dynamic_sar_support = true,
2c3fc505 221 .hw_restart_disconnect = false,
d81bbb68 222 .use_fw_tx_credits = true,
acd4324e 223 .delay_unmap_buffer = false,
63b89662 224 .mcast_frame_registration = false,
a8b10da0 225 },
d63955b3
MK		 226 {
227 .id = QCA6174_HW_2_1_VERSION,
079a0490 228 .dev_id = QCA6164_2_1_DEVICE_ID,
367c899f 229 .bus = ATH10K_BUS_PCI,
079a0490
BM		 230 .name = "qca6164 hw2.1",
231 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
232 .uart_pin = 6,
233 .otp_exe_param = 0,
234 .channel_counters_freq_hz = 88000,
235 .max_probe_resp_desc_thres = 0,
0b8e3c4c 236 .cal_data_len = 8124,
079a0490
BM		 237 .fw = {
238 .dir = QCA6174_HW_2_1_FW_DIR,
079a0490
BM		 239 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
240 .board_size = QCA6174_BOARD_DATA_SZ,
241 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
242 },
6bae9de6 243 .rx_desc_ops = &qca988x_rx_desc_ops,
ae02c871 244 .hw_ops = &qca988x_ops,
2f38c3c0 245 .decap_align_bytes = 4,
a4aab099 246 .spectral_bin_discard = 0,
2e9bcd0d 247 .spectral_bin_offset = 0,
cc914a55
BG		 248 .vht160_mcs_rx_highest = 0,
249 .vht160_mcs_tx_highest = 0,
2ea9f12c 250 .n_cipher_suites = 8,
9f2992fe
RP		 251 .ast_skid_limit = 0x10,
252 .num_wds_entries = 0x20,
f13cc6bd 253 .target_64bit = false,
bb8d0d15 254 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 255 .shadow_reg_support = false,
4945af5b 256 .rri_on_ddr = false,
58da3b42 257 .hw_filter_reset_required = true,
39501ea6 258 .fw_diag_ce_download = false,
09b8cd69 259 .credit_size_workaround = false,
4fa42ade 260 .tx_stats_over_pktlog = false,
442545ba 261 .dynamic_sar_support = false,
2c3fc505 262 .hw_restart_disconnect = false,
d81bbb68 263 .use_fw_tx_credits = true,
acd4324e 264 .delay_unmap_buffer = false,
63b89662 265 .mcast_frame_registration = false,
079a0490
BM		 266 },
267 {
268 .id = QCA6174_HW_2_1_VERSION,
269 .dev_id = QCA6174_2_1_DEVICE_ID,
367c899f 270 .bus = ATH10K_BUS_PCI,
d63955b3
MK		 271 .name = "qca6174 hw2.1",
272 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
273 .uart_pin = 6,
d772703e 274 .otp_exe_param = 0,
9c8fb548 275 .channel_counters_freq_hz = 88000,
7b7da0a0 276 .max_probe_resp_desc_thres = 0,
0b8e3c4c 277 .cal_data_len = 8124,
d63955b3
MK		 278 .fw = {
279 .dir = QCA6174_HW_2_1_FW_DIR,
d63955b3
MK		 280 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
281 .board_size = QCA6174_BOARD_DATA_SZ,
282 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
283 },
6bae9de6 284 .rx_desc_ops = &qca988x_rx_desc_ops,
ae02c871 285 .hw_ops = &qca988x_ops,
2f38c3c0 286 .decap_align_bytes = 4,
a4aab099 287 .spectral_bin_discard = 0,
2e9bcd0d 288 .spectral_bin_offset = 0,
cc914a55
BG		 289 .vht160_mcs_rx_highest = 0,
290 .vht160_mcs_tx_highest = 0,
2ea9f12c 291 .n_cipher_suites = 8,
9f2992fe
RP		 292 .ast_skid_limit = 0x10,
293 .num_wds_entries = 0x20,
f13cc6bd 294 .target_64bit = false,
bb8d0d15 295 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 296 .shadow_reg_support = false,
4945af5b 297 .rri_on_ddr = false,
58da3b42 298 .hw_filter_reset_required = true,
39501ea6 299 .fw_diag_ce_download = false,
09b8cd69 300 .credit_size_workaround = false,
4fa42ade 301 .tx_stats_over_pktlog = false,
442545ba 302 .dynamic_sar_support = false,
2c3fc505 303 .hw_restart_disconnect = false,
d81bbb68 304 .use_fw_tx_credits = true,
acd4324e 305 .delay_unmap_buffer = false,
63b89662 306 .mcast_frame_registration = false,
d63955b3
MK		 307 },
308 {
309 .id = QCA6174_HW_3_0_VERSION,
079a0490 310 .dev_id = QCA6174_2_1_DEVICE_ID,
367c899f 311 .bus = ATH10K_BUS_PCI,
d63955b3
MK		 312 .name = "qca6174 hw3.0",
313 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
314 .uart_pin = 6,
d772703e 315 .otp_exe_param = 0,
9c8fb548 316 .channel_counters_freq_hz = 88000,
7b7da0a0 317 .max_probe_resp_desc_thres = 0,
0b8e3c4c 318 .cal_data_len = 8124,
d63955b3
MK		 319 .fw = {
320 .dir = QCA6174_HW_3_0_FW_DIR,
d63955b3
MK		 321 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
322 .board_size = QCA6174_BOARD_DATA_SZ,
323 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
324 },
6bae9de6 325 .rx_desc_ops = &qca988x_rx_desc_ops,
ae02c871 326 .hw_ops = &qca988x_ops,
2f38c3c0 327 .decap_align_bytes = 4,
a4aab099 328 .spectral_bin_discard = 0,
2e9bcd0d 329 .spectral_bin_offset = 0,
cc914a55
BG		 330 .vht160_mcs_rx_highest = 0,
331 .vht160_mcs_tx_highest = 0,
2ea9f12c 332 .n_cipher_suites = 8,
9f2992fe
RP		 333 .ast_skid_limit = 0x10,
334 .num_wds_entries = 0x20,
f13cc6bd 335 .target_64bit = false,
bb8d0d15 336 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 337 .shadow_reg_support = false,
4945af5b 338 .rri_on_ddr = false,
58da3b42 339 .hw_filter_reset_required = true,
39501ea6 340 .fw_diag_ce_download = false,
09b8cd69 341 .credit_size_workaround = false,
4fa42ade 342 .tx_stats_over_pktlog = false,
442545ba 343 .dynamic_sar_support = false,
2c3fc505 344 .hw_restart_disconnect = false,
d81bbb68 345 .use_fw_tx_credits = true,
acd4324e 346 .delay_unmap_buffer = false,
63b89662 347 .mcast_frame_registration = false,
d63955b3 348 },
608b8f73
MK		 349 {
350 .id = QCA6174_HW_3_2_VERSION,
079a0490 351 .dev_id = QCA6174_2_1_DEVICE_ID,
367c899f 352 .bus = ATH10K_BUS_PCI,
608b8f73
MK		 353 .name = "qca6174 hw3.2",
354 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
355 .uart_pin = 6,
d772703e 356 .otp_exe_param = 0,
9c8fb548 357 .channel_counters_freq_hz = 88000,
7b7da0a0 358 .max_probe_resp_desc_thres = 0,
0b8e3c4c 359 .cal_data_len = 8124,
608b8f73
MK		 360 .fw = {
361 /* uses same binaries as hw3.0 */
362 .dir = QCA6174_HW_3_0_FW_DIR,
608b8f73
MK		 363 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
364 .board_size = QCA6174_BOARD_DATA_SZ,
365 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
366 },
6bae9de6 367 .rx_desc_ops = &qca988x_rx_desc_ops,
583a6629
RH		 368 .hw_ops = &qca6174_ops,
369 .hw_clk = qca6174_clk,
370 .target_cpu_freq = 176000000,
2f38c3c0 371 .decap_align_bytes = 4,
a4aab099 372 .spectral_bin_discard = 0,
2e9bcd0d 373 .spectral_bin_offset = 0,
cc914a55
BG		 374 .vht160_mcs_rx_highest = 0,
375 .vht160_mcs_tx_highest = 0,
2ea9f12c 376 .n_cipher_suites = 8,
9f2992fe
RP		 377 .ast_skid_limit = 0x10,
378 .num_wds_entries = 0x20,
f13cc6bd 379 .target_64bit = false,
bb8d0d15 380 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 381 .shadow_reg_support = false,
4945af5b 382 .rri_on_ddr = false,
58da3b42 383 .hw_filter_reset_required = true,
39501ea6 384 .fw_diag_ce_download = true,
09b8cd69 385 .credit_size_workaround = false,
4fa42ade 386 .tx_stats_over_pktlog = false,
cbcbabb9 387 .supports_peer_stats_info = true,
442545ba 388 .dynamic_sar_support = true,
2c3fc505 389 .hw_restart_disconnect = false,
d81bbb68 390 .use_fw_tx_credits = true,
acd4324e 391 .delay_unmap_buffer = false,
63b89662 392 .mcast_frame_registration = true,
608b8f73 393 },
8bd47021
VT		 394 {
395 .id = QCA99X0_HW_2_0_DEV_VERSION,
079a0490 396 .dev_id = QCA99X0_2_0_DEVICE_ID,
367c899f 397 .bus = ATH10K_BUS_PCI,
8bd47021
VT		 398 .name = "qca99x0 hw2.0",
399 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
400 .uart_pin = 7,
d772703e 401 .otp_exe_param = 0x00000700,
d9156b5f 402 .continuous_frag_desc = true,
5269c659 403 .cck_rate_map_rev2 = true,
9c8fb548 404 .channel_counters_freq_hz = 150000,
7b7da0a0 405 .max_probe_resp_desc_thres = 24,
5699a6f2
RM		 406 .tx_chain_mask = 0xf,
407 .rx_chain_mask = 0xf,
408 .max_spatial_stream = 4,
0b8e3c4c 409 .cal_data_len = 12064,
8bd47021
VT		 410 .fw = {
411 .dir = QCA99X0_HW_2_0_FW_DIR,
8bd47021
VT		 412 .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
413 .board_size = QCA99X0_BOARD_DATA_SZ,
414 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
415 },
7d42298e 416 .sw_decrypt_mcast_mgmt = true,
6bae9de6 417 .rx_desc_ops = &qca99x0_rx_desc_ops,
ae02c871 418 .hw_ops = &qca99x0_ops,
2f38c3c0 419 .decap_align_bytes = 1,
a4aab099 420 .spectral_bin_discard = 4,
2e9bcd0d 421 .spectral_bin_offset = 0,
cc914a55
BG		 422 .vht160_mcs_rx_highest = 0,
423 .vht160_mcs_tx_highest = 0,
2ea9f12c 424 .n_cipher_suites = 11,
9f2992fe
RP		 425 .ast_skid_limit = 0x10,
426 .num_wds_entries = 0x20,
f13cc6bd 427 .target_64bit = false,
bb8d0d15 428 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 429 .shadow_reg_support = false,
4945af5b 430 .rri_on_ddr = false,
58da3b42 431 .hw_filter_reset_required = true,
39501ea6 432 .fw_diag_ce_download = false,
09b8cd69 433 .credit_size_workaround = false,
4fa42ade 434 .tx_stats_over_pktlog = false,
442545ba 435 .dynamic_sar_support = false,
2c3fc505 436 .hw_restart_disconnect = false,
d81bbb68 437 .use_fw_tx_credits = true,
acd4324e 438 .delay_unmap_buffer = false,
63b89662 439 .mcast_frame_registration = false,
8bd47021 440 },
651b4cdc
VT		 441 {
442 .id = QCA9984_HW_1_0_DEV_VERSION,
443 .dev_id = QCA9984_1_0_DEVICE_ID,
367c899f 444 .bus = ATH10K_BUS_PCI,
651b4cdc
VT		 445 .name = "qca9984/qca9994 hw1.0",
446 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
447 .uart_pin = 7,
bafe4926 448 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
651b4cdc
VT		 449 .otp_exe_param = 0x00000700,
450 .continuous_frag_desc = true,
5269c659 451 .cck_rate_map_rev2 = true,
651b4cdc
VT		 452 .channel_counters_freq_hz = 150000,
453 .max_probe_resp_desc_thres = 24,
651b4cdc
VT		 454 .tx_chain_mask = 0xf,
455 .rx_chain_mask = 0xf,
456 .max_spatial_stream = 4,
457 .cal_data_len = 12064,
458 .fw = {
459 .dir = QCA9984_HW_1_0_FW_DIR,
460 .board = QCA9984_HW_1_0_BOARD_DATA_FILE,
31324d17 461 .eboard = QCA9984_HW_1_0_EBOARD_DATA_FILE,
651b4cdc
VT		 462 .board_size = QCA99X0_BOARD_DATA_SZ,
463 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
31324d17 464 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ,
651b4cdc 465 },
7d42298e 466 .sw_decrypt_mcast_mgmt = true,
6bae9de6 467 .rx_desc_ops = &qca99x0_rx_desc_ops,
ae02c871 468 .hw_ops = &qca99x0_ops,
2f38c3c0 469 .decap_align_bytes = 1,
a4aab099 470 .spectral_bin_discard = 12,
2e9bcd0d 471 .spectral_bin_offset = 8,
cc914a55
BG		 472
473 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz
474 * or 2x2 160Mhz, long-guard-interval.
475 */
476 .vht160_mcs_rx_highest = 1560,
477 .vht160_mcs_tx_highest = 1560,
2ea9f12c 478 .n_cipher_suites = 11,
9f2992fe
RP		 479 .ast_skid_limit = 0x10,
480 .num_wds_entries = 0x20,
f13cc6bd 481 .target_64bit = false,
bb8d0d15 482 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 483 .shadow_reg_support = false,
4945af5b 484 .rri_on_ddr = false,
58da3b42 485 .hw_filter_reset_required = true,
39501ea6 486 .fw_diag_ce_download = false,
09b8cd69 487 .credit_size_workaround = false,
4fa42ade 488 .tx_stats_over_pktlog = false,
442545ba 489 .dynamic_sar_support = false,
2c3fc505 490 .hw_restart_disconnect = false,
d81bbb68 491 .use_fw_tx_credits = true,
acd4324e 492 .delay_unmap_buffer = false,
63b89662 493 .mcast_frame_registration = false,
651b4cdc 494 },
e565c312
AK		 495 {
496 .id = QCA9888_HW_2_0_DEV_VERSION,
497 .dev_id = QCA9888_2_0_DEVICE_ID,
367c899f 498 .bus = ATH10K_BUS_PCI,
e565c312
AK		 499 .name = "qca9888 hw2.0",
500 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
501 .uart_pin = 7,
bafe4926 502 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
e565c312
AK		 503 .otp_exe_param = 0x00000700,
504 .continuous_frag_desc = true,
505 .channel_counters_freq_hz = 150000,
506 .max_probe_resp_desc_thres = 24,
e565c312
AK		 507 .tx_chain_mask = 3,
508 .rx_chain_mask = 3,
509 .max_spatial_stream = 2,
510 .cal_data_len = 12064,
511 .fw = {
512 .dir = QCA9888_HW_2_0_FW_DIR,
513 .board = QCA9888_HW_2_0_BOARD_DATA_FILE,
514 .board_size = QCA99X0_BOARD_DATA_SZ,
515 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
516 },
7d42298e 517 .sw_decrypt_mcast_mgmt = true,
6bae9de6 518 .rx_desc_ops = &qca99x0_rx_desc_ops,
ae02c871 519 .hw_ops = &qca99x0_ops,
2f38c3c0 520 .decap_align_bytes = 1,
a4aab099 521 .spectral_bin_discard = 12,
2e9bcd0d 522 .spectral_bin_offset = 8,
68248349
SE		 523
524 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or
525 * 1x1 160Mhz, long-guard-interval.
526 */
527 .vht160_mcs_rx_highest = 780,
528 .vht160_mcs_tx_highest = 780,
2ea9f12c 529 .n_cipher_suites = 11,
9f2992fe
RP		 530 .ast_skid_limit = 0x10,
531 .num_wds_entries = 0x20,
f13cc6bd 532 .target_64bit = false,
bb8d0d15 533 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 534 .shadow_reg_support = false,
4945af5b 535 .rri_on_ddr = false,
58da3b42 536 .hw_filter_reset_required = true,
39501ea6 537 .fw_diag_ce_download = false,
09b8cd69 538 .credit_size_workaround = false,
4fa42ade 539 .tx_stats_over_pktlog = false,
442545ba 540 .dynamic_sar_support = false,
2c3fc505 541 .hw_restart_disconnect = false,
d81bbb68 542 .use_fw_tx_credits = true,
acd4324e 543 .delay_unmap_buffer = false,
63b89662 544 .mcast_frame_registration = false,
e565c312 545 },
034074f3
BM		 546 {
547 .id = QCA9377_HW_1_0_DEV_VERSION,
548 .dev_id = QCA9377_1_0_DEVICE_ID,
367c899f 549 .bus = ATH10K_BUS_PCI,
034074f3
BM		 550 .name = "qca9377 hw1.0",
551 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
552 .uart_pin = 6,
553 .otp_exe_param = 0,
554 .channel_counters_freq_hz = 88000,
555 .max_probe_resp_desc_thres = 0,
0b8e3c4c 556 .cal_data_len = 8124,
034074f3
BM		 557 .fw = {
558 .dir = QCA9377_HW_1_0_FW_DIR,
034074f3
BM		 559 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
560 .board_size = QCA9377_BOARD_DATA_SZ,
561 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
562 },
6bae9de6 563 .rx_desc_ops = &qca988x_rx_desc_ops,
ae02c871 564 .hw_ops = &qca988x_ops,
2f38c3c0 565 .decap_align_bytes = 4,
a4aab099 566 .spectral_bin_discard = 0,
2e9bcd0d 567 .spectral_bin_offset = 0,
cc914a55
BG		 568 .vht160_mcs_rx_highest = 0,
569 .vht160_mcs_tx_highest = 0,
2ea9f12c 570 .n_cipher_suites = 8,
9f2992fe
RP		 571 .ast_skid_limit = 0x10,
572 .num_wds_entries = 0x20,
f13cc6bd 573 .target_64bit = false,
bb8d0d15 574 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 575 .shadow_reg_support = false,
4945af5b 576 .rri_on_ddr = false,
58da3b42 577 .hw_filter_reset_required = true,
39501ea6 578 .fw_diag_ce_download = false,
09b8cd69 579 .credit_size_workaround = false,
4fa42ade 580 .tx_stats_over_pktlog = false,
442545ba 581 .dynamic_sar_support = false,
2c3fc505 582 .hw_restart_disconnect = false,
d81bbb68 583 .use_fw_tx_credits = true,
acd4324e 584 .delay_unmap_buffer = false,
63b89662 585 .mcast_frame_registration = false,
034074f3 586 },
a226b519 587 {
12551ced 588 .id = QCA9377_HW_1_1_DEV_VERSION,
079a0490 589 .dev_id = QCA9377_1_0_DEVICE_ID,
367c899f 590 .bus = ATH10K_BUS_PCI,
12551ced 591 .name = "qca9377 hw1.1",
a226b519 592 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
6cf21395 593 .uart_pin = 6,
a226b519 594 .otp_exe_param = 0,
6cf21395
BM		 595 .channel_counters_freq_hz = 88000,
596 .max_probe_resp_desc_thres = 0,
0b8e3c4c 597 .cal_data_len = 8124,
a226b519
BM		 598 .fw = {
599 .dir = QCA9377_HW_1_0_FW_DIR,
a226b519
BM		 600 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
601 .board_size = QCA9377_BOARD_DATA_SZ,
602 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
603 },
6bae9de6 604 .rx_desc_ops = &qca988x_rx_desc_ops,
912b6e88
RH		 605 .hw_ops = &qca6174_ops,
606 .hw_clk = qca6174_clk,
607 .target_cpu_freq = 176000000,
2f38c3c0 608 .decap_align_bytes = 4,
a4aab099 609 .spectral_bin_discard = 0,
2e9bcd0d 610 .spectral_bin_offset = 0,
cc914a55
BG		 611 .vht160_mcs_rx_highest = 0,
612 .vht160_mcs_tx_highest = 0,
2ea9f12c 613 .n_cipher_suites = 8,
9f2992fe
RP		 614 .ast_skid_limit = 0x10,
615 .num_wds_entries = 0x20,
f13cc6bd 616 .target_64bit = false,
bb8d0d15 617 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 618 .shadow_reg_support = false,
4945af5b 619 .rri_on_ddr = false,
58da3b42 620 .hw_filter_reset_required = true,
39501ea6 621 .fw_diag_ce_download = true,
09b8cd69 622 .credit_size_workaround = false,
4fa42ade 623 .tx_stats_over_pktlog = false,
442545ba 624 .dynamic_sar_support = false,
2c3fc505 625 .hw_restart_disconnect = false,
d81bbb68 626 .use_fw_tx_credits = true,
acd4324e 627 .delay_unmap_buffer = false,
63b89662 628 .mcast_frame_registration = false,
a226b519 629 },
6e51b0e4
ES		 630 {
631 .id = QCA9377_HW_1_1_DEV_VERSION,
632 .dev_id = QCA9377_1_0_DEVICE_ID,
633 .bus = ATH10K_BUS_SDIO,
634 .name = "qca9377 hw1.1 sdio",
635 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
636 .uart_pin = 19,
637 .otp_exe_param = 0,
638 .channel_counters_freq_hz = 88000,
639 .max_probe_resp_desc_thres = 0,
640 .cal_data_len = 8124,
641 .fw = {
642 .dir = QCA9377_HW_1_0_FW_DIR,
643 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
644 .board_size = QCA9377_BOARD_DATA_SZ,
645 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
646 },
6bae9de6 647 .rx_desc_ops = &qca988x_rx_desc_ops,
6e51b0e4
ES		 648 .hw_ops = &qca6174_ops,
649 .hw_clk = qca6174_clk,
650 .target_cpu_freq = 176000000,
651 .decap_align_bytes = 4,
652 .n_cipher_suites = 8,
653 .num_peers = TARGET_QCA9377_HL_NUM_PEERS,
654 .ast_skid_limit = 0x10,
655 .num_wds_entries = 0x20,
656 .uart_pin_workaround = true,
09b8cd69 657 .credit_size_workaround = true,
442545ba 658 .dynamic_sar_support = false,
2c3fc505 659 .hw_restart_disconnect = false,
d81bbb68 660 .use_fw_tx_credits = true,
acd4324e 661 .delay_unmap_buffer = false,
63b89662 662 .mcast_frame_registration = false,
6e51b0e4 663 },
b1a958c9
RM		 664 {
665 .id = QCA4019_HW_1_0_DEV_VERSION,
666 .dev_id = 0,
367c899f 667 .bus = ATH10K_BUS_AHB,
b1a958c9
RM		 668 .name = "qca4019 hw1.0",
669 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
670 .uart_pin = 7,
8e100354 671 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
b1a958c9
RM		 672 .otp_exe_param = 0x0010000,
673 .continuous_frag_desc = true,
5269c659 674 .cck_rate_map_rev2 = true,
b1a958c9
RM		 675 .channel_counters_freq_hz = 125000,
676 .max_probe_resp_desc_thres = 24,
5699a6f2
RM		 677 .tx_chain_mask = 0x3,
678 .rx_chain_mask = 0x3,
679 .max_spatial_stream = 2,
0b8e3c4c 680 .cal_data_len = 12064,
b1a958c9
RM		 681 .fw = {
682 .dir = QCA4019_HW_1_0_FW_DIR,
b1a958c9
RM		 683 .board = QCA4019_HW_1_0_BOARD_DATA_FILE,
684 .board_size = QCA4019_BOARD_DATA_SZ,
685 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
686 },
7d42298e 687 .sw_decrypt_mcast_mgmt = true,
6bae9de6 688 .rx_desc_ops = &qca99x0_rx_desc_ops,
ae02c871 689 .hw_ops = &qca99x0_ops,
2f38c3c0 690 .decap_align_bytes = 1,
a4aab099 691 .spectral_bin_discard = 4,
2e9bcd0d 692 .spectral_bin_offset = 0,
cc914a55
BG		 693 .vht160_mcs_rx_highest = 0,
694 .vht160_mcs_tx_highest = 0,
2ea9f12c 695 .n_cipher_suites = 11,
9f2992fe
RP		 696 .ast_skid_limit = 0x10,
697 .num_wds_entries = 0x20,
f13cc6bd 698 .target_64bit = false,
bb8d0d15 699 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
b2e40d7a 700 .shadow_reg_support = false,
4945af5b 701 .rri_on_ddr = false,
58da3b42 702 .hw_filter_reset_required = true,
39501ea6 703 .fw_diag_ce_download = false,
09b8cd69 704 .credit_size_workaround = false,
4fa42ade 705 .tx_stats_over_pktlog = false,
442545ba 706 .dynamic_sar_support = false,
2c3fc505 707 .hw_restart_disconnect = false,
d81bbb68 708 .use_fw_tx_credits = true,
acd4324e 709 .delay_unmap_buffer = false,
63b89662 710 .mcast_frame_registration = false,
b1a958c9 711 },
03a72288
RP		 712 {
713 .id = WCN3990_HW_1_0_DEV_VERSION,
714 .dev_id = 0,
2c2008a6 715 .bus = ATH10K_BUS_SNOC,
03a72288
RP		 716 .name = "wcn3990 hw1.0",
717 .continuous_frag_desc = true,
718 .tx_chain_mask = 0x7,
719 .rx_chain_mask = 0x7,
720 .max_spatial_stream = 4,
721 .fw = {
722 .dir = WCN3990_HW_1_0_FW_DIR,
723 },
724 .sw_decrypt_mcast_mgmt = true,
6bae9de6 725 .rx_desc_ops = &wcn3990_rx_desc_ops,
03a72288
RP		 726 .hw_ops = &wcn3990_ops,
727 .decap_align_bytes = 1,
15493239 728 .num_peers = TARGET_HL_TLV_NUM_PEERS,
7ba31e6e 729 .n_cipher_suites = 11,
15493239
AA		 730 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT,
731 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES,
f13cc6bd 732 .target_64bit = true,
bb8d0d15 733 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
b2e40d7a 734 .shadow_reg_support = true,
4945af5b 735 .rri_on_ddr = true,
58da3b42 736 .hw_filter_reset_required = false,
39501ea6 737 .fw_diag_ce_download = false,
09b8cd69 738 .credit_size_workaround = false,
4fa42ade 739 .tx_stats_over_pktlog = false,
442545ba 740 .dynamic_sar_support = true,
2c3fc505 741 .hw_restart_disconnect = true,
d81bbb68 742 .use_fw_tx_credits = false,
acd4324e 743 .delay_unmap_buffer = true,
63b89662 744 .mcast_frame_registration = false,
03a72288 745 },
5e3dd157
KV		 746};
747
b27bc5a4
MK		 748static const char *const ath10k_core_fw_feature_str[] = {
749 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
750 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
751 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
752 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
753 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
754 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
755 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
756 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
757 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
758 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
5af82fa6 759 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
62f77f09 760 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
90eceb3b 761 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
9b783763 762 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
64e001f4 763 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param",
2cdce425 764 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war",
705d7aa0 765 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast",
36d9cdb6 766 [ATH10K_FW_FEATURE_NO_PS] = "no-ps",
1807da49 767 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference",
71e9c29f 768 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi",
13104929 769 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel",
8b97b055 770 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate",
9af7c32c 771 [ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery",
b27bc5a4
MK		 772};
773
774static unsigned int ath10k_core_get_fw_feature_str(char *buf,
775 size_t buf_len,
776 enum ath10k_fw_features feat)
777{
5af82fa6
KV		 778 /* make sure that ath10k_core_fw_feature_str[] gets updated */
779 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
780 ATH10K_FW_FEATURE_COUNT);
781
b27bc5a4
MK		 782 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
783 WARN_ON(!ath10k_core_fw_feature_str[feat])) {
784 return scnprintf(buf, buf_len, "bit%d", feat);
785 }
786
787 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
788}
789
790void ath10k_core_get_fw_features_str(struct ath10k *ar,
791 char *buf,
792 size_t buf_len)
793{
182f1e5a 794 size_t len = 0;
b27bc5a4
MK		 795 int i;
796
797 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
c4cdf753 798 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) {
b27bc5a4
MK		 799 if (len > 0)
800 len += scnprintf(buf + len, buf_len - len, ",");
801
802 len += ath10k_core_get_fw_feature_str(buf + len,
803 buf_len - len,
804 i);
805 }
806 }
807}
808
5e3dd157
KV		 809static void ath10k_send_suspend_complete(struct ath10k *ar)
810{
7aa7a72a 811 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
5e3dd157 812
9042e17d 813 complete(&ar->target_suspend);
5e3dd157
KV		 814}
815
8da96730 816static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode)
60bdfffa 817{
09b8cd69 818 bool mtu_workaround = ar->hw_params.credit_size_workaround;
8da96730 819 int ret;
60bdfffa
ES		 820 u32 param = 0;
821
8da96730
KL		 822 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256);
823 if (ret)
824 return ret;
825
826 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99);
827 if (ret)
828 return ret;
829
830 ret = ath10k_bmi_read32(ar, hi_acs_flags, &param);
831 if (ret)
832 return ret;
60bdfffa 833
d81686d3 834 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET;
60bdfffa 835
09b8cd69 836 if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround)
2f918ea9
WG		 837 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
838 else
839 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
8cdee1af
WG		 840
841 if (mode == ATH10K_FIRMWARE_MODE_UTF)
842 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
843 else
844 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
845
8da96730
KL		 846 ret = ath10k_bmi_write32(ar, hi_acs_flags, param);
847 if (ret)
848 return ret;
6cd70c65 849
3c45f21a
WG		 850 ret = ath10k_bmi_read32(ar, hi_option_flag2, &param);
851 if (ret)
852 return ret;
853
854 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST;
855
856 ret = ath10k_bmi_write32(ar, hi_option_flag2, param);
857 if (ret)
858 return ret;
859
8da96730 860 return 0;
60bdfffa
ES		 861}
862
5e3dd157
KV		 863static int ath10k_init_configure_target(struct ath10k *ar)
864{
865 u32 param_host;
866 int ret;
867
868 /* tell target which HTC version it is used*/
869 ret = ath10k_bmi_write32(ar, hi_app_host_interest,
870 HTC_PROTOCOL_VERSION);
871 if (ret) {
7aa7a72a 872 ath10k_err(ar, "settings HTC version failed\n");
5e3dd157
KV		 873 return ret;
874 }
875
876 /* set the firmware mode to STA/IBSS/AP */
877 ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
878 if (ret) {
7aa7a72a 879 ath10k_err(ar, "setting firmware mode (1/2) failed\n");
5e3dd157
KV		 880 return ret;
881 }
882
883 /* TODO following parameters need to be re-visited. */
884 /* num_device */
885 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
886 /* Firmware mode */
887 /* FIXME: Why FW_MODE_AP ??.*/
888 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
889 /* mac_addr_method */
890 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
891 /* firmware_bridge */
892 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
893 /* fwsubmode */
894 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
895
896 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
897 if (ret) {
7aa7a72a 898 ath10k_err(ar, "setting firmware mode (2/2) failed\n");
5e3dd157
KV		 899 return ret;
900 }
901
902 /* We do all byte-swapping on the host */
903 ret = ath10k_bmi_write32(ar, hi_be, 0);
904 if (ret) {
7aa7a72a 905 ath10k_err(ar, "setting host CPU BE mode failed\n");
5e3dd157
KV		 906 return ret;
907 }
908
909 /* FW descriptor/Data swap flags */
910 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
911
912 if (ret) {
7aa7a72a 913 ath10k_err(ar, "setting FW data/desc swap flags failed\n");
5e3dd157
KV		 914 return ret;
915 }
916
36582e5d
MK		 917 /* Some devices have a special sanity check that verifies the PCI
918 * Device ID is written to this host interest var. It is known to be
919 * required to boot QCA6164.
920 */
921 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
922 ar->dev_id);
923 if (ret) {
924 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
925 return ret;
926 }
927
5e3dd157
KV		 928 return 0;
929}
930
931static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
932 const char *dir,
933 const char *file)
934{
935 char filename[100];
936 const struct firmware *fw;
937 int ret;
938
939 if (file == NULL)
940 return ERR_PTR(-ENOENT);
941
942 if (dir == NULL)
943 dir = ".";
944
945 snprintf(filename, sizeof(filename), "%s/%s", dir, file);
c8e02802 946 ret = firmware_request_nowarn(&fw, filename, ar->dev);
9f5bcfe9
MK		 947 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n",
948 filename, ret);
949
5e3dd157
KV		 950 if (ret)
951 return ERR_PTR(ret);
952
953 return fw;
954}
955
a58227ef
KV		 956static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
957 size_t data_len)
5e3dd157 958{
9764a2af
MK		 959 u32 board_data_size = ar->hw_params.fw.board_size;
960 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
5e3dd157
KV		 961 u32 board_ext_data_addr;
962 int ret;
963
964 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
965 if (ret) {
7aa7a72a
MK		 966 ath10k_err(ar, "could not read board ext data addr (%d)\n",
967 ret);
5e3dd157
KV		 968 return ret;
969 }
970
7aa7a72a 971 ath10k_dbg(ar, ATH10K_DBG_BOOT,
effea968 972 "boot push board extended data addr 0x%x\n",
5e3dd157
KV		 973 board_ext_data_addr);
974
975 if (board_ext_data_addr == 0)
976 return 0;
977
a58227ef 978 if (data_len != (board_data_size + board_ext_data_size)) {
7aa7a72a 979 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
a58227ef 980 data_len, board_data_size, board_ext_data_size);
5e3dd157
KV		 981 return -EINVAL;
982 }
983
984 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
a58227ef 985 data + board_data_size,
5e3dd157
KV		 986 board_ext_data_size);
987 if (ret) {
7aa7a72a 988 ath10k_err(ar, "could not write board ext data (%d)\n", ret);
5e3dd157
KV		 989 return ret;
990 }
991
992 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
993 (board_ext_data_size << 16) | 1);
994 if (ret) {
7aa7a72a
MK		 995 ath10k_err(ar, "could not write board ext data bit (%d)\n",
996 ret);
5e3dd157
KV		 997 return ret;
998 }
999
1000 return 0;
1001}
1002
db0984e5
MP		 1003static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
1004{
1005 u32 result, address;
1006 u8 board_id, chip_id;
31324d17 1007 bool ext_bid_support;
a9f5f287 1008 int ret, bmi_board_id_param;
db0984e5
MP		 1009
1010 address = ar->hw_params.patch_load_addr;
1011
7ebf721d
KV		 1012 if (!ar->normal_mode_fw.fw_file.otp_data ||
1013 !ar->normal_mode_fw.fw_file.otp_len) {
db0984e5
MP		 1014 ath10k_warn(ar,
1015 "failed to retrieve board id because of invalid otp\n");
1016 return -ENODATA;
1017 }
1018
a4b9f641
VP		 1019 if (ar->id.bmi_ids_valid) {
1020 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1021 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n",
1022 ar->id.bmi_board_id, ar->id.bmi_chip_id);
1023 goto skip_otp_download;
1024 }
1025
db0984e5
MP		 1026 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1027 "boot upload otp to 0x%x len %zd for board id\n",
7ebf721d 1028 address, ar->normal_mode_fw.fw_file.otp_len);
db0984e5 1029
7ebf721d
KV		 1030 ret = ath10k_bmi_fast_download(ar, address,
1031 ar->normal_mode_fw.fw_file.otp_data,
1032 ar->normal_mode_fw.fw_file.otp_len);
db0984e5
MP		 1033 if (ret) {
1034 ath10k_err(ar, "could not write otp for board id check: %d\n",
1035 ret);
1036 return ret;
1037 }
1038
a9f5f287 1039 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
27deb0f1
CL		 1040 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||
1041 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)
a9f5f287
AK		 1042 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID;
1043 else
1044 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID;
1045
1046 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result);
db0984e5
MP		 1047 if (ret) {
1048 ath10k_err(ar, "could not execute otp for board id check: %d\n",
1049 ret);
1050 return ret;
1051 }
1052
1053 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
1054 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
31324d17 1055 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT);
db0984e5
MP		 1056
1057 ath10k_dbg(ar, ATH10K_DBG_BOOT,
31324d17
SM		 1058 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n",
1059 result, board_id, chip_id, ext_bid_support);
1060
1061 ar->id.ext_bid_supported = ext_bid_support;
db0984e5 1062
d2e202c0
RH		 1063 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 ||
1064 (board_id == 0)) {
7be52c03
KV		 1065 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1066 "board id does not exist in otp, ignore it\n");
db0984e5 1067 return -EOPNOTSUPP;
d2e202c0 1068 }
db0984e5
MP		 1069
1070 ar->id.bmi_ids_valid = true;
1071 ar->id.bmi_board_id = board_id;
1072 ar->id.bmi_chip_id = chip_id;
1073
a4b9f641
VP		 1074skip_otp_download:
1075
db0984e5
MP		 1076 return 0;
1077}
1078
1657b8f8
WR		 1079static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data)
1080{
1081 struct ath10k *ar = data;
1082 const char *bdf_ext;
1083 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC;
1084 u8 bdf_enabled;
1085 int i;
1086
1087 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE)
1088 return;
1089
1090 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) {
1091 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1092 "wrong smbios bdf ext type length (%d).\n",
1093 hdr->length);
1094 return;
1095 }
1096
1097 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET);
1098 if (!bdf_enabled) {
1099 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n");
1100 return;
1101 }
1102
1103 /* Only one string exists (per spec) */
1104 bdf_ext = (char *)hdr + hdr->length;
1105
1106 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) {
1107 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1108 "bdf variant magic does not match.\n");
1109 return;
1110 }
1111
1112 for (i = 0; i < strlen(bdf_ext); i++) {
1113 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) {
1114 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1115 "bdf variant name contains non ascii chars.\n");
1116 return;
1117 }
1118 }
1119
1120 /* Copy extension name without magic suffix */
1121 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic),
1122 sizeof(ar->id.bdf_ext)) < 0) {
1123 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1124 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1125 bdf_ext);
1126 return;
1127 }
1128
1129 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1130 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
1131 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext);
1132}
1133
1134static int ath10k_core_check_smbios(struct ath10k *ar)
1135{
1136 ar->id.bdf_ext[0] = '\0';
1137 dmi_walk(ath10k_core_check_bdfext, ar);
1138
1139 if (ar->id.bdf_ext[0] == '\0')
1140 return -ENODATA;
1141
1142 return 0;
1143}
1144
4e938105 1145int ath10k_core_check_dt(struct ath10k *ar)
d06f26c5
SE		 1146{
1147 struct device_node *node;
1148 const char *variant = NULL;
1149
1150 node = ar->dev->of_node;
1151 if (!node)
1152 return -ENOENT;
1153
1154 of_property_read_string(node, "qcom,ath10k-calibration-variant",
1155 &variant);
1156 if (!variant)
1157 return -ENODATA;
1158
1159 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0)
1160 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1161 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1162 variant);
1163
1164 return 0;
1165}
4e938105 1166EXPORT_SYMBOL(ath10k_core_check_dt);
d06f26c5 1167
7ebf721d 1168static int ath10k_download_fw(struct ath10k *ar)
5e3dd157 1169{
43d2a30f 1170 u32 address, data_len;
43d2a30f 1171 const void *data;
5e3dd157 1172 int ret;
3b58d6a5 1173 struct pm_qos_request latency_qos;
5e3dd157 1174
5e3dd157
KV		 1175 address = ar->hw_params.patch_load_addr;
1176
7ebf721d
KV		 1177 data = ar->running_fw->fw_file.firmware_data;
1178 data_len = ar->running_fw->fw_file.firmware_len;
1179
5459c5d4 1180 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file);
7ebf721d
KV		 1181 if (ret) {
1182 ath10k_err(ar, "failed to configure fw code swap: %d\n",
1183 ret);
1184 return ret;
43d2a30f
KV		 1185 }
1186
1187 ath10k_dbg(ar, ATH10K_DBG_BOOT,
75b34800 1188 "boot uploading firmware image %pK len %d\n",
7ebf721d 1189 data, data_len);
43d2a30f 1190
39501ea6
CH		 1191 /* Check if device supports to download firmware via
1192 * diag copy engine. Downloading firmware via diag CE
1193 * greatly reduces the time to download firmware.
1194 */
1195 if (ar->hw_params.fw_diag_ce_download) {
1196 ret = ath10k_hw_diag_fast_download(ar, address,
1197 data, data_len);
1198 if (ret == 0)
1199 /* firmware upload via diag ce was successful */
1200 return 0;
1201
1202 ath10k_warn(ar,
1203 "failed to upload firmware via diag ce, trying BMI: %d",
1204 ret);
5e3dd157
KV		 1205 }
1206
3b58d6a5 1207 memset(&latency_qos, 0, sizeof(latency_qos));
81e95ad7 1208 cpu_latency_qos_add_request(&latency_qos, 0);
3b58d6a5
IJ		 1209
1210 ret = ath10k_bmi_fast_download(ar, address, data, data_len);
1211
81e95ad7 1212 cpu_latency_qos_remove_request(&latency_qos);
3b58d6a5
IJ		 1213
1214 return ret;
29385057
MK		 1215}
1216
ba94c753 1217void ath10k_core_free_board_files(struct ath10k *ar)
29385057 1218{
7ebf721d
KV		 1219 if (!IS_ERR(ar->normal_mode_fw.board))
1220 release_firmware(ar->normal_mode_fw.board);
29385057 1221
31324d17
SM		 1222 if (!IS_ERR(ar->normal_mode_fw.ext_board))
1223 release_firmware(ar->normal_mode_fw.ext_board);
1224
7ebf721d
KV		 1225 ar->normal_mode_fw.board = NULL;
1226 ar->normal_mode_fw.board_data = NULL;
1227 ar->normal_mode_fw.board_len = 0;
31324d17
SM		 1228 ar->normal_mode_fw.ext_board = NULL;
1229 ar->normal_mode_fw.ext_board_data = NULL;
1230 ar->normal_mode_fw.ext_board_len = 0;
0a51b343 1231}
ba94c753 1232EXPORT_SYMBOL(ath10k_core_free_board_files);
0a51b343
MP		 1233
1234static void ath10k_core_free_firmware_files(struct ath10k *ar)
1235{
7ebf721d
KV		 1236 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware))
1237 release_firmware(ar->normal_mode_fw.fw_file.firmware);
29385057 1238
db2cf865 1239 if (!IS_ERR(ar->cal_file))
a58227ef
KV		 1240 release_firmware(ar->cal_file);
1241
9a5f91a1
RM		 1242 if (!IS_ERR(ar->pre_cal_file))
1243 release_firmware(ar->pre_cal_file);
1244
5459c5d4 1245 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file);
dcb02db1 1246
7ebf721d
KV		 1247 ar->normal_mode_fw.fw_file.otp_data = NULL;
1248 ar->normal_mode_fw.fw_file.otp_len = 0;
958df3a0 1249
7ebf721d
KV		 1250 ar->normal_mode_fw.fw_file.firmware = NULL;
1251 ar->normal_mode_fw.fw_file.firmware_data = NULL;
1252 ar->normal_mode_fw.fw_file.firmware_len = 0;
a58227ef
KV		 1253
1254 ar->cal_file = NULL;
9a5f91a1 1255 ar->pre_cal_file = NULL;
a58227ef
KV		 1256}
1257
1258static int ath10k_fetch_cal_file(struct ath10k *ar)
1259{
1260 char filename[100];
1261
3d9195ea
RM		 1262 /* pre-cal-<bus>-<id>.bin */
1263 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin",
1264 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1265
1266 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
1267 if (!IS_ERR(ar->pre_cal_file))
1268 goto success;
1269
a58227ef
KV		 1270 /* cal-<bus>-<id>.bin */
1271 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
1272 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1273
1274 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
1275 if (IS_ERR(ar->cal_file))
1276 /* calibration file is optional, don't print any warnings */
1277 return PTR_ERR(ar->cal_file);
3d9195ea 1278success:
a58227ef
KV		 1279 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
1280 ATH10K_FW_DIR, filename);
1281
1282 return 0;
29385057
MK		 1283}
1284
31324d17 1285static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type)
29385057 1286{
31324d17 1287 const struct firmware *fw;
f2a7064a 1288 char boardname[100];
de57e2c8 1289
31324d17
SM		 1290 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1291 if (!ar->hw_params.fw.board) {
1292 ath10k_err(ar, "failed to find board file fw entry\n");
1293 return -EINVAL;
1294 }
1295
f2a7064a
RM		 1296 scnprintf(boardname, sizeof(boardname), "board-%s-%s.bin",
1297 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1298
31324d17
SM		 1299 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
1300 ar->hw_params.fw.dir,
f2a7064a
RM		 1301 boardname);
1302 if (IS_ERR(ar->normal_mode_fw.board)) {
1303 fw = ath10k_fetch_fw_file(ar,
1304 ar->hw_params.fw.dir,
1305 ar->hw_params.fw.board);
1306 ar->normal_mode_fw.board = fw;
1307 }
1308
31324d17
SM		 1309 if (IS_ERR(ar->normal_mode_fw.board))
1310 return PTR_ERR(ar->normal_mode_fw.board);
1311
1312 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data;
1313 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size;
1314 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1315 if (!ar->hw_params.fw.eboard) {
1316 ath10k_err(ar, "failed to find eboard file fw entry\n");
1317 return -EINVAL;
1318 }
de57e2c8 1319
31324d17
SM		 1320 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
1321 ar->hw_params.fw.eboard);
1322 ar->normal_mode_fw.ext_board = fw;
1323 if (IS_ERR(ar->normal_mode_fw.ext_board))
1324 return PTR_ERR(ar->normal_mode_fw.ext_board);
1325
1326 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data;
1327 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size;
1328 }
29385057 1329
de57e2c8
MK		 1330 return 0;
1331}
1332
0a51b343
MP		 1333static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
1334 const void *buf, size_t buf_len,
31324d17
SM		 1335 const char *boardname,
1336 int bd_ie_type)
de57e2c8 1337{
0a51b343
MP		 1338 const struct ath10k_fw_ie *hdr;
1339 bool name_match_found;
1340 int ret, board_ie_id;
1341 size_t board_ie_len;
1342 const void *board_ie_data;
1343
1344 name_match_found = false;
1345
1346 /* go through ATH10K_BD_IE_BOARD_ elements */
1347 while (buf_len > sizeof(struct ath10k_fw_ie)) {
1348 hdr = buf;
1349 board_ie_id = le32_to_cpu(hdr->id);
1350 board_ie_len = le32_to_cpu(hdr->len);
1351 board_ie_data = hdr->data;
1352
1353 buf_len -= sizeof(*hdr);
1354 buf += sizeof(*hdr);
1355
1356 if (buf_len < ALIGN(board_ie_len, 4)) {
1357 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
1358 buf_len, ALIGN(board_ie_len, 4));
1359 ret = -EINVAL;
1360 goto out;
1361 }
1362
1363 switch (board_ie_id) {
1364 case ATH10K_BD_IE_BOARD_NAME:
1365 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
1366 board_ie_data, board_ie_len);
1367
1368 if (board_ie_len != strlen(boardname))
1369 break;
1370
1371 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1372 if (ret)
1373 break;
1374
1375 name_match_found = true;
1376 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1377 "boot found match for name '%s'",
1378 boardname);
1379 break;
1380 case ATH10K_BD_IE_BOARD_DATA:
1381 if (!name_match_found)
1382 /* no match found */
1383 break;
1384
31324d17
SM		 1385 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1386 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1387 "boot found board data for '%s'",
1388 boardname);
0a51b343 1389
31324d17
SM		 1390 ar->normal_mode_fw.board_data = board_ie_data;
1391 ar->normal_mode_fw.board_len = board_ie_len;
1392 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1393 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1394 "boot found eboard data for '%s'",
1395 boardname);
1396
1397 ar->normal_mode_fw.ext_board_data = board_ie_data;
1398 ar->normal_mode_fw.ext_board_len = board_ie_len;
1399 }
0a51b343
MP		 1400
1401 ret = 0;
1402 goto out;
1403 default:
1404 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
1405 board_ie_id);
1406 break;
1407 }
1408
1409 /* jump over the padding */
1410 board_ie_len = ALIGN(board_ie_len, 4);
1411
1412 buf_len -= board_ie_len;
1413 buf += board_ie_len;
29385057
MK		 1414 }
1415
0a51b343
MP		 1416 /* no match found */
1417 ret = -ENOENT;
1418
1419out:
1420 return ret;
1421}
1422
c8489668
TH		 1423static int ath10k_core_search_bd(struct ath10k *ar,
1424 const char *boardname,
1425 const u8 *data,
1426 size_t len)
1427{
1428 size_t ie_len;
1429 struct ath10k_fw_ie *hdr;
1430 int ret = -ENOENT, ie_id;
1431
1432 while (len > sizeof(struct ath10k_fw_ie)) {
1433 hdr = (struct ath10k_fw_ie *)data;
1434 ie_id = le32_to_cpu(hdr->id);
1435 ie_len = le32_to_cpu(hdr->len);
1436
1437 len -= sizeof(*hdr);
1438 data = hdr->data;
1439
1440 if (len < ALIGN(ie_len, 4)) {
1441 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1442 ie_id, ie_len, len);
1443 return -EINVAL;
1444 }
1445
1446 switch (ie_id) {
1447 case ATH10K_BD_IE_BOARD:
1448 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
31324d17
SM		 1449 boardname,
1450 ATH10K_BD_IE_BOARD);
1451 if (ret == -ENOENT)
1452 /* no match found, continue */
1453 break;
1454
1455 /* either found or error, so stop searching */
1456 goto out;
1457 case ATH10K_BD_IE_BOARD_EXT:
1458 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
1459 boardname,
1460 ATH10K_BD_IE_BOARD_EXT);
c8489668
TH		 1461 if (ret == -ENOENT)
1462 /* no match found, continue */
1463 break;
1464
1465 /* either found or error, so stop searching */
1466 goto out;
1467 }
1468
1469 /* jump over the padding */
1470 ie_len = ALIGN(ie_len, 4);
1471
1472 len -= ie_len;
1473 data += ie_len;
1474 }
1475
1476out:
1477 /* return result of parse_bd_ie_board() or -ENOENT */
1478 return ret;
1479}
1480
0a51b343
MP		 1481static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
1482 const char *boardname,
2bc2b87b
AK		 1483 const char *fallback_boardname1,
1484 const char *fallback_boardname2,
0a51b343
MP		 1485 const char *filename)
1486{
c8489668 1487 size_t len, magic_len;
0a51b343 1488 const u8 *data;
c8489668 1489 int ret;
0a51b343 1490
31324d17
SM		 1491 /* Skip if already fetched during board data download */
1492 if (!ar->normal_mode_fw.board)
1493 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
1494 ar->hw_params.fw.dir,
1495 filename);
7ebf721d
KV		 1496 if (IS_ERR(ar->normal_mode_fw.board))
1497 return PTR_ERR(ar->normal_mode_fw.board);
29385057 1498
7ebf721d
KV		 1499 data = ar->normal_mode_fw.board->data;
1500 len = ar->normal_mode_fw.board->size;
0a51b343
MP		 1501
1502 /* magic has extra null byte padded */
1503 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
1504 if (len < magic_len) {
1505 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
1506 ar->hw_params.fw.dir, filename, len);
1507 ret = -EINVAL;
1508 goto err;
1509 }
1510
1511 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
1512 ath10k_err(ar, "found invalid board magic\n");
1513 ret = -EINVAL;
1514 goto err;
1515 }
1516
1517 /* magic is padded to 4 bytes */
1518 magic_len = ALIGN(magic_len, 4);
1519 if (len < magic_len) {
1520 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
1521 ar->hw_params.fw.dir, filename, len);
1522 ret = -EINVAL;
1523 goto err;
1524 }
1525
1526 data += magic_len;
1527 len -= magic_len;
1528
c8489668
TH		 1529 /* attempt to find boardname in the IE list */
1530 ret = ath10k_core_search_bd(ar, boardname, data, len);
0a51b343 1531
c8489668 1532 /* if we didn't find it and have a fallback name, try that */
2bc2b87b
AK		 1533 if (ret == -ENOENT && fallback_boardname1)
1534 ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len);
1535
1536 if (ret == -ENOENT && fallback_boardname2)
1537 ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len);
0a51b343 1538
c8489668 1539 if (ret == -ENOENT) {
0a51b343
MP		 1540 ath10k_err(ar,
1541 "failed to fetch board data for %s from %s/%s\n",
bd5632b0 1542 boardname, ar->hw_params.fw.dir, filename);
0a51b343 1543 ret = -ENODATA;
0a51b343
MP		 1544 }
1545
c8489668
TH		 1546 if (ret)
1547 goto err;
1548
0a51b343
MP		 1549 return 0;
1550
1551err:
1552 ath10k_core_free_board_files(ar);
1553 return ret;
1554}
1555
1556static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
2bc2b87b
AK		 1557 size_t name_len, bool with_variant,
1558 bool with_chip_id)
0a51b343 1559{
1657b8f8
WR		 1560 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */
1561 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 };
1562
c8489668 1563 if (with_variant && ar->id.bdf_ext[0] != '\0')
d06f26c5
SE		 1564 scnprintf(variant, sizeof(variant), ",variant=%s",
1565 ar->id.bdf_ext);
1566
db0984e5
MP		 1567 if (ar->id.bmi_ids_valid) {
1568 scnprintf(name, name_len,
d06f26c5 1569 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s",
db0984e5
MP		 1570 ath10k_bus_str(ar->hif.bus),
1571 ar->id.bmi_chip_id,
d06f26c5 1572 ar->id.bmi_board_id, variant);
db0984e5
MP		 1573 goto out;
1574 }
1575
22e8a460 1576 if (ar->id.qmi_ids_valid) {
2bc2b87b 1577 if (with_chip_id)
4e938105
RP		 1578 scnprintf(name, name_len,
1579 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s",
1580 ath10k_bus_str(ar->hif.bus),
1581 ar->id.qmi_board_id, ar->id.qmi_chip_id,
1582 variant);
1583 else
1584 scnprintf(name, name_len,
1585 "bus=%s,qmi-board-id=%x",
1586 ath10k_bus_str(ar->hif.bus),
1587 ar->id.qmi_board_id);
22e8a460
RP		 1588 goto out;
1589 }
1590
0a51b343 1591 scnprintf(name, name_len,
1657b8f8 1592 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s",
0a51b343
MP		 1593 ath10k_bus_str(ar->hif.bus),
1594 ar->id.vendor, ar->id.device,
1657b8f8 1595 ar->id.subsystem_vendor, ar->id.subsystem_device, variant);
db0984e5 1596out:
0a51b343 1597 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
de57e2c8
MK		 1598
1599 return 0;
1600}
1601
31324d17
SM		 1602static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name,
1603 size_t name_len)
1604{
1605 if (ar->id.bmi_ids_valid) {
1606 scnprintf(name, name_len,
1607 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d",
1608 ath10k_bus_str(ar->hif.bus),
1609 ar->id.bmi_chip_id,
1610 ar->id.bmi_eboard_id);
1611
1612 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name);
1613 return 0;
1614 }
1615 /* Fallback if returned board id is zero */
1616 return -1;
1617}
1618
ba94c753 1619int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type)
de57e2c8 1620{
2bc2b87b 1621 char boardname[100], fallback_boardname1[100], fallback_boardname2[100];
de57e2c8
MK		 1622 int ret;
1623
31324d17 1624 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
2bc2b87b 1625 /* With variant and chip id */
31324d17 1626 ret = ath10k_core_create_board_name(ar, boardname,
2bc2b87b
AK		 1627 sizeof(boardname), true,
1628 true);
31324d17
SM		 1629 if (ret) {
1630 ath10k_err(ar, "failed to create board name: %d", ret);
1631 return ret;
1632 }
de57e2c8 1633
2bc2b87b
AK		 1634 /* Without variant and only chip-id */
1635 ret = ath10k_core_create_board_name(ar, fallback_boardname1,
1636 sizeof(boardname), false,
1637 true);
1638 if (ret) {
1639 ath10k_err(ar, "failed to create 1st fallback board name: %d",
1640 ret);
1641 return ret;
1642 }
1643
1644 /* Without variant and without chip-id */
1645 ret = ath10k_core_create_board_name(ar, fallback_boardname2,
1646 sizeof(boardname), false,
1647 false);
31324d17 1648 if (ret) {
2bc2b87b
AK		 1649 ath10k_err(ar, "failed to create 2nd fallback board name: %d",
1650 ret);
31324d17
SM		 1651 return ret;
1652 }
1653 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1654 ret = ath10k_core_create_eboard_name(ar, boardname,
1655 sizeof(boardname));
1656 if (ret) {
1657 ath10k_err(ar, "fallback to eboard.bin since board id 0");
1658 goto fallback;
1659 }
c8489668
TH		 1660 }
1661
0a51b343
MP		 1662 ar->bd_api = 2;
1663 ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
2bc2b87b
AK		 1664 fallback_boardname1,
1665 fallback_boardname2,
0a51b343
MP		 1666 ATH10K_BOARD_API2_FILE);
1667 if (!ret)
1668 goto success;
1669
31324d17 1670fallback:
0a51b343 1671 ar->bd_api = 1;
31324d17 1672 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type);
de57e2c8 1673 if (ret) {
310c01af
KV		 1674 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n",
1675 ar->hw_params.fw.dir);
de57e2c8
MK		 1676 return ret;
1677 }
958df3a0 1678
0a51b343
MP		 1679success:
1680 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
d0ed74f3
MK		 1681 return 0;
1682}
ba94c753 1683EXPORT_SYMBOL(ath10k_core_fetch_board_file);
d0ed74f3 1684
31324d17
SM		 1685static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar)
1686{
1687 u32 result, address;
1688 u8 ext_board_id;
1689 int ret;
1690
1691 address = ar->hw_params.patch_load_addr;
1692
1693 if (!ar->normal_mode_fw.fw_file.otp_data ||
1694 !ar->normal_mode_fw.fw_file.otp_len) {
1695 ath10k_warn(ar,
1696 "failed to retrieve extended board id due to otp binary missing\n");
1697 return -ENODATA;
1698 }
1699
1700 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1701 "boot upload otp to 0x%x len %zd for ext board id\n",
1702 address, ar->normal_mode_fw.fw_file.otp_len);
1703
1704 ret = ath10k_bmi_fast_download(ar, address,
1705 ar->normal_mode_fw.fw_file.otp_data,
1706 ar->normal_mode_fw.fw_file.otp_len);
1707 if (ret) {
1708 ath10k_err(ar, "could not write otp for ext board id check: %d\n",
1709 ret);
1710 return ret;
1711 }
1712
1713 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result);
1714 if (ret) {
1715 ath10k_err(ar, "could not execute otp for ext board id check: %d\n",
1716 ret);
1717 return ret;
1718 }
1719
1720 if (!result) {
1721 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1722 "ext board id does not exist in otp, ignore it\n");
1723 return -EOPNOTSUPP;
1724 }
1725
1726 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK;
1727
1728 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1729 "boot get otp ext board id result 0x%08x ext_board_id %d\n",
1730 result, ext_board_id);
1731
1732 ar->id.bmi_eboard_id = ext_board_id;
1733
1734 return 0;
1735}
1736
5849ed48
SM		 1737static int ath10k_download_board_data(struct ath10k *ar, const void *data,
1738 size_t data_len)
1739{
1740 u32 board_data_size = ar->hw_params.fw.board_size;
31324d17
SM		 1741 u32 eboard_data_size = ar->hw_params.fw.ext_board_size;
1742 u32 board_address;
1743 u32 ext_board_address;
5849ed48
SM		 1744 int ret;
1745
1746 ret = ath10k_push_board_ext_data(ar, data, data_len);
1747 if (ret) {
1748 ath10k_err(ar, "could not push board ext data (%d)\n", ret);
1749 goto exit;
1750 }
1751
31324d17 1752 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address);
5849ed48
SM		 1753 if (ret) {
1754 ath10k_err(ar, "could not read board data addr (%d)\n", ret);
1755 goto exit;
1756 }
1757
31324d17 1758 ret = ath10k_bmi_write_memory(ar, board_address, data,
5849ed48
SM		 1759 min_t(u32, board_data_size,
1760 data_len));
1761 if (ret) {
1762 ath10k_err(ar, "could not write board data (%d)\n", ret);
1763 goto exit;
1764 }
1765
1766 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
1767 if (ret) {
1768 ath10k_err(ar, "could not write board data bit (%d)\n", ret);
1769 goto exit;
1770 }
1771
31324d17
SM		 1772 if (!ar->id.ext_bid_supported)
1773 goto exit;
1774
1775 /* Extended board data download */
1776 ret = ath10k_core_get_ext_board_id_from_otp(ar);
1777 if (ret == -EOPNOTSUPP) {
1778 /* Not fetching ext_board_data if ext board id is 0 */
1779 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n");
1780 return 0;
1781 } else if (ret) {
1782 ath10k_err(ar, "failed to get extended board id: %d\n", ret);
1783 goto exit;
1784 }
1785
1786 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT);
1787 if (ret)
1788 goto exit;
1789
1790 if (ar->normal_mode_fw.ext_board_data) {
1791 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET;
1792 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1793 "boot writing ext board data to addr 0x%x",
1794 ext_board_address);
1795 ret = ath10k_bmi_write_memory(ar, ext_board_address,
1796 ar->normal_mode_fw.ext_board_data,
1797 min_t(u32, eboard_data_size, data_len));
1798 if (ret)
1799 ath10k_err(ar, "failed to write ext board data: %d\n", ret);
1800 }
1801
5849ed48
SM		 1802exit:
1803 return ret;
1804}
1805
1806static int ath10k_download_and_run_otp(struct ath10k *ar)
1807{
1808 u32 result, address = ar->hw_params.patch_load_addr;
1809 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
1810 int ret;
1811
1812 ret = ath10k_download_board_data(ar,
1813 ar->running_fw->board_data,
1814 ar->running_fw->board_len);
1815 if (ret) {
1816 ath10k_err(ar, "failed to download board data: %d\n", ret);
1817 return ret;
1818 }
1819
1820 /* OTP is optional */
1821
1822 if (!ar->running_fw->fw_file.otp_data ||
1823 !ar->running_fw->fw_file.otp_len) {
1824 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n",
1825 ar->running_fw->fw_file.otp_data,
1826 ar->running_fw->fw_file.otp_len);
1827 return 0;
1828 }
1829
1830 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
1831 address, ar->running_fw->fw_file.otp_len);
1832
1833 ret = ath10k_bmi_fast_download(ar, address,
1834 ar->running_fw->fw_file.otp_data,
1835 ar->running_fw->fw_file.otp_len);
1836 if (ret) {
1837 ath10k_err(ar, "could not write otp (%d)\n", ret);
1838 return ret;
1839 }
1840
1841 /* As of now pre-cal is valid for 10_4 variants */
1842 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
27deb0f1
CL		 1843 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||
1844 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)
5849ed48
SM		 1845 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL;
1846
1847 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
1848 if (ret) {
1849 ath10k_err(ar, "could not execute otp (%d)\n", ret);
1850 return ret;
1851 }
1852
1853 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
1854
1855 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
1856 ar->running_fw->fw_file.fw_features)) &&
1857 result != 0) {
1858 ath10k_err(ar, "otp calibration failed: %d", result);
1859 return -EINVAL;
1860 }
1861
1862 return 0;
1863}
1864
1865static int ath10k_download_cal_file(struct ath10k *ar,
1866 const struct firmware *file)
1867{
1868 int ret;
1869
1870 if (!file)
1871 return -ENOENT;
1872
1873 if (IS_ERR(file))
1874 return PTR_ERR(file);
1875
1876 ret = ath10k_download_board_data(ar, file->data, file->size);
1877 if (ret) {
1878 ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
1879 return ret;
1880 }
1881
1882 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
1883
1884 return 0;
1885}
1886
1887static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name)
1888{
1889 struct device_node *node;
1890 int data_len;
1891 void *data;
1892 int ret;
1893
1894 node = ar->dev->of_node;
1895 if (!node)
1896 /* Device Tree is optional, don't print any warnings if
1897 * there's no node for ath10k.
1898 */
1899 return -ENOENT;
1900
1901 if (!of_get_property(node, dt_name, &data_len)) {
1902 /* The calibration data node is optional */
1903 return -ENOENT;
1904 }
1905
1906 if (data_len != ar->hw_params.cal_data_len) {
1907 ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
1908 data_len);
1909 ret = -EMSGSIZE;
1910 goto out;
1911 }
1912
1913 data = kmalloc(data_len, GFP_KERNEL);
1914 if (!data) {
1915 ret = -ENOMEM;
1916 goto out;
1917 }
1918
1919 ret = of_property_read_u8_array(node, dt_name, data, data_len);
1920 if (ret) {
1921 ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
1922 ret);
1923 goto out_free;
1924 }
1925
1926 ret = ath10k_download_board_data(ar, data, data_len);
1927 if (ret) {
1928 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
1929 ret);
1930 goto out_free;
1931 }
1932
1933 ret = 0;
1934
1935out_free:
1936 kfree(data);
1937
1938out:
1939 return ret;
1940}
1941
1942static int ath10k_download_cal_eeprom(struct ath10k *ar)
1943{
1944 size_t data_len;
1945 void *data = NULL;
1946 int ret;
1947
1948 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len);
1949 if (ret) {
1950 if (ret != -EOPNOTSUPP)
1951 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n",
1952 ret);
1953 goto out_free;
1954 }
1955
1956 ret = ath10k_download_board_data(ar, data, data_len);
1957 if (ret) {
1958 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n",
1959 ret);
1960 goto out_free;
1961 }
1962
1963 ret = 0;
1964
1965out_free:
1966 kfree(data);
1967
1968 return ret;
1969}
1970
27deb0f1
CL		 1971static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name)
1972{
1973 struct nvmem_cell *cell;
1974 void *buf;
1975 size_t len;
1976 int ret;
1977
1978 cell = devm_nvmem_cell_get(ar->dev, cell_name);
1979 if (IS_ERR(cell)) {
1980 ret = PTR_ERR(cell);
1981 return ret;
1982 }
1983
1984 buf = nvmem_cell_read(cell, &len);
1985 if (IS_ERR(buf))
1986 return PTR_ERR(buf);
1987
1988 if (ar->hw_params.cal_data_len != len) {
1989 kfree(buf);
1990 ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n",
1991 cell_name, len, ar->hw_params.cal_data_len);
1992 return -EMSGSIZE;
1993 }
1994
1995 ret = ath10k_download_board_data(ar, buf, len);
1996 kfree(buf);
1997 if (ret)
1998 ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n",
1999 cell_name, ret);
2000
2001 return ret;
2002}
2003
9dfe240b
KV		 2004int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
2005 struct ath10k_fw_file *fw_file)
1a222435
KV		 2006{
2007 size_t magic_len, len, ie_len;
2008 int ie_id, i, index, bit, ret;
2009 struct ath10k_fw_ie *hdr;
2010 const u8 *data;
202e86e6 2011 __le32 *timestamp, *version;
1a222435
KV		 2012
2013 /* first fetch the firmware file (firmware-*.bin) */
7ebf721d
KV		 2014 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
2015 name);
9f5bcfe9 2016 if (IS_ERR(fw_file->firmware))
7ebf721d 2017 return PTR_ERR(fw_file->firmware);
1a222435 2018
7ebf721d
KV		 2019 data = fw_file->firmware->data;
2020 len = fw_file->firmware->size;
1a222435
KV		 2021
2022 /* magic also includes the null byte, check that as well */
2023 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
2024
2025 if (len < magic_len) {
7aa7a72a 2026 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
53c02284 2027 ar->hw_params.fw.dir, name, len);
9bab1cc0
MK		 2028 ret = -EINVAL;
2029 goto err;
1a222435
KV		 2030 }
2031
2032 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
7aa7a72a 2033 ath10k_err(ar, "invalid firmware magic\n");
9bab1cc0
MK		 2034 ret = -EINVAL;
2035 goto err;
1a222435
KV		 2036 }
2037
2038 /* jump over the padding */
2039 magic_len = ALIGN(magic_len, 4);
2040
2041 len -= magic_len;
2042 data += magic_len;
2043
2044 /* loop elements */
2045 while (len > sizeof(struct ath10k_fw_ie)) {
2046 hdr = (struct ath10k_fw_ie *)data;
2047
2048 ie_id = le32_to_cpu(hdr->id);
2049 ie_len = le32_to_cpu(hdr->len);
2050
2051 len -= sizeof(*hdr);
2052 data += sizeof(*hdr);
2053
2054 if (len < ie_len) {
7aa7a72a 2055 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
1a222435 2056 ie_id, len, ie_len);
9bab1cc0
MK		 2057 ret = -EINVAL;
2058 goto err;
1a222435
KV		 2059 }
2060
2061 switch (ie_id) {
2062 case ATH10K_FW_IE_FW_VERSION:
45317355 2063 if (ie_len > sizeof(fw_file->fw_version) - 1)
1a222435
KV		 2064 break;
2065
45317355
KV		 2066 memcpy(fw_file->fw_version, data, ie_len);
2067 fw_file->fw_version[ie_len] = '\0';
1a222435 2068
7aa7a72a 2069 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1a222435 2070 "found fw version %s\n",
45317355 2071 fw_file->fw_version);
1a222435
KV		 2072 break;
2073 case ATH10K_FW_IE_TIMESTAMP:
2074 if (ie_len != sizeof(u32))
2075 break;
2076
2077 timestamp = (__le32 *)data;
2078
7aa7a72a 2079 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
1a222435
KV		 2080 le32_to_cpup(timestamp));
2081 break;
2082 case ATH10K_FW_IE_FEATURES:
7aa7a72a 2083 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1a222435
KV		 2084 "found firmware features ie (%zd B)\n",
2085 ie_len);
2086
2087 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
2088 index = i / 8;
2089 bit = i % 8;
2090
2091 if (index == ie_len)
2092 break;
2093
f591a1a5 2094 if (data[index] & (1 << bit)) {
7aa7a72a 2095 ath10k_dbg(ar, ATH10K_DBG_BOOT,
f591a1a5
BG		 2096 "Enabling feature bit: %i\n",
2097 i);
c4cdf753 2098 __set_bit(i, fw_file->fw_features);
f591a1a5 2099 }
1a222435
KV		 2100 }
2101
7aa7a72a 2102 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
8d0a0710 2103 fw_file->fw_features,
c4cdf753 2104 sizeof(fw_file->fw_features));
1a222435
KV		 2105 break;
2106 case ATH10K_FW_IE_FW_IMAGE:
7aa7a72a 2107 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1a222435
KV		 2108 "found fw image ie (%zd B)\n",
2109 ie_len);
2110
7ebf721d
KV		 2111 fw_file->firmware_data = data;
2112 fw_file->firmware_len = ie_len;
1a222435
KV		 2113
2114 break;
2115 case ATH10K_FW_IE_OTP_IMAGE:
7aa7a72a 2116 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1a222435
KV		 2117 "found otp image ie (%zd B)\n",
2118 ie_len);
2119
7ebf721d
KV		 2120 fw_file->otp_data = data;
2121 fw_file->otp_len = ie_len;
1a222435
KV		 2122
2123 break;
202e86e6
KV		 2124 case ATH10K_FW_IE_WMI_OP_VERSION:
2125 if (ie_len != sizeof(u32))
2126 break;
2127
2128 version = (__le32 *)data;
2129
bf3c13ab 2130 fw_file->wmi_op_version = le32_to_cpup(version);
202e86e6
KV		 2131
2132 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
bf3c13ab 2133 fw_file->wmi_op_version);
202e86e6 2134 break;
8348db29
RM		 2135 case ATH10K_FW_IE_HTT_OP_VERSION:
2136 if (ie_len != sizeof(u32))
2137 break;
2138
2139 version = (__le32 *)data;
2140
77561f93 2141 fw_file->htt_op_version = le32_to_cpup(version);
8348db29
RM		 2142
2143 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
77561f93 2144 fw_file->htt_op_version);
8348db29 2145 break;
dcb02db1
VT		 2146 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
2147 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2148 "found fw code swap image ie (%zd B)\n",
2149 ie_len);
7ebf721d
KV		 2150 fw_file->codeswap_data = data;
2151 fw_file->codeswap_len = ie_len;
dcb02db1 2152 break;
1a222435 2153 default:
7aa7a72a 2154 ath10k_warn(ar, "Unknown FW IE: %u\n",
1a222435
KV		 2155 le32_to_cpu(hdr->id));
2156 break;
2157 }
2158
9ce8b24a
RH		 2159 /* jump over the padding */
2160 ie_len = ALIGN(ie_len, 4);
2161
1a222435
KV		 2162 len -= ie_len;
2163 data += ie_len;
e05634ee 2164 }
1a222435 2165
71e9c29f
RP		 2166 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) &&
2167 (!fw_file->firmware_data || !fw_file->firmware_len)) {
7aa7a72a 2168 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
53c02284 2169 ar->hw_params.fw.dir, name);
1a222435
KV		 2170 ret = -ENOMEDIUM;
2171 goto err;
2172 }
2173
1a222435
KV		 2174 return 0;
2175
2176err:
2177 ath10k_core_free_firmware_files(ar);
2178 return ret;
2179}
2180
1c61bedc
ES		 2181static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name,
2182 size_t fw_name_len, int fw_api)
2183{
f008d153
ES		 2184 switch (ar->hif.bus) {
2185 case ATH10K_BUS_SDIO:
b00435e6 2186 case ATH10K_BUS_USB:
f008d153
ES		 2187 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin",
2188 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus),
2189 fw_api);
2190 break;
2191 case ATH10K_BUS_PCI:
2192 case ATH10K_BUS_AHB:
63855e3d 2193 case ATH10K_BUS_SNOC:
f008d153
ES		 2194 scnprintf(fw_name, fw_name_len, "%s-%d.bin",
2195 ATH10K_FW_FILE_BASE, fw_api);
2196 break;
2197 }
1c61bedc
ES		 2198}
2199
1a222435
KV		 2200static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
2201{
1c61bedc
ES		 2202 int ret, i;
2203 char fw_name[100];
1a222435 2204
a58227ef
KV		 2205 /* calibration file is optional, don't check for any errors */
2206 ath10k_fetch_cal_file(ar);
2207
1c61bedc
ES		 2208 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) {
2209 ar->fw_api = i;
2210 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n",
2211 ar->fw_api);
53513c30 2212
1c61bedc
ES		 2213 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api);
2214 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name,
2215 &ar->normal_mode_fw.fw_file);
2216 if (!ret)
2217 goto success;
2218 }
24c88f78 2219
1c61bedc 2220 /* we end up here if we couldn't fetch any firmware */
24c88f78 2221
1c61bedc
ES		 2222 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d",
2223 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir,
2224 ret);
53c02284 2225
1c61bedc 2226 return ret;
1a222435 2227
53c02284 2228success:
7aa7a72a 2229 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
1a222435
KV		 2230
2231 return 0;
2232}
2233
3d9195ea
RM		 2234static int ath10k_core_pre_cal_download(struct ath10k *ar)
2235{
2236 int ret;
2237
27deb0f1
CL		 2238 ret = ath10k_download_cal_nvmem(ar, "pre-calibration");
2239 if (ret == 0) {
2240 ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM;
2241 goto success;
2242 } else if (ret == -EPROBE_DEFER) {
2243 return ret;
2244 }
2245
2246 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2247 "boot did not find a pre-calibration nvmem-cell, try file next: %d\n",
2248 ret);
2249
3d9195ea
RM		 2250 ret = ath10k_download_cal_file(ar, ar->pre_cal_file);
2251 if (ret == 0) {
2252 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;
2253 goto success;
2254 }
2255
2256 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2257 "boot did not find a pre calibration file, try DT next: %d\n",
2258 ret);
2259
2260 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data");
2261 if (ret) {
2262 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2263 "unable to load pre cal data from DT: %d\n", ret);
2264 return ret;
2265 }
2266 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT;
2267
2268success:
2269 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
2270 ath10k_cal_mode_str(ar->cal_mode));
2271
2272 return 0;
2273}
2274
2275static int ath10k_core_pre_cal_config(struct ath10k *ar)
2276{
2277 int ret;
2278
2279 ret = ath10k_core_pre_cal_download(ar);
2280 if (ret) {
2281 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2282 "failed to load pre cal data: %d\n", ret);
2283 return ret;
2284 }
2285
2286 ret = ath10k_core_get_board_id_from_otp(ar);
2287 if (ret) {
2288 ath10k_err(ar, "failed to get board id: %d\n", ret);
2289 return ret;
2290 }
2291
2292 ret = ath10k_download_and_run_otp(ar);
2293 if (ret) {
2294 ath10k_err(ar, "failed to run otp: %d\n", ret);
2295 return ret;
2296 }
2297
2298 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2299 "pre cal configuration done successfully\n");
2300
2301 return 0;
2302}
2303
83091559 2304static int ath10k_download_cal_data(struct ath10k *ar)
5e3dd157
KV		 2305{
2306 int ret;
2307
3d9195ea
RM		 2308 ret = ath10k_core_pre_cal_config(ar);
2309 if (ret == 0)
2310 return 0;
2311
2312 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2313 "pre cal download procedure failed, try cal file: %d\n",
2314 ret);
2315
27deb0f1
CL		 2316 ret = ath10k_download_cal_nvmem(ar, "calibration");
2317 if (ret == 0) {
2318 ar->cal_mode = ATH10K_CAL_MODE_NVMEM;
2319 goto done;
2320 } else if (ret == -EPROBE_DEFER) {
2321 return ret;
2322 }
2323
2324 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2325 "boot did not find a calibration nvmem-cell, try file next: %d\n",
2326 ret);
2327
f454add4 2328 ret = ath10k_download_cal_file(ar, ar->cal_file);
a58227ef
KV		 2329 if (ret == 0) {
2330 ar->cal_mode = ATH10K_CAL_MODE_FILE;
2331 goto done;
2332 }
2333
2334 ath10k_dbg(ar, ATH10K_DBG_BOOT,
5aabff05
TK		 2335 "boot did not find a calibration file, try DT next: %d\n",
2336 ret);
2337
f454add4 2338 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data");
5aabff05
TK		 2339 if (ret == 0) {
2340 ar->cal_mode = ATH10K_CAL_MODE_DT;
2341 goto done;
2342 }
2343
2344 ath10k_dbg(ar, ATH10K_DBG_BOOT,
6847f967
SE		 2345 "boot did not find DT entry, try target EEPROM next: %d\n",
2346 ret);
2347
2348 ret = ath10k_download_cal_eeprom(ar);
2349 if (ret == 0) {
2350 ar->cal_mode = ATH10K_CAL_MODE_EEPROM;
2351 goto done;
2352 }
2353
2354 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2355 "boot did not find target EEPROM entry, try OTP next: %d\n",
a58227ef
KV		 2356 ret);
2357
5e3dd157 2358 ret = ath10k_download_and_run_otp(ar);
36a8f413 2359 if (ret) {
7aa7a72a 2360 ath10k_err(ar, "failed to run otp: %d\n", ret);
5e3dd157 2361 return ret;
36a8f413 2362 }
5e3dd157 2363
a58227ef
KV		 2364 ar->cal_mode = ATH10K_CAL_MODE_OTP;
2365
2366done:
2367 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
2368 ath10k_cal_mode_str(ar->cal_mode));
2369 return 0;
5e3dd157
KV		 2370}
2371
9f83993e
TC		 2372static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar)
2373{
2374 struct device_node *node;
2375 u8 coex_support = 0;
2376 int ret;
2377
2378 node = ar->dev->of_node;
2379 if (!node)
2380 goto out;
2381
2382 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support);
2383 if (ret) {
2384 ar->coex_support = true;
2385 goto out;
2386 }
2387
2388 if (coex_support) {
2389 ar->coex_support = true;
2390 } else {
2391 ar->coex_support = false;
2392 ar->coex_gpio_pin = -1;
2393 goto out;
2394 }
2395
2396 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin",
2397 &ar->coex_gpio_pin);
2398 if (ret)
2399 ar->coex_gpio_pin = -1;
2400
2401out:
2402 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n",
2403 ar->coex_support, ar->coex_gpio_pin);
2404}
2405
5e3dd157
KV		 2406static int ath10k_init_uart(struct ath10k *ar)
2407{
2408 int ret;
2409
2410 /*
2411 * Explicitly setting UART prints to zero as target turns it on
2412 * based on scratch registers.
2413 */
2414 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
2415 if (ret) {
7aa7a72a 2416 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
5e3dd157
KV		 2417 return ret;
2418 }
2419
1340cc63
MP		 2420 if (!uart_print) {
2421 if (ar->hw_params.uart_pin_workaround) {
2422 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin,
2423 ar->hw_params.uart_pin);
2424 if (ret) {
2425 ath10k_warn(ar, "failed to set UART TX pin: %d",
2426 ret);
2427 return ret;
2428 }
4504f0e5
WG		 2429 }
2430
5e3dd157 2431 return 0;
4504f0e5 2432 }
5e3dd157 2433
3a8200b2 2434 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
5e3dd157 2435 if (ret) {
7aa7a72a 2436 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
5e3dd157
KV		 2437 return ret;
2438 }
2439
2440 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
2441 if (ret) {
7aa7a72a 2442 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
5e3dd157
KV		 2443 return ret;
2444 }
2445
03fc137b
BM		 2446 /* Set the UART baud rate to 19200. */
2447 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
2448 if (ret) {
7aa7a72a 2449 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
03fc137b
BM		 2450 return ret;
2451 }
2452
7aa7a72a 2453 ath10k_info(ar, "UART prints enabled\n");
5e3dd157
KV		 2454 return 0;
2455}
2456
2457static int ath10k_init_hw_params(struct ath10k *ar)
2458{
3f649ab7 2459 const struct ath10k_hw_params *hw_params;
5e3dd157
KV		 2460 int i;
2461
2462 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
2463 hw_params = &ath10k_hw_params_list[i];
2464
367c899f
ES		 2465 if (hw_params->bus == ar->hif.bus &&
2466 hw_params->id == ar->target_version &&
079a0490 2467 hw_params->dev_id == ar->dev_id)
5e3dd157
KV		 2468 break;
2469 }
2470
2471 if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
7aa7a72a 2472 ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
5e3dd157
KV		 2473 ar->target_version);
2474 return -EINVAL;
2475 }
2476
2477 ar->hw_params = *hw_params;
2478
7aa7a72a 2479 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
c8c39afe 2480 ar->hw_params.name, ar->target_version);
5e3dd157
KV		 2481
2482 return 0;
2483}
2484
5dadbe4e
WG		 2485void ath10k_core_start_recovery(struct ath10k *ar)
2486{
2487 if (test_and_set_bit(ATH10K_FLAG_RESTARTING, &ar->dev_flags)) {
2488 ath10k_warn(ar, "already restarting\n");
2489 return;
2490 }
2491
2492 queue_work(ar->workqueue, &ar->restart_work);
2493}
2494EXPORT_SYMBOL(ath10k_core_start_recovery);
2495
e2f8b74e
WG		 2496void ath10k_core_napi_enable(struct ath10k *ar)
2497{
2498 lockdep_assert_held(&ar->conf_mutex);
2499
2500 if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags))
2501 return;
2502
2503 napi_enable(&ar->napi);
2504 set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags);
2505}
2506EXPORT_SYMBOL(ath10k_core_napi_enable);
2507
2508void ath10k_core_napi_sync_disable(struct ath10k *ar)
2509{
2510 lockdep_assert_held(&ar->conf_mutex);
2511
2512 if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags))
2513 return;
2514
2515 napi_synchronize(&ar->napi);
2516 napi_disable(&ar->napi);
2517 clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags);
2518}
2519EXPORT_SYMBOL(ath10k_core_napi_sync_disable);
2520
affd3217
MK		 2521static void ath10k_core_restart(struct work_struct *work)
2522{
2523 struct ath10k *ar = container_of(work, struct ath10k, restart_work);
727000e6 2524 int ret;
affd3217 2525
7962b0d8
MK		 2526 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
2527
2528 /* Place a barrier to make sure the compiler doesn't reorder
2529 * CRASH_FLUSH and calling other functions.
2530 */
2531 barrier();
2532
2533 ieee80211_stop_queues(ar->hw);
2534 ath10k_drain_tx(ar);
881ed54e
DW		 2535 complete(&ar->scan.started);
2536 complete(&ar->scan.completed);
2537 complete(&ar->scan.on_channel);
2538 complete(&ar->offchan_tx_completed);
2539 complete(&ar->install_key_done);
2540 complete(&ar->vdev_setup_done);
fe36e70f 2541 complete(&ar->vdev_delete_done);
881ed54e
DW		 2542 complete(&ar->thermal.wmi_sync);
2543 complete(&ar->bss_survey_done);
7962b0d8
MK		 2544 wake_up(&ar->htt.empty_tx_wq);
2545 wake_up(&ar->wmi.tx_credits_wq);
2546 wake_up(&ar->peer_mapping_wq);
2547
d94475c2
MSS		 2548 /* TODO: We can have one instance of cancelling coverage_class_work by
2549 * moving it to ath10k_halt(), so that both stop() and restart() would
2550 * call that but it takes conf_mutex() and if we call cancel_work_sync()
2551 * with conf_mutex it will deadlock.
2552 */
2553 cancel_work_sync(&ar->set_coverage_class_work);
2554
affd3217
MK		 2555 mutex_lock(&ar->conf_mutex);
2556
2557 switch (ar->state) {
2558 case ATH10K_STATE_ON:
affd3217 2559 ar->state = ATH10K_STATE_RESTARTING;
c2cac2f7 2560 ath10k_halt(ar);
5c81c7fd 2561 ath10k_scan_finish(ar);
affd3217
MK		 2562 ieee80211_restart_hw(ar->hw);
2563 break;
2564 case ATH10K_STATE_OFF:
5e90de86 2565 /* this can happen if driver is being unloaded
d6dfe25c
MR		 2566 * or if the crash happens during FW probing
2567 */
7aa7a72a 2568 ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
affd3217
MK		 2569 break;
2570 case ATH10K_STATE_RESTARTING:
c5058f5b
MK		 2571 /* hw restart might be requested from multiple places */
2572 break;
affd3217
MK		 2573 case ATH10K_STATE_RESTARTED:
2574 ar->state = ATH10K_STATE_WEDGED;
1885c0f7 2575 fallthrough;
affd3217 2576 case ATH10K_STATE_WEDGED:
7aa7a72a 2577 ath10k_warn(ar, "device is wedged, will not restart\n");
affd3217 2578 break;
43d2a30f
KV		 2579 case ATH10K_STATE_UTF:
2580 ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
2581 break;
affd3217
MK		 2582 }
2583
2584 mutex_unlock(&ar->conf_mutex);
727000e6 2585
f25b9f28 2586 ret = ath10k_coredump_submit(ar);
727000e6
AK		 2587 if (ret)
2588 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d",
2589 ret);
0e622f67
SV		 2590
2591 complete(&ar->driver_recovery);
affd3217
MK		 2592}
2593
ebee76f7
BB		 2594static void ath10k_core_set_coverage_class_work(struct work_struct *work)
2595{
2596 struct ath10k *ar = container_of(work, struct ath10k,
2597 set_coverage_class_work);
2598
2599 if (ar->hw_params.hw_ops->set_coverage_class)
2600 ar->hw_params.hw_ops->set_coverage_class(ar, -1);
2601}
2602
5f2144d9 2603static int ath10k_core_init_firmware_features(struct ath10k *ar)
cfd1061e 2604{
c4cdf753 2605 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
4875e0b5 2606 int max_num_peers;
c4cdf753
KV		 2607
2608 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) &&
2609 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
5f2144d9
KV		 2610 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
2611 return -EINVAL;
2612 }
2613
bf3c13ab 2614 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
202e86e6 2615 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
bf3c13ab 2616 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version);
202e86e6
KV		 2617 return -EINVAL;
2618 }
2619
ccec9038
DL		 2620 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
2621 switch (ath10k_cryptmode_param) {
2622 case ATH10K_CRYPT_MODE_HW:
2623 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2624 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
2625 break;
2626 case ATH10K_CRYPT_MODE_SW:
2627 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
c4cdf753 2628 fw_file->fw_features)) {
ccec9038
DL		 2629 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
2630 return -EINVAL;
2631 }
2632
2633 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2634 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
2635 break;
2636 default:
2637 ath10k_info(ar, "invalid cryptmode: %d\n",
2638 ath10k_cryptmode_param);
2639 return -EINVAL;
2640 }
2641
2642 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
2643 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
2644
a0974054 2645 if (ath10k_frame_mode == ATH10K_HW_TXRX_RAW) {
b6c7bafa 2646 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
c4cdf753 2647 fw_file->fw_features)) {
b6c7bafa
BC		 2648 ath10k_err(ar, "rawmode = 1 requires support from firmware");
2649 return -EINVAL;
2650 }
2651 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2652 }
2653
ccec9038
DL		 2654 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
2655 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
2656
2657 /* Workaround:
2658 *
2659 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
2660 * and causes enormous performance issues (malformed frames,
2661 * etc).
2662 *
2663 * Disabling A-MSDU makes RAW mode stable with heavy traffic
2664 * albeit a bit slower compared to regular operation.
2665 */
2666 ar->htt.max_num_amsdu = 1;
2667 }
2668
202e86e6
KV		 2669 /* Backwards compatibility for firmwares without
2670 * ATH10K_FW_IE_WMI_OP_VERSION.
2671 */
bf3c13ab 2672 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
c4cdf753 2673 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
4a16fbec 2674 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
c4cdf753 2675 fw_file->fw_features))
bf3c13ab 2676 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
202e86e6 2677 else
bf3c13ab 2678 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
202e86e6 2679 } else {
bf3c13ab 2680 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
202e86e6
KV		 2681 }
2682 }
2683
bf3c13ab 2684 switch (fw_file->wmi_op_version) {
202e86e6 2685 case ATH10K_FW_WMI_OP_VERSION_MAIN:
4875e0b5 2686 max_num_peers = TARGET_NUM_PEERS;
cfd1061e 2687 ar->max_num_stations = TARGET_NUM_STATIONS;
30c78167 2688 ar->max_num_vdevs = TARGET_NUM_VDEVS;
91ad5f56 2689 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
6274cd41
YL		 2690 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
2691 WMI_STAT_PEER;
5c8726ec 2692 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
202e86e6
KV		 2693 break;
2694 case ATH10K_FW_WMI_OP_VERSION_10_1:
2695 case ATH10K_FW_WMI_OP_VERSION_10_2:
4a16fbec 2696 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
cc61a1bb 2697 if (ath10k_peer_stats_enabled(ar)) {
4875e0b5 2698 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
af9a6a3a
AK		 2699 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
2700 } else {
4875e0b5 2701 max_num_peers = TARGET_10X_NUM_PEERS;
af9a6a3a
AK		 2702 ar->max_num_stations = TARGET_10X_NUM_STATIONS;
2703 }
30c78167 2704 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
91ad5f56 2705 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
6274cd41 2706 ar->fw_stats_req_mask = WMI_STAT_PEER;
5c8726ec 2707 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
202e86e6 2708 break;
ca996ec5 2709 case ATH10K_FW_WMI_OP_VERSION_TLV:
4875e0b5 2710 max_num_peers = TARGET_TLV_NUM_PEERS;
ca996ec5 2711 ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
49274332 2712 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
8cca3d60 2713 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
a73dbce3
AS		 2714 if (ar->hif.bus == ATH10K_BUS_SDIO)
2715 ar->htt.max_num_pending_tx =
2716 TARGET_TLV_NUM_MSDU_DESC_HL;
2717 else
2718 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
25c86619 2719 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
f40a307e
SV		 2720 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV |
2721 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD;
5c8726ec 2722 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
dc405152 2723 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC;
ca996ec5 2724 break;
9bd21322 2725 case ATH10K_FW_WMI_OP_VERSION_10_4:
4875e0b5 2726 max_num_peers = TARGET_10_4_NUM_PEERS;
d1e52a8e
RM		 2727 ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
2728 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
2729 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
2730 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
f9575793 2731 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER |
1b3fdb50
RM		 2732 WMI_10_4_STAT_PEER_EXTD |
2733 WMI_10_4_STAT_VDEV_EXTD;
5699a6f2 2734 ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
add6cd8d 2735 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS;
99ad1cba
MK		 2736
2737 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
c4cdf753 2738 fw_file->fw_features))
99ad1cba
MK		 2739 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC;
2740 else
2741 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
d1e52a8e 2742 break;
202e86e6
KV		 2743 case ATH10K_FW_WMI_OP_VERSION_UNSET:
2744 case ATH10K_FW_WMI_OP_VERSION_MAX:
4875e0b5 2745 default:
202e86e6
KV		 2746 WARN_ON(1);
2747 return -EINVAL;
cfd1061e 2748 }
5f2144d9 2749
4875e0b5
ES		 2750 if (ar->hw_params.num_peers)
2751 ar->max_num_peers = ar->hw_params.num_peers;
2752 else
2753 ar->max_num_peers = max_num_peers;
2754
dc3632a1
KV		 2755 /* Backwards compatibility for firmwares without
2756 * ATH10K_FW_IE_HTT_OP_VERSION.
2757 */
77561f93 2758 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
bf3c13ab 2759 switch (fw_file->wmi_op_version) {
dc3632a1 2760 case ATH10K_FW_WMI_OP_VERSION_MAIN:
77561f93 2761 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
dc3632a1
KV		 2762 break;
2763 case ATH10K_FW_WMI_OP_VERSION_10_1:
2764 case ATH10K_FW_WMI_OP_VERSION_10_2:
2765 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
77561f93 2766 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
dc3632a1
KV		 2767 break;
2768 case ATH10K_FW_WMI_OP_VERSION_TLV:
77561f93 2769 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
dc3632a1 2770 break;
9bd21322 2771 case ATH10K_FW_WMI_OP_VERSION_10_4:
dc3632a1
KV		 2772 case ATH10K_FW_WMI_OP_VERSION_UNSET:
2773 case ATH10K_FW_WMI_OP_VERSION_MAX:
ce30c4fe 2774 ath10k_err(ar, "htt op version not found from fw meta data");
dc3632a1
KV		 2775 return -EINVAL;
2776 }
2777 }
2778
5f2144d9 2779 return 0;
cfd1061e
MK		 2780}
2781
47b1848d
MK		 2782static int ath10k_core_reset_rx_filter(struct ath10k *ar)
2783{
2784 int ret;
2785 int vdev_id;
2786 int vdev_type;
2787 int vdev_subtype;
2788 const u8 *vdev_addr;
2789
2790 vdev_id = 0;
2791 vdev_type = WMI_VDEV_TYPE_STA;
2792 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE);
2793 vdev_addr = ar->mac_addr;
2794
2795 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype,
2796 vdev_addr);
2797 if (ret) {
2798 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret);
2799 return ret;
2800 }
2801
2802 ret = ath10k_wmi_vdev_delete(ar, vdev_id);
2803 if (ret) {
2804 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret);
2805 return ret;
2806 }
2807
2808 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be
2809 * serialized properly implicitly.
2810 *
2811 * Moreover (most) WMI commands have no explicit acknowledges. It is
2812 * possible to infer it implicitly by poking firmware with echo
2813 * command - getting a reply means all preceding comments have been
2814 * (mostly) processed.
2815 *
2816 * In case of vdev create/delete this is sufficient.
2817 *
2818 * Without this it's possible to end up with a race when HTT Rx ring is
2819 * started before vdev create/delete hack is complete allowing a short
2820 * window of opportunity to receive (and Tx ACK) a bunch of frames.
2821 */
2822 ret = ath10k_wmi_barrier(ar);
2823 if (ret) {
2824 ath10k_err(ar, "failed to ping firmware: %d\n", ret);
2825 return ret;
2826 }
2827
2828 return 0;
2829}
2830
53884577
RP		 2831static int ath10k_core_compat_services(struct ath10k *ar)
2832{
2833 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
2834
2835 /* all 10.x firmware versions support thermal throttling but don't
2836 * advertise the support via service flags so we have to hardcode
2837 * it here
2838 */
2839 switch (fw_file->wmi_op_version) {
2840 case ATH10K_FW_WMI_OP_VERSION_10_1:
2841 case ATH10K_FW_WMI_OP_VERSION_10_2:
2842 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2843 case ATH10K_FW_WMI_OP_VERSION_10_4:
2844 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map);
2845 break;
2846 default:
2847 break;
2848 }
2849
2850 return 0;
2851}
2852
9af7c32c
VN		 2853#define TGT_IRAM_READ_PER_ITR (8 * 1024)
2854
2855static int ath10k_core_copy_target_iram(struct ath10k *ar)
2856{
2857 const struct ath10k_hw_mem_layout *hw_mem;
2858 const struct ath10k_mem_region *tmp, *mem_region = NULL;
2859 dma_addr_t paddr;
2860 void *vaddr = NULL;
2861 u8 num_read_itr;
2862 int i, ret;
2863 u32 len, remaining_len;
2864
6f8c8bf4
AK		 2865 /* copy target iram feature must work also when
2866 * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so
2867 * _ath10k_coredump_get_mem_layout() to accomplist that
2868 */
2869 hw_mem = _ath10k_coredump_get_mem_layout(ar);
9af7c32c 2870 if (!hw_mem)
6f8c8bf4
AK		 2871 /* if CONFIG_DEV_COREDUMP is disabled we get NULL, then
2872 * just silently disable the feature by doing nothing
2873 */
2874 return 0;
9af7c32c
VN		 2875
2876 for (i = 0; i < hw_mem->region_table.size; i++) {
2877 tmp = &hw_mem->region_table.regions[i];
2878 if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) {
2879 mem_region = tmp;
2880 break;
2881 }
2882 }
2883
2884 if (!mem_region)
2885 return -ENOMEM;
2886
2887 for (i = 0; i < ar->wmi.num_mem_chunks; i++) {
2888 if (ar->wmi.mem_chunks[i].req_id ==
2889 WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) {
2890 vaddr = ar->wmi.mem_chunks[i].vaddr;
2891 len = ar->wmi.mem_chunks[i].len;
2892 break;
2893 }
2894 }
2895
2896 if (!vaddr || !len) {
2897 ath10k_warn(ar, "No allocated memory for IRAM back up");
2898 return -ENOMEM;
2899 }
2900
2901 len = (len < mem_region->len) ? len : mem_region->len;
2902 paddr = mem_region->start;
2903 num_read_itr = len / TGT_IRAM_READ_PER_ITR;
2904 remaining_len = len % TGT_IRAM_READ_PER_ITR;
2905 for (i = 0; i < num_read_itr; i++) {
2906 ret = ath10k_hif_diag_read(ar, paddr, vaddr,
2907 TGT_IRAM_READ_PER_ITR);
2908 if (ret) {
2909 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d",
2910 ret);
2911 return ret;
2912 }
2913
2914 paddr += TGT_IRAM_READ_PER_ITR;
2915 vaddr += TGT_IRAM_READ_PER_ITR;
2916 }
2917
2918 if (remaining_len) {
2919 ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len);
2920 if (ret) {
2921 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d",
2922 ret);
2923 return ret;
2924 }
2925 }
2926
2927 ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n");
2928
2929 return 0;
2930}
2931
7ebf721d
KV		 2932int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
2933 const struct ath10k_fw_components *fw)
5e3dd157 2934{
5e3dd157 2935 int status;
f9575793 2936 u32 val;
5e3dd157 2937
60631c5c
KV		 2938 lockdep_assert_held(&ar->conf_mutex);
2939
7962b0d8
MK		 2940 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
2941
7ebf721d
KV		 2942 ar->running_fw = fw;
2943
71e9c29f
RP		 2944 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
2945 ar->running_fw->fw_file.fw_features)) {
2946 ath10k_bmi_start(ar);
64d151d4 2947
ad0dc042
KV		 2948 /* Enable hardware clock to speed up firmware download */
2949 if (ar->hw_params.hw_ops->enable_pll_clk) {
2950 status = ar->hw_params.hw_ops->enable_pll_clk(ar);
2951 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n",
2952 status);
2953 }
2954
71e9c29f
RP		 2955 if (ath10k_init_configure_target(ar)) {
2956 status = -EINVAL;
2957 goto err;
2958 }
83091559 2959
71e9c29f
RP		 2960 status = ath10k_download_cal_data(ar);
2961 if (status)
163f5264 2962 goto err;
71e9c29f 2963
762fd1ae 2964 /* Some of qca988x solutions are having global reset issue
71e9c29f
RP		 2965 * during target initialization. Bypassing PLL setting before
2966 * downloading firmware and letting the SoC run on REF_CLK is
2967 * fixing the problem. Corresponding firmware change is also
2968 * needed to set the clock source once the target is
2969 * initialized.
2970 */
2971 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
2972 ar->running_fw->fw_file.fw_features)) {
2973 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
2974 if (status) {
2975 ath10k_err(ar, "could not write to skip_clock_init: %d\n",
2976 status);
2977 goto err;
2978 }
163f5264 2979 }
163f5264 2980
71e9c29f
RP		 2981 status = ath10k_download_fw(ar);
2982 if (status)
2983 goto err;
5e3dd157 2984
71e9c29f
RP		 2985 status = ath10k_init_uart(ar);
2986 if (status)
2987 goto err;
5e3dd157 2988
8da96730
KL		 2989 if (ar->hif.bus == ATH10K_BUS_SDIO) {
2990 status = ath10k_init_sdio(ar, mode);
2991 if (status) {
2992 ath10k_err(ar, "failed to init SDIO: %d\n", status);
2993 goto err;
2994 }
2995 }
71e9c29f 2996 }
60bdfffa 2997
cd003fad
MK		 2998 ar->htc.htc_ops.target_send_suspend_complete =
2999 ath10k_send_suspend_complete;
5e3dd157 3000
cd003fad
MK		 3001 status = ath10k_htc_init(ar);
3002 if (status) {
7aa7a72a 3003 ath10k_err(ar, "could not init HTC (%d)\n", status);
5e3dd157
KV		 3004 goto err;
3005 }
3006
71e9c29f
RP		 3007 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3008 ar->running_fw->fw_file.fw_features)) {
3009 status = ath10k_bmi_done(ar);
3010 if (status)
3011 goto err;
3012 }
5e3dd157
KV		 3013
3014 status = ath10k_wmi_attach(ar);
3015 if (status) {
7aa7a72a 3016 ath10k_err(ar, "WMI attach failed: %d\n", status);
cd003fad 3017 goto err;
5e3dd157
KV		 3018 }
3019
95bf21f9
MK		 3020 status = ath10k_htt_init(ar);
3021 if (status) {
7aa7a72a 3022 ath10k_err(ar, "failed to init htt: %d\n", status);
95bf21f9
MK		 3023 goto err_wmi_detach;
3024 }
3025
9ec34a86 3026 status = ath10k_htt_tx_start(&ar->htt);
95bf21f9 3027 if (status) {
7aa7a72a 3028 ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
95bf21f9
MK		 3029 goto err_wmi_detach;
3030 }
3031
f35a7f91
RP		 3032 /* If firmware indicates Full Rx Reorder support it must be used in a
3033 * slightly different manner. Let HTT code know.
3034 */
3035 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
3036 ar->wmi.svc_map));
3037
95bf21f9
MK		 3038 status = ath10k_htt_rx_alloc(&ar->htt);
3039 if (status) {
7aa7a72a 3040 ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
95bf21f9
MK		 3041 goto err_htt_tx_detach;
3042 }
3043
67e3c63f
MK		 3044 status = ath10k_hif_start(ar);
3045 if (status) {
7aa7a72a 3046 ath10k_err(ar, "could not start HIF: %d\n", status);
95bf21f9 3047 goto err_htt_rx_detach;
67e3c63f
MK		 3048 }
3049
3050 status = ath10k_htc_wait_target(&ar->htc);
3051 if (status) {
7aa7a72a 3052 ath10k_err(ar, "failed to connect to HTC: %d\n", status);
67e3c63f
MK		 3053 goto err_hif_stop;
3054 }
5e3dd157 3055
557e1714 3056 status = ath10k_hif_start_post(ar);
40194e3b
WG		 3057 if (status) {
3058 ath10k_err(ar, "failed to swap mailbox: %d\n", status);
3059 goto err_hif_stop;
3060 }
3061
43d2a30f
KV		 3062 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3063 status = ath10k_htt_connect(&ar->htt);
3064 if (status) {
3065 ath10k_err(ar, "failed to connect htt (%d)\n", status);
3066 goto err_hif_stop;
3067 }
5e3dd157
KV		 3068 }
3069
95bf21f9
MK		 3070 status = ath10k_wmi_connect(ar);
3071 if (status) {
7aa7a72a 3072 ath10k_err(ar, "could not connect wmi: %d\n", status);
95bf21f9
MK		 3073 goto err_hif_stop;
3074 }
3075
3076 status = ath10k_htc_start(&ar->htc);
3077 if (status) {
7aa7a72a 3078 ath10k_err(ar, "failed to start htc: %d\n", status);
95bf21f9
MK		 3079 goto err_hif_stop;
3080 }
3081
43d2a30f
KV		 3082 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3083 status = ath10k_wmi_wait_for_service_ready(ar);
9eea5689 3084 if (status) {
43d2a30f 3085 ath10k_warn(ar, "wmi service ready event not received");
43d2a30f
KV		 3086 goto err_hif_stop;
3087 }
95bf21f9 3088 }
5e3dd157 3089
7aa7a72a 3090 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
c8c39afe 3091 ar->hw->wiphy->fw_version);
5e3dd157 3092
9af7c32c
VN		 3093 if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY,
3094 ar->running_fw->fw_file.fw_features)) {
3095 status = ath10k_core_copy_target_iram(ar);
3096 if (status) {
3097 ath10k_warn(ar, "failed to copy target iram contents: %d",
3098 status);
3099 goto err_hif_stop;
3100 }
3101 }
3102
cb428152
T		 3103 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) &&
3104 mode == ATH10K_FIRMWARE_MODE_NORMAL) {
f9575793
MSS		 3105 val = 0;
3106 if (ath10k_peer_stats_enabled(ar))
3107 val = WMI_10_4_PEER_STATS;
3108
1b3fdb50
RM		 3109 /* Enable vdev stats by default */
3110 val |= WMI_10_4_VDEV_STATS;
3111
fa7937e3
RM		 3112 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
3113 val |= WMI_10_4_BSS_CHANNEL_INFO_64;
3114
9f83993e
TC		 3115 ath10k_core_fetch_btcoex_dt(ar);
3116
39136248
RM		 3117 /* 10.4 firmware supports BT-Coex without reloading firmware
3118 * via pdev param. To support Bluetooth coexistence pdev param,
3119 * WMI_COEX_GPIO_SUPPORT of extended resource config should be
3120 * enabled always.
9f83993e
TC		 3121 *
3122 * We can still enable BTCOEX if firmware has the support
b8a71b95 3123 * even though btceox_support value is
9f83993e 3124 * ATH10K_DT_BTCOEX_NOT_FOUND
39136248 3125 */
9f83993e 3126
39136248
RM		 3127 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) &&
3128 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM,
9f83993e
TC		 3129 ar->running_fw->fw_file.fw_features) &&
3130 ar->coex_support)
39136248
RM		 3131 val |= WMI_10_4_COEX_GPIO_SUPPORT;
3132
add6cd8d
MP		 3133 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY,
3134 ar->wmi.svc_map))
3135 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY;
3136
3137 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA,
3138 ar->wmi.svc_map))
3139 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA;
3140
c7fd8d23
BP		 3141 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI,
3142 ar->wmi.svc_map))
3143 val |= WMI_10_4_TX_DATA_ACK_RSSI;
3144
bb31b7cb
MP		 3145 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map))
3146 val |= WMI_10_4_REPORT_AIRTIME;
3147
7b2531d9
TC		 3148 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT,
3149 ar->wmi.svc_map))
3150 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT;
3151
7e247a9e 3152 status = ath10k_mac_ext_resource_config(ar, val);
f9575793
MSS		 3153 if (status) {
3154 ath10k_err(ar,
3155 "failed to send ext resource cfg command : %d\n",
3156 status);
3157 goto err_hif_stop;
3158 }
3159 }
3160
5e3dd157
KV		 3161 status = ath10k_wmi_cmd_init(ar);
3162 if (status) {
7aa7a72a
MK		 3163 ath10k_err(ar, "could not send WMI init command (%d)\n",
3164 status);
b7967dc7 3165 goto err_hif_stop;
5e3dd157
KV		 3166 }
3167
3168 status = ath10k_wmi_wait_for_unified_ready(ar);
9eea5689 3169 if (status) {
7aa7a72a 3170 ath10k_err(ar, "wmi unified ready event not received\n");
b7967dc7 3171 goto err_hif_stop;
5e3dd157
KV		 3172 }
3173
53884577
RP		 3174 status = ath10k_core_compat_services(ar);
3175 if (status) {
3176 ath10k_err(ar, "compat services failed: %d\n", status);
3177 goto err_hif_stop;
3178 }
3179
05e7ba24
CL		 3180 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr);
3181 if (status && status != -EOPNOTSUPP) {
3182 ath10k_err(ar,
3183 "failed to set base mac address: %d\n", status);
3184 goto err_hif_stop;
3185 }
3186
47b1848d
MK		 3187 /* Some firmware revisions do not properly set up hardware rx filter
3188 * registers.
3189 *
3190 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK
3191 * is filled with 0s instead of 1s allowing HW to respond with ACKs to
3192 * any frames that matches MAC_PCU_RX_FILTER which is also
3193 * misconfigured to accept anything.
3194 *
3195 * The ADDR1 is programmed using internal firmware structure field and
3196 * can't be (easily/sanely) reached from the driver explicitly. It is
3197 * possible to implicitly make it correct by creating a dummy vdev and
3198 * then deleting it.
3199 */
58da3b42
RP		 3200 if (ar->hw_params.hw_filter_reset_required &&
3201 mode == ATH10K_FIRMWARE_MODE_NORMAL) {
cb428152
T		 3202 status = ath10k_core_reset_rx_filter(ar);
3203 if (status) {
3204 ath10k_err(ar,
3205 "failed to reset rx filter: %d\n", status);
3206 goto err_hif_stop;
3207 }
47b1848d
MK		 3208 }
3209
c545070e
MK		 3210 status = ath10k_htt_rx_ring_refill(ar);
3211 if (status) {
3212 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
3213 goto err_hif_stop;
3214 }
3215
30d2049b
BG		 3216 if (ar->max_num_vdevs >= 64)
3217 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL;
3218 else
3219 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
4ad24a9d
AK		 3220
3221 INIT_LIST_HEAD(&ar->arvifs);
3222
43d2a30f
KV		 3223 /* we don't care about HTT in UTF mode */
3224 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3225 status = ath10k_htt_setup(&ar->htt);
3226 if (status) {
3227 ath10k_err(ar, "failed to setup htt: %d\n", status);
3228 goto err_hif_stop;
3229 }
95bf21f9 3230 }
5e3dd157 3231
db66ea04
KV		 3232 status = ath10k_debug_start(ar);
3233 if (status)
b7967dc7 3234 goto err_hif_stop;
db66ea04 3235
d9e47698
GS		 3236 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log);
3237 if (status && status != -EOPNOTSUPP) {
80ce8ca7 3238 ath10k_warn(ar, "set target log mode failed: %d\n", status);
d9e47698
GS		 3239 goto err_hif_stop;
3240 }
3241
dd30a36e
MK		 3242 return 0;
3243
67e3c63f
MK		 3244err_hif_stop:
3245 ath10k_hif_stop(ar);
95bf21f9
MK		 3246err_htt_rx_detach:
3247 ath10k_htt_rx_free(&ar->htt);
3248err_htt_tx_detach:
3249 ath10k_htt_tx_free(&ar->htt);
dd30a36e
MK		 3250err_wmi_detach:
3251 ath10k_wmi_detach(ar);
3252err:
3253 return status;
3254}
818bdd16 3255EXPORT_SYMBOL(ath10k_core_start);
dd30a36e 3256
00f5482b
MP		 3257int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
3258{
3259 int ret;
a7a42849 3260 unsigned long time_left;
00f5482b
MP		 3261
3262 reinit_completion(&ar->target_suspend);
3263
3264 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
3265 if (ret) {
7aa7a72a 3266 ath10k_warn(ar, "could not suspend target (%d)\n", ret);
00f5482b
MP		 3267 return ret;
3268 }
3269
a7a42849 3270 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
00f5482b 3271
a7a42849 3272 if (!time_left) {
7aa7a72a 3273 ath10k_warn(ar, "suspend timed out - target pause event never came\n");
00f5482b
MP		 3274 return -ETIMEDOUT;
3275 }
3276
3277 return 0;
3278}
3279
dd30a36e
MK		 3280void ath10k_core_stop(struct ath10k *ar)
3281{
60631c5c 3282 lockdep_assert_held(&ar->conf_mutex);
f1ee2682 3283 ath10k_debug_stop(ar);
60631c5c 3284
00f5482b 3285 /* try to suspend target */
43d2a30f
KV		 3286 if (ar->state != ATH10K_STATE_RESTARTING &&
3287 ar->state != ATH10K_STATE_UTF)
216a1836
MK		 3288 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
3289
95bf21f9 3290 ath10k_hif_stop(ar);
9ec34a86 3291 ath10k_htt_tx_stop(&ar->htt);
95bf21f9 3292 ath10k_htt_rx_free(&ar->htt);
dd30a36e 3293 ath10k_wmi_detach(ar);
a4b9f641
VP		 3294
3295 ar->id.bmi_ids_valid = false;
dd30a36e 3296}
818bdd16
MK		 3297EXPORT_SYMBOL(ath10k_core_stop);
3298
3299/* mac80211 manages fw/hw initialization through start/stop hooks. However in
3300 * order to know what hw capabilities should be advertised to mac80211 it is
3301 * necessary to load the firmware (and tear it down immediately since start
d6dfe25c
MR		 3302 * hook will try to init it again) before registering
3303 */
818bdd16
MK		 3304static int ath10k_core_probe_fw(struct ath10k *ar)
3305{
29385057
MK		 3306 struct bmi_target_info target_info;
3307 int ret = 0;
818bdd16 3308
3c545a25 3309 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL);
818bdd16 3310 if (ret) {
cf0d37ae 3311 ath10k_err(ar, "could not power on hif bus (%d)\n", ret);
818bdd16
MK		 3312 return ret;
3313 }
3314
71e9c29f
RP		 3315 switch (ar->hif.bus) {
3316 case ATH10K_BUS_SDIO:
3317 memset(&target_info, 0, sizeof(target_info));
34dd398a 3318 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info);
71e9c29f
RP		 3319 if (ret) {
3320 ath10k_err(ar, "could not get target info (%d)\n", ret);
3321 goto err_power_down;
3322 }
3323 ar->target_version = target_info.version;
3324 ar->hw->wiphy->hw_version = target_info.version;
3325 break;
3326 case ATH10K_BUS_PCI:
3327 case ATH10K_BUS_AHB:
e6fe214e 3328 case ATH10K_BUS_USB:
71e9c29f 3329 memset(&target_info, 0, sizeof(target_info));
34dd398a 3330 ret = ath10k_bmi_get_target_info(ar, &target_info);
71e9c29f
RP		 3331 if (ret) {
3332 ath10k_err(ar, "could not get target info (%d)\n", ret);
3333 goto err_power_down;
3334 }
3335 ar->target_version = target_info.version;
3336 ar->hw->wiphy->hw_version = target_info.version;
3337 break;
3338 case ATH10K_BUS_SNOC:
140d1214
RP		 3339 memset(&target_info, 0, sizeof(target_info));
3340 ret = ath10k_hif_get_target_info(ar, &target_info);
3341 if (ret) {
3342 ath10k_err(ar, "could not get target info (%d)\n", ret);
3343 goto err_power_down;
3344 }
3345 ar->target_version = target_info.version;
3346 ar->hw->wiphy->hw_version = target_info.version;
71e9c29f
RP		 3347 break;
3348 default:
3349 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus);
29385057
MK		 3350 }
3351
29385057
MK		 3352 ret = ath10k_init_hw_params(ar);
3353 if (ret) {
7aa7a72a 3354 ath10k_err(ar, "could not get hw params (%d)\n", ret);
c6ce492d 3355 goto err_power_down;
29385057
MK		 3356 }
3357
3358 ret = ath10k_core_fetch_firmware_files(ar);
3359 if (ret) {
7aa7a72a 3360 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
c6ce492d 3361 goto err_power_down;
29385057
MK		 3362 }
3363
45317355
KV		 3364 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) !=
3365 sizeof(ar->normal_mode_fw.fw_file.fw_version));
3366 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version,
3367 sizeof(ar->hw->wiphy->fw_version));
3368
23f591ea
KV		 3369 ath10k_debug_print_hwfw_info(ar);
3370
71e9c29f
RP		 3371 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3372 ar->normal_mode_fw.fw_file.fw_features)) {
3373 ret = ath10k_core_pre_cal_download(ar);
3374 if (ret) {
3375 /* pre calibration data download is not necessary
3376 * for all the chipsets. Ignore failures and continue.
3377 */
3378 ath10k_dbg(ar, ATH10K_DBG_BOOT,
3379 "could not load pre cal data: %d\n", ret);
3380 }
3d9195ea 3381
71e9c29f
RP		 3382 ret = ath10k_core_get_board_id_from_otp(ar);
3383 if (ret && ret != -EOPNOTSUPP) {
3384 ath10k_err(ar, "failed to get board id from otp: %d\n",
3385 ret);
3386 goto err_free_firmware_files;
3387 }
db0984e5 3388
71e9c29f
RP		 3389 ret = ath10k_core_check_smbios(ar);
3390 if (ret)
3391 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n");
d06f26c5 3392
71e9c29f
RP		 3393 ret = ath10k_core_check_dt(ar);
3394 if (ret)
3395 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n");
1657b8f8 3396
31324d17 3397 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD);
71e9c29f
RP		 3398 if (ret) {
3399 ath10k_err(ar, "failed to fetch board file: %d\n", ret);
3400 goto err_free_firmware_files;
3401 }
db0984e5 3402
71e9c29f
RP		 3403 ath10k_debug_print_board_info(ar);
3404 }
23f591ea 3405
0a14501e 3406 device_get_mac_address(ar->dev, ar->mac_addr);
9d580466 3407
5f2144d9
KV		 3408 ret = ath10k_core_init_firmware_features(ar);
3409 if (ret) {
3410 ath10k_err(ar, "fatal problem with firmware features: %d\n",
3411 ret);
3412 goto err_free_firmware_files;
3413 }
cfd1061e 3414
71e9c29f
RP		 3415 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3416 ar->normal_mode_fw.fw_file.fw_features)) {
3417 ret = ath10k_swap_code_seg_init(ar,
3418 &ar->normal_mode_fw.fw_file);
3419 if (ret) {
3420 ath10k_err(ar, "failed to initialize code swap segment: %d\n",
3421 ret);
3422 goto err_free_firmware_files;
3423 }
dcb02db1
VT		 3424 }
3425
60631c5c
KV		 3426 mutex_lock(&ar->conf_mutex);
3427
7ebf721d
KV		 3428 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL,
3429 &ar->normal_mode_fw);
818bdd16 3430 if (ret) {
7aa7a72a 3431 ath10k_err(ar, "could not init core (%d)\n", ret);
c6ce492d 3432 goto err_unlock;
818bdd16
MK		 3433 }
3434
23f591ea 3435 ath10k_debug_print_boot_info(ar);
818bdd16 3436 ath10k_core_stop(ar);
60631c5c
KV		 3437
3438 mutex_unlock(&ar->conf_mutex);
3439
818bdd16
MK		 3440 ath10k_hif_power_down(ar);
3441 return 0;
c6ce492d
KV		 3442
3443err_unlock:
3444 mutex_unlock(&ar->conf_mutex);
3445
5f2144d9 3446err_free_firmware_files:
c6ce492d
KV		 3447 ath10k_core_free_firmware_files(ar);
3448
3449err_power_down:
3450 ath10k_hif_power_down(ar);
3451
3452 return ret;
818bdd16 3453}
dd30a36e 3454
6782cb69 3455static void ath10k_core_register_work(struct work_struct *work)
dd30a36e 3456{
6782cb69 3457 struct ath10k *ar = container_of(work, struct ath10k, register_work);
dd30a36e
MK		 3458 int status;
3459
8c1d7fa5
TP		 3460 /* peer stats are enabled by default */
3461 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags);
3462
818bdd16
MK		 3463 status = ath10k_core_probe_fw(ar);
3464 if (status) {
7aa7a72a 3465 ath10k_err(ar, "could not probe fw (%d)\n", status);
6782cb69 3466 goto err;
818bdd16 3467 }
dd30a36e 3468
5e3dd157 3469 status = ath10k_mac_register(ar);
818bdd16 3470 if (status) {
7aa7a72a 3471 ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
29385057 3472 goto err_release_fw;
818bdd16 3473 }
5e3dd157 3474
703f261d
AL		 3475 status = ath10k_coredump_register(ar);
3476 if (status) {
3477 ath10k_err(ar, "unable to register coredump\n");
3478 goto err_unregister_mac;
3479 }
3480
e13cf7a3 3481 status = ath10k_debug_register(ar);
5e3dd157 3482 if (status) {
7aa7a72a 3483 ath10k_err(ar, "unable to initialize debugfs\n");
703f261d 3484 goto err_unregister_coredump;
5e3dd157
KV		 3485 }
3486
855aed12
SW		 3487 status = ath10k_spectral_create(ar);
3488 if (status) {
7aa7a72a 3489 ath10k_err(ar, "failed to initialize spectral\n");
855aed12
SW		 3490 goto err_debug_destroy;
3491 }
3492
fe6f36d6
RM		 3493 status = ath10k_thermal_register(ar);
3494 if (status) {
3495 ath10k_err(ar, "could not register thermal device: %d\n",
3496 status);
3497 goto err_spectral_destroy;
3498 }
3499
6782cb69
MK		 3500 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
3501 return;
5e3dd157 3502
fe6f36d6
RM		 3503err_spectral_destroy:
3504 ath10k_spectral_destroy(ar);
855aed12
SW		 3505err_debug_destroy:
3506 ath10k_debug_destroy(ar);
703f261d
AL		 3507err_unregister_coredump:
3508 ath10k_coredump_unregister(ar);
5e3dd157
KV		 3509err_unregister_mac:
3510 ath10k_mac_unregister(ar);
29385057
MK		 3511err_release_fw:
3512 ath10k_core_free_firmware_files(ar);
6782cb69 3513err:
a491a920
MK		 3514 /* TODO: It's probably a good idea to release device from the driver
3515 * but calling device_release_driver() here will cause a deadlock.
3516 */
6782cb69
MK		 3517 return;
3518}
3519
c0d8d565
ES		 3520int ath10k_core_register(struct ath10k *ar,
3521 const struct ath10k_bus_params *bus_params)
6782cb69 3522{
01dc76df
KV		 3523 ar->bus_param = *bus_params;
3524
6782cb69
MK		 3525 queue_work(ar->workqueue, &ar->register_work);
3526
3527 return 0;
5e3dd157
KV		 3528}
3529EXPORT_SYMBOL(ath10k_core_register);
3530
3531void ath10k_core_unregister(struct ath10k *ar)
3532{
6782cb69
MK		 3533 cancel_work_sync(&ar->register_work);
3534
3535 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
3536 return;
3537
fe6f36d6 3538 ath10k_thermal_unregister(ar);
804eef14
SW		 3539 /* Stop spectral before unregistering from mac80211 to remove the
3540 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
3541 * would be already be free'd recursively, leading to a double free.
3542 */
3543 ath10k_spectral_destroy(ar);
3544
5e3dd157
KV		 3545 /* We must unregister from mac80211 before we stop HTC and HIF.
3546 * Otherwise we will fail to submit commands to FW and mac80211 will be
d6dfe25c
MR		 3547 * unhappy about callback failures.
3548 */
5e3dd157 3549 ath10k_mac_unregister(ar);
db66ea04 3550
43d2a30f
KV		 3551 ath10k_testmode_destroy(ar);
3552
29385057 3553 ath10k_core_free_firmware_files(ar);
0a51b343 3554 ath10k_core_free_board_files(ar);
6f1f56ea 3555
e13cf7a3 3556 ath10k_debug_unregister(ar);
5e3dd157
KV		 3557}
3558EXPORT_SYMBOL(ath10k_core_unregister);
3559
e7b54194 3560struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
e07db352 3561 enum ath10k_bus bus,
d63955b3 3562 enum ath10k_hw_rev hw_rev,
0d0a6939
MK		 3563 const struct ath10k_hif_ops *hif_ops)
3564{
3565 struct ath10k *ar;
e13cf7a3 3566 int ret;
0d0a6939 3567
e7b54194 3568 ar = ath10k_mac_create(priv_size);
0d0a6939
MK		 3569 if (!ar)
3570 return NULL;
3571
3572 ar->ath_common.priv = ar;
3573 ar->ath_common.hw = ar->hw;
0d0a6939 3574 ar->dev = dev;
d63955b3 3575 ar->hw_rev = hw_rev;
0d0a6939 3576 ar->hif.ops = hif_ops;
e07db352 3577 ar->hif.bus = bus;
0d0a6939 3578
d63955b3
MK		 3579 switch (hw_rev) {
3580 case ATH10K_HW_QCA988X:
6fd3dd71 3581 case ATH10K_HW_QCA9887:
d63955b3 3582 ar->regs = &qca988x_regs;
03a016f8 3583 ar->hw_ce_regs = &qcax_ce_regs;
2f2cfc4a 3584 ar->hw_values = &qca988x_values;
d63955b3
MK		 3585 break;
3586 case ATH10K_HW_QCA6174:
a226b519 3587 case ATH10K_HW_QCA9377:
d63955b3 3588 ar->regs = &qca6174_regs;
03a016f8 3589 ar->hw_ce_regs = &qcax_ce_regs;
2f2cfc4a 3590 ar->hw_values = &qca6174_values;
d63955b3 3591 break;
8bd47021 3592 case ATH10K_HW_QCA99X0:
651b4cdc 3593 case ATH10K_HW_QCA9984:
8bd47021 3594 ar->regs = &qca99x0_regs;
03a016f8 3595 ar->hw_ce_regs = &qcax_ce_regs;
8bd47021
VT		 3596 ar->hw_values = &qca99x0_values;
3597 break;
e565c312
AK		 3598 case ATH10K_HW_QCA9888:
3599 ar->regs = &qca99x0_regs;
03a016f8 3600 ar->hw_ce_regs = &qcax_ce_regs;
e565c312
AK		 3601 ar->hw_values = &qca9888_values;
3602 break;
37a219a5
RM		 3603 case ATH10K_HW_QCA4019:
3604 ar->regs = &qca4019_regs;
03a016f8 3605 ar->hw_ce_regs = &qcax_ce_regs;
37a219a5
RM		 3606 ar->hw_values = &qca4019_values;
3607 break;
f9e18304
GS		 3608 case ATH10K_HW_WCN3990:
3609 ar->regs = &wcn3990_regs;
3610 ar->hw_ce_regs = &wcn3990_ce_regs;
3611 ar->hw_values = &wcn3990_values;
3612 break;
d63955b3
MK		 3613 default:
3614 ath10k_err(ar, "unsupported core hardware revision %d\n",
3615 hw_rev);
bc2ef649 3616 ret = -EOPNOTSUPP;
d63955b3
MK		 3617 goto err_free_mac;
3618 }
3619
0d0a6939
MK		 3620 init_completion(&ar->scan.started);
3621 init_completion(&ar->scan.completed);
3622 init_completion(&ar->scan.on_channel);
3623 init_completion(&ar->target_suspend);
0e622f67 3624 init_completion(&ar->driver_recovery);
5fd3ac3c 3625 init_completion(&ar->wow.wakeup_completed);
0d0a6939
MK		 3626
3627 init_completion(&ar->install_key_done);
3628 init_completion(&ar->vdev_setup_done);
fe36e70f 3629 init_completion(&ar->vdev_delete_done);
ac2953fc 3630 init_completion(&ar->thermal.wmi_sync);
fa7937e3 3631 init_completion(&ar->bss_survey_done);
c6f537a1 3632 init_completion(&ar->peer_delete_done);
0f7cb268 3633 init_completion(&ar->peer_stats_info_complete);
0d0a6939 3634
5c81c7fd 3635 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
0d0a6939
MK		 3636
3637 ar->workqueue = create_singlethread_workqueue("ath10k_wq");
3638 if (!ar->workqueue)
e13cf7a3 3639 goto err_free_mac;
0d0a6939 3640
c8ecfc1c
RM		 3641 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
3642 if (!ar->workqueue_aux)
3643 goto err_free_wq;
3644
c8334512
WG		 3645 ar->workqueue_tx_complete =
3646 create_singlethread_workqueue("ath10k_tx_complete_wq");
3647 if (!ar->workqueue_tx_complete)
3648 goto err_free_aux_wq;
3649
0d0a6939 3650 mutex_init(&ar->conf_mutex);
38faed15 3651 mutex_init(&ar->dump_mutex);
0d0a6939
MK		 3652 spin_lock_init(&ar->data_lock);
3653
b719ebc3
AW		 3654 for (int ac = 0; ac < IEEE80211_NUM_ACS; ac++)
3655 spin_lock_init(&ar->queue_lock[ac]);
3656
0d0a6939
MK		 3657 INIT_LIST_HEAD(&ar->peers);
3658 init_waitqueue_head(&ar->peer_mapping_wq);
7962b0d8
MK		 3659 init_waitqueue_head(&ar->htt.empty_tx_wq);
3660 init_waitqueue_head(&ar->wmi.tx_credits_wq);
0d0a6939 3661
cfee8793
WG		 3662 skb_queue_head_init(&ar->htt.rx_indication_head);
3663
0d0a6939
MK		 3664 init_completion(&ar->offchan_tx_completed);
3665 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
3666 skb_queue_head_init(&ar->offchan_tx_queue);
3667
3668 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
3669 skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
3670
6782cb69 3671 INIT_WORK(&ar->register_work, ath10k_core_register_work);
0d0a6939 3672 INIT_WORK(&ar->restart_work, ath10k_core_restart);
ebee76f7
BB		 3673 INIT_WORK(&ar->set_coverage_class_work,
3674 ath10k_core_set_coverage_class_work);
0d0a6939 3675
3c97f5de
RM		 3676 init_dummy_netdev(&ar->napi_dev);
3677
e2fcf60c 3678 ret = ath10k_coredump_create(ar);
e13cf7a3 3679 if (ret)
c8334512 3680 goto err_free_tx_complete;
e13cf7a3 3681
e2fcf60c
KV		 3682 ret = ath10k_debug_create(ar);
3683 if (ret)
3684 goto err_free_coredump;
3685
0d0a6939
MK		 3686 return ar;
3687
e2fcf60c
KV		 3688err_free_coredump:
3689 ath10k_coredump_destroy(ar);
c8334512
WG		 3690err_free_tx_complete:
3691 destroy_workqueue(ar->workqueue_tx_complete);
c8ecfc1c
RM		 3692err_free_aux_wq:
3693 destroy_workqueue(ar->workqueue_aux);
e13cf7a3
MK		 3694err_free_wq:
3695 destroy_workqueue(ar->workqueue);
e13cf7a3 3696err_free_mac:
0d0a6939 3697 ath10k_mac_destroy(ar);
e13cf7a3 3698
0d0a6939
MK		 3699 return NULL;
3700}
3701EXPORT_SYMBOL(ath10k_core_create);
3702
3703void ath10k_core_destroy(struct ath10k *ar)
3704{
0d0a6939
MK		 3705 destroy_workqueue(ar->workqueue);
3706
c8ecfc1c
RM		 3707 destroy_workqueue(ar->workqueue_aux);
3708
c8334512
WG		 3709 destroy_workqueue(ar->workqueue_tx_complete);
3710
e13cf7a3 3711 ath10k_debug_destroy(ar);
e2fcf60c 3712 ath10k_coredump_destroy(ar);
9ec34a86 3713 ath10k_htt_tx_destroy(&ar->htt);
a925a376 3714 ath10k_wmi_free_host_mem(ar);
0d0a6939
MK		 3715 ath10k_mac_destroy(ar);
3716}
3717EXPORT_SYMBOL(ath10k_core_destroy);
3718
5e3dd157 3719MODULE_AUTHOR("Qualcomm Atheros");
b855de0f 3720MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards.");
5e3dd157 3721MODULE_LICENSE("Dual BSD/GPL");
Linux 6.x block layer and io_uring tree(s)