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c37d4a00 ZQ |
1 | /* |
2 | * drivers/tdm/line_ctrl/slic_ds26522.h | |
3 | * | |
4 | * Copyright 2016 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Author: Zhao Qiang <B45475@freescale.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
14 | #define DS26522_RF_ADDR_START 0x00 | |
15 | #define DS26522_RF_ADDR_END 0xef | |
16 | #define DS26522_GLB_ADDR_START 0xf0 | |
17 | #define DS26522_GLB_ADDR_END 0xff | |
18 | #define DS26522_TF_ADDR_START 0x100 | |
19 | #define DS26522_TF_ADDR_END 0x1ef | |
20 | #define DS26522_LIU_ADDR_START 0x1000 | |
21 | #define DS26522_LIU_ADDR_END 0x101f | |
22 | #define DS26522_TEST_ADDR_START 0x1008 | |
23 | #define DS26522_TEST_ADDR_END 0x101f | |
24 | #define DS26522_BERT_ADDR_START 0x1100 | |
25 | #define DS26522_BERT_ADDR_END 0x110f | |
26 | ||
27 | #define DS26522_RMMR_ADDR 0x80 | |
28 | #define DS26522_RCR1_ADDR 0x81 | |
29 | #define DS26522_RCR3_ADDR 0x83 | |
30 | #define DS26522_RIOCR_ADDR 0x84 | |
31 | ||
32 | #define DS26522_GTCR1_ADDR 0xf0 | |
33 | #define DS26522_GFCR_ADDR 0xf1 | |
34 | #define DS26522_GTCR2_ADDR 0xf2 | |
35 | #define DS26522_GTCCR_ADDR 0xf3 | |
36 | #define DS26522_GLSRR_ADDR 0xf5 | |
37 | #define DS26522_GFSRR_ADDR 0xf6 | |
38 | #define DS26522_IDR_ADDR 0xf8 | |
39 | ||
40 | #define DS26522_E1TAF_ADDR 0x164 | |
41 | #define DS26522_E1TNAF_ADDR 0x165 | |
42 | #define DS26522_TMMR_ADDR 0x180 | |
43 | #define DS26522_TCR1_ADDR 0x181 | |
44 | #define DS26522_TIOCR_ADDR 0x184 | |
45 | ||
46 | #define DS26522_LTRCR_ADDR 0x1000 | |
47 | #define DS26522_LTITSR_ADDR 0x1001 | |
48 | #define DS26522_LMCR_ADDR 0x1002 | |
49 | #define DS26522_LRISMR_ADDR 0x1007 | |
50 | ||
51 | #define MAX_NUM_OF_CHANNELS 8 | |
52 | #define PQ_MDS_8E1T1_BRD_REV 0x00 | |
53 | #define PQ_MDS_8E1T1_PLD_REV 0x00 | |
54 | ||
55 | #define DS26522_GTCCR_BPREFSEL_REFCLKIN 0xa0 | |
56 | #define DS26522_GTCCR_BFREQSEL_1544KHZ 0x08 | |
57 | #define DS26522_GTCCR_FREQSEL_1544KHZ 0x04 | |
58 | #define DS26522_GTCCR_BFREQSEL_2048KHZ 0x00 | |
59 | #define DS26522_GTCCR_FREQSEL_2048KHZ 0x00 | |
60 | ||
61 | #define DS26522_GFCR_BPCLK_2048KHZ 0x00 | |
62 | ||
63 | #define DS26522_GTCR2_TSSYNCOUT 0x02 | |
64 | #define DS26522_GTCR1 0x00 | |
65 | ||
66 | #define DS26522_GFSRR_RESET 0x01 | |
67 | #define DS26522_GFSRR_NORMAL 0x00 | |
68 | ||
69 | #define DS26522_GLSRR_RESET 0x01 | |
70 | #define DS26522_GLSRR_NORMAL 0x00 | |
71 | ||
72 | #define DS26522_RMMR_SFTRST 0x02 | |
73 | #define DS26522_RMMR_FRM_EN 0x80 | |
74 | #define DS26522_RMMR_INIT_DONE 0x40 | |
75 | #define DS26522_RMMR_T1 0x00 | |
76 | #define DS26522_RMMR_E1 0x01 | |
77 | ||
78 | #define DS26522_E1TAF_DEFAULT 0x1b | |
79 | #define DS26522_E1TNAF_DEFAULT 0x40 | |
80 | ||
81 | #define DS26522_TMMR_SFTRST 0x02 | |
82 | #define DS26522_TMMR_FRM_EN 0x80 | |
83 | #define DS26522_TMMR_INIT_DONE 0x40 | |
84 | #define DS26522_TMMR_T1 0x00 | |
85 | #define DS26522_TMMR_E1 0x01 | |
86 | ||
87 | #define DS26522_RCR1_T1_SYNCT 0x80 | |
88 | #define DS26522_RCR1_T1_RB8ZS 0x40 | |
89 | #define DS26522_RCR1_T1_SYNCC 0x08 | |
90 | ||
91 | #define DS26522_RCR1_E1_HDB3 0x40 | |
92 | #define DS26522_RCR1_E1_CCS 0x20 | |
93 | ||
94 | #define DS26522_RIOCR_1544KHZ 0x00 | |
95 | #define DS26522_RIOCR_2048KHZ 0x10 | |
96 | #define DS26522_RIOCR_RSIO_OUT 0x00 | |
97 | ||
98 | #define DS26522_RCR3_FLB 0x01 | |
99 | ||
100 | #define DS26522_TIOCR_1544KHZ 0x00 | |
101 | #define DS26522_TIOCR_2048KHZ 0x10 | |
102 | #define DS26522_TIOCR_TSIO_OUT 0x04 | |
103 | ||
104 | #define DS26522_TCR1_TB8ZS 0x04 | |
105 | ||
106 | #define DS26522_LTRCR_T1 0x02 | |
107 | #define DS26522_LTRCR_E1 0x00 | |
108 | ||
109 | #define DS26522_LTITSR_TLIS_75OHM 0x00 | |
110 | #define DS26522_LTITSR_LBOS_75OHM 0x00 | |
111 | #define DS26522_LTITSR_TLIS_100OHM 0x10 | |
112 | #define DS26522_LTITSR_TLIS_0DB_CSU 0x00 | |
113 | ||
114 | #define DS26522_LRISMR_75OHM 0x00 | |
115 | #define DS26522_LRISMR_100OHM 0x10 | |
116 | #define DS26522_LRISMR_MAX 0x03 | |
117 | ||
118 | #define DS26522_LMCR_TE 0x01 | |
119 | ||
120 | enum line_rate { | |
121 | LINE_RATE_T1, /* T1 line rate (1.544 Mbps) */ | |
122 | LINE_RATE_E1 /* E1 line rate (2.048 Mbps) */ | |
123 | }; | |
124 | ||
125 | enum tdm_trans_mode { | |
126 | NORMAL = 0, | |
127 | FRAMER_LB | |
128 | }; | |
129 | ||
130 | enum card_support_type { | |
131 | LM_CARD = 0, | |
132 | DS26522_CARD, | |
133 | NO_CARD | |
134 | }; |