projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drivers/net: Remove unnecessary k.alloc/v.alloc OOM messages
[linux-2.6-block.git] / drivers / net / wan / dscc4.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
3 *
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
6 *
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
9 *
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
12 *
13 *
14 * Theory of Operation
15 *
16 * I. Board Compatibility
17 *
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * - Errata sheet DS5 (courtesy of Michael Skerritt).
25 * Jens David has built an adapter based on the same chipset. Take a look
26 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
27 * driver.
28 * Sample code (2 revisions) is available at Infineon.
29 *
30 * II. Board-specific settings
31 *
32 * Pcisync can transmit some clock signal to the outside world on the
33 * *first two* ports provided you put a quartz and a line driver on it and
34 * remove the jumpers. The operation is described on Etinc web site. If you
35 * go DCE on these ports, don't forget to use an adequate cable.
36 *
37 * Sharing of the PCI interrupt line for this board is possible.
38 *
39 * III. Driver operation
40 *
41 * The rx/tx operations are based on a linked list of descriptors. The driver
42 * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
43 * I tried to fix it, the more it started to look like (convoluted) software
44 * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
45 * this a rfc2119 MUST.
46 *
47 * Tx direction
48 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
49 * The device is supposed to be enabled again during an ALLS irq (we could
50 * use HI but as it's easy to lose events, it's fscked).
51 *
52 * Rx direction
53 * The received frames aren't supposed to span over multiple receiving areas.
54 * I may implement it some day but it isn't the highest ranked item.
55 *
56 * IV. Notes
57 * The current error (XDU, RFO) recovery code is untested.
58 * So far, RDO takes his RX channel down and the right sequence to enable it
25985edc 59 * again is still a mystery. If RDO happens, plan a reboot. More details
1da177e4
LT		 60 * in the code (NB: as this happens, TX still works).
61 * Don't mess the cables during operation, especially on DTE ports. I don't
62 * suggest it for DCE either but at least one can get some messages instead
63 * of a complete instant freeze.
64 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
65 * the documentation/chipset releases.
66 *
67 * TODO:
68 * - test X25.
69 * - use polling at high irq/s,
70 * - performance analysis,
71 * - endianness.
72 *
73 * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
74 * - Contribution to support the new generic HDLC layer.
75 *
76 * 2002/01 Ueimor
77 * - old style interface removal
78 * - dscc4_release_ring fix (related to DMA mapping)
79 * - hard_start_xmit fix (hint: TxSizeMax)
80 * - misc crapectomy.
81 */
82
09a1732b
JP		 83#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
84
1da177e4 85#include <linux/module.h>
d43c36dc 86#include <linux/sched.h>
1da177e4
LT		 87#include <linux/types.h>
88#include <linux/errno.h>
89#include <linux/list.h>
90#include <linux/ioport.h>
91#include <linux/pci.h>
92#include <linux/kernel.h>
93#include <linux/mm.h>
5a0e3ad6 94#include <linux/slab.h>
1da177e4
LT		 95
96#include <asm/system.h>
97#include <asm/cache.h>
98#include <asm/byteorder.h>
99#include <asm/uaccess.h>
100#include <asm/io.h>
101#include <asm/irq.h>
102
103#include <linux/init.h>
a6b7a407 104#include <linux/interrupt.h>
1da177e4
LT		 105#include <linux/string.h>
106
107#include <linux/if_arp.h>
108#include <linux/netdevice.h>
109#include <linux/skbuff.h>
110#include <linux/delay.h>
1da177e4 111#include <linux/hdlc.h>
14cc3e2b 112#include <linux/mutex.h>
1da177e4
LT		 113
114/* Version */
115static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
116static int debug;
117static int quartz;
118
119#ifdef CONFIG_DSCC4_PCI_RST
14cc3e2b 120static DEFINE_MUTEX(dscc4_mutex);
1da177e4
LT		 121static u32 dscc4_pci_config_store[16];
122#endif
123
124#define DRV_NAME "dscc4"
125
126#undef DSCC4_POLLING
127
128/* Module parameters */
129
130MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
b595076a 131MODULE_DESCRIPTION("Siemens PEB20534 PCI Controller");
1da177e4
LT		 132MODULE_LICENSE("GPL");
133module_param(debug, int, 0);
134MODULE_PARM_DESC(debug,"Enable/disable extra messages");
135module_param(quartz, int, 0);
136MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
137
138/* Structures */
139
140struct thingie {
141 int define;
142 u32 bits;
143};
144
145struct TxFD {
409cd63e
AV		 146 __le32 state;
147 __le32 next;
148 __le32 data;
149 __le32 complete;
1da177e4 150 u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
409cd63e
AV		 151 /* FWIW, datasheet calls that "dummy" and says that card
152 * never looks at it; neither does the driver */
1da177e4
LT		 153};
154
155struct RxFD {
409cd63e
AV		 156 __le32 state1;
157 __le32 next;
158 __le32 data;
159 __le32 state2;
160 __le32 end;
1da177e4
LT		 161};
162
163#define DUMMY_SKB_SIZE 64
164#define TX_LOW 8
165#define TX_RING_SIZE 32
166#define RX_RING_SIZE 32
167#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
168#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
169#define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
170#define TX_TIMEOUT (HZ/10)
171#define DSCC4_HZ_MAX 33000000
172#define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
173#define dev_per_card 4
174#define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
175
176#define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
177#define TO_SIZE(state) (((state) >> 16) & 0x1fff)
178
179/*
180 * Given the operating range of Linux HDLC, the 2 defines below could be
181 * made simpler. However they are a fine reminder for the limitations of
182 * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
183 */
184#define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
185#define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
186#define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
187#define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
188
189struct dscc4_pci_priv {
409cd63e 190 __le32 *iqcfg;
1da177e4
LT		 191 int cfg_cur;
192 spinlock_t lock;
193 struct pci_dev *pdev;
194
195 struct dscc4_dev_priv *root;
196 dma_addr_t iqcfg_dma;
197 u32 xtal_hz;
198};
199
200struct dscc4_dev_priv {
201 struct sk_buff *rx_skbuff[RX_RING_SIZE];
202 struct sk_buff *tx_skbuff[TX_RING_SIZE];
203
204 struct RxFD *rx_fd;
205 struct TxFD *tx_fd;
409cd63e
AV		 206 __le32 *iqrx;
207 __le32 *iqtx;
1da177e4
LT		 208
209 /* FIXME: check all the volatile are required */
210 volatile u32 tx_current;
211 u32 rx_current;
212 u32 iqtx_current;
213 u32 iqrx_current;
214
215 volatile u32 tx_dirty;
216 volatile u32 ltda;
217 u32 rx_dirty;
218 u32 lrda;
219
220 dma_addr_t tx_fd_dma;
221 dma_addr_t rx_fd_dma;
222 dma_addr_t iqtx_dma;
223 dma_addr_t iqrx_dma;
224
225 u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
226
227 struct timer_list timer;
228
229 struct dscc4_pci_priv *pci_priv;
230 spinlock_t lock;
231
232 int dev_id;
233 volatile u32 flags;
234 u32 timer_help;
235
236 unsigned short encoding;
237 unsigned short parity;
238 struct net_device *dev;
239 sync_serial_settings settings;
240 void __iomem *base_addr;
241 u32 __pad __attribute__ ((aligned (4)));
242};
243
244/* GLOBAL registers definitions */
245#define GCMDR 0x00
246#define GSTAR 0x04
247#define GMODE 0x08
248#define IQLENR0 0x0C
249#define IQLENR1 0x10
250#define IQRX0 0x14
251#define IQTX0 0x24
252#define IQCFG 0x3c
253#define FIFOCR1 0x44
254#define FIFOCR2 0x48
255#define FIFOCR3 0x4c
256#define FIFOCR4 0x34
257#define CH0CFG 0x50
258#define CH0BRDA 0x54
259#define CH0BTDA 0x58
260#define CH0FRDA 0x98
261#define CH0FTDA 0xb0
262#define CH0LRDA 0xc8
263#define CH0LTDA 0xe0
264
265/* SCC registers definitions */
266#define SCC_START 0x0100
267#define SCC_OFFSET 0x80
268#define CMDR 0x00
269#define STAR 0x04
270#define CCR0 0x08
271#define CCR1 0x0c
272#define CCR2 0x10
273#define BRR 0x2C
274#define RLCR 0x40
275#define IMR 0x54
276#define ISR 0x58
277
278#define GPDIR 0x0400
279#define GPDATA 0x0404
280#define GPIM 0x0408
281
282/* Bit masks */
283#define EncodingMask 0x00700000
284#define CrcMask 0x00000003
285
286#define IntRxScc0 0x10000000
287#define IntTxScc0 0x01000000
288
289#define TxPollCmd 0x00000400
290#define RxActivate 0x08000000
291#define MTFi 0x04000000
292#define Rdr 0x00400000
293#define Rdt 0x00200000
294#define Idr 0x00100000
295#define Idt 0x00080000
296#define TxSccRes 0x01000000
297#define RxSccRes 0x00010000
298#define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
299#define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
300
301#define Ccr0ClockMask 0x0000003f
302#define Ccr1LoopMask 0x00000200
303#define IsrMask 0x000fffff
304#define BrrExpMask 0x00000f00
305#define BrrMultMask 0x0000003f
306#define EncodingMask 0x00700000
409cd63e 307#define Hold cpu_to_le32(0x40000000)
1da177e4
LT		 308#define SccBusy 0x10000000
309#define PowerUp 0x80000000
310#define Vis 0x00001000
311#define FrameOk (FrameVfr | FrameCrc)
312#define FrameVfr 0x80
313#define FrameRdo 0x40
314#define FrameCrc 0x20
315#define FrameRab 0x10
409cd63e
AV		 316#define FrameAborted cpu_to_le32(0x00000200)
317#define FrameEnd cpu_to_le32(0x80000000)
318#define DataComplete cpu_to_le32(0x40000000)
1da177e4
LT		 319#define LengthCheck 0x00008000
320#define SccEvt 0x02000000
321#define NoAck 0x00000200
322#define Action 0x00000001
409cd63e 323#define HiDesc cpu_to_le32(0x20000000)
1da177e4
LT		 324
325/* SCC events */
326#define RxEvt 0xf0000000
327#define TxEvt 0x0f000000
328#define Alls 0x00040000
329#define Xdu 0x00010000
330#define Cts 0x00004000
331#define Xmr 0x00002000
332#define Xpr 0x00001000
333#define Rdo 0x00000080
334#define Rfs 0x00000040
335#define Cd 0x00000004
336#define Rfo 0x00000002
337#define Flex 0x00000001
338
339/* DMA core events */
340#define Cfg 0x00200000
341#define Hi 0x00040000
342#define Fi 0x00020000
343#define Err 0x00010000
344#define Arf 0x00000002
345#define ArAck 0x00000001
346
347/* State flags */
348#define Ready 0x00000000
349#define NeedIDR 0x00000001
350#define NeedIDT 0x00000002
351#define RdoSet 0x00000004
352#define FakeReset 0x00000008
353
354/* Don't mask RDO. Ever. */
355#ifdef DSCC4_POLLING
356#define EventsMask 0xfffeef7f
357#else
358#define EventsMask 0xfffa8f7a
359#endif
360
361/* Functions prototypes */
362static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
363static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
364static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
365static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
366static int dscc4_open(struct net_device *);
d71a6749
SH		 367static netdev_tx_t dscc4_start_xmit(struct sk_buff *,
368 struct net_device *);
1da177e4
LT		 369static int dscc4_close(struct net_device *);
370static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
371static int dscc4_init_ring(struct net_device *);
372static void dscc4_release_ring(struct dscc4_dev_priv *);
373static void dscc4_timer(unsigned long);
374static void dscc4_tx_timeout(struct net_device *);
7d12e780 375static irqreturn_t dscc4_irq(int irq, void *dev_id);
1da177e4
LT		 376static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
377static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
378#ifdef DSCC4_POLLING
379static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
380#endif
381
382static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
383{
384 return dev_to_hdlc(dev)->priv;
385}
386
387static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
388{
389 return p->dev;
390}
391
392static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
393 struct net_device *dev, int offset)
394{
395 u32 state;
396
397 /* Cf scc_writel for concern regarding thread-safety */
398 state = dpriv->scc_regs[offset >> 2];
399 state &= ~mask;
400 state |= value;
401 dpriv->scc_regs[offset >> 2] = state;
402 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
403}
404
405static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
406 struct net_device *dev, int offset)
407{
408 /*
409 * Thread-UNsafe.
410 * As of 2002/02/16, there are no thread racing for access.
411 */
412 dpriv->scc_regs[offset >> 2] = bits;
413 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
414}
415
416static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
417{
418 return dpriv->scc_regs[offset >> 2];
419}
420
421static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
422{
423 /* Cf errata DS5 p.4 */
424 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
425 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
426}
427
428static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
429 struct net_device *dev)
430{
431 dpriv->ltda = dpriv->tx_fd_dma +
432 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
433 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
434 /* Flush posted writes *NOW* */
435 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
436}
437
438static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
439 struct net_device *dev)
440{
441 dpriv->lrda = dpriv->rx_fd_dma +
442 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
443 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
444}
445
446static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
447{
448 return dpriv->tx_current == dpriv->tx_dirty;
449}
450
451static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
452 struct net_device *dev)
453{
454 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
455}
456
7665a089
AB		 457static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
458 struct net_device *dev, const char *msg)
1da177e4
LT		 459{
460 int ret = 0;
461
462 if (debug > 1) {
463 if (SOURCE_ID(state) != dpriv->dev_id) {
464 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
465 dev->name, msg, SOURCE_ID(state), state );
466 ret = -1;
467 }
468 if (state & 0x0df80c00) {
469 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
470 dev->name, msg, state);
471 ret = -1;
472 }
473 }
474 return ret;
475}
476
7665a089
AB		 477static void dscc4_tx_print(struct net_device *dev,
478 struct dscc4_dev_priv *dpriv,
479 char *msg)
1da177e4
LT		 480{
481 printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
482 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
483}
484
485static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
486{
487 struct pci_dev *pdev = dpriv->pci_priv->pdev;
488 struct TxFD *tx_fd = dpriv->tx_fd;
489 struct RxFD *rx_fd = dpriv->rx_fd;
490 struct sk_buff **skbuff;
491 int i;
492
493 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
494 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
495
496 skbuff = dpriv->tx_skbuff;
497 for (i = 0; i < TX_RING_SIZE; i++) {
498 if (*skbuff) {
409cd63e
AV		 499 pci_unmap_single(pdev, le32_to_cpu(tx_fd->data),
500 (*skbuff)->len, PCI_DMA_TODEVICE);
1da177e4
LT		 501 dev_kfree_skb(*skbuff);
502 }
503 skbuff++;
504 tx_fd++;
505 }
506
507 skbuff = dpriv->rx_skbuff;
508 for (i = 0; i < RX_RING_SIZE; i++) {
509 if (*skbuff) {
409cd63e 510 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
1da177e4
LT		 511 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
512 dev_kfree_skb(*skbuff);
513 }
514 skbuff++;
515 rx_fd++;
516 }
517}
518
7665a089
AB		 519static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
520 struct net_device *dev)
1da177e4
LT		 521{
522 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
523 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
524 const int len = RX_MAX(HDLC_MAX_MRU);
525 struct sk_buff *skb;
526 int ret = 0;
527
528 skb = dev_alloc_skb(len);
529 dpriv->rx_skbuff[dirty] = skb;
530 if (skb) {
531 skb->protocol = hdlc_type_trans(skb, dev);
409cd63e
AV		 532 rx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
533 skb->data, len, PCI_DMA_FROMDEVICE));
1da177e4 534 } else {
409cd63e 535 rx_fd->data = 0;
1da177e4
LT		 536 ret = -1;
537 }
538 return ret;
539}
540
541/*
542 * IRQ/thread/whatever safe
543 */
544static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
545 struct net_device *dev, char *msg)
546{
547 s8 i = 0;
548
549 do {
550 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
551 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
552 msg, i);
553 goto done;
554 }
3173c890 555 schedule_timeout_uninterruptible(10);
1da177e4
LT		 556 rmb();
557 } while (++i > 0);
09a1732b 558 netdev_err(dev, "%s timeout\n", msg);
1da177e4
LT		 559done:
560 return (i >= 0) ? i : -EAGAIN;
561}
562
563static int dscc4_do_action(struct net_device *dev, char *msg)
564{
565 void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
566 s16 i = 0;
567
568 writel(Action, ioaddr + GCMDR);
569 ioaddr += GSTAR;
570 do {
571 u32 state = readl(ioaddr);
572
573 if (state & ArAck) {
09a1732b 574 netdev_dbg(dev, "%s ack\n", msg);
1da177e4
LT		 575 writel(ArAck, ioaddr);
576 goto done;
577 } else if (state & Arf) {
09a1732b 578 netdev_err(dev, "%s failed\n", msg);
1da177e4
LT		 579 writel(Arf, ioaddr);
580 i = -1;
581 goto done;
582 }
583 rmb();
584 } while (++i > 0);
09a1732b 585 netdev_err(dev, "%s timeout\n", msg);
1da177e4
LT		 586done:
587 return i;
588}
589
590static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
591{
592 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
593 s8 i = 0;
594
595 do {
596 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
409cd63e 597 (dpriv->iqtx[cur] & cpu_to_le32(Xpr)))
1da177e4
LT		 598 break;
599 smp_rmb();
3173c890 600 schedule_timeout_uninterruptible(10);
1da177e4
LT		 601 } while (++i > 0);
602
603 return (i >= 0 ) ? i : -EAGAIN;
604}
605
606#if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
607static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
608{
609 unsigned long flags;
610
611 spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
612 /* Cf errata DS5 p.6 */
613 writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
614 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
615 readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
616 writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
617 writel(Action, dpriv->base_addr + GCMDR);
618 spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
619}
620
621#endif
622
623#if 0
624static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
625{
626 u16 i = 0;
627
628 /* Cf errata DS5 p.7 */
629 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
630 scc_writel(0x00050000, dpriv, dev, CCR2);
631 /*
632 * Must be longer than the time required to fill the fifo.
633 */
634 while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
635 udelay(1);
636 wmb();
637 }
638
639 writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
640 if (dscc4_do_action(dev, "Rdt") < 0)
09a1732b 641 netdev_err(dev, "Tx reset failed\n");
1da177e4
LT		 642}
643#endif
644
645/* TODO: (ab)use this function to refill a completely depleted RX ring. */
646static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
647 struct net_device *dev)
648{
649 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
1da177e4
LT		 650 struct pci_dev *pdev = dpriv->pci_priv->pdev;
651 struct sk_buff *skb;
652 int pkt_len;
653
654 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
655 if (!skb) {
b39d66a8 656 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __func__);
1da177e4
LT		 657 goto refill;
658 }
409cd63e
AV		 659 pkt_len = TO_SIZE(le32_to_cpu(rx_fd->state2));
660 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
661 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
1da177e4 662 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
198191c4
KH		 663 dev->stats.rx_packets++;
664 dev->stats.rx_bytes += pkt_len;
1da177e4
LT		 665 skb_put(skb, pkt_len);
666 if (netif_running(dev))
667 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4
LT		 668 netif_rx(skb);
669 } else {
670 if (skb->data[pkt_len] & FrameRdo)
198191c4 671 dev->stats.rx_fifo_errors++;
5de3fcab 672 else if (!(skb->data[pkt_len] & FrameCrc))
198191c4 673 dev->stats.rx_crc_errors++;
5de3fcab 674 else if ((skb->data[pkt_len] & (FrameVfr | FrameRab)) !=
fab4e763 675 (FrameVfr | FrameRab))
198191c4 676 dev->stats.rx_length_errors++;
5de3fcab 677 dev->stats.rx_errors++;
1da177e4
LT		 678 dev_kfree_skb_irq(skb);
679 }
680refill:
681 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
682 if (try_get_rx_skb(dpriv, dev) < 0)
683 break;
684 dpriv->rx_dirty++;
685 }
686 dscc4_rx_update(dpriv, dev);
687 rx_fd->state2 = 0x00000000;
409cd63e 688 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 689}
690
691static void dscc4_free1(struct pci_dev *pdev)
692{
693 struct dscc4_pci_priv *ppriv;
694 struct dscc4_dev_priv *root;
695 int i;
696
697 ppriv = pci_get_drvdata(pdev);
698 root = ppriv->root;
699
700 for (i = 0; i < dev_per_card; i++)
701 unregister_hdlc_device(dscc4_to_dev(root + i));
702
703 pci_set_drvdata(pdev, NULL);
704
705 for (i = 0; i < dev_per_card; i++)
706 free_netdev(root[i].dev);
707 kfree(root);
708 kfree(ppriv);
709}
710
711static int __devinit dscc4_init_one(struct pci_dev *pdev,
712 const struct pci_device_id *ent)
713{
714 struct dscc4_pci_priv *priv;
715 struct dscc4_dev_priv *dpriv;
716 void __iomem *ioaddr;
717 int i, rc;
718
719 printk(KERN_DEBUG "%s", version);
720
721 rc = pci_enable_device(pdev);
722 if (rc < 0)
723 goto out;
724
725 rc = pci_request_region(pdev, 0, "registers");
726 if (rc < 0) {
09a1732b 727 pr_err("can't reserve MMIO region (regs)\n");
1da177e4
LT		 728 goto err_disable_0;
729 }
730 rc = pci_request_region(pdev, 1, "LBI interface");
731 if (rc < 0) {
09a1732b 732 pr_err("can't reserve MMIO region (lbi)\n");
1da177e4
LT		 733 goto err_free_mmio_region_1;
734 }
735
275f165f 736 ioaddr = pci_ioremap_bar(pdev, 0);
1da177e4 737 if (!ioaddr) {
09a1732b
JP		 738 pr_err("cannot remap MMIO region %llx @ %llx\n",
739 (unsigned long long)pci_resource_len(pdev, 0),
740 (unsigned long long)pci_resource_start(pdev, 0));
1da177e4
LT		 741 rc = -EIO;
742 goto err_free_mmio_regions_2;
743 }
7c7459d1
GKH		 744 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n",
745 (unsigned long long)pci_resource_start(pdev, 0),
746 (unsigned long long)pci_resource_start(pdev, 1), pdev->irq);
1da177e4
LT		 747
748 /* Cf errata DS5 p.2 */
749 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
750 pci_set_master(pdev);
751
752 rc = dscc4_found1(pdev, ioaddr);
753 if (rc < 0)
754 goto err_iounmap_3;
755
756 priv = pci_get_drvdata(pdev);
757
1fb9df5d 758 rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root);
1da177e4 759 if (rc < 0) {
09a1732b 760 pr_warn("IRQ %d busy\n", pdev->irq);
1da177e4
LT		 761 goto err_release_4;
762 }
763
764 /* power up/little endian/dma core controlled via lrda/ltda */
765 writel(0x00000001, ioaddr + GMODE);
766 /* Shared interrupt queue */
767 {
768 u32 bits;
769
770 bits = (IRQ_RING_SIZE >> 5) - 1;
771 bits |= bits << 4;
772 bits |= bits << 8;
773 bits |= bits << 16;
774 writel(bits, ioaddr + IQLENR0);
775 }
776 /* Global interrupt queue */
777 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
409cd63e
AV		 778 priv->iqcfg = (__le32 *) pci_alloc_consistent(pdev,
779 IRQ_RING_SIZE*sizeof(__le32), &priv->iqcfg_dma);
1da177e4
LT		 780 if (!priv->iqcfg)
781 goto err_free_irq_5;
782 writel(priv->iqcfg_dma, ioaddr + IQCFG);
783
784 rc = -ENOMEM;
785
786 /*
787 * SCC 0-3 private rx/tx irq structures
788 * IQRX/TXi needs to be set soon. Learned it the hard way...
789 */
790 for (i = 0; i < dev_per_card; i++) {
791 dpriv = priv->root + i;
409cd63e 792 dpriv->iqtx = (__le32 *) pci_alloc_consistent(pdev,
1da177e4
LT		 793 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
794 if (!dpriv->iqtx)
795 goto err_free_iqtx_6;
796 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
797 }
798 for (i = 0; i < dev_per_card; i++) {
799 dpriv = priv->root + i;
409cd63e 800 dpriv->iqrx = (__le32 *) pci_alloc_consistent(pdev,
1da177e4
LT		 801 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
802 if (!dpriv->iqrx)
803 goto err_free_iqrx_7;
804 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
805 }
806
807 /* Cf application hint. Beware of hard-lock condition on threshold. */
808 writel(0x42104000, ioaddr + FIFOCR1);
809 //writel(0x9ce69800, ioaddr + FIFOCR2);
810 writel(0xdef6d800, ioaddr + FIFOCR2);
811 //writel(0x11111111, ioaddr + FIFOCR4);
812 writel(0x18181818, ioaddr + FIFOCR4);
813 // FIXME: should depend on the chipset revision
814 writel(0x0000000e, ioaddr + FIFOCR3);
815
816 writel(0xff200001, ioaddr + GCMDR);
817
818 rc = 0;
819out:
820 return rc;
821
822err_free_iqrx_7:
823 while (--i >= 0) {
824 dpriv = priv->root + i;
825 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
826 dpriv->iqrx, dpriv->iqrx_dma);
827 }
828 i = dev_per_card;
829err_free_iqtx_6:
830 while (--i >= 0) {
831 dpriv = priv->root + i;
832 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
833 dpriv->iqtx, dpriv->iqtx_dma);
834 }
835 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
836 priv->iqcfg_dma);
837err_free_irq_5:
838 free_irq(pdev->irq, priv->root);
839err_release_4:
840 dscc4_free1(pdev);
841err_iounmap_3:
842 iounmap (ioaddr);
843err_free_mmio_regions_2:
844 pci_release_region(pdev, 1);
845err_free_mmio_region_1:
846 pci_release_region(pdev, 0);
847err_disable_0:
848 pci_disable_device(pdev);
849 goto out;
850};
851
852/*
853 * Let's hope the default values are decent enough to protect my
854 * feet from the user's gun - Ueimor
855 */
856static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
857 struct net_device *dev)
858{
859 /* No interrupts, SCC core disabled. Let's relax */
860 scc_writel(0x00000000, dpriv, dev, CCR0);
861
862 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
863
864 /*
865 * No address recognition/crc-CCITT/cts enabled
866 * Shared flags transmission disabled - cf errata DS5 p.11
867 * Carrier detect disabled - cf errata p.14
868 * FIXME: carrier detection/polarity may be handled more gracefully.
869 */
870 scc_writel(0x02408000, dpriv, dev, CCR1);
871
872 /* crc not forwarded - Cf errata DS5 p.11 */
873 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
874 // crc forwarded
875 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
876}
877
878static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
879{
880 int ret = 0;
881
882 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
883 ret = -EOPNOTSUPP;
884 else
885 dpriv->pci_priv->xtal_hz = hz;
886
887 return ret;
888}
889
991990a1
KH		 890static const struct net_device_ops dscc4_ops = {
891 .ndo_open = dscc4_open,
892 .ndo_stop = dscc4_close,
893 .ndo_change_mtu = hdlc_change_mtu,
894 .ndo_start_xmit = hdlc_start_xmit,
895 .ndo_do_ioctl = dscc4_ioctl,
896 .ndo_tx_timeout = dscc4_tx_timeout,
897};
898
1da177e4
LT		 899static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
900{
901 struct dscc4_pci_priv *ppriv;
902 struct dscc4_dev_priv *root;
903 int i, ret = -ENOMEM;
904
dd00cc48 905 root = kcalloc(dev_per_card, sizeof(*root), GFP_KERNEL);
e404decb 906 if (!root)
1da177e4 907 goto err_out;
1da177e4
LT		 908
909 for (i = 0; i < dev_per_card; i++) {
910 root[i].dev = alloc_hdlcdev(root + i);
911 if (!root[i].dev)
912 goto err_free_dev;
913 }
914
dd00cc48 915 ppriv = kzalloc(sizeof(*ppriv), GFP_KERNEL);
e404decb 916 if (!ppriv)
1da177e4 917 goto err_free_dev;
1da177e4
LT		 918
919 ppriv->root = root;
920 spin_lock_init(&ppriv->lock);
921
922 for (i = 0; i < dev_per_card; i++) {
923 struct dscc4_dev_priv *dpriv = root + i;
924 struct net_device *d = dscc4_to_dev(dpriv);
925 hdlc_device *hdlc = dev_to_hdlc(d);
926
927 d->base_addr = (unsigned long)ioaddr;
1da177e4 928 d->irq = pdev->irq;
991990a1 929 d->netdev_ops = &dscc4_ops;
1da177e4 930 d->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 931 SET_NETDEV_DEV(d, &pdev->dev);
932
933 dpriv->dev_id = i;
934 dpriv->pci_priv = ppriv;
935 dpriv->base_addr = ioaddr;
936 spin_lock_init(&dpriv->lock);
937
938 hdlc->xmit = dscc4_start_xmit;
939 hdlc->attach = dscc4_hdlc_attach;
940
941 dscc4_init_registers(dpriv, d);
942 dpriv->parity = PARITY_CRC16_PR0_CCITT;
943 dpriv->encoding = ENCODING_NRZ;
944
945 ret = dscc4_init_ring(d);
946 if (ret < 0)
947 goto err_unregister;
948
949 ret = register_hdlc_device(d);
950 if (ret < 0) {
09a1732b 951 pr_err("unable to register\n");
1da177e4
LT		 952 dscc4_release_ring(dpriv);
953 goto err_unregister;
954 }
955 }
956
957 ret = dscc4_set_quartz(root, quartz);
958 if (ret < 0)
959 goto err_unregister;
960
961 pci_set_drvdata(pdev, ppriv);
962 return ret;
963
964err_unregister:
965 while (i-- > 0) {
966 dscc4_release_ring(root + i);
967 unregister_hdlc_device(dscc4_to_dev(root + i));
968 }
969 kfree(ppriv);
970 i = dev_per_card;
971err_free_dev:
972 while (i-- > 0)
973 free_netdev(root[i].dev);
974 kfree(root);
975err_out:
976 return ret;
977};
978
979/* FIXME: get rid of the unneeded code */
980static void dscc4_timer(unsigned long data)
981{
982 struct net_device *dev = (struct net_device *)data;
983 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
984// struct dscc4_pci_priv *ppriv;
985
986 goto done;
987done:
988 dpriv->timer.expires = jiffies + TX_TIMEOUT;
989 add_timer(&dpriv->timer);
990}
991
992static void dscc4_tx_timeout(struct net_device *dev)
993{
994 /* FIXME: something is missing there */
995}
996
997static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
998{
999 sync_serial_settings *settings = &dpriv->settings;
1000
1001 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
1002 struct net_device *dev = dscc4_to_dev(dpriv);
1003
09a1732b 1004 netdev_info(dev, "loopback requires clock\n");
1da177e4
LT		 1005 return -1;
1006 }
1007 return 0;
1008}
1009
1010#ifdef CONFIG_DSCC4_PCI_RST
1011/*
1012 * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
1013 * so as to provide a safe way to reset the asic while not the whole machine
1014 * rebooting.
1015 *
1016 * This code doesn't need to be efficient. Keep It Simple
1017 */
1018static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
1019{
1020 int i;
1021
14cc3e2b 1022 mutex_lock(&dscc4_mutex);
1da177e4
LT		 1023 for (i = 0; i < 16; i++)
1024 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1025
1026 /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1027 writel(0x001c0000, ioaddr + GMODE);
1028 /* Configure GPIO port as output */
1029 writel(0x0000ffff, ioaddr + GPDIR);
1030 /* Disable interruption */
1031 writel(0x0000ffff, ioaddr + GPIM);
1032
1033 writel(0x0000ffff, ioaddr + GPDATA);
1034 writel(0x00000000, ioaddr + GPDATA);
1035
1036 /* Flush posted writes */
1037 readl(ioaddr + GSTAR);
1038
3173c890 1039 schedule_timeout_uninterruptible(10);
1da177e4
LT		 1040
1041 for (i = 0; i < 16; i++)
1042 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
14cc3e2b 1043 mutex_unlock(&dscc4_mutex);
1da177e4
LT		 1044}
1045#else
1046#define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1047#endif /* CONFIG_DSCC4_PCI_RST */
1048
1049static int dscc4_open(struct net_device *dev)
1050{
1051 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1052 struct dscc4_pci_priv *ppriv;
1053 int ret = -EAGAIN;
1054
991990a1 1055 if ((dscc4_loopback_check(dpriv) < 0))
1da177e4
LT		 1056 goto err;
1057
1058 if ((ret = hdlc_open(dev)))
1059 goto err;
1060
1061 ppriv = dpriv->pci_priv;
1062
1063 /*
1064 * Due to various bugs, there is no way to reliably reset a
25985edc 1065 * specific port (manufacturer's dependent special PCI #RST wiring
1da177e4
LT		 1066 * apart: it affects all ports). Thus the device goes in the best
1067 * silent mode possible at dscc4_close() time and simply claims to
1068 * be up if it's opened again. It still isn't possible to change
1069 * the HDLC configuration without rebooting but at least the ports
1070 * can be up/down ifconfig'ed without killing the host.
1071 */
1072 if (dpriv->flags & FakeReset) {
1073 dpriv->flags &= ~FakeReset;
1074 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1075 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1076 scc_writel(EventsMask, dpriv, dev, IMR);
09a1732b 1077 netdev_info(dev, "up again\n");
1da177e4
LT		 1078 goto done;
1079 }
1080
1081 /* IDT+IDR during XPR */
1082 dpriv->flags = NeedIDR | NeedIDT;
1083
1084 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1085
1086 /*
1087 * The following is a bit paranoid...
1088 *
1089 * NB: the datasheet "...CEC will stay active if the SCC is in
1090 * power-down mode or..." and CCR2.RAC = 1 are two different
1091 * situations.
1092 */
1093 if (scc_readl_star(dpriv, dev) & SccBusy) {
09a1732b 1094 netdev_err(dev, "busy - try later\n");
1da177e4
LT		 1095 ret = -EAGAIN;
1096 goto err_out;
1097 } else
09a1732b 1098 netdev_info(dev, "available - good\n");
1da177e4
LT		 1099
1100 scc_writel(EventsMask, dpriv, dev, IMR);
1101
1102 /* Posted write is flushed in the wait_ack loop */
1103 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1104
1105 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1106 goto err_disable_scc_events;
1107
1108 /*
1109 * I would expect XPR near CE completion (before ? after ?).
1110 * At worst, this code won't see a late XPR and people
1111 * will have to re-issue an ifconfig (this is harmless).
1112 * WARNING, a really missing XPR usually means a hardware
1113 * reset is needed. Suggestions anyone ?
1114 */
1115 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
09a1732b 1116 pr_err("XPR timeout\n");
1da177e4
LT		 1117 goto err_disable_scc_events;
1118 }
1119
1120 if (debug > 2)
1121 dscc4_tx_print(dev, dpriv, "Open");
1122
1123done:
1124 netif_start_queue(dev);
1125
1126 init_timer(&dpriv->timer);
1127 dpriv->timer.expires = jiffies + 10*HZ;
1128 dpriv->timer.data = (unsigned long)dev;
d8bda9f1 1129 dpriv->timer.function = dscc4_timer;
1da177e4
LT		 1130 add_timer(&dpriv->timer);
1131 netif_carrier_on(dev);
1132
1133 return 0;
1134
1135err_disable_scc_events:
1136 scc_writel(0xffffffff, dpriv, dev, IMR);
1137 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1138err_out:
1139 hdlc_close(dev);
1140err:
1141 return ret;
1142}
1143
1144#ifdef DSCC4_POLLING
1145static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1146{
1147 /* FIXME: it's gonna be easy (TM), for sure */
1148}
1149#endif /* DSCC4_POLLING */
1150
d71a6749
SH		 1151static netdev_tx_t dscc4_start_xmit(struct sk_buff *skb,
1152 struct net_device *dev)
1da177e4
LT		 1153{
1154 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1155 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1156 struct TxFD *tx_fd;
1157 int next;
1158
1159 next = dpriv->tx_current%TX_RING_SIZE;
1160 dpriv->tx_skbuff[next] = skb;
1161 tx_fd = dpriv->tx_fd + next;
1162 tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
409cd63e
AV		 1163 tx_fd->data = cpu_to_le32(pci_map_single(ppriv->pdev, skb->data, skb->len,
1164 PCI_DMA_TODEVICE));
1da177e4
LT		 1165 tx_fd->complete = 0x00000000;
1166 tx_fd->jiffies = jiffies;
1167 mb();
1168
1169#ifdef DSCC4_POLLING
1170 spin_lock(&dpriv->lock);
1171 while (dscc4_tx_poll(dpriv, dev));
1172 spin_unlock(&dpriv->lock);
1173#endif
1174
1da177e4
LT		 1175 if (debug > 2)
1176 dscc4_tx_print(dev, dpriv, "Xmit");
1177 /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1178 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1179 netif_stop_queue(dev);
1180
1181 if (dscc4_tx_quiescent(dpriv, dev))
1182 dscc4_do_tx(dpriv, dev);
1183
ec634fe3 1184 return NETDEV_TX_OK;
1da177e4
LT		 1185}
1186
1187static int dscc4_close(struct net_device *dev)
1188{
1189 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1190
1191 del_timer_sync(&dpriv->timer);
1192 netif_stop_queue(dev);
1193
1194 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1195 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1196 scc_writel(0xffffffff, dpriv, dev, IMR);
1197
1198 dpriv->flags |= FakeReset;
1199
1200 hdlc_close(dev);
1201
1202 return 0;
1203}
1204
1205static inline int dscc4_check_clock_ability(int port)
1206{
1207 int ret = 0;
1208
1209#ifdef CONFIG_DSCC4_PCISYNC
1210 if (port >= 2)
1211 ret = -1;
1212#endif
1213 return ret;
1214}
1215
1216/*
1217 * DS1 p.137: "There are a total of 13 different clocking modes..."
1218 * ^^
1219 * Design choices:
1220 * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1221 * Clock mode 3b _should_ work but the testing seems to make this point
1222 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1223 * This is supposed to provide least surprise "DTE like" behavior.
1224 * - if line rate is specified, clocks are assumed to be locally generated.
1225 * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1226 * between these it automagically done according on the required frequency
1227 * scaling. Of course some rounding may take place.
1228 * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1229 * appropriate external clocking device for testing.
25985edc 1230 * - no time-slot/clock mode 5: shameless laziness.
1da177e4 1231 *
25985edc 1232 * The clock signals wiring can be (is ?) manufacturer dependent. Good luck.
1da177e4
LT		 1233 *
1234 * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1235 * won't pass the init sequence. For example, straight back-to-back DTE without
1236 * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1237 * called.
1238 *
1239 * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1240 * DS0 for example)
1241 *
1242 * Clock mode related bits of CCR0:
1243 * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1244 * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1245 * | | +-------- High Speed: say 0
1246 * | | | +-+-+-- Clock Mode: 0..7
1247 * | | | | | |
1248 * -+-+-+-+-+-+-+-+
1249 * x|x|5|4|3|2|1|0| lower bits
1250 *
1251 * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1252 * +-+-+-+------------------ M (0..15)
1253 * | | | | +-+-+-+-+-+-- N (0..63)
1254 * 0 0 0 0 | | | | 0 0 | | | | | |
1255 * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1256 * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1257 *
1258 */
1259static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1260{
1261 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1262 int ret = -1;
1263 u32 brr;
1264
1265 *state &= ~Ccr0ClockMask;
1266 if (*bps) { /* Clock generated - required for DCE */
1267 u32 n = 0, m = 0, divider;
1268 int xtal;
1269
1270 xtal = dpriv->pci_priv->xtal_hz;
1271 if (!xtal)
1272 goto done;
1273 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1274 goto done;
1275 divider = xtal / *bps;
1276 if (divider > BRR_DIVIDER_MAX) {
1277 divider >>= 4;
1278 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1279 } else
1280 *state |= 0x00000037; /* Clock mode 7b (BRG) */
1281 if (divider >> 22) {
1282 n = 63;
1283 m = 15;
1284 } else if (divider) {
1285 /* Extraction of the 6 highest weighted bits */
1286 m = 0;
1287 while (0xffffffc0 & divider) {
1288 m++;
1289 divider >>= 1;
1290 }
1291 n = divider;
1292 }
1293 brr = (m << 8) | n;
1294 divider = n << m;
1295 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1296 divider <<= 4;
1297 *bps = xtal / divider;
1298 } else {
1299 /*
1300 * External clock - DTE
1301 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1302 * Nothing more to be done
1303 */
1304 brr = 0;
1305 }
1306 scc_writel(brr, dpriv, dev, BRR);
1307 ret = 0;
1308done:
1309 return ret;
1310}
1311
1312static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1313{
1314 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1315 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1316 const size_t size = sizeof(dpriv->settings);
1317 int ret = 0;
1318
1319 if (dev->flags & IFF_UP)
1320 return -EBUSY;
1321
1322 if (cmd != SIOCWANDEV)
1323 return -EOPNOTSUPP;
1324
1325 switch(ifr->ifr_settings.type) {
1326 case IF_GET_IFACE:
1327 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1328 if (ifr->ifr_settings.size < size) {
1329 ifr->ifr_settings.size = size; /* data size wanted */
1330 return -ENOBUFS;
1331 }
1332 if (copy_to_user(line, &dpriv->settings, size))
1333 return -EFAULT;
1334 break;
1335
1336 case IF_IFACE_SYNC_SERIAL:
1337 if (!capable(CAP_NET_ADMIN))
1338 return -EPERM;
1339
1340 if (dpriv->flags & FakeReset) {
09a1732b 1341 netdev_info(dev, "please reset the device before this command\n");
1da177e4
LT		 1342 return -EPERM;
1343 }
1344 if (copy_from_user(&dpriv->settings, line, size))
1345 return -EFAULT;
1346 ret = dscc4_set_iface(dpriv, dev);
1347 break;
1348
1349 default:
1350 ret = hdlc_ioctl(dev, ifr, cmd);
1351 break;
1352 }
1353
1354 return ret;
1355}
1356
215faf9c 1357static int dscc4_match(const struct thingie *p, int value)
1da177e4
LT		 1358{
1359 int i;
1360
1361 for (i = 0; p[i].define != -1; i++) {
1362 if (value == p[i].define)
1363 break;
1364 }
1365 if (p[i].define == -1)
1366 return -1;
1367 else
1368 return i;
1369}
1370
1371static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1372 struct net_device *dev)
1373{
1374 sync_serial_settings *settings = &dpriv->settings;
1375 int ret = -EOPNOTSUPP;
1376 u32 bps, state;
1377
1378 bps = settings->clock_rate;
1379 state = scc_readl(dpriv, CCR0);
1380 if (dscc4_set_clock(dev, &bps, &state) < 0)
1381 goto done;
1382 if (bps) { /* DCE */
1383 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1384 if (settings->clock_rate != bps) {
1385 printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1386 dev->name, settings->clock_rate, bps);
1387 settings->clock_rate = bps;
1388 }
1389 } else { /* DTE */
1390 state |= PowerUp | Vis;
1391 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1392 }
1393 scc_writel(state, dpriv, dev, CCR0);
1394 ret = 0;
1395done:
1396 return ret;
1397}
1398
1399static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1400 struct net_device *dev)
1401{
215faf9c 1402 static const struct thingie encoding[] = {
1da177e4
LT		 1403 { ENCODING_NRZ, 0x00000000 },
1404 { ENCODING_NRZI, 0x00200000 },
1405 { ENCODING_FM_MARK, 0x00400000 },
1406 { ENCODING_FM_SPACE, 0x00500000 },
1407 { ENCODING_MANCHESTER, 0x00600000 },
1408 { -1, 0}
1409 };
1410 int i, ret = 0;
1411
1412 i = dscc4_match(encoding, dpriv->encoding);
1413 if (i >= 0)
1414 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1415 else
1416 ret = -EOPNOTSUPP;
1417 return ret;
1418}
1419
1420static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1421 struct net_device *dev)
1422{
1423 sync_serial_settings *settings = &dpriv->settings;
1424 u32 state;
1425
1426 state = scc_readl(dpriv, CCR1);
1427 if (settings->loopback) {
1428 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1429 state |= 0x00000100;
1430 } else {
1431 printk(KERN_DEBUG "%s: normal\n", dev->name);
1432 state &= ~0x00000100;
1433 }
1434 scc_writel(state, dpriv, dev, CCR1);
1435 return 0;
1436}
1437
1438static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1439 struct net_device *dev)
1440{
215faf9c 1441 static const struct thingie crc[] = {
1da177e4
LT		 1442 { PARITY_CRC16_PR0_CCITT, 0x00000010 },
1443 { PARITY_CRC16_PR1_CCITT, 0x00000000 },
1444 { PARITY_CRC32_PR0_CCITT, 0x00000011 },
1445 { PARITY_CRC32_PR1_CCITT, 0x00000001 }
1446 };
1447 int i, ret = 0;
1448
1449 i = dscc4_match(crc, dpriv->parity);
1450 if (i >= 0)
1451 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1452 else
1453 ret = -EOPNOTSUPP;
1454 return ret;
1455}
1456
1457static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1458{
1459 struct {
1460 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1461 } *p, do_setting[] = {
1462 { dscc4_encoding_setting },
1463 { dscc4_clock_setting },
1464 { dscc4_loopback_setting },
1465 { dscc4_crc_setting },
1466 { NULL }
1467 };
1468 int ret = 0;
1469
1470 for (p = do_setting; p->action; p++) {
1471 if ((ret = p->action(dpriv, dev)) < 0)
1472 break;
1473 }
1474 return ret;
1475}
1476
7d12e780 1477static irqreturn_t dscc4_irq(int irq, void *token)
1da177e4
LT		 1478{
1479 struct dscc4_dev_priv *root = token;
1480 struct dscc4_pci_priv *priv;
1481 struct net_device *dev;
1482 void __iomem *ioaddr;
1483 u32 state;
1484 unsigned long flags;
1485 int i, handled = 1;
1486
1487 priv = root->pci_priv;
1488 dev = dscc4_to_dev(root);
1489
1490 spin_lock_irqsave(&priv->lock, flags);
1491
1492 ioaddr = root->base_addr;
1493
1494 state = readl(ioaddr + GSTAR);
1495 if (!state) {
1496 handled = 0;
1497 goto out;
1498 }
1499 if (debug > 3)
1500 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1501 writel(state, ioaddr + GSTAR);
1502
1503 if (state & Arf) {
09a1732b 1504 netdev_err(dev, "failure (Arf). Harass the maintainer\n");
1da177e4
LT		 1505 goto out;
1506 }
1507 state &= ~ArAck;
1508 if (state & Cfg) {
1509 if (debug > 0)
1510 printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
409cd63e 1511 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & cpu_to_le32(Arf))
09a1732b 1512 netdev_err(dev, "CFG failed\n");
1da177e4
LT		 1513 if (!(state &= ~Cfg))
1514 goto out;
1515 }
1516 if (state & RxEvt) {
1517 i = dev_per_card - 1;
1518 do {
1519 dscc4_rx_irq(priv, root + i);
1520 } while (--i >= 0);
1521 state &= ~RxEvt;
1522 }
1523 if (state & TxEvt) {
1524 i = dev_per_card - 1;
1525 do {
1526 dscc4_tx_irq(priv, root + i);
1527 } while (--i >= 0);
1528 state &= ~TxEvt;
1529 }
1530out:
1531 spin_unlock_irqrestore(&priv->lock, flags);
1532 return IRQ_RETVAL(handled);
1533}
1534
1535static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1536 struct dscc4_dev_priv *dpriv)
1537{
1538 struct net_device *dev = dscc4_to_dev(dpriv);
1539 u32 state;
1540 int cur, loop = 0;
1541
1542try:
1543 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
409cd63e 1544 state = le32_to_cpu(dpriv->iqtx[cur]);
1da177e4
LT		 1545 if (!state) {
1546 if (debug > 4)
1547 printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1548 state);
1549 if ((debug > 1) && (loop > 1))
1550 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1551 if (loop && netif_queue_stopped(dev))
1552 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1553 netif_wake_queue(dev);
1554
1555 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1556 !dscc4_tx_done(dpriv))
1557 dscc4_do_tx(dpriv, dev);
1558 return;
1559 }
1560 loop++;
1561 dpriv->iqtx[cur] = 0;
1562 dpriv->iqtx_current++;
1563
1564 if (state_check(state, dpriv, dev, "Tx") < 0)
1565 return;
1566
1567 if (state & SccEvt) {
1568 if (state & Alls) {
1da177e4
LT		 1569 struct sk_buff *skb;
1570 struct TxFD *tx_fd;
1571
1572 if (debug > 2)
1573 dscc4_tx_print(dev, dpriv, "Alls");
1574 /*
1575 * DataComplete can't be trusted for Tx completion.
1576 * Cf errata DS5 p.8
1577 */
1578 cur = dpriv->tx_dirty%TX_RING_SIZE;
1579 tx_fd = dpriv->tx_fd + cur;
1580 skb = dpriv->tx_skbuff[cur];
1581 if (skb) {
409cd63e 1582 pci_unmap_single(ppriv->pdev, le32_to_cpu(tx_fd->data),
1da177e4
LT		 1583 skb->len, PCI_DMA_TODEVICE);
1584 if (tx_fd->state & FrameEnd) {
198191c4
KH		 1585 dev->stats.tx_packets++;
1586 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 1587 }
1588 dev_kfree_skb_irq(skb);
1589 dpriv->tx_skbuff[cur] = NULL;
1590 ++dpriv->tx_dirty;
1591 } else {
1592 if (debug > 1)
09a1732b
JP		 1593 netdev_err(dev, "Tx: NULL skb %d\n",
1594 cur);
1da177e4
LT		 1595 }
1596 /*
1597 * If the driver ends sending crap on the wire, it
1598 * will be way easier to diagnose than the (not so)
1599 * random freeze induced by null sized tx frames.
1600 */
1601 tx_fd->data = tx_fd->next;
1602 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1603 tx_fd->complete = 0x00000000;
1604 tx_fd->jiffies = 0;
1605
1606 if (!(state &= ~Alls))
1607 goto try;
1608 }
1609 /*
1610 * Transmit Data Underrun
1611 */
1612 if (state & Xdu) {
09a1732b 1613 netdev_err(dev, "Tx Data Underrun. Ask maintainer\n");
1da177e4
LT		 1614 dpriv->flags = NeedIDT;
1615 /* Tx reset */
1616 writel(MTFi | Rdt,
1617 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1618 writel(Action, dpriv->base_addr + GCMDR);
1619 return;
1620 }
1621 if (state & Cts) {
09a1732b 1622 netdev_info(dev, "CTS transition\n");
1da177e4
LT		 1623 if (!(state &= ~Cts)) /* DEBUG */
1624 goto try;
1625 }
1626 if (state & Xmr) {
1627 /* Frame needs to be sent again - FIXME */
09a1732b 1628 netdev_err(dev, "Tx ReTx. Ask maintainer\n");
1da177e4
LT		 1629 if (!(state &= ~Xmr)) /* DEBUG */
1630 goto try;
1631 }
1632 if (state & Xpr) {
1633 void __iomem *scc_addr;
1634 unsigned long ring;
1635 int i;
1636
1637 /*
1638 * - the busy condition happens (sometimes);
1639 * - it doesn't seem to make the handler unreliable.
1640 */
1641 for (i = 1; i; i <<= 1) {
1642 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1643 break;
1644 }
1645 if (!i)
09a1732b 1646 netdev_info(dev, "busy in irq\n");
1da177e4
LT		 1647
1648 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1649 /* Keep this order: IDT before IDR */
1650 if (dpriv->flags & NeedIDT) {
1651 if (debug > 2)
1652 dscc4_tx_print(dev, dpriv, "Xpr");
1653 ring = dpriv->tx_fd_dma +
1654 (dpriv->tx_dirty%TX_RING_SIZE)*
1655 sizeof(struct TxFD);
1656 writel(ring, scc_addr + CH0BTDA);
1657 dscc4_do_tx(dpriv, dev);
1658 writel(MTFi | Idt, scc_addr + CH0CFG);
1659 if (dscc4_do_action(dev, "IDT") < 0)
1660 goto err_xpr;
1661 dpriv->flags &= ~NeedIDT;
1662 }
1663 if (dpriv->flags & NeedIDR) {
1664 ring = dpriv->rx_fd_dma +
1665 (dpriv->rx_current%RX_RING_SIZE)*
1666 sizeof(struct RxFD);
1667 writel(ring, scc_addr + CH0BRDA);
1668 dscc4_rx_update(dpriv, dev);
1669 writel(MTFi | Idr, scc_addr + CH0CFG);
1670 if (dscc4_do_action(dev, "IDR") < 0)
1671 goto err_xpr;
1672 dpriv->flags &= ~NeedIDR;
1673 smp_wmb();
1674 /* Activate receiver and misc */
1675 scc_writel(0x08050008, dpriv, dev, CCR2);
1676 }
1677 err_xpr:
1678 if (!(state &= ~Xpr))
1679 goto try;
1680 }
1681 if (state & Cd) {
1682 if (debug > 0)
09a1732b 1683 netdev_info(dev, "CD transition\n");
1da177e4
LT		 1684 if (!(state &= ~Cd)) /* DEBUG */
1685 goto try;
1686 }
1687 } else { /* ! SccEvt */
1688 if (state & Hi) {
1689#ifdef DSCC4_POLLING
1690 while (!dscc4_tx_poll(dpriv, dev));
1691#endif
09a1732b 1692 netdev_info(dev, "Tx Hi\n");
1da177e4
LT		 1693 state &= ~Hi;
1694 }
1695 if (state & Err) {
09a1732b 1696 netdev_info(dev, "Tx ERR\n");
198191c4 1697 dev->stats.tx_errors++;
1da177e4
LT		 1698 state &= ~Err;
1699 }
1700 }
1701 goto try;
1702}
1703
1704static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1705 struct dscc4_dev_priv *dpriv)
1706{
1707 struct net_device *dev = dscc4_to_dev(dpriv);
1708 u32 state;
1709 int cur;
1710
1711try:
1712 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
409cd63e 1713 state = le32_to_cpu(dpriv->iqrx[cur]);
1da177e4
LT		 1714 if (!state)
1715 return;
1716 dpriv->iqrx[cur] = 0;
1717 dpriv->iqrx_current++;
1718
1719 if (state_check(state, dpriv, dev, "Rx") < 0)
1720 return;
1721
1722 if (!(state & SccEvt)){
1723 struct RxFD *rx_fd;
1724
1725 if (debug > 4)
1726 printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1727 state);
1728 state &= 0x00ffffff;
1729 if (state & Err) { /* Hold or reset */
1730 printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1731 cur = dpriv->rx_current%RX_RING_SIZE;
1732 rx_fd = dpriv->rx_fd + cur;
1733 /*
1734 * Presume we're not facing a DMAC receiver reset.
1735 * As We use the rx size-filtering feature of the
1736 * DSCC4, the beginning of a new frame is waiting in
1737 * the rx fifo. I bet a Receive Data Overflow will
1738 * happen most of time but let's try and avoid it.
1739 * Btw (as for RDO) if one experiences ERR whereas
1740 * the system looks rather idle, there may be a
1741 * problem with latency. In this case, increasing
1742 * RX_RING_SIZE may help.
1743 */
1744 //while (dpriv->rx_needs_refill) {
1745 while (!(rx_fd->state1 & Hold)) {
1746 rx_fd++;
1747 cur++;
1748 if (!(cur = cur%RX_RING_SIZE))
1749 rx_fd = dpriv->rx_fd;
1750 }
1751 //dpriv->rx_needs_refill--;
1752 try_get_rx_skb(dpriv, dev);
1753 if (!rx_fd->data)
1754 goto try;
1755 rx_fd->state1 &= ~Hold;
1756 rx_fd->state2 = 0x00000000;
409cd63e 1757 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 1758 //}
1759 goto try;
1760 }
1761 if (state & Fi) {
1762 dscc4_rx_skb(dpriv, dev);
1763 goto try;
1764 }
1765 if (state & Hi ) { /* HI bit */
09a1732b 1766 netdev_info(dev, "Rx Hi\n");
1da177e4
LT		 1767 state &= ~Hi;
1768 goto try;
1769 }
1770 } else { /* SccEvt */
1771 if (debug > 1) {
1772 //FIXME: verifier la presence de tous les evenements
1773 static struct {
1774 u32 mask;
1775 const char *irq_name;
1776 } evts[] = {
1777 { 0x00008000, "TIN"},
1778 { 0x00000020, "RSC"},
1779 { 0x00000010, "PCE"},
1780 { 0x00000008, "PLLA"},
1781 { 0, NULL}
1782 }, *evt;
1783
1784 for (evt = evts; evt->irq_name; evt++) {
1785 if (state & evt->mask) {
1786 printk(KERN_DEBUG "%s: %s\n",
1787 dev->name, evt->irq_name);
1788 if (!(state &= ~evt->mask))
1789 goto try;
1790 }
1791 }
1792 } else {
1793 if (!(state &= ~0x0000c03c))
1794 goto try;
1795 }
1796 if (state & Cts) {
09a1732b 1797 netdev_info(dev, "CTS transition\n");
1da177e4
LT		 1798 if (!(state &= ~Cts)) /* DEBUG */
1799 goto try;
1800 }
1801 /*
1802 * Receive Data Overflow (FIXME: fscked)
1803 */
1804 if (state & Rdo) {
1805 struct RxFD *rx_fd;
1806 void __iomem *scc_addr;
1807 int cur;
1808
1809 //if (debug)
1810 // dscc4_rx_dump(dpriv);
1811 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1812
1813 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1814 /*
1815 * This has no effect. Why ?
1816 * ORed with TxSccRes, one sees the CFG ack (for
1817 * the TX part only).
1818 */
1819 scc_writel(RxSccRes, dpriv, dev, CMDR);
1820 dpriv->flags |= RdoSet;
1821
1822 /*
1823 * Let's try and save something in the received data.
1824 * rx_current must be incremented at least once to
1825 * avoid HOLD in the BRDA-to-be-pointed desc.
1826 */
1827 do {
1828 cur = dpriv->rx_current++%RX_RING_SIZE;
1829 rx_fd = dpriv->rx_fd + cur;
1830 if (!(rx_fd->state2 & DataComplete))
1831 break;
1832 if (rx_fd->state2 & FrameAborted) {
198191c4 1833 dev->stats.rx_over_errors++;
1da177e4
LT		 1834 rx_fd->state1 |= Hold;
1835 rx_fd->state2 = 0x00000000;
409cd63e 1836 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 1837 } else
1838 dscc4_rx_skb(dpriv, dev);
1839 } while (1);
1840
1841 if (debug > 0) {
1842 if (dpriv->flags & RdoSet)
1843 printk(KERN_DEBUG
1844 "%s: no RDO in Rx data\n", DRV_NAME);
1845 }
1846#ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1847 /*
1848 * FIXME: must the reset be this violent ?
1849 */
1850#warning "FIXME: CH0BRDA"
1851 writel(dpriv->rx_fd_dma +
1852 (dpriv->rx_current%RX_RING_SIZE)*
1853 sizeof(struct RxFD), scc_addr + CH0BRDA);
1854 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1855 if (dscc4_do_action(dev, "RDR") < 0) {
09a1732b 1856 netdev_err(dev, "RDO recovery failed(RDR)\n");
1da177e4
LT		 1857 goto rdo_end;
1858 }
1859 writel(MTFi|Idr, scc_addr + CH0CFG);
1860 if (dscc4_do_action(dev, "IDR") < 0) {
09a1732b 1861 netdev_err(dev, "RDO recovery failed(IDR)\n");
1da177e4
LT		 1862 goto rdo_end;
1863 }
1864 rdo_end:
1865#endif
1866 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1867 goto try;
1868 }
1869 if (state & Cd) {
09a1732b 1870 netdev_info(dev, "CD transition\n");
1da177e4
LT		 1871 if (!(state &= ~Cd)) /* DEBUG */
1872 goto try;
1873 }
1874 if (state & Flex) {
1875 printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1876 if (!(state &= ~Flex))
1877 goto try;
1878 }
1879 }
1880}
1881
1882/*
1883 * I had expected the following to work for the first descriptor
1884 * (tx_fd->state = 0xc0000000)
1885 * - Hold=1 (don't try and branch to the next descripto);
1886 * - No=0 (I want an empty data section, i.e. size=0);
1887 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1888 * It failed and locked solid. Thus the introduction of a dummy skb.
1889 * Problem is acknowledged in errata sheet DS5. Joy :o/
1890 */
7665a089 1891static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1da177e4
LT		 1892{
1893 struct sk_buff *skb;
1894
1895 skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1896 if (skb) {
1897 int last = dpriv->tx_dirty%TX_RING_SIZE;
1898 struct TxFD *tx_fd = dpriv->tx_fd + last;
1899
1900 skb->len = DUMMY_SKB_SIZE;
27d7ff46
ACM		 1901 skb_copy_to_linear_data(skb, version,
1902 strlen(version) % DUMMY_SKB_SIZE);
1da177e4 1903 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
409cd63e
AV		 1904 tx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
1905 skb->data, DUMMY_SKB_SIZE,
1906 PCI_DMA_TODEVICE));
1da177e4
LT		 1907 dpriv->tx_skbuff[last] = skb;
1908 }
1909 return skb;
1910}
1911
1912static int dscc4_init_ring(struct net_device *dev)
1913{
1914 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1915 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1916 struct TxFD *tx_fd;
1917 struct RxFD *rx_fd;
1918 void *ring;
1919 int i;
1920
1921 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1922 if (!ring)
1923 goto err_out;
1924 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1925
1926 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1927 if (!ring)
1928 goto err_free_dma_rx;
1929 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1930
1931 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1932 dpriv->tx_dirty = 0xffffffff;
1933 i = dpriv->tx_current = 0;
1934 do {
1935 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1936 tx_fd->complete = 0x00000000;
1937 /* FIXME: NULL should be ok - to be tried */
409cd63e
AV		 1938 tx_fd->data = cpu_to_le32(dpriv->tx_fd_dma);
1939 (tx_fd++)->next = cpu_to_le32(dpriv->tx_fd_dma +
1da177e4
LT		 1940 (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1941 } while (i < TX_RING_SIZE);
1942
3e710bfa 1943 if (!dscc4_init_dummy_skb(dpriv))
1da177e4
LT		 1944 goto err_free_dma_tx;
1945
1946 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1947 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1948 do {
1949 /* size set by the host. Multiple of 4 bytes please */
1950 rx_fd->state1 = HiDesc;
1951 rx_fd->state2 = 0x00000000;
409cd63e 1952 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 1953 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1954 // FIXME: return value verifiee mais traitement suspect
1955 if (try_get_rx_skb(dpriv, dev) >= 0)
1956 dpriv->rx_dirty++;
409cd63e 1957 (rx_fd++)->next = cpu_to_le32(dpriv->rx_fd_dma +
1da177e4
LT		 1958 (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1959 } while (i < RX_RING_SIZE);
1960
1961 return 0;
1962
1963err_free_dma_tx:
1964 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1965err_free_dma_rx:
1966 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1967err_out:
1968 return -ENOMEM;
1969}
1970
1971static void __devexit dscc4_remove_one(struct pci_dev *pdev)
1972{
1973 struct dscc4_pci_priv *ppriv;
1974 struct dscc4_dev_priv *root;
1975 void __iomem *ioaddr;
1976 int i;
1977
1978 ppriv = pci_get_drvdata(pdev);
1979 root = ppriv->root;
1980
1981 ioaddr = root->base_addr;
1982
1983 dscc4_pci_reset(pdev, ioaddr);
1984
1985 free_irq(pdev->irq, root);
1986 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1987 ppriv->iqcfg_dma);
1988 for (i = 0; i < dev_per_card; i++) {
1989 struct dscc4_dev_priv *dpriv = root + i;
1990
1991 dscc4_release_ring(dpriv);
1992 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1993 dpriv->iqrx, dpriv->iqrx_dma);
1994 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1995 dpriv->iqtx, dpriv->iqtx_dma);
1996 }
1997
1998 dscc4_free1(pdev);
1999
2000 iounmap(ioaddr);
2001
2002 pci_release_region(pdev, 1);
2003 pci_release_region(pdev, 0);
2004
2005 pci_disable_device(pdev);
2006}
2007
2008static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2009 unsigned short parity)
2010{
2011 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2012
2013 if (encoding != ENCODING_NRZ &&
2014 encoding != ENCODING_NRZI &&
2015 encoding != ENCODING_FM_MARK &&
2016 encoding != ENCODING_FM_SPACE &&
2017 encoding != ENCODING_MANCHESTER)
2018 return -EINVAL;
2019
2020 if (parity != PARITY_NONE &&
2021 parity != PARITY_CRC16_PR0_CCITT &&
2022 parity != PARITY_CRC16_PR1_CCITT &&
2023 parity != PARITY_CRC32_PR0_CCITT &&
2024 parity != PARITY_CRC32_PR1_CCITT)
2025 return -EINVAL;
2026
2027 dpriv->encoding = encoding;
2028 dpriv->parity = parity;
2029 return 0;
2030}
2031
2032#ifndef MODULE
2033static int __init dscc4_setup(char *str)
2034{
2035 int *args[] = { &debug, &quartz, NULL }, **p = args;
2036
2037 while (*p && (get_option(&str, *p) == 2))
2038 p++;
2039 return 1;
2040}
2041
2042__setup("dscc4.setup=", dscc4_setup);
2043#endif
2044
a3aa1884 2045static DEFINE_PCI_DEVICE_TABLE(dscc4_pci_tbl) = {
1da177e4
LT		 2046 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2047 PCI_ANY_ID, PCI_ANY_ID, },
2048 { 0,}
2049};
2050MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2051
2052static struct pci_driver dscc4_driver = {
2053 .name = DRV_NAME,
2054 .id_table = dscc4_pci_tbl,
2055 .probe = dscc4_init_one,
2056 .remove = __devexit_p(dscc4_remove_one),
2057};
2058
2059static int __init dscc4_init_module(void)
2060{
29917620 2061 return pci_register_driver(&dscc4_driver);
1da177e4
LT		 2062}
2063
2064static void __exit dscc4_cleanup_module(void)
2065{
2066 pci_unregister_driver(&dscc4_driver);
2067}
2068
2069module_init(dscc4_init_module);
2070module_exit(dscc4_cleanup_module);
Linux 6.x block layer and io_uring tree(s)