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vmxnet3: Enable HW Rx VLAN stripping by default
[linux-2.6-block.git] / drivers / net / vmxnet3 / vmxnet3_drv.c
CommitLineData
d1a890fa
SB		 1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
24 *
25 */
26
b038b040
SR		 27#include <net/ip6_checksum.h>
28
d1a890fa
SB		 29#include "vmxnet3_int.h"
30
31char vmxnet3_driver_name[] = "vmxnet3";
32#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
33
d1a890fa
SB		 34/*
35 * PCI Device ID Table
36 * Last entry must be all 0s
37 */
a3aa1884 38static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = {
d1a890fa
SB		 39 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
40 {0}
41};
42
43MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
44
45static atomic_t devices_found;
46
09c5088e
SB		 47#define VMXNET3_MAX_DEVICES 10
48static int enable_mq = 1;
49static int irq_share_mode;
d1a890fa 50
f9f25026
SB		 51static void
52vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
53
d1a890fa
SB		 54/*
55 * Enable/Disable the given intr
56 */
57static void
58vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
59{
60 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
61}
62
63
64static void
65vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
66{
67 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
68}
69
70
71/*
72 * Enable/Disable all intrs used by the device
73 */
74static void
75vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
76{
77 int i;
78
79 for (i = 0; i < adapter->intr.num_intrs; i++)
80 vmxnet3_enable_intr(adapter, i);
6929fe8a
RZ		 81 adapter->shared->devRead.intrConf.intrCtrl &=
82 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 83}
84
85
86static void
87vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
88{
89 int i;
90
6929fe8a
RZ		 91 adapter->shared->devRead.intrConf.intrCtrl |=
92 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 93 for (i = 0; i < adapter->intr.num_intrs; i++)
94 vmxnet3_disable_intr(adapter, i);
95}
96
97
98static void
99vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
100{
101 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
102}
103
104
105static bool
106vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
107{
09c5088e 108 return tq->stopped;
d1a890fa
SB		 109}
110
111
112static void
113vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
114{
115 tq->stopped = false;
09c5088e 116 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
d1a890fa
SB		 117}
118
119
120static void
121vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
122{
123 tq->stopped = false;
09c5088e 124 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 125}
126
127
128static void
129vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
130{
131 tq->stopped = true;
132 tq->num_stop++;
09c5088e 133 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 134}
135
136
137/*
138 * Check the link state. This may start or stop the tx queue.
139 */
140static void
4a1745fc 141vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
d1a890fa
SB		 142{
143 u32 ret;
09c5088e 144 int i;
d1a890fa
SB		 145
146 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
147 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
148 adapter->link_speed = ret >> 16;
149 if (ret & 1) { /* Link is up. */
150 printk(KERN_INFO "%s: NIC Link is Up %d Mbps\n",
151 adapter->netdev->name, adapter->link_speed);
152 if (!netif_carrier_ok(adapter->netdev))
153 netif_carrier_on(adapter->netdev);
154
09c5088e
SB		 155 if (affectTxQueue) {
156 for (i = 0; i < adapter->num_tx_queues; i++)
157 vmxnet3_tq_start(&adapter->tx_queue[i],
158 adapter);
159 }
d1a890fa
SB		 160 } else {
161 printk(KERN_INFO "%s: NIC Link is Down\n",
162 adapter->netdev->name);
163 if (netif_carrier_ok(adapter->netdev))
164 netif_carrier_off(adapter->netdev);
165
09c5088e
SB		 166 if (affectTxQueue) {
167 for (i = 0; i < adapter->num_tx_queues; i++)
168 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
169 }
d1a890fa
SB		 170 }
171}
172
d1a890fa
SB		 173static void
174vmxnet3_process_events(struct vmxnet3_adapter *adapter)
175{
09c5088e 176 int i;
115924b6 177 u32 events = le32_to_cpu(adapter->shared->ecr);
d1a890fa
SB		 178 if (!events)
179 return;
180
181 vmxnet3_ack_events(adapter, events);
182
183 /* Check if link state has changed */
184 if (events & VMXNET3_ECR_LINK)
4a1745fc 185 vmxnet3_check_link(adapter, true);
d1a890fa
SB		 186
187 /* Check if there is an error on xmit/recv queues */
188 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
189 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
190 VMXNET3_CMD_GET_QUEUE_STATUS);
191
09c5088e
SB		 192 for (i = 0; i < adapter->num_tx_queues; i++)
193 if (adapter->tqd_start[i].status.stopped)
194 dev_err(&adapter->netdev->dev,
195 "%s: tq[%d] error 0x%x\n",
196 adapter->netdev->name, i, le32_to_cpu(
197 adapter->tqd_start[i].status.error));
198 for (i = 0; i < adapter->num_rx_queues; i++)
199 if (adapter->rqd_start[i].status.stopped)
200 dev_err(&adapter->netdev->dev,
201 "%s: rq[%d] error 0x%x\n",
202 adapter->netdev->name, i,
203 adapter->rqd_start[i].status.error);
d1a890fa
SB		 204
205 schedule_work(&adapter->work);
206 }
207}
208
115924b6
SB		 209#ifdef __BIG_ENDIAN_BITFIELD
210/*
211 * The device expects the bitfields in shared structures to be written in
212 * little endian. When CPU is big endian, the following routines are used to
213 * correctly read and write into ABI.
214 * The general technique used here is : double word bitfields are defined in
215 * opposite order for big endian architecture. Then before reading them in
216 * driver the complete double word is translated using le32_to_cpu. Similarly
217 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
218 * double words into required format.
219 * In order to avoid touching bits in shared structure more than once, temporary
220 * descriptors are used. These are passed as srcDesc to following functions.
221 */
222static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
223 struct Vmxnet3_RxDesc *dstDesc)
224{
225 u32 *src = (u32 *)srcDesc + 2;
226 u32 *dst = (u32 *)dstDesc + 2;
227 dstDesc->addr = le64_to_cpu(srcDesc->addr);
228 *dst = le32_to_cpu(*src);
229 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
230}
231
232static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
233 struct Vmxnet3_TxDesc *dstDesc)
234{
235 int i;
236 u32 *src = (u32 *)(srcDesc + 1);
237 u32 *dst = (u32 *)(dstDesc + 1);
238
239 /* Working backwards so that the gen bit is set at the end. */
240 for (i = 2; i > 0; i--) {
241 src--;
242 dst--;
243 *dst = cpu_to_le32(*src);
244 }
245}
246
247
248static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
249 struct Vmxnet3_RxCompDesc *dstDesc)
250{
251 int i = 0;
252 u32 *src = (u32 *)srcDesc;
253 u32 *dst = (u32 *)dstDesc;
254 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
255 *dst = le32_to_cpu(*src);
256 src++;
257 dst++;
258 }
259}
260
261
262/* Used to read bitfield values from double words. */
263static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
264{
265 u32 temp = le32_to_cpu(*bitfield);
266 u32 mask = ((1 << size) - 1) << pos;
267 temp &= mask;
268 temp >>= pos;
269 return temp;
270}
271
272
273
274#endif /* __BIG_ENDIAN_BITFIELD */
275
276#ifdef __BIG_ENDIAN_BITFIELD
277
278# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
279 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
280 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
281# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
282 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
283 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
284# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
285 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
286 VMXNET3_TCD_GEN_SIZE)
287# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
288 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
289# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
290 (dstrcd) = (tmp); \
291 vmxnet3_RxCompToCPU((rcd), (tmp)); \
292 } while (0)
293# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
294 (dstrxd) = (tmp); \
295 vmxnet3_RxDescToCPU((rxd), (tmp)); \
296 } while (0)
297
298#else
299
300# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
301# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
302# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
303# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
304# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
305# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
306
307#endif /* __BIG_ENDIAN_BITFIELD */
308
d1a890fa
SB		 309
310static void
311vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
312 struct pci_dev *pdev)
313{
314 if (tbi->map_type == VMXNET3_MAP_SINGLE)
315 pci_unmap_single(pdev, tbi->dma_addr, tbi->len,
316 PCI_DMA_TODEVICE);
317 else if (tbi->map_type == VMXNET3_MAP_PAGE)
318 pci_unmap_page(pdev, tbi->dma_addr, tbi->len,
319 PCI_DMA_TODEVICE);
320 else
321 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
322
323 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
324}
325
326
327static int
328vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
329 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
330{
331 struct sk_buff *skb;
332 int entries = 0;
333
334 /* no out of order completion */
335 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
115924b6 336 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
d1a890fa
SB		 337
338 skb = tq->buf_info[eop_idx].skb;
339 BUG_ON(skb == NULL);
340 tq->buf_info[eop_idx].skb = NULL;
341
342 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
343
344 while (tq->tx_ring.next2comp != eop_idx) {
345 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
346 pdev);
347
348 /* update next2comp w/o tx_lock. Since we are marking more,
349 * instead of less, tx ring entries avail, the worst case is
350 * that the tx routine incorrectly re-queues a pkt due to
351 * insufficient tx ring entries.
352 */
353 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
354 entries++;
355 }
356
357 dev_kfree_skb_any(skb);
358 return entries;
359}
360
361
362static int
363vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
364 struct vmxnet3_adapter *adapter)
365{
366 int completed = 0;
367 union Vmxnet3_GenericDesc *gdesc;
368
369 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
115924b6
SB		 370 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
371 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
372 &gdesc->tcd), tq, adapter->pdev,
373 adapter);
d1a890fa
SB		 374
375 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
376 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
377 }
378
379 if (completed) {
380 spin_lock(&tq->tx_lock);
381 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
382 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
383 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
384 netif_carrier_ok(adapter->netdev))) {
385 vmxnet3_tq_wake(tq, adapter);
386 }
387 spin_unlock(&tq->tx_lock);
388 }
389 return completed;
390}
391
392
393static void
394vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
395 struct vmxnet3_adapter *adapter)
396{
397 int i;
398
399 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
400 struct vmxnet3_tx_buf_info *tbi;
401 union Vmxnet3_GenericDesc *gdesc;
402
403 tbi = tq->buf_info + tq->tx_ring.next2comp;
404 gdesc = tq->tx_ring.base + tq->tx_ring.next2comp;
405
406 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
407 if (tbi->skb) {
408 dev_kfree_skb_any(tbi->skb);
409 tbi->skb = NULL;
410 }
411 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
412 }
413
414 /* sanity check, verify all buffers are indeed unmapped and freed */
415 for (i = 0; i < tq->tx_ring.size; i++) {
416 BUG_ON(tq->buf_info[i].skb != NULL ||
417 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
418 }
419
420 tq->tx_ring.gen = VMXNET3_INIT_GEN;
421 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
422
423 tq->comp_ring.gen = VMXNET3_INIT_GEN;
424 tq->comp_ring.next2proc = 0;
425}
426
427
09c5088e 428static void
d1a890fa
SB		 429vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
430 struct vmxnet3_adapter *adapter)
431{
432 if (tq->tx_ring.base) {
433 pci_free_consistent(adapter->pdev, tq->tx_ring.size *
434 sizeof(struct Vmxnet3_TxDesc),
435 tq->tx_ring.base, tq->tx_ring.basePA);
436 tq->tx_ring.base = NULL;
437 }
438 if (tq->data_ring.base) {
439 pci_free_consistent(adapter->pdev, tq->data_ring.size *
440 sizeof(struct Vmxnet3_TxDataDesc),
441 tq->data_ring.base, tq->data_ring.basePA);
442 tq->data_ring.base = NULL;
443 }
444 if (tq->comp_ring.base) {
445 pci_free_consistent(adapter->pdev, tq->comp_ring.size *
446 sizeof(struct Vmxnet3_TxCompDesc),
447 tq->comp_ring.base, tq->comp_ring.basePA);
448 tq->comp_ring.base = NULL;
449 }
450 kfree(tq->buf_info);
451 tq->buf_info = NULL;
452}
453
454
09c5088e
SB		 455/* Destroy all tx queues */
456void
457vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
458{
459 int i;
460
461 for (i = 0; i < adapter->num_tx_queues; i++)
462 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
463}
464
465
d1a890fa
SB		 466static void
467vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
468 struct vmxnet3_adapter *adapter)
469{
470 int i;
471
472 /* reset the tx ring contents to 0 and reset the tx ring states */
473 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
474 sizeof(struct Vmxnet3_TxDesc));
475 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
476 tq->tx_ring.gen = VMXNET3_INIT_GEN;
477
478 memset(tq->data_ring.base, 0, tq->data_ring.size *
479 sizeof(struct Vmxnet3_TxDataDesc));
480
481 /* reset the tx comp ring contents to 0 and reset comp ring states */
482 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
483 sizeof(struct Vmxnet3_TxCompDesc));
484 tq->comp_ring.next2proc = 0;
485 tq->comp_ring.gen = VMXNET3_INIT_GEN;
486
487 /* reset the bookkeeping data */
488 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
489 for (i = 0; i < tq->tx_ring.size; i++)
490 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
491
492 /* stats are not reset */
493}
494
495
496static int
497vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
498 struct vmxnet3_adapter *adapter)
499{
500 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
501 tq->comp_ring.base || tq->buf_info);
502
503 tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size
504 * sizeof(struct Vmxnet3_TxDesc),
505 &tq->tx_ring.basePA);
506 if (!tq->tx_ring.base) {
507 printk(KERN_ERR "%s: failed to allocate tx ring\n",
508 adapter->netdev->name);
509 goto err;
510 }
511
512 tq->data_ring.base = pci_alloc_consistent(adapter->pdev,
513 tq->data_ring.size *
514 sizeof(struct Vmxnet3_TxDataDesc),
515 &tq->data_ring.basePA);
516 if (!tq->data_ring.base) {
517 printk(KERN_ERR "%s: failed to allocate data ring\n",
518 adapter->netdev->name);
519 goto err;
520 }
521
522 tq->comp_ring.base = pci_alloc_consistent(adapter->pdev,
523 tq->comp_ring.size *
524 sizeof(struct Vmxnet3_TxCompDesc),
525 &tq->comp_ring.basePA);
526 if (!tq->comp_ring.base) {
527 printk(KERN_ERR "%s: failed to allocate tx comp ring\n",
528 adapter->netdev->name);
529 goto err;
530 }
531
532 tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]),
533 GFP_KERNEL);
534 if (!tq->buf_info) {
535 printk(KERN_ERR "%s: failed to allocate tx bufinfo\n",
536 adapter->netdev->name);
537 goto err;
538 }
539
540 return 0;
541
542err:
543 vmxnet3_tq_destroy(tq, adapter);
544 return -ENOMEM;
545}
546
09c5088e
SB		 547static void
548vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
549{
550 int i;
551
552 for (i = 0; i < adapter->num_tx_queues; i++)
553 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
554}
d1a890fa
SB		 555
556/*
557 * starting from ring->next2fill, allocate rx buffers for the given ring
558 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
559 * are allocated or allocation fails
560 */
561
562static int
563vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
564 int num_to_alloc, struct vmxnet3_adapter *adapter)
565{
566 int num_allocated = 0;
567 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
568 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
569 u32 val;
570
571 while (num_allocated < num_to_alloc) {
572 struct vmxnet3_rx_buf_info *rbi;
573 union Vmxnet3_GenericDesc *gd;
574
575 rbi = rbi_base + ring->next2fill;
576 gd = ring->base + ring->next2fill;
577
578 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
579 if (rbi->skb == NULL) {
580 rbi->skb = dev_alloc_skb(rbi->len +
581 NET_IP_ALIGN);
582 if (unlikely(rbi->skb == NULL)) {
583 rq->stats.rx_buf_alloc_failure++;
584 break;
585 }
586 rbi->skb->dev = adapter->netdev;
587
588 skb_reserve(rbi->skb, NET_IP_ALIGN);
589 rbi->dma_addr = pci_map_single(adapter->pdev,
590 rbi->skb->data, rbi->len,
591 PCI_DMA_FROMDEVICE);
592 } else {
593 /* rx buffer skipped by the device */
594 }
595 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
596 } else {
597 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
598 rbi->len != PAGE_SIZE);
599
600 if (rbi->page == NULL) {
601 rbi->page = alloc_page(GFP_ATOMIC);
602 if (unlikely(rbi->page == NULL)) {
603 rq->stats.rx_buf_alloc_failure++;
604 break;
605 }
606 rbi->dma_addr = pci_map_page(adapter->pdev,
607 rbi->page, 0, PAGE_SIZE,
608 PCI_DMA_FROMDEVICE);
609 } else {
610 /* rx buffers skipped by the device */
611 }
612 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
613 }
614
615 BUG_ON(rbi->dma_addr == 0);
115924b6
SB		 616 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
617 gd->dword[2] = cpu_to_le32((ring->gen << VMXNET3_RXD_GEN_SHIFT)
618 | val | rbi->len);
d1a890fa
SB		 619
620 num_allocated++;
621 vmxnet3_cmd_ring_adv_next2fill(ring);
622 }
623 rq->uncommitted[ring_idx] += num_allocated;
624
f6965582
RD		 625 dev_dbg(&adapter->netdev->dev,
626 "alloc_rx_buf: %d allocated, next2fill %u, next2comp "
d1a890fa
SB		 627 "%u, uncommited %u\n", num_allocated, ring->next2fill,
628 ring->next2comp, rq->uncommitted[ring_idx]);
629
630 /* so that the device can distinguish a full ring and an empty ring */
631 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
632
633 return num_allocated;
634}
635
636
637static void
638vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
639 struct vmxnet3_rx_buf_info *rbi)
640{
641 struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
642 skb_shinfo(skb)->nr_frags;
643
644 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
645
646 frag->page = rbi->page;
647 frag->page_offset = 0;
648 frag->size = rcd->len;
649 skb->data_len += frag->size;
650 skb_shinfo(skb)->nr_frags++;
651}
652
653
654static void
655vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
656 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
657 struct vmxnet3_adapter *adapter)
658{
659 u32 dw2, len;
660 unsigned long buf_offset;
661 int i;
662 union Vmxnet3_GenericDesc *gdesc;
663 struct vmxnet3_tx_buf_info *tbi = NULL;
664
665 BUG_ON(ctx->copy_size > skb_headlen(skb));
666
667 /* use the previous gen bit for the SOP desc */
668 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
669
670 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
671 gdesc = ctx->sop_txd; /* both loops below can be skipped */
672
673 /* no need to map the buffer if headers are copied */
674 if (ctx->copy_size) {
115924b6 675 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
d1a890fa 676 tq->tx_ring.next2fill *
115924b6
SB		 677 sizeof(struct Vmxnet3_TxDataDesc));
678 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
d1a890fa
SB		 679 ctx->sop_txd->dword[3] = 0;
680
681 tbi = tq->buf_info + tq->tx_ring.next2fill;
682 tbi->map_type = VMXNET3_MAP_NONE;
683
f6965582
RD		 684 dev_dbg(&adapter->netdev->dev,
685 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 686 tq->tx_ring.next2fill,
687 le64_to_cpu(ctx->sop_txd->txd.addr),
d1a890fa
SB		 688 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
689 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
690
691 /* use the right gen for non-SOP desc */
692 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
693 }
694
695 /* linear part can use multiple tx desc if it's big */
696 len = skb_headlen(skb) - ctx->copy_size;
697 buf_offset = ctx->copy_size;
698 while (len) {
699 u32 buf_size;
700
1f4b1612
BD		 701 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
702 buf_size = len;
703 dw2 |= len;
704 } else {
705 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
706 /* spec says that for TxDesc.len, 0 == 2^14 */
707 }
d1a890fa
SB		 708
709 tbi = tq->buf_info + tq->tx_ring.next2fill;
710 tbi->map_type = VMXNET3_MAP_SINGLE;
711 tbi->dma_addr = pci_map_single(adapter->pdev,
712 skb->data + buf_offset, buf_size,
713 PCI_DMA_TODEVICE);
714
1f4b1612 715 tbi->len = buf_size;
d1a890fa
SB		 716
717 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
718 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
719
115924b6 720 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
1f4b1612 721 gdesc->dword[2] = cpu_to_le32(dw2);
d1a890fa
SB		 722 gdesc->dword[3] = 0;
723
f6965582
RD		 724 dev_dbg(&adapter->netdev->dev,
725 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 726 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
727 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
d1a890fa
SB		 728 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
729 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
730
731 len -= buf_size;
732 buf_offset += buf_size;
733 }
734
735 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
736 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
737
738 tbi = tq->buf_info + tq->tx_ring.next2fill;
739 tbi->map_type = VMXNET3_MAP_PAGE;
740 tbi->dma_addr = pci_map_page(adapter->pdev, frag->page,
741 frag->page_offset, frag->size,
742 PCI_DMA_TODEVICE);
743
744 tbi->len = frag->size;
745
746 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
747 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
748
115924b6
SB		 749 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
750 gdesc->dword[2] = cpu_to_le32(dw2 | frag->size);
d1a890fa
SB		 751 gdesc->dword[3] = 0;
752
f6965582
RD		 753 dev_dbg(&adapter->netdev->dev,
754 "txd[%u]: 0x%llu %u %u\n",
115924b6
SB		 755 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
756 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
d1a890fa
SB		 757 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
758 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
759 }
760
761 ctx->eop_txd = gdesc;
762
763 /* set the last buf_info for the pkt */
764 tbi->skb = skb;
765 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
766}
767
768
09c5088e
SB		 769/* Init all tx queues */
770static void
771vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
772{
773 int i;
774
775 for (i = 0; i < adapter->num_tx_queues; i++)
776 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
777}
778
779
d1a890fa
SB		 780/*
781 * parse and copy relevant protocol headers:
782 * For a tso pkt, relevant headers are L2/3/4 including options
783 * For a pkt requesting csum offloading, they are L2/3 and may include L4
784 * if it's a TCP/UDP pkt
785 *
786 * Returns:
787 * -1: error happens during parsing
788 * 0: protocol headers parsed, but too big to be copied
789 * 1: protocol headers parsed and copied
790 *
791 * Other effects:
792 * 1. related *ctx fields are updated.
793 * 2. ctx->copy_size is # of bytes copied
794 * 3. the portion copied is guaranteed to be in the linear part
795 *
796 */
797static int
798vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
799 struct vmxnet3_tx_ctx *ctx,
800 struct vmxnet3_adapter *adapter)
801{
802 struct Vmxnet3_TxDataDesc *tdd;
803
0d0b1672 804 if (ctx->mss) { /* TSO */
d1a890fa
SB		 805 ctx->eth_ip_hdr_size = skb_transport_offset(skb);
806 ctx->l4_hdr_size = ((struct tcphdr *)
807 skb_transport_header(skb))->doff * 4;
808 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
809 } else {
810 unsigned int pull_size;
811
812 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 813 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
d1a890fa
SB		 814
815 if (ctx->ipv4) {
816 struct iphdr *iph = (struct iphdr *)
817 skb_network_header(skb);
818 if (iph->protocol == IPPROTO_TCP) {
819 pull_size = ctx->eth_ip_hdr_size +
820 sizeof(struct tcphdr);
821
822 if (unlikely(!pskb_may_pull(skb,
823 pull_size))) {
824 goto err;
825 }
826 ctx->l4_hdr_size = ((struct tcphdr *)
827 skb_transport_header(skb))->doff * 4;
828 } else if (iph->protocol == IPPROTO_UDP) {
829 ctx->l4_hdr_size =
830 sizeof(struct udphdr);
831 } else {
832 ctx->l4_hdr_size = 0;
833 }
834 } else {
835 /* for simplicity, don't copy L4 headers */
836 ctx->l4_hdr_size = 0;
837 }
838 ctx->copy_size = ctx->eth_ip_hdr_size +
839 ctx->l4_hdr_size;
840 } else {
841 ctx->eth_ip_hdr_size = 0;
842 ctx->l4_hdr_size = 0;
843 /* copy as much as allowed */
844 ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE
845 , skb_headlen(skb));
846 }
847
848 /* make sure headers are accessible directly */
849 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
850 goto err;
851 }
852
853 if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) {
854 tq->stats.oversized_hdr++;
855 ctx->copy_size = 0;
856 return 0;
857 }
858
859 tdd = tq->data_ring.base + tq->tx_ring.next2fill;
860
861 memcpy(tdd->data, skb->data, ctx->copy_size);
f6965582
RD		 862 dev_dbg(&adapter->netdev->dev,
863 "copy %u bytes to dataRing[%u]\n",
d1a890fa
SB		 864 ctx->copy_size, tq->tx_ring.next2fill);
865 return 1;
866
867err:
868 return -1;
869}
870
871
872static void
873vmxnet3_prepare_tso(struct sk_buff *skb,
874 struct vmxnet3_tx_ctx *ctx)
875{
876 struct tcphdr *tcph = (struct tcphdr *)skb_transport_header(skb);
877 if (ctx->ipv4) {
878 struct iphdr *iph = (struct iphdr *)skb_network_header(skb);
879 iph->check = 0;
880 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
881 IPPROTO_TCP, 0);
882 } else {
883 struct ipv6hdr *iph = (struct ipv6hdr *)skb_network_header(skb);
884 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
885 IPPROTO_TCP, 0);
886 }
887}
888
889
890/*
891 * Transmits a pkt thru a given tq
892 * Returns:
893 * NETDEV_TX_OK: descriptors are setup successfully
894 * NETDEV_TX_OK: error occured, the pkt is dropped
895 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
896 *
897 * Side-effects:
898 * 1. tx ring may be changed
899 * 2. tq stats may be updated accordingly
900 * 3. shared->txNumDeferred may be updated
901 */
902
903static int
904vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
905 struct vmxnet3_adapter *adapter, struct net_device *netdev)
906{
907 int ret;
908 u32 count;
909 unsigned long flags;
910 struct vmxnet3_tx_ctx ctx;
911 union Vmxnet3_GenericDesc *gdesc;
115924b6
SB		 912#ifdef __BIG_ENDIAN_BITFIELD
913 /* Use temporary descriptor to avoid touching bits multiple times */
914 union Vmxnet3_GenericDesc tempTxDesc;
915#endif
d1a890fa
SB		 916
917 /* conservatively estimate # of descriptors to use */
918 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) +
919 skb_shinfo(skb)->nr_frags + 1;
920
1b803fbf 921 ctx.ipv4 = (skb->protocol == cpu_to_be16(ETH_P_IP));
d1a890fa
SB		 922
923 ctx.mss = skb_shinfo(skb)->gso_size;
924 if (ctx.mss) {
925 if (skb_header_cloned(skb)) {
926 if (unlikely(pskb_expand_head(skb, 0, 0,
927 GFP_ATOMIC) != 0)) {
928 tq->stats.drop_tso++;
929 goto drop_pkt;
930 }
931 tq->stats.copy_skb_header++;
932 }
933 vmxnet3_prepare_tso(skb, &ctx);
934 } else {
935 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
936
937 /* non-tso pkts must not use more than
938 * VMXNET3_MAX_TXD_PER_PKT entries
939 */
940 if (skb_linearize(skb) != 0) {
941 tq->stats.drop_too_many_frags++;
942 goto drop_pkt;
943 }
944 tq->stats.linearized++;
945
946 /* recalculate the # of descriptors to use */
947 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
948 }
949 }
950
09c5088e
SB		 951 spin_lock_irqsave(&tq->tx_lock, flags);
952
953 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
954 tq->stats.tx_ring_full++;
955 dev_dbg(&adapter->netdev->dev,
956 "tx queue stopped on %s, next2comp %u"
957 " next2fill %u\n", adapter->netdev->name,
958 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
959
960 vmxnet3_tq_stop(tq, adapter);
961 spin_unlock_irqrestore(&tq->tx_lock, flags);
962 return NETDEV_TX_BUSY;
963 }
964
965
d1a890fa
SB		 966 ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter);
967 if (ret >= 0) {
968 BUG_ON(ret <= 0 && ctx.copy_size != 0);
969 /* hdrs parsed, check against other limits */
970 if (ctx.mss) {
971 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
972 VMXNET3_MAX_TX_BUF_SIZE)) {
973 goto hdr_too_big;
974 }
975 } else {
976 if (skb->ip_summed == CHECKSUM_PARTIAL) {
977 if (unlikely(ctx.eth_ip_hdr_size +
978 skb->csum_offset >
979 VMXNET3_MAX_CSUM_OFFSET)) {
980 goto hdr_too_big;
981 }
982 }
983 }
984 } else {
985 tq->stats.drop_hdr_inspect_err++;
f955e141 986 goto unlock_drop_pkt;
d1a890fa
SB		 987 }
988
d1a890fa
SB		 989 /* fill tx descs related to addr & len */
990 vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter);
991
992 /* setup the EOP desc */
115924b6 993 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
d1a890fa
SB		 994
995 /* setup the SOP desc */
115924b6
SB		 996#ifdef __BIG_ENDIAN_BITFIELD
997 gdesc = &tempTxDesc;
998 gdesc->dword[2] = ctx.sop_txd->dword[2];
999 gdesc->dword[3] = ctx.sop_txd->dword[3];
1000#else
d1a890fa 1001 gdesc = ctx.sop_txd;
115924b6 1002#endif
d1a890fa
SB		 1003 if (ctx.mss) {
1004 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
1005 gdesc->txd.om = VMXNET3_OM_TSO;
1006 gdesc->txd.msscof = ctx.mss;
115924b6
SB		 1007 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
1008 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
d1a890fa
SB		 1009 } else {
1010 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1011 gdesc->txd.hlen = ctx.eth_ip_hdr_size;
1012 gdesc->txd.om = VMXNET3_OM_CSUM;
1013 gdesc->txd.msscof = ctx.eth_ip_hdr_size +
1014 skb->csum_offset;
1015 } else {
1016 gdesc->txd.om = 0;
1017 gdesc->txd.msscof = 0;
1018 }
115924b6 1019 le32_add_cpu(&tq->shared->txNumDeferred, 1);
d1a890fa
SB		 1020 }
1021
1022 if (vlan_tx_tag_present(skb)) {
1023 gdesc->txd.ti = 1;
1024 gdesc->txd.tci = vlan_tx_tag_get(skb);
1025 }
1026
115924b6
SB		 1027 /* finally flips the GEN bit of the SOP desc. */
1028 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1029 VMXNET3_TXD_GEN);
1030#ifdef __BIG_ENDIAN_BITFIELD
1031 /* Finished updating in bitfields of Tx Desc, so write them in original
1032 * place.
1033 */
1034 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1035 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1036 gdesc = ctx.sop_txd;
1037#endif
f6965582
RD		 1038 dev_dbg(&adapter->netdev->dev,
1039 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
d1a890fa 1040 (u32)((union Vmxnet3_GenericDesc *)ctx.sop_txd -
115924b6
SB		 1041 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1042 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
d1a890fa
SB		 1043
1044 spin_unlock_irqrestore(&tq->tx_lock, flags);
1045
115924b6
SB		 1046 if (le32_to_cpu(tq->shared->txNumDeferred) >=
1047 le32_to_cpu(tq->shared->txThreshold)) {
d1a890fa 1048 tq->shared->txNumDeferred = 0;
09c5088e
SB		 1049 VMXNET3_WRITE_BAR0_REG(adapter,
1050 VMXNET3_REG_TXPROD + tq->qid * 8,
d1a890fa
SB		 1051 tq->tx_ring.next2fill);
1052 }
d1a890fa
SB		 1053
1054 return NETDEV_TX_OK;
1055
1056hdr_too_big:
1057 tq->stats.drop_oversized_hdr++;
f955e141
DC		 1058unlock_drop_pkt:
1059 spin_unlock_irqrestore(&tq->tx_lock, flags);
d1a890fa
SB		 1060drop_pkt:
1061 tq->stats.drop_total++;
1062 dev_kfree_skb(skb);
1063 return NETDEV_TX_OK;
1064}
1065
1066
1067static netdev_tx_t
1068vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1069{
1070 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1071
09c5088e
SB		 1072 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1073 return vmxnet3_tq_xmit(skb,
1074 &adapter->tx_queue[skb->queue_mapping],
1075 adapter, netdev);
d1a890fa
SB		 1076}
1077
1078
1079static void
1080vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1081 struct sk_buff *skb,
1082 union Vmxnet3_GenericDesc *gdesc)
1083{
1084 if (!gdesc->rcd.cnc && adapter->rxcsum) {
1085 /* typical case: TCP/UDP over IP and both csums are correct */
115924b6 1086 if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) ==
d1a890fa
SB		 1087 VMXNET3_RCD_CSUM_OK) {
1088 skb->ip_summed = CHECKSUM_UNNECESSARY;
1089 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
1090 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
1091 BUG_ON(gdesc->rcd.frg);
1092 } else {
1093 if (gdesc->rcd.csum) {
1094 skb->csum = htons(gdesc->rcd.csum);
1095 skb->ip_summed = CHECKSUM_PARTIAL;
1096 } else {
bc8acf2c 1097 skb_checksum_none_assert(skb);
d1a890fa
SB		 1098 }
1099 }
1100 } else {
bc8acf2c 1101 skb_checksum_none_assert(skb);
d1a890fa
SB		 1102 }
1103}
1104
1105
1106static void
1107vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1108 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1109{
1110 rq->stats.drop_err++;
1111 if (!rcd->fcs)
1112 rq->stats.drop_fcs++;
1113
1114 rq->stats.drop_total++;
1115
1116 /*
1117 * We do not unmap and chain the rx buffer to the skb.
1118 * We basically pretend this buffer is not used and will be recycled
1119 * by vmxnet3_rq_alloc_rx_buf()
1120 */
1121
1122 /*
1123 * ctx->skb may be NULL if this is the first and the only one
1124 * desc for the pkt
1125 */
1126 if (ctx->skb)
1127 dev_kfree_skb_irq(ctx->skb);
1128
1129 ctx->skb = NULL;
1130}
1131
1132
1133static int
1134vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1135 struct vmxnet3_adapter *adapter, int quota)
1136{
215faf9c
JP		 1137 static const u32 rxprod_reg[2] = {
1138 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1139 };
d1a890fa
SB		 1140 u32 num_rxd = 0;
1141 struct Vmxnet3_RxCompDesc *rcd;
1142 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
115924b6
SB		 1143#ifdef __BIG_ENDIAN_BITFIELD
1144 struct Vmxnet3_RxDesc rxCmdDesc;
1145 struct Vmxnet3_RxCompDesc rxComp;
1146#endif
1147 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1148 &rxComp);
d1a890fa
SB		 1149 while (rcd->gen == rq->comp_ring.gen) {
1150 struct vmxnet3_rx_buf_info *rbi;
1151 struct sk_buff *skb;
1152 int num_to_alloc;
1153 struct Vmxnet3_RxDesc *rxd;
1154 u32 idx, ring_idx;
1155
1156 if (num_rxd >= quota) {
1157 /* we may stop even before we see the EOP desc of
1158 * the current pkt
1159 */
1160 break;
1161 }
1162 num_rxd++;
09c5088e 1163 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2);
d1a890fa 1164 idx = rcd->rxdIdx;
09c5088e 1165 ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1;
115924b6
SB		 1166 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1167 &rxCmdDesc);
d1a890fa
SB		 1168 rbi = rq->buf_info[ring_idx] + idx;
1169
115924b6
SB		 1170 BUG_ON(rxd->addr != rbi->dma_addr ||
1171 rxd->len != rbi->len);
d1a890fa
SB		 1172
1173 if (unlikely(rcd->eop && rcd->err)) {
1174 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1175 goto rcd_done;
1176 }
1177
1178 if (rcd->sop) { /* first buf of the pkt */
1179 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1180 rcd->rqID != rq->qid);
1181
1182 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1183 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1184
1185 if (unlikely(rcd->len == 0)) {
1186 /* Pretend the rx buffer is skipped. */
1187 BUG_ON(!(rcd->sop && rcd->eop));
f6965582
RD		 1188 dev_dbg(&adapter->netdev->dev,
1189 "rxRing[%u][%u] 0 length\n",
d1a890fa
SB		 1190 ring_idx, idx);
1191 goto rcd_done;
1192 }
1193
1194 ctx->skb = rbi->skb;
1195 rbi->skb = NULL;
1196
1197 pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len,
1198 PCI_DMA_FROMDEVICE);
1199
1200 skb_put(ctx->skb, rcd->len);
1201 } else {
1202 BUG_ON(ctx->skb == NULL);
1203 /* non SOP buffer must be type 1 in most cases */
1204 if (rbi->buf_type == VMXNET3_RX_BUF_PAGE) {
1205 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
1206
1207 if (rcd->len) {
1208 pci_unmap_page(adapter->pdev,
1209 rbi->dma_addr, rbi->len,
1210 PCI_DMA_FROMDEVICE);
1211
1212 vmxnet3_append_frag(ctx->skb, rcd, rbi);
1213 rbi->page = NULL;
1214 }
1215 } else {
1216 /*
1217 * The only time a non-SOP buffer is type 0 is
1218 * when it's EOP and error flag is raised, which
1219 * has already been handled.
1220 */
1221 BUG_ON(true);
1222 }
1223 }
1224
1225 skb = ctx->skb;
1226 if (rcd->eop) {
1227 skb->len += skb->data_len;
1228 skb->truesize += skb->data_len;
1229
1230 vmxnet3_rx_csum(adapter, skb,
1231 (union Vmxnet3_GenericDesc *)rcd);
1232 skb->protocol = eth_type_trans(skb, adapter->netdev);
1233
1234 if (unlikely(adapter->vlan_grp && rcd->ts)) {
1235 vlan_hwaccel_receive_skb(skb,
1236 adapter->vlan_grp, rcd->tci);
1237 } else {
1238 netif_receive_skb(skb);
1239 }
1240
d1a890fa
SB		 1241 ctx->skb = NULL;
1242 }
1243
1244rcd_done:
1245 /* device may skip some rx descs */
1246 rq->rx_ring[ring_idx].next2comp = idx;
1247 VMXNET3_INC_RING_IDX_ONLY(rq->rx_ring[ring_idx].next2comp,
1248 rq->rx_ring[ring_idx].size);
1249
1250 /* refill rx buffers frequently to avoid starving the h/w */
1251 num_to_alloc = vmxnet3_cmd_ring_desc_avail(rq->rx_ring +
1252 ring_idx);
1253 if (unlikely(num_to_alloc > VMXNET3_RX_ALLOC_THRESHOLD(rq,
1254 ring_idx, adapter))) {
1255 vmxnet3_rq_alloc_rx_buf(rq, ring_idx, num_to_alloc,
1256 adapter);
1257
1258 /* if needed, update the register */
1259 if (unlikely(rq->shared->updateRxProd)) {
1260 VMXNET3_WRITE_BAR0_REG(adapter,
1261 rxprod_reg[ring_idx] + rq->qid * 8,
1262 rq->rx_ring[ring_idx].next2fill);
1263 rq->uncommitted[ring_idx] = 0;
1264 }
1265 }
1266
1267 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
115924b6
SB		 1268 vmxnet3_getRxComp(rcd,
1269 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
d1a890fa
SB		 1270 }
1271
1272 return num_rxd;
1273}
1274
1275
1276static void
1277vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1278 struct vmxnet3_adapter *adapter)
1279{
1280 u32 i, ring_idx;
1281 struct Vmxnet3_RxDesc *rxd;
1282
1283 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1284 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
115924b6
SB		 1285#ifdef __BIG_ENDIAN_BITFIELD
1286 struct Vmxnet3_RxDesc rxDesc;
1287#endif
1288 vmxnet3_getRxDesc(rxd,
1289 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
d1a890fa
SB		 1290
1291 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1292 rq->buf_info[ring_idx][i].skb) {
1293 pci_unmap_single(adapter->pdev, rxd->addr,
1294 rxd->len, PCI_DMA_FROMDEVICE);
1295 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1296 rq->buf_info[ring_idx][i].skb = NULL;
1297 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1298 rq->buf_info[ring_idx][i].page) {
1299 pci_unmap_page(adapter->pdev, rxd->addr,
1300 rxd->len, PCI_DMA_FROMDEVICE);
1301 put_page(rq->buf_info[ring_idx][i].page);
1302 rq->buf_info[ring_idx][i].page = NULL;
1303 }
1304 }
1305
1306 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1307 rq->rx_ring[ring_idx].next2fill =
1308 rq->rx_ring[ring_idx].next2comp = 0;
1309 rq->uncommitted[ring_idx] = 0;
1310 }
1311
1312 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1313 rq->comp_ring.next2proc = 0;
1314}
1315
1316
09c5088e
SB		 1317static void
1318vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1319{
1320 int i;
1321
1322 for (i = 0; i < adapter->num_rx_queues; i++)
1323 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1324}
1325
1326
d1a890fa
SB		 1327void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1328 struct vmxnet3_adapter *adapter)
1329{
1330 int i;
1331 int j;
1332
1333 /* all rx buffers must have already been freed */
1334 for (i = 0; i < 2; i++) {
1335 if (rq->buf_info[i]) {
1336 for (j = 0; j < rq->rx_ring[i].size; j++)
1337 BUG_ON(rq->buf_info[i][j].page != NULL);
1338 }
1339 }
1340
1341
1342 kfree(rq->buf_info[0]);
1343
1344 for (i = 0; i < 2; i++) {
1345 if (rq->rx_ring[i].base) {
1346 pci_free_consistent(adapter->pdev, rq->rx_ring[i].size
1347 * sizeof(struct Vmxnet3_RxDesc),
1348 rq->rx_ring[i].base,
1349 rq->rx_ring[i].basePA);
1350 rq->rx_ring[i].base = NULL;
1351 }
1352 rq->buf_info[i] = NULL;
1353 }
1354
1355 if (rq->comp_ring.base) {
1356 pci_free_consistent(adapter->pdev, rq->comp_ring.size *
1357 sizeof(struct Vmxnet3_RxCompDesc),
1358 rq->comp_ring.base, rq->comp_ring.basePA);
1359 rq->comp_ring.base = NULL;
1360 }
1361}
1362
1363
1364static int
1365vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1366 struct vmxnet3_adapter *adapter)
1367{
1368 int i;
1369
1370 /* initialize buf_info */
1371 for (i = 0; i < rq->rx_ring[0].size; i++) {
1372
1373 /* 1st buf for a pkt is skbuff */
1374 if (i % adapter->rx_buf_per_pkt == 0) {
1375 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1376 rq->buf_info[0][i].len = adapter->skb_buf_size;
1377 } else { /* subsequent bufs for a pkt is frag */
1378 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1379 rq->buf_info[0][i].len = PAGE_SIZE;
1380 }
1381 }
1382 for (i = 0; i < rq->rx_ring[1].size; i++) {
1383 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1384 rq->buf_info[1][i].len = PAGE_SIZE;
1385 }
1386
1387 /* reset internal state and allocate buffers for both rings */
1388 for (i = 0; i < 2; i++) {
1389 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
1390 rq->uncommitted[i] = 0;
1391
1392 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1393 sizeof(struct Vmxnet3_RxDesc));
1394 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1395 }
1396 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1397 adapter) == 0) {
1398 /* at least has 1 rx buffer for the 1st ring */
1399 return -ENOMEM;
1400 }
1401 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1402
1403 /* reset the comp ring */
1404 rq->comp_ring.next2proc = 0;
1405 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1406 sizeof(struct Vmxnet3_RxCompDesc));
1407 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1408
1409 /* reset rxctx */
1410 rq->rx_ctx.skb = NULL;
1411
1412 /* stats are not reset */
1413 return 0;
1414}
1415
1416
09c5088e
SB		 1417static int
1418vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1419{
1420 int i, err = 0;
1421
1422 for (i = 0; i < adapter->num_rx_queues; i++) {
1423 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1424 if (unlikely(err)) {
1425 dev_err(&adapter->netdev->dev, "%s: failed to "
1426 "initialize rx queue%i\n",
1427 adapter->netdev->name, i);
1428 break;
1429 }
1430 }
1431 return err;
1432
1433}
1434
1435
d1a890fa
SB		 1436static int
1437vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1438{
1439 int i;
1440 size_t sz;
1441 struct vmxnet3_rx_buf_info *bi;
1442
1443 for (i = 0; i < 2; i++) {
1444
1445 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1446 rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz,
1447 &rq->rx_ring[i].basePA);
1448 if (!rq->rx_ring[i].base) {
1449 printk(KERN_ERR "%s: failed to allocate rx ring %d\n",
1450 adapter->netdev->name, i);
1451 goto err;
1452 }
1453 }
1454
1455 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1456 rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz,
1457 &rq->comp_ring.basePA);
1458 if (!rq->comp_ring.base) {
1459 printk(KERN_ERR "%s: failed to allocate rx comp ring\n",
1460 adapter->netdev->name);
1461 goto err;
1462 }
1463
1464 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1465 rq->rx_ring[1].size);
476c609e 1466 bi = kzalloc(sz, GFP_KERNEL);
d1a890fa
SB		 1467 if (!bi) {
1468 printk(KERN_ERR "%s: failed to allocate rx bufinfo\n",
1469 adapter->netdev->name);
1470 goto err;
1471 }
d1a890fa
SB		 1472 rq->buf_info[0] = bi;
1473 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1474
1475 return 0;
1476
1477err:
1478 vmxnet3_rq_destroy(rq, adapter);
1479 return -ENOMEM;
1480}
1481
1482
09c5088e
SB		 1483static int
1484vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1485{
1486 int i, err = 0;
1487
1488 for (i = 0; i < adapter->num_rx_queues; i++) {
1489 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1490 if (unlikely(err)) {
1491 dev_err(&adapter->netdev->dev,
1492 "%s: failed to create rx queue%i\n",
1493 adapter->netdev->name, i);
1494 goto err_out;
1495 }
1496 }
1497 return err;
1498err_out:
1499 vmxnet3_rq_destroy_all(adapter);
1500 return err;
1501
1502}
1503
1504/* Multiple queue aware polling function for tx and rx */
1505
d1a890fa
SB		 1506static int
1507vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1508{
09c5088e 1509 int rcd_done = 0, i;
d1a890fa
SB		 1510 if (unlikely(adapter->shared->ecr))
1511 vmxnet3_process_events(adapter);
09c5088e
SB		 1512 for (i = 0; i < adapter->num_tx_queues; i++)
1513 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
d1a890fa 1514
09c5088e
SB		 1515 for (i = 0; i < adapter->num_rx_queues; i++)
1516 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1517 adapter, budget);
1518 return rcd_done;
d1a890fa
SB		 1519}
1520
1521
1522static int
1523vmxnet3_poll(struct napi_struct *napi, int budget)
1524{
09c5088e
SB		 1525 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1526 struct vmxnet3_rx_queue, napi);
1527 int rxd_done;
1528
1529 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1530
1531 if (rxd_done < budget) {
1532 napi_complete(napi);
1533 vmxnet3_enable_all_intrs(rx_queue->adapter);
1534 }
1535 return rxd_done;
1536}
1537
1538/*
1539 * NAPI polling function for MSI-X mode with multiple Rx queues
1540 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1541 */
1542
1543static int
1544vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1545{
1546 struct vmxnet3_rx_queue *rq = container_of(napi,
1547 struct vmxnet3_rx_queue, napi);
1548 struct vmxnet3_adapter *adapter = rq->adapter;
d1a890fa
SB		 1549 int rxd_done;
1550
09c5088e
SB		 1551 /* When sharing interrupt with corresponding tx queue, process
1552 * tx completions in that queue as well
1553 */
1554 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1555 struct vmxnet3_tx_queue *tq =
1556 &adapter->tx_queue[rq - adapter->rx_queue];
1557 vmxnet3_tq_tx_complete(tq, adapter);
1558 }
1559
1560 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
d1a890fa
SB		 1561
1562 if (rxd_done < budget) {
1563 napi_complete(napi);
09c5088e 1564 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
d1a890fa
SB		 1565 }
1566 return rxd_done;
1567}
1568
1569
09c5088e
SB		 1570#ifdef CONFIG_PCI_MSI
1571
1572/*
1573 * Handle completion interrupts on tx queues
1574 * Returns whether or not the intr is handled
1575 */
1576
1577static irqreturn_t
1578vmxnet3_msix_tx(int irq, void *data)
1579{
1580 struct vmxnet3_tx_queue *tq = data;
1581 struct vmxnet3_adapter *adapter = tq->adapter;
1582
1583 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1584 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
1585
1586 /* Handle the case where only one irq is allocate for all tx queues */
1587 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1588 int i;
1589 for (i = 0; i < adapter->num_tx_queues; i++) {
1590 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
1591 vmxnet3_tq_tx_complete(txq, adapter);
1592 }
1593 } else {
1594 vmxnet3_tq_tx_complete(tq, adapter);
1595 }
1596 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
1597
1598 return IRQ_HANDLED;
1599}
1600
1601
1602/*
1603 * Handle completion interrupts on rx queues. Returns whether or not the
1604 * intr is handled
1605 */
1606
1607static irqreturn_t
1608vmxnet3_msix_rx(int irq, void *data)
1609{
1610 struct vmxnet3_rx_queue *rq = data;
1611 struct vmxnet3_adapter *adapter = rq->adapter;
1612
1613 /* disable intr if needed */
1614 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1615 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
1616 napi_schedule(&rq->napi);
1617
1618 return IRQ_HANDLED;
1619}
1620
1621/*
1622 *----------------------------------------------------------------------------
1623 *
1624 * vmxnet3_msix_event --
1625 *
1626 * vmxnet3 msix event intr handler
1627 *
1628 * Result:
1629 * whether or not the intr is handled
1630 *
1631 *----------------------------------------------------------------------------
1632 */
1633
1634static irqreturn_t
1635vmxnet3_msix_event(int irq, void *data)
1636{
1637 struct net_device *dev = data;
1638 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1639
1640 /* disable intr if needed */
1641 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1642 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
1643
1644 if (adapter->shared->ecr)
1645 vmxnet3_process_events(adapter);
1646
1647 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
1648
1649 return IRQ_HANDLED;
1650}
1651
1652#endif /* CONFIG_PCI_MSI */
1653
1654
d1a890fa
SB		 1655/* Interrupt handler for vmxnet3 */
1656static irqreturn_t
1657vmxnet3_intr(int irq, void *dev_id)
1658{
1659 struct net_device *dev = dev_id;
1660 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1661
09c5088e 1662 if (adapter->intr.type == VMXNET3_IT_INTX) {
d1a890fa
SB		 1663 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
1664 if (unlikely(icr == 0))
1665 /* not ours */
1666 return IRQ_NONE;
1667 }
1668
1669
1670 /* disable intr if needed */
1671 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
09c5088e 1672 vmxnet3_disable_all_intrs(adapter);
d1a890fa 1673
09c5088e 1674 napi_schedule(&adapter->rx_queue[0].napi);
d1a890fa
SB		 1675
1676 return IRQ_HANDLED;
1677}
1678
1679#ifdef CONFIG_NET_POLL_CONTROLLER
1680
d1a890fa
SB		 1681/* netpoll callback. */
1682static void
1683vmxnet3_netpoll(struct net_device *netdev)
1684{
1685 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1686
09c5088e
SB		 1687 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1688 vmxnet3_disable_all_intrs(adapter);
1689
1690 vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size);
1691 vmxnet3_enable_all_intrs(adapter);
d1a890fa 1692
d1a890fa 1693}
09c5088e 1694#endif /* CONFIG_NET_POLL_CONTROLLER */
d1a890fa
SB		 1695
1696static int
1697vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
1698{
09c5088e
SB		 1699 struct vmxnet3_intr *intr = &adapter->intr;
1700 int err = 0, i;
1701 int vector = 0;
d1a890fa 1702
8f7e524c 1703#ifdef CONFIG_PCI_MSI
d1a890fa 1704 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 1705 for (i = 0; i < adapter->num_tx_queues; i++) {
1706 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1707 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
1708 adapter->netdev->name, vector);
1709 err = request_irq(
1710 intr->msix_entries[vector].vector,
1711 vmxnet3_msix_tx, 0,
1712 adapter->tx_queue[i].name,
1713 &adapter->tx_queue[i]);
1714 } else {
1715 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
1716 adapter->netdev->name, vector);
1717 }
1718 if (err) {
1719 dev_err(&adapter->netdev->dev,
1720 "Failed to request irq for MSIX, %s, "
1721 "error %d\n",
1722 adapter->tx_queue[i].name, err);
1723 return err;
1724 }
1725
1726 /* Handle the case where only 1 MSIx was allocated for
1727 * all tx queues */
1728 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1729 for (; i < adapter->num_tx_queues; i++)
1730 adapter->tx_queue[i].comp_ring.intr_idx
1731 = vector;
1732 vector++;
1733 break;
1734 } else {
1735 adapter->tx_queue[i].comp_ring.intr_idx
1736 = vector++;
1737 }
1738 }
1739 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
1740 vector = 0;
1741
1742 for (i = 0; i < adapter->num_rx_queues; i++) {
1743 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
1744 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
1745 adapter->netdev->name, vector);
1746 else
1747 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
1748 adapter->netdev->name, vector);
1749 err = request_irq(intr->msix_entries[vector].vector,
1750 vmxnet3_msix_rx, 0,
1751 adapter->rx_queue[i].name,
1752 &(adapter->rx_queue[i]));
1753 if (err) {
1754 printk(KERN_ERR "Failed to request irq for MSIX"
1755 ", %s, error %d\n",
1756 adapter->rx_queue[i].name, err);
1757 return err;
1758 }
1759
1760 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
1761 }
1762
1763 sprintf(intr->event_msi_vector_name, "%s-event-%d",
1764 adapter->netdev->name, vector);
1765 err = request_irq(intr->msix_entries[vector].vector,
1766 vmxnet3_msix_event, 0,
1767 intr->event_msi_vector_name, adapter->netdev);
1768 intr->event_intr_idx = vector;
1769
1770 } else if (intr->type == VMXNET3_IT_MSI) {
1771 adapter->num_rx_queues = 1;
d1a890fa
SB		 1772 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
1773 adapter->netdev->name, adapter->netdev);
09c5088e 1774 } else {
115924b6 1775#endif
09c5088e 1776 adapter->num_rx_queues = 1;
d1a890fa
SB		 1777 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
1778 IRQF_SHARED, adapter->netdev->name,
1779 adapter->netdev);
09c5088e 1780#ifdef CONFIG_PCI_MSI
d1a890fa 1781 }
09c5088e
SB		 1782#endif
1783 intr->num_intrs = vector + 1;
1784 if (err) {
d1a890fa 1785 printk(KERN_ERR "Failed to request irq %s (intr type:%d), error"
09c5088e
SB		 1786 ":%d\n", adapter->netdev->name, intr->type, err);
1787 } else {
1788 /* Number of rx queues will not change after this */
1789 for (i = 0; i < adapter->num_rx_queues; i++) {
1790 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1791 rq->qid = i;
1792 rq->qid2 = i + adapter->num_rx_queues;
1793 }
d1a890fa
SB		 1794
1795
d1a890fa 1796
09c5088e
SB		 1797 /* init our intr settings */
1798 for (i = 0; i < intr->num_intrs; i++)
1799 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
1800 if (adapter->intr.type != VMXNET3_IT_MSIX) {
1801 adapter->intr.event_intr_idx = 0;
1802 for (i = 0; i < adapter->num_tx_queues; i++)
1803 adapter->tx_queue[i].comp_ring.intr_idx = 0;
1804 adapter->rx_queue[0].comp_ring.intr_idx = 0;
1805 }
d1a890fa
SB		 1806
1807 printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors "
09c5088e
SB		 1808 "allocated\n", adapter->netdev->name, intr->type,
1809 intr->mask_mode, intr->num_intrs);
d1a890fa
SB		 1810 }
1811
1812 return err;
1813}
1814
1815
1816static void
1817vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
1818{
09c5088e
SB		 1819 struct vmxnet3_intr *intr = &adapter->intr;
1820 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
d1a890fa 1821
09c5088e 1822 switch (intr->type) {
8f7e524c 1823#ifdef CONFIG_PCI_MSI
d1a890fa
SB		 1824 case VMXNET3_IT_MSIX:
1825 {
09c5088e 1826 int i, vector = 0;
d1a890fa 1827
09c5088e
SB		 1828 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1829 for (i = 0; i < adapter->num_tx_queues; i++) {
1830 free_irq(intr->msix_entries[vector++].vector,
1831 &(adapter->tx_queue[i]));
1832 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
1833 break;
1834 }
1835 }
1836
1837 for (i = 0; i < adapter->num_rx_queues; i++) {
1838 free_irq(intr->msix_entries[vector++].vector,
1839 &(adapter->rx_queue[i]));
1840 }
1841
1842 free_irq(intr->msix_entries[vector].vector,
1843 adapter->netdev);
1844 BUG_ON(vector >= intr->num_intrs);
d1a890fa
SB		 1845 break;
1846 }
8f7e524c 1847#endif
d1a890fa
SB		 1848 case VMXNET3_IT_MSI:
1849 free_irq(adapter->pdev->irq, adapter->netdev);
1850 break;
1851 case VMXNET3_IT_INTX:
1852 free_irq(adapter->pdev->irq, adapter->netdev);
1853 break;
1854 default:
1855 BUG_ON(true);
1856 }
1857}
1858
d1a890fa
SB		 1859static void
1860vmxnet3_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
1861{
1862 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1863 struct Vmxnet3_DriverShared *shared = adapter->shared;
1864 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1865
1866 if (grp) {
1867 /* add vlan rx stripping. */
1868 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX) {
1869 int i;
d1a890fa
SB		 1870 adapter->vlan_grp = grp;
1871
d1a890fa
SB		 1872 /*
1873 * Clear entire vfTable; then enable untagged pkts.
1874 * Note: setting one entry in vfTable to non-zero turns
1875 * on VLAN rx filtering.
1876 */
1877 for (i = 0; i < VMXNET3_VFT_SIZE; i++)
1878 vfTable[i] = 0;
1879
1880 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
1881 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1882 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1883 } else {
1884 printk(KERN_ERR "%s: vlan_rx_register when device has "
1885 "no NETIF_F_HW_VLAN_RX\n", netdev->name);
1886 }
1887 } else {
1888 /* remove vlan rx stripping. */
1889 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
1890 adapter->vlan_grp = NULL;
1891
3843e515 1892 if (devRead->misc.uptFeatures & UPT1_F_RXVLAN) {
d1a890fa
SB		 1893 int i;
1894
1895 for (i = 0; i < VMXNET3_VFT_SIZE; i++) {
1896 /* clear entire vfTable; this also disables
1897 * VLAN rx filtering
1898 */
1899 vfTable[i] = 0;
1900 }
1901 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1902 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
d1a890fa
SB		 1903 }
1904 }
1905}
1906
1907
1908static void
1909vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
1910{
1911 if (adapter->vlan_grp) {
1912 u16 vid;
1913 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1914 bool activeVlan = false;
1915
b738127d 1916 for (vid = 0; vid < VLAN_N_VID; vid++) {
d1a890fa
SB		 1917 if (vlan_group_get_device(adapter->vlan_grp, vid)) {
1918 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
1919 activeVlan = true;
1920 }
1921 }
1922 if (activeVlan) {
1923 /* continue to allow untagged pkts */
1924 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
1925 }
1926 }
1927}
1928
1929
1930static void
1931vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1932{
1933 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1934 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1935
1936 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
1937 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1938 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1939}
1940
1941
1942static void
1943vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1944{
1945 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1946 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1947
1948 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
1949 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1950 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1951}
1952
1953
1954static u8 *
1955vmxnet3_copy_mc(struct net_device *netdev)
1956{
1957 u8 *buf = NULL;
4cd24eaf 1958 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
d1a890fa
SB		 1959
1960 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
1961 if (sz <= 0xffff) {
1962 /* We may be called with BH disabled */
1963 buf = kmalloc(sz, GFP_ATOMIC);
1964 if (buf) {
22bedad3 1965 struct netdev_hw_addr *ha;
567ec874 1966 int i = 0;
d1a890fa 1967
22bedad3
JP		 1968 netdev_for_each_mc_addr(ha, netdev)
1969 memcpy(buf + i++ * ETH_ALEN, ha->addr,
d1a890fa 1970 ETH_ALEN);
d1a890fa
SB		 1971 }
1972 }
1973 return buf;
1974}
1975
1976
1977static void
1978vmxnet3_set_mc(struct net_device *netdev)
1979{
1980 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1981 struct Vmxnet3_RxFilterConf *rxConf =
1982 &adapter->shared->devRead.rxFilterConf;
1983 u8 *new_table = NULL;
1984 u32 new_mode = VMXNET3_RXM_UCAST;
1985
1986 if (netdev->flags & IFF_PROMISC)
1987 new_mode |= VMXNET3_RXM_PROMISC;
1988
1989 if (netdev->flags & IFF_BROADCAST)
1990 new_mode |= VMXNET3_RXM_BCAST;
1991
1992 if (netdev->flags & IFF_ALLMULTI)
1993 new_mode |= VMXNET3_RXM_ALL_MULTI;
1994 else
4cd24eaf 1995 if (!netdev_mc_empty(netdev)) {
d1a890fa
SB		 1996 new_table = vmxnet3_copy_mc(netdev);
1997 if (new_table) {
1998 new_mode |= VMXNET3_RXM_MCAST;
115924b6 1999 rxConf->mfTableLen = cpu_to_le16(
4cd24eaf 2000 netdev_mc_count(netdev) * ETH_ALEN);
115924b6
SB		 2001 rxConf->mfTablePA = cpu_to_le64(virt_to_phys(
2002 new_table));
d1a890fa
SB		 2003 } else {
2004 printk(KERN_INFO "%s: failed to copy mcast list"
2005 ", setting ALL_MULTI\n", netdev->name);
2006 new_mode |= VMXNET3_RXM_ALL_MULTI;
2007 }
2008 }
2009
2010
2011 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2012 rxConf->mfTableLen = 0;
2013 rxConf->mfTablePA = 0;
2014 }
2015
2016 if (new_mode != rxConf->rxMode) {
115924b6 2017 rxConf->rxMode = cpu_to_le32(new_mode);
d1a890fa
SB		 2018 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2019 VMXNET3_CMD_UPDATE_RX_MODE);
2020 }
2021
2022 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2023 VMXNET3_CMD_UPDATE_MAC_FILTERS);
2024
2025 kfree(new_table);
2026}
2027
09c5088e
SB		 2028void
2029vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2030{
2031 int i;
2032
2033 for (i = 0; i < adapter->num_rx_queues; i++)
2034 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2035}
2036
d1a890fa
SB		 2037
2038/*
2039 * Set up driver_shared based on settings in adapter.
2040 */
2041
2042static void
2043vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2044{
2045 struct Vmxnet3_DriverShared *shared = adapter->shared;
2046 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2047 struct Vmxnet3_TxQueueConf *tqc;
2048 struct Vmxnet3_RxQueueConf *rqc;
2049 int i;
2050
2051 memset(shared, 0, sizeof(*shared));
2052
2053 /* driver settings */
115924b6
SB		 2054 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2055 devRead->misc.driverInfo.version = cpu_to_le32(
2056 VMXNET3_DRIVER_VERSION_NUM);
d1a890fa
SB		 2057 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2058 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2059 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
115924b6
SB		 2060 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2061 *((u32 *)&devRead->misc.driverInfo.gos));
2062 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2063 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
d1a890fa 2064
115924b6
SB		 2065 devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter));
2066 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
d1a890fa
SB		 2067
2068 /* set up feature flags */
2069 if (adapter->rxcsum)
3843e515 2070 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
d1a890fa
SB		 2071
2072 if (adapter->lro) {
3843e515 2073 devRead->misc.uptFeatures |= UPT1_F_LRO;
115924b6 2074 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
d1a890fa 2075 }
54da3d00 2076 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX)
3843e515 2077 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
d1a890fa 2078
115924b6
SB		 2079 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2080 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2081 devRead->misc.queueDescLen = cpu_to_le32(
09c5088e
SB		 2082 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2083 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
d1a890fa
SB		 2084
2085 /* tx queue settings */
09c5088e
SB		 2086 devRead->misc.numTxQueues = adapter->num_tx_queues;
2087 for (i = 0; i < adapter->num_tx_queues; i++) {
2088 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2089 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2090 tqc = &adapter->tqd_start[i].conf;
2091 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2092 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2093 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2094 tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info));
2095 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2096 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2097 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2098 tqc->ddLen = cpu_to_le32(
2099 sizeof(struct vmxnet3_tx_buf_info) *
2100 tqc->txRingSize);
2101 tqc->intrIdx = tq->comp_ring.intr_idx;
2102 }
d1a890fa
SB		 2103
2104 /* rx queue settings */
09c5088e
SB		 2105 devRead->misc.numRxQueues = adapter->num_rx_queues;
2106 for (i = 0; i < adapter->num_rx_queues; i++) {
2107 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2108 rqc = &adapter->rqd_start[i].conf;
2109 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2110 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2111 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2112 rqc->ddPA = cpu_to_le64(virt_to_phys(
2113 rq->buf_info));
2114 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2115 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2116 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2117 rqc->ddLen = cpu_to_le32(
2118 sizeof(struct vmxnet3_rx_buf_info) *
2119 (rqc->rxRingSize[0] +
2120 rqc->rxRingSize[1]));
2121 rqc->intrIdx = rq->comp_ring.intr_idx;
2122 }
2123
2124#ifdef VMXNET3_RSS
2125 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2126
2127 if (adapter->rss) {
2128 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2129 devRead->misc.uptFeatures |= UPT1_F_RSS;
2130 devRead->misc.numRxQueues = adapter->num_rx_queues;
2131 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2132 UPT1_RSS_HASH_TYPE_IPV4 |
2133 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2134 UPT1_RSS_HASH_TYPE_IPV6;
2135 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2136 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2137 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2138 get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize);
2139 for (i = 0; i < rssConf->indTableSize; i++)
2140 rssConf->indTable[i] = i % adapter->num_rx_queues;
2141
2142 devRead->rssConfDesc.confVer = 1;
2143 devRead->rssConfDesc.confLen = sizeof(*rssConf);
2144 devRead->rssConfDesc.confPA = virt_to_phys(rssConf);
2145 }
2146
2147#endif /* VMXNET3_RSS */
d1a890fa
SB		 2148
2149 /* intr settings */
2150 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2151 VMXNET3_IMM_AUTO;
2152 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2153 for (i = 0; i < adapter->intr.num_intrs; i++)
2154 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2155
2156 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
6929fe8a 2157 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 2158
2159 /* rx filter settings */
2160 devRead->rxFilterConf.rxMode = 0;
2161 vmxnet3_restore_vlan(adapter);
f9f25026
SB		 2162 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2163
d1a890fa
SB		 2164 /* the rest are already zeroed */
2165}
2166
2167
2168int
2169vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2170{
09c5088e 2171 int err, i;
d1a890fa
SB		 2172 u32 ret;
2173
09c5088e
SB		 2174 dev_dbg(&adapter->netdev->dev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
2175 " ring sizes %u %u %u\n", adapter->netdev->name,
2176 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2177 adapter->tx_queue[0].tx_ring.size,
2178 adapter->rx_queue[0].rx_ring[0].size,
2179 adapter->rx_queue[0].rx_ring[1].size);
2180
2181 vmxnet3_tq_init_all(adapter);
2182 err = vmxnet3_rq_init_all(adapter);
d1a890fa
SB		 2183 if (err) {
2184 printk(KERN_ERR "Failed to init rx queue for %s: error %d\n",
2185 adapter->netdev->name, err);
2186 goto rq_err;
2187 }
2188
2189 err = vmxnet3_request_irqs(adapter);
2190 if (err) {
2191 printk(KERN_ERR "Failed to setup irq for %s: error %d\n",
2192 adapter->netdev->name, err);
2193 goto irq_err;
2194 }
2195
2196 vmxnet3_setup_driver_shared(adapter);
2197
115924b6
SB		 2198 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2199 adapter->shared_pa));
2200 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2201 adapter->shared_pa));
d1a890fa
SB		 2202 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2203 VMXNET3_CMD_ACTIVATE_DEV);
2204 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2205
2206 if (ret != 0) {
2207 printk(KERN_ERR "Failed to activate dev %s: error %u\n",
2208 adapter->netdev->name, ret);
2209 err = -EINVAL;
2210 goto activate_err;
2211 }
09c5088e
SB		 2212
2213 for (i = 0; i < adapter->num_rx_queues; i++) {
2214 VMXNET3_WRITE_BAR0_REG(adapter,
2215 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2216 adapter->rx_queue[i].rx_ring[0].next2fill);
2217 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2218 (i * VMXNET3_REG_ALIGN)),
2219 adapter->rx_queue[i].rx_ring[1].next2fill);
2220 }
d1a890fa
SB		 2221
2222 /* Apply the rx filter settins last. */
2223 vmxnet3_set_mc(adapter->netdev);
2224
2225 /*
2226 * Check link state when first activating device. It will start the
2227 * tx queue if the link is up.
2228 */
4a1745fc 2229 vmxnet3_check_link(adapter, true);
09c5088e
SB		 2230 for (i = 0; i < adapter->num_rx_queues; i++)
2231 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2232 vmxnet3_enable_all_intrs(adapter);
2233 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2234 return 0;
2235
2236activate_err:
2237 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2238 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2239 vmxnet3_free_irqs(adapter);
2240irq_err:
2241rq_err:
2242 /* free up buffers we allocated */
09c5088e 2243 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2244 return err;
2245}
2246
2247
2248void
2249vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2250{
2251 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
2252}
2253
2254
2255int
2256vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2257{
09c5088e 2258 int i;
d1a890fa
SB		 2259 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2260 return 0;
2261
2262
2263 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2264 VMXNET3_CMD_QUIESCE_DEV);
2265 vmxnet3_disable_all_intrs(adapter);
2266
09c5088e
SB		 2267 for (i = 0; i < adapter->num_rx_queues; i++)
2268 napi_disable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2269 netif_tx_disable(adapter->netdev);
2270 adapter->link_speed = 0;
2271 netif_carrier_off(adapter->netdev);
2272
09c5088e
SB		 2273 vmxnet3_tq_cleanup_all(adapter);
2274 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2275 vmxnet3_free_irqs(adapter);
2276 return 0;
2277}
2278
2279
2280static void
2281vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2282{
2283 u32 tmp;
2284
2285 tmp = *(u32 *)mac;
2286 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2287
2288 tmp = (mac[5] << 8) | mac[4];
2289 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2290}
2291
2292
2293static int
2294vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2295{
2296 struct sockaddr *addr = p;
2297 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2298
2299 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2300 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2301
2302 return 0;
2303}
2304
2305
2306/* ==================== initialization and cleanup routines ============ */
2307
2308static int
2309vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
2310{
2311 int err;
2312 unsigned long mmio_start, mmio_len;
2313 struct pci_dev *pdev = adapter->pdev;
2314
2315 err = pci_enable_device(pdev);
2316 if (err) {
2317 printk(KERN_ERR "Failed to enable adapter %s: error %d\n",
2318 pci_name(pdev), err);
2319 return err;
2320 }
2321
2322 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
2323 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
2324 printk(KERN_ERR "pci_set_consistent_dma_mask failed "
2325 "for adapter %s\n", pci_name(pdev));
2326 err = -EIO;
2327 goto err_set_mask;
2328 }
2329 *dma64 = true;
2330 } else {
2331 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
2332 printk(KERN_ERR "pci_set_dma_mask failed for adapter "
2333 "%s\n", pci_name(pdev));
2334 err = -EIO;
2335 goto err_set_mask;
2336 }
2337 *dma64 = false;
2338 }
2339
2340 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2341 vmxnet3_driver_name);
2342 if (err) {
2343 printk(KERN_ERR "Failed to request region for adapter %s: "
2344 "error %d\n", pci_name(pdev), err);
2345 goto err_set_mask;
2346 }
2347
2348 pci_set_master(pdev);
2349
2350 mmio_start = pci_resource_start(pdev, 0);
2351 mmio_len = pci_resource_len(pdev, 0);
2352 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2353 if (!adapter->hw_addr0) {
2354 printk(KERN_ERR "Failed to map bar0 for adapter %s\n",
2355 pci_name(pdev));
2356 err = -EIO;
2357 goto err_ioremap;
2358 }
2359
2360 mmio_start = pci_resource_start(pdev, 1);
2361 mmio_len = pci_resource_len(pdev, 1);
2362 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2363 if (!adapter->hw_addr1) {
2364 printk(KERN_ERR "Failed to map bar1 for adapter %s\n",
2365 pci_name(pdev));
2366 err = -EIO;
2367 goto err_bar1;
2368 }
2369 return 0;
2370
2371err_bar1:
2372 iounmap(adapter->hw_addr0);
2373err_ioremap:
2374 pci_release_selected_regions(pdev, (1 << 2) - 1);
2375err_set_mask:
2376 pci_disable_device(pdev);
2377 return err;
2378}
2379
2380
2381static void
2382vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2383{
2384 BUG_ON(!adapter->pdev);
2385
2386 iounmap(adapter->hw_addr0);
2387 iounmap(adapter->hw_addr1);
2388 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2389 pci_disable_device(adapter->pdev);
2390}
2391
2392
2393static void
2394vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2395{
09c5088e
SB		 2396 size_t sz, i, ring0_size, ring1_size, comp_size;
2397 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
2398
d1a890fa
SB		 2399
2400 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2401 VMXNET3_MAX_ETH_HDR_SIZE) {
2402 adapter->skb_buf_size = adapter->netdev->mtu +
2403 VMXNET3_MAX_ETH_HDR_SIZE;
2404 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2405 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2406
2407 adapter->rx_buf_per_pkt = 1;
2408 } else {
2409 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2410 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2411 VMXNET3_MAX_ETH_HDR_SIZE;
2412 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2413 }
2414
2415 /*
2416 * for simplicity, force the ring0 size to be a multiple of
2417 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2418 */
2419 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
09c5088e
SB		 2420 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2421 ring0_size = (ring0_size + sz - 1) / sz * sz;
a53255d3 2422 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
09c5088e
SB		 2423 sz * sz);
2424 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2425 comp_size = ring0_size + ring1_size;
2426
2427 for (i = 0; i < adapter->num_rx_queues; i++) {
2428 rq = &adapter->rx_queue[i];
2429 rq->rx_ring[0].size = ring0_size;
2430 rq->rx_ring[1].size = ring1_size;
2431 rq->comp_ring.size = comp_size;
2432 }
d1a890fa
SB		 2433}
2434
2435
2436int
2437vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2438 u32 rx_ring_size, u32 rx_ring2_size)
2439{
09c5088e
SB		 2440 int err = 0, i;
2441
2442 for (i = 0; i < adapter->num_tx_queues; i++) {
2443 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2444 tq->tx_ring.size = tx_ring_size;
2445 tq->data_ring.size = tx_ring_size;
2446 tq->comp_ring.size = tx_ring_size;
2447 tq->shared = &adapter->tqd_start[i].ctrl;
2448 tq->stopped = true;
2449 tq->adapter = adapter;
2450 tq->qid = i;
2451 err = vmxnet3_tq_create(tq, adapter);
2452 /*
2453 * Too late to change num_tx_queues. We cannot do away with
2454 * lesser number of queues than what we asked for
2455 */
2456 if (err)
2457 goto queue_err;
2458 }
d1a890fa 2459
09c5088e
SB		 2460 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2461 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
d1a890fa 2462 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e
SB		 2463 for (i = 0; i < adapter->num_rx_queues; i++) {
2464 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2465 /* qid and qid2 for rx queues will be assigned later when num
2466 * of rx queues is finalized after allocating intrs */
2467 rq->shared = &adapter->rqd_start[i].ctrl;
2468 rq->adapter = adapter;
2469 err = vmxnet3_rq_create(rq, adapter);
2470 if (err) {
2471 if (i == 0) {
2472 printk(KERN_ERR "Could not allocate any rx"
2473 "queues. Aborting.\n");
2474 goto queue_err;
2475 } else {
2476 printk(KERN_INFO "Number of rx queues changed "
2477 "to : %d.\n", i);
2478 adapter->num_rx_queues = i;
2479 err = 0;
2480 break;
2481 }
2482 }
2483 }
2484 return err;
2485queue_err:
2486 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2487 return err;
2488}
2489
2490static int
2491vmxnet3_open(struct net_device *netdev)
2492{
2493 struct vmxnet3_adapter *adapter;
09c5088e 2494 int err, i;
d1a890fa
SB		 2495
2496 adapter = netdev_priv(netdev);
2497
09c5088e
SB		 2498 for (i = 0; i < adapter->num_tx_queues; i++)
2499 spin_lock_init(&adapter->tx_queue[i].tx_lock);
d1a890fa
SB		 2500
2501 err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE,
2502 VMXNET3_DEF_RX_RING_SIZE,
2503 VMXNET3_DEF_RX_RING_SIZE);
2504 if (err)
2505 goto queue_err;
2506
2507 err = vmxnet3_activate_dev(adapter);
2508 if (err)
2509 goto activate_err;
2510
2511 return 0;
2512
2513activate_err:
09c5088e
SB		 2514 vmxnet3_rq_destroy_all(adapter);
2515 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2516queue_err:
2517 return err;
2518}
2519
2520
2521static int
2522vmxnet3_close(struct net_device *netdev)
2523{
2524 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2525
2526 /*
2527 * Reset_work may be in the middle of resetting the device, wait for its
2528 * completion.
2529 */
2530 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2531 msleep(1);
2532
2533 vmxnet3_quiesce_dev(adapter);
2534
09c5088e
SB		 2535 vmxnet3_rq_destroy_all(adapter);
2536 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2537
2538 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2539
2540
2541 return 0;
2542}
2543
2544
2545void
2546vmxnet3_force_close(struct vmxnet3_adapter *adapter)
2547{
09c5088e
SB		 2548 int i;
2549
d1a890fa
SB		 2550 /*
2551 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
2552 * vmxnet3_close() will deadlock.
2553 */
2554 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
2555
2556 /* we need to enable NAPI, otherwise dev_close will deadlock */
09c5088e
SB		 2557 for (i = 0; i < adapter->num_rx_queues; i++)
2558 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2559 dev_close(adapter->netdev);
2560}
2561
2562
2563static int
2564vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
2565{
2566 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2567 int err = 0;
2568
2569 if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU)
2570 return -EINVAL;
2571
2572 if (new_mtu > 1500 && !adapter->jumbo_frame)
2573 return -EINVAL;
2574
2575 netdev->mtu = new_mtu;
2576
2577 /*
2578 * Reset_work may be in the middle of resetting the device, wait for its
2579 * completion.
2580 */
2581 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2582 msleep(1);
2583
2584 if (netif_running(netdev)) {
2585 vmxnet3_quiesce_dev(adapter);
2586 vmxnet3_reset_dev(adapter);
2587
2588 /* we need to re-create the rx queue based on the new mtu */
09c5088e 2589 vmxnet3_rq_destroy_all(adapter);
d1a890fa 2590 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e 2591 err = vmxnet3_rq_create_all(adapter);
d1a890fa 2592 if (err) {
09c5088e 2593 printk(KERN_ERR "%s: failed to re-create rx queues,"
d1a890fa
SB		 2594 " error %d. Closing it.\n", netdev->name, err);
2595 goto out;
2596 }
2597
2598 err = vmxnet3_activate_dev(adapter);
2599 if (err) {
2600 printk(KERN_ERR "%s: failed to re-activate, error %d. "
2601 "Closing it\n", netdev->name, err);
2602 goto out;
2603 }
2604 }
2605
2606out:
2607 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2608 if (err)
2609 vmxnet3_force_close(adapter);
2610
2611 return err;
2612}
2613
2614
2615static void
2616vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
2617{
2618 struct net_device *netdev = adapter->netdev;
2619
2620 netdev->features = NETIF_F_SG |
2621 NETIF_F_HW_CSUM |
2622 NETIF_F_HW_VLAN_TX |
2623 NETIF_F_HW_VLAN_RX |
2624 NETIF_F_HW_VLAN_FILTER |
2625 NETIF_F_TSO |
2626 NETIF_F_TSO6 |
2627 NETIF_F_LRO;
2628
2629 printk(KERN_INFO "features: sg csum vlan jf tso tsoIPv6 lro");
2630
2631 adapter->rxcsum = true;
2632 adapter->jumbo_frame = true;
2633 adapter->lro = true;
2634
2635 if (dma64) {
2636 netdev->features |= NETIF_F_HIGHDMA;
2637 printk(" highDMA");
2638 }
2639
2640 netdev->vlan_features = netdev->features;
2641 printk("\n");
2642}
2643
2644
2645static void
2646vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2647{
2648 u32 tmp;
2649
2650 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
2651 *(u32 *)mac = tmp;
2652
2653 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
2654 mac[4] = tmp & 0xff;
2655 mac[5] = (tmp >> 8) & 0xff;
2656}
2657
09c5088e
SB		 2658#ifdef CONFIG_PCI_MSI
2659
2660/*
2661 * Enable MSIx vectors.
2662 * Returns :
2663 * 0 on successful enabling of required vectors,
2664 * VMXNET3_LINUX_MIN_MSIX_VECT when only minumum number of vectors required
2665 * could be enabled.
2666 * number of vectors which can be enabled otherwise (this number is smaller
2667 * than VMXNET3_LINUX_MIN_MSIX_VECT)
2668 */
2669
2670static int
2671vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter,
2672 int vectors)
2673{
2674 int err = 0, vector_threshold;
2675 vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT;
2676
2677 while (vectors >= vector_threshold) {
2678 err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries,
2679 vectors);
2680 if (!err) {
2681 adapter->intr.num_intrs = vectors;
2682 return 0;
2683 } else if (err < 0) {
2684 printk(KERN_ERR "Failed to enable MSI-X for %s, error"
2685 " %d\n", adapter->netdev->name, err);
2686 vectors = 0;
2687 } else if (err < vector_threshold) {
2688 break;
2689 } else {
2690 /* If fails to enable required number of MSI-x vectors
2691 * try enabling 3 of them. One each for rx, tx and event
2692 */
2693 vectors = vector_threshold;
2694 printk(KERN_ERR "Failed to enable %d MSI-X for %s, try"
2695 " %d instead\n", vectors, adapter->netdev->name,
2696 vector_threshold);
2697 }
2698 }
2699
2700 printk(KERN_INFO "Number of MSI-X interrupts which can be allocatedi"
2701 " are lower than min threshold required.\n");
2702 return err;
2703}
2704
2705
2706#endif /* CONFIG_PCI_MSI */
d1a890fa
SB		 2707
2708static void
2709vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
2710{
2711 u32 cfg;
2712
2713 /* intr settings */
2714 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2715 VMXNET3_CMD_GET_CONF_INTR);
2716 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2717 adapter->intr.type = cfg & 0x3;
2718 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
2719
2720 if (adapter->intr.type == VMXNET3_IT_AUTO) {
0bdc0d70
SB		 2721 adapter->intr.type = VMXNET3_IT_MSIX;
2722 }
d1a890fa 2723
8f7e524c 2724#ifdef CONFIG_PCI_MSI
0bdc0d70 2725 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 2726 int vector, err = 0;
2727
2728 adapter->intr.num_intrs = (adapter->share_intr ==
2729 VMXNET3_INTR_TXSHARE) ? 1 :
2730 adapter->num_tx_queues;
2731 adapter->intr.num_intrs += (adapter->share_intr ==
2732 VMXNET3_INTR_BUDDYSHARE) ? 0 :
2733 adapter->num_rx_queues;
2734 adapter->intr.num_intrs += 1; /* for link event */
2735
2736 adapter->intr.num_intrs = (adapter->intr.num_intrs >
2737 VMXNET3_LINUX_MIN_MSIX_VECT
2738 ? adapter->intr.num_intrs :
2739 VMXNET3_LINUX_MIN_MSIX_VECT);
2740
2741 for (vector = 0; vector < adapter->intr.num_intrs; vector++)
2742 adapter->intr.msix_entries[vector].entry = vector;
2743
2744 err = vmxnet3_acquire_msix_vectors(adapter,
2745 adapter->intr.num_intrs);
2746 /* If we cannot allocate one MSIx vector per queue
2747 * then limit the number of rx queues to 1
2748 */
2749 if (err == VMXNET3_LINUX_MIN_MSIX_VECT) {
2750 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
2751 || adapter->num_rx_queues != 2) {
2752 adapter->share_intr = VMXNET3_INTR_TXSHARE;
2753 printk(KERN_ERR "Number of rx queues : 1\n");
2754 adapter->num_rx_queues = 1;
2755 adapter->intr.num_intrs =
2756 VMXNET3_LINUX_MIN_MSIX_VECT;
2757 }
d1a890fa
SB		 2758 return;
2759 }
09c5088e
SB		 2760 if (!err)
2761 return;
2762
2763 /* If we cannot allocate MSIx vectors use only one rx queue */
2764 printk(KERN_INFO "Failed to enable MSI-X for %s, error %d."
2765 "#rx queues : 1, try MSI\n", adapter->netdev->name, err);
2766
0bdc0d70
SB		 2767 adapter->intr.type = VMXNET3_IT_MSI;
2768 }
d1a890fa 2769
0bdc0d70
SB		 2770 if (adapter->intr.type == VMXNET3_IT_MSI) {
2771 int err;
d1a890fa
SB		 2772 err = pci_enable_msi(adapter->pdev);
2773 if (!err) {
09c5088e 2774 adapter->num_rx_queues = 1;
d1a890fa 2775 adapter->intr.num_intrs = 1;
d1a890fa
SB		 2776 return;
2777 }
2778 }
0bdc0d70 2779#endif /* CONFIG_PCI_MSI */
d1a890fa 2780
09c5088e
SB		 2781 adapter->num_rx_queues = 1;
2782 printk(KERN_INFO "Using INTx interrupt, #Rx queues: 1.\n");
d1a890fa
SB		 2783 adapter->intr.type = VMXNET3_IT_INTX;
2784
2785 /* INT-X related setting */
2786 adapter->intr.num_intrs = 1;
2787}
2788
2789
2790static void
2791vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
2792{
2793 if (adapter->intr.type == VMXNET3_IT_MSIX)
2794 pci_disable_msix(adapter->pdev);
2795 else if (adapter->intr.type == VMXNET3_IT_MSI)
2796 pci_disable_msi(adapter->pdev);
2797 else
2798 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
2799}
2800
2801
2802static void
2803vmxnet3_tx_timeout(struct net_device *netdev)
2804{
2805 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2806 adapter->tx_timeout_count++;
2807
2808 printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name);
2809 schedule_work(&adapter->work);
09c5088e 2810 netif_wake_queue(adapter->netdev);
d1a890fa
SB		 2811}
2812
2813
2814static void
2815vmxnet3_reset_work(struct work_struct *data)
2816{
2817 struct vmxnet3_adapter *adapter;
2818
2819 adapter = container_of(data, struct vmxnet3_adapter, work);
2820
2821 /* if another thread is resetting the device, no need to proceed */
2822 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2823 return;
2824
2825 /* if the device is closed, we must leave it alone */
d9a5f210 2826 rtnl_lock();
d1a890fa
SB		 2827 if (netif_running(adapter->netdev)) {
2828 printk(KERN_INFO "%s: resetting\n", adapter->netdev->name);
2829 vmxnet3_quiesce_dev(adapter);
2830 vmxnet3_reset_dev(adapter);
2831 vmxnet3_activate_dev(adapter);
2832 } else {
2833 printk(KERN_INFO "%s: already closed\n", adapter->netdev->name);
2834 }
d9a5f210 2835 rtnl_unlock();
d1a890fa
SB		 2836
2837 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2838}
2839
2840
2841static int __devinit
2842vmxnet3_probe_device(struct pci_dev *pdev,
2843 const struct pci_device_id *id)
2844{
2845 static const struct net_device_ops vmxnet3_netdev_ops = {
2846 .ndo_open = vmxnet3_open,
2847 .ndo_stop = vmxnet3_close,
2848 .ndo_start_xmit = vmxnet3_xmit_frame,
2849 .ndo_set_mac_address = vmxnet3_set_mac_addr,
2850 .ndo_change_mtu = vmxnet3_change_mtu,
2851 .ndo_get_stats = vmxnet3_get_stats,
2852 .ndo_tx_timeout = vmxnet3_tx_timeout,
2853 .ndo_set_multicast_list = vmxnet3_set_mc,
2854 .ndo_vlan_rx_register = vmxnet3_vlan_rx_register,
2855 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
2856 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
2857#ifdef CONFIG_NET_POLL_CONTROLLER
2858 .ndo_poll_controller = vmxnet3_netpoll,
2859#endif
2860 };
2861 int err;
2862 bool dma64 = false; /* stupid gcc */
2863 u32 ver;
2864 struct net_device *netdev;
2865 struct vmxnet3_adapter *adapter;
2866 u8 mac[ETH_ALEN];
09c5088e
SB		 2867 int size;
2868 int num_tx_queues;
2869 int num_rx_queues;
2870
2871#ifdef VMXNET3_RSS
2872 if (enable_mq)
2873 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
2874 (int)num_online_cpus());
2875 else
2876#endif
2877 num_rx_queues = 1;
2878
2879 if (enable_mq)
2880 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
2881 (int)num_online_cpus());
2882 else
2883 num_tx_queues = 1;
2884
2885 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
2886 max(num_tx_queues, num_rx_queues));
2887 printk(KERN_INFO "# of Tx queues : %d, # of Rx queues : %d\n",
2888 num_tx_queues, num_rx_queues);
d1a890fa 2889
d1a890fa
SB		 2890 if (!netdev) {
2891 printk(KERN_ERR "Failed to alloc ethernet device for adapter "
2892 "%s\n", pci_name(pdev));
2893 return -ENOMEM;
2894 }
2895
2896 pci_set_drvdata(pdev, netdev);
2897 adapter = netdev_priv(netdev);
2898 adapter->netdev = netdev;
2899 adapter->pdev = pdev;
2900
2901 adapter->shared = pci_alloc_consistent(adapter->pdev,
2902 sizeof(struct Vmxnet3_DriverShared),
2903 &adapter->shared_pa);
2904 if (!adapter->shared) {
2905 printk(KERN_ERR "Failed to allocate memory for %s\n",
2906 pci_name(pdev));
2907 err = -ENOMEM;
2908 goto err_alloc_shared;
2909 }
2910
09c5088e
SB		 2911 adapter->num_rx_queues = num_rx_queues;
2912 adapter->num_tx_queues = num_tx_queues;
2913
2914 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
2915 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
2916 adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size,
d1a890fa
SB		 2917 &adapter->queue_desc_pa);
2918
2919 if (!adapter->tqd_start) {
2920 printk(KERN_ERR "Failed to allocate memory for %s\n",
2921 pci_name(pdev));
2922 err = -ENOMEM;
2923 goto err_alloc_queue_desc;
2924 }
09c5088e
SB		 2925 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
2926 adapter->num_tx_queues);
d1a890fa
SB		 2927
2928 adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL);
2929 if (adapter->pm_conf == NULL) {
2930 printk(KERN_ERR "Failed to allocate memory for %s\n",
2931 pci_name(pdev));
2932 err = -ENOMEM;
2933 goto err_alloc_pm;
2934 }
2935
09c5088e
SB		 2936#ifdef VMXNET3_RSS
2937
2938 adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL);
2939 if (adapter->rss_conf == NULL) {
2940 printk(KERN_ERR "Failed to allocate memory for %s\n",
2941 pci_name(pdev));
2942 err = -ENOMEM;
2943 goto err_alloc_rss;
2944 }
2945#endif /* VMXNET3_RSS */
2946
d1a890fa
SB		 2947 err = vmxnet3_alloc_pci_resources(adapter, &dma64);
2948 if (err < 0)
2949 goto err_alloc_pci;
2950
2951 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
2952 if (ver & 1) {
2953 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1);
2954 } else {
2955 printk(KERN_ERR "Incompatible h/w version (0x%x) for adapter"
2956 " %s\n", ver, pci_name(pdev));
2957 err = -EBUSY;
2958 goto err_ver;
2959 }
2960
2961 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
2962 if (ver & 1) {
2963 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
2964 } else {
2965 printk(KERN_ERR "Incompatible upt version (0x%x) for "
2966 "adapter %s\n", ver, pci_name(pdev));
2967 err = -EBUSY;
2968 goto err_ver;
2969 }
2970
2971 vmxnet3_declare_features(adapter, dma64);
2972
2973 adapter->dev_number = atomic_read(&devices_found);
09c5088e
SB		 2974
2975 adapter->share_intr = irq_share_mode;
2976 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE &&
2977 adapter->num_tx_queues != adapter->num_rx_queues)
2978 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
2979
d1a890fa
SB		 2980 vmxnet3_alloc_intr_resources(adapter);
2981
09c5088e
SB		 2982#ifdef VMXNET3_RSS
2983 if (adapter->num_rx_queues > 1 &&
2984 adapter->intr.type == VMXNET3_IT_MSIX) {
2985 adapter->rss = true;
2986 printk(KERN_INFO "RSS is enabled.\n");
2987 } else {
2988 adapter->rss = false;
2989 }
2990#endif
2991
d1a890fa
SB		 2992 vmxnet3_read_mac_addr(adapter, mac);
2993 memcpy(netdev->dev_addr, mac, netdev->addr_len);
2994
2995 netdev->netdev_ops = &vmxnet3_netdev_ops;
d1a890fa 2996 vmxnet3_set_ethtool_ops(netdev);
09c5088e 2997 netdev->watchdog_timeo = 5 * HZ;
d1a890fa
SB		 2998
2999 INIT_WORK(&adapter->work, vmxnet3_reset_work);
3000
09c5088e
SB		 3001 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3002 int i;
3003 for (i = 0; i < adapter->num_rx_queues; i++) {
3004 netif_napi_add(adapter->netdev,
3005 &adapter->rx_queue[i].napi,
3006 vmxnet3_poll_rx_only, 64);
3007 }
3008 } else {
3009 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3010 vmxnet3_poll, 64);
3011 }
3012
3013 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3014 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3015
d1a890fa
SB		 3016 SET_NETDEV_DEV(netdev, &pdev->dev);
3017 err = register_netdev(netdev);
3018
3019 if (err) {
3020 printk(KERN_ERR "Failed to register adapter %s\n",
3021 pci_name(pdev));
3022 goto err_register;
3023 }
3024
3025 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
4a1745fc 3026 vmxnet3_check_link(adapter, false);
d1a890fa
SB		 3027 atomic_inc(&devices_found);
3028 return 0;
3029
3030err_register:
3031 vmxnet3_free_intr_resources(adapter);
3032err_ver:
3033 vmxnet3_free_pci_resources(adapter);
3034err_alloc_pci:
09c5088e
SB		 3035#ifdef VMXNET3_RSS
3036 kfree(adapter->rss_conf);
3037err_alloc_rss:
3038#endif
d1a890fa
SB		 3039 kfree(adapter->pm_conf);
3040err_alloc_pm:
09c5088e
SB		 3041 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3042 adapter->queue_desc_pa);
d1a890fa
SB		 3043err_alloc_queue_desc:
3044 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3045 adapter->shared, adapter->shared_pa);
3046err_alloc_shared:
3047 pci_set_drvdata(pdev, NULL);
3048 free_netdev(netdev);
3049 return err;
3050}
3051
3052
3053static void __devexit
3054vmxnet3_remove_device(struct pci_dev *pdev)
3055{
3056 struct net_device *netdev = pci_get_drvdata(pdev);
3057 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
09c5088e
SB		 3058 int size = 0;
3059 int num_rx_queues;
3060
3061#ifdef VMXNET3_RSS
3062 if (enable_mq)
3063 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3064 (int)num_online_cpus());
3065 else
3066#endif
3067 num_rx_queues = 1;
d1a890fa 3068
23f333a2 3069 cancel_work_sync(&adapter->work);
d1a890fa
SB		 3070
3071 unregister_netdev(netdev);
3072
3073 vmxnet3_free_intr_resources(adapter);
3074 vmxnet3_free_pci_resources(adapter);
09c5088e
SB		 3075#ifdef VMXNET3_RSS
3076 kfree(adapter->rss_conf);
3077#endif
d1a890fa 3078 kfree(adapter->pm_conf);
09c5088e
SB		 3079
3080 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3081 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3082 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3083 adapter->queue_desc_pa);
d1a890fa
SB		 3084 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3085 adapter->shared, adapter->shared_pa);
3086 free_netdev(netdev);
3087}
3088
3089
3090#ifdef CONFIG_PM
3091
3092static int
3093vmxnet3_suspend(struct device *device)
3094{
3095 struct pci_dev *pdev = to_pci_dev(device);
3096 struct net_device *netdev = pci_get_drvdata(pdev);
3097 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3098 struct Vmxnet3_PMConf *pmConf;
3099 struct ethhdr *ehdr;
3100 struct arphdr *ahdr;
3101 u8 *arpreq;
3102 struct in_device *in_dev;
3103 struct in_ifaddr *ifa;
3104 int i = 0;
3105
3106 if (!netif_running(netdev))
3107 return 0;
3108
3109 vmxnet3_disable_all_intrs(adapter);
3110 vmxnet3_free_irqs(adapter);
3111 vmxnet3_free_intr_resources(adapter);
3112
3113 netif_device_detach(netdev);
09c5088e 3114 netif_tx_stop_all_queues(netdev);
d1a890fa
SB		 3115
3116 /* Create wake-up filters. */
3117 pmConf = adapter->pm_conf;
3118 memset(pmConf, 0, sizeof(*pmConf));
3119
3120 if (adapter->wol & WAKE_UCAST) {
3121 pmConf->filters[i].patternSize = ETH_ALEN;
3122 pmConf->filters[i].maskSize = 1;
3123 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3124 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3125
3843e515 3126 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3127 i++;
3128 }
3129
3130 if (adapter->wol & WAKE_ARP) {
3131 in_dev = in_dev_get(netdev);
3132 if (!in_dev)
3133 goto skip_arp;
3134
3135 ifa = (struct in_ifaddr *)in_dev->ifa_list;
3136 if (!ifa)
3137 goto skip_arp;
3138
3139 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3140 sizeof(struct arphdr) + /* ARP header */
3141 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3142 2 * sizeof(u32); /*2 IPv4 addresses */
3143 pmConf->filters[i].maskSize =
3144 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3145
3146 /* ETH_P_ARP in Ethernet header. */
3147 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3148 ehdr->h_proto = htons(ETH_P_ARP);
3149
3150 /* ARPOP_REQUEST in ARP header. */
3151 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3152 ahdr->ar_op = htons(ARPOP_REQUEST);
3153 arpreq = (u8 *)(ahdr + 1);
3154
3155 /* The Unicast IPv4 address in 'tip' field. */
3156 arpreq += 2 * ETH_ALEN + sizeof(u32);
3157 *(u32 *)arpreq = ifa->ifa_address;
3158
3159 /* The mask for the relevant bits. */
3160 pmConf->filters[i].mask[0] = 0x00;
3161 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3162 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3163 pmConf->filters[i].mask[3] = 0x00;
3164 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3165 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3166 in_dev_put(in_dev);
3167
3843e515 3168 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3169 i++;
3170 }
3171
3172skip_arp:
3173 if (adapter->wol & WAKE_MAGIC)
3843e515 3174 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
d1a890fa
SB		 3175
3176 pmConf->numFilters = i;
3177
115924b6
SB		 3178 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3179 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3180 *pmConf));
3181 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
3182 pmConf));
d1a890fa
SB		 3183
3184 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3185 VMXNET3_CMD_UPDATE_PMCFG);
3186
3187 pci_save_state(pdev);
3188 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3189 adapter->wol);
3190 pci_disable_device(pdev);
3191 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3192
3193 return 0;
3194}
3195
3196
3197static int
3198vmxnet3_resume(struct device *device)
3199{
3200 int err;
3201 struct pci_dev *pdev = to_pci_dev(device);
3202 struct net_device *netdev = pci_get_drvdata(pdev);
3203 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3204 struct Vmxnet3_PMConf *pmConf;
3205
3206 if (!netif_running(netdev))
3207 return 0;
3208
3209 /* Destroy wake-up filters. */
3210 pmConf = adapter->pm_conf;
3211 memset(pmConf, 0, sizeof(*pmConf));
3212
115924b6
SB		 3213 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3214 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3215 *pmConf));
0561cf3d 3216 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
115924b6 3217 pmConf));
d1a890fa
SB		 3218
3219 netif_device_attach(netdev);
3220 pci_set_power_state(pdev, PCI_D0);
3221 pci_restore_state(pdev);
3222 err = pci_enable_device_mem(pdev);
3223 if (err != 0)
3224 return err;
3225
3226 pci_enable_wake(pdev, PCI_D0, 0);
3227
3228 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3229 VMXNET3_CMD_UPDATE_PMCFG);
3230 vmxnet3_alloc_intr_resources(adapter);
3231 vmxnet3_request_irqs(adapter);
3232 vmxnet3_enable_all_intrs(adapter);
3233
3234 return 0;
3235}
3236
47145210 3237static const struct dev_pm_ops vmxnet3_pm_ops = {
d1a890fa
SB		 3238 .suspend = vmxnet3_suspend,
3239 .resume = vmxnet3_resume,
3240};
3241#endif
3242
3243static struct pci_driver vmxnet3_driver = {
3244 .name = vmxnet3_driver_name,
3245 .id_table = vmxnet3_pciid_table,
3246 .probe = vmxnet3_probe_device,
3247 .remove = __devexit_p(vmxnet3_remove_device),
3248#ifdef CONFIG_PM
3249 .driver.pm = &vmxnet3_pm_ops,
3250#endif
3251};
3252
3253
3254static int __init
3255vmxnet3_init_module(void)
3256{
3257 printk(KERN_INFO "%s - version %s\n", VMXNET3_DRIVER_DESC,
3258 VMXNET3_DRIVER_VERSION_REPORT);
3259 return pci_register_driver(&vmxnet3_driver);
3260}
3261
3262module_init(vmxnet3_init_module);
3263
3264
3265static void
3266vmxnet3_exit_module(void)
3267{
3268 pci_unregister_driver(&vmxnet3_driver);
3269}
3270
3271module_exit(vmxnet3_exit_module);
3272
3273MODULE_AUTHOR("VMware, Inc.");
3274MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3275MODULE_LICENSE("GPL v2");
3276MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
Linux 6.x block layer and io_uring tree(s)