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1da177e4 LT |
1 | /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */ |
2 | /* | |
3 | Written 1998-2001 by Donald Becker. | |
4 | ||
5 | Current Maintainer: Roger Luethi <rl@hellgate.ch> | |
6 | ||
7 | This software may be used and distributed according to the terms of | |
8 | the GNU General Public License (GPL), incorporated herein by reference. | |
9 | Drivers based on or derived from this code fall under the GPL and must | |
10 | retain the authorship, copyright and license notice. This file is not | |
11 | a complete program and may only be used when the entire operating | |
12 | system is licensed under the GPL. | |
13 | ||
14 | This driver is designed for the VIA VT86C100A Rhine-I. | |
15 | It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM | |
16 | and management NIC 6105M). | |
17 | ||
18 | The author may be reached as becker@scyld.com, or C/O | |
19 | Scyld Computing Corporation | |
20 | 410 Severn Ave., Suite 210 | |
21 | Annapolis MD 21403 | |
22 | ||
23 | ||
24 | This driver contains some changes from the original Donald Becker | |
25 | version. He may or may not be interested in bug reports on this | |
26 | code. You can find his versions at: | |
27 | http://www.scyld.com/network/via-rhine.html | |
03a8c661 | 28 | [link no longer provides useful info -jgarzik] |
1da177e4 LT |
29 | |
30 | */ | |
31 | ||
32 | #define DRV_NAME "via-rhine" | |
e84df485 RL |
33 | #define DRV_VERSION "1.4.3" |
34 | #define DRV_RELDATE "2007-03-06" | |
1da177e4 LT |
35 | |
36 | ||
37 | /* A few user-configurable values. | |
38 | These may be modified when a driver module is loaded. */ | |
39 | ||
40 | static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
41 | static int max_interrupt_work = 20; | |
42 | ||
43 | /* Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
44 | Setting to > 1518 effectively disables this feature. */ | |
45 | static int rx_copybreak; | |
46 | ||
b933b4d9 RL |
47 | /* Work-around for broken BIOSes: they are unable to get the chip back out of |
48 | power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */ | |
49 | static int avoid_D3; | |
50 | ||
1da177e4 LT |
51 | /* |
52 | * In case you are looking for 'options[]' or 'full_duplex[]', they | |
53 | * are gone. Use ethtool(8) instead. | |
54 | */ | |
55 | ||
56 | /* Maximum number of multicast addresses to filter (vs. rx-all-multicast). | |
57 | The Rhine has a 64 element 8390-like hash table. */ | |
58 | static const int multicast_filter_limit = 32; | |
59 | ||
60 | ||
61 | /* Operational parameters that are set at compile time. */ | |
62 | ||
63 | /* Keep the ring sizes a power of two for compile efficiency. | |
64 | The compiler will convert <unsigned>'%'<2^N> into a bit mask. | |
65 | Making the Tx ring too large decreases the effectiveness of channel | |
66 | bonding and packet priority. | |
67 | There are no ill effects from too-large receive rings. */ | |
68 | #define TX_RING_SIZE 16 | |
69 | #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */ | |
633949a1 RL |
70 | #ifdef CONFIG_VIA_RHINE_NAPI |
71 | #define RX_RING_SIZE 64 | |
72 | #else | |
1da177e4 | 73 | #define RX_RING_SIZE 16 |
633949a1 | 74 | #endif |
1da177e4 LT |
75 | |
76 | ||
77 | /* Operational parameters that usually are not changed. */ | |
78 | ||
79 | /* Time in jiffies before concluding the transmitter is hung. */ | |
80 | #define TX_TIMEOUT (2*HZ) | |
81 | ||
82 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
83 | ||
84 | #include <linux/module.h> | |
85 | #include <linux/moduleparam.h> | |
86 | #include <linux/kernel.h> | |
87 | #include <linux/string.h> | |
88 | #include <linux/timer.h> | |
89 | #include <linux/errno.h> | |
90 | #include <linux/ioport.h> | |
91 | #include <linux/slab.h> | |
92 | #include <linux/interrupt.h> | |
93 | #include <linux/pci.h> | |
1e7f0bd8 | 94 | #include <linux/dma-mapping.h> |
1da177e4 LT |
95 | #include <linux/netdevice.h> |
96 | #include <linux/etherdevice.h> | |
97 | #include <linux/skbuff.h> | |
98 | #include <linux/init.h> | |
99 | #include <linux/delay.h> | |
100 | #include <linux/mii.h> | |
101 | #include <linux/ethtool.h> | |
102 | #include <linux/crc32.h> | |
103 | #include <linux/bitops.h> | |
104 | #include <asm/processor.h> /* Processor type for cache alignment. */ | |
105 | #include <asm/io.h> | |
106 | #include <asm/irq.h> | |
107 | #include <asm/uaccess.h> | |
e84df485 | 108 | #include <linux/dmi.h> |
1da177e4 LT |
109 | |
110 | /* These identify the driver base version and may not be removed. */ | |
111 | static char version[] __devinitdata = | |
112 | KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n"; | |
113 | ||
114 | /* This driver was written to use PCI memory space. Some early versions | |
115 | of the Rhine may only work correctly with I/O space accesses. */ | |
116 | #ifdef CONFIG_VIA_RHINE_MMIO | |
117 | #define USE_MMIO | |
118 | #else | |
119 | #endif | |
120 | ||
121 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
122 | MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver"); | |
123 | MODULE_LICENSE("GPL"); | |
124 | ||
125 | module_param(max_interrupt_work, int, 0); | |
126 | module_param(debug, int, 0); | |
127 | module_param(rx_copybreak, int, 0); | |
b933b4d9 | 128 | module_param(avoid_D3, bool, 0); |
1da177e4 LT |
129 | MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt"); |
130 | MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)"); | |
131 | MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames"); | |
b933b4d9 | 132 | MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)"); |
1da177e4 LT |
133 | |
134 | /* | |
135 | Theory of Operation | |
136 | ||
137 | I. Board Compatibility | |
138 | ||
139 | This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet | |
140 | controller. | |
141 | ||
142 | II. Board-specific settings | |
143 | ||
144 | Boards with this chip are functional only in a bus-master PCI slot. | |
145 | ||
146 | Many operational settings are loaded from the EEPROM to the Config word at | |
147 | offset 0x78. For most of these settings, this driver assumes that they are | |
148 | correct. | |
149 | If this driver is compiled to use PCI memory space operations the EEPROM | |
150 | must be configured to enable memory ops. | |
151 | ||
152 | III. Driver operation | |
153 | ||
154 | IIIa. Ring buffers | |
155 | ||
156 | This driver uses two statically allocated fixed-size descriptor lists | |
157 | formed into rings by a branch from the final descriptor to the beginning of | |
158 | the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. | |
159 | ||
160 | IIIb/c. Transmit/Receive Structure | |
161 | ||
162 | This driver attempts to use a zero-copy receive and transmit scheme. | |
163 | ||
164 | Alas, all data buffers are required to start on a 32 bit boundary, so | |
165 | the driver must often copy transmit packets into bounce buffers. | |
166 | ||
167 | The driver allocates full frame size skbuffs for the Rx ring buffers at | |
168 | open() time and passes the skb->data field to the chip as receive data | |
169 | buffers. When an incoming frame is less than RX_COPYBREAK bytes long, | |
170 | a fresh skbuff is allocated and the frame is copied to the new skbuff. | |
171 | When the incoming frame is larger, the skbuff is passed directly up the | |
172 | protocol stack. Buffers consumed this way are replaced by newly allocated | |
173 | skbuffs in the last phase of rhine_rx(). | |
174 | ||
175 | The RX_COPYBREAK value is chosen to trade-off the memory wasted by | |
176 | using a full-sized skbuff for small frames vs. the copying costs of larger | |
177 | frames. New boards are typically used in generously configured machines | |
178 | and the underfilled buffers have negligible impact compared to the benefit of | |
179 | a single allocation size, so the default value of zero results in never | |
180 | copying packets. When copying is done, the cost is usually mitigated by using | |
181 | a combined copy/checksum routine. Copying also preloads the cache, which is | |
182 | most useful with small frames. | |
183 | ||
184 | Since the VIA chips are only able to transfer data to buffers on 32 bit | |
185 | boundaries, the IP header at offset 14 in an ethernet frame isn't | |
186 | longword aligned for further processing. Copying these unaligned buffers | |
187 | has the beneficial effect of 16-byte aligning the IP header. | |
188 | ||
189 | IIId. Synchronization | |
190 | ||
191 | The driver runs as two independent, single-threaded flows of control. One | |
192 | is the send-packet routine, which enforces single-threaded use by the | |
193 | dev->priv->lock spinlock. The other thread is the interrupt handler, which | |
194 | is single threaded by the hardware and interrupt handling software. | |
195 | ||
196 | The send packet thread has partial control over the Tx ring. It locks the | |
197 | dev->priv->lock whenever it's queuing a Tx packet. If the next slot in the ring | |
198 | is not available it stops the transmit queue by calling netif_stop_queue. | |
199 | ||
200 | The interrupt handler has exclusive control over the Rx ring and records stats | |
201 | from the Tx ring. After reaping the stats, it marks the Tx queue entry as | |
202 | empty by incrementing the dirty_tx mark. If at least half of the entries in | |
203 | the Rx ring are available the transmit queue is woken up if it was stopped. | |
204 | ||
205 | IV. Notes | |
206 | ||
207 | IVb. References | |
208 | ||
209 | Preliminary VT86C100A manual from http://www.via.com.tw/ | |
210 | http://www.scyld.com/expert/100mbps.html | |
211 | http://www.scyld.com/expert/NWay.html | |
212 | ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf | |
213 | ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF | |
214 | ||
215 | ||
216 | IVc. Errata | |
217 | ||
218 | The VT86C100A manual is not reliable information. | |
219 | The 3043 chip does not handle unaligned transmit or receive buffers, resulting | |
220 | in significant performance degradation for bounce buffer copies on transmit | |
221 | and unaligned IP headers on receive. | |
222 | The chip does not pad to minimum transmit length. | |
223 | ||
224 | */ | |
225 | ||
226 | ||
227 | /* This table drives the PCI probe routines. It's mostly boilerplate in all | |
228 | of the drivers, and will likely be provided by some future kernel. | |
229 | Note the matching code -- the first table entry matchs all 56** cards but | |
230 | second only the 1234 card. | |
231 | */ | |
232 | ||
233 | enum rhine_revs { | |
234 | VT86C100A = 0x00, | |
235 | VTunknown0 = 0x20, | |
236 | VT6102 = 0x40, | |
237 | VT8231 = 0x50, /* Integrated MAC */ | |
238 | VT8233 = 0x60, /* Integrated MAC */ | |
239 | VT8235 = 0x74, /* Integrated MAC */ | |
240 | VT8237 = 0x78, /* Integrated MAC */ | |
241 | VTunknown1 = 0x7C, | |
242 | VT6105 = 0x80, | |
243 | VT6105_B0 = 0x83, | |
244 | VT6105L = 0x8A, | |
245 | VT6107 = 0x8C, | |
246 | VTunknown2 = 0x8E, | |
247 | VT6105M = 0x90, /* Management adapter */ | |
248 | }; | |
249 | ||
250 | enum rhine_quirks { | |
251 | rqWOL = 0x0001, /* Wake-On-LAN support */ | |
252 | rqForceReset = 0x0002, | |
253 | rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */ | |
254 | rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */ | |
255 | rqRhineI = 0x0100, /* See comment below */ | |
256 | }; | |
257 | /* | |
258 | * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable | |
259 | * MMIO as well as for the collision counter and the Tx FIFO underflow | |
260 | * indicator. In addition, Tx and Rx buffers need to 4 byte aligned. | |
261 | */ | |
262 | ||
263 | /* Beware of PCI posted writes */ | |
264 | #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0) | |
265 | ||
46009c8b JG |
266 | static const struct pci_device_id rhine_pci_tbl[] = { |
267 | { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */ | |
268 | { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */ | |
269 | { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */ | |
270 | { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */ | |
1da177e4 LT |
271 | { } /* terminate list */ |
272 | }; | |
273 | MODULE_DEVICE_TABLE(pci, rhine_pci_tbl); | |
274 | ||
275 | ||
276 | /* Offsets to the device registers. */ | |
277 | enum register_offsets { | |
278 | StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08, | |
279 | ChipCmd1=0x09, | |
280 | IntrStatus=0x0C, IntrEnable=0x0E, | |
281 | MulticastFilter0=0x10, MulticastFilter1=0x14, | |
282 | RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54, | |
283 | MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, | |
284 | MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74, | |
285 | ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B, | |
286 | RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81, | |
287 | StickyHW=0x83, IntrStatus2=0x84, | |
288 | WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4, | |
289 | WOLcrClr1=0xA6, WOLcgClr=0xA7, | |
290 | PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD, | |
291 | }; | |
292 | ||
293 | /* Bits in ConfigD */ | |
294 | enum backoff_bits { | |
295 | BackOptional=0x01, BackModify=0x02, | |
296 | BackCaptureEffect=0x04, BackRandom=0x08 | |
297 | }; | |
298 | ||
299 | #ifdef USE_MMIO | |
300 | /* Registers we check that mmio and reg are the same. */ | |
301 | static const int mmio_verify_registers[] = { | |
302 | RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD, | |
303 | 0 | |
304 | }; | |
305 | #endif | |
306 | ||
307 | /* Bits in the interrupt status/mask registers. */ | |
308 | enum intr_status_bits { | |
309 | IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020, | |
310 | IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210, | |
311 | IntrPCIErr=0x0040, | |
312 | IntrStatsMax=0x0080, IntrRxEarly=0x0100, | |
313 | IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000, | |
314 | IntrTxAborted=0x2000, IntrLinkChange=0x4000, | |
315 | IntrRxWakeUp=0x8000, | |
316 | IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260, | |
317 | IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */ | |
318 | IntrTxErrSummary=0x082218, | |
319 | }; | |
320 | ||
321 | /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */ | |
322 | enum wol_bits { | |
323 | WOLucast = 0x10, | |
324 | WOLmagic = 0x20, | |
325 | WOLbmcast = 0x30, | |
326 | WOLlnkon = 0x40, | |
327 | WOLlnkoff = 0x80, | |
328 | }; | |
329 | ||
330 | /* The Rx and Tx buffer descriptors. */ | |
331 | struct rx_desc { | |
332 | s32 rx_status; | |
333 | u32 desc_length; /* Chain flag, Buffer/frame length */ | |
334 | u32 addr; | |
335 | u32 next_desc; | |
336 | }; | |
337 | struct tx_desc { | |
338 | s32 tx_status; | |
339 | u32 desc_length; /* Chain flag, Tx Config, Frame length */ | |
340 | u32 addr; | |
341 | u32 next_desc; | |
342 | }; | |
343 | ||
344 | /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */ | |
345 | #define TXDESC 0x00e08000 | |
346 | ||
347 | enum rx_status_bits { | |
348 | RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F | |
349 | }; | |
350 | ||
351 | /* Bits in *_desc.*_status */ | |
352 | enum desc_status_bits { | |
353 | DescOwn=0x80000000 | |
354 | }; | |
355 | ||
356 | /* Bits in ChipCmd. */ | |
357 | enum chip_cmd_bits { | |
358 | CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08, | |
359 | CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40, | |
360 | Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04, | |
361 | Cmd1NoTxPoll=0x08, Cmd1Reset=0x80, | |
362 | }; | |
363 | ||
364 | struct rhine_private { | |
365 | /* Descriptor rings */ | |
366 | struct rx_desc *rx_ring; | |
367 | struct tx_desc *tx_ring; | |
368 | dma_addr_t rx_ring_dma; | |
369 | dma_addr_t tx_ring_dma; | |
370 | ||
371 | /* The addresses of receive-in-place skbuffs. */ | |
372 | struct sk_buff *rx_skbuff[RX_RING_SIZE]; | |
373 | dma_addr_t rx_skbuff_dma[RX_RING_SIZE]; | |
374 | ||
375 | /* The saved address of a sent-in-place packet/buffer, for later free(). */ | |
376 | struct sk_buff *tx_skbuff[TX_RING_SIZE]; | |
377 | dma_addr_t tx_skbuff_dma[TX_RING_SIZE]; | |
378 | ||
4be5de25 | 379 | /* Tx bounce buffers (Rhine-I only) */ |
1da177e4 LT |
380 | unsigned char *tx_buf[TX_RING_SIZE]; |
381 | unsigned char *tx_bufs; | |
382 | dma_addr_t tx_bufs_dma; | |
383 | ||
384 | struct pci_dev *pdev; | |
385 | long pioaddr; | |
386 | struct net_device_stats stats; | |
387 | spinlock_t lock; | |
388 | ||
389 | /* Frequently used values: keep some adjacent for cache effect. */ | |
390 | u32 quirks; | |
391 | struct rx_desc *rx_head_desc; | |
392 | unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ | |
393 | unsigned int cur_tx, dirty_tx; | |
394 | unsigned int rx_buf_sz; /* Based on MTU+slack. */ | |
395 | u8 wolopts; | |
396 | ||
397 | u8 tx_thresh, rx_thresh; | |
398 | ||
399 | struct mii_if_info mii_if; | |
400 | void __iomem *base; | |
401 | }; | |
402 | ||
403 | static int mdio_read(struct net_device *dev, int phy_id, int location); | |
404 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value); | |
405 | static int rhine_open(struct net_device *dev); | |
406 | static void rhine_tx_timeout(struct net_device *dev); | |
407 | static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev); | |
7d12e780 | 408 | static irqreturn_t rhine_interrupt(int irq, void *dev_instance); |
1da177e4 | 409 | static void rhine_tx(struct net_device *dev); |
633949a1 | 410 | static int rhine_rx(struct net_device *dev, int limit); |
1da177e4 LT |
411 | static void rhine_error(struct net_device *dev, int intr_status); |
412 | static void rhine_set_rx_mode(struct net_device *dev); | |
413 | static struct net_device_stats *rhine_get_stats(struct net_device *dev); | |
414 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
7282d491 | 415 | static const struct ethtool_ops netdev_ethtool_ops; |
1da177e4 | 416 | static int rhine_close(struct net_device *dev); |
d18c3db5 | 417 | static void rhine_shutdown (struct pci_dev *pdev); |
1da177e4 LT |
418 | |
419 | #define RHINE_WAIT_FOR(condition) do { \ | |
420 | int i=1024; \ | |
421 | while (!(condition) && --i) \ | |
422 | ; \ | |
423 | if (debug > 1 && i < 512) \ | |
424 | printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \ | |
425 | DRV_NAME, 1024-i, __func__, __LINE__); \ | |
426 | } while(0) | |
427 | ||
428 | static inline u32 get_intr_status(struct net_device *dev) | |
429 | { | |
430 | struct rhine_private *rp = netdev_priv(dev); | |
431 | void __iomem *ioaddr = rp->base; | |
432 | u32 intr_status; | |
433 | ||
434 | intr_status = ioread16(ioaddr + IntrStatus); | |
435 | /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */ | |
436 | if (rp->quirks & rqStatusWBRace) | |
437 | intr_status |= ioread8(ioaddr + IntrStatus2) << 16; | |
438 | return intr_status; | |
439 | } | |
440 | ||
441 | /* | |
442 | * Get power related registers into sane state. | |
443 | * Notify user about past WOL event. | |
444 | */ | |
445 | static void rhine_power_init(struct net_device *dev) | |
446 | { | |
447 | struct rhine_private *rp = netdev_priv(dev); | |
448 | void __iomem *ioaddr = rp->base; | |
449 | u16 wolstat; | |
450 | ||
451 | if (rp->quirks & rqWOL) { | |
452 | /* Make sure chip is in power state D0 */ | |
453 | iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW); | |
454 | ||
455 | /* Disable "force PME-enable" */ | |
456 | iowrite8(0x80, ioaddr + WOLcgClr); | |
457 | ||
458 | /* Clear power-event config bits (WOL) */ | |
459 | iowrite8(0xFF, ioaddr + WOLcrClr); | |
460 | /* More recent cards can manage two additional patterns */ | |
461 | if (rp->quirks & rq6patterns) | |
462 | iowrite8(0x03, ioaddr + WOLcrClr1); | |
463 | ||
464 | /* Save power-event status bits */ | |
465 | wolstat = ioread8(ioaddr + PwrcsrSet); | |
466 | if (rp->quirks & rq6patterns) | |
467 | wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8; | |
468 | ||
469 | /* Clear power-event status bits */ | |
470 | iowrite8(0xFF, ioaddr + PwrcsrClr); | |
471 | if (rp->quirks & rq6patterns) | |
472 | iowrite8(0x03, ioaddr + PwrcsrClr1); | |
473 | ||
474 | if (wolstat) { | |
475 | char *reason; | |
476 | switch (wolstat) { | |
477 | case WOLmagic: | |
478 | reason = "Magic packet"; | |
479 | break; | |
480 | case WOLlnkon: | |
481 | reason = "Link went up"; | |
482 | break; | |
483 | case WOLlnkoff: | |
484 | reason = "Link went down"; | |
485 | break; | |
486 | case WOLucast: | |
487 | reason = "Unicast packet"; | |
488 | break; | |
489 | case WOLbmcast: | |
490 | reason = "Multicast/broadcast packet"; | |
491 | break; | |
492 | default: | |
493 | reason = "Unknown"; | |
494 | } | |
495 | printk(KERN_INFO "%s: Woke system up. Reason: %s.\n", | |
496 | DRV_NAME, reason); | |
497 | } | |
498 | } | |
499 | } | |
500 | ||
501 | static void rhine_chip_reset(struct net_device *dev) | |
502 | { | |
503 | struct rhine_private *rp = netdev_priv(dev); | |
504 | void __iomem *ioaddr = rp->base; | |
505 | ||
506 | iowrite8(Cmd1Reset, ioaddr + ChipCmd1); | |
507 | IOSYNC; | |
508 | ||
509 | if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) { | |
510 | printk(KERN_INFO "%s: Reset not complete yet. " | |
511 | "Trying harder.\n", DRV_NAME); | |
512 | ||
513 | /* Force reset */ | |
514 | if (rp->quirks & rqForceReset) | |
515 | iowrite8(0x40, ioaddr + MiscCmd); | |
516 | ||
517 | /* Reset can take somewhat longer (rare) */ | |
518 | RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset)); | |
519 | } | |
520 | ||
521 | if (debug > 1) | |
522 | printk(KERN_INFO "%s: Reset %s.\n", dev->name, | |
523 | (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ? | |
524 | "failed" : "succeeded"); | |
525 | } | |
526 | ||
527 | #ifdef USE_MMIO | |
528 | static void enable_mmio(long pioaddr, u32 quirks) | |
529 | { | |
530 | int n; | |
531 | if (quirks & rqRhineI) { | |
532 | /* More recent docs say that this bit is reserved ... */ | |
533 | n = inb(pioaddr + ConfigA) | 0x20; | |
534 | outb(n, pioaddr + ConfigA); | |
535 | } else { | |
536 | n = inb(pioaddr + ConfigD) | 0x80; | |
537 | outb(n, pioaddr + ConfigD); | |
538 | } | |
539 | } | |
540 | #endif | |
541 | ||
542 | /* | |
543 | * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM | |
544 | * (plus 0x6C for Rhine-I/II) | |
545 | */ | |
546 | static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev) | |
547 | { | |
548 | struct rhine_private *rp = netdev_priv(dev); | |
549 | void __iomem *ioaddr = rp->base; | |
550 | ||
551 | outb(0x20, pioaddr + MACRegEEcsr); | |
552 | RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20)); | |
553 | ||
554 | #ifdef USE_MMIO | |
555 | /* | |
556 | * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable | |
557 | * MMIO. If reloading EEPROM was done first this could be avoided, but | |
558 | * it is not known if that still works with the "win98-reboot" problem. | |
559 | */ | |
560 | enable_mmio(pioaddr, rp->quirks); | |
561 | #endif | |
562 | ||
563 | /* Turn off EEPROM-controlled wake-up (magic packet) */ | |
564 | if (rp->quirks & rqWOL) | |
565 | iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA); | |
566 | ||
567 | } | |
568 | ||
569 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
570 | static void rhine_poll(struct net_device *dev) | |
571 | { | |
572 | disable_irq(dev->irq); | |
7d12e780 | 573 | rhine_interrupt(dev->irq, (void *)dev); |
1da177e4 LT |
574 | enable_irq(dev->irq); |
575 | } | |
576 | #endif | |
577 | ||
633949a1 RL |
578 | #ifdef CONFIG_VIA_RHINE_NAPI |
579 | static int rhine_napipoll(struct net_device *dev, int *budget) | |
580 | { | |
581 | struct rhine_private *rp = netdev_priv(dev); | |
582 | void __iomem *ioaddr = rp->base; | |
583 | int done, limit = min(dev->quota, *budget); | |
584 | ||
585 | done = rhine_rx(dev, limit); | |
586 | *budget -= done; | |
587 | dev->quota -= done; | |
588 | ||
589 | if (done < limit) { | |
590 | netif_rx_complete(dev); | |
591 | ||
592 | iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow | | |
593 | IntrRxDropped | IntrRxNoBuf | IntrTxAborted | | |
594 | IntrTxDone | IntrTxError | IntrTxUnderrun | | |
595 | IntrPCIErr | IntrStatsMax | IntrLinkChange, | |
596 | ioaddr + IntrEnable); | |
597 | return 0; | |
598 | } | |
599 | else | |
600 | return 1; | |
601 | } | |
602 | #endif | |
603 | ||
1da177e4 LT |
604 | static void rhine_hw_init(struct net_device *dev, long pioaddr) |
605 | { | |
606 | struct rhine_private *rp = netdev_priv(dev); | |
607 | ||
608 | /* Reset the chip to erase previous misconfiguration. */ | |
609 | rhine_chip_reset(dev); | |
610 | ||
611 | /* Rhine-I needs extra time to recuperate before EEPROM reload */ | |
612 | if (rp->quirks & rqRhineI) | |
613 | msleep(5); | |
614 | ||
615 | /* Reload EEPROM controlled bytes cleared by soft reset */ | |
616 | rhine_reload_eeprom(pioaddr, dev); | |
617 | } | |
618 | ||
619 | static int __devinit rhine_init_one(struct pci_dev *pdev, | |
620 | const struct pci_device_id *ent) | |
621 | { | |
622 | struct net_device *dev; | |
623 | struct rhine_private *rp; | |
624 | int i, rc; | |
625 | u8 pci_rev; | |
626 | u32 quirks; | |
627 | long pioaddr; | |
628 | long memaddr; | |
629 | void __iomem *ioaddr; | |
630 | int io_size, phy_id; | |
631 | const char *name; | |
632 | #ifdef USE_MMIO | |
633 | int bar = 1; | |
634 | #else | |
635 | int bar = 0; | |
636 | #endif | |
637 | ||
638 | /* when built into the kernel, we only print version if device is found */ | |
639 | #ifndef MODULE | |
640 | static int printed_version; | |
641 | if (!printed_version++) | |
642 | printk(version); | |
643 | #endif | |
644 | ||
645 | pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev); | |
646 | ||
647 | io_size = 256; | |
648 | phy_id = 0; | |
649 | quirks = 0; | |
650 | name = "Rhine"; | |
651 | if (pci_rev < VTunknown0) { | |
652 | quirks = rqRhineI; | |
653 | io_size = 128; | |
654 | } | |
655 | else if (pci_rev >= VT6102) { | |
656 | quirks = rqWOL | rqForceReset; | |
657 | if (pci_rev < VT6105) { | |
658 | name = "Rhine II"; | |
659 | quirks |= rqStatusWBRace; /* Rhine-II exclusive */ | |
660 | } | |
661 | else { | |
662 | phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */ | |
663 | if (pci_rev >= VT6105_B0) | |
664 | quirks |= rq6patterns; | |
665 | if (pci_rev < VT6105M) | |
666 | name = "Rhine III"; | |
667 | else | |
668 | name = "Rhine III (Management Adapter)"; | |
669 | } | |
670 | } | |
671 | ||
672 | rc = pci_enable_device(pdev); | |
673 | if (rc) | |
674 | goto err_out; | |
675 | ||
676 | /* this should always be supported */ | |
1e7f0bd8 | 677 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
1da177e4 LT |
678 | if (rc) { |
679 | printk(KERN_ERR "32-bit PCI DMA addresses not supported by " | |
680 | "the card!?\n"); | |
681 | goto err_out; | |
682 | } | |
683 | ||
684 | /* sanity check */ | |
685 | if ((pci_resource_len(pdev, 0) < io_size) || | |
686 | (pci_resource_len(pdev, 1) < io_size)) { | |
687 | rc = -EIO; | |
688 | printk(KERN_ERR "Insufficient PCI resources, aborting\n"); | |
689 | goto err_out; | |
690 | } | |
691 | ||
692 | pioaddr = pci_resource_start(pdev, 0); | |
693 | memaddr = pci_resource_start(pdev, 1); | |
694 | ||
695 | pci_set_master(pdev); | |
696 | ||
697 | dev = alloc_etherdev(sizeof(struct rhine_private)); | |
698 | if (!dev) { | |
699 | rc = -ENOMEM; | |
700 | printk(KERN_ERR "alloc_etherdev failed\n"); | |
701 | goto err_out; | |
702 | } | |
703 | SET_MODULE_OWNER(dev); | |
704 | SET_NETDEV_DEV(dev, &pdev->dev); | |
705 | ||
706 | rp = netdev_priv(dev); | |
707 | rp->quirks = quirks; | |
708 | rp->pioaddr = pioaddr; | |
709 | rp->pdev = pdev; | |
710 | ||
711 | rc = pci_request_regions(pdev, DRV_NAME); | |
712 | if (rc) | |
713 | goto err_out_free_netdev; | |
714 | ||
715 | ioaddr = pci_iomap(pdev, bar, io_size); | |
716 | if (!ioaddr) { | |
717 | rc = -EIO; | |
718 | printk(KERN_ERR "ioremap failed for device %s, region 0x%X " | |
719 | "@ 0x%lX\n", pci_name(pdev), io_size, memaddr); | |
720 | goto err_out_free_res; | |
721 | } | |
722 | ||
723 | #ifdef USE_MMIO | |
724 | enable_mmio(pioaddr, quirks); | |
725 | ||
726 | /* Check that selected MMIO registers match the PIO ones */ | |
727 | i = 0; | |
728 | while (mmio_verify_registers[i]) { | |
729 | int reg = mmio_verify_registers[i++]; | |
730 | unsigned char a = inb(pioaddr+reg); | |
731 | unsigned char b = readb(ioaddr+reg); | |
732 | if (a != b) { | |
733 | rc = -EIO; | |
734 | printk(KERN_ERR "MMIO do not match PIO [%02x] " | |
735 | "(%02x != %02x)\n", reg, a, b); | |
736 | goto err_out_unmap; | |
737 | } | |
738 | } | |
739 | #endif /* USE_MMIO */ | |
740 | ||
741 | dev->base_addr = (unsigned long)ioaddr; | |
742 | rp->base = ioaddr; | |
743 | ||
744 | /* Get chip registers into a sane state */ | |
745 | rhine_power_init(dev); | |
746 | rhine_hw_init(dev, pioaddr); | |
747 | ||
748 | for (i = 0; i < 6; i++) | |
749 | dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i); | |
b81e8e1f | 750 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 751 | |
b81e8e1f | 752 | if (!is_valid_ether_addr(dev->perm_addr)) { |
1da177e4 LT |
753 | rc = -EIO; |
754 | printk(KERN_ERR "Invalid MAC address\n"); | |
755 | goto err_out_unmap; | |
756 | } | |
757 | ||
758 | /* For Rhine-I/II, phy_id is loaded from EEPROM */ | |
759 | if (!phy_id) | |
760 | phy_id = ioread8(ioaddr + 0x6C); | |
761 | ||
762 | dev->irq = pdev->irq; | |
763 | ||
764 | spin_lock_init(&rp->lock); | |
765 | rp->mii_if.dev = dev; | |
766 | rp->mii_if.mdio_read = mdio_read; | |
767 | rp->mii_if.mdio_write = mdio_write; | |
768 | rp->mii_if.phy_id_mask = 0x1f; | |
769 | rp->mii_if.reg_num_mask = 0x1f; | |
770 | ||
771 | /* The chip-specific entries in the device structure. */ | |
772 | dev->open = rhine_open; | |
773 | dev->hard_start_xmit = rhine_start_tx; | |
774 | dev->stop = rhine_close; | |
775 | dev->get_stats = rhine_get_stats; | |
776 | dev->set_multicast_list = rhine_set_rx_mode; | |
777 | dev->do_ioctl = netdev_ioctl; | |
778 | dev->ethtool_ops = &netdev_ethtool_ops; | |
779 | dev->tx_timeout = rhine_tx_timeout; | |
780 | dev->watchdog_timeo = TX_TIMEOUT; | |
781 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
782 | dev->poll_controller = rhine_poll; | |
633949a1 RL |
783 | #endif |
784 | #ifdef CONFIG_VIA_RHINE_NAPI | |
785 | dev->poll = rhine_napipoll; | |
786 | dev->weight = 64; | |
1da177e4 LT |
787 | #endif |
788 | if (rp->quirks & rqRhineI) | |
789 | dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM; | |
790 | ||
791 | /* dev->name not defined before register_netdev()! */ | |
792 | rc = register_netdev(dev); | |
793 | if (rc) | |
794 | goto err_out_unmap; | |
795 | ||
796 | printk(KERN_INFO "%s: VIA %s at 0x%lx, ", | |
797 | dev->name, name, | |
798 | #ifdef USE_MMIO | |
799 | memaddr | |
800 | #else | |
801 | (long)ioaddr | |
802 | #endif | |
803 | ); | |
804 | ||
805 | for (i = 0; i < 5; i++) | |
806 | printk("%2.2x:", dev->dev_addr[i]); | |
807 | printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], pdev->irq); | |
808 | ||
809 | pci_set_drvdata(pdev, dev); | |
810 | ||
811 | { | |
812 | u16 mii_cmd; | |
813 | int mii_status = mdio_read(dev, phy_id, 1); | |
814 | mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE; | |
815 | mdio_write(dev, phy_id, MII_BMCR, mii_cmd); | |
816 | if (mii_status != 0xffff && mii_status != 0x0000) { | |
817 | rp->mii_if.advertising = mdio_read(dev, phy_id, 4); | |
818 | printk(KERN_INFO "%s: MII PHY found at address " | |
819 | "%d, status 0x%4.4x advertising %4.4x " | |
820 | "Link %4.4x.\n", dev->name, phy_id, | |
821 | mii_status, rp->mii_if.advertising, | |
822 | mdio_read(dev, phy_id, 5)); | |
823 | ||
824 | /* set IFF_RUNNING */ | |
825 | if (mii_status & BMSR_LSTATUS) | |
826 | netif_carrier_on(dev); | |
827 | else | |
828 | netif_carrier_off(dev); | |
829 | ||
830 | } | |
831 | } | |
832 | rp->mii_if.phy_id = phy_id; | |
b933b4d9 RL |
833 | if (debug > 1 && avoid_D3) |
834 | printk(KERN_INFO "%s: No D3 power state at shutdown.\n", | |
835 | dev->name); | |
1da177e4 LT |
836 | |
837 | return 0; | |
838 | ||
839 | err_out_unmap: | |
840 | pci_iounmap(pdev, ioaddr); | |
841 | err_out_free_res: | |
842 | pci_release_regions(pdev); | |
843 | err_out_free_netdev: | |
844 | free_netdev(dev); | |
845 | err_out: | |
846 | return rc; | |
847 | } | |
848 | ||
849 | static int alloc_ring(struct net_device* dev) | |
850 | { | |
851 | struct rhine_private *rp = netdev_priv(dev); | |
852 | void *ring; | |
853 | dma_addr_t ring_dma; | |
854 | ||
855 | ring = pci_alloc_consistent(rp->pdev, | |
856 | RX_RING_SIZE * sizeof(struct rx_desc) + | |
857 | TX_RING_SIZE * sizeof(struct tx_desc), | |
858 | &ring_dma); | |
859 | if (!ring) { | |
860 | printk(KERN_ERR "Could not allocate DMA memory.\n"); | |
861 | return -ENOMEM; | |
862 | } | |
863 | if (rp->quirks & rqRhineI) { | |
864 | rp->tx_bufs = pci_alloc_consistent(rp->pdev, | |
865 | PKT_BUF_SZ * TX_RING_SIZE, | |
866 | &rp->tx_bufs_dma); | |
867 | if (rp->tx_bufs == NULL) { | |
868 | pci_free_consistent(rp->pdev, | |
869 | RX_RING_SIZE * sizeof(struct rx_desc) + | |
870 | TX_RING_SIZE * sizeof(struct tx_desc), | |
871 | ring, ring_dma); | |
872 | return -ENOMEM; | |
873 | } | |
874 | } | |
875 | ||
876 | rp->rx_ring = ring; | |
877 | rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc); | |
878 | rp->rx_ring_dma = ring_dma; | |
879 | rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc); | |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
884 | static void free_ring(struct net_device* dev) | |
885 | { | |
886 | struct rhine_private *rp = netdev_priv(dev); | |
887 | ||
888 | pci_free_consistent(rp->pdev, | |
889 | RX_RING_SIZE * sizeof(struct rx_desc) + | |
890 | TX_RING_SIZE * sizeof(struct tx_desc), | |
891 | rp->rx_ring, rp->rx_ring_dma); | |
892 | rp->tx_ring = NULL; | |
893 | ||
894 | if (rp->tx_bufs) | |
895 | pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE, | |
896 | rp->tx_bufs, rp->tx_bufs_dma); | |
897 | ||
898 | rp->tx_bufs = NULL; | |
899 | ||
900 | } | |
901 | ||
902 | static void alloc_rbufs(struct net_device *dev) | |
903 | { | |
904 | struct rhine_private *rp = netdev_priv(dev); | |
905 | dma_addr_t next; | |
906 | int i; | |
907 | ||
908 | rp->dirty_rx = rp->cur_rx = 0; | |
909 | ||
910 | rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); | |
911 | rp->rx_head_desc = &rp->rx_ring[0]; | |
912 | next = rp->rx_ring_dma; | |
913 | ||
914 | /* Init the ring entries */ | |
915 | for (i = 0; i < RX_RING_SIZE; i++) { | |
916 | rp->rx_ring[i].rx_status = 0; | |
917 | rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz); | |
918 | next += sizeof(struct rx_desc); | |
919 | rp->rx_ring[i].next_desc = cpu_to_le32(next); | |
920 | rp->rx_skbuff[i] = NULL; | |
921 | } | |
922 | /* Mark the last entry as wrapping the ring. */ | |
923 | rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma); | |
924 | ||
925 | /* Fill in the Rx buffers. Handle allocation failure gracefully. */ | |
926 | for (i = 0; i < RX_RING_SIZE; i++) { | |
927 | struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz); | |
928 | rp->rx_skbuff[i] = skb; | |
929 | if (skb == NULL) | |
930 | break; | |
931 | skb->dev = dev; /* Mark as being used by this device. */ | |
932 | ||
933 | rp->rx_skbuff_dma[i] = | |
689be439 | 934 | pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz, |
1da177e4 LT |
935 | PCI_DMA_FROMDEVICE); |
936 | ||
937 | rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]); | |
938 | rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn); | |
939 | } | |
940 | rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
941 | } | |
942 | ||
943 | static void free_rbufs(struct net_device* dev) | |
944 | { | |
945 | struct rhine_private *rp = netdev_priv(dev); | |
946 | int i; | |
947 | ||
948 | /* Free all the skbuffs in the Rx queue. */ | |
949 | for (i = 0; i < RX_RING_SIZE; i++) { | |
950 | rp->rx_ring[i].rx_status = 0; | |
951 | rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ | |
952 | if (rp->rx_skbuff[i]) { | |
953 | pci_unmap_single(rp->pdev, | |
954 | rp->rx_skbuff_dma[i], | |
955 | rp->rx_buf_sz, PCI_DMA_FROMDEVICE); | |
956 | dev_kfree_skb(rp->rx_skbuff[i]); | |
957 | } | |
958 | rp->rx_skbuff[i] = NULL; | |
959 | } | |
960 | } | |
961 | ||
962 | static void alloc_tbufs(struct net_device* dev) | |
963 | { | |
964 | struct rhine_private *rp = netdev_priv(dev); | |
965 | dma_addr_t next; | |
966 | int i; | |
967 | ||
968 | rp->dirty_tx = rp->cur_tx = 0; | |
969 | next = rp->tx_ring_dma; | |
970 | for (i = 0; i < TX_RING_SIZE; i++) { | |
971 | rp->tx_skbuff[i] = NULL; | |
972 | rp->tx_ring[i].tx_status = 0; | |
973 | rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC); | |
974 | next += sizeof(struct tx_desc); | |
975 | rp->tx_ring[i].next_desc = cpu_to_le32(next); | |
4be5de25 RL |
976 | if (rp->quirks & rqRhineI) |
977 | rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ]; | |
1da177e4 LT |
978 | } |
979 | rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma); | |
980 | ||
981 | } | |
982 | ||
983 | static void free_tbufs(struct net_device* dev) | |
984 | { | |
985 | struct rhine_private *rp = netdev_priv(dev); | |
986 | int i; | |
987 | ||
988 | for (i = 0; i < TX_RING_SIZE; i++) { | |
989 | rp->tx_ring[i].tx_status = 0; | |
990 | rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC); | |
991 | rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ | |
992 | if (rp->tx_skbuff[i]) { | |
993 | if (rp->tx_skbuff_dma[i]) { | |
994 | pci_unmap_single(rp->pdev, | |
995 | rp->tx_skbuff_dma[i], | |
996 | rp->tx_skbuff[i]->len, | |
997 | PCI_DMA_TODEVICE); | |
998 | } | |
999 | dev_kfree_skb(rp->tx_skbuff[i]); | |
1000 | } | |
1001 | rp->tx_skbuff[i] = NULL; | |
1002 | rp->tx_buf[i] = NULL; | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | static void rhine_check_media(struct net_device *dev, unsigned int init_media) | |
1007 | { | |
1008 | struct rhine_private *rp = netdev_priv(dev); | |
1009 | void __iomem *ioaddr = rp->base; | |
1010 | ||
1011 | mii_check_media(&rp->mii_if, debug, init_media); | |
1012 | ||
1013 | if (rp->mii_if.full_duplex) | |
1014 | iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex, | |
1015 | ioaddr + ChipCmd1); | |
1016 | else | |
1017 | iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex, | |
1018 | ioaddr + ChipCmd1); | |
00b428c2 RL |
1019 | if (debug > 1) |
1020 | printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name, | |
1021 | rp->mii_if.force_media, netif_carrier_ok(dev)); | |
1022 | } | |
1023 | ||
1024 | /* Called after status of force_media possibly changed */ | |
0761be4f | 1025 | static void rhine_set_carrier(struct mii_if_info *mii) |
00b428c2 RL |
1026 | { |
1027 | if (mii->force_media) { | |
1028 | /* autoneg is off: Link is always assumed to be up */ | |
1029 | if (!netif_carrier_ok(mii->dev)) | |
1030 | netif_carrier_on(mii->dev); | |
1031 | } | |
1032 | else /* Let MMI library update carrier status */ | |
1033 | rhine_check_media(mii->dev, 0); | |
1034 | if (debug > 1) | |
1035 | printk(KERN_INFO "%s: force_media %d, carrier %d\n", | |
1036 | mii->dev->name, mii->force_media, | |
1037 | netif_carrier_ok(mii->dev)); | |
1da177e4 LT |
1038 | } |
1039 | ||
1040 | static void init_registers(struct net_device *dev) | |
1041 | { | |
1042 | struct rhine_private *rp = netdev_priv(dev); | |
1043 | void __iomem *ioaddr = rp->base; | |
1044 | int i; | |
1045 | ||
1046 | for (i = 0; i < 6; i++) | |
1047 | iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i); | |
1048 | ||
1049 | /* Initialize other registers. */ | |
1050 | iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */ | |
1051 | /* Configure initial FIFO thresholds. */ | |
1052 | iowrite8(0x20, ioaddr + TxConfig); | |
1053 | rp->tx_thresh = 0x20; | |
1054 | rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */ | |
1055 | ||
1056 | iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr); | |
1057 | iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr); | |
1058 | ||
1059 | rhine_set_rx_mode(dev); | |
1060 | ||
ab197668 SH |
1061 | netif_poll_enable(dev); |
1062 | ||
1da177e4 LT |
1063 | /* Enable interrupts by setting the interrupt mask. */ |
1064 | iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow | | |
1065 | IntrRxDropped | IntrRxNoBuf | IntrTxAborted | | |
1066 | IntrTxDone | IntrTxError | IntrTxUnderrun | | |
1067 | IntrPCIErr | IntrStatsMax | IntrLinkChange, | |
1068 | ioaddr + IntrEnable); | |
1069 | ||
1070 | iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8), | |
1071 | ioaddr + ChipCmd); | |
1072 | rhine_check_media(dev, 1); | |
1073 | } | |
1074 | ||
1075 | /* Enable MII link status auto-polling (required for IntrLinkChange) */ | |
1076 | static void rhine_enable_linkmon(void __iomem *ioaddr) | |
1077 | { | |
1078 | iowrite8(0, ioaddr + MIICmd); | |
1079 | iowrite8(MII_BMSR, ioaddr + MIIRegAddr); | |
1080 | iowrite8(0x80, ioaddr + MIICmd); | |
1081 | ||
1082 | RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20)); | |
1083 | ||
1084 | iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr); | |
1085 | } | |
1086 | ||
1087 | /* Disable MII link status auto-polling (required for MDIO access) */ | |
1088 | static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks) | |
1089 | { | |
1090 | iowrite8(0, ioaddr + MIICmd); | |
1091 | ||
1092 | if (quirks & rqRhineI) { | |
1093 | iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR | |
1094 | ||
38bb6b28 JL |
1095 | /* Can be called from ISR. Evil. */ |
1096 | mdelay(1); | |
1da177e4 LT |
1097 | |
1098 | /* 0x80 must be set immediately before turning it off */ | |
1099 | iowrite8(0x80, ioaddr + MIICmd); | |
1100 | ||
1101 | RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20); | |
1102 | ||
1103 | /* Heh. Now clear 0x80 again. */ | |
1104 | iowrite8(0, ioaddr + MIICmd); | |
1105 | } | |
1106 | else | |
1107 | RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80); | |
1108 | } | |
1109 | ||
1110 | /* Read and write over the MII Management Data I/O (MDIO) interface. */ | |
1111 | ||
1112 | static int mdio_read(struct net_device *dev, int phy_id, int regnum) | |
1113 | { | |
1114 | struct rhine_private *rp = netdev_priv(dev); | |
1115 | void __iomem *ioaddr = rp->base; | |
1116 | int result; | |
1117 | ||
1118 | rhine_disable_linkmon(ioaddr, rp->quirks); | |
1119 | ||
1120 | /* rhine_disable_linkmon already cleared MIICmd */ | |
1121 | iowrite8(phy_id, ioaddr + MIIPhyAddr); | |
1122 | iowrite8(regnum, ioaddr + MIIRegAddr); | |
1123 | iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */ | |
1124 | RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40)); | |
1125 | result = ioread16(ioaddr + MIIData); | |
1126 | ||
1127 | rhine_enable_linkmon(ioaddr); | |
1128 | return result; | |
1129 | } | |
1130 | ||
1131 | static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value) | |
1132 | { | |
1133 | struct rhine_private *rp = netdev_priv(dev); | |
1134 | void __iomem *ioaddr = rp->base; | |
1135 | ||
1136 | rhine_disable_linkmon(ioaddr, rp->quirks); | |
1137 | ||
1138 | /* rhine_disable_linkmon already cleared MIICmd */ | |
1139 | iowrite8(phy_id, ioaddr + MIIPhyAddr); | |
1140 | iowrite8(regnum, ioaddr + MIIRegAddr); | |
1141 | iowrite16(value, ioaddr + MIIData); | |
1142 | iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */ | |
1143 | RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20)); | |
1144 | ||
1145 | rhine_enable_linkmon(ioaddr); | |
1146 | } | |
1147 | ||
1148 | static int rhine_open(struct net_device *dev) | |
1149 | { | |
1150 | struct rhine_private *rp = netdev_priv(dev); | |
1151 | void __iomem *ioaddr = rp->base; | |
1152 | int rc; | |
1153 | ||
1fb9df5d | 1154 | rc = request_irq(rp->pdev->irq, &rhine_interrupt, IRQF_SHARED, dev->name, |
1da177e4 LT |
1155 | dev); |
1156 | if (rc) | |
1157 | return rc; | |
1158 | ||
1159 | if (debug > 1) | |
1160 | printk(KERN_DEBUG "%s: rhine_open() irq %d.\n", | |
1161 | dev->name, rp->pdev->irq); | |
1162 | ||
1163 | rc = alloc_ring(dev); | |
1164 | if (rc) { | |
1165 | free_irq(rp->pdev->irq, dev); | |
1166 | return rc; | |
1167 | } | |
1168 | alloc_rbufs(dev); | |
1169 | alloc_tbufs(dev); | |
1170 | rhine_chip_reset(dev); | |
1171 | init_registers(dev); | |
1172 | if (debug > 2) | |
1173 | printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x " | |
1174 | "MII status: %4.4x.\n", | |
1175 | dev->name, ioread16(ioaddr + ChipCmd), | |
1176 | mdio_read(dev, rp->mii_if.phy_id, MII_BMSR)); | |
1177 | ||
1178 | netif_start_queue(dev); | |
1179 | ||
1180 | return 0; | |
1181 | } | |
1182 | ||
1183 | static void rhine_tx_timeout(struct net_device *dev) | |
1184 | { | |
1185 | struct rhine_private *rp = netdev_priv(dev); | |
1186 | void __iomem *ioaddr = rp->base; | |
1187 | ||
1188 | printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status " | |
1189 | "%4.4x, resetting...\n", | |
1190 | dev->name, ioread16(ioaddr + IntrStatus), | |
1191 | mdio_read(dev, rp->mii_if.phy_id, MII_BMSR)); | |
1192 | ||
1193 | /* protect against concurrent rx interrupts */ | |
1194 | disable_irq(rp->pdev->irq); | |
1195 | ||
1196 | spin_lock(&rp->lock); | |
1197 | ||
1198 | /* clear all descriptors */ | |
1199 | free_tbufs(dev); | |
1200 | free_rbufs(dev); | |
1201 | alloc_tbufs(dev); | |
1202 | alloc_rbufs(dev); | |
1203 | ||
1204 | /* Reinitialize the hardware. */ | |
1205 | rhine_chip_reset(dev); | |
1206 | init_registers(dev); | |
1207 | ||
1208 | spin_unlock(&rp->lock); | |
1209 | enable_irq(rp->pdev->irq); | |
1210 | ||
1211 | dev->trans_start = jiffies; | |
1212 | rp->stats.tx_errors++; | |
1213 | netif_wake_queue(dev); | |
1214 | } | |
1215 | ||
1216 | static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev) | |
1217 | { | |
1218 | struct rhine_private *rp = netdev_priv(dev); | |
1219 | void __iomem *ioaddr = rp->base; | |
1220 | unsigned entry; | |
1221 | ||
1222 | /* Caution: the write order is important here, set the field | |
1223 | with the "ownership" bits last. */ | |
1224 | ||
1225 | /* Calculate the next Tx descriptor entry. */ | |
1226 | entry = rp->cur_tx % TX_RING_SIZE; | |
1227 | ||
5b057c6b HX |
1228 | if (skb_padto(skb, ETH_ZLEN)) |
1229 | return 0; | |
1da177e4 LT |
1230 | |
1231 | rp->tx_skbuff[entry] = skb; | |
1232 | ||
1233 | if ((rp->quirks & rqRhineI) && | |
84fa7933 | 1234 | (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) { |
1da177e4 LT |
1235 | /* Must use alignment buffer. */ |
1236 | if (skb->len > PKT_BUF_SZ) { | |
1237 | /* packet too long, drop it */ | |
1238 | dev_kfree_skb(skb); | |
1239 | rp->tx_skbuff[entry] = NULL; | |
1240 | rp->stats.tx_dropped++; | |
1241 | return 0; | |
1242 | } | |
3e0d167a CB |
1243 | |
1244 | /* Padding is not copied and so must be redone. */ | |
1da177e4 | 1245 | skb_copy_and_csum_dev(skb, rp->tx_buf[entry]); |
3e0d167a CB |
1246 | if (skb->len < ETH_ZLEN) |
1247 | memset(rp->tx_buf[entry] + skb->len, 0, | |
1248 | ETH_ZLEN - skb->len); | |
1da177e4 LT |
1249 | rp->tx_skbuff_dma[entry] = 0; |
1250 | rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma + | |
1251 | (rp->tx_buf[entry] - | |
1252 | rp->tx_bufs)); | |
1253 | } else { | |
1254 | rp->tx_skbuff_dma[entry] = | |
1255 | pci_map_single(rp->pdev, skb->data, skb->len, | |
1256 | PCI_DMA_TODEVICE); | |
1257 | rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]); | |
1258 | } | |
1259 | ||
1260 | rp->tx_ring[entry].desc_length = | |
1261 | cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN)); | |
1262 | ||
1263 | /* lock eth irq */ | |
1264 | spin_lock_irq(&rp->lock); | |
1265 | wmb(); | |
1266 | rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn); | |
1267 | wmb(); | |
1268 | ||
1269 | rp->cur_tx++; | |
1270 | ||
1271 | /* Non-x86 Todo: explicitly flush cache lines here. */ | |
1272 | ||
1273 | /* Wake the potentially-idle transmit channel */ | |
1274 | iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, | |
1275 | ioaddr + ChipCmd1); | |
1276 | IOSYNC; | |
1277 | ||
1278 | if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN) | |
1279 | netif_stop_queue(dev); | |
1280 | ||
1281 | dev->trans_start = jiffies; | |
1282 | ||
1283 | spin_unlock_irq(&rp->lock); | |
1284 | ||
1285 | if (debug > 4) { | |
1286 | printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n", | |
1287 | dev->name, rp->cur_tx-1, entry); | |
1288 | } | |
1289 | return 0; | |
1290 | } | |
1291 | ||
1292 | /* The interrupt handler does all of the Rx thread work and cleans up | |
1293 | after the Tx thread. */ | |
7d12e780 | 1294 | static irqreturn_t rhine_interrupt(int irq, void *dev_instance) |
1da177e4 LT |
1295 | { |
1296 | struct net_device *dev = dev_instance; | |
1297 | struct rhine_private *rp = netdev_priv(dev); | |
1298 | void __iomem *ioaddr = rp->base; | |
1299 | u32 intr_status; | |
1300 | int boguscnt = max_interrupt_work; | |
1301 | int handled = 0; | |
1302 | ||
1303 | while ((intr_status = get_intr_status(dev))) { | |
1304 | handled = 1; | |
1305 | ||
1306 | /* Acknowledge all of the current interrupt sources ASAP. */ | |
1307 | if (intr_status & IntrTxDescRace) | |
1308 | iowrite8(0x08, ioaddr + IntrStatus2); | |
1309 | iowrite16(intr_status & 0xffff, ioaddr + IntrStatus); | |
1310 | IOSYNC; | |
1311 | ||
1312 | if (debug > 4) | |
1313 | printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n", | |
1314 | dev->name, intr_status); | |
1315 | ||
1316 | if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped | | |
633949a1 RL |
1317 | IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) { |
1318 | #ifdef CONFIG_VIA_RHINE_NAPI | |
1319 | iowrite16(IntrTxAborted | | |
1320 | IntrTxDone | IntrTxError | IntrTxUnderrun | | |
1321 | IntrPCIErr | IntrStatsMax | IntrLinkChange, | |
1322 | ioaddr + IntrEnable); | |
1323 | ||
1324 | netif_rx_schedule(dev); | |
1325 | #else | |
1326 | rhine_rx(dev, RX_RING_SIZE); | |
1327 | #endif | |
1328 | } | |
1da177e4 LT |
1329 | |
1330 | if (intr_status & (IntrTxErrSummary | IntrTxDone)) { | |
1331 | if (intr_status & IntrTxErrSummary) { | |
1332 | /* Avoid scavenging before Tx engine turned off */ | |
1333 | RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn)); | |
1334 | if (debug > 2 && | |
1335 | ioread8(ioaddr+ChipCmd) & CmdTxOn) | |
1336 | printk(KERN_WARNING "%s: " | |
1337 | "rhine_interrupt() Tx engine" | |
1338 | "still on.\n", dev->name); | |
1339 | } | |
1340 | rhine_tx(dev); | |
1341 | } | |
1342 | ||
1343 | /* Abnormal error summary/uncommon events handlers. */ | |
1344 | if (intr_status & (IntrPCIErr | IntrLinkChange | | |
1345 | IntrStatsMax | IntrTxError | IntrTxAborted | | |
1346 | IntrTxUnderrun | IntrTxDescRace)) | |
1347 | rhine_error(dev, intr_status); | |
1348 | ||
1349 | if (--boguscnt < 0) { | |
1350 | printk(KERN_WARNING "%s: Too much work at interrupt, " | |
1351 | "status=%#8.8x.\n", | |
1352 | dev->name, intr_status); | |
1353 | break; | |
1354 | } | |
1355 | } | |
1356 | ||
1357 | if (debug > 3) | |
1358 | printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n", | |
1359 | dev->name, ioread16(ioaddr + IntrStatus)); | |
1360 | return IRQ_RETVAL(handled); | |
1361 | } | |
1362 | ||
1363 | /* This routine is logically part of the interrupt handler, but isolated | |
1364 | for clarity. */ | |
1365 | static void rhine_tx(struct net_device *dev) | |
1366 | { | |
1367 | struct rhine_private *rp = netdev_priv(dev); | |
1368 | int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE; | |
1369 | ||
1370 | spin_lock(&rp->lock); | |
1371 | ||
1372 | /* find and cleanup dirty tx descriptors */ | |
1373 | while (rp->dirty_tx != rp->cur_tx) { | |
1374 | txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status); | |
1375 | if (debug > 6) | |
ed4030d1 | 1376 | printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n", |
1da177e4 LT |
1377 | entry, txstatus); |
1378 | if (txstatus & DescOwn) | |
1379 | break; | |
1380 | if (txstatus & 0x8000) { | |
1381 | if (debug > 1) | |
1382 | printk(KERN_DEBUG "%s: Transmit error, " | |
1383 | "Tx status %8.8x.\n", | |
1384 | dev->name, txstatus); | |
1385 | rp->stats.tx_errors++; | |
1386 | if (txstatus & 0x0400) rp->stats.tx_carrier_errors++; | |
1387 | if (txstatus & 0x0200) rp->stats.tx_window_errors++; | |
1388 | if (txstatus & 0x0100) rp->stats.tx_aborted_errors++; | |
1389 | if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++; | |
1390 | if (((rp->quirks & rqRhineI) && txstatus & 0x0002) || | |
1391 | (txstatus & 0x0800) || (txstatus & 0x1000)) { | |
1392 | rp->stats.tx_fifo_errors++; | |
1393 | rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn); | |
1394 | break; /* Keep the skb - we try again */ | |
1395 | } | |
1396 | /* Transmitter restarted in 'abnormal' handler. */ | |
1397 | } else { | |
1398 | if (rp->quirks & rqRhineI) | |
1399 | rp->stats.collisions += (txstatus >> 3) & 0x0F; | |
1400 | else | |
1401 | rp->stats.collisions += txstatus & 0x0F; | |
1402 | if (debug > 6) | |
1403 | printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n", | |
1404 | (txstatus >> 3) & 0xF, | |
1405 | txstatus & 0xF); | |
1406 | rp->stats.tx_bytes += rp->tx_skbuff[entry]->len; | |
1407 | rp->stats.tx_packets++; | |
1408 | } | |
1409 | /* Free the original skb. */ | |
1410 | if (rp->tx_skbuff_dma[entry]) { | |
1411 | pci_unmap_single(rp->pdev, | |
1412 | rp->tx_skbuff_dma[entry], | |
1413 | rp->tx_skbuff[entry]->len, | |
1414 | PCI_DMA_TODEVICE); | |
1415 | } | |
1416 | dev_kfree_skb_irq(rp->tx_skbuff[entry]); | |
1417 | rp->tx_skbuff[entry] = NULL; | |
1418 | entry = (++rp->dirty_tx) % TX_RING_SIZE; | |
1419 | } | |
1420 | if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4) | |
1421 | netif_wake_queue(dev); | |
1422 | ||
1423 | spin_unlock(&rp->lock); | |
1424 | } | |
1425 | ||
633949a1 RL |
1426 | /* Process up to limit frames from receive ring */ |
1427 | static int rhine_rx(struct net_device *dev, int limit) | |
1da177e4 LT |
1428 | { |
1429 | struct rhine_private *rp = netdev_priv(dev); | |
633949a1 | 1430 | int count; |
1da177e4 | 1431 | int entry = rp->cur_rx % RX_RING_SIZE; |
1da177e4 LT |
1432 | |
1433 | if (debug > 4) { | |
1434 | printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n", | |
1435 | dev->name, entry, | |
1436 | le32_to_cpu(rp->rx_head_desc->rx_status)); | |
1437 | } | |
1438 | ||
1439 | /* If EOP is set on the next entry, it's a new packet. Send it up. */ | |
633949a1 | 1440 | for (count = 0; count < limit; ++count) { |
1da177e4 LT |
1441 | struct rx_desc *desc = rp->rx_head_desc; |
1442 | u32 desc_status = le32_to_cpu(desc->rx_status); | |
1443 | int data_size = desc_status >> 16; | |
1444 | ||
633949a1 RL |
1445 | if (desc_status & DescOwn) |
1446 | break; | |
1447 | ||
1da177e4 | 1448 | if (debug > 4) |
ed4030d1 | 1449 | printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n", |
1da177e4 | 1450 | desc_status); |
633949a1 | 1451 | |
1da177e4 LT |
1452 | if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) { |
1453 | if ((desc_status & RxWholePkt) != RxWholePkt) { | |
1454 | printk(KERN_WARNING "%s: Oversized Ethernet " | |
1455 | "frame spanned multiple buffers, entry " | |
1456 | "%#x length %d status %8.8x!\n", | |
1457 | dev->name, entry, data_size, | |
1458 | desc_status); | |
1459 | printk(KERN_WARNING "%s: Oversized Ethernet " | |
1460 | "frame %p vs %p.\n", dev->name, | |
1461 | rp->rx_head_desc, &rp->rx_ring[entry]); | |
1462 | rp->stats.rx_length_errors++; | |
1463 | } else if (desc_status & RxErr) { | |
1464 | /* There was a error. */ | |
1465 | if (debug > 2) | |
ed4030d1 | 1466 | printk(KERN_DEBUG "rhine_rx() Rx " |
1da177e4 LT |
1467 | "error was %8.8x.\n", |
1468 | desc_status); | |
1469 | rp->stats.rx_errors++; | |
1470 | if (desc_status & 0x0030) rp->stats.rx_length_errors++; | |
1471 | if (desc_status & 0x0048) rp->stats.rx_fifo_errors++; | |
1472 | if (desc_status & 0x0004) rp->stats.rx_frame_errors++; | |
1473 | if (desc_status & 0x0002) { | |
1474 | /* this can also be updated outside the interrupt handler */ | |
1475 | spin_lock(&rp->lock); | |
1476 | rp->stats.rx_crc_errors++; | |
1477 | spin_unlock(&rp->lock); | |
1478 | } | |
1479 | } | |
1480 | } else { | |
1481 | struct sk_buff *skb; | |
1482 | /* Length should omit the CRC */ | |
1483 | int pkt_len = data_size - 4; | |
1484 | ||
1485 | /* Check if the packet is long enough to accept without | |
1486 | copying to a minimally-sized skbuff. */ | |
1487 | if (pkt_len < rx_copybreak && | |
1488 | (skb = dev_alloc_skb(pkt_len + 2)) != NULL) { | |
1da177e4 LT |
1489 | skb_reserve(skb, 2); /* 16 byte align the IP header */ |
1490 | pci_dma_sync_single_for_cpu(rp->pdev, | |
1491 | rp->rx_skbuff_dma[entry], | |
1492 | rp->rx_buf_sz, | |
1493 | PCI_DMA_FROMDEVICE); | |
1494 | ||
1495 | eth_copy_and_sum(skb, | |
689be439 | 1496 | rp->rx_skbuff[entry]->data, |
1da177e4 LT |
1497 | pkt_len, 0); |
1498 | skb_put(skb, pkt_len); | |
1499 | pci_dma_sync_single_for_device(rp->pdev, | |
1500 | rp->rx_skbuff_dma[entry], | |
1501 | rp->rx_buf_sz, | |
1502 | PCI_DMA_FROMDEVICE); | |
1503 | } else { | |
1504 | skb = rp->rx_skbuff[entry]; | |
1505 | if (skb == NULL) { | |
1506 | printk(KERN_ERR "%s: Inconsistent Rx " | |
1507 | "descriptor chain.\n", | |
1508 | dev->name); | |
1509 | break; | |
1510 | } | |
1511 | rp->rx_skbuff[entry] = NULL; | |
1512 | skb_put(skb, pkt_len); | |
1513 | pci_unmap_single(rp->pdev, | |
1514 | rp->rx_skbuff_dma[entry], | |
1515 | rp->rx_buf_sz, | |
1516 | PCI_DMA_FROMDEVICE); | |
1517 | } | |
1518 | skb->protocol = eth_type_trans(skb, dev); | |
633949a1 RL |
1519 | #ifdef CONFIG_VIA_RHINE_NAPI |
1520 | netif_receive_skb(skb); | |
1521 | #else | |
1da177e4 | 1522 | netif_rx(skb); |
633949a1 | 1523 | #endif |
1da177e4 LT |
1524 | dev->last_rx = jiffies; |
1525 | rp->stats.rx_bytes += pkt_len; | |
1526 | rp->stats.rx_packets++; | |
1527 | } | |
1528 | entry = (++rp->cur_rx) % RX_RING_SIZE; | |
1529 | rp->rx_head_desc = &rp->rx_ring[entry]; | |
1530 | } | |
1531 | ||
1532 | /* Refill the Rx ring buffers. */ | |
1533 | for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) { | |
1534 | struct sk_buff *skb; | |
1535 | entry = rp->dirty_rx % RX_RING_SIZE; | |
1536 | if (rp->rx_skbuff[entry] == NULL) { | |
1537 | skb = dev_alloc_skb(rp->rx_buf_sz); | |
1538 | rp->rx_skbuff[entry] = skb; | |
1539 | if (skb == NULL) | |
1540 | break; /* Better luck next round. */ | |
1541 | skb->dev = dev; /* Mark as being used by this device. */ | |
1542 | rp->rx_skbuff_dma[entry] = | |
689be439 | 1543 | pci_map_single(rp->pdev, skb->data, |
1da177e4 LT |
1544 | rp->rx_buf_sz, |
1545 | PCI_DMA_FROMDEVICE); | |
1546 | rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]); | |
1547 | } | |
1548 | rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn); | |
1549 | } | |
633949a1 RL |
1550 | |
1551 | return count; | |
1da177e4 LT |
1552 | } |
1553 | ||
1554 | /* | |
1555 | * Clears the "tally counters" for CRC errors and missed frames(?). | |
1556 | * It has been reported that some chips need a write of 0 to clear | |
1557 | * these, for others the counters are set to 1 when written to and | |
1558 | * instead cleared when read. So we clear them both ways ... | |
1559 | */ | |
1560 | static inline void clear_tally_counters(void __iomem *ioaddr) | |
1561 | { | |
1562 | iowrite32(0, ioaddr + RxMissed); | |
1563 | ioread16(ioaddr + RxCRCErrs); | |
1564 | ioread16(ioaddr + RxMissed); | |
1565 | } | |
1566 | ||
1567 | static void rhine_restart_tx(struct net_device *dev) { | |
1568 | struct rhine_private *rp = netdev_priv(dev); | |
1569 | void __iomem *ioaddr = rp->base; | |
1570 | int entry = rp->dirty_tx % TX_RING_SIZE; | |
1571 | u32 intr_status; | |
1572 | ||
1573 | /* | |
1574 | * If new errors occured, we need to sort them out before doing Tx. | |
1575 | * In that case the ISR will be back here RSN anyway. | |
1576 | */ | |
1577 | intr_status = get_intr_status(dev); | |
1578 | ||
1579 | if ((intr_status & IntrTxErrSummary) == 0) { | |
1580 | ||
1581 | /* We know better than the chip where it should continue. */ | |
1582 | iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc), | |
1583 | ioaddr + TxRingPtr); | |
1584 | ||
1585 | iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn, | |
1586 | ioaddr + ChipCmd); | |
1587 | iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, | |
1588 | ioaddr + ChipCmd1); | |
1589 | IOSYNC; | |
1590 | } | |
1591 | else { | |
1592 | /* This should never happen */ | |
1593 | if (debug > 1) | |
1594 | printk(KERN_WARNING "%s: rhine_restart_tx() " | |
1595 | "Another error occured %8.8x.\n", | |
1596 | dev->name, intr_status); | |
1597 | } | |
1598 | ||
1599 | } | |
1600 | ||
1601 | static void rhine_error(struct net_device *dev, int intr_status) | |
1602 | { | |
1603 | struct rhine_private *rp = netdev_priv(dev); | |
1604 | void __iomem *ioaddr = rp->base; | |
1605 | ||
1606 | spin_lock(&rp->lock); | |
1607 | ||
1608 | if (intr_status & IntrLinkChange) | |
38bb6b28 | 1609 | rhine_check_media(dev, 0); |
1da177e4 LT |
1610 | if (intr_status & IntrStatsMax) { |
1611 | rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs); | |
1612 | rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed); | |
1613 | clear_tally_counters(ioaddr); | |
1614 | } | |
1615 | if (intr_status & IntrTxAborted) { | |
1616 | if (debug > 1) | |
1617 | printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n", | |
1618 | dev->name, intr_status); | |
1619 | } | |
1620 | if (intr_status & IntrTxUnderrun) { | |
1621 | if (rp->tx_thresh < 0xE0) | |
1622 | iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig); | |
1623 | if (debug > 1) | |
1624 | printk(KERN_INFO "%s: Transmitter underrun, Tx " | |
1625 | "threshold now %2.2x.\n", | |
1626 | dev->name, rp->tx_thresh); | |
1627 | } | |
1628 | if (intr_status & IntrTxDescRace) { | |
1629 | if (debug > 2) | |
1630 | printk(KERN_INFO "%s: Tx descriptor write-back race.\n", | |
1631 | dev->name); | |
1632 | } | |
1633 | if ((intr_status & IntrTxError) && | |
1634 | (intr_status & (IntrTxAborted | | |
1635 | IntrTxUnderrun | IntrTxDescRace)) == 0) { | |
1636 | if (rp->tx_thresh < 0xE0) { | |
1637 | iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig); | |
1638 | } | |
1639 | if (debug > 1) | |
1640 | printk(KERN_INFO "%s: Unspecified error. Tx " | |
1641 | "threshold now %2.2x.\n", | |
1642 | dev->name, rp->tx_thresh); | |
1643 | } | |
1644 | if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace | | |
1645 | IntrTxError)) | |
1646 | rhine_restart_tx(dev); | |
1647 | ||
1648 | if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun | | |
1649 | IntrTxError | IntrTxAborted | IntrNormalSummary | | |
1650 | IntrTxDescRace)) { | |
1651 | if (debug > 1) | |
1652 | printk(KERN_ERR "%s: Something Wicked happened! " | |
1653 | "%8.8x.\n", dev->name, intr_status); | |
1654 | } | |
1655 | ||
1656 | spin_unlock(&rp->lock); | |
1657 | } | |
1658 | ||
1659 | static struct net_device_stats *rhine_get_stats(struct net_device *dev) | |
1660 | { | |
1661 | struct rhine_private *rp = netdev_priv(dev); | |
1662 | void __iomem *ioaddr = rp->base; | |
1663 | unsigned long flags; | |
1664 | ||
1665 | spin_lock_irqsave(&rp->lock, flags); | |
1666 | rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs); | |
1667 | rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed); | |
1668 | clear_tally_counters(ioaddr); | |
1669 | spin_unlock_irqrestore(&rp->lock, flags); | |
1670 | ||
1671 | return &rp->stats; | |
1672 | } | |
1673 | ||
1674 | static void rhine_set_rx_mode(struct net_device *dev) | |
1675 | { | |
1676 | struct rhine_private *rp = netdev_priv(dev); | |
1677 | void __iomem *ioaddr = rp->base; | |
1678 | u32 mc_filter[2]; /* Multicast hash filter */ | |
1679 | u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */ | |
1680 | ||
1681 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1da177e4 LT |
1682 | rx_mode = 0x1C; |
1683 | iowrite32(0xffffffff, ioaddr + MulticastFilter0); | |
1684 | iowrite32(0xffffffff, ioaddr + MulticastFilter1); | |
1685 | } else if ((dev->mc_count > multicast_filter_limit) | |
1686 | || (dev->flags & IFF_ALLMULTI)) { | |
1687 | /* Too many to match, or accept all multicasts. */ | |
1688 | iowrite32(0xffffffff, ioaddr + MulticastFilter0); | |
1689 | iowrite32(0xffffffff, ioaddr + MulticastFilter1); | |
1690 | rx_mode = 0x0C; | |
1691 | } else { | |
1692 | struct dev_mc_list *mclist; | |
1693 | int i; | |
1694 | memset(mc_filter, 0, sizeof(mc_filter)); | |
1695 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
1696 | i++, mclist = mclist->next) { | |
1697 | int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; | |
1698 | ||
1699 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
1700 | } | |
1701 | iowrite32(mc_filter[0], ioaddr + MulticastFilter0); | |
1702 | iowrite32(mc_filter[1], ioaddr + MulticastFilter1); | |
1703 | rx_mode = 0x0C; | |
1704 | } | |
1705 | iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig); | |
1706 | } | |
1707 | ||
1708 | static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
1709 | { | |
1710 | struct rhine_private *rp = netdev_priv(dev); | |
1711 | ||
1712 | strcpy(info->driver, DRV_NAME); | |
1713 | strcpy(info->version, DRV_VERSION); | |
1714 | strcpy(info->bus_info, pci_name(rp->pdev)); | |
1715 | } | |
1716 | ||
1717 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1718 | { | |
1719 | struct rhine_private *rp = netdev_priv(dev); | |
1720 | int rc; | |
1721 | ||
1722 | spin_lock_irq(&rp->lock); | |
1723 | rc = mii_ethtool_gset(&rp->mii_if, cmd); | |
1724 | spin_unlock_irq(&rp->lock); | |
1725 | ||
1726 | return rc; | |
1727 | } | |
1728 | ||
1729 | static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1730 | { | |
1731 | struct rhine_private *rp = netdev_priv(dev); | |
1732 | int rc; | |
1733 | ||
1734 | spin_lock_irq(&rp->lock); | |
1735 | rc = mii_ethtool_sset(&rp->mii_if, cmd); | |
1736 | spin_unlock_irq(&rp->lock); | |
00b428c2 | 1737 | rhine_set_carrier(&rp->mii_if); |
1da177e4 LT |
1738 | |
1739 | return rc; | |
1740 | } | |
1741 | ||
1742 | static int netdev_nway_reset(struct net_device *dev) | |
1743 | { | |
1744 | struct rhine_private *rp = netdev_priv(dev); | |
1745 | ||
1746 | return mii_nway_restart(&rp->mii_if); | |
1747 | } | |
1748 | ||
1749 | static u32 netdev_get_link(struct net_device *dev) | |
1750 | { | |
1751 | struct rhine_private *rp = netdev_priv(dev); | |
1752 | ||
1753 | return mii_link_ok(&rp->mii_if); | |
1754 | } | |
1755 | ||
1756 | static u32 netdev_get_msglevel(struct net_device *dev) | |
1757 | { | |
1758 | return debug; | |
1759 | } | |
1760 | ||
1761 | static void netdev_set_msglevel(struct net_device *dev, u32 value) | |
1762 | { | |
1763 | debug = value; | |
1764 | } | |
1765 | ||
1766 | static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1767 | { | |
1768 | struct rhine_private *rp = netdev_priv(dev); | |
1769 | ||
1770 | if (!(rp->quirks & rqWOL)) | |
1771 | return; | |
1772 | ||
1773 | spin_lock_irq(&rp->lock); | |
1774 | wol->supported = WAKE_PHY | WAKE_MAGIC | | |
1775 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */ | |
1776 | wol->wolopts = rp->wolopts; | |
1777 | spin_unlock_irq(&rp->lock); | |
1778 | } | |
1779 | ||
1780 | static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1781 | { | |
1782 | struct rhine_private *rp = netdev_priv(dev); | |
1783 | u32 support = WAKE_PHY | WAKE_MAGIC | | |
1784 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */ | |
1785 | ||
1786 | if (!(rp->quirks & rqWOL)) | |
1787 | return -EINVAL; | |
1788 | ||
1789 | if (wol->wolopts & ~support) | |
1790 | return -EINVAL; | |
1791 | ||
1792 | spin_lock_irq(&rp->lock); | |
1793 | rp->wolopts = wol->wolopts; | |
1794 | spin_unlock_irq(&rp->lock); | |
1795 | ||
1796 | return 0; | |
1797 | } | |
1798 | ||
7282d491 | 1799 | static const struct ethtool_ops netdev_ethtool_ops = { |
1da177e4 LT |
1800 | .get_drvinfo = netdev_get_drvinfo, |
1801 | .get_settings = netdev_get_settings, | |
1802 | .set_settings = netdev_set_settings, | |
1803 | .nway_reset = netdev_nway_reset, | |
1804 | .get_link = netdev_get_link, | |
1805 | .get_msglevel = netdev_get_msglevel, | |
1806 | .set_msglevel = netdev_set_msglevel, | |
1807 | .get_wol = rhine_get_wol, | |
1808 | .set_wol = rhine_set_wol, | |
1809 | .get_sg = ethtool_op_get_sg, | |
1810 | .get_tx_csum = ethtool_op_get_tx_csum, | |
b81e8e1f | 1811 | .get_perm_addr = ethtool_op_get_perm_addr, |
1da177e4 LT |
1812 | }; |
1813 | ||
1814 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1815 | { | |
1816 | struct rhine_private *rp = netdev_priv(dev); | |
1817 | int rc; | |
1818 | ||
1819 | if (!netif_running(dev)) | |
1820 | return -EINVAL; | |
1821 | ||
1822 | spin_lock_irq(&rp->lock); | |
1823 | rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL); | |
1824 | spin_unlock_irq(&rp->lock); | |
00b428c2 | 1825 | rhine_set_carrier(&rp->mii_if); |
1da177e4 LT |
1826 | |
1827 | return rc; | |
1828 | } | |
1829 | ||
1830 | static int rhine_close(struct net_device *dev) | |
1831 | { | |
1832 | struct rhine_private *rp = netdev_priv(dev); | |
1833 | void __iomem *ioaddr = rp->base; | |
1834 | ||
1835 | spin_lock_irq(&rp->lock); | |
1836 | ||
1837 | netif_stop_queue(dev); | |
633949a1 | 1838 | netif_poll_disable(dev); |
1da177e4 LT |
1839 | |
1840 | if (debug > 1) | |
1841 | printk(KERN_DEBUG "%s: Shutting down ethercard, " | |
1842 | "status was %4.4x.\n", | |
1843 | dev->name, ioread16(ioaddr + ChipCmd)); | |
1844 | ||
1845 | /* Switch to loopback mode to avoid hardware races. */ | |
1846 | iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig); | |
1847 | ||
1848 | /* Disable interrupts by clearing the interrupt mask. */ | |
1849 | iowrite16(0x0000, ioaddr + IntrEnable); | |
1850 | ||
1851 | /* Stop the chip's Tx and Rx processes. */ | |
1852 | iowrite16(CmdStop, ioaddr + ChipCmd); | |
1853 | ||
1854 | spin_unlock_irq(&rp->lock); | |
1855 | ||
1856 | free_irq(rp->pdev->irq, dev); | |
1857 | free_rbufs(dev); | |
1858 | free_tbufs(dev); | |
1859 | free_ring(dev); | |
1860 | ||
1861 | return 0; | |
1862 | } | |
1863 | ||
1864 | ||
1865 | static void __devexit rhine_remove_one(struct pci_dev *pdev) | |
1866 | { | |
1867 | struct net_device *dev = pci_get_drvdata(pdev); | |
1868 | struct rhine_private *rp = netdev_priv(dev); | |
1869 | ||
1870 | unregister_netdev(dev); | |
1871 | ||
1872 | pci_iounmap(pdev, rp->base); | |
1873 | pci_release_regions(pdev); | |
1874 | ||
1875 | free_netdev(dev); | |
1876 | pci_disable_device(pdev); | |
1877 | pci_set_drvdata(pdev, NULL); | |
1878 | } | |
1879 | ||
d18c3db5 | 1880 | static void rhine_shutdown (struct pci_dev *pdev) |
1da177e4 | 1881 | { |
1da177e4 LT |
1882 | struct net_device *dev = pci_get_drvdata(pdev); |
1883 | struct rhine_private *rp = netdev_priv(dev); | |
1884 | void __iomem *ioaddr = rp->base; | |
1885 | ||
1886 | if (!(rp->quirks & rqWOL)) | |
1887 | return; /* Nothing to do for non-WOL adapters */ | |
1888 | ||
1889 | rhine_power_init(dev); | |
1890 | ||
1891 | /* Make sure we use pattern 0, 1 and not 4, 5 */ | |
1892 | if (rp->quirks & rq6patterns) | |
1893 | iowrite8(0x04, ioaddr + 0xA7); | |
1894 | ||
1895 | if (rp->wolopts & WAKE_MAGIC) { | |
1896 | iowrite8(WOLmagic, ioaddr + WOLcrSet); | |
1897 | /* | |
1898 | * Turn EEPROM-controlled wake-up back on -- some hardware may | |
1899 | * not cooperate otherwise. | |
1900 | */ | |
1901 | iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA); | |
1902 | } | |
1903 | ||
1904 | if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST)) | |
1905 | iowrite8(WOLbmcast, ioaddr + WOLcgSet); | |
1906 | ||
1907 | if (rp->wolopts & WAKE_PHY) | |
1908 | iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet); | |
1909 | ||
1910 | if (rp->wolopts & WAKE_UCAST) | |
1911 | iowrite8(WOLucast, ioaddr + WOLcrSet); | |
1912 | ||
1913 | if (rp->wolopts) { | |
1914 | /* Enable legacy WOL (for old motherboards) */ | |
1915 | iowrite8(0x01, ioaddr + PwcfgSet); | |
1916 | iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW); | |
1917 | } | |
1918 | ||
1919 | /* Hit power state D3 (sleep) */ | |
b933b4d9 RL |
1920 | if (!avoid_D3) |
1921 | iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW); | |
1da177e4 LT |
1922 | |
1923 | /* TODO: Check use of pci_enable_wake() */ | |
1924 | ||
1925 | } | |
1926 | ||
1927 | #ifdef CONFIG_PM | |
1928 | static int rhine_suspend(struct pci_dev *pdev, pm_message_t state) | |
1929 | { | |
1930 | struct net_device *dev = pci_get_drvdata(pdev); | |
1931 | struct rhine_private *rp = netdev_priv(dev); | |
1932 | unsigned long flags; | |
1933 | ||
1934 | if (!netif_running(dev)) | |
1935 | return 0; | |
1936 | ||
1937 | netif_device_detach(dev); | |
1938 | pci_save_state(pdev); | |
1939 | ||
1940 | spin_lock_irqsave(&rp->lock, flags); | |
d18c3db5 | 1941 | rhine_shutdown(pdev); |
1da177e4 LT |
1942 | spin_unlock_irqrestore(&rp->lock, flags); |
1943 | ||
1944 | free_irq(dev->irq, dev); | |
1945 | return 0; | |
1946 | } | |
1947 | ||
1948 | static int rhine_resume(struct pci_dev *pdev) | |
1949 | { | |
1950 | struct net_device *dev = pci_get_drvdata(pdev); | |
1951 | struct rhine_private *rp = netdev_priv(dev); | |
1952 | unsigned long flags; | |
1953 | int ret; | |
1954 | ||
1955 | if (!netif_running(dev)) | |
1956 | return 0; | |
1957 | ||
1fb9df5d | 1958 | if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev)) |
1da177e4 LT |
1959 | printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name); |
1960 | ||
1961 | ret = pci_set_power_state(pdev, PCI_D0); | |
1962 | if (debug > 1) | |
1963 | printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n", | |
1964 | dev->name, ret ? "failed" : "succeeded", ret); | |
1965 | ||
1966 | pci_restore_state(pdev); | |
1967 | ||
1968 | spin_lock_irqsave(&rp->lock, flags); | |
1969 | #ifdef USE_MMIO | |
1970 | enable_mmio(rp->pioaddr, rp->quirks); | |
1971 | #endif | |
1972 | rhine_power_init(dev); | |
1973 | free_tbufs(dev); | |
1974 | free_rbufs(dev); | |
1975 | alloc_tbufs(dev); | |
1976 | alloc_rbufs(dev); | |
1977 | init_registers(dev); | |
1978 | spin_unlock_irqrestore(&rp->lock, flags); | |
1979 | ||
1980 | netif_device_attach(dev); | |
1981 | ||
1982 | return 0; | |
1983 | } | |
1984 | #endif /* CONFIG_PM */ | |
1985 | ||
1986 | static struct pci_driver rhine_driver = { | |
1987 | .name = DRV_NAME, | |
1988 | .id_table = rhine_pci_tbl, | |
1989 | .probe = rhine_init_one, | |
1990 | .remove = __devexit_p(rhine_remove_one), | |
1991 | #ifdef CONFIG_PM | |
1992 | .suspend = rhine_suspend, | |
1993 | .resume = rhine_resume, | |
1994 | #endif /* CONFIG_PM */ | |
d18c3db5 | 1995 | .shutdown = rhine_shutdown, |
1da177e4 LT |
1996 | }; |
1997 | ||
e84df485 RL |
1998 | static struct dmi_system_id __initdata rhine_dmi_table[] = { |
1999 | { | |
2000 | .ident = "EPIA-M", | |
2001 | .matches = { | |
2002 | DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."), | |
2003 | DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"), | |
2004 | }, | |
2005 | }, | |
2006 | { | |
2007 | .ident = "KV7", | |
2008 | .matches = { | |
2009 | DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"), | |
2010 | DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"), | |
2011 | }, | |
2012 | }, | |
2013 | { NULL } | |
2014 | }; | |
1da177e4 LT |
2015 | |
2016 | static int __init rhine_init(void) | |
2017 | { | |
2018 | /* when a module, this is printed whether or not devices are found in probe */ | |
2019 | #ifdef MODULE | |
2020 | printk(version); | |
2021 | #endif | |
e84df485 RL |
2022 | if (dmi_check_system(rhine_dmi_table)) { |
2023 | /* these BIOSes fail at PXE boot if chip is in D3 */ | |
2024 | avoid_D3 = 1; | |
2025 | printk(KERN_WARNING "%s: Broken BIOS detected, avoid_D3 " | |
2026 | "enabled.\n", | |
2027 | DRV_NAME); | |
2028 | } | |
2029 | else if (avoid_D3) | |
2030 | printk(KERN_INFO "%s: avoid_D3 set.\n", DRV_NAME); | |
2031 | ||
29917620 | 2032 | return pci_register_driver(&rhine_driver); |
1da177e4 LT |
2033 | } |
2034 | ||
2035 | ||
2036 | static void __exit rhine_cleanup(void) | |
2037 | { | |
2038 | pci_unregister_driver(&rhine_driver); | |
2039 | } | |
2040 | ||
2041 | ||
2042 | module_init(rhine_init); | |
2043 | module_exit(rhine_cleanup); |