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[linux-block.git] / drivers / net / via-rhine.c
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1da177e4
LT		 1/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
03a8c661 28 [link no longer provides useful info -jgarzik]
1da177e4
LT		 29
30*/
31
32#define DRV_NAME "via-rhine"
03a8c661
JG		 33#define DRV_VERSION "1.4.0"
34#define DRV_RELDATE "June-27-2006"
1da177e4
LT		 35
36
37/* A few user-configurable values.
38 These may be modified when a driver module is loaded. */
39
40static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
41static int max_interrupt_work = 20;
42
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1518 effectively disables this feature. */
45static int rx_copybreak;
46
47/*
48 * In case you are looking for 'options[]' or 'full_duplex[]', they
49 * are gone. Use ethtool(8) instead.
50 */
51
52/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
53 The Rhine has a 64 element 8390-like hash table. */
54static const int multicast_filter_limit = 32;
55
56
57/* Operational parameters that are set at compile time. */
58
59/* Keep the ring sizes a power of two for compile efficiency.
60 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
61 Making the Tx ring too large decreases the effectiveness of channel
62 bonding and packet priority.
63 There are no ill effects from too-large receive rings. */
64#define TX_RING_SIZE 16
65#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
66#define RX_RING_SIZE 16
67
68
69/* Operational parameters that usually are not changed. */
70
71/* Time in jiffies before concluding the transmitter is hung. */
72#define TX_TIMEOUT (2*HZ)
73
74#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
75
76#include <linux/module.h>
77#include <linux/moduleparam.h>
78#include <linux/kernel.h>
79#include <linux/string.h>
80#include <linux/timer.h>
81#include <linux/errno.h>
82#include <linux/ioport.h>
83#include <linux/slab.h>
84#include <linux/interrupt.h>
85#include <linux/pci.h>
1e7f0bd8 86#include <linux/dma-mapping.h>
1da177e4
LT		 87#include <linux/netdevice.h>
88#include <linux/etherdevice.h>
89#include <linux/skbuff.h>
90#include <linux/init.h>
91#include <linux/delay.h>
92#include <linux/mii.h>
93#include <linux/ethtool.h>
94#include <linux/crc32.h>
95#include <linux/bitops.h>
96#include <asm/processor.h> /* Processor type for cache alignment. */
97#include <asm/io.h>
98#include <asm/irq.h>
99#include <asm/uaccess.h>
100
101/* These identify the driver base version and may not be removed. */
102static char version[] __devinitdata =
103KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
104
105/* This driver was written to use PCI memory space. Some early versions
106 of the Rhine may only work correctly with I/O space accesses. */
107#ifdef CONFIG_VIA_RHINE_MMIO
108#define USE_MMIO
109#else
110#endif
111
112MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
113MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
114MODULE_LICENSE("GPL");
115
116module_param(max_interrupt_work, int, 0);
117module_param(debug, int, 0);
118module_param(rx_copybreak, int, 0);
119MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
120MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
121MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
122
123/*
124 Theory of Operation
125
126I. Board Compatibility
127
128This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
129controller.
130
131II. Board-specific settings
132
133Boards with this chip are functional only in a bus-master PCI slot.
134
135Many operational settings are loaded from the EEPROM to the Config word at
136offset 0x78. For most of these settings, this driver assumes that they are
137correct.
138If this driver is compiled to use PCI memory space operations the EEPROM
139must be configured to enable memory ops.
140
141III. Driver operation
142
143IIIa. Ring buffers
144
145This driver uses two statically allocated fixed-size descriptor lists
146formed into rings by a branch from the final descriptor to the beginning of
147the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
148
149IIIb/c. Transmit/Receive Structure
150
151This driver attempts to use a zero-copy receive and transmit scheme.
152
153Alas, all data buffers are required to start on a 32 bit boundary, so
154the driver must often copy transmit packets into bounce buffers.
155
156The driver allocates full frame size skbuffs for the Rx ring buffers at
157open() time and passes the skb->data field to the chip as receive data
158buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
159a fresh skbuff is allocated and the frame is copied to the new skbuff.
160When the incoming frame is larger, the skbuff is passed directly up the
161protocol stack. Buffers consumed this way are replaced by newly allocated
162skbuffs in the last phase of rhine_rx().
163
164The RX_COPYBREAK value is chosen to trade-off the memory wasted by
165using a full-sized skbuff for small frames vs. the copying costs of larger
166frames. New boards are typically used in generously configured machines
167and the underfilled buffers have negligible impact compared to the benefit of
168a single allocation size, so the default value of zero results in never
169copying packets. When copying is done, the cost is usually mitigated by using
170a combined copy/checksum routine. Copying also preloads the cache, which is
171most useful with small frames.
172
173Since the VIA chips are only able to transfer data to buffers on 32 bit
174boundaries, the IP header at offset 14 in an ethernet frame isn't
175longword aligned for further processing. Copying these unaligned buffers
176has the beneficial effect of 16-byte aligning the IP header.
177
178IIId. Synchronization
179
180The driver runs as two independent, single-threaded flows of control. One
181is the send-packet routine, which enforces single-threaded use by the
182dev->priv->lock spinlock. The other thread is the interrupt handler, which
183is single threaded by the hardware and interrupt handling software.
184
185The send packet thread has partial control over the Tx ring. It locks the
186dev->priv->lock whenever it's queuing a Tx packet. If the next slot in the ring
187is not available it stops the transmit queue by calling netif_stop_queue.
188
189The interrupt handler has exclusive control over the Rx ring and records stats
190from the Tx ring. After reaping the stats, it marks the Tx queue entry as
191empty by incrementing the dirty_tx mark. If at least half of the entries in
192the Rx ring are available the transmit queue is woken up if it was stopped.
193
194IV. Notes
195
196IVb. References
197
198Preliminary VT86C100A manual from http://www.via.com.tw/
199http://www.scyld.com/expert/100mbps.html
200http://www.scyld.com/expert/NWay.html
201ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
202ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
203
204
205IVc. Errata
206
207The VT86C100A manual is not reliable information.
208The 3043 chip does not handle unaligned transmit or receive buffers, resulting
209in significant performance degradation for bounce buffer copies on transmit
210and unaligned IP headers on receive.
211The chip does not pad to minimum transmit length.
212
213*/
214
215
216/* This table drives the PCI probe routines. It's mostly boilerplate in all
217 of the drivers, and will likely be provided by some future kernel.
218 Note the matching code -- the first table entry matchs all 56** cards but
219 second only the 1234 card.
220*/
221
222enum rhine_revs {
223 VT86C100A = 0x00,
224 VTunknown0 = 0x20,
225 VT6102 = 0x40,
226 VT8231 = 0x50, /* Integrated MAC */
227 VT8233 = 0x60, /* Integrated MAC */
228 VT8235 = 0x74, /* Integrated MAC */
229 VT8237 = 0x78, /* Integrated MAC */
230 VTunknown1 = 0x7C,
231 VT6105 = 0x80,
232 VT6105_B0 = 0x83,
233 VT6105L = 0x8A,
234 VT6107 = 0x8C,
235 VTunknown2 = 0x8E,
236 VT6105M = 0x90, /* Management adapter */
237};
238
239enum rhine_quirks {
240 rqWOL = 0x0001, /* Wake-On-LAN support */
241 rqForceReset = 0x0002,
242 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
243 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
244 rqRhineI = 0x0100, /* See comment below */
245};
246/*
247 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
248 * MMIO as well as for the collision counter and the Tx FIFO underflow
249 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
250 */
251
252/* Beware of PCI posted writes */
253#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
254
46009c8b
JG		 255static const struct pci_device_id rhine_pci_tbl[] = {
256 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
257 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
258 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
259 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
1da177e4
LT		 260 { } /* terminate list */
261};
262MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
263
264
265/* Offsets to the device registers. */
266enum register_offsets {
267 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
268 ChipCmd1=0x09,
269 IntrStatus=0x0C, IntrEnable=0x0E,
270 MulticastFilter0=0x10, MulticastFilter1=0x14,
271 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
272 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
273 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
274 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
275 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
276 StickyHW=0x83, IntrStatus2=0x84,
277 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
278 WOLcrClr1=0xA6, WOLcgClr=0xA7,
279 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
280};
281
282/* Bits in ConfigD */
283enum backoff_bits {
284 BackOptional=0x01, BackModify=0x02,
285 BackCaptureEffect=0x04, BackRandom=0x08
286};
287
288#ifdef USE_MMIO
289/* Registers we check that mmio and reg are the same. */
290static const int mmio_verify_registers[] = {
291 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
292 0
293};
294#endif
295
296/* Bits in the interrupt status/mask registers. */
297enum intr_status_bits {
298 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
299 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
300 IntrPCIErr=0x0040,
301 IntrStatsMax=0x0080, IntrRxEarly=0x0100,
302 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
303 IntrTxAborted=0x2000, IntrLinkChange=0x4000,
304 IntrRxWakeUp=0x8000,
305 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
306 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
307 IntrTxErrSummary=0x082218,
308};
309
310/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
311enum wol_bits {
312 WOLucast = 0x10,
313 WOLmagic = 0x20,
314 WOLbmcast = 0x30,
315 WOLlnkon = 0x40,
316 WOLlnkoff = 0x80,
317};
318
319/* The Rx and Tx buffer descriptors. */
320struct rx_desc {
321 s32 rx_status;
322 u32 desc_length; /* Chain flag, Buffer/frame length */
323 u32 addr;
324 u32 next_desc;
325};
326struct tx_desc {
327 s32 tx_status;
328 u32 desc_length; /* Chain flag, Tx Config, Frame length */
329 u32 addr;
330 u32 next_desc;
331};
332
333/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
334#define TXDESC 0x00e08000
335
336enum rx_status_bits {
337 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
338};
339
340/* Bits in *_desc.*_status */
341enum desc_status_bits {
342 DescOwn=0x80000000
343};
344
345/* Bits in ChipCmd. */
346enum chip_cmd_bits {
347 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
348 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
349 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
350 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
351};
352
353struct rhine_private {
354 /* Descriptor rings */
355 struct rx_desc *rx_ring;
356 struct tx_desc *tx_ring;
357 dma_addr_t rx_ring_dma;
358 dma_addr_t tx_ring_dma;
359
360 /* The addresses of receive-in-place skbuffs. */
361 struct sk_buff *rx_skbuff[RX_RING_SIZE];
362 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
363
364 /* The saved address of a sent-in-place packet/buffer, for later free(). */
365 struct sk_buff *tx_skbuff[TX_RING_SIZE];
366 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
367
4be5de25 368 /* Tx bounce buffers (Rhine-I only) */
1da177e4
LT		 369 unsigned char *tx_buf[TX_RING_SIZE];
370 unsigned char *tx_bufs;
371 dma_addr_t tx_bufs_dma;
372
373 struct pci_dev *pdev;
374 long pioaddr;
375 struct net_device_stats stats;
376 spinlock_t lock;
377
378 /* Frequently used values: keep some adjacent for cache effect. */
379 u32 quirks;
380 struct rx_desc *rx_head_desc;
381 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
382 unsigned int cur_tx, dirty_tx;
383 unsigned int rx_buf_sz; /* Based on MTU+slack. */
384 u8 wolopts;
385
386 u8 tx_thresh, rx_thresh;
387
388 struct mii_if_info mii_if;
389 void __iomem *base;
390};
391
392static int mdio_read(struct net_device *dev, int phy_id, int location);
393static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
394static int rhine_open(struct net_device *dev);
395static void rhine_tx_timeout(struct net_device *dev);
396static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev);
397static irqreturn_t rhine_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
398static void rhine_tx(struct net_device *dev);
399static void rhine_rx(struct net_device *dev);
400static void rhine_error(struct net_device *dev, int intr_status);
401static void rhine_set_rx_mode(struct net_device *dev);
402static struct net_device_stats *rhine_get_stats(struct net_device *dev);
403static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
404static struct ethtool_ops netdev_ethtool_ops;
405static int rhine_close(struct net_device *dev);
d18c3db5 406static void rhine_shutdown (struct pci_dev *pdev);
1da177e4
LT		 407
408#define RHINE_WAIT_FOR(condition) do { \
409 int i=1024; \
410 while (!(condition) && --i) \
411 ; \
412 if (debug > 1 && i < 512) \
413 printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
414 DRV_NAME, 1024-i, __func__, __LINE__); \
415} while(0)
416
417static inline u32 get_intr_status(struct net_device *dev)
418{
419 struct rhine_private *rp = netdev_priv(dev);
420 void __iomem *ioaddr = rp->base;
421 u32 intr_status;
422
423 intr_status = ioread16(ioaddr + IntrStatus);
424 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
425 if (rp->quirks & rqStatusWBRace)
426 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
427 return intr_status;
428}
429
430/*
431 * Get power related registers into sane state.
432 * Notify user about past WOL event.
433 */
434static void rhine_power_init(struct net_device *dev)
435{
436 struct rhine_private *rp = netdev_priv(dev);
437 void __iomem *ioaddr = rp->base;
438 u16 wolstat;
439
440 if (rp->quirks & rqWOL) {
441 /* Make sure chip is in power state D0 */
442 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
443
444 /* Disable "force PME-enable" */
445 iowrite8(0x80, ioaddr + WOLcgClr);
446
447 /* Clear power-event config bits (WOL) */
448 iowrite8(0xFF, ioaddr + WOLcrClr);
449 /* More recent cards can manage two additional patterns */
450 if (rp->quirks & rq6patterns)
451 iowrite8(0x03, ioaddr + WOLcrClr1);
452
453 /* Save power-event status bits */
454 wolstat = ioread8(ioaddr + PwrcsrSet);
455 if (rp->quirks & rq6patterns)
456 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
457
458 /* Clear power-event status bits */
459 iowrite8(0xFF, ioaddr + PwrcsrClr);
460 if (rp->quirks & rq6patterns)
461 iowrite8(0x03, ioaddr + PwrcsrClr1);
462
463 if (wolstat) {
464 char *reason;
465 switch (wolstat) {
466 case WOLmagic:
467 reason = "Magic packet";
468 break;
469 case WOLlnkon:
470 reason = "Link went up";
471 break;
472 case WOLlnkoff:
473 reason = "Link went down";
474 break;
475 case WOLucast:
476 reason = "Unicast packet";
477 break;
478 case WOLbmcast:
479 reason = "Multicast/broadcast packet";
480 break;
481 default:
482 reason = "Unknown";
483 }
484 printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
485 DRV_NAME, reason);
486 }
487 }
488}
489
490static void rhine_chip_reset(struct net_device *dev)
491{
492 struct rhine_private *rp = netdev_priv(dev);
493 void __iomem *ioaddr = rp->base;
494
495 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
496 IOSYNC;
497
498 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
499 printk(KERN_INFO "%s: Reset not complete yet. "
500 "Trying harder.\n", DRV_NAME);
501
502 /* Force reset */
503 if (rp->quirks & rqForceReset)
504 iowrite8(0x40, ioaddr + MiscCmd);
505
506 /* Reset can take somewhat longer (rare) */
507 RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
508 }
509
510 if (debug > 1)
511 printk(KERN_INFO "%s: Reset %s.\n", dev->name,
512 (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
513 "failed" : "succeeded");
514}
515
516#ifdef USE_MMIO
517static void enable_mmio(long pioaddr, u32 quirks)
518{
519 int n;
520 if (quirks & rqRhineI) {
521 /* More recent docs say that this bit is reserved ... */
522 n = inb(pioaddr + ConfigA) | 0x20;
523 outb(n, pioaddr + ConfigA);
524 } else {
525 n = inb(pioaddr + ConfigD) | 0x80;
526 outb(n, pioaddr + ConfigD);
527 }
528}
529#endif
530
531/*
532 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
533 * (plus 0x6C for Rhine-I/II)
534 */
535static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
536{
537 struct rhine_private *rp = netdev_priv(dev);
538 void __iomem *ioaddr = rp->base;
539
540 outb(0x20, pioaddr + MACRegEEcsr);
541 RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
542
543#ifdef USE_MMIO
544 /*
545 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
546 * MMIO. If reloading EEPROM was done first this could be avoided, but
547 * it is not known if that still works with the "win98-reboot" problem.
548 */
549 enable_mmio(pioaddr, rp->quirks);
550#endif
551
552 /* Turn off EEPROM-controlled wake-up (magic packet) */
553 if (rp->quirks & rqWOL)
554 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
555
556}
557
558#ifdef CONFIG_NET_POLL_CONTROLLER
559static void rhine_poll(struct net_device *dev)
560{
561 disable_irq(dev->irq);
562 rhine_interrupt(dev->irq, (void *)dev, NULL);
563 enable_irq(dev->irq);
564}
565#endif
566
567static void rhine_hw_init(struct net_device *dev, long pioaddr)
568{
569 struct rhine_private *rp = netdev_priv(dev);
570
571 /* Reset the chip to erase previous misconfiguration. */
572 rhine_chip_reset(dev);
573
574 /* Rhine-I needs extra time to recuperate before EEPROM reload */
575 if (rp->quirks & rqRhineI)
576 msleep(5);
577
578 /* Reload EEPROM controlled bytes cleared by soft reset */
579 rhine_reload_eeprom(pioaddr, dev);
580}
581
582static int __devinit rhine_init_one(struct pci_dev *pdev,
583 const struct pci_device_id *ent)
584{
585 struct net_device *dev;
586 struct rhine_private *rp;
587 int i, rc;
588 u8 pci_rev;
589 u32 quirks;
590 long pioaddr;
591 long memaddr;
592 void __iomem *ioaddr;
593 int io_size, phy_id;
594 const char *name;
595#ifdef USE_MMIO
596 int bar = 1;
597#else
598 int bar = 0;
599#endif
600
601/* when built into the kernel, we only print version if device is found */
602#ifndef MODULE
603 static int printed_version;
604 if (!printed_version++)
605 printk(version);
606#endif
607
608 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
609
610 io_size = 256;
611 phy_id = 0;
612 quirks = 0;
613 name = "Rhine";
614 if (pci_rev < VTunknown0) {
615 quirks = rqRhineI;
616 io_size = 128;
617 }
618 else if (pci_rev >= VT6102) {
619 quirks = rqWOL | rqForceReset;
620 if (pci_rev < VT6105) {
621 name = "Rhine II";
622 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
623 }
624 else {
625 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
626 if (pci_rev >= VT6105_B0)
627 quirks |= rq6patterns;
628 if (pci_rev < VT6105M)
629 name = "Rhine III";
630 else
631 name = "Rhine III (Management Adapter)";
632 }
633 }
634
635 rc = pci_enable_device(pdev);
636 if (rc)
637 goto err_out;
638
639 /* this should always be supported */
1e7f0bd8 640 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4
LT		 641 if (rc) {
642 printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
643 "the card!?\n");
644 goto err_out;
645 }
646
647 /* sanity check */
648 if ((pci_resource_len(pdev, 0) < io_size) ||
649 (pci_resource_len(pdev, 1) < io_size)) {
650 rc = -EIO;
651 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
652 goto err_out;
653 }
654
655 pioaddr = pci_resource_start(pdev, 0);
656 memaddr = pci_resource_start(pdev, 1);
657
658 pci_set_master(pdev);
659
660 dev = alloc_etherdev(sizeof(struct rhine_private));
661 if (!dev) {
662 rc = -ENOMEM;
663 printk(KERN_ERR "alloc_etherdev failed\n");
664 goto err_out;
665 }
666 SET_MODULE_OWNER(dev);
667 SET_NETDEV_DEV(dev, &pdev->dev);
668
669 rp = netdev_priv(dev);
670 rp->quirks = quirks;
671 rp->pioaddr = pioaddr;
672 rp->pdev = pdev;
673
674 rc = pci_request_regions(pdev, DRV_NAME);
675 if (rc)
676 goto err_out_free_netdev;
677
678 ioaddr = pci_iomap(pdev, bar, io_size);
679 if (!ioaddr) {
680 rc = -EIO;
681 printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
682 "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
683 goto err_out_free_res;
684 }
685
686#ifdef USE_MMIO
687 enable_mmio(pioaddr, quirks);
688
689 /* Check that selected MMIO registers match the PIO ones */
690 i = 0;
691 while (mmio_verify_registers[i]) {
692 int reg = mmio_verify_registers[i++];
693 unsigned char a = inb(pioaddr+reg);
694 unsigned char b = readb(ioaddr+reg);
695 if (a != b) {
696 rc = -EIO;
697 printk(KERN_ERR "MMIO do not match PIO [%02x] "
698 "(%02x != %02x)\n", reg, a, b);
699 goto err_out_unmap;
700 }
701 }
702#endif /* USE_MMIO */
703
704 dev->base_addr = (unsigned long)ioaddr;
705 rp->base = ioaddr;
706
707 /* Get chip registers into a sane state */
708 rhine_power_init(dev);
709 rhine_hw_init(dev, pioaddr);
710
711 for (i = 0; i < 6; i++)
712 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
b81e8e1f 713 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 714
b81e8e1f 715 if (!is_valid_ether_addr(dev->perm_addr)) {
1da177e4
LT		 716 rc = -EIO;
717 printk(KERN_ERR "Invalid MAC address\n");
718 goto err_out_unmap;
719 }
720
721 /* For Rhine-I/II, phy_id is loaded from EEPROM */
722 if (!phy_id)
723 phy_id = ioread8(ioaddr + 0x6C);
724
725 dev->irq = pdev->irq;
726
727 spin_lock_init(&rp->lock);
728 rp->mii_if.dev = dev;
729 rp->mii_if.mdio_read = mdio_read;
730 rp->mii_if.mdio_write = mdio_write;
731 rp->mii_if.phy_id_mask = 0x1f;
732 rp->mii_if.reg_num_mask = 0x1f;
733
734 /* The chip-specific entries in the device structure. */
735 dev->open = rhine_open;
736 dev->hard_start_xmit = rhine_start_tx;
737 dev->stop = rhine_close;
738 dev->get_stats = rhine_get_stats;
739 dev->set_multicast_list = rhine_set_rx_mode;
740 dev->do_ioctl = netdev_ioctl;
741 dev->ethtool_ops = &netdev_ethtool_ops;
742 dev->tx_timeout = rhine_tx_timeout;
743 dev->watchdog_timeo = TX_TIMEOUT;
744#ifdef CONFIG_NET_POLL_CONTROLLER
745 dev->poll_controller = rhine_poll;
746#endif
747 if (rp->quirks & rqRhineI)
748 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
749
750 /* dev->name not defined before register_netdev()! */
751 rc = register_netdev(dev);
752 if (rc)
753 goto err_out_unmap;
754
755 printk(KERN_INFO "%s: VIA %s at 0x%lx, ",
756 dev->name, name,
757#ifdef USE_MMIO
758 memaddr
759#else
760 (long)ioaddr
761#endif
762 );
763
764 for (i = 0; i < 5; i++)
765 printk("%2.2x:", dev->dev_addr[i]);
766 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], pdev->irq);
767
768 pci_set_drvdata(pdev, dev);
769
770 {
771 u16 mii_cmd;
772 int mii_status = mdio_read(dev, phy_id, 1);
773 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
774 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
775 if (mii_status != 0xffff && mii_status != 0x0000) {
776 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
777 printk(KERN_INFO "%s: MII PHY found at address "
778 "%d, status 0x%4.4x advertising %4.4x "
779 "Link %4.4x.\n", dev->name, phy_id,
780 mii_status, rp->mii_if.advertising,
781 mdio_read(dev, phy_id, 5));
782
783 /* set IFF_RUNNING */
784 if (mii_status & BMSR_LSTATUS)
785 netif_carrier_on(dev);
786 else
787 netif_carrier_off(dev);
788
789 }
790 }
791 rp->mii_if.phy_id = phy_id;
792
793 return 0;
794
795err_out_unmap:
796 pci_iounmap(pdev, ioaddr);
797err_out_free_res:
798 pci_release_regions(pdev);
799err_out_free_netdev:
800 free_netdev(dev);
801err_out:
802 return rc;
803}
804
805static int alloc_ring(struct net_device* dev)
806{
807 struct rhine_private *rp = netdev_priv(dev);
808 void *ring;
809 dma_addr_t ring_dma;
810
811 ring = pci_alloc_consistent(rp->pdev,
812 RX_RING_SIZE * sizeof(struct rx_desc) +
813 TX_RING_SIZE * sizeof(struct tx_desc),
814 &ring_dma);
815 if (!ring) {
816 printk(KERN_ERR "Could not allocate DMA memory.\n");
817 return -ENOMEM;
818 }
819 if (rp->quirks & rqRhineI) {
820 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
821 PKT_BUF_SZ * TX_RING_SIZE,
822 &rp->tx_bufs_dma);
823 if (rp->tx_bufs == NULL) {
824 pci_free_consistent(rp->pdev,
825 RX_RING_SIZE * sizeof(struct rx_desc) +
826 TX_RING_SIZE * sizeof(struct tx_desc),
827 ring, ring_dma);
828 return -ENOMEM;
829 }
830 }
831
832 rp->rx_ring = ring;
833 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
834 rp->rx_ring_dma = ring_dma;
835 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
836
837 return 0;
838}
839
840static void free_ring(struct net_device* dev)
841{
842 struct rhine_private *rp = netdev_priv(dev);
843
844 pci_free_consistent(rp->pdev,
845 RX_RING_SIZE * sizeof(struct rx_desc) +
846 TX_RING_SIZE * sizeof(struct tx_desc),
847 rp->rx_ring, rp->rx_ring_dma);
848 rp->tx_ring = NULL;
849
850 if (rp->tx_bufs)
851 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
852 rp->tx_bufs, rp->tx_bufs_dma);
853
854 rp->tx_bufs = NULL;
855
856}
857
858static void alloc_rbufs(struct net_device *dev)
859{
860 struct rhine_private *rp = netdev_priv(dev);
861 dma_addr_t next;
862 int i;
863
864 rp->dirty_rx = rp->cur_rx = 0;
865
866 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
867 rp->rx_head_desc = &rp->rx_ring[0];
868 next = rp->rx_ring_dma;
869
870 /* Init the ring entries */
871 for (i = 0; i < RX_RING_SIZE; i++) {
872 rp->rx_ring[i].rx_status = 0;
873 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
874 next += sizeof(struct rx_desc);
875 rp->rx_ring[i].next_desc = cpu_to_le32(next);
876 rp->rx_skbuff[i] = NULL;
877 }
878 /* Mark the last entry as wrapping the ring. */
879 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
880
881 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
882 for (i = 0; i < RX_RING_SIZE; i++) {
883 struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz);
884 rp->rx_skbuff[i] = skb;
885 if (skb == NULL)
886 break;
887 skb->dev = dev; /* Mark as being used by this device. */
888
889 rp->rx_skbuff_dma[i] =
689be439 890 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
1da177e4
LT		 891 PCI_DMA_FROMDEVICE);
892
893 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
894 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
895 }
896 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
897}
898
899static void free_rbufs(struct net_device* dev)
900{
901 struct rhine_private *rp = netdev_priv(dev);
902 int i;
903
904 /* Free all the skbuffs in the Rx queue. */
905 for (i = 0; i < RX_RING_SIZE; i++) {
906 rp->rx_ring[i].rx_status = 0;
907 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
908 if (rp->rx_skbuff[i]) {
909 pci_unmap_single(rp->pdev,
910 rp->rx_skbuff_dma[i],
911 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
912 dev_kfree_skb(rp->rx_skbuff[i]);
913 }
914 rp->rx_skbuff[i] = NULL;
915 }
916}
917
918static void alloc_tbufs(struct net_device* dev)
919{
920 struct rhine_private *rp = netdev_priv(dev);
921 dma_addr_t next;
922 int i;
923
924 rp->dirty_tx = rp->cur_tx = 0;
925 next = rp->tx_ring_dma;
926 for (i = 0; i < TX_RING_SIZE; i++) {
927 rp->tx_skbuff[i] = NULL;
928 rp->tx_ring[i].tx_status = 0;
929 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
930 next += sizeof(struct tx_desc);
931 rp->tx_ring[i].next_desc = cpu_to_le32(next);
4be5de25
RL		 932 if (rp->quirks & rqRhineI)
933 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
1da177e4
LT		 934 }
935 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
936
937}
938
939static void free_tbufs(struct net_device* dev)
940{
941 struct rhine_private *rp = netdev_priv(dev);
942 int i;
943
944 for (i = 0; i < TX_RING_SIZE; i++) {
945 rp->tx_ring[i].tx_status = 0;
946 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
947 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
948 if (rp->tx_skbuff[i]) {
949 if (rp->tx_skbuff_dma[i]) {
950 pci_unmap_single(rp->pdev,
951 rp->tx_skbuff_dma[i],
952 rp->tx_skbuff[i]->len,
953 PCI_DMA_TODEVICE);
954 }
955 dev_kfree_skb(rp->tx_skbuff[i]);
956 }
957 rp->tx_skbuff[i] = NULL;
958 rp->tx_buf[i] = NULL;
959 }
960}
961
962static void rhine_check_media(struct net_device *dev, unsigned int init_media)
963{
964 struct rhine_private *rp = netdev_priv(dev);
965 void __iomem *ioaddr = rp->base;
966
967 mii_check_media(&rp->mii_if, debug, init_media);
968
969 if (rp->mii_if.full_duplex)
970 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
971 ioaddr + ChipCmd1);
972 else
973 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
974 ioaddr + ChipCmd1);
00b428c2
RL		 975 if (debug > 1)
976 printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name,
977 rp->mii_if.force_media, netif_carrier_ok(dev));
978}
979
980/* Called after status of force_media possibly changed */
0761be4f 981static void rhine_set_carrier(struct mii_if_info *mii)
00b428c2
RL		 982{
983 if (mii->force_media) {
984 /* autoneg is off: Link is always assumed to be up */
985 if (!netif_carrier_ok(mii->dev))
986 netif_carrier_on(mii->dev);
987 }
988 else /* Let MMI library update carrier status */
989 rhine_check_media(mii->dev, 0);
990 if (debug > 1)
991 printk(KERN_INFO "%s: force_media %d, carrier %d\n",
992 mii->dev->name, mii->force_media,
993 netif_carrier_ok(mii->dev));
1da177e4
LT		 994}
995
996static void init_registers(struct net_device *dev)
997{
998 struct rhine_private *rp = netdev_priv(dev);
999 void __iomem *ioaddr = rp->base;
1000 int i;
1001
1002 for (i = 0; i < 6; i++)
1003 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1004
1005 /* Initialize other registers. */
1006 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1007 /* Configure initial FIFO thresholds. */
1008 iowrite8(0x20, ioaddr + TxConfig);
1009 rp->tx_thresh = 0x20;
1010 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1011
1012 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1013 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1014
1015 rhine_set_rx_mode(dev);
1016
1017 /* Enable interrupts by setting the interrupt mask. */
1018 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1019 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1020 IntrTxDone | IntrTxError | IntrTxUnderrun |
1021 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1022 ioaddr + IntrEnable);
1023
1024 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1025 ioaddr + ChipCmd);
1026 rhine_check_media(dev, 1);
1027}
1028
1029/* Enable MII link status auto-polling (required for IntrLinkChange) */
1030static void rhine_enable_linkmon(void __iomem *ioaddr)
1031{
1032 iowrite8(0, ioaddr + MIICmd);
1033 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1034 iowrite8(0x80, ioaddr + MIICmd);
1035
1036 RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1037
1038 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1039}
1040
1041/* Disable MII link status auto-polling (required for MDIO access) */
1042static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1043{
1044 iowrite8(0, ioaddr + MIICmd);
1045
1046 if (quirks & rqRhineI) {
1047 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1048
38bb6b28
JL		 1049 /* Can be called from ISR. Evil. */
1050 mdelay(1);
1da177e4
LT		 1051
1052 /* 0x80 must be set immediately before turning it off */
1053 iowrite8(0x80, ioaddr + MIICmd);
1054
1055 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1056
1057 /* Heh. Now clear 0x80 again. */
1058 iowrite8(0, ioaddr + MIICmd);
1059 }
1060 else
1061 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1062}
1063
1064/* Read and write over the MII Management Data I/O (MDIO) interface. */
1065
1066static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1067{
1068 struct rhine_private *rp = netdev_priv(dev);
1069 void __iomem *ioaddr = rp->base;
1070 int result;
1071
1072 rhine_disable_linkmon(ioaddr, rp->quirks);
1073
1074 /* rhine_disable_linkmon already cleared MIICmd */
1075 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1076 iowrite8(regnum, ioaddr + MIIRegAddr);
1077 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1078 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1079 result = ioread16(ioaddr + MIIData);
1080
1081 rhine_enable_linkmon(ioaddr);
1082 return result;
1083}
1084
1085static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1086{
1087 struct rhine_private *rp = netdev_priv(dev);
1088 void __iomem *ioaddr = rp->base;
1089
1090 rhine_disable_linkmon(ioaddr, rp->quirks);
1091
1092 /* rhine_disable_linkmon already cleared MIICmd */
1093 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1094 iowrite8(regnum, ioaddr + MIIRegAddr);
1095 iowrite16(value, ioaddr + MIIData);
1096 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1097 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1098
1099 rhine_enable_linkmon(ioaddr);
1100}
1101
1102static int rhine_open(struct net_device *dev)
1103{
1104 struct rhine_private *rp = netdev_priv(dev);
1105 void __iomem *ioaddr = rp->base;
1106 int rc;
1107
1fb9df5d 1108 rc = request_irq(rp->pdev->irq, &rhine_interrupt, IRQF_SHARED, dev->name,
1da177e4
LT		 1109 dev);
1110 if (rc)
1111 return rc;
1112
1113 if (debug > 1)
1114 printk(KERN_DEBUG "%s: rhine_open() irq %d.\n",
1115 dev->name, rp->pdev->irq);
1116
1117 rc = alloc_ring(dev);
1118 if (rc) {
1119 free_irq(rp->pdev->irq, dev);
1120 return rc;
1121 }
1122 alloc_rbufs(dev);
1123 alloc_tbufs(dev);
1124 rhine_chip_reset(dev);
1125 init_registers(dev);
1126 if (debug > 2)
1127 printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
1128 "MII status: %4.4x.\n",
1129 dev->name, ioread16(ioaddr + ChipCmd),
1130 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1131
1132 netif_start_queue(dev);
1133
1134 return 0;
1135}
1136
1137static void rhine_tx_timeout(struct net_device *dev)
1138{
1139 struct rhine_private *rp = netdev_priv(dev);
1140 void __iomem *ioaddr = rp->base;
1141
1142 printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status "
1143 "%4.4x, resetting...\n",
1144 dev->name, ioread16(ioaddr + IntrStatus),
1145 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1146
1147 /* protect against concurrent rx interrupts */
1148 disable_irq(rp->pdev->irq);
1149
1150 spin_lock(&rp->lock);
1151
1152 /* clear all descriptors */
1153 free_tbufs(dev);
1154 free_rbufs(dev);
1155 alloc_tbufs(dev);
1156 alloc_rbufs(dev);
1157
1158 /* Reinitialize the hardware. */
1159 rhine_chip_reset(dev);
1160 init_registers(dev);
1161
1162 spin_unlock(&rp->lock);
1163 enable_irq(rp->pdev->irq);
1164
1165 dev->trans_start = jiffies;
1166 rp->stats.tx_errors++;
1167 netif_wake_queue(dev);
1168}
1169
1170static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev)
1171{
1172 struct rhine_private *rp = netdev_priv(dev);
1173 void __iomem *ioaddr = rp->base;
1174 unsigned entry;
1175
1176 /* Caution: the write order is important here, set the field
1177 with the "ownership" bits last. */
1178
1179 /* Calculate the next Tx descriptor entry. */
1180 entry = rp->cur_tx % TX_RING_SIZE;
1181
5b057c6b
HX		 1182 if (skb_padto(skb, ETH_ZLEN))
1183 return 0;
1da177e4
LT		 1184
1185 rp->tx_skbuff[entry] = skb;
1186
1187 if ((rp->quirks & rqRhineI) &&
1188 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_HW)) {
1189 /* Must use alignment buffer. */
1190 if (skb->len > PKT_BUF_SZ) {
1191 /* packet too long, drop it */
1192 dev_kfree_skb(skb);
1193 rp->tx_skbuff[entry] = NULL;
1194 rp->stats.tx_dropped++;
1195 return 0;
1196 }
3e0d167a
CB		 1197
1198 /* Padding is not copied and so must be redone. */
1da177e4 1199 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
3e0d167a
CB		 1200 if (skb->len < ETH_ZLEN)
1201 memset(rp->tx_buf[entry] + skb->len, 0,
1202 ETH_ZLEN - skb->len);
1da177e4
LT		 1203 rp->tx_skbuff_dma[entry] = 0;
1204 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1205 (rp->tx_buf[entry] -
1206 rp->tx_bufs));
1207 } else {
1208 rp->tx_skbuff_dma[entry] =
1209 pci_map_single(rp->pdev, skb->data, skb->len,
1210 PCI_DMA_TODEVICE);
1211 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1212 }
1213
1214 rp->tx_ring[entry].desc_length =
1215 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1216
1217 /* lock eth irq */
1218 spin_lock_irq(&rp->lock);
1219 wmb();
1220 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1221 wmb();
1222
1223 rp->cur_tx++;
1224
1225 /* Non-x86 Todo: explicitly flush cache lines here. */
1226
1227 /* Wake the potentially-idle transmit channel */
1228 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1229 ioaddr + ChipCmd1);
1230 IOSYNC;
1231
1232 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1233 netif_stop_queue(dev);
1234
1235 dev->trans_start = jiffies;
1236
1237 spin_unlock_irq(&rp->lock);
1238
1239 if (debug > 4) {
1240 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1241 dev->name, rp->cur_tx-1, entry);
1242 }
1243 return 0;
1244}
1245
1246/* The interrupt handler does all of the Rx thread work and cleans up
1247 after the Tx thread. */
1248static irqreturn_t rhine_interrupt(int irq, void *dev_instance, struct pt_regs *rgs)
1249{
1250 struct net_device *dev = dev_instance;
1251 struct rhine_private *rp = netdev_priv(dev);
1252 void __iomem *ioaddr = rp->base;
1253 u32 intr_status;
1254 int boguscnt = max_interrupt_work;
1255 int handled = 0;
1256
1257 while ((intr_status = get_intr_status(dev))) {
1258 handled = 1;
1259
1260 /* Acknowledge all of the current interrupt sources ASAP. */
1261 if (intr_status & IntrTxDescRace)
1262 iowrite8(0x08, ioaddr + IntrStatus2);
1263 iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1264 IOSYNC;
1265
1266 if (debug > 4)
1267 printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n",
1268 dev->name, intr_status);
1269
1270 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
1271 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf))
1272 rhine_rx(dev);
1273
1274 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1275 if (intr_status & IntrTxErrSummary) {
1276 /* Avoid scavenging before Tx engine turned off */
1277 RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1278 if (debug > 2 &&
1279 ioread8(ioaddr+ChipCmd) & CmdTxOn)
1280 printk(KERN_WARNING "%s: "
1281 "rhine_interrupt() Tx engine"
1282 "still on.\n", dev->name);
1283 }
1284 rhine_tx(dev);
1285 }
1286
1287 /* Abnormal error summary/uncommon events handlers. */
1288 if (intr_status & (IntrPCIErr | IntrLinkChange |
1289 IntrStatsMax | IntrTxError | IntrTxAborted |
1290 IntrTxUnderrun | IntrTxDescRace))
1291 rhine_error(dev, intr_status);
1292
1293 if (--boguscnt < 0) {
1294 printk(KERN_WARNING "%s: Too much work at interrupt, "
1295 "status=%#8.8x.\n",
1296 dev->name, intr_status);
1297 break;
1298 }
1299 }
1300
1301 if (debug > 3)
1302 printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n",
1303 dev->name, ioread16(ioaddr + IntrStatus));
1304 return IRQ_RETVAL(handled);
1305}
1306
1307/* This routine is logically part of the interrupt handler, but isolated
1308 for clarity. */
1309static void rhine_tx(struct net_device *dev)
1310{
1311 struct rhine_private *rp = netdev_priv(dev);
1312 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1313
1314 spin_lock(&rp->lock);
1315
1316 /* find and cleanup dirty tx descriptors */
1317 while (rp->dirty_tx != rp->cur_tx) {
1318 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1319 if (debug > 6)
ed4030d1 1320 printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
1da177e4
LT		 1321 entry, txstatus);
1322 if (txstatus & DescOwn)
1323 break;
1324 if (txstatus & 0x8000) {
1325 if (debug > 1)
1326 printk(KERN_DEBUG "%s: Transmit error, "
1327 "Tx status %8.8x.\n",
1328 dev->name, txstatus);
1329 rp->stats.tx_errors++;
1330 if (txstatus & 0x0400) rp->stats.tx_carrier_errors++;
1331 if (txstatus & 0x0200) rp->stats.tx_window_errors++;
1332 if (txstatus & 0x0100) rp->stats.tx_aborted_errors++;
1333 if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++;
1334 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1335 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1336 rp->stats.tx_fifo_errors++;
1337 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1338 break; /* Keep the skb - we try again */
1339 }
1340 /* Transmitter restarted in 'abnormal' handler. */
1341 } else {
1342 if (rp->quirks & rqRhineI)
1343 rp->stats.collisions += (txstatus >> 3) & 0x0F;
1344 else
1345 rp->stats.collisions += txstatus & 0x0F;
1346 if (debug > 6)
1347 printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n",
1348 (txstatus >> 3) & 0xF,
1349 txstatus & 0xF);
1350 rp->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1351 rp->stats.tx_packets++;
1352 }
1353 /* Free the original skb. */
1354 if (rp->tx_skbuff_dma[entry]) {
1355 pci_unmap_single(rp->pdev,
1356 rp->tx_skbuff_dma[entry],
1357 rp->tx_skbuff[entry]->len,
1358 PCI_DMA_TODEVICE);
1359 }
1360 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1361 rp->tx_skbuff[entry] = NULL;
1362 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1363 }
1364 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1365 netif_wake_queue(dev);
1366
1367 spin_unlock(&rp->lock);
1368}
1369
1370/* This routine is logically part of the interrupt handler, but isolated
1371 for clarity and better register allocation. */
1372static void rhine_rx(struct net_device *dev)
1373{
1374 struct rhine_private *rp = netdev_priv(dev);
1375 int entry = rp->cur_rx % RX_RING_SIZE;
1376 int boguscnt = rp->dirty_rx + RX_RING_SIZE - rp->cur_rx;
1377
1378 if (debug > 4) {
1379 printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n",
1380 dev->name, entry,
1381 le32_to_cpu(rp->rx_head_desc->rx_status));
1382 }
1383
1384 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1385 while (!(rp->rx_head_desc->rx_status & cpu_to_le32(DescOwn))) {
1386 struct rx_desc *desc = rp->rx_head_desc;
1387 u32 desc_status = le32_to_cpu(desc->rx_status);
1388 int data_size = desc_status >> 16;
1389
1390 if (debug > 4)
ed4030d1 1391 printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
1da177e4
LT		 1392 desc_status);
1393 if (--boguscnt < 0)
1394 break;
1395 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1396 if ((desc_status & RxWholePkt) != RxWholePkt) {
1397 printk(KERN_WARNING "%s: Oversized Ethernet "
1398 "frame spanned multiple buffers, entry "
1399 "%#x length %d status %8.8x!\n",
1400 dev->name, entry, data_size,
1401 desc_status);
1402 printk(KERN_WARNING "%s: Oversized Ethernet "
1403 "frame %p vs %p.\n", dev->name,
1404 rp->rx_head_desc, &rp->rx_ring[entry]);
1405 rp->stats.rx_length_errors++;
1406 } else if (desc_status & RxErr) {
1407 /* There was a error. */
1408 if (debug > 2)
ed4030d1 1409 printk(KERN_DEBUG "rhine_rx() Rx "
1da177e4
LT		 1410 "error was %8.8x.\n",
1411 desc_status);
1412 rp->stats.rx_errors++;
1413 if (desc_status & 0x0030) rp->stats.rx_length_errors++;
1414 if (desc_status & 0x0048) rp->stats.rx_fifo_errors++;
1415 if (desc_status & 0x0004) rp->stats.rx_frame_errors++;
1416 if (desc_status & 0x0002) {
1417 /* this can also be updated outside the interrupt handler */
1418 spin_lock(&rp->lock);
1419 rp->stats.rx_crc_errors++;
1420 spin_unlock(&rp->lock);
1421 }
1422 }
1423 } else {
1424 struct sk_buff *skb;
1425 /* Length should omit the CRC */
1426 int pkt_len = data_size - 4;
1427
1428 /* Check if the packet is long enough to accept without
1429 copying to a minimally-sized skbuff. */
1430 if (pkt_len < rx_copybreak &&
1431 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1432 skb->dev = dev;
1433 skb_reserve(skb, 2); /* 16 byte align the IP header */
1434 pci_dma_sync_single_for_cpu(rp->pdev,
1435 rp->rx_skbuff_dma[entry],
1436 rp->rx_buf_sz,
1437 PCI_DMA_FROMDEVICE);
1438
1439 eth_copy_and_sum(skb,
689be439 1440 rp->rx_skbuff[entry]->data,
1da177e4
LT		 1441 pkt_len, 0);
1442 skb_put(skb, pkt_len);
1443 pci_dma_sync_single_for_device(rp->pdev,
1444 rp->rx_skbuff_dma[entry],
1445 rp->rx_buf_sz,
1446 PCI_DMA_FROMDEVICE);
1447 } else {
1448 skb = rp->rx_skbuff[entry];
1449 if (skb == NULL) {
1450 printk(KERN_ERR "%s: Inconsistent Rx "
1451 "descriptor chain.\n",
1452 dev->name);
1453 break;
1454 }
1455 rp->rx_skbuff[entry] = NULL;
1456 skb_put(skb, pkt_len);
1457 pci_unmap_single(rp->pdev,
1458 rp->rx_skbuff_dma[entry],
1459 rp->rx_buf_sz,
1460 PCI_DMA_FROMDEVICE);
1461 }
1462 skb->protocol = eth_type_trans(skb, dev);
1463 netif_rx(skb);
1464 dev->last_rx = jiffies;
1465 rp->stats.rx_bytes += pkt_len;
1466 rp->stats.rx_packets++;
1467 }
1468 entry = (++rp->cur_rx) % RX_RING_SIZE;
1469 rp->rx_head_desc = &rp->rx_ring[entry];
1470 }
1471
1472 /* Refill the Rx ring buffers. */
1473 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1474 struct sk_buff *skb;
1475 entry = rp->dirty_rx % RX_RING_SIZE;
1476 if (rp->rx_skbuff[entry] == NULL) {
1477 skb = dev_alloc_skb(rp->rx_buf_sz);
1478 rp->rx_skbuff[entry] = skb;
1479 if (skb == NULL)
1480 break; /* Better luck next round. */
1481 skb->dev = dev; /* Mark as being used by this device. */
1482 rp->rx_skbuff_dma[entry] =
689be439 1483 pci_map_single(rp->pdev, skb->data,
1da177e4
LT		 1484 rp->rx_buf_sz,
1485 PCI_DMA_FROMDEVICE);
1486 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1487 }
1488 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1489 }
1490}
1491
1492/*
1493 * Clears the "tally counters" for CRC errors and missed frames(?).
1494 * It has been reported that some chips need a write of 0 to clear
1495 * these, for others the counters are set to 1 when written to and
1496 * instead cleared when read. So we clear them both ways ...
1497 */
1498static inline void clear_tally_counters(void __iomem *ioaddr)
1499{
1500 iowrite32(0, ioaddr + RxMissed);
1501 ioread16(ioaddr + RxCRCErrs);
1502 ioread16(ioaddr + RxMissed);
1503}
1504
1505static void rhine_restart_tx(struct net_device *dev) {
1506 struct rhine_private *rp = netdev_priv(dev);
1507 void __iomem *ioaddr = rp->base;
1508 int entry = rp->dirty_tx % TX_RING_SIZE;
1509 u32 intr_status;
1510
1511 /*
1512 * If new errors occured, we need to sort them out before doing Tx.
1513 * In that case the ISR will be back here RSN anyway.
1514 */
1515 intr_status = get_intr_status(dev);
1516
1517 if ((intr_status & IntrTxErrSummary) == 0) {
1518
1519 /* We know better than the chip where it should continue. */
1520 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1521 ioaddr + TxRingPtr);
1522
1523 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1524 ioaddr + ChipCmd);
1525 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1526 ioaddr + ChipCmd1);
1527 IOSYNC;
1528 }
1529 else {
1530 /* This should never happen */
1531 if (debug > 1)
1532 printk(KERN_WARNING "%s: rhine_restart_tx() "
1533 "Another error occured %8.8x.\n",
1534 dev->name, intr_status);
1535 }
1536
1537}
1538
1539static void rhine_error(struct net_device *dev, int intr_status)
1540{
1541 struct rhine_private *rp = netdev_priv(dev);
1542 void __iomem *ioaddr = rp->base;
1543
1544 spin_lock(&rp->lock);
1545
1546 if (intr_status & IntrLinkChange)
38bb6b28 1547 rhine_check_media(dev, 0);
1da177e4
LT		 1548 if (intr_status & IntrStatsMax) {
1549 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1550 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1551 clear_tally_counters(ioaddr);
1552 }
1553 if (intr_status & IntrTxAborted) {
1554 if (debug > 1)
1555 printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n",
1556 dev->name, intr_status);
1557 }
1558 if (intr_status & IntrTxUnderrun) {
1559 if (rp->tx_thresh < 0xE0)
1560 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1561 if (debug > 1)
1562 printk(KERN_INFO "%s: Transmitter underrun, Tx "
1563 "threshold now %2.2x.\n",
1564 dev->name, rp->tx_thresh);
1565 }
1566 if (intr_status & IntrTxDescRace) {
1567 if (debug > 2)
1568 printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
1569 dev->name);
1570 }
1571 if ((intr_status & IntrTxError) &&
1572 (intr_status & (IntrTxAborted |
1573 IntrTxUnderrun | IntrTxDescRace)) == 0) {
1574 if (rp->tx_thresh < 0xE0) {
1575 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1576 }
1577 if (debug > 1)
1578 printk(KERN_INFO "%s: Unspecified error. Tx "
1579 "threshold now %2.2x.\n",
1580 dev->name, rp->tx_thresh);
1581 }
1582 if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1583 IntrTxError))
1584 rhine_restart_tx(dev);
1585
1586 if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1587 IntrTxError | IntrTxAborted | IntrNormalSummary |
1588 IntrTxDescRace)) {
1589 if (debug > 1)
1590 printk(KERN_ERR "%s: Something Wicked happened! "
1591 "%8.8x.\n", dev->name, intr_status);
1592 }
1593
1594 spin_unlock(&rp->lock);
1595}
1596
1597static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1598{
1599 struct rhine_private *rp = netdev_priv(dev);
1600 void __iomem *ioaddr = rp->base;
1601 unsigned long flags;
1602
1603 spin_lock_irqsave(&rp->lock, flags);
1604 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1605 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1606 clear_tally_counters(ioaddr);
1607 spin_unlock_irqrestore(&rp->lock, flags);
1608
1609 return &rp->stats;
1610}
1611
1612static void rhine_set_rx_mode(struct net_device *dev)
1613{
1614 struct rhine_private *rp = netdev_priv(dev);
1615 void __iomem *ioaddr = rp->base;
1616 u32 mc_filter[2]; /* Multicast hash filter */
1617 u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */
1618
1619 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1620 /* Unconditionally log net taps. */
1621 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1622 dev->name);
1623 rx_mode = 0x1C;
1624 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1625 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1626 } else if ((dev->mc_count > multicast_filter_limit)
1627 || (dev->flags & IFF_ALLMULTI)) {
1628 /* Too many to match, or accept all multicasts. */
1629 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1630 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1631 rx_mode = 0x0C;
1632 } else {
1633 struct dev_mc_list *mclist;
1634 int i;
1635 memset(mc_filter, 0, sizeof(mc_filter));
1636 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1637 i++, mclist = mclist->next) {
1638 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1639
1640 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1641 }
1642 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1643 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1644 rx_mode = 0x0C;
1645 }
1646 iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig);
1647}
1648
1649static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1650{
1651 struct rhine_private *rp = netdev_priv(dev);
1652
1653 strcpy(info->driver, DRV_NAME);
1654 strcpy(info->version, DRV_VERSION);
1655 strcpy(info->bus_info, pci_name(rp->pdev));
1656}
1657
1658static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1659{
1660 struct rhine_private *rp = netdev_priv(dev);
1661 int rc;
1662
1663 spin_lock_irq(&rp->lock);
1664 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1665 spin_unlock_irq(&rp->lock);
1666
1667 return rc;
1668}
1669
1670static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1671{
1672 struct rhine_private *rp = netdev_priv(dev);
1673 int rc;
1674
1675 spin_lock_irq(&rp->lock);
1676 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1677 spin_unlock_irq(&rp->lock);
00b428c2 1678 rhine_set_carrier(&rp->mii_if);
1da177e4
LT		 1679
1680 return rc;
1681}
1682
1683static int netdev_nway_reset(struct net_device *dev)
1684{
1685 struct rhine_private *rp = netdev_priv(dev);
1686
1687 return mii_nway_restart(&rp->mii_if);
1688}
1689
1690static u32 netdev_get_link(struct net_device *dev)
1691{
1692 struct rhine_private *rp = netdev_priv(dev);
1693
1694 return mii_link_ok(&rp->mii_if);
1695}
1696
1697static u32 netdev_get_msglevel(struct net_device *dev)
1698{
1699 return debug;
1700}
1701
1702static void netdev_set_msglevel(struct net_device *dev, u32 value)
1703{
1704 debug = value;
1705}
1706
1707static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1708{
1709 struct rhine_private *rp = netdev_priv(dev);
1710
1711 if (!(rp->quirks & rqWOL))
1712 return;
1713
1714 spin_lock_irq(&rp->lock);
1715 wol->supported = WAKE_PHY | WAKE_MAGIC |
1716 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1717 wol->wolopts = rp->wolopts;
1718 spin_unlock_irq(&rp->lock);
1719}
1720
1721static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1722{
1723 struct rhine_private *rp = netdev_priv(dev);
1724 u32 support = WAKE_PHY | WAKE_MAGIC |
1725 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1726
1727 if (!(rp->quirks & rqWOL))
1728 return -EINVAL;
1729
1730 if (wol->wolopts & ~support)
1731 return -EINVAL;
1732
1733 spin_lock_irq(&rp->lock);
1734 rp->wolopts = wol->wolopts;
1735 spin_unlock_irq(&rp->lock);
1736
1737 return 0;
1738}
1739
1740static struct ethtool_ops netdev_ethtool_ops = {
1741 .get_drvinfo = netdev_get_drvinfo,
1742 .get_settings = netdev_get_settings,
1743 .set_settings = netdev_set_settings,
1744 .nway_reset = netdev_nway_reset,
1745 .get_link = netdev_get_link,
1746 .get_msglevel = netdev_get_msglevel,
1747 .set_msglevel = netdev_set_msglevel,
1748 .get_wol = rhine_get_wol,
1749 .set_wol = rhine_set_wol,
1750 .get_sg = ethtool_op_get_sg,
1751 .get_tx_csum = ethtool_op_get_tx_csum,
b81e8e1f 1752 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1753};
1754
1755static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1756{
1757 struct rhine_private *rp = netdev_priv(dev);
1758 int rc;
1759
1760 if (!netif_running(dev))
1761 return -EINVAL;
1762
1763 spin_lock_irq(&rp->lock);
1764 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
1765 spin_unlock_irq(&rp->lock);
00b428c2 1766 rhine_set_carrier(&rp->mii_if);
1da177e4
LT		 1767
1768 return rc;
1769}
1770
1771static int rhine_close(struct net_device *dev)
1772{
1773 struct rhine_private *rp = netdev_priv(dev);
1774 void __iomem *ioaddr = rp->base;
1775
1776 spin_lock_irq(&rp->lock);
1777
1778 netif_stop_queue(dev);
1779
1780 if (debug > 1)
1781 printk(KERN_DEBUG "%s: Shutting down ethercard, "
1782 "status was %4.4x.\n",
1783 dev->name, ioread16(ioaddr + ChipCmd));
1784
1785 /* Switch to loopback mode to avoid hardware races. */
1786 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
1787
1788 /* Disable interrupts by clearing the interrupt mask. */
1789 iowrite16(0x0000, ioaddr + IntrEnable);
1790
1791 /* Stop the chip's Tx and Rx processes. */
1792 iowrite16(CmdStop, ioaddr + ChipCmd);
1793
1794 spin_unlock_irq(&rp->lock);
1795
1796 free_irq(rp->pdev->irq, dev);
1797 free_rbufs(dev);
1798 free_tbufs(dev);
1799 free_ring(dev);
1800
1801 return 0;
1802}
1803
1804
1805static void __devexit rhine_remove_one(struct pci_dev *pdev)
1806{
1807 struct net_device *dev = pci_get_drvdata(pdev);
1808 struct rhine_private *rp = netdev_priv(dev);
1809
1810 unregister_netdev(dev);
1811
1812 pci_iounmap(pdev, rp->base);
1813 pci_release_regions(pdev);
1814
1815 free_netdev(dev);
1816 pci_disable_device(pdev);
1817 pci_set_drvdata(pdev, NULL);
1818}
1819
d18c3db5 1820static void rhine_shutdown (struct pci_dev *pdev)
1da177e4 1821{
1da177e4
LT		 1822 struct net_device *dev = pci_get_drvdata(pdev);
1823 struct rhine_private *rp = netdev_priv(dev);
1824 void __iomem *ioaddr = rp->base;
1825
1826 if (!(rp->quirks & rqWOL))
1827 return; /* Nothing to do for non-WOL adapters */
1828
1829 rhine_power_init(dev);
1830
1831 /* Make sure we use pattern 0, 1 and not 4, 5 */
1832 if (rp->quirks & rq6patterns)
1833 iowrite8(0x04, ioaddr + 0xA7);
1834
1835 if (rp->wolopts & WAKE_MAGIC) {
1836 iowrite8(WOLmagic, ioaddr + WOLcrSet);
1837 /*
1838 * Turn EEPROM-controlled wake-up back on -- some hardware may
1839 * not cooperate otherwise.
1840 */
1841 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
1842 }
1843
1844 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
1845 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
1846
1847 if (rp->wolopts & WAKE_PHY)
1848 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
1849
1850 if (rp->wolopts & WAKE_UCAST)
1851 iowrite8(WOLucast, ioaddr + WOLcrSet);
1852
1853 if (rp->wolopts) {
1854 /* Enable legacy WOL (for old motherboards) */
1855 iowrite8(0x01, ioaddr + PwcfgSet);
1856 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
1857 }
1858
1859 /* Hit power state D3 (sleep) */
1860 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
1861
1862 /* TODO: Check use of pci_enable_wake() */
1863
1864}
1865
1866#ifdef CONFIG_PM
1867static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
1868{
1869 struct net_device *dev = pci_get_drvdata(pdev);
1870 struct rhine_private *rp = netdev_priv(dev);
1871 unsigned long flags;
1872
1873 if (!netif_running(dev))
1874 return 0;
1875
1876 netif_device_detach(dev);
1877 pci_save_state(pdev);
1878
1879 spin_lock_irqsave(&rp->lock, flags);
d18c3db5 1880 rhine_shutdown(pdev);
1da177e4
LT		 1881 spin_unlock_irqrestore(&rp->lock, flags);
1882
1883 free_irq(dev->irq, dev);
1884 return 0;
1885}
1886
1887static int rhine_resume(struct pci_dev *pdev)
1888{
1889 struct net_device *dev = pci_get_drvdata(pdev);
1890 struct rhine_private *rp = netdev_priv(dev);
1891 unsigned long flags;
1892 int ret;
1893
1894 if (!netif_running(dev))
1895 return 0;
1896
1fb9df5d 1897 if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
1da177e4
LT		 1898 printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
1899
1900 ret = pci_set_power_state(pdev, PCI_D0);
1901 if (debug > 1)
1902 printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n",
1903 dev->name, ret ? "failed" : "succeeded", ret);
1904
1905 pci_restore_state(pdev);
1906
1907 spin_lock_irqsave(&rp->lock, flags);
1908#ifdef USE_MMIO
1909 enable_mmio(rp->pioaddr, rp->quirks);
1910#endif
1911 rhine_power_init(dev);
1912 free_tbufs(dev);
1913 free_rbufs(dev);
1914 alloc_tbufs(dev);
1915 alloc_rbufs(dev);
1916 init_registers(dev);
1917 spin_unlock_irqrestore(&rp->lock, flags);
1918
1919 netif_device_attach(dev);
1920
1921 return 0;
1922}
1923#endif /* CONFIG_PM */
1924
1925static struct pci_driver rhine_driver = {
1926 .name = DRV_NAME,
1927 .id_table = rhine_pci_tbl,
1928 .probe = rhine_init_one,
1929 .remove = __devexit_p(rhine_remove_one),
1930#ifdef CONFIG_PM
1931 .suspend = rhine_suspend,
1932 .resume = rhine_resume,
1933#endif /* CONFIG_PM */
d18c3db5 1934 .shutdown = rhine_shutdown,
1da177e4
LT		 1935};
1936
1937
1938static int __init rhine_init(void)
1939{
1940/* when a module, this is printed whether or not devices are found in probe */
1941#ifdef MODULE
1942 printk(version);
1943#endif
1944 return pci_module_init(&rhine_driver);
1945}
1946
1947
1948static void __exit rhine_cleanup(void)
1949{
1950 pci_unregister_driver(&rhine_driver);
1951}
1952
1953
1954module_init(rhine_init);
1955module_exit(rhine_cleanup);
Linux 6.x block layer and io_uring tree(s)