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[PATCH] pcmcia: convert DEV_OK to pcmcia_dev_present
[linux-2.6-block.git] / drivers / net / via-rhine.c
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1da177e4
LT		 1/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
28
29
30 Linux kernel version history:
31
32 LK1.1.0:
33 - Jeff Garzik: softnet 'n stuff
34
35 LK1.1.1:
36 - Justin Guyett: softnet and locking fixes
37 - Jeff Garzik: use PCI interface
38
39 LK1.1.2:
40 - Urban Widmark: minor cleanups, merges from Becker 1.03a/1.04 versions
41
42 LK1.1.3:
43 - Urban Widmark: use PCI DMA interface (with thanks to the eepro100.c
44 code) update "Theory of Operation" with
45 softnet/locking changes
46 - Dave Miller: PCI DMA and endian fixups
47 - Jeff Garzik: MOD_xxx race fixes, updated PCI resource allocation
48
49 LK1.1.4:
50 - Urban Widmark: fix gcc 2.95.2 problem and
51 remove writel's to fixed address 0x7c
52
53 LK1.1.5:
54 - Urban Widmark: mdio locking, bounce buffer changes
55 merges from Beckers 1.05 version
56 added netif_running_on/off support
57
58 LK1.1.6:
59 - Urban Widmark: merges from Beckers 1.08b version (VT6102 + mdio)
60 set netif_running_on/off on startup, del_timer_sync
61
62 LK1.1.7:
63 - Manfred Spraul: added reset into tx_timeout
64
65 LK1.1.9:
66 - Urban Widmark: merges from Beckers 1.10 version
67 (media selection + eeprom reload)
68 - David Vrabel: merges from D-Link "1.11" version
69 (disable WOL and PME on startup)
70
71 LK1.1.10:
72 - Manfred Spraul: use "singlecopy" for unaligned buffers
73 don't allocate bounce buffers for !ReqTxAlign cards
74
75 LK1.1.11:
76 - David Woodhouse: Set dev->base_addr before the first time we call
77 wait_for_reset(). It's a lot happier that way.
78 Free np->tx_bufs only if we actually allocated it.
79
80 LK1.1.12:
81 - Martin Eriksson: Allow Memory-Mapped IO to be enabled.
82
83 LK1.1.13 (jgarzik):
84 - Add ethtool support
85 - Replace some MII-related magic numbers with constants
86
87 LK1.1.14 (Ivan G.):
88 - fixes comments for Rhine-III
89 - removes W_MAX_TIMEOUT (unused)
90 - adds HasDavicomPhy for Rhine-I (basis: linuxfet driver; my card
91 is R-I and has Davicom chip, flag is referenced in kernel driver)
92 - sends chip_id as a parameter to wait_for_reset since np is not
93 initialized on first call
94 - changes mmio "else if (chip_id==VT6102)" to "else" so it will work
95 for Rhine-III's (documentation says same bit is correct)
96 - transmit frame queue message is off by one - fixed
97 - adds IntrNormalSummary to "Something Wicked" exclusion list
98 so normal interrupts will not trigger the message (src: Donald Becker)
99 (Roger Luethi)
100 - show confused chip where to continue after Tx error
101 - location of collision counter is chip specific
102 - allow selecting backoff algorithm (module parameter)
103
104 LK1.1.15 (jgarzik):
105 - Use new MII lib helper generic_mii_ioctl
106
107 LK1.1.16 (Roger Luethi)
108 - Etherleak fix
109 - Handle Tx buffer underrun
110 - Fix bugs in full duplex handling
111 - New reset code uses "force reset" cmd on Rhine-II
112 - Various clean ups
113
114 LK1.1.17 (Roger Luethi)
115 - Fix race in via_rhine_start_tx()
116 - On errors, wait for Tx engine to turn off before scavenging
117 - Handle Tx descriptor write-back race on Rhine-II
118 - Force flushing for PCI posted writes
119 - More reset code changes
120
121 LK1.1.18 (Roger Luethi)
122 - No filtering multicast in promisc mode (Edward Peng)
123 - Fix for Rhine-I Tx timeouts
124
125 LK1.1.19 (Roger Luethi)
126 - Increase Tx threshold for unspecified errors
127
128 LK1.2.0-2.6 (Roger Luethi)
129 - Massive clean-up
130 - Rewrite PHY, media handling (remove options, full_duplex, backoff)
131 - Fix Tx engine race for good
132
133*/
134
135#define DRV_NAME "via-rhine"
136#define DRV_VERSION "1.2.0-2.6"
137#define DRV_RELDATE "June-10-2004"
138
139
140/* A few user-configurable values.
141 These may be modified when a driver module is loaded. */
142
143static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
144static int max_interrupt_work = 20;
145
146/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
147 Setting to > 1518 effectively disables this feature. */
148static int rx_copybreak;
149
150/*
151 * In case you are looking for 'options[]' or 'full_duplex[]', they
152 * are gone. Use ethtool(8) instead.
153 */
154
155/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
156 The Rhine has a 64 element 8390-like hash table. */
157static const int multicast_filter_limit = 32;
158
159
160/* Operational parameters that are set at compile time. */
161
162/* Keep the ring sizes a power of two for compile efficiency.
163 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
164 Making the Tx ring too large decreases the effectiveness of channel
165 bonding and packet priority.
166 There are no ill effects from too-large receive rings. */
167#define TX_RING_SIZE 16
168#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
169#define RX_RING_SIZE 16
170
171
172/* Operational parameters that usually are not changed. */
173
174/* Time in jiffies before concluding the transmitter is hung. */
175#define TX_TIMEOUT (2*HZ)
176
177#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
178
179#include <linux/module.h>
180#include <linux/moduleparam.h>
181#include <linux/kernel.h>
182#include <linux/string.h>
183#include <linux/timer.h>
184#include <linux/errno.h>
185#include <linux/ioport.h>
186#include <linux/slab.h>
187#include <linux/interrupt.h>
188#include <linux/pci.h>
1e7f0bd8 189#include <linux/dma-mapping.h>
1da177e4
LT		 190#include <linux/netdevice.h>
191#include <linux/etherdevice.h>
192#include <linux/skbuff.h>
193#include <linux/init.h>
194#include <linux/delay.h>
195#include <linux/mii.h>
196#include <linux/ethtool.h>
197#include <linux/crc32.h>
198#include <linux/bitops.h>
199#include <asm/processor.h> /* Processor type for cache alignment. */
200#include <asm/io.h>
201#include <asm/irq.h>
202#include <asm/uaccess.h>
203
204/* These identify the driver base version and may not be removed. */
205static char version[] __devinitdata =
206KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
207
208/* This driver was written to use PCI memory space. Some early versions
209 of the Rhine may only work correctly with I/O space accesses. */
210#ifdef CONFIG_VIA_RHINE_MMIO
211#define USE_MMIO
212#else
213#endif
214
215MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
216MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
217MODULE_LICENSE("GPL");
218
219module_param(max_interrupt_work, int, 0);
220module_param(debug, int, 0);
221module_param(rx_copybreak, int, 0);
222MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
223MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
224MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
225
226/*
227 Theory of Operation
228
229I. Board Compatibility
230
231This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
232controller.
233
234II. Board-specific settings
235
236Boards with this chip are functional only in a bus-master PCI slot.
237
238Many operational settings are loaded from the EEPROM to the Config word at
239offset 0x78. For most of these settings, this driver assumes that they are
240correct.
241If this driver is compiled to use PCI memory space operations the EEPROM
242must be configured to enable memory ops.
243
244III. Driver operation
245
246IIIa. Ring buffers
247
248This driver uses two statically allocated fixed-size descriptor lists
249formed into rings by a branch from the final descriptor to the beginning of
250the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
251
252IIIb/c. Transmit/Receive Structure
253
254This driver attempts to use a zero-copy receive and transmit scheme.
255
256Alas, all data buffers are required to start on a 32 bit boundary, so
257the driver must often copy transmit packets into bounce buffers.
258
259The driver allocates full frame size skbuffs for the Rx ring buffers at
260open() time and passes the skb->data field to the chip as receive data
261buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
262a fresh skbuff is allocated and the frame is copied to the new skbuff.
263When the incoming frame is larger, the skbuff is passed directly up the
264protocol stack. Buffers consumed this way are replaced by newly allocated
265skbuffs in the last phase of rhine_rx().
266
267The RX_COPYBREAK value is chosen to trade-off the memory wasted by
268using a full-sized skbuff for small frames vs. the copying costs of larger
269frames. New boards are typically used in generously configured machines
270and the underfilled buffers have negligible impact compared to the benefit of
271a single allocation size, so the default value of zero results in never
272copying packets. When copying is done, the cost is usually mitigated by using
273a combined copy/checksum routine. Copying also preloads the cache, which is
274most useful with small frames.
275
276Since the VIA chips are only able to transfer data to buffers on 32 bit
277boundaries, the IP header at offset 14 in an ethernet frame isn't
278longword aligned for further processing. Copying these unaligned buffers
279has the beneficial effect of 16-byte aligning the IP header.
280
281IIId. Synchronization
282
283The driver runs as two independent, single-threaded flows of control. One
284is the send-packet routine, which enforces single-threaded use by the
285dev->priv->lock spinlock. The other thread is the interrupt handler, which
286is single threaded by the hardware and interrupt handling software.
287
288The send packet thread has partial control over the Tx ring. It locks the
289dev->priv->lock whenever it's queuing a Tx packet. If the next slot in the ring
290is not available it stops the transmit queue by calling netif_stop_queue.
291
292The interrupt handler has exclusive control over the Rx ring and records stats
293from the Tx ring. After reaping the stats, it marks the Tx queue entry as
294empty by incrementing the dirty_tx mark. If at least half of the entries in
295the Rx ring are available the transmit queue is woken up if it was stopped.
296
297IV. Notes
298
299IVb. References
300
301Preliminary VT86C100A manual from http://www.via.com.tw/
302http://www.scyld.com/expert/100mbps.html
303http://www.scyld.com/expert/NWay.html
304ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
305ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
306
307
308IVc. Errata
309
310The VT86C100A manual is not reliable information.
311The 3043 chip does not handle unaligned transmit or receive buffers, resulting
312in significant performance degradation for bounce buffer copies on transmit
313and unaligned IP headers on receive.
314The chip does not pad to minimum transmit length.
315
316*/
317
318
319/* This table drives the PCI probe routines. It's mostly boilerplate in all
320 of the drivers, and will likely be provided by some future kernel.
321 Note the matching code -- the first table entry matchs all 56** cards but
322 second only the 1234 card.
323*/
324
325enum rhine_revs {
326 VT86C100A = 0x00,
327 VTunknown0 = 0x20,
328 VT6102 = 0x40,
329 VT8231 = 0x50, /* Integrated MAC */
330 VT8233 = 0x60, /* Integrated MAC */
331 VT8235 = 0x74, /* Integrated MAC */
332 VT8237 = 0x78, /* Integrated MAC */
333 VTunknown1 = 0x7C,
334 VT6105 = 0x80,
335 VT6105_B0 = 0x83,
336 VT6105L = 0x8A,
337 VT6107 = 0x8C,
338 VTunknown2 = 0x8E,
339 VT6105M = 0x90, /* Management adapter */
340};
341
342enum rhine_quirks {
343 rqWOL = 0x0001, /* Wake-On-LAN support */
344 rqForceReset = 0x0002,
345 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
346 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
347 rqRhineI = 0x0100, /* See comment below */
348};
349/*
350 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
351 * MMIO as well as for the collision counter and the Tx FIFO underflow
352 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
353 */
354
355/* Beware of PCI posted writes */
356#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
357
358static struct pci_device_id rhine_pci_tbl[] =
359{
360 {0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT86C100A */
361 {0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT6102 */
362 {0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* 6105{,L,LOM} */
363 {0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT6105M */
364 { } /* terminate list */
365};
366MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
367
368
369/* Offsets to the device registers. */
370enum register_offsets {
371 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
372 ChipCmd1=0x09,
373 IntrStatus=0x0C, IntrEnable=0x0E,
374 MulticastFilter0=0x10, MulticastFilter1=0x14,
375 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
376 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
377 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
378 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
379 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
380 StickyHW=0x83, IntrStatus2=0x84,
381 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
382 WOLcrClr1=0xA6, WOLcgClr=0xA7,
383 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
384};
385
386/* Bits in ConfigD */
387enum backoff_bits {
388 BackOptional=0x01, BackModify=0x02,
389 BackCaptureEffect=0x04, BackRandom=0x08
390};
391
392#ifdef USE_MMIO
393/* Registers we check that mmio and reg are the same. */
394static const int mmio_verify_registers[] = {
395 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
396 0
397};
398#endif
399
400/* Bits in the interrupt status/mask registers. */
401enum intr_status_bits {
402 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
403 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
404 IntrPCIErr=0x0040,
405 IntrStatsMax=0x0080, IntrRxEarly=0x0100,
406 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
407 IntrTxAborted=0x2000, IntrLinkChange=0x4000,
408 IntrRxWakeUp=0x8000,
409 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
410 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
411 IntrTxErrSummary=0x082218,
412};
413
414/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
415enum wol_bits {
416 WOLucast = 0x10,
417 WOLmagic = 0x20,
418 WOLbmcast = 0x30,
419 WOLlnkon = 0x40,
420 WOLlnkoff = 0x80,
421};
422
423/* The Rx and Tx buffer descriptors. */
424struct rx_desc {
425 s32 rx_status;
426 u32 desc_length; /* Chain flag, Buffer/frame length */
427 u32 addr;
428 u32 next_desc;
429};
430struct tx_desc {
431 s32 tx_status;
432 u32 desc_length; /* Chain flag, Tx Config, Frame length */
433 u32 addr;
434 u32 next_desc;
435};
436
437/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
438#define TXDESC 0x00e08000
439
440enum rx_status_bits {
441 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
442};
443
444/* Bits in *_desc.*_status */
445enum desc_status_bits {
446 DescOwn=0x80000000
447};
448
449/* Bits in ChipCmd. */
450enum chip_cmd_bits {
451 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
452 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
453 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
454 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
455};
456
457struct rhine_private {
458 /* Descriptor rings */
459 struct rx_desc *rx_ring;
460 struct tx_desc *tx_ring;
461 dma_addr_t rx_ring_dma;
462 dma_addr_t tx_ring_dma;
463
464 /* The addresses of receive-in-place skbuffs. */
465 struct sk_buff *rx_skbuff[RX_RING_SIZE];
466 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
467
468 /* The saved address of a sent-in-place packet/buffer, for later free(). */
469 struct sk_buff *tx_skbuff[TX_RING_SIZE];
470 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
471
472 /* Tx bounce buffers */
473 unsigned char *tx_buf[TX_RING_SIZE];
474 unsigned char *tx_bufs;
475 dma_addr_t tx_bufs_dma;
476
477 struct pci_dev *pdev;
478 long pioaddr;
479 struct net_device_stats stats;
480 spinlock_t lock;
481
482 /* Frequently used values: keep some adjacent for cache effect. */
483 u32 quirks;
484 struct rx_desc *rx_head_desc;
485 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
486 unsigned int cur_tx, dirty_tx;
487 unsigned int rx_buf_sz; /* Based on MTU+slack. */
488 u8 wolopts;
489
490 u8 tx_thresh, rx_thresh;
491
492 struct mii_if_info mii_if;
6ba98d31
JL		 493 struct work_struct tx_timeout_task;
494 struct work_struct check_media_task;
1da177e4
LT		 495 void __iomem *base;
496};
497
498static int mdio_read(struct net_device *dev, int phy_id, int location);
499static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
500static int rhine_open(struct net_device *dev);
501static void rhine_tx_timeout(struct net_device *dev);
6ba98d31
JL		 502static void rhine_tx_timeout_task(struct net_device *dev);
503static void rhine_check_media_task(struct net_device *dev);
1da177e4
LT		 504static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev);
505static irqreturn_t rhine_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
506static void rhine_tx(struct net_device *dev);
507static void rhine_rx(struct net_device *dev);
508static void rhine_error(struct net_device *dev, int intr_status);
509static void rhine_set_rx_mode(struct net_device *dev);
510static struct net_device_stats *rhine_get_stats(struct net_device *dev);
511static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
512static struct ethtool_ops netdev_ethtool_ops;
513static int rhine_close(struct net_device *dev);
d18c3db5 514static void rhine_shutdown (struct pci_dev *pdev);
1da177e4
LT		 515
516#define RHINE_WAIT_FOR(condition) do { \
517 int i=1024; \
518 while (!(condition) && --i) \
519 ; \
520 if (debug > 1 && i < 512) \
521 printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
522 DRV_NAME, 1024-i, __func__, __LINE__); \
523} while(0)
524
525static inline u32 get_intr_status(struct net_device *dev)
526{
527 struct rhine_private *rp = netdev_priv(dev);
528 void __iomem *ioaddr = rp->base;
529 u32 intr_status;
530
531 intr_status = ioread16(ioaddr + IntrStatus);
532 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
533 if (rp->quirks & rqStatusWBRace)
534 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
535 return intr_status;
536}
537
538/*
539 * Get power related registers into sane state.
540 * Notify user about past WOL event.
541 */
542static void rhine_power_init(struct net_device *dev)
543{
544 struct rhine_private *rp = netdev_priv(dev);
545 void __iomem *ioaddr = rp->base;
546 u16 wolstat;
547
548 if (rp->quirks & rqWOL) {
549 /* Make sure chip is in power state D0 */
550 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
551
552 /* Disable "force PME-enable" */
553 iowrite8(0x80, ioaddr + WOLcgClr);
554
555 /* Clear power-event config bits (WOL) */
556 iowrite8(0xFF, ioaddr + WOLcrClr);
557 /* More recent cards can manage two additional patterns */
558 if (rp->quirks & rq6patterns)
559 iowrite8(0x03, ioaddr + WOLcrClr1);
560
561 /* Save power-event status bits */
562 wolstat = ioread8(ioaddr + PwrcsrSet);
563 if (rp->quirks & rq6patterns)
564 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
565
566 /* Clear power-event status bits */
567 iowrite8(0xFF, ioaddr + PwrcsrClr);
568 if (rp->quirks & rq6patterns)
569 iowrite8(0x03, ioaddr + PwrcsrClr1);
570
571 if (wolstat) {
572 char *reason;
573 switch (wolstat) {
574 case WOLmagic:
575 reason = "Magic packet";
576 break;
577 case WOLlnkon:
578 reason = "Link went up";
579 break;
580 case WOLlnkoff:
581 reason = "Link went down";
582 break;
583 case WOLucast:
584 reason = "Unicast packet";
585 break;
586 case WOLbmcast:
587 reason = "Multicast/broadcast packet";
588 break;
589 default:
590 reason = "Unknown";
591 }
592 printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
593 DRV_NAME, reason);
594 }
595 }
596}
597
598static void rhine_chip_reset(struct net_device *dev)
599{
600 struct rhine_private *rp = netdev_priv(dev);
601 void __iomem *ioaddr = rp->base;
602
603 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
604 IOSYNC;
605
606 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
607 printk(KERN_INFO "%s: Reset not complete yet. "
608 "Trying harder.\n", DRV_NAME);
609
610 /* Force reset */
611 if (rp->quirks & rqForceReset)
612 iowrite8(0x40, ioaddr + MiscCmd);
613
614 /* Reset can take somewhat longer (rare) */
615 RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
616 }
617
618 if (debug > 1)
619 printk(KERN_INFO "%s: Reset %s.\n", dev->name,
620 (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
621 "failed" : "succeeded");
622}
623
624#ifdef USE_MMIO
625static void enable_mmio(long pioaddr, u32 quirks)
626{
627 int n;
628 if (quirks & rqRhineI) {
629 /* More recent docs say that this bit is reserved ... */
630 n = inb(pioaddr + ConfigA) | 0x20;
631 outb(n, pioaddr + ConfigA);
632 } else {
633 n = inb(pioaddr + ConfigD) | 0x80;
634 outb(n, pioaddr + ConfigD);
635 }
636}
637#endif
638
639/*
640 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
641 * (plus 0x6C for Rhine-I/II)
642 */
643static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
644{
645 struct rhine_private *rp = netdev_priv(dev);
646 void __iomem *ioaddr = rp->base;
647
648 outb(0x20, pioaddr + MACRegEEcsr);
649 RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
650
651#ifdef USE_MMIO
652 /*
653 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
654 * MMIO. If reloading EEPROM was done first this could be avoided, but
655 * it is not known if that still works with the "win98-reboot" problem.
656 */
657 enable_mmio(pioaddr, rp->quirks);
658#endif
659
660 /* Turn off EEPROM-controlled wake-up (magic packet) */
661 if (rp->quirks & rqWOL)
662 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
663
664}
665
666#ifdef CONFIG_NET_POLL_CONTROLLER
667static void rhine_poll(struct net_device *dev)
668{
669 disable_irq(dev->irq);
670 rhine_interrupt(dev->irq, (void *)dev, NULL);
671 enable_irq(dev->irq);
672}
673#endif
674
675static void rhine_hw_init(struct net_device *dev, long pioaddr)
676{
677 struct rhine_private *rp = netdev_priv(dev);
678
679 /* Reset the chip to erase previous misconfiguration. */
680 rhine_chip_reset(dev);
681
682 /* Rhine-I needs extra time to recuperate before EEPROM reload */
683 if (rp->quirks & rqRhineI)
684 msleep(5);
685
686 /* Reload EEPROM controlled bytes cleared by soft reset */
687 rhine_reload_eeprom(pioaddr, dev);
688}
689
690static int __devinit rhine_init_one(struct pci_dev *pdev,
691 const struct pci_device_id *ent)
692{
693 struct net_device *dev;
694 struct rhine_private *rp;
695 int i, rc;
696 u8 pci_rev;
697 u32 quirks;
698 long pioaddr;
699 long memaddr;
700 void __iomem *ioaddr;
701 int io_size, phy_id;
702 const char *name;
703#ifdef USE_MMIO
704 int bar = 1;
705#else
706 int bar = 0;
707#endif
708
709/* when built into the kernel, we only print version if device is found */
710#ifndef MODULE
711 static int printed_version;
712 if (!printed_version++)
713 printk(version);
714#endif
715
716 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
717
718 io_size = 256;
719 phy_id = 0;
720 quirks = 0;
721 name = "Rhine";
722 if (pci_rev < VTunknown0) {
723 quirks = rqRhineI;
724 io_size = 128;
725 }
726 else if (pci_rev >= VT6102) {
727 quirks = rqWOL | rqForceReset;
728 if (pci_rev < VT6105) {
729 name = "Rhine II";
730 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
731 }
732 else {
733 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
734 if (pci_rev >= VT6105_B0)
735 quirks |= rq6patterns;
736 if (pci_rev < VT6105M)
737 name = "Rhine III";
738 else
739 name = "Rhine III (Management Adapter)";
740 }
741 }
742
743 rc = pci_enable_device(pdev);
744 if (rc)
745 goto err_out;
746
747 /* this should always be supported */
1e7f0bd8 748 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4
LT		 749 if (rc) {
750 printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
751 "the card!?\n");
752 goto err_out;
753 }
754
755 /* sanity check */
756 if ((pci_resource_len(pdev, 0) < io_size) ||
757 (pci_resource_len(pdev, 1) < io_size)) {
758 rc = -EIO;
759 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
760 goto err_out;
761 }
762
763 pioaddr = pci_resource_start(pdev, 0);
764 memaddr = pci_resource_start(pdev, 1);
765
766 pci_set_master(pdev);
767
768 dev = alloc_etherdev(sizeof(struct rhine_private));
769 if (!dev) {
770 rc = -ENOMEM;
771 printk(KERN_ERR "alloc_etherdev failed\n");
772 goto err_out;
773 }
774 SET_MODULE_OWNER(dev);
775 SET_NETDEV_DEV(dev, &pdev->dev);
776
777 rp = netdev_priv(dev);
778 rp->quirks = quirks;
779 rp->pioaddr = pioaddr;
780 rp->pdev = pdev;
781
782 rc = pci_request_regions(pdev, DRV_NAME);
783 if (rc)
784 goto err_out_free_netdev;
785
786 ioaddr = pci_iomap(pdev, bar, io_size);
787 if (!ioaddr) {
788 rc = -EIO;
789 printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
790 "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
791 goto err_out_free_res;
792 }
793
794#ifdef USE_MMIO
795 enable_mmio(pioaddr, quirks);
796
797 /* Check that selected MMIO registers match the PIO ones */
798 i = 0;
799 while (mmio_verify_registers[i]) {
800 int reg = mmio_verify_registers[i++];
801 unsigned char a = inb(pioaddr+reg);
802 unsigned char b = readb(ioaddr+reg);
803 if (a != b) {
804 rc = -EIO;
805 printk(KERN_ERR "MMIO do not match PIO [%02x] "
806 "(%02x != %02x)\n", reg, a, b);
807 goto err_out_unmap;
808 }
809 }
810#endif /* USE_MMIO */
811
812 dev->base_addr = (unsigned long)ioaddr;
813 rp->base = ioaddr;
814
815 /* Get chip registers into a sane state */
816 rhine_power_init(dev);
817 rhine_hw_init(dev, pioaddr);
818
819 for (i = 0; i < 6; i++)
820 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
b81e8e1f 821 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 822
b81e8e1f 823 if (!is_valid_ether_addr(dev->perm_addr)) {
1da177e4
LT		 824 rc = -EIO;
825 printk(KERN_ERR "Invalid MAC address\n");
826 goto err_out_unmap;
827 }
828
829 /* For Rhine-I/II, phy_id is loaded from EEPROM */
830 if (!phy_id)
831 phy_id = ioread8(ioaddr + 0x6C);
832
833 dev->irq = pdev->irq;
834
835 spin_lock_init(&rp->lock);
836 rp->mii_if.dev = dev;
837 rp->mii_if.mdio_read = mdio_read;
838 rp->mii_if.mdio_write = mdio_write;
839 rp->mii_if.phy_id_mask = 0x1f;
840 rp->mii_if.reg_num_mask = 0x1f;
841
842 /* The chip-specific entries in the device structure. */
843 dev->open = rhine_open;
844 dev->hard_start_xmit = rhine_start_tx;
845 dev->stop = rhine_close;
846 dev->get_stats = rhine_get_stats;
847 dev->set_multicast_list = rhine_set_rx_mode;
848 dev->do_ioctl = netdev_ioctl;
849 dev->ethtool_ops = &netdev_ethtool_ops;
850 dev->tx_timeout = rhine_tx_timeout;
851 dev->watchdog_timeo = TX_TIMEOUT;
852#ifdef CONFIG_NET_POLL_CONTROLLER
853 dev->poll_controller = rhine_poll;
854#endif
855 if (rp->quirks & rqRhineI)
856 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
857
6ba98d31
JL		 858 INIT_WORK(&rp->tx_timeout_task,
859 (void (*)(void *))rhine_tx_timeout_task, dev);
860
861 INIT_WORK(&rp->check_media_task,
862 (void (*)(void *))rhine_check_media_task, dev);
863
1da177e4
LT		 864 /* dev->name not defined before register_netdev()! */
865 rc = register_netdev(dev);
866 if (rc)
867 goto err_out_unmap;
868
869 printk(KERN_INFO "%s: VIA %s at 0x%lx, ",
870 dev->name, name,
871#ifdef USE_MMIO
872 memaddr
873#else
874 (long)ioaddr
875#endif
876 );
877
878 for (i = 0; i < 5; i++)
879 printk("%2.2x:", dev->dev_addr[i]);
880 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], pdev->irq);
881
882 pci_set_drvdata(pdev, dev);
883
884 {
885 u16 mii_cmd;
886 int mii_status = mdio_read(dev, phy_id, 1);
887 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
888 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
889 if (mii_status != 0xffff && mii_status != 0x0000) {
890 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
891 printk(KERN_INFO "%s: MII PHY found at address "
892 "%d, status 0x%4.4x advertising %4.4x "
893 "Link %4.4x.\n", dev->name, phy_id,
894 mii_status, rp->mii_if.advertising,
895 mdio_read(dev, phy_id, 5));
896
897 /* set IFF_RUNNING */
898 if (mii_status & BMSR_LSTATUS)
899 netif_carrier_on(dev);
900 else
901 netif_carrier_off(dev);
902
903 }
904 }
905 rp->mii_if.phy_id = phy_id;
906
907 return 0;
908
909err_out_unmap:
910 pci_iounmap(pdev, ioaddr);
911err_out_free_res:
912 pci_release_regions(pdev);
913err_out_free_netdev:
914 free_netdev(dev);
915err_out:
916 return rc;
917}
918
919static int alloc_ring(struct net_device* dev)
920{
921 struct rhine_private *rp = netdev_priv(dev);
922 void *ring;
923 dma_addr_t ring_dma;
924
925 ring = pci_alloc_consistent(rp->pdev,
926 RX_RING_SIZE * sizeof(struct rx_desc) +
927 TX_RING_SIZE * sizeof(struct tx_desc),
928 &ring_dma);
929 if (!ring) {
930 printk(KERN_ERR "Could not allocate DMA memory.\n");
931 return -ENOMEM;
932 }
933 if (rp->quirks & rqRhineI) {
934 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
935 PKT_BUF_SZ * TX_RING_SIZE,
936 &rp->tx_bufs_dma);
937 if (rp->tx_bufs == NULL) {
938 pci_free_consistent(rp->pdev,
939 RX_RING_SIZE * sizeof(struct rx_desc) +
940 TX_RING_SIZE * sizeof(struct tx_desc),
941 ring, ring_dma);
942 return -ENOMEM;
943 }
944 }
945
946 rp->rx_ring = ring;
947 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
948 rp->rx_ring_dma = ring_dma;
949 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
950
951 return 0;
952}
953
954static void free_ring(struct net_device* dev)
955{
956 struct rhine_private *rp = netdev_priv(dev);
957
958 pci_free_consistent(rp->pdev,
959 RX_RING_SIZE * sizeof(struct rx_desc) +
960 TX_RING_SIZE * sizeof(struct tx_desc),
961 rp->rx_ring, rp->rx_ring_dma);
962 rp->tx_ring = NULL;
963
964 if (rp->tx_bufs)
965 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
966 rp->tx_bufs, rp->tx_bufs_dma);
967
968 rp->tx_bufs = NULL;
969
970}
971
972static void alloc_rbufs(struct net_device *dev)
973{
974 struct rhine_private *rp = netdev_priv(dev);
975 dma_addr_t next;
976 int i;
977
978 rp->dirty_rx = rp->cur_rx = 0;
979
980 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
981 rp->rx_head_desc = &rp->rx_ring[0];
982 next = rp->rx_ring_dma;
983
984 /* Init the ring entries */
985 for (i = 0; i < RX_RING_SIZE; i++) {
986 rp->rx_ring[i].rx_status = 0;
987 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
988 next += sizeof(struct rx_desc);
989 rp->rx_ring[i].next_desc = cpu_to_le32(next);
990 rp->rx_skbuff[i] = NULL;
991 }
992 /* Mark the last entry as wrapping the ring. */
993 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
994
995 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
996 for (i = 0; i < RX_RING_SIZE; i++) {
997 struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz);
998 rp->rx_skbuff[i] = skb;
999 if (skb == NULL)
1000 break;
1001 skb->dev = dev; /* Mark as being used by this device. */
1002
1003 rp->rx_skbuff_dma[i] =
689be439 1004 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
1da177e4
LT		 1005 PCI_DMA_FROMDEVICE);
1006
1007 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
1008 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
1009 }
1010 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1011}
1012
1013static void free_rbufs(struct net_device* dev)
1014{
1015 struct rhine_private *rp = netdev_priv(dev);
1016 int i;
1017
1018 /* Free all the skbuffs in the Rx queue. */
1019 for (i = 0; i < RX_RING_SIZE; i++) {
1020 rp->rx_ring[i].rx_status = 0;
1021 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1022 if (rp->rx_skbuff[i]) {
1023 pci_unmap_single(rp->pdev,
1024 rp->rx_skbuff_dma[i],
1025 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1026 dev_kfree_skb(rp->rx_skbuff[i]);
1027 }
1028 rp->rx_skbuff[i] = NULL;
1029 }
1030}
1031
1032static void alloc_tbufs(struct net_device* dev)
1033{
1034 struct rhine_private *rp = netdev_priv(dev);
1035 dma_addr_t next;
1036 int i;
1037
1038 rp->dirty_tx = rp->cur_tx = 0;
1039 next = rp->tx_ring_dma;
1040 for (i = 0; i < TX_RING_SIZE; i++) {
1041 rp->tx_skbuff[i] = NULL;
1042 rp->tx_ring[i].tx_status = 0;
1043 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1044 next += sizeof(struct tx_desc);
1045 rp->tx_ring[i].next_desc = cpu_to_le32(next);
1046 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
1047 }
1048 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
1049
1050}
1051
1052static void free_tbufs(struct net_device* dev)
1053{
1054 struct rhine_private *rp = netdev_priv(dev);
1055 int i;
1056
1057 for (i = 0; i < TX_RING_SIZE; i++) {
1058 rp->tx_ring[i].tx_status = 0;
1059 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1060 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1061 if (rp->tx_skbuff[i]) {
1062 if (rp->tx_skbuff_dma[i]) {
1063 pci_unmap_single(rp->pdev,
1064 rp->tx_skbuff_dma[i],
1065 rp->tx_skbuff[i]->len,
1066 PCI_DMA_TODEVICE);
1067 }
1068 dev_kfree_skb(rp->tx_skbuff[i]);
1069 }
1070 rp->tx_skbuff[i] = NULL;
1071 rp->tx_buf[i] = NULL;
1072 }
1073}
1074
1075static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1076{
1077 struct rhine_private *rp = netdev_priv(dev);
1078 void __iomem *ioaddr = rp->base;
1079
1080 mii_check_media(&rp->mii_if, debug, init_media);
1081
1082 if (rp->mii_if.full_duplex)
1083 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1084 ioaddr + ChipCmd1);
1085 else
1086 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1087 ioaddr + ChipCmd1);
00b428c2
RL		 1088 if (debug > 1)
1089 printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name,
1090 rp->mii_if.force_media, netif_carrier_ok(dev));
1091}
1092
1093/* Called after status of force_media possibly changed */
1094void rhine_set_carrier(struct mii_if_info *mii)
1095{
1096 if (mii->force_media) {
1097 /* autoneg is off: Link is always assumed to be up */
1098 if (!netif_carrier_ok(mii->dev))
1099 netif_carrier_on(mii->dev);
1100 }
1101 else /* Let MMI library update carrier status */
1102 rhine_check_media(mii->dev, 0);
1103 if (debug > 1)
1104 printk(KERN_INFO "%s: force_media %d, carrier %d\n",
1105 mii->dev->name, mii->force_media,
1106 netif_carrier_ok(mii->dev));
1da177e4
LT		 1107}
1108
6ba98d31
JL		 1109static void rhine_check_media_task(struct net_device *dev)
1110{
1111 rhine_check_media(dev, 0);
1112}
1113
1da177e4
LT		 1114static void init_registers(struct net_device *dev)
1115{
1116 struct rhine_private *rp = netdev_priv(dev);
1117 void __iomem *ioaddr = rp->base;
1118 int i;
1119
1120 for (i = 0; i < 6; i++)
1121 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1122
1123 /* Initialize other registers. */
1124 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1125 /* Configure initial FIFO thresholds. */
1126 iowrite8(0x20, ioaddr + TxConfig);
1127 rp->tx_thresh = 0x20;
1128 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1129
1130 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1131 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1132
1133 rhine_set_rx_mode(dev);
1134
1135 /* Enable interrupts by setting the interrupt mask. */
1136 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1137 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1138 IntrTxDone | IntrTxError | IntrTxUnderrun |
1139 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1140 ioaddr + IntrEnable);
1141
1142 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1143 ioaddr + ChipCmd);
1144 rhine_check_media(dev, 1);
1145}
1146
1147/* Enable MII link status auto-polling (required for IntrLinkChange) */
1148static void rhine_enable_linkmon(void __iomem *ioaddr)
1149{
1150 iowrite8(0, ioaddr + MIICmd);
1151 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1152 iowrite8(0x80, ioaddr + MIICmd);
1153
1154 RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1155
1156 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1157}
1158
1159/* Disable MII link status auto-polling (required for MDIO access) */
1160static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1161{
1162 iowrite8(0, ioaddr + MIICmd);
1163
1164 if (quirks & rqRhineI) {
1165 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1166
6ba98d31
JL		 1167 /* Do not call from ISR! */
1168 msleep(1);
1da177e4
LT		 1169
1170 /* 0x80 must be set immediately before turning it off */
1171 iowrite8(0x80, ioaddr + MIICmd);
1172
1173 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1174
1175 /* Heh. Now clear 0x80 again. */
1176 iowrite8(0, ioaddr + MIICmd);
1177 }
1178 else
1179 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1180}
1181
1182/* Read and write over the MII Management Data I/O (MDIO) interface. */
1183
1184static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1185{
1186 struct rhine_private *rp = netdev_priv(dev);
1187 void __iomem *ioaddr = rp->base;
1188 int result;
1189
1190 rhine_disable_linkmon(ioaddr, rp->quirks);
1191
1192 /* rhine_disable_linkmon already cleared MIICmd */
1193 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1194 iowrite8(regnum, ioaddr + MIIRegAddr);
1195 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1196 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1197 result = ioread16(ioaddr + MIIData);
1198
1199 rhine_enable_linkmon(ioaddr);
1200 return result;
1201}
1202
1203static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1204{
1205 struct rhine_private *rp = netdev_priv(dev);
1206 void __iomem *ioaddr = rp->base;
1207
1208 rhine_disable_linkmon(ioaddr, rp->quirks);
1209
1210 /* rhine_disable_linkmon already cleared MIICmd */
1211 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1212 iowrite8(regnum, ioaddr + MIIRegAddr);
1213 iowrite16(value, ioaddr + MIIData);
1214 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1215 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1216
1217 rhine_enable_linkmon(ioaddr);
1218}
1219
1220static int rhine_open(struct net_device *dev)
1221{
1222 struct rhine_private *rp = netdev_priv(dev);
1223 void __iomem *ioaddr = rp->base;
1224 int rc;
1225
1226 rc = request_irq(rp->pdev->irq, &rhine_interrupt, SA_SHIRQ, dev->name,
1227 dev);
1228 if (rc)
1229 return rc;
1230
1231 if (debug > 1)
1232 printk(KERN_DEBUG "%s: rhine_open() irq %d.\n",
1233 dev->name, rp->pdev->irq);
1234
1235 rc = alloc_ring(dev);
1236 if (rc) {
1237 free_irq(rp->pdev->irq, dev);
1238 return rc;
1239 }
1240 alloc_rbufs(dev);
1241 alloc_tbufs(dev);
1242 rhine_chip_reset(dev);
1243 init_registers(dev);
1244 if (debug > 2)
1245 printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
1246 "MII status: %4.4x.\n",
1247 dev->name, ioread16(ioaddr + ChipCmd),
1248 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1249
1250 netif_start_queue(dev);
1251
1252 return 0;
1253}
1254
1255static void rhine_tx_timeout(struct net_device *dev)
6ba98d31
JL		 1256{
1257 struct rhine_private *rp = netdev_priv(dev);
1258
1259 /*
1260 * Move bulk of work outside of interrupt context
1261 */
1262 schedule_work(&rp->tx_timeout_task);
1263}
1264
1265static void rhine_tx_timeout_task(struct net_device *dev)
1da177e4
LT		 1266{
1267 struct rhine_private *rp = netdev_priv(dev);
1268 void __iomem *ioaddr = rp->base;
1269
1270 printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status "
1271 "%4.4x, resetting...\n",
1272 dev->name, ioread16(ioaddr + IntrStatus),
1273 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1274
1275 /* protect against concurrent rx interrupts */
1276 disable_irq(rp->pdev->irq);
1277
1278 spin_lock(&rp->lock);
1279
1280 /* clear all descriptors */
1281 free_tbufs(dev);
1282 free_rbufs(dev);
1283 alloc_tbufs(dev);
1284 alloc_rbufs(dev);
1285
1286 /* Reinitialize the hardware. */
1287 rhine_chip_reset(dev);
1288 init_registers(dev);
1289
1290 spin_unlock(&rp->lock);
1291 enable_irq(rp->pdev->irq);
1292
1293 dev->trans_start = jiffies;
1294 rp->stats.tx_errors++;
1295 netif_wake_queue(dev);
1296}
1297
1298static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev)
1299{
1300 struct rhine_private *rp = netdev_priv(dev);
1301 void __iomem *ioaddr = rp->base;
1302 unsigned entry;
1303
1304 /* Caution: the write order is important here, set the field
1305 with the "ownership" bits last. */
1306
1307 /* Calculate the next Tx descriptor entry. */
1308 entry = rp->cur_tx % TX_RING_SIZE;
1309
1310 if (skb->len < ETH_ZLEN) {
1311 skb = skb_padto(skb, ETH_ZLEN);
1312 if (skb == NULL)
1313 return 0;
1314 }
1315
1316 rp->tx_skbuff[entry] = skb;
1317
1318 if ((rp->quirks & rqRhineI) &&
1319 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_HW)) {
1320 /* Must use alignment buffer. */
1321 if (skb->len > PKT_BUF_SZ) {
1322 /* packet too long, drop it */
1323 dev_kfree_skb(skb);
1324 rp->tx_skbuff[entry] = NULL;
1325 rp->stats.tx_dropped++;
1326 return 0;
1327 }
1328 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1329 rp->tx_skbuff_dma[entry] = 0;
1330 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1331 (rp->tx_buf[entry] -
1332 rp->tx_bufs));
1333 } else {
1334 rp->tx_skbuff_dma[entry] =
1335 pci_map_single(rp->pdev, skb->data, skb->len,
1336 PCI_DMA_TODEVICE);
1337 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1338 }
1339
1340 rp->tx_ring[entry].desc_length =
1341 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1342
1343 /* lock eth irq */
1344 spin_lock_irq(&rp->lock);
1345 wmb();
1346 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1347 wmb();
1348
1349 rp->cur_tx++;
1350
1351 /* Non-x86 Todo: explicitly flush cache lines here. */
1352
1353 /* Wake the potentially-idle transmit channel */
1354 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1355 ioaddr + ChipCmd1);
1356 IOSYNC;
1357
1358 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1359 netif_stop_queue(dev);
1360
1361 dev->trans_start = jiffies;
1362
1363 spin_unlock_irq(&rp->lock);
1364
1365 if (debug > 4) {
1366 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1367 dev->name, rp->cur_tx-1, entry);
1368 }
1369 return 0;
1370}
1371
1372/* The interrupt handler does all of the Rx thread work and cleans up
1373 after the Tx thread. */
1374static irqreturn_t rhine_interrupt(int irq, void *dev_instance, struct pt_regs *rgs)
1375{
1376 struct net_device *dev = dev_instance;
1377 struct rhine_private *rp = netdev_priv(dev);
1378 void __iomem *ioaddr = rp->base;
1379 u32 intr_status;
1380 int boguscnt = max_interrupt_work;
1381 int handled = 0;
1382
1383 while ((intr_status = get_intr_status(dev))) {
1384 handled = 1;
1385
1386 /* Acknowledge all of the current interrupt sources ASAP. */
1387 if (intr_status & IntrTxDescRace)
1388 iowrite8(0x08, ioaddr + IntrStatus2);
1389 iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1390 IOSYNC;
1391
1392 if (debug > 4)
1393 printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n",
1394 dev->name, intr_status);
1395
1396 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
1397 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf))
1398 rhine_rx(dev);
1399
1400 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1401 if (intr_status & IntrTxErrSummary) {
1402 /* Avoid scavenging before Tx engine turned off */
1403 RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1404 if (debug > 2 &&
1405 ioread8(ioaddr+ChipCmd) & CmdTxOn)
1406 printk(KERN_WARNING "%s: "
1407 "rhine_interrupt() Tx engine"
1408 "still on.\n", dev->name);
1409 }
1410 rhine_tx(dev);
1411 }
1412
1413 /* Abnormal error summary/uncommon events handlers. */
1414 if (intr_status & (IntrPCIErr | IntrLinkChange |
1415 IntrStatsMax | IntrTxError | IntrTxAborted |
1416 IntrTxUnderrun | IntrTxDescRace))
1417 rhine_error(dev, intr_status);
1418
1419 if (--boguscnt < 0) {
1420 printk(KERN_WARNING "%s: Too much work at interrupt, "
1421 "status=%#8.8x.\n",
1422 dev->name, intr_status);
1423 break;
1424 }
1425 }
1426
1427 if (debug > 3)
1428 printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n",
1429 dev->name, ioread16(ioaddr + IntrStatus));
1430 return IRQ_RETVAL(handled);
1431}
1432
1433/* This routine is logically part of the interrupt handler, but isolated
1434 for clarity. */
1435static void rhine_tx(struct net_device *dev)
1436{
1437 struct rhine_private *rp = netdev_priv(dev);
1438 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1439
1440 spin_lock(&rp->lock);
1441
1442 /* find and cleanup dirty tx descriptors */
1443 while (rp->dirty_tx != rp->cur_tx) {
1444 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1445 if (debug > 6)
ed4030d1 1446 printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
1da177e4
LT		 1447 entry, txstatus);
1448 if (txstatus & DescOwn)
1449 break;
1450 if (txstatus & 0x8000) {
1451 if (debug > 1)
1452 printk(KERN_DEBUG "%s: Transmit error, "
1453 "Tx status %8.8x.\n",
1454 dev->name, txstatus);
1455 rp->stats.tx_errors++;
1456 if (txstatus & 0x0400) rp->stats.tx_carrier_errors++;
1457 if (txstatus & 0x0200) rp->stats.tx_window_errors++;
1458 if (txstatus & 0x0100) rp->stats.tx_aborted_errors++;
1459 if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++;
1460 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1461 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1462 rp->stats.tx_fifo_errors++;
1463 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1464 break; /* Keep the skb - we try again */
1465 }
1466 /* Transmitter restarted in 'abnormal' handler. */
1467 } else {
1468 if (rp->quirks & rqRhineI)
1469 rp->stats.collisions += (txstatus >> 3) & 0x0F;
1470 else
1471 rp->stats.collisions += txstatus & 0x0F;
1472 if (debug > 6)
1473 printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n",
1474 (txstatus >> 3) & 0xF,
1475 txstatus & 0xF);
1476 rp->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1477 rp->stats.tx_packets++;
1478 }
1479 /* Free the original skb. */
1480 if (rp->tx_skbuff_dma[entry]) {
1481 pci_unmap_single(rp->pdev,
1482 rp->tx_skbuff_dma[entry],
1483 rp->tx_skbuff[entry]->len,
1484 PCI_DMA_TODEVICE);
1485 }
1486 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1487 rp->tx_skbuff[entry] = NULL;
1488 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1489 }
1490 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1491 netif_wake_queue(dev);
1492
1493 spin_unlock(&rp->lock);
1494}
1495
1496/* This routine is logically part of the interrupt handler, but isolated
1497 for clarity and better register allocation. */
1498static void rhine_rx(struct net_device *dev)
1499{
1500 struct rhine_private *rp = netdev_priv(dev);
1501 int entry = rp->cur_rx % RX_RING_SIZE;
1502 int boguscnt = rp->dirty_rx + RX_RING_SIZE - rp->cur_rx;
1503
1504 if (debug > 4) {
1505 printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n",
1506 dev->name, entry,
1507 le32_to_cpu(rp->rx_head_desc->rx_status));
1508 }
1509
1510 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1511 while (!(rp->rx_head_desc->rx_status & cpu_to_le32(DescOwn))) {
1512 struct rx_desc *desc = rp->rx_head_desc;
1513 u32 desc_status = le32_to_cpu(desc->rx_status);
1514 int data_size = desc_status >> 16;
1515
1516 if (debug > 4)
ed4030d1 1517 printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
1da177e4
LT		 1518 desc_status);
1519 if (--boguscnt < 0)
1520 break;
1521 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1522 if ((desc_status & RxWholePkt) != RxWholePkt) {
1523 printk(KERN_WARNING "%s: Oversized Ethernet "
1524 "frame spanned multiple buffers, entry "
1525 "%#x length %d status %8.8x!\n",
1526 dev->name, entry, data_size,
1527 desc_status);
1528 printk(KERN_WARNING "%s: Oversized Ethernet "
1529 "frame %p vs %p.\n", dev->name,
1530 rp->rx_head_desc, &rp->rx_ring[entry]);
1531 rp->stats.rx_length_errors++;
1532 } else if (desc_status & RxErr) {
1533 /* There was a error. */
1534 if (debug > 2)
ed4030d1 1535 printk(KERN_DEBUG "rhine_rx() Rx "
1da177e4
LT		 1536 "error was %8.8x.\n",
1537 desc_status);
1538 rp->stats.rx_errors++;
1539 if (desc_status & 0x0030) rp->stats.rx_length_errors++;
1540 if (desc_status & 0x0048) rp->stats.rx_fifo_errors++;
1541 if (desc_status & 0x0004) rp->stats.rx_frame_errors++;
1542 if (desc_status & 0x0002) {
1543 /* this can also be updated outside the interrupt handler */
1544 spin_lock(&rp->lock);
1545 rp->stats.rx_crc_errors++;
1546 spin_unlock(&rp->lock);
1547 }
1548 }
1549 } else {
1550 struct sk_buff *skb;
1551 /* Length should omit the CRC */
1552 int pkt_len = data_size - 4;
1553
1554 /* Check if the packet is long enough to accept without
1555 copying to a minimally-sized skbuff. */
1556 if (pkt_len < rx_copybreak &&
1557 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1558 skb->dev = dev;
1559 skb_reserve(skb, 2); /* 16 byte align the IP header */
1560 pci_dma_sync_single_for_cpu(rp->pdev,
1561 rp->rx_skbuff_dma[entry],
1562 rp->rx_buf_sz,
1563 PCI_DMA_FROMDEVICE);
1564
1565 eth_copy_and_sum(skb,
689be439 1566 rp->rx_skbuff[entry]->data,
1da177e4
LT		 1567 pkt_len, 0);
1568 skb_put(skb, pkt_len);
1569 pci_dma_sync_single_for_device(rp->pdev,
1570 rp->rx_skbuff_dma[entry],
1571 rp->rx_buf_sz,
1572 PCI_DMA_FROMDEVICE);
1573 } else {
1574 skb = rp->rx_skbuff[entry];
1575 if (skb == NULL) {
1576 printk(KERN_ERR "%s: Inconsistent Rx "
1577 "descriptor chain.\n",
1578 dev->name);
1579 break;
1580 }
1581 rp->rx_skbuff[entry] = NULL;
1582 skb_put(skb, pkt_len);
1583 pci_unmap_single(rp->pdev,
1584 rp->rx_skbuff_dma[entry],
1585 rp->rx_buf_sz,
1586 PCI_DMA_FROMDEVICE);
1587 }
1588 skb->protocol = eth_type_trans(skb, dev);
1589 netif_rx(skb);
1590 dev->last_rx = jiffies;
1591 rp->stats.rx_bytes += pkt_len;
1592 rp->stats.rx_packets++;
1593 }
1594 entry = (++rp->cur_rx) % RX_RING_SIZE;
1595 rp->rx_head_desc = &rp->rx_ring[entry];
1596 }
1597
1598 /* Refill the Rx ring buffers. */
1599 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1600 struct sk_buff *skb;
1601 entry = rp->dirty_rx % RX_RING_SIZE;
1602 if (rp->rx_skbuff[entry] == NULL) {
1603 skb = dev_alloc_skb(rp->rx_buf_sz);
1604 rp->rx_skbuff[entry] = skb;
1605 if (skb == NULL)
1606 break; /* Better luck next round. */
1607 skb->dev = dev; /* Mark as being used by this device. */
1608 rp->rx_skbuff_dma[entry] =
689be439 1609 pci_map_single(rp->pdev, skb->data,
1da177e4
LT		 1610 rp->rx_buf_sz,
1611 PCI_DMA_FROMDEVICE);
1612 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1613 }
1614 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1615 }
1616}
1617
1618/*
1619 * Clears the "tally counters" for CRC errors and missed frames(?).
1620 * It has been reported that some chips need a write of 0 to clear
1621 * these, for others the counters are set to 1 when written to and
1622 * instead cleared when read. So we clear them both ways ...
1623 */
1624static inline void clear_tally_counters(void __iomem *ioaddr)
1625{
1626 iowrite32(0, ioaddr + RxMissed);
1627 ioread16(ioaddr + RxCRCErrs);
1628 ioread16(ioaddr + RxMissed);
1629}
1630
1631static void rhine_restart_tx(struct net_device *dev) {
1632 struct rhine_private *rp = netdev_priv(dev);
1633 void __iomem *ioaddr = rp->base;
1634 int entry = rp->dirty_tx % TX_RING_SIZE;
1635 u32 intr_status;
1636
1637 /*
1638 * If new errors occured, we need to sort them out before doing Tx.
1639 * In that case the ISR will be back here RSN anyway.
1640 */
1641 intr_status = get_intr_status(dev);
1642
1643 if ((intr_status & IntrTxErrSummary) == 0) {
1644
1645 /* We know better than the chip where it should continue. */
1646 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1647 ioaddr + TxRingPtr);
1648
1649 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1650 ioaddr + ChipCmd);
1651 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1652 ioaddr + ChipCmd1);
1653 IOSYNC;
1654 }
1655 else {
1656 /* This should never happen */
1657 if (debug > 1)
1658 printk(KERN_WARNING "%s: rhine_restart_tx() "
1659 "Another error occured %8.8x.\n",
1660 dev->name, intr_status);
1661 }
1662
1663}
1664
1665static void rhine_error(struct net_device *dev, int intr_status)
1666{
1667 struct rhine_private *rp = netdev_priv(dev);
1668 void __iomem *ioaddr = rp->base;
1669
1670 spin_lock(&rp->lock);
1671
1672 if (intr_status & IntrLinkChange)
6ba98d31 1673 schedule_work(&rp->check_media_task);
1da177e4
LT		 1674 if (intr_status & IntrStatsMax) {
1675 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1676 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1677 clear_tally_counters(ioaddr);
1678 }
1679 if (intr_status & IntrTxAborted) {
1680 if (debug > 1)
1681 printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n",
1682 dev->name, intr_status);
1683 }
1684 if (intr_status & IntrTxUnderrun) {
1685 if (rp->tx_thresh < 0xE0)
1686 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1687 if (debug > 1)
1688 printk(KERN_INFO "%s: Transmitter underrun, Tx "
1689 "threshold now %2.2x.\n",
1690 dev->name, rp->tx_thresh);
1691 }
1692 if (intr_status & IntrTxDescRace) {
1693 if (debug > 2)
1694 printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
1695 dev->name);
1696 }
1697 if ((intr_status & IntrTxError) &&
1698 (intr_status & (IntrTxAborted |
1699 IntrTxUnderrun | IntrTxDescRace)) == 0) {
1700 if (rp->tx_thresh < 0xE0) {
1701 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1702 }
1703 if (debug > 1)
1704 printk(KERN_INFO "%s: Unspecified error. Tx "
1705 "threshold now %2.2x.\n",
1706 dev->name, rp->tx_thresh);
1707 }
1708 if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1709 IntrTxError))
1710 rhine_restart_tx(dev);
1711
1712 if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1713 IntrTxError | IntrTxAborted | IntrNormalSummary |
1714 IntrTxDescRace)) {
1715 if (debug > 1)
1716 printk(KERN_ERR "%s: Something Wicked happened! "
1717 "%8.8x.\n", dev->name, intr_status);
1718 }
1719
1720 spin_unlock(&rp->lock);
1721}
1722
1723static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1724{
1725 struct rhine_private *rp = netdev_priv(dev);
1726 void __iomem *ioaddr = rp->base;
1727 unsigned long flags;
1728
1729 spin_lock_irqsave(&rp->lock, flags);
1730 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1731 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1732 clear_tally_counters(ioaddr);
1733 spin_unlock_irqrestore(&rp->lock, flags);
1734
1735 return &rp->stats;
1736}
1737
1738static void rhine_set_rx_mode(struct net_device *dev)
1739{
1740 struct rhine_private *rp = netdev_priv(dev);
1741 void __iomem *ioaddr = rp->base;
1742 u32 mc_filter[2]; /* Multicast hash filter */
1743 u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */
1744
1745 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1746 /* Unconditionally log net taps. */
1747 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1748 dev->name);
1749 rx_mode = 0x1C;
1750 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1751 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1752 } else if ((dev->mc_count > multicast_filter_limit)
1753 || (dev->flags & IFF_ALLMULTI)) {
1754 /* Too many to match, or accept all multicasts. */
1755 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1756 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1757 rx_mode = 0x0C;
1758 } else {
1759 struct dev_mc_list *mclist;
1760 int i;
1761 memset(mc_filter, 0, sizeof(mc_filter));
1762 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1763 i++, mclist = mclist->next) {
1764 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1765
1766 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1767 }
1768 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1769 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1770 rx_mode = 0x0C;
1771 }
1772 iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig);
1773}
1774
1775static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1776{
1777 struct rhine_private *rp = netdev_priv(dev);
1778
1779 strcpy(info->driver, DRV_NAME);
1780 strcpy(info->version, DRV_VERSION);
1781 strcpy(info->bus_info, pci_name(rp->pdev));
1782}
1783
1784static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1785{
1786 struct rhine_private *rp = netdev_priv(dev);
1787 int rc;
1788
1789 spin_lock_irq(&rp->lock);
1790 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1791 spin_unlock_irq(&rp->lock);
1792
1793 return rc;
1794}
1795
1796static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1797{
1798 struct rhine_private *rp = netdev_priv(dev);
1799 int rc;
1800
1801 spin_lock_irq(&rp->lock);
1802 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1803 spin_unlock_irq(&rp->lock);
00b428c2 1804 rhine_set_carrier(&rp->mii_if);
1da177e4
LT		 1805
1806 return rc;
1807}
1808
1809static int netdev_nway_reset(struct net_device *dev)
1810{
1811 struct rhine_private *rp = netdev_priv(dev);
1812
1813 return mii_nway_restart(&rp->mii_if);
1814}
1815
1816static u32 netdev_get_link(struct net_device *dev)
1817{
1818 struct rhine_private *rp = netdev_priv(dev);
1819
1820 return mii_link_ok(&rp->mii_if);
1821}
1822
1823static u32 netdev_get_msglevel(struct net_device *dev)
1824{
1825 return debug;
1826}
1827
1828static void netdev_set_msglevel(struct net_device *dev, u32 value)
1829{
1830 debug = value;
1831}
1832
1833static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1834{
1835 struct rhine_private *rp = netdev_priv(dev);
1836
1837 if (!(rp->quirks & rqWOL))
1838 return;
1839
1840 spin_lock_irq(&rp->lock);
1841 wol->supported = WAKE_PHY | WAKE_MAGIC |
1842 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1843 wol->wolopts = rp->wolopts;
1844 spin_unlock_irq(&rp->lock);
1845}
1846
1847static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1848{
1849 struct rhine_private *rp = netdev_priv(dev);
1850 u32 support = WAKE_PHY | WAKE_MAGIC |
1851 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1852
1853 if (!(rp->quirks & rqWOL))
1854 return -EINVAL;
1855
1856 if (wol->wolopts & ~support)
1857 return -EINVAL;
1858
1859 spin_lock_irq(&rp->lock);
1860 rp->wolopts = wol->wolopts;
1861 spin_unlock_irq(&rp->lock);
1862
1863 return 0;
1864}
1865
1866static struct ethtool_ops netdev_ethtool_ops = {
1867 .get_drvinfo = netdev_get_drvinfo,
1868 .get_settings = netdev_get_settings,
1869 .set_settings = netdev_set_settings,
1870 .nway_reset = netdev_nway_reset,
1871 .get_link = netdev_get_link,
1872 .get_msglevel = netdev_get_msglevel,
1873 .set_msglevel = netdev_set_msglevel,
1874 .get_wol = rhine_get_wol,
1875 .set_wol = rhine_set_wol,
1876 .get_sg = ethtool_op_get_sg,
1877 .get_tx_csum = ethtool_op_get_tx_csum,
b81e8e1f 1878 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1879};
1880
1881static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1882{
1883 struct rhine_private *rp = netdev_priv(dev);
1884 int rc;
1885
1886 if (!netif_running(dev))
1887 return -EINVAL;
1888
1889 spin_lock_irq(&rp->lock);
1890 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
1891 spin_unlock_irq(&rp->lock);
00b428c2 1892 rhine_set_carrier(&rp->mii_if);
1da177e4
LT		 1893
1894 return rc;
1895}
1896
1897static int rhine_close(struct net_device *dev)
1898{
1899 struct rhine_private *rp = netdev_priv(dev);
1900 void __iomem *ioaddr = rp->base;
1901
1902 spin_lock_irq(&rp->lock);
1903
1904 netif_stop_queue(dev);
1905
1906 if (debug > 1)
1907 printk(KERN_DEBUG "%s: Shutting down ethercard, "
1908 "status was %4.4x.\n",
1909 dev->name, ioread16(ioaddr + ChipCmd));
1910
1911 /* Switch to loopback mode to avoid hardware races. */
1912 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
1913
1914 /* Disable interrupts by clearing the interrupt mask. */
1915 iowrite16(0x0000, ioaddr + IntrEnable);
1916
1917 /* Stop the chip's Tx and Rx processes. */
1918 iowrite16(CmdStop, ioaddr + ChipCmd);
1919
1920 spin_unlock_irq(&rp->lock);
1921
1922 free_irq(rp->pdev->irq, dev);
6ba98d31
JL		 1923
1924 flush_scheduled_work();
1925
1da177e4
LT		 1926 free_rbufs(dev);
1927 free_tbufs(dev);
1928 free_ring(dev);
1929
1930 return 0;
1931}
1932
1933
1934static void __devexit rhine_remove_one(struct pci_dev *pdev)
1935{
1936 struct net_device *dev = pci_get_drvdata(pdev);
1937 struct rhine_private *rp = netdev_priv(dev);
1938
1939 unregister_netdev(dev);
1940
1941 pci_iounmap(pdev, rp->base);
1942 pci_release_regions(pdev);
1943
1944 free_netdev(dev);
1945 pci_disable_device(pdev);
1946 pci_set_drvdata(pdev, NULL);
1947}
1948
d18c3db5 1949static void rhine_shutdown (struct pci_dev *pdev)
1da177e4 1950{
1da177e4
LT		 1951 struct net_device *dev = pci_get_drvdata(pdev);
1952 struct rhine_private *rp = netdev_priv(dev);
1953 void __iomem *ioaddr = rp->base;
1954
1955 if (!(rp->quirks & rqWOL))
1956 return; /* Nothing to do for non-WOL adapters */
1957
1958 rhine_power_init(dev);
1959
1960 /* Make sure we use pattern 0, 1 and not 4, 5 */
1961 if (rp->quirks & rq6patterns)
1962 iowrite8(0x04, ioaddr + 0xA7);
1963
1964 if (rp->wolopts & WAKE_MAGIC) {
1965 iowrite8(WOLmagic, ioaddr + WOLcrSet);
1966 /*
1967 * Turn EEPROM-controlled wake-up back on -- some hardware may
1968 * not cooperate otherwise.
1969 */
1970 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
1971 }
1972
1973 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
1974 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
1975
1976 if (rp->wolopts & WAKE_PHY)
1977 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
1978
1979 if (rp->wolopts & WAKE_UCAST)
1980 iowrite8(WOLucast, ioaddr + WOLcrSet);
1981
1982 if (rp->wolopts) {
1983 /* Enable legacy WOL (for old motherboards) */
1984 iowrite8(0x01, ioaddr + PwcfgSet);
1985 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
1986 }
1987
1988 /* Hit power state D3 (sleep) */
1989 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
1990
1991 /* TODO: Check use of pci_enable_wake() */
1992
1993}
1994
1995#ifdef CONFIG_PM
1996static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
1997{
1998 struct net_device *dev = pci_get_drvdata(pdev);
1999 struct rhine_private *rp = netdev_priv(dev);
2000 unsigned long flags;
2001
2002 if (!netif_running(dev))
2003 return 0;
2004
2005 netif_device_detach(dev);
2006 pci_save_state(pdev);
2007
2008 spin_lock_irqsave(&rp->lock, flags);
d18c3db5 2009 rhine_shutdown(pdev);
1da177e4
LT		 2010 spin_unlock_irqrestore(&rp->lock, flags);
2011
2012 free_irq(dev->irq, dev);
2013 return 0;
2014}
2015
2016static int rhine_resume(struct pci_dev *pdev)
2017{
2018 struct net_device *dev = pci_get_drvdata(pdev);
2019 struct rhine_private *rp = netdev_priv(dev);
2020 unsigned long flags;
2021 int ret;
2022
2023 if (!netif_running(dev))
2024 return 0;
2025
2026 if (request_irq(dev->irq, rhine_interrupt, SA_SHIRQ, dev->name, dev))
2027 printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
2028
2029 ret = pci_set_power_state(pdev, PCI_D0);
2030 if (debug > 1)
2031 printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n",
2032 dev->name, ret ? "failed" : "succeeded", ret);
2033
2034 pci_restore_state(pdev);
2035
2036 spin_lock_irqsave(&rp->lock, flags);
2037#ifdef USE_MMIO
2038 enable_mmio(rp->pioaddr, rp->quirks);
2039#endif
2040 rhine_power_init(dev);
2041 free_tbufs(dev);
2042 free_rbufs(dev);
2043 alloc_tbufs(dev);
2044 alloc_rbufs(dev);
2045 init_registers(dev);
2046 spin_unlock_irqrestore(&rp->lock, flags);
2047
2048 netif_device_attach(dev);
2049
2050 return 0;
2051}
2052#endif /* CONFIG_PM */
2053
2054static struct pci_driver rhine_driver = {
2055 .name = DRV_NAME,
2056 .id_table = rhine_pci_tbl,
2057 .probe = rhine_init_one,
2058 .remove = __devexit_p(rhine_remove_one),
2059#ifdef CONFIG_PM
2060 .suspend = rhine_suspend,
2061 .resume = rhine_resume,
2062#endif /* CONFIG_PM */
d18c3db5 2063 .shutdown = rhine_shutdown,
1da177e4
LT		 2064};
2065
2066
2067static int __init rhine_init(void)
2068{
2069/* when a module, this is printed whether or not devices are found in probe */
2070#ifdef MODULE
2071 printk(version);
2072#endif
2073 return pci_module_init(&rhine_driver);
2074}
2075
2076
2077static void __exit rhine_cleanup(void)
2078{
2079 pci_unregister_driver(&rhine_driver);
2080}
2081
2082
2083module_init(rhine_init);
2084module_exit(rhine_cleanup);
Linux 6.x block layer and io_uring tree(s)