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2f7ca802 SG |
1 | /*************************************************************************** |
2 | * | |
3 | * Copyright (C) 2007-2008 SMSC | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | * | |
19 | *****************************************************************************/ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/kmod.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/ethtool.h> | |
27 | #include <linux/mii.h> | |
28 | #include <linux/usb.h> | |
bbd9f9ee SG |
29 | #include <linux/bitrev.h> |
30 | #include <linux/crc16.h> | |
2f7ca802 SG |
31 | #include <linux/crc32.h> |
32 | #include <linux/usb/usbnet.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2f7ca802 SG |
34 | #include "smsc95xx.h" |
35 | ||
36 | #define SMSC_CHIPNAME "smsc95xx" | |
f7b29271 | 37 | #define SMSC_DRIVER_VERSION "1.0.4" |
2f7ca802 SG |
38 | #define HS_USB_PKT_SIZE (512) |
39 | #define FS_USB_PKT_SIZE (64) | |
40 | #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) | |
41 | #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) | |
42 | #define DEFAULT_BULK_IN_DELAY (0x00002000) | |
43 | #define MAX_SINGLE_PACKET_SIZE (2048) | |
44 | #define LAN95XX_EEPROM_MAGIC (0x9500) | |
45 | #define EEPROM_MAC_OFFSET (0x01) | |
f7b29271 | 46 | #define DEFAULT_TX_CSUM_ENABLE (true) |
2f7ca802 SG |
47 | #define DEFAULT_RX_CSUM_ENABLE (true) |
48 | #define SMSC95XX_INTERNAL_PHY_ID (1) | |
49 | #define SMSC95XX_TX_OVERHEAD (8) | |
f7b29271 | 50 | #define SMSC95XX_TX_OVERHEAD_CSUM (12) |
bbd9f9ee SG |
51 | #define SUPPORTED_WAKE (WAKE_UCAST | WAKE_BCAST | \ |
52 | WAKE_MCAST | WAKE_ARP | WAKE_MAGIC) | |
2f7ca802 | 53 | |
769ea6d8 SG |
54 | #define check_warn(ret, fmt, args...) \ |
55 | ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); }) | |
56 | ||
57 | #define check_warn_return(ret, fmt, args...) \ | |
58 | ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } }) | |
59 | ||
60 | #define check_warn_goto_done(ret, fmt, args...) \ | |
61 | ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } }) | |
62 | ||
2f7ca802 SG |
63 | struct smsc95xx_priv { |
64 | u32 mac_cr; | |
3c0f3c60 MZ |
65 | u32 hash_hi; |
66 | u32 hash_lo; | |
e0e474a8 | 67 | u32 wolopts; |
2f7ca802 | 68 | spinlock_t mac_cr_lock; |
bbd9f9ee | 69 | int wuff_filter_count; |
2f7ca802 SG |
70 | }; |
71 | ||
eb939922 | 72 | static bool turbo_mode = true; |
2f7ca802 SG |
73 | module_param(turbo_mode, bool, 0644); |
74 | MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); | |
75 | ||
769ea6d8 SG |
76 | static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index, |
77 | u32 *data) | |
2f7ca802 | 78 | { |
72108fd2 | 79 | u32 buf; |
2f7ca802 SG |
80 | int ret; |
81 | ||
82 | BUG_ON(!dev); | |
83 | ||
72108fd2 ML |
84 | ret = usbnet_read_cmd(dev, USB_VENDOR_REQUEST_READ_REGISTER, |
85 | USB_DIR_IN | USB_TYPE_VENDOR | | |
86 | USB_RECIP_DEVICE, | |
87 | 0, index, &buf, 4); | |
2f7ca802 | 88 | if (unlikely(ret < 0)) |
60b86755 | 89 | netdev_warn(dev->net, "Failed to read register index 0x%08x\n", index); |
2f7ca802 | 90 | |
72108fd2 ML |
91 | le32_to_cpus(&buf); |
92 | *data = buf; | |
2f7ca802 SG |
93 | |
94 | return ret; | |
95 | } | |
96 | ||
769ea6d8 SG |
97 | static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index, |
98 | u32 data) | |
2f7ca802 | 99 | { |
72108fd2 | 100 | u32 buf; |
2f7ca802 SG |
101 | int ret; |
102 | ||
103 | BUG_ON(!dev); | |
104 | ||
72108fd2 ML |
105 | buf = data; |
106 | cpu_to_le32s(&buf); | |
2f7ca802 | 107 | |
2f7ca802 | 108 | |
72108fd2 ML |
109 | ret = usbnet_write_cmd(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, |
110 | USB_DIR_OUT | USB_TYPE_VENDOR | | |
111 | USB_RECIP_DEVICE, | |
112 | 0, index, &buf, 4); | |
2f7ca802 | 113 | if (unlikely(ret < 0)) |
60b86755 | 114 | netdev_warn(dev->net, "Failed to write register index 0x%08x\n", index); |
2f7ca802 | 115 | |
2f7ca802 SG |
116 | return ret; |
117 | } | |
118 | ||
e0e474a8 SG |
119 | static int smsc95xx_set_feature(struct usbnet *dev, u32 feature) |
120 | { | |
121 | if (WARN_ON_ONCE(!dev)) | |
122 | return -EINVAL; | |
123 | ||
72108fd2 ML |
124 | return usbnet_write_cmd(dev, USB_REQ_SET_FEATURE, |
125 | USB_RECIP_DEVICE, feature, 0, NULL, 0); | |
e0e474a8 SG |
126 | } |
127 | ||
128 | static int smsc95xx_clear_feature(struct usbnet *dev, u32 feature) | |
129 | { | |
130 | if (WARN_ON_ONCE(!dev)) | |
131 | return -EINVAL; | |
132 | ||
72108fd2 ML |
133 | return usbnet_write_cmd(dev, USB_REQ_CLEAR_FEATURE, |
134 | USB_RECIP_DEVICE, feature, 0, NULL, 0); | |
e0e474a8 SG |
135 | } |
136 | ||
2f7ca802 SG |
137 | /* Loop until the read is completed with timeout |
138 | * called with phy_mutex held */ | |
769ea6d8 | 139 | static int __must_check smsc95xx_phy_wait_not_busy(struct usbnet *dev) |
2f7ca802 SG |
140 | { |
141 | unsigned long start_time = jiffies; | |
142 | u32 val; | |
769ea6d8 | 143 | int ret; |
2f7ca802 SG |
144 | |
145 | do { | |
769ea6d8 SG |
146 | ret = smsc95xx_read_reg(dev, MII_ADDR, &val); |
147 | check_warn_return(ret, "Error reading MII_ACCESS"); | |
2f7ca802 SG |
148 | if (!(val & MII_BUSY_)) |
149 | return 0; | |
150 | } while (!time_after(jiffies, start_time + HZ)); | |
151 | ||
152 | return -EIO; | |
153 | } | |
154 | ||
155 | static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx) | |
156 | { | |
157 | struct usbnet *dev = netdev_priv(netdev); | |
158 | u32 val, addr; | |
769ea6d8 | 159 | int ret; |
2f7ca802 SG |
160 | |
161 | mutex_lock(&dev->phy_mutex); | |
162 | ||
163 | /* confirm MII not busy */ | |
769ea6d8 SG |
164 | ret = smsc95xx_phy_wait_not_busy(dev); |
165 | check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_read"); | |
2f7ca802 SG |
166 | |
167 | /* set the address, index & direction (read from PHY) */ | |
168 | phy_id &= dev->mii.phy_id_mask; | |
169 | idx &= dev->mii.reg_num_mask; | |
170 | addr = (phy_id << 11) | (idx << 6) | MII_READ_; | |
769ea6d8 SG |
171 | ret = smsc95xx_write_reg(dev, MII_ADDR, addr); |
172 | check_warn_goto_done(ret, "Error writing MII_ADDR"); | |
2f7ca802 | 173 | |
769ea6d8 SG |
174 | ret = smsc95xx_phy_wait_not_busy(dev); |
175 | check_warn_goto_done(ret, "Timed out reading MII reg %02X", idx); | |
2f7ca802 | 176 | |
769ea6d8 SG |
177 | ret = smsc95xx_read_reg(dev, MII_DATA, &val); |
178 | check_warn_goto_done(ret, "Error reading MII_DATA"); | |
2f7ca802 | 179 | |
769ea6d8 | 180 | ret = (u16)(val & 0xFFFF); |
2f7ca802 | 181 | |
769ea6d8 SG |
182 | done: |
183 | mutex_unlock(&dev->phy_mutex); | |
184 | return ret; | |
2f7ca802 SG |
185 | } |
186 | ||
187 | static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx, | |
188 | int regval) | |
189 | { | |
190 | struct usbnet *dev = netdev_priv(netdev); | |
191 | u32 val, addr; | |
769ea6d8 | 192 | int ret; |
2f7ca802 SG |
193 | |
194 | mutex_lock(&dev->phy_mutex); | |
195 | ||
196 | /* confirm MII not busy */ | |
769ea6d8 SG |
197 | ret = smsc95xx_phy_wait_not_busy(dev); |
198 | check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_write"); | |
2f7ca802 SG |
199 | |
200 | val = regval; | |
769ea6d8 SG |
201 | ret = smsc95xx_write_reg(dev, MII_DATA, val); |
202 | check_warn_goto_done(ret, "Error writing MII_DATA"); | |
2f7ca802 SG |
203 | |
204 | /* set the address, index & direction (write to PHY) */ | |
205 | phy_id &= dev->mii.phy_id_mask; | |
206 | idx &= dev->mii.reg_num_mask; | |
207 | addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; | |
769ea6d8 SG |
208 | ret = smsc95xx_write_reg(dev, MII_ADDR, addr); |
209 | check_warn_goto_done(ret, "Error writing MII_ADDR"); | |
2f7ca802 | 210 | |
769ea6d8 SG |
211 | ret = smsc95xx_phy_wait_not_busy(dev); |
212 | check_warn_goto_done(ret, "Timed out writing MII reg %02X", idx); | |
2f7ca802 | 213 | |
769ea6d8 | 214 | done: |
2f7ca802 SG |
215 | mutex_unlock(&dev->phy_mutex); |
216 | } | |
217 | ||
769ea6d8 | 218 | static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev) |
2f7ca802 SG |
219 | { |
220 | unsigned long start_time = jiffies; | |
221 | u32 val; | |
769ea6d8 | 222 | int ret; |
2f7ca802 SG |
223 | |
224 | do { | |
769ea6d8 SG |
225 | ret = smsc95xx_read_reg(dev, E2P_CMD, &val); |
226 | check_warn_return(ret, "Error reading E2P_CMD"); | |
2f7ca802 SG |
227 | if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) |
228 | break; | |
229 | udelay(40); | |
230 | } while (!time_after(jiffies, start_time + HZ)); | |
231 | ||
232 | if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { | |
60b86755 | 233 | netdev_warn(dev->net, "EEPROM read operation timeout\n"); |
2f7ca802 SG |
234 | return -EIO; |
235 | } | |
236 | ||
237 | return 0; | |
238 | } | |
239 | ||
769ea6d8 | 240 | static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev) |
2f7ca802 SG |
241 | { |
242 | unsigned long start_time = jiffies; | |
243 | u32 val; | |
769ea6d8 | 244 | int ret; |
2f7ca802 SG |
245 | |
246 | do { | |
769ea6d8 SG |
247 | ret = smsc95xx_read_reg(dev, E2P_CMD, &val); |
248 | check_warn_return(ret, "Error reading E2P_CMD"); | |
2f7ca802 | 249 | |
2f7ca802 SG |
250 | if (!(val & E2P_CMD_BUSY_)) |
251 | return 0; | |
252 | ||
253 | udelay(40); | |
254 | } while (!time_after(jiffies, start_time + HZ)); | |
255 | ||
60b86755 | 256 | netdev_warn(dev->net, "EEPROM is busy\n"); |
2f7ca802 SG |
257 | return -EIO; |
258 | } | |
259 | ||
260 | static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length, | |
261 | u8 *data) | |
262 | { | |
263 | u32 val; | |
264 | int i, ret; | |
265 | ||
266 | BUG_ON(!dev); | |
267 | BUG_ON(!data); | |
268 | ||
269 | ret = smsc95xx_eeprom_confirm_not_busy(dev); | |
270 | if (ret) | |
271 | return ret; | |
272 | ||
273 | for (i = 0; i < length; i++) { | |
274 | val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); | |
769ea6d8 SG |
275 | ret = smsc95xx_write_reg(dev, E2P_CMD, val); |
276 | check_warn_return(ret, "Error writing E2P_CMD"); | |
2f7ca802 SG |
277 | |
278 | ret = smsc95xx_wait_eeprom(dev); | |
279 | if (ret < 0) | |
280 | return ret; | |
281 | ||
769ea6d8 SG |
282 | ret = smsc95xx_read_reg(dev, E2P_DATA, &val); |
283 | check_warn_return(ret, "Error reading E2P_DATA"); | |
2f7ca802 SG |
284 | |
285 | data[i] = val & 0xFF; | |
286 | offset++; | |
287 | } | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length, | |
293 | u8 *data) | |
294 | { | |
295 | u32 val; | |
296 | int i, ret; | |
297 | ||
298 | BUG_ON(!dev); | |
299 | BUG_ON(!data); | |
300 | ||
301 | ret = smsc95xx_eeprom_confirm_not_busy(dev); | |
302 | if (ret) | |
303 | return ret; | |
304 | ||
305 | /* Issue write/erase enable command */ | |
306 | val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_; | |
769ea6d8 SG |
307 | ret = smsc95xx_write_reg(dev, E2P_CMD, val); |
308 | check_warn_return(ret, "Error writing E2P_DATA"); | |
2f7ca802 SG |
309 | |
310 | ret = smsc95xx_wait_eeprom(dev); | |
311 | if (ret < 0) | |
312 | return ret; | |
313 | ||
314 | for (i = 0; i < length; i++) { | |
315 | ||
316 | /* Fill data register */ | |
317 | val = data[i]; | |
769ea6d8 SG |
318 | ret = smsc95xx_write_reg(dev, E2P_DATA, val); |
319 | check_warn_return(ret, "Error writing E2P_DATA"); | |
2f7ca802 SG |
320 | |
321 | /* Send "write" command */ | |
322 | val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_); | |
769ea6d8 SG |
323 | ret = smsc95xx_write_reg(dev, E2P_CMD, val); |
324 | check_warn_return(ret, "Error writing E2P_CMD"); | |
2f7ca802 SG |
325 | |
326 | ret = smsc95xx_wait_eeprom(dev); | |
327 | if (ret < 0) | |
328 | return ret; | |
329 | ||
330 | offset++; | |
331 | } | |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
769ea6d8 SG |
336 | static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index, |
337 | u32 *data) | |
2f7ca802 | 338 | { |
1d74a6bd | 339 | const u16 size = 4; |
72108fd2 | 340 | int ret; |
2f7ca802 | 341 | |
72108fd2 ML |
342 | ret = usbnet_write_cmd_async(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, |
343 | USB_DIR_OUT | USB_TYPE_VENDOR | | |
344 | USB_RECIP_DEVICE, | |
345 | 0, index, data, size); | |
346 | if (ret < 0) | |
347 | netdev_warn(dev->net, "Error write async cmd, sts=%d\n", | |
348 | ret); | |
349 | return ret; | |
2f7ca802 SG |
350 | } |
351 | ||
352 | /* returns hash bit number for given MAC address | |
353 | * example: | |
354 | * 01 00 5E 00 00 01 -> returns bit number 31 */ | |
355 | static unsigned int smsc95xx_hash(char addr[ETH_ALEN]) | |
356 | { | |
357 | return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; | |
358 | } | |
359 | ||
360 | static void smsc95xx_set_multicast(struct net_device *netdev) | |
361 | { | |
362 | struct usbnet *dev = netdev_priv(netdev); | |
363 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
2f7ca802 | 364 | unsigned long flags; |
769ea6d8 | 365 | int ret; |
2f7ca802 | 366 | |
3c0f3c60 MZ |
367 | pdata->hash_hi = 0; |
368 | pdata->hash_lo = 0; | |
369 | ||
2f7ca802 SG |
370 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); |
371 | ||
372 | if (dev->net->flags & IFF_PROMISC) { | |
a475f603 | 373 | netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n"); |
2f7ca802 SG |
374 | pdata->mac_cr |= MAC_CR_PRMS_; |
375 | pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
376 | } else if (dev->net->flags & IFF_ALLMULTI) { | |
a475f603 | 377 | netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n"); |
2f7ca802 SG |
378 | pdata->mac_cr |= MAC_CR_MCPAS_; |
379 | pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_); | |
4cd24eaf | 380 | } else if (!netdev_mc_empty(dev->net)) { |
22bedad3 | 381 | struct netdev_hw_addr *ha; |
2f7ca802 SG |
382 | |
383 | pdata->mac_cr |= MAC_CR_HPFILT_; | |
384 | pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_); | |
385 | ||
22bedad3 JP |
386 | netdev_for_each_mc_addr(ha, netdev) { |
387 | u32 bitnum = smsc95xx_hash(ha->addr); | |
a92635dc JP |
388 | u32 mask = 0x01 << (bitnum & 0x1F); |
389 | if (bitnum & 0x20) | |
3c0f3c60 | 390 | pdata->hash_hi |= mask; |
a92635dc | 391 | else |
3c0f3c60 | 392 | pdata->hash_lo |= mask; |
2f7ca802 SG |
393 | } |
394 | ||
a475f603 | 395 | netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n", |
3c0f3c60 | 396 | pdata->hash_hi, pdata->hash_lo); |
2f7ca802 | 397 | } else { |
a475f603 | 398 | netif_dbg(dev, drv, dev->net, "receive own packets only\n"); |
2f7ca802 SG |
399 | pdata->mac_cr &= |
400 | ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
401 | } | |
402 | ||
403 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
404 | ||
405 | /* Initiate async writes, as we can't wait for completion here */ | |
769ea6d8 SG |
406 | ret = smsc95xx_write_reg_async(dev, HASHH, &pdata->hash_hi); |
407 | check_warn(ret, "failed to initiate async write to HASHH"); | |
408 | ||
409 | ret = smsc95xx_write_reg_async(dev, HASHL, &pdata->hash_lo); | |
410 | check_warn(ret, "failed to initiate async write to HASHL"); | |
411 | ||
412 | ret = smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr); | |
413 | check_warn(ret, "failed to initiate async write to MAC_CR"); | |
2f7ca802 SG |
414 | } |
415 | ||
769ea6d8 SG |
416 | static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex, |
417 | u16 lcladv, u16 rmtadv) | |
2f7ca802 SG |
418 | { |
419 | u32 flow, afc_cfg = 0; | |
420 | ||
421 | int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg); | |
769ea6d8 | 422 | check_warn_return(ret, "Error reading AFC_CFG"); |
2f7ca802 SG |
423 | |
424 | if (duplex == DUPLEX_FULL) { | |
bc02ff95 | 425 | u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
2f7ca802 SG |
426 | |
427 | if (cap & FLOW_CTRL_RX) | |
428 | flow = 0xFFFF0002; | |
429 | else | |
430 | flow = 0; | |
431 | ||
432 | if (cap & FLOW_CTRL_TX) | |
433 | afc_cfg |= 0xF; | |
434 | else | |
435 | afc_cfg &= ~0xF; | |
436 | ||
a475f603 | 437 | netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n", |
60b86755 JP |
438 | cap & FLOW_CTRL_RX ? "enabled" : "disabled", |
439 | cap & FLOW_CTRL_TX ? "enabled" : "disabled"); | |
2f7ca802 | 440 | } else { |
a475f603 | 441 | netif_dbg(dev, link, dev->net, "half duplex\n"); |
2f7ca802 SG |
442 | flow = 0; |
443 | afc_cfg |= 0xF; | |
444 | } | |
445 | ||
769ea6d8 SG |
446 | ret = smsc95xx_write_reg(dev, FLOW, flow); |
447 | check_warn_return(ret, "Error writing FLOW"); | |
448 | ||
449 | ret = smsc95xx_write_reg(dev, AFC_CFG, afc_cfg); | |
450 | check_warn_return(ret, "Error writing AFC_CFG"); | |
451 | ||
452 | return 0; | |
2f7ca802 SG |
453 | } |
454 | ||
455 | static int smsc95xx_link_reset(struct usbnet *dev) | |
456 | { | |
457 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
458 | struct mii_if_info *mii = &dev->mii; | |
8ae6daca | 459 | struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; |
2f7ca802 SG |
460 | unsigned long flags; |
461 | u16 lcladv, rmtadv; | |
769ea6d8 | 462 | int ret; |
2f7ca802 SG |
463 | |
464 | /* clear interrupt status */ | |
769ea6d8 SG |
465 | ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC); |
466 | check_warn_return(ret, "Error reading PHY_INT_SRC"); | |
467 | ||
468 | ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); | |
469 | check_warn_return(ret, "Error writing INT_STS"); | |
2f7ca802 SG |
470 | |
471 | mii_check_media(mii, 1, 1); | |
472 | mii_ethtool_gset(&dev->mii, &ecmd); | |
473 | lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE); | |
474 | rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA); | |
475 | ||
8ae6daca DD |
476 | netif_dbg(dev, link, dev->net, |
477 | "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n", | |
478 | ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv); | |
2f7ca802 SG |
479 | |
480 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); | |
481 | if (ecmd.duplex != DUPLEX_FULL) { | |
482 | pdata->mac_cr &= ~MAC_CR_FDPX_; | |
483 | pdata->mac_cr |= MAC_CR_RCVOWN_; | |
484 | } else { | |
485 | pdata->mac_cr &= ~MAC_CR_RCVOWN_; | |
486 | pdata->mac_cr |= MAC_CR_FDPX_; | |
487 | } | |
488 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
489 | ||
769ea6d8 SG |
490 | ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); |
491 | check_warn_return(ret, "Error writing MAC_CR"); | |
2f7ca802 | 492 | |
769ea6d8 SG |
493 | ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv); |
494 | check_warn_return(ret, "Error updating PHY flow control"); | |
2f7ca802 SG |
495 | |
496 | return 0; | |
497 | } | |
498 | ||
499 | static void smsc95xx_status(struct usbnet *dev, struct urb *urb) | |
500 | { | |
501 | u32 intdata; | |
502 | ||
503 | if (urb->actual_length != 4) { | |
60b86755 JP |
504 | netdev_warn(dev->net, "unexpected urb length %d\n", |
505 | urb->actual_length); | |
2f7ca802 SG |
506 | return; |
507 | } | |
508 | ||
509 | memcpy(&intdata, urb->transfer_buffer, 4); | |
1d74a6bd | 510 | le32_to_cpus(&intdata); |
2f7ca802 | 511 | |
a475f603 | 512 | netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata); |
2f7ca802 SG |
513 | |
514 | if (intdata & INT_ENP_PHY_INT_) | |
515 | usbnet_defer_kevent(dev, EVENT_LINK_RESET); | |
516 | else | |
60b86755 JP |
517 | netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n", |
518 | intdata); | |
2f7ca802 SG |
519 | } |
520 | ||
f7b29271 | 521 | /* Enable or disable Tx & Rx checksum offload engines */ |
c8f44aff MM |
522 | static int smsc95xx_set_features(struct net_device *netdev, |
523 | netdev_features_t features) | |
2f7ca802 | 524 | { |
78e47fe4 | 525 | struct usbnet *dev = netdev_priv(netdev); |
2f7ca802 | 526 | u32 read_buf; |
78e47fe4 MM |
527 | int ret; |
528 | ||
529 | ret = smsc95xx_read_reg(dev, COE_CR, &read_buf); | |
769ea6d8 | 530 | check_warn_return(ret, "Failed to read COE_CR: %d\n", ret); |
2f7ca802 | 531 | |
78e47fe4 | 532 | if (features & NETIF_F_HW_CSUM) |
f7b29271 SG |
533 | read_buf |= Tx_COE_EN_; |
534 | else | |
535 | read_buf &= ~Tx_COE_EN_; | |
536 | ||
78e47fe4 | 537 | if (features & NETIF_F_RXCSUM) |
2f7ca802 SG |
538 | read_buf |= Rx_COE_EN_; |
539 | else | |
540 | read_buf &= ~Rx_COE_EN_; | |
541 | ||
542 | ret = smsc95xx_write_reg(dev, COE_CR, read_buf); | |
769ea6d8 | 543 | check_warn_return(ret, "Failed to write COE_CR: %d\n", ret); |
2f7ca802 | 544 | |
a475f603 | 545 | netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf); |
2f7ca802 SG |
546 | return 0; |
547 | } | |
548 | ||
549 | static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net) | |
550 | { | |
551 | return MAX_EEPROM_SIZE; | |
552 | } | |
553 | ||
554 | static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev, | |
555 | struct ethtool_eeprom *ee, u8 *data) | |
556 | { | |
557 | struct usbnet *dev = netdev_priv(netdev); | |
558 | ||
559 | ee->magic = LAN95XX_EEPROM_MAGIC; | |
560 | ||
561 | return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data); | |
562 | } | |
563 | ||
564 | static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev, | |
565 | struct ethtool_eeprom *ee, u8 *data) | |
566 | { | |
567 | struct usbnet *dev = netdev_priv(netdev); | |
568 | ||
569 | if (ee->magic != LAN95XX_EEPROM_MAGIC) { | |
60b86755 JP |
570 | netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n", |
571 | ee->magic); | |
2f7ca802 SG |
572 | return -EINVAL; |
573 | } | |
574 | ||
575 | return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data); | |
576 | } | |
577 | ||
9fa32e94 EV |
578 | static int smsc95xx_ethtool_getregslen(struct net_device *netdev) |
579 | { | |
580 | /* all smsc95xx registers */ | |
581 | return COE_CR - ID_REV + 1; | |
582 | } | |
583 | ||
584 | static void | |
585 | smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs, | |
586 | void *buf) | |
587 | { | |
588 | struct usbnet *dev = netdev_priv(netdev); | |
d348446b DC |
589 | unsigned int i, j; |
590 | int retval; | |
9fa32e94 EV |
591 | u32 *data = buf; |
592 | ||
593 | retval = smsc95xx_read_reg(dev, ID_REV, ®s->version); | |
594 | if (retval < 0) { | |
595 | netdev_warn(netdev, "REGS: cannot read ID_REV\n"); | |
596 | return; | |
597 | } | |
598 | ||
599 | for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) { | |
600 | retval = smsc95xx_read_reg(dev, i, &data[j]); | |
601 | if (retval < 0) { | |
602 | netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i); | |
603 | return; | |
604 | } | |
605 | } | |
606 | } | |
607 | ||
e0e474a8 SG |
608 | static void smsc95xx_ethtool_get_wol(struct net_device *net, |
609 | struct ethtool_wolinfo *wolinfo) | |
610 | { | |
611 | struct usbnet *dev = netdev_priv(net); | |
612 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
613 | ||
614 | wolinfo->supported = SUPPORTED_WAKE; | |
615 | wolinfo->wolopts = pdata->wolopts; | |
616 | } | |
617 | ||
618 | static int smsc95xx_ethtool_set_wol(struct net_device *net, | |
619 | struct ethtool_wolinfo *wolinfo) | |
620 | { | |
621 | struct usbnet *dev = netdev_priv(net); | |
622 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
623 | ||
624 | pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE; | |
625 | return 0; | |
626 | } | |
627 | ||
0fc0b732 | 628 | static const struct ethtool_ops smsc95xx_ethtool_ops = { |
2f7ca802 SG |
629 | .get_link = usbnet_get_link, |
630 | .nway_reset = usbnet_nway_reset, | |
631 | .get_drvinfo = usbnet_get_drvinfo, | |
632 | .get_msglevel = usbnet_get_msglevel, | |
633 | .set_msglevel = usbnet_set_msglevel, | |
634 | .get_settings = usbnet_get_settings, | |
635 | .set_settings = usbnet_set_settings, | |
636 | .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len, | |
637 | .get_eeprom = smsc95xx_ethtool_get_eeprom, | |
638 | .set_eeprom = smsc95xx_ethtool_set_eeprom, | |
9fa32e94 EV |
639 | .get_regs_len = smsc95xx_ethtool_getregslen, |
640 | .get_regs = smsc95xx_ethtool_getregs, | |
e0e474a8 SG |
641 | .get_wol = smsc95xx_ethtool_get_wol, |
642 | .set_wol = smsc95xx_ethtool_set_wol, | |
2f7ca802 SG |
643 | }; |
644 | ||
645 | static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
646 | { | |
647 | struct usbnet *dev = netdev_priv(netdev); | |
648 | ||
649 | if (!netif_running(netdev)) | |
650 | return -EINVAL; | |
651 | ||
652 | return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); | |
653 | } | |
654 | ||
655 | static void smsc95xx_init_mac_address(struct usbnet *dev) | |
656 | { | |
657 | /* try reading mac address from EEPROM */ | |
658 | if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, | |
659 | dev->net->dev_addr) == 0) { | |
660 | if (is_valid_ether_addr(dev->net->dev_addr)) { | |
661 | /* eeprom values are valid so use them */ | |
a475f603 | 662 | netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n"); |
2f7ca802 SG |
663 | return; |
664 | } | |
665 | } | |
666 | ||
667 | /* no eeprom, or eeprom values are invalid. generate random MAC */ | |
f2cedb63 | 668 | eth_hw_addr_random(dev->net); |
c7e12ead | 669 | netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n"); |
2f7ca802 SG |
670 | } |
671 | ||
672 | static int smsc95xx_set_mac_address(struct usbnet *dev) | |
673 | { | |
674 | u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 | | |
675 | dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24; | |
676 | u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8; | |
677 | int ret; | |
678 | ||
679 | ret = smsc95xx_write_reg(dev, ADDRL, addr_lo); | |
769ea6d8 | 680 | check_warn_return(ret, "Failed to write ADDRL: %d\n", ret); |
2f7ca802 SG |
681 | |
682 | ret = smsc95xx_write_reg(dev, ADDRH, addr_hi); | |
769ea6d8 | 683 | check_warn_return(ret, "Failed to write ADDRH: %d\n", ret); |
2f7ca802 SG |
684 | |
685 | return 0; | |
686 | } | |
687 | ||
688 | /* starts the TX path */ | |
769ea6d8 | 689 | static int smsc95xx_start_tx_path(struct usbnet *dev) |
2f7ca802 SG |
690 | { |
691 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
692 | unsigned long flags; | |
769ea6d8 | 693 | int ret; |
2f7ca802 SG |
694 | |
695 | /* Enable Tx at MAC */ | |
696 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); | |
697 | pdata->mac_cr |= MAC_CR_TXEN_; | |
698 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
699 | ||
769ea6d8 SG |
700 | ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); |
701 | check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret); | |
2f7ca802 SG |
702 | |
703 | /* Enable Tx at SCSRs */ | |
769ea6d8 SG |
704 | ret = smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_); |
705 | check_warn_return(ret, "Failed to write TX_CFG: %d\n", ret); | |
706 | ||
707 | return 0; | |
2f7ca802 SG |
708 | } |
709 | ||
710 | /* Starts the Receive path */ | |
769ea6d8 | 711 | static int smsc95xx_start_rx_path(struct usbnet *dev) |
2f7ca802 SG |
712 | { |
713 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
714 | unsigned long flags; | |
769ea6d8 | 715 | int ret; |
2f7ca802 SG |
716 | |
717 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); | |
718 | pdata->mac_cr |= MAC_CR_RXEN_; | |
719 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
720 | ||
769ea6d8 SG |
721 | ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); |
722 | check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret); | |
723 | ||
724 | return 0; | |
2f7ca802 SG |
725 | } |
726 | ||
727 | static int smsc95xx_phy_initialize(struct usbnet *dev) | |
728 | { | |
769ea6d8 | 729 | int bmcr, ret, timeout = 0; |
db443c44 | 730 | |
2f7ca802 SG |
731 | /* Initialize MII structure */ |
732 | dev->mii.dev = dev->net; | |
733 | dev->mii.mdio_read = smsc95xx_mdio_read; | |
734 | dev->mii.mdio_write = smsc95xx_mdio_write; | |
735 | dev->mii.phy_id_mask = 0x1f; | |
736 | dev->mii.reg_num_mask = 0x1f; | |
737 | dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID; | |
738 | ||
db443c44 | 739 | /* reset phy and wait for reset to complete */ |
2f7ca802 | 740 | smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
db443c44 SG |
741 | |
742 | do { | |
743 | msleep(10); | |
744 | bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR); | |
745 | timeout++; | |
d9460920 | 746 | } while ((bmcr & BMCR_RESET) && (timeout < 100)); |
db443c44 SG |
747 | |
748 | if (timeout >= 100) { | |
749 | netdev_warn(dev->net, "timeout on PHY Reset"); | |
750 | return -EIO; | |
751 | } | |
752 | ||
2f7ca802 SG |
753 | smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, |
754 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | | |
755 | ADVERTISE_PAUSE_ASYM); | |
756 | ||
757 | /* read to clear */ | |
769ea6d8 SG |
758 | ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC); |
759 | check_warn_return(ret, "Failed to read PHY_INT_SRC during init"); | |
2f7ca802 SG |
760 | |
761 | smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK, | |
762 | PHY_INT_MASK_DEFAULT_); | |
763 | mii_nway_restart(&dev->mii); | |
764 | ||
a475f603 | 765 | netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n"); |
2f7ca802 SG |
766 | return 0; |
767 | } | |
768 | ||
769 | static int smsc95xx_reset(struct usbnet *dev) | |
770 | { | |
771 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
772 | u32 read_buf, write_buf, burst_cap; | |
773 | int ret = 0, timeout; | |
2f7ca802 | 774 | |
a475f603 | 775 | netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n"); |
2f7ca802 | 776 | |
4436761b | 777 | ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_); |
769ea6d8 | 778 | check_warn_return(ret, "Failed to write HW_CFG_LRST_ bit in HW_CFG\n"); |
2f7ca802 SG |
779 | |
780 | timeout = 0; | |
781 | do { | |
cf2acec2 | 782 | msleep(10); |
2f7ca802 | 783 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); |
769ea6d8 | 784 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
2f7ca802 SG |
785 | timeout++; |
786 | } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); | |
787 | ||
788 | if (timeout >= 100) { | |
60b86755 | 789 | netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n"); |
2f7ca802 SG |
790 | return ret; |
791 | } | |
792 | ||
4436761b | 793 | ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_); |
769ea6d8 | 794 | check_warn_return(ret, "Failed to write PM_CTRL: %d\n", ret); |
2f7ca802 SG |
795 | |
796 | timeout = 0; | |
797 | do { | |
cf2acec2 | 798 | msleep(10); |
2f7ca802 | 799 | ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); |
769ea6d8 | 800 | check_warn_return(ret, "Failed to read PM_CTRL: %d\n", ret); |
2f7ca802 SG |
801 | timeout++; |
802 | } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); | |
803 | ||
804 | if (timeout >= 100) { | |
60b86755 | 805 | netdev_warn(dev->net, "timeout waiting for PHY Reset\n"); |
2f7ca802 SG |
806 | return ret; |
807 | } | |
808 | ||
2f7ca802 SG |
809 | ret = smsc95xx_set_mac_address(dev); |
810 | if (ret < 0) | |
811 | return ret; | |
812 | ||
a475f603 JP |
813 | netif_dbg(dev, ifup, dev->net, |
814 | "MAC Address: %pM\n", dev->net->dev_addr); | |
2f7ca802 SG |
815 | |
816 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 | 817 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
2f7ca802 | 818 | |
a475f603 JP |
819 | netif_dbg(dev, ifup, dev->net, |
820 | "Read Value from HW_CFG : 0x%08x\n", read_buf); | |
2f7ca802 SG |
821 | |
822 | read_buf |= HW_CFG_BIR_; | |
823 | ||
824 | ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); | |
769ea6d8 | 825 | check_warn_return(ret, "Failed to write HW_CFG_BIR_ bit in HW_CFG\n"); |
2f7ca802 SG |
826 | |
827 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 | 828 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
a475f603 JP |
829 | netif_dbg(dev, ifup, dev->net, |
830 | "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n", | |
831 | read_buf); | |
2f7ca802 SG |
832 | |
833 | if (!turbo_mode) { | |
834 | burst_cap = 0; | |
835 | dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE; | |
836 | } else if (dev->udev->speed == USB_SPEED_HIGH) { | |
837 | burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; | |
838 | dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; | |
839 | } else { | |
840 | burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; | |
841 | dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; | |
842 | } | |
843 | ||
a475f603 JP |
844 | netif_dbg(dev, ifup, dev->net, |
845 | "rx_urb_size=%ld\n", (ulong)dev->rx_urb_size); | |
2f7ca802 SG |
846 | |
847 | ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); | |
769ea6d8 | 848 | check_warn_return(ret, "Failed to write BURST_CAP: %d\n", ret); |
2f7ca802 SG |
849 | |
850 | ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf); | |
769ea6d8 SG |
851 | check_warn_return(ret, "Failed to read BURST_CAP: %d\n", ret); |
852 | ||
a475f603 JP |
853 | netif_dbg(dev, ifup, dev->net, |
854 | "Read Value from BURST_CAP after writing: 0x%08x\n", | |
855 | read_buf); | |
2f7ca802 | 856 | |
4436761b | 857 | ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); |
769ea6d8 | 858 | check_warn_return(ret, "Failed to write BULK_IN_DLY: %d\n", ret); |
2f7ca802 SG |
859 | |
860 | ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf); | |
769ea6d8 SG |
861 | check_warn_return(ret, "Failed to read BULK_IN_DLY: %d\n", ret); |
862 | ||
a475f603 JP |
863 | netif_dbg(dev, ifup, dev->net, |
864 | "Read Value from BULK_IN_DLY after writing: 0x%08x\n", | |
865 | read_buf); | |
2f7ca802 SG |
866 | |
867 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 SG |
868 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
869 | ||
a475f603 JP |
870 | netif_dbg(dev, ifup, dev->net, |
871 | "Read Value from HW_CFG: 0x%08x\n", read_buf); | |
2f7ca802 SG |
872 | |
873 | if (turbo_mode) | |
874 | read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); | |
875 | ||
876 | read_buf &= ~HW_CFG_RXDOFF_; | |
877 | ||
878 | /* set Rx data offset=2, Make IP header aligns on word boundary. */ | |
879 | read_buf |= NET_IP_ALIGN << 9; | |
880 | ||
881 | ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); | |
769ea6d8 | 882 | check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret); |
2f7ca802 SG |
883 | |
884 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 SG |
885 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
886 | ||
a475f603 JP |
887 | netif_dbg(dev, ifup, dev->net, |
888 | "Read Value from HW_CFG after writing: 0x%08x\n", read_buf); | |
2f7ca802 | 889 | |
4436761b | 890 | ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); |
769ea6d8 | 891 | check_warn_return(ret, "Failed to write INT_STS: %d\n", ret); |
2f7ca802 SG |
892 | |
893 | ret = smsc95xx_read_reg(dev, ID_REV, &read_buf); | |
769ea6d8 | 894 | check_warn_return(ret, "Failed to read ID_REV: %d\n", ret); |
a475f603 | 895 | netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf); |
2f7ca802 | 896 | |
f293501c SG |
897 | /* Configure GPIO pins as LED outputs */ |
898 | write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED | | |
899 | LED_GPIO_CFG_FDX_LED; | |
900 | ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf); | |
769ea6d8 | 901 | check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d\n", ret); |
f293501c | 902 | |
2f7ca802 | 903 | /* Init Tx */ |
4436761b | 904 | ret = smsc95xx_write_reg(dev, FLOW, 0); |
769ea6d8 | 905 | check_warn_return(ret, "Failed to write FLOW: %d\n", ret); |
2f7ca802 | 906 | |
4436761b | 907 | ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT); |
769ea6d8 | 908 | check_warn_return(ret, "Failed to write AFC_CFG: %d\n", ret); |
2f7ca802 SG |
909 | |
910 | /* Don't need mac_cr_lock during initialisation */ | |
911 | ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr); | |
769ea6d8 | 912 | check_warn_return(ret, "Failed to read MAC_CR: %d\n", ret); |
2f7ca802 SG |
913 | |
914 | /* Init Rx */ | |
915 | /* Set Vlan */ | |
4436761b | 916 | ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q); |
769ea6d8 | 917 | check_warn_return(ret, "Failed to write VLAN1: %d\n", ret); |
2f7ca802 | 918 | |
f7b29271 | 919 | /* Enable or disable checksum offload engines */ |
769ea6d8 SG |
920 | ret = smsc95xx_set_features(dev->net, dev->net->features); |
921 | check_warn_return(ret, "Failed to set checksum offload features"); | |
2f7ca802 SG |
922 | |
923 | smsc95xx_set_multicast(dev->net); | |
924 | ||
769ea6d8 SG |
925 | ret = smsc95xx_phy_initialize(dev); |
926 | check_warn_return(ret, "Failed to init PHY"); | |
2f7ca802 SG |
927 | |
928 | ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf); | |
769ea6d8 | 929 | check_warn_return(ret, "Failed to read INT_EP_CTL: %d\n", ret); |
2f7ca802 SG |
930 | |
931 | /* enable PHY interrupts */ | |
932 | read_buf |= INT_EP_CTL_PHY_INT_; | |
933 | ||
934 | ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf); | |
769ea6d8 | 935 | check_warn_return(ret, "Failed to write INT_EP_CTL: %d\n", ret); |
2f7ca802 | 936 | |
769ea6d8 SG |
937 | ret = smsc95xx_start_tx_path(dev); |
938 | check_warn_return(ret, "Failed to start TX path"); | |
939 | ||
940 | ret = smsc95xx_start_rx_path(dev); | |
941 | check_warn_return(ret, "Failed to start RX path"); | |
2f7ca802 | 942 | |
a475f603 | 943 | netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n"); |
2f7ca802 SG |
944 | return 0; |
945 | } | |
946 | ||
63e77b39 SH |
947 | static const struct net_device_ops smsc95xx_netdev_ops = { |
948 | .ndo_open = usbnet_open, | |
949 | .ndo_stop = usbnet_stop, | |
950 | .ndo_start_xmit = usbnet_start_xmit, | |
951 | .ndo_tx_timeout = usbnet_tx_timeout, | |
952 | .ndo_change_mtu = usbnet_change_mtu, | |
953 | .ndo_set_mac_address = eth_mac_addr, | |
954 | .ndo_validate_addr = eth_validate_addr, | |
955 | .ndo_do_ioctl = smsc95xx_ioctl, | |
afc4b13d | 956 | .ndo_set_rx_mode = smsc95xx_set_multicast, |
78e47fe4 | 957 | .ndo_set_features = smsc95xx_set_features, |
63e77b39 SH |
958 | }; |
959 | ||
2f7ca802 SG |
960 | static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf) |
961 | { | |
962 | struct smsc95xx_priv *pdata = NULL; | |
bbd9f9ee | 963 | u32 val; |
2f7ca802 SG |
964 | int ret; |
965 | ||
966 | printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n"); | |
967 | ||
968 | ret = usbnet_get_endpoints(dev, intf); | |
769ea6d8 | 969 | check_warn_return(ret, "usbnet_get_endpoints failed: %d\n", ret); |
2f7ca802 SG |
970 | |
971 | dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv), | |
972 | GFP_KERNEL); | |
973 | ||
974 | pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
975 | if (!pdata) { | |
60b86755 | 976 | netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n"); |
2f7ca802 SG |
977 | return -ENOMEM; |
978 | } | |
979 | ||
980 | spin_lock_init(&pdata->mac_cr_lock); | |
981 | ||
78e47fe4 MM |
982 | if (DEFAULT_TX_CSUM_ENABLE) |
983 | dev->net->features |= NETIF_F_HW_CSUM; | |
984 | if (DEFAULT_RX_CSUM_ENABLE) | |
985 | dev->net->features |= NETIF_F_RXCSUM; | |
986 | ||
987 | dev->net->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM; | |
2f7ca802 | 988 | |
f4e8ab7c BB |
989 | smsc95xx_init_mac_address(dev); |
990 | ||
2f7ca802 SG |
991 | /* Init all registers */ |
992 | ret = smsc95xx_reset(dev); | |
993 | ||
bbd9f9ee SG |
994 | /* detect device revision as different features may be available */ |
995 | ret = smsc95xx_read_reg(dev, ID_REV, &val); | |
996 | check_warn_return(ret, "Failed to read ID_REV: %d\n", ret); | |
997 | val >>= 16; | |
998 | if ((val == ID_REV_CHIP_ID_9500A_) || (val == ID_REV_CHIP_ID_9512_)) | |
999 | pdata->wuff_filter_count = LAN9500A_WUFF_NUM; | |
1000 | else | |
1001 | pdata->wuff_filter_count = LAN9500_WUFF_NUM; | |
1002 | ||
63e77b39 | 1003 | dev->net->netdev_ops = &smsc95xx_netdev_ops; |
2f7ca802 | 1004 | dev->net->ethtool_ops = &smsc95xx_ethtool_ops; |
2f7ca802 | 1005 | dev->net->flags |= IFF_MULTICAST; |
78e47fe4 | 1006 | dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM; |
9bbf5660 | 1007 | dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len; |
2f7ca802 SG |
1008 | return 0; |
1009 | } | |
1010 | ||
1011 | static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf) | |
1012 | { | |
1013 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
1014 | if (pdata) { | |
a475f603 | 1015 | netif_dbg(dev, ifdown, dev->net, "free pdata\n"); |
2f7ca802 SG |
1016 | kfree(pdata); |
1017 | pdata = NULL; | |
1018 | dev->data[0] = 0; | |
1019 | } | |
1020 | } | |
1021 | ||
bbd9f9ee SG |
1022 | static u16 smsc_crc(const u8 *buffer, size_t len, int filter) |
1023 | { | |
1024 | return bitrev16(crc16(0xFFFF, buffer, len)) << ((filter % 2) * 16); | |
1025 | } | |
1026 | ||
b5a04475 SG |
1027 | static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message) |
1028 | { | |
1029 | struct usbnet *dev = usb_get_intfdata(intf); | |
e0e474a8 | 1030 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); |
b5a04475 SG |
1031 | int ret; |
1032 | u32 val; | |
1033 | ||
b5a04475 SG |
1034 | ret = usbnet_suspend(intf, message); |
1035 | check_warn_return(ret, "usbnet_suspend error"); | |
1036 | ||
e0e474a8 SG |
1037 | /* if no wol options set, enter lowest power SUSPEND2 mode */ |
1038 | if (!(pdata->wolopts & SUPPORTED_WAKE)) { | |
1039 | netdev_info(dev->net, "entering SUSPEND2 mode"); | |
1040 | ||
1041 | /* disable energy detect (link up) & wake up events */ | |
1042 | ret = smsc95xx_read_reg(dev, WUCSR, &val); | |
1043 | check_warn_return(ret, "Error reading WUCSR"); | |
1044 | ||
1045 | val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_); | |
1046 | ||
1047 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1048 | check_warn_return(ret, "Error writing WUCSR"); | |
1049 | ||
1050 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1051 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1052 | ||
1053 | val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_); | |
1054 | ||
1055 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1056 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1057 | ||
1058 | /* enter suspend2 mode */ | |
1059 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1060 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1061 | ||
1062 | val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_); | |
1063 | val |= PM_CTL_SUS_MODE_2; | |
1064 | ||
1065 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1066 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1067 | ||
1068 | return 0; | |
1069 | } | |
1070 | ||
bbd9f9ee SG |
1071 | if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) { |
1072 | u32 *filter_mask = kzalloc(32, GFP_KERNEL); | |
1073 | u32 *command = kzalloc(2, GFP_KERNEL); | |
1074 | u32 *offset = kzalloc(2, GFP_KERNEL); | |
1075 | u32 *crc = kzalloc(4, GFP_KERNEL); | |
1076 | int i, filter = 0; | |
1077 | ||
1078 | if (pdata->wolopts & WAKE_BCAST) { | |
1079 | const u8 bcast[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; | |
1080 | netdev_info(dev->net, "enabling broadcast detection"); | |
1081 | filter_mask[filter * 4] = 0x003F; | |
1082 | filter_mask[filter * 4 + 1] = 0x00; | |
1083 | filter_mask[filter * 4 + 2] = 0x00; | |
1084 | filter_mask[filter * 4 + 3] = 0x00; | |
1085 | command[filter/4] |= 0x05UL << ((filter % 4) * 8); | |
1086 | offset[filter/4] |= 0x00 << ((filter % 4) * 8); | |
1087 | crc[filter/2] |= smsc_crc(bcast, 6, filter); | |
1088 | filter++; | |
1089 | } | |
1090 | ||
1091 | if (pdata->wolopts & WAKE_MCAST) { | |
1092 | const u8 mcast[] = {0x01, 0x00, 0x5E}; | |
1093 | netdev_info(dev->net, "enabling multicast detection"); | |
1094 | filter_mask[filter * 4] = 0x0007; | |
1095 | filter_mask[filter * 4 + 1] = 0x00; | |
1096 | filter_mask[filter * 4 + 2] = 0x00; | |
1097 | filter_mask[filter * 4 + 3] = 0x00; | |
1098 | command[filter/4] |= 0x09UL << ((filter % 4) * 8); | |
1099 | offset[filter/4] |= 0x00 << ((filter % 4) * 8); | |
1100 | crc[filter/2] |= smsc_crc(mcast, 3, filter); | |
1101 | filter++; | |
1102 | } | |
1103 | ||
1104 | if (pdata->wolopts & WAKE_ARP) { | |
1105 | const u8 arp[] = {0x08, 0x06}; | |
1106 | netdev_info(dev->net, "enabling ARP detection"); | |
1107 | filter_mask[filter * 4] = 0x0003; | |
1108 | filter_mask[filter * 4 + 1] = 0x00; | |
1109 | filter_mask[filter * 4 + 2] = 0x00; | |
1110 | filter_mask[filter * 4 + 3] = 0x00; | |
1111 | command[filter/4] |= 0x05UL << ((filter % 4) * 8); | |
1112 | offset[filter/4] |= 0x0C << ((filter % 4) * 8); | |
1113 | crc[filter/2] |= smsc_crc(arp, 2, filter); | |
1114 | filter++; | |
1115 | } | |
1116 | ||
1117 | if (pdata->wolopts & WAKE_UCAST) { | |
1118 | netdev_info(dev->net, "enabling unicast detection"); | |
1119 | filter_mask[filter * 4] = 0x003F; | |
1120 | filter_mask[filter * 4 + 1] = 0x00; | |
1121 | filter_mask[filter * 4 + 2] = 0x00; | |
1122 | filter_mask[filter * 4 + 3] = 0x00; | |
1123 | command[filter/4] |= 0x01UL << ((filter % 4) * 8); | |
1124 | offset[filter/4] |= 0x00 << ((filter % 4) * 8); | |
1125 | crc[filter/2] |= smsc_crc(dev->net->dev_addr, ETH_ALEN, filter); | |
1126 | filter++; | |
1127 | } | |
1128 | ||
1129 | for (i = 0; i < (pdata->wuff_filter_count * 4); i++) { | |
1130 | ret = smsc95xx_write_reg(dev, WUFF, filter_mask[i]); | |
1131 | check_warn_return(ret, "Error writing WUFF"); | |
1132 | } | |
1133 | ||
1134 | for (i = 0; i < (pdata->wuff_filter_count / 4); i++) { | |
1135 | ret = smsc95xx_write_reg(dev, WUFF, command[i]); | |
1136 | check_warn_return(ret, "Error writing WUFF"); | |
1137 | } | |
1138 | ||
1139 | for (i = 0; i < (pdata->wuff_filter_count / 4); i++) { | |
1140 | ret = smsc95xx_write_reg(dev, WUFF, offset[i]); | |
1141 | check_warn_return(ret, "Error writing WUFF"); | |
1142 | } | |
1143 | ||
1144 | for (i = 0; i < (pdata->wuff_filter_count / 2); i++) { | |
1145 | ret = smsc95xx_write_reg(dev, WUFF, crc[i]); | |
1146 | check_warn_return(ret, "Error writing WUFF"); | |
1147 | } | |
1148 | ||
1149 | /* clear any pending pattern match packet status */ | |
1150 | ret = smsc95xx_read_reg(dev, WUCSR, &val); | |
1151 | check_warn_return(ret, "Error reading WUCSR"); | |
1152 | ||
1153 | val |= WUCSR_WUFR_; | |
1154 | ||
1155 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1156 | check_warn_return(ret, "Error writing WUCSR"); | |
1157 | } | |
1158 | ||
e0e474a8 SG |
1159 | if (pdata->wolopts & WAKE_MAGIC) { |
1160 | /* clear any pending magic packet status */ | |
1161 | ret = smsc95xx_read_reg(dev, WUCSR, &val); | |
1162 | check_warn_return(ret, "Error reading WUCSR"); | |
1163 | ||
1164 | val |= WUCSR_MPR_; | |
1165 | ||
1166 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1167 | check_warn_return(ret, "Error writing WUCSR"); | |
1168 | } | |
1169 | ||
bbd9f9ee | 1170 | /* enable/disable wakeup sources */ |
e0e474a8 SG |
1171 | ret = smsc95xx_read_reg(dev, WUCSR, &val); |
1172 | check_warn_return(ret, "Error reading WUCSR"); | |
1173 | ||
bbd9f9ee SG |
1174 | if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) { |
1175 | netdev_info(dev->net, "enabling pattern match wakeup"); | |
1176 | val |= WUCSR_WAKE_EN_; | |
1177 | } else { | |
1178 | netdev_info(dev->net, "disabling pattern match wakeup"); | |
1179 | val &= ~WUCSR_WAKE_EN_; | |
1180 | } | |
1181 | ||
e0e474a8 SG |
1182 | if (pdata->wolopts & WAKE_MAGIC) { |
1183 | netdev_info(dev->net, "enabling magic packet wakeup"); | |
1184 | val |= WUCSR_MPEN_; | |
1185 | } else { | |
1186 | netdev_info(dev->net, "disabling magic packet wakeup"); | |
1187 | val &= ~WUCSR_MPEN_; | |
1188 | } | |
1189 | ||
1190 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1191 | check_warn_return(ret, "Error writing WUCSR"); | |
1192 | ||
1193 | /* enable wol wakeup source */ | |
1194 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1195 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1196 | ||
1197 | val |= PM_CTL_WOL_EN_; | |
1198 | ||
1199 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1200 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1201 | ||
bbd9f9ee | 1202 | /* enable receiver to enable frame reception */ |
e0e474a8 SG |
1203 | smsc95xx_start_rx_path(dev); |
1204 | ||
1205 | /* some wol options are enabled, so enter SUSPEND0 */ | |
1206 | netdev_info(dev->net, "entering SUSPEND0 mode"); | |
b5a04475 SG |
1207 | |
1208 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1209 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1210 | ||
e0e474a8 SG |
1211 | val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_)); |
1212 | val |= PM_CTL_SUS_MODE_0; | |
b5a04475 SG |
1213 | |
1214 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1215 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1216 | ||
e0e474a8 SG |
1217 | /* clear wol status */ |
1218 | val &= ~PM_CTL_WUPS_; | |
1219 | val |= PM_CTL_WUPS_WOL_; | |
1220 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1221 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1222 | ||
1223 | /* read back PM_CTRL */ | |
1224 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1225 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1226 | ||
1227 | smsc95xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP); | |
1228 | ||
1229 | return 0; | |
1230 | } | |
1231 | ||
1232 | static int smsc95xx_resume(struct usb_interface *intf) | |
1233 | { | |
1234 | struct usbnet *dev = usb_get_intfdata(intf); | |
1235 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
1236 | int ret; | |
1237 | u32 val; | |
1238 | ||
1239 | BUG_ON(!dev); | |
1240 | ||
bbd9f9ee | 1241 | if (pdata->wolopts) { |
e0e474a8 SG |
1242 | smsc95xx_clear_feature(dev, USB_DEVICE_REMOTE_WAKEUP); |
1243 | ||
bbd9f9ee | 1244 | /* clear wake-up sources */ |
e0e474a8 SG |
1245 | ret = smsc95xx_read_reg(dev, WUCSR, &val); |
1246 | check_warn_return(ret, "Error reading WUCSR"); | |
1247 | ||
bbd9f9ee | 1248 | val &= ~(WUCSR_WAKE_EN_ | WUCSR_MPEN_); |
e0e474a8 SG |
1249 | |
1250 | ret = smsc95xx_write_reg(dev, WUCSR, val); | |
1251 | check_warn_return(ret, "Error writing WUCSR"); | |
1252 | ||
1253 | /* clear wake-up status */ | |
1254 | ret = smsc95xx_read_reg(dev, PM_CTRL, &val); | |
1255 | check_warn_return(ret, "Error reading PM_CTRL"); | |
1256 | ||
1257 | val &= ~PM_CTL_WOL_EN_; | |
1258 | val |= PM_CTL_WUPS_; | |
1259 | ||
1260 | ret = smsc95xx_write_reg(dev, PM_CTRL, val); | |
1261 | check_warn_return(ret, "Error writing PM_CTRL"); | |
1262 | } | |
1263 | ||
1264 | return usbnet_resume(intf); | |
1265 | check_warn_return(ret, "usbnet_resume error"); | |
1266 | ||
b5a04475 SG |
1267 | return 0; |
1268 | } | |
1269 | ||
2f7ca802 SG |
1270 | static void smsc95xx_rx_csum_offload(struct sk_buff *skb) |
1271 | { | |
1272 | skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2); | |
1273 | skb->ip_summed = CHECKSUM_COMPLETE; | |
1274 | skb_trim(skb, skb->len - 2); | |
1275 | } | |
1276 | ||
1277 | static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) | |
1278 | { | |
2f7ca802 SG |
1279 | while (skb->len > 0) { |
1280 | u32 header, align_count; | |
1281 | struct sk_buff *ax_skb; | |
1282 | unsigned char *packet; | |
1283 | u16 size; | |
1284 | ||
1285 | memcpy(&header, skb->data, sizeof(header)); | |
1286 | le32_to_cpus(&header); | |
1287 | skb_pull(skb, 4 + NET_IP_ALIGN); | |
1288 | packet = skb->data; | |
1289 | ||
1290 | /* get the packet length */ | |
1291 | size = (u16)((header & RX_STS_FL_) >> 16); | |
1292 | align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4; | |
1293 | ||
1294 | if (unlikely(header & RX_STS_ES_)) { | |
a475f603 JP |
1295 | netif_dbg(dev, rx_err, dev->net, |
1296 | "Error header=0x%08x\n", header); | |
80667ac1 HX |
1297 | dev->net->stats.rx_errors++; |
1298 | dev->net->stats.rx_dropped++; | |
2f7ca802 SG |
1299 | |
1300 | if (header & RX_STS_CRC_) { | |
80667ac1 | 1301 | dev->net->stats.rx_crc_errors++; |
2f7ca802 SG |
1302 | } else { |
1303 | if (header & (RX_STS_TL_ | RX_STS_RF_)) | |
80667ac1 | 1304 | dev->net->stats.rx_frame_errors++; |
2f7ca802 SG |
1305 | |
1306 | if ((header & RX_STS_LE_) && | |
1307 | (!(header & RX_STS_FT_))) | |
80667ac1 | 1308 | dev->net->stats.rx_length_errors++; |
2f7ca802 SG |
1309 | } |
1310 | } else { | |
1311 | /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */ | |
1312 | if (unlikely(size > (ETH_FRAME_LEN + 12))) { | |
a475f603 JP |
1313 | netif_dbg(dev, rx_err, dev->net, |
1314 | "size err header=0x%08x\n", header); | |
2f7ca802 SG |
1315 | return 0; |
1316 | } | |
1317 | ||
1318 | /* last frame in this batch */ | |
1319 | if (skb->len == size) { | |
78e47fe4 | 1320 | if (dev->net->features & NETIF_F_RXCSUM) |
2f7ca802 | 1321 | smsc95xx_rx_csum_offload(skb); |
df18acca | 1322 | skb_trim(skb, skb->len - 4); /* remove fcs */ |
2f7ca802 SG |
1323 | skb->truesize = size + sizeof(struct sk_buff); |
1324 | ||
1325 | return 1; | |
1326 | } | |
1327 | ||
1328 | ax_skb = skb_clone(skb, GFP_ATOMIC); | |
1329 | if (unlikely(!ax_skb)) { | |
60b86755 | 1330 | netdev_warn(dev->net, "Error allocating skb\n"); |
2f7ca802 SG |
1331 | return 0; |
1332 | } | |
1333 | ||
1334 | ax_skb->len = size; | |
1335 | ax_skb->data = packet; | |
1336 | skb_set_tail_pointer(ax_skb, size); | |
1337 | ||
78e47fe4 | 1338 | if (dev->net->features & NETIF_F_RXCSUM) |
2f7ca802 | 1339 | smsc95xx_rx_csum_offload(ax_skb); |
df18acca | 1340 | skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */ |
2f7ca802 SG |
1341 | ax_skb->truesize = size + sizeof(struct sk_buff); |
1342 | ||
1343 | usbnet_skb_return(dev, ax_skb); | |
1344 | } | |
1345 | ||
1346 | skb_pull(skb, size); | |
1347 | ||
1348 | /* padding bytes before the next frame starts */ | |
1349 | if (skb->len) | |
1350 | skb_pull(skb, align_count); | |
1351 | } | |
1352 | ||
1353 | if (unlikely(skb->len < 0)) { | |
60b86755 | 1354 | netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len); |
2f7ca802 SG |
1355 | return 0; |
1356 | } | |
1357 | ||
1358 | return 1; | |
1359 | } | |
1360 | ||
f7b29271 SG |
1361 | static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb) |
1362 | { | |
55508d60 MM |
1363 | u16 low_16 = (u16)skb_checksum_start_offset(skb); |
1364 | u16 high_16 = low_16 + skb->csum_offset; | |
f7b29271 SG |
1365 | return (high_16 << 16) | low_16; |
1366 | } | |
1367 | ||
2f7ca802 SG |
1368 | static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev, |
1369 | struct sk_buff *skb, gfp_t flags) | |
1370 | { | |
78e47fe4 | 1371 | bool csum = skb->ip_summed == CHECKSUM_PARTIAL; |
f7b29271 | 1372 | int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD; |
2f7ca802 SG |
1373 | u32 tx_cmd_a, tx_cmd_b; |
1374 | ||
f7b29271 SG |
1375 | /* We do not advertise SG, so skbs should be already linearized */ |
1376 | BUG_ON(skb_shinfo(skb)->nr_frags); | |
1377 | ||
1378 | if (skb_headroom(skb) < overhead) { | |
2f7ca802 | 1379 | struct sk_buff *skb2 = skb_copy_expand(skb, |
f7b29271 | 1380 | overhead, 0, flags); |
2f7ca802 SG |
1381 | dev_kfree_skb_any(skb); |
1382 | skb = skb2; | |
1383 | if (!skb) | |
1384 | return NULL; | |
1385 | } | |
1386 | ||
f7b29271 | 1387 | if (csum) { |
11bc3088 SG |
1388 | if (skb->len <= 45) { |
1389 | /* workaround - hardware tx checksum does not work | |
1390 | * properly with extremely small packets */ | |
55508d60 | 1391 | long csstart = skb_checksum_start_offset(skb); |
11bc3088 SG |
1392 | __wsum calc = csum_partial(skb->data + csstart, |
1393 | skb->len - csstart, 0); | |
1394 | *((__sum16 *)(skb->data + csstart | |
1395 | + skb->csum_offset)) = csum_fold(calc); | |
1396 | ||
1397 | csum = false; | |
1398 | } else { | |
1399 | u32 csum_preamble = smsc95xx_calc_csum_preamble(skb); | |
1400 | skb_push(skb, 4); | |
1401 | memcpy(skb->data, &csum_preamble, 4); | |
1402 | } | |
f7b29271 SG |
1403 | } |
1404 | ||
2f7ca802 SG |
1405 | skb_push(skb, 4); |
1406 | tx_cmd_b = (u32)(skb->len - 4); | |
f7b29271 SG |
1407 | if (csum) |
1408 | tx_cmd_b |= TX_CMD_B_CSUM_ENABLE; | |
2f7ca802 SG |
1409 | cpu_to_le32s(&tx_cmd_b); |
1410 | memcpy(skb->data, &tx_cmd_b, 4); | |
1411 | ||
1412 | skb_push(skb, 4); | |
1413 | tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ | | |
1414 | TX_CMD_A_LAST_SEG_; | |
1415 | cpu_to_le32s(&tx_cmd_a); | |
1416 | memcpy(skb->data, &tx_cmd_a, 4); | |
1417 | ||
1418 | return skb; | |
1419 | } | |
1420 | ||
1421 | static const struct driver_info smsc95xx_info = { | |
1422 | .description = "smsc95xx USB 2.0 Ethernet", | |
1423 | .bind = smsc95xx_bind, | |
1424 | .unbind = smsc95xx_unbind, | |
1425 | .link_reset = smsc95xx_link_reset, | |
1426 | .reset = smsc95xx_reset, | |
1427 | .rx_fixup = smsc95xx_rx_fixup, | |
1428 | .tx_fixup = smsc95xx_tx_fixup, | |
1429 | .status = smsc95xx_status, | |
07d69d42 | 1430 | .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR, |
2f7ca802 SG |
1431 | }; |
1432 | ||
1433 | static const struct usb_device_id products[] = { | |
1434 | { | |
1435 | /* SMSC9500 USB Ethernet Device */ | |
1436 | USB_DEVICE(0x0424, 0x9500), | |
1437 | .driver_info = (unsigned long) &smsc95xx_info, | |
1438 | }, | |
6f41d12b SG |
1439 | { |
1440 | /* SMSC9505 USB Ethernet Device */ | |
1441 | USB_DEVICE(0x0424, 0x9505), | |
1442 | .driver_info = (unsigned long) &smsc95xx_info, | |
1443 | }, | |
1444 | { | |
1445 | /* SMSC9500A USB Ethernet Device */ | |
1446 | USB_DEVICE(0x0424, 0x9E00), | |
1447 | .driver_info = (unsigned long) &smsc95xx_info, | |
1448 | }, | |
1449 | { | |
1450 | /* SMSC9505A USB Ethernet Device */ | |
1451 | USB_DEVICE(0x0424, 0x9E01), | |
1452 | .driver_info = (unsigned long) &smsc95xx_info, | |
1453 | }, | |
726474b8 SG |
1454 | { |
1455 | /* SMSC9512/9514 USB Hub & Ethernet Device */ | |
1456 | USB_DEVICE(0x0424, 0xec00), | |
1457 | .driver_info = (unsigned long) &smsc95xx_info, | |
1458 | }, | |
6f41d12b SG |
1459 | { |
1460 | /* SMSC9500 USB Ethernet Device (SAL10) */ | |
1461 | USB_DEVICE(0x0424, 0x9900), | |
1462 | .driver_info = (unsigned long) &smsc95xx_info, | |
1463 | }, | |
1464 | { | |
1465 | /* SMSC9505 USB Ethernet Device (SAL10) */ | |
1466 | USB_DEVICE(0x0424, 0x9901), | |
1467 | .driver_info = (unsigned long) &smsc95xx_info, | |
1468 | }, | |
1469 | { | |
1470 | /* SMSC9500A USB Ethernet Device (SAL10) */ | |
1471 | USB_DEVICE(0x0424, 0x9902), | |
1472 | .driver_info = (unsigned long) &smsc95xx_info, | |
1473 | }, | |
1474 | { | |
1475 | /* SMSC9505A USB Ethernet Device (SAL10) */ | |
1476 | USB_DEVICE(0x0424, 0x9903), | |
1477 | .driver_info = (unsigned long) &smsc95xx_info, | |
1478 | }, | |
1479 | { | |
1480 | /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */ | |
1481 | USB_DEVICE(0x0424, 0x9904), | |
1482 | .driver_info = (unsigned long) &smsc95xx_info, | |
1483 | }, | |
1484 | { | |
1485 | /* SMSC9500A USB Ethernet Device (HAL) */ | |
1486 | USB_DEVICE(0x0424, 0x9905), | |
1487 | .driver_info = (unsigned long) &smsc95xx_info, | |
1488 | }, | |
1489 | { | |
1490 | /* SMSC9505A USB Ethernet Device (HAL) */ | |
1491 | USB_DEVICE(0x0424, 0x9906), | |
1492 | .driver_info = (unsigned long) &smsc95xx_info, | |
1493 | }, | |
1494 | { | |
1495 | /* SMSC9500 USB Ethernet Device (Alternate ID) */ | |
1496 | USB_DEVICE(0x0424, 0x9907), | |
1497 | .driver_info = (unsigned long) &smsc95xx_info, | |
1498 | }, | |
1499 | { | |
1500 | /* SMSC9500A USB Ethernet Device (Alternate ID) */ | |
1501 | USB_DEVICE(0x0424, 0x9908), | |
1502 | .driver_info = (unsigned long) &smsc95xx_info, | |
1503 | }, | |
1504 | { | |
1505 | /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */ | |
1506 | USB_DEVICE(0x0424, 0x9909), | |
1507 | .driver_info = (unsigned long) &smsc95xx_info, | |
1508 | }, | |
88edaa41 SG |
1509 | { |
1510 | /* SMSC LAN9530 USB Ethernet Device */ | |
1511 | USB_DEVICE(0x0424, 0x9530), | |
1512 | .driver_info = (unsigned long) &smsc95xx_info, | |
1513 | }, | |
1514 | { | |
1515 | /* SMSC LAN9730 USB Ethernet Device */ | |
1516 | USB_DEVICE(0x0424, 0x9730), | |
1517 | .driver_info = (unsigned long) &smsc95xx_info, | |
1518 | }, | |
1519 | { | |
1520 | /* SMSC LAN89530 USB Ethernet Device */ | |
1521 | USB_DEVICE(0x0424, 0x9E08), | |
1522 | .driver_info = (unsigned long) &smsc95xx_info, | |
1523 | }, | |
2f7ca802 SG |
1524 | { }, /* END */ |
1525 | }; | |
1526 | MODULE_DEVICE_TABLE(usb, products); | |
1527 | ||
1528 | static struct usb_driver smsc95xx_driver = { | |
1529 | .name = "smsc95xx", | |
1530 | .id_table = products, | |
1531 | .probe = usbnet_probe, | |
b5a04475 | 1532 | .suspend = smsc95xx_suspend, |
e0e474a8 SG |
1533 | .resume = smsc95xx_resume, |
1534 | .reset_resume = smsc95xx_resume, | |
2f7ca802 | 1535 | .disconnect = usbnet_disconnect, |
e1f12eb6 | 1536 | .disable_hub_initiated_lpm = 1, |
2f7ca802 SG |
1537 | }; |
1538 | ||
d632eb1b | 1539 | module_usb_driver(smsc95xx_driver); |
2f7ca802 SG |
1540 | |
1541 | MODULE_AUTHOR("Nancy Lin"); | |
90b24cfb | 1542 | MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>"); |
2f7ca802 SG |
1543 | MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices"); |
1544 | MODULE_LICENSE("GPL"); |