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2f7ca802 SG |
1 | /*************************************************************************** |
2 | * | |
3 | * Copyright (C) 2007-2008 SMSC | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | * | |
19 | *****************************************************************************/ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/kmod.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/ethtool.h> | |
27 | #include <linux/mii.h> | |
28 | #include <linux/usb.h> | |
bbd9f9ee SG |
29 | #include <linux/bitrev.h> |
30 | #include <linux/crc16.h> | |
2f7ca802 SG |
31 | #include <linux/crc32.h> |
32 | #include <linux/usb/usbnet.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2f7ca802 SG |
34 | #include "smsc95xx.h" |
35 | ||
36 | #define SMSC_CHIPNAME "smsc95xx" | |
f7b29271 | 37 | #define SMSC_DRIVER_VERSION "1.0.4" |
2f7ca802 SG |
38 | #define HS_USB_PKT_SIZE (512) |
39 | #define FS_USB_PKT_SIZE (64) | |
40 | #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) | |
41 | #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) | |
42 | #define DEFAULT_BULK_IN_DELAY (0x00002000) | |
43 | #define MAX_SINGLE_PACKET_SIZE (2048) | |
44 | #define LAN95XX_EEPROM_MAGIC (0x9500) | |
45 | #define EEPROM_MAC_OFFSET (0x01) | |
f7b29271 | 46 | #define DEFAULT_TX_CSUM_ENABLE (true) |
2f7ca802 SG |
47 | #define DEFAULT_RX_CSUM_ENABLE (true) |
48 | #define SMSC95XX_INTERNAL_PHY_ID (1) | |
49 | #define SMSC95XX_TX_OVERHEAD (8) | |
f7b29271 | 50 | #define SMSC95XX_TX_OVERHEAD_CSUM (12) |
e5e3af83 | 51 | #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \ |
bbd9f9ee | 52 | WAKE_MCAST | WAKE_ARP | WAKE_MAGIC) |
2f7ca802 | 53 | |
9ebca507 SG |
54 | #define FEATURE_8_WAKEUP_FILTERS (0x01) |
55 | #define FEATURE_PHY_NLP_CROSSOVER (0x02) | |
56 | #define FEATURE_AUTOSUSPEND (0x04) | |
57 | ||
769ea6d8 SG |
58 | #define check_warn(ret, fmt, args...) \ |
59 | ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); }) | |
60 | ||
61 | #define check_warn_return(ret, fmt, args...) \ | |
62 | ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } }) | |
63 | ||
64 | #define check_warn_goto_done(ret, fmt, args...) \ | |
65 | ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } }) | |
66 | ||
2f7ca802 SG |
67 | struct smsc95xx_priv { |
68 | u32 mac_cr; | |
3c0f3c60 MZ |
69 | u32 hash_hi; |
70 | u32 hash_lo; | |
e0e474a8 | 71 | u32 wolopts; |
2f7ca802 | 72 | spinlock_t mac_cr_lock; |
9ebca507 | 73 | u8 features; |
2f7ca802 SG |
74 | }; |
75 | ||
eb939922 | 76 | static bool turbo_mode = true; |
2f7ca802 SG |
77 | module_param(turbo_mode, bool, 0644); |
78 | MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); | |
79 | ||
ec32115d ML |
80 | static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index, |
81 | u32 *data, int in_pm) | |
2f7ca802 | 82 | { |
72108fd2 | 83 | u32 buf; |
2f7ca802 | 84 | int ret; |
ec32115d | 85 | int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16); |
2f7ca802 SG |
86 | |
87 | BUG_ON(!dev); | |
88 | ||
ec32115d ML |
89 | if (!in_pm) |
90 | fn = usbnet_read_cmd; | |
91 | else | |
92 | fn = usbnet_read_cmd_nopm; | |
93 | ||
94 | ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN | |
95 | | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
96 | 0, index, &buf, 4); | |
2f7ca802 | 97 | if (unlikely(ret < 0)) |
1e1d7412 JP |
98 | netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n", |
99 | index, ret); | |
2f7ca802 | 100 | |
72108fd2 ML |
101 | le32_to_cpus(&buf); |
102 | *data = buf; | |
2f7ca802 SG |
103 | |
104 | return ret; | |
105 | } | |
106 | ||
ec32115d ML |
107 | static int __must_check __smsc95xx_write_reg(struct usbnet *dev, u32 index, |
108 | u32 data, int in_pm) | |
2f7ca802 | 109 | { |
72108fd2 | 110 | u32 buf; |
2f7ca802 | 111 | int ret; |
ec32115d | 112 | int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16); |
2f7ca802 SG |
113 | |
114 | BUG_ON(!dev); | |
115 | ||
ec32115d ML |
116 | if (!in_pm) |
117 | fn = usbnet_write_cmd; | |
118 | else | |
119 | fn = usbnet_write_cmd_nopm; | |
120 | ||
72108fd2 ML |
121 | buf = data; |
122 | cpu_to_le32s(&buf); | |
2f7ca802 | 123 | |
ec32115d ML |
124 | ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT |
125 | | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
126 | 0, index, &buf, 4); | |
2f7ca802 | 127 | if (unlikely(ret < 0)) |
1e1d7412 JP |
128 | netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n", |
129 | index, ret); | |
2f7ca802 | 130 | |
2f7ca802 SG |
131 | return ret; |
132 | } | |
133 | ||
ec32115d ML |
134 | static int __must_check smsc95xx_read_reg_nopm(struct usbnet *dev, u32 index, |
135 | u32 *data) | |
136 | { | |
137 | return __smsc95xx_read_reg(dev, index, data, 1); | |
138 | } | |
139 | ||
140 | static int __must_check smsc95xx_write_reg_nopm(struct usbnet *dev, u32 index, | |
141 | u32 data) | |
142 | { | |
143 | return __smsc95xx_write_reg(dev, index, data, 1); | |
144 | } | |
145 | ||
146 | static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index, | |
147 | u32 *data) | |
148 | { | |
149 | return __smsc95xx_read_reg(dev, index, data, 0); | |
150 | } | |
151 | ||
152 | static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index, | |
153 | u32 data) | |
154 | { | |
155 | return __smsc95xx_write_reg(dev, index, data, 0); | |
156 | } | |
e0e474a8 | 157 | |
2f7ca802 SG |
158 | /* Loop until the read is completed with timeout |
159 | * called with phy_mutex held */ | |
e5e3af83 SG |
160 | static int __must_check __smsc95xx_phy_wait_not_busy(struct usbnet *dev, |
161 | int in_pm) | |
2f7ca802 SG |
162 | { |
163 | unsigned long start_time = jiffies; | |
164 | u32 val; | |
769ea6d8 | 165 | int ret; |
2f7ca802 SG |
166 | |
167 | do { | |
e5e3af83 | 168 | ret = __smsc95xx_read_reg(dev, MII_ADDR, &val, in_pm); |
1e1d7412 | 169 | check_warn_return(ret, "Error reading MII_ACCESS\n"); |
2f7ca802 SG |
170 | if (!(val & MII_BUSY_)) |
171 | return 0; | |
172 | } while (!time_after(jiffies, start_time + HZ)); | |
173 | ||
174 | return -EIO; | |
175 | } | |
176 | ||
e5e3af83 SG |
177 | static int __smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx, |
178 | int in_pm) | |
2f7ca802 SG |
179 | { |
180 | struct usbnet *dev = netdev_priv(netdev); | |
181 | u32 val, addr; | |
769ea6d8 | 182 | int ret; |
2f7ca802 SG |
183 | |
184 | mutex_lock(&dev->phy_mutex); | |
185 | ||
186 | /* confirm MII not busy */ | |
e5e3af83 | 187 | ret = __smsc95xx_phy_wait_not_busy(dev, in_pm); |
1e1d7412 | 188 | check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_read\n"); |
2f7ca802 SG |
189 | |
190 | /* set the address, index & direction (read from PHY) */ | |
191 | phy_id &= dev->mii.phy_id_mask; | |
192 | idx &= dev->mii.reg_num_mask; | |
80928805 | 193 | addr = (phy_id << 11) | (idx << 6) | MII_READ_ | MII_BUSY_; |
e5e3af83 | 194 | ret = __smsc95xx_write_reg(dev, MII_ADDR, addr, in_pm); |
1e1d7412 | 195 | check_warn_goto_done(ret, "Error writing MII_ADDR\n"); |
2f7ca802 | 196 | |
e5e3af83 | 197 | ret = __smsc95xx_phy_wait_not_busy(dev, in_pm); |
1e1d7412 | 198 | check_warn_goto_done(ret, "Timed out reading MII reg %02X\n", idx); |
2f7ca802 | 199 | |
e5e3af83 | 200 | ret = __smsc95xx_read_reg(dev, MII_DATA, &val, in_pm); |
1e1d7412 | 201 | check_warn_goto_done(ret, "Error reading MII_DATA\n"); |
2f7ca802 | 202 | |
769ea6d8 | 203 | ret = (u16)(val & 0xFFFF); |
2f7ca802 | 204 | |
769ea6d8 SG |
205 | done: |
206 | mutex_unlock(&dev->phy_mutex); | |
207 | return ret; | |
2f7ca802 SG |
208 | } |
209 | ||
e5e3af83 SG |
210 | static void __smsc95xx_mdio_write(struct net_device *netdev, int phy_id, |
211 | int idx, int regval, int in_pm) | |
2f7ca802 SG |
212 | { |
213 | struct usbnet *dev = netdev_priv(netdev); | |
214 | u32 val, addr; | |
769ea6d8 | 215 | int ret; |
2f7ca802 SG |
216 | |
217 | mutex_lock(&dev->phy_mutex); | |
218 | ||
219 | /* confirm MII not busy */ | |
e5e3af83 | 220 | ret = __smsc95xx_phy_wait_not_busy(dev, in_pm); |
1e1d7412 | 221 | check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_write\n"); |
2f7ca802 SG |
222 | |
223 | val = regval; | |
e5e3af83 | 224 | ret = __smsc95xx_write_reg(dev, MII_DATA, val, in_pm); |
1e1d7412 | 225 | check_warn_goto_done(ret, "Error writing MII_DATA\n"); |
2f7ca802 SG |
226 | |
227 | /* set the address, index & direction (write to PHY) */ | |
228 | phy_id &= dev->mii.phy_id_mask; | |
229 | idx &= dev->mii.reg_num_mask; | |
80928805 | 230 | addr = (phy_id << 11) | (idx << 6) | MII_WRITE_ | MII_BUSY_; |
e5e3af83 | 231 | ret = __smsc95xx_write_reg(dev, MII_ADDR, addr, in_pm); |
1e1d7412 | 232 | check_warn_goto_done(ret, "Error writing MII_ADDR\n"); |
2f7ca802 | 233 | |
e5e3af83 | 234 | ret = __smsc95xx_phy_wait_not_busy(dev, in_pm); |
1e1d7412 | 235 | check_warn_goto_done(ret, "Timed out writing MII reg %02X\n", idx); |
2f7ca802 | 236 | |
769ea6d8 | 237 | done: |
2f7ca802 SG |
238 | mutex_unlock(&dev->phy_mutex); |
239 | } | |
240 | ||
e5e3af83 SG |
241 | static int smsc95xx_mdio_read_nopm(struct net_device *netdev, int phy_id, |
242 | int idx) | |
243 | { | |
244 | return __smsc95xx_mdio_read(netdev, phy_id, idx, 1); | |
245 | } | |
246 | ||
247 | static void smsc95xx_mdio_write_nopm(struct net_device *netdev, int phy_id, | |
248 | int idx, int regval) | |
249 | { | |
250 | __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 1); | |
251 | } | |
252 | ||
253 | static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx) | |
254 | { | |
255 | return __smsc95xx_mdio_read(netdev, phy_id, idx, 0); | |
256 | } | |
257 | ||
258 | static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx, | |
259 | int regval) | |
260 | { | |
261 | __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 0); | |
262 | } | |
263 | ||
769ea6d8 | 264 | static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev) |
2f7ca802 SG |
265 | { |
266 | unsigned long start_time = jiffies; | |
267 | u32 val; | |
769ea6d8 | 268 | int ret; |
2f7ca802 SG |
269 | |
270 | do { | |
769ea6d8 | 271 | ret = smsc95xx_read_reg(dev, E2P_CMD, &val); |
1e1d7412 | 272 | check_warn_return(ret, "Error reading E2P_CMD\n"); |
2f7ca802 SG |
273 | if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) |
274 | break; | |
275 | udelay(40); | |
276 | } while (!time_after(jiffies, start_time + HZ)); | |
277 | ||
278 | if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { | |
60b86755 | 279 | netdev_warn(dev->net, "EEPROM read operation timeout\n"); |
2f7ca802 SG |
280 | return -EIO; |
281 | } | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
769ea6d8 | 286 | static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev) |
2f7ca802 SG |
287 | { |
288 | unsigned long start_time = jiffies; | |
289 | u32 val; | |
769ea6d8 | 290 | int ret; |
2f7ca802 SG |
291 | |
292 | do { | |
769ea6d8 | 293 | ret = smsc95xx_read_reg(dev, E2P_CMD, &val); |
1e1d7412 | 294 | check_warn_return(ret, "Error reading E2P_CMD\n"); |
2f7ca802 | 295 | |
2f7ca802 SG |
296 | if (!(val & E2P_CMD_BUSY_)) |
297 | return 0; | |
298 | ||
299 | udelay(40); | |
300 | } while (!time_after(jiffies, start_time + HZ)); | |
301 | ||
60b86755 | 302 | netdev_warn(dev->net, "EEPROM is busy\n"); |
2f7ca802 SG |
303 | return -EIO; |
304 | } | |
305 | ||
306 | static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length, | |
307 | u8 *data) | |
308 | { | |
309 | u32 val; | |
310 | int i, ret; | |
311 | ||
312 | BUG_ON(!dev); | |
313 | BUG_ON(!data); | |
314 | ||
315 | ret = smsc95xx_eeprom_confirm_not_busy(dev); | |
316 | if (ret) | |
317 | return ret; | |
318 | ||
319 | for (i = 0; i < length; i++) { | |
320 | val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); | |
769ea6d8 | 321 | ret = smsc95xx_write_reg(dev, E2P_CMD, val); |
1e1d7412 | 322 | check_warn_return(ret, "Error writing E2P_CMD\n"); |
2f7ca802 SG |
323 | |
324 | ret = smsc95xx_wait_eeprom(dev); | |
325 | if (ret < 0) | |
326 | return ret; | |
327 | ||
769ea6d8 | 328 | ret = smsc95xx_read_reg(dev, E2P_DATA, &val); |
1e1d7412 | 329 | check_warn_return(ret, "Error reading E2P_DATA\n"); |
2f7ca802 SG |
330 | |
331 | data[i] = val & 0xFF; | |
332 | offset++; | |
333 | } | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
338 | static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length, | |
339 | u8 *data) | |
340 | { | |
341 | u32 val; | |
342 | int i, ret; | |
343 | ||
344 | BUG_ON(!dev); | |
345 | BUG_ON(!data); | |
346 | ||
347 | ret = smsc95xx_eeprom_confirm_not_busy(dev); | |
348 | if (ret) | |
349 | return ret; | |
350 | ||
351 | /* Issue write/erase enable command */ | |
352 | val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_; | |
769ea6d8 | 353 | ret = smsc95xx_write_reg(dev, E2P_CMD, val); |
1e1d7412 | 354 | check_warn_return(ret, "Error writing E2P_DATA\n"); |
2f7ca802 SG |
355 | |
356 | ret = smsc95xx_wait_eeprom(dev); | |
357 | if (ret < 0) | |
358 | return ret; | |
359 | ||
360 | for (i = 0; i < length; i++) { | |
361 | ||
362 | /* Fill data register */ | |
363 | val = data[i]; | |
769ea6d8 | 364 | ret = smsc95xx_write_reg(dev, E2P_DATA, val); |
1e1d7412 | 365 | check_warn_return(ret, "Error writing E2P_DATA\n"); |
2f7ca802 SG |
366 | |
367 | /* Send "write" command */ | |
368 | val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_); | |
769ea6d8 | 369 | ret = smsc95xx_write_reg(dev, E2P_CMD, val); |
1e1d7412 | 370 | check_warn_return(ret, "Error writing E2P_CMD\n"); |
2f7ca802 SG |
371 | |
372 | ret = smsc95xx_wait_eeprom(dev); | |
373 | if (ret < 0) | |
374 | return ret; | |
375 | ||
376 | offset++; | |
377 | } | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
769ea6d8 SG |
382 | static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index, |
383 | u32 *data) | |
2f7ca802 | 384 | { |
1d74a6bd | 385 | const u16 size = 4; |
72108fd2 | 386 | int ret; |
2f7ca802 | 387 | |
72108fd2 ML |
388 | ret = usbnet_write_cmd_async(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, |
389 | USB_DIR_OUT | USB_TYPE_VENDOR | | |
390 | USB_RECIP_DEVICE, | |
391 | 0, index, data, size); | |
392 | if (ret < 0) | |
393 | netdev_warn(dev->net, "Error write async cmd, sts=%d\n", | |
394 | ret); | |
395 | return ret; | |
2f7ca802 SG |
396 | } |
397 | ||
398 | /* returns hash bit number for given MAC address | |
399 | * example: | |
400 | * 01 00 5E 00 00 01 -> returns bit number 31 */ | |
401 | static unsigned int smsc95xx_hash(char addr[ETH_ALEN]) | |
402 | { | |
403 | return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; | |
404 | } | |
405 | ||
406 | static void smsc95xx_set_multicast(struct net_device *netdev) | |
407 | { | |
408 | struct usbnet *dev = netdev_priv(netdev); | |
409 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
2f7ca802 | 410 | unsigned long flags; |
769ea6d8 | 411 | int ret; |
2f7ca802 | 412 | |
3c0f3c60 MZ |
413 | pdata->hash_hi = 0; |
414 | pdata->hash_lo = 0; | |
415 | ||
2f7ca802 SG |
416 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); |
417 | ||
418 | if (dev->net->flags & IFF_PROMISC) { | |
a475f603 | 419 | netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n"); |
2f7ca802 SG |
420 | pdata->mac_cr |= MAC_CR_PRMS_; |
421 | pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
422 | } else if (dev->net->flags & IFF_ALLMULTI) { | |
a475f603 | 423 | netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n"); |
2f7ca802 SG |
424 | pdata->mac_cr |= MAC_CR_MCPAS_; |
425 | pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_); | |
4cd24eaf | 426 | } else if (!netdev_mc_empty(dev->net)) { |
22bedad3 | 427 | struct netdev_hw_addr *ha; |
2f7ca802 SG |
428 | |
429 | pdata->mac_cr |= MAC_CR_HPFILT_; | |
430 | pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_); | |
431 | ||
22bedad3 JP |
432 | netdev_for_each_mc_addr(ha, netdev) { |
433 | u32 bitnum = smsc95xx_hash(ha->addr); | |
a92635dc JP |
434 | u32 mask = 0x01 << (bitnum & 0x1F); |
435 | if (bitnum & 0x20) | |
3c0f3c60 | 436 | pdata->hash_hi |= mask; |
a92635dc | 437 | else |
3c0f3c60 | 438 | pdata->hash_lo |= mask; |
2f7ca802 SG |
439 | } |
440 | ||
a475f603 | 441 | netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n", |
3c0f3c60 | 442 | pdata->hash_hi, pdata->hash_lo); |
2f7ca802 | 443 | } else { |
a475f603 | 444 | netif_dbg(dev, drv, dev->net, "receive own packets only\n"); |
2f7ca802 SG |
445 | pdata->mac_cr &= |
446 | ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
447 | } | |
448 | ||
449 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
450 | ||
451 | /* Initiate async writes, as we can't wait for completion here */ | |
769ea6d8 | 452 | ret = smsc95xx_write_reg_async(dev, HASHH, &pdata->hash_hi); |
1e1d7412 | 453 | check_warn(ret, "failed to initiate async write to HASHH\n"); |
769ea6d8 SG |
454 | |
455 | ret = smsc95xx_write_reg_async(dev, HASHL, &pdata->hash_lo); | |
1e1d7412 | 456 | check_warn(ret, "failed to initiate async write to HASHL\n"); |
769ea6d8 SG |
457 | |
458 | ret = smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr); | |
1e1d7412 | 459 | check_warn(ret, "failed to initiate async write to MAC_CR\n"); |
2f7ca802 SG |
460 | } |
461 | ||
769ea6d8 SG |
462 | static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex, |
463 | u16 lcladv, u16 rmtadv) | |
2f7ca802 SG |
464 | { |
465 | u32 flow, afc_cfg = 0; | |
466 | ||
467 | int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg); | |
1e1d7412 | 468 | check_warn_return(ret, "Error reading AFC_CFG\n"); |
2f7ca802 SG |
469 | |
470 | if (duplex == DUPLEX_FULL) { | |
bc02ff95 | 471 | u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
2f7ca802 SG |
472 | |
473 | if (cap & FLOW_CTRL_RX) | |
474 | flow = 0xFFFF0002; | |
475 | else | |
476 | flow = 0; | |
477 | ||
478 | if (cap & FLOW_CTRL_TX) | |
479 | afc_cfg |= 0xF; | |
480 | else | |
481 | afc_cfg &= ~0xF; | |
482 | ||
a475f603 | 483 | netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n", |
60b86755 JP |
484 | cap & FLOW_CTRL_RX ? "enabled" : "disabled", |
485 | cap & FLOW_CTRL_TX ? "enabled" : "disabled"); | |
2f7ca802 | 486 | } else { |
a475f603 | 487 | netif_dbg(dev, link, dev->net, "half duplex\n"); |
2f7ca802 SG |
488 | flow = 0; |
489 | afc_cfg |= 0xF; | |
490 | } | |
491 | ||
769ea6d8 | 492 | ret = smsc95xx_write_reg(dev, FLOW, flow); |
1e1d7412 | 493 | check_warn_return(ret, "Error writing FLOW\n"); |
769ea6d8 SG |
494 | |
495 | ret = smsc95xx_write_reg(dev, AFC_CFG, afc_cfg); | |
1e1d7412 | 496 | check_warn_return(ret, "Error writing AFC_CFG\n"); |
769ea6d8 SG |
497 | |
498 | return 0; | |
2f7ca802 SG |
499 | } |
500 | ||
501 | static int smsc95xx_link_reset(struct usbnet *dev) | |
502 | { | |
503 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
504 | struct mii_if_info *mii = &dev->mii; | |
8ae6daca | 505 | struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; |
2f7ca802 SG |
506 | unsigned long flags; |
507 | u16 lcladv, rmtadv; | |
769ea6d8 | 508 | int ret; |
2f7ca802 SG |
509 | |
510 | /* clear interrupt status */ | |
769ea6d8 | 511 | ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC); |
1e1d7412 | 512 | check_warn_return(ret, "Error reading PHY_INT_SRC\n"); |
769ea6d8 SG |
513 | |
514 | ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); | |
1e1d7412 | 515 | check_warn_return(ret, "Error writing INT_STS\n"); |
2f7ca802 SG |
516 | |
517 | mii_check_media(mii, 1, 1); | |
518 | mii_ethtool_gset(&dev->mii, &ecmd); | |
519 | lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE); | |
520 | rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA); | |
521 | ||
8ae6daca DD |
522 | netif_dbg(dev, link, dev->net, |
523 | "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n", | |
524 | ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv); | |
2f7ca802 SG |
525 | |
526 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); | |
527 | if (ecmd.duplex != DUPLEX_FULL) { | |
528 | pdata->mac_cr &= ~MAC_CR_FDPX_; | |
529 | pdata->mac_cr |= MAC_CR_RCVOWN_; | |
530 | } else { | |
531 | pdata->mac_cr &= ~MAC_CR_RCVOWN_; | |
532 | pdata->mac_cr |= MAC_CR_FDPX_; | |
533 | } | |
534 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
535 | ||
769ea6d8 | 536 | ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); |
1e1d7412 | 537 | check_warn_return(ret, "Error writing MAC_CR\n"); |
2f7ca802 | 538 | |
769ea6d8 | 539 | ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv); |
1e1d7412 | 540 | check_warn_return(ret, "Error updating PHY flow control\n"); |
2f7ca802 SG |
541 | |
542 | return 0; | |
543 | } | |
544 | ||
545 | static void smsc95xx_status(struct usbnet *dev, struct urb *urb) | |
546 | { | |
547 | u32 intdata; | |
548 | ||
549 | if (urb->actual_length != 4) { | |
60b86755 JP |
550 | netdev_warn(dev->net, "unexpected urb length %d\n", |
551 | urb->actual_length); | |
2f7ca802 SG |
552 | return; |
553 | } | |
554 | ||
555 | memcpy(&intdata, urb->transfer_buffer, 4); | |
1d74a6bd | 556 | le32_to_cpus(&intdata); |
2f7ca802 | 557 | |
a475f603 | 558 | netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata); |
2f7ca802 SG |
559 | |
560 | if (intdata & INT_ENP_PHY_INT_) | |
561 | usbnet_defer_kevent(dev, EVENT_LINK_RESET); | |
562 | else | |
60b86755 JP |
563 | netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n", |
564 | intdata); | |
2f7ca802 SG |
565 | } |
566 | ||
f7b29271 | 567 | /* Enable or disable Tx & Rx checksum offload engines */ |
c8f44aff MM |
568 | static int smsc95xx_set_features(struct net_device *netdev, |
569 | netdev_features_t features) | |
2f7ca802 | 570 | { |
78e47fe4 | 571 | struct usbnet *dev = netdev_priv(netdev); |
2f7ca802 | 572 | u32 read_buf; |
78e47fe4 MM |
573 | int ret; |
574 | ||
575 | ret = smsc95xx_read_reg(dev, COE_CR, &read_buf); | |
769ea6d8 | 576 | check_warn_return(ret, "Failed to read COE_CR: %d\n", ret); |
2f7ca802 | 577 | |
78e47fe4 | 578 | if (features & NETIF_F_HW_CSUM) |
f7b29271 SG |
579 | read_buf |= Tx_COE_EN_; |
580 | else | |
581 | read_buf &= ~Tx_COE_EN_; | |
582 | ||
78e47fe4 | 583 | if (features & NETIF_F_RXCSUM) |
2f7ca802 SG |
584 | read_buf |= Rx_COE_EN_; |
585 | else | |
586 | read_buf &= ~Rx_COE_EN_; | |
587 | ||
588 | ret = smsc95xx_write_reg(dev, COE_CR, read_buf); | |
769ea6d8 | 589 | check_warn_return(ret, "Failed to write COE_CR: %d\n", ret); |
2f7ca802 | 590 | |
a475f603 | 591 | netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf); |
2f7ca802 SG |
592 | return 0; |
593 | } | |
594 | ||
595 | static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net) | |
596 | { | |
597 | return MAX_EEPROM_SIZE; | |
598 | } | |
599 | ||
600 | static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev, | |
601 | struct ethtool_eeprom *ee, u8 *data) | |
602 | { | |
603 | struct usbnet *dev = netdev_priv(netdev); | |
604 | ||
605 | ee->magic = LAN95XX_EEPROM_MAGIC; | |
606 | ||
607 | return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data); | |
608 | } | |
609 | ||
610 | static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev, | |
611 | struct ethtool_eeprom *ee, u8 *data) | |
612 | { | |
613 | struct usbnet *dev = netdev_priv(netdev); | |
614 | ||
615 | if (ee->magic != LAN95XX_EEPROM_MAGIC) { | |
60b86755 JP |
616 | netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n", |
617 | ee->magic); | |
2f7ca802 SG |
618 | return -EINVAL; |
619 | } | |
620 | ||
621 | return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data); | |
622 | } | |
623 | ||
9fa32e94 EV |
624 | static int smsc95xx_ethtool_getregslen(struct net_device *netdev) |
625 | { | |
626 | /* all smsc95xx registers */ | |
627 | return COE_CR - ID_REV + 1; | |
628 | } | |
629 | ||
630 | static void | |
631 | smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs, | |
632 | void *buf) | |
633 | { | |
634 | struct usbnet *dev = netdev_priv(netdev); | |
d348446b DC |
635 | unsigned int i, j; |
636 | int retval; | |
9fa32e94 EV |
637 | u32 *data = buf; |
638 | ||
639 | retval = smsc95xx_read_reg(dev, ID_REV, ®s->version); | |
640 | if (retval < 0) { | |
641 | netdev_warn(netdev, "REGS: cannot read ID_REV\n"); | |
642 | return; | |
643 | } | |
644 | ||
645 | for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) { | |
646 | retval = smsc95xx_read_reg(dev, i, &data[j]); | |
647 | if (retval < 0) { | |
648 | netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i); | |
649 | return; | |
650 | } | |
651 | } | |
652 | } | |
653 | ||
e0e474a8 SG |
654 | static void smsc95xx_ethtool_get_wol(struct net_device *net, |
655 | struct ethtool_wolinfo *wolinfo) | |
656 | { | |
657 | struct usbnet *dev = netdev_priv(net); | |
658 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
659 | ||
660 | wolinfo->supported = SUPPORTED_WAKE; | |
661 | wolinfo->wolopts = pdata->wolopts; | |
662 | } | |
663 | ||
664 | static int smsc95xx_ethtool_set_wol(struct net_device *net, | |
665 | struct ethtool_wolinfo *wolinfo) | |
666 | { | |
667 | struct usbnet *dev = netdev_priv(net); | |
668 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
3b14692c | 669 | int ret; |
e0e474a8 SG |
670 | |
671 | pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE; | |
3b14692c SG |
672 | |
673 | ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts); | |
674 | check_warn_return(ret, "device_set_wakeup_enable error %d\n", ret); | |
675 | ||
e0e474a8 SG |
676 | return 0; |
677 | } | |
678 | ||
0fc0b732 | 679 | static const struct ethtool_ops smsc95xx_ethtool_ops = { |
2f7ca802 SG |
680 | .get_link = usbnet_get_link, |
681 | .nway_reset = usbnet_nway_reset, | |
682 | .get_drvinfo = usbnet_get_drvinfo, | |
683 | .get_msglevel = usbnet_get_msglevel, | |
684 | .set_msglevel = usbnet_set_msglevel, | |
685 | .get_settings = usbnet_get_settings, | |
686 | .set_settings = usbnet_set_settings, | |
687 | .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len, | |
688 | .get_eeprom = smsc95xx_ethtool_get_eeprom, | |
689 | .set_eeprom = smsc95xx_ethtool_set_eeprom, | |
9fa32e94 EV |
690 | .get_regs_len = smsc95xx_ethtool_getregslen, |
691 | .get_regs = smsc95xx_ethtool_getregs, | |
e0e474a8 SG |
692 | .get_wol = smsc95xx_ethtool_get_wol, |
693 | .set_wol = smsc95xx_ethtool_set_wol, | |
2f7ca802 SG |
694 | }; |
695 | ||
696 | static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
697 | { | |
698 | struct usbnet *dev = netdev_priv(netdev); | |
699 | ||
700 | if (!netif_running(netdev)) | |
701 | return -EINVAL; | |
702 | ||
703 | return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); | |
704 | } | |
705 | ||
706 | static void smsc95xx_init_mac_address(struct usbnet *dev) | |
707 | { | |
708 | /* try reading mac address from EEPROM */ | |
709 | if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, | |
710 | dev->net->dev_addr) == 0) { | |
711 | if (is_valid_ether_addr(dev->net->dev_addr)) { | |
712 | /* eeprom values are valid so use them */ | |
a475f603 | 713 | netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n"); |
2f7ca802 SG |
714 | return; |
715 | } | |
716 | } | |
717 | ||
718 | /* no eeprom, or eeprom values are invalid. generate random MAC */ | |
f2cedb63 | 719 | eth_hw_addr_random(dev->net); |
c7e12ead | 720 | netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n"); |
2f7ca802 SG |
721 | } |
722 | ||
723 | static int smsc95xx_set_mac_address(struct usbnet *dev) | |
724 | { | |
725 | u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 | | |
726 | dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24; | |
727 | u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8; | |
728 | int ret; | |
729 | ||
730 | ret = smsc95xx_write_reg(dev, ADDRL, addr_lo); | |
769ea6d8 | 731 | check_warn_return(ret, "Failed to write ADDRL: %d\n", ret); |
2f7ca802 SG |
732 | |
733 | ret = smsc95xx_write_reg(dev, ADDRH, addr_hi); | |
769ea6d8 | 734 | check_warn_return(ret, "Failed to write ADDRH: %d\n", ret); |
2f7ca802 SG |
735 | |
736 | return 0; | |
737 | } | |
738 | ||
739 | /* starts the TX path */ | |
769ea6d8 | 740 | static int smsc95xx_start_tx_path(struct usbnet *dev) |
2f7ca802 SG |
741 | { |
742 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
743 | unsigned long flags; | |
769ea6d8 | 744 | int ret; |
2f7ca802 SG |
745 | |
746 | /* Enable Tx at MAC */ | |
747 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); | |
748 | pdata->mac_cr |= MAC_CR_TXEN_; | |
749 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
750 | ||
769ea6d8 SG |
751 | ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); |
752 | check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret); | |
2f7ca802 SG |
753 | |
754 | /* Enable Tx at SCSRs */ | |
769ea6d8 SG |
755 | ret = smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_); |
756 | check_warn_return(ret, "Failed to write TX_CFG: %d\n", ret); | |
757 | ||
758 | return 0; | |
2f7ca802 SG |
759 | } |
760 | ||
761 | /* Starts the Receive path */ | |
ec32115d | 762 | static int smsc95xx_start_rx_path(struct usbnet *dev, int in_pm) |
2f7ca802 SG |
763 | { |
764 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
765 | unsigned long flags; | |
769ea6d8 | 766 | int ret; |
2f7ca802 SG |
767 | |
768 | spin_lock_irqsave(&pdata->mac_cr_lock, flags); | |
769 | pdata->mac_cr |= MAC_CR_RXEN_; | |
770 | spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); | |
771 | ||
ec32115d | 772 | ret = __smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr, in_pm); |
769ea6d8 SG |
773 | check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret); |
774 | ||
775 | return 0; | |
2f7ca802 SG |
776 | } |
777 | ||
778 | static int smsc95xx_phy_initialize(struct usbnet *dev) | |
779 | { | |
769ea6d8 | 780 | int bmcr, ret, timeout = 0; |
db443c44 | 781 | |
2f7ca802 SG |
782 | /* Initialize MII structure */ |
783 | dev->mii.dev = dev->net; | |
784 | dev->mii.mdio_read = smsc95xx_mdio_read; | |
785 | dev->mii.mdio_write = smsc95xx_mdio_write; | |
786 | dev->mii.phy_id_mask = 0x1f; | |
787 | dev->mii.reg_num_mask = 0x1f; | |
788 | dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID; | |
789 | ||
db443c44 | 790 | /* reset phy and wait for reset to complete */ |
2f7ca802 | 791 | smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
db443c44 SG |
792 | |
793 | do { | |
794 | msleep(10); | |
795 | bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR); | |
796 | timeout++; | |
d9460920 | 797 | } while ((bmcr & BMCR_RESET) && (timeout < 100)); |
db443c44 SG |
798 | |
799 | if (timeout >= 100) { | |
800 | netdev_warn(dev->net, "timeout on PHY Reset"); | |
801 | return -EIO; | |
802 | } | |
803 | ||
2f7ca802 SG |
804 | smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, |
805 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | | |
806 | ADVERTISE_PAUSE_ASYM); | |
807 | ||
808 | /* read to clear */ | |
769ea6d8 | 809 | ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC); |
1e1d7412 | 810 | check_warn_return(ret, "Failed to read PHY_INT_SRC during init\n"); |
2f7ca802 SG |
811 | |
812 | smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK, | |
813 | PHY_INT_MASK_DEFAULT_); | |
814 | mii_nway_restart(&dev->mii); | |
815 | ||
a475f603 | 816 | netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n"); |
2f7ca802 SG |
817 | return 0; |
818 | } | |
819 | ||
820 | static int smsc95xx_reset(struct usbnet *dev) | |
821 | { | |
822 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
823 | u32 read_buf, write_buf, burst_cap; | |
824 | int ret = 0, timeout; | |
2f7ca802 | 825 | |
a475f603 | 826 | netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n"); |
2f7ca802 | 827 | |
4436761b | 828 | ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_); |
769ea6d8 | 829 | check_warn_return(ret, "Failed to write HW_CFG_LRST_ bit in HW_CFG\n"); |
2f7ca802 SG |
830 | |
831 | timeout = 0; | |
832 | do { | |
cf2acec2 | 833 | msleep(10); |
2f7ca802 | 834 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); |
769ea6d8 | 835 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
2f7ca802 SG |
836 | timeout++; |
837 | } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); | |
838 | ||
839 | if (timeout >= 100) { | |
60b86755 | 840 | netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n"); |
2f7ca802 SG |
841 | return ret; |
842 | } | |
843 | ||
4436761b | 844 | ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_); |
769ea6d8 | 845 | check_warn_return(ret, "Failed to write PM_CTRL: %d\n", ret); |
2f7ca802 SG |
846 | |
847 | timeout = 0; | |
848 | do { | |
cf2acec2 | 849 | msleep(10); |
2f7ca802 | 850 | ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); |
769ea6d8 | 851 | check_warn_return(ret, "Failed to read PM_CTRL: %d\n", ret); |
2f7ca802 SG |
852 | timeout++; |
853 | } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); | |
854 | ||
855 | if (timeout >= 100) { | |
60b86755 | 856 | netdev_warn(dev->net, "timeout waiting for PHY Reset\n"); |
2f7ca802 SG |
857 | return ret; |
858 | } | |
859 | ||
2f7ca802 SG |
860 | ret = smsc95xx_set_mac_address(dev); |
861 | if (ret < 0) | |
862 | return ret; | |
863 | ||
1e1d7412 JP |
864 | netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n", |
865 | dev->net->dev_addr); | |
2f7ca802 SG |
866 | |
867 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 | 868 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
2f7ca802 | 869 | |
1e1d7412 JP |
870 | netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n", |
871 | read_buf); | |
2f7ca802 SG |
872 | |
873 | read_buf |= HW_CFG_BIR_; | |
874 | ||
875 | ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); | |
769ea6d8 | 876 | check_warn_return(ret, "Failed to write HW_CFG_BIR_ bit in HW_CFG\n"); |
2f7ca802 SG |
877 | |
878 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 | 879 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
a475f603 JP |
880 | netif_dbg(dev, ifup, dev->net, |
881 | "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n", | |
882 | read_buf); | |
2f7ca802 SG |
883 | |
884 | if (!turbo_mode) { | |
885 | burst_cap = 0; | |
886 | dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE; | |
887 | } else if (dev->udev->speed == USB_SPEED_HIGH) { | |
888 | burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; | |
889 | dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; | |
890 | } else { | |
891 | burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; | |
892 | dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; | |
893 | } | |
894 | ||
1e1d7412 JP |
895 | netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n", |
896 | (ulong)dev->rx_urb_size); | |
2f7ca802 SG |
897 | |
898 | ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); | |
769ea6d8 | 899 | check_warn_return(ret, "Failed to write BURST_CAP: %d\n", ret); |
2f7ca802 SG |
900 | |
901 | ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf); | |
769ea6d8 SG |
902 | check_warn_return(ret, "Failed to read BURST_CAP: %d\n", ret); |
903 | ||
a475f603 JP |
904 | netif_dbg(dev, ifup, dev->net, |
905 | "Read Value from BURST_CAP after writing: 0x%08x\n", | |
906 | read_buf); | |
2f7ca802 | 907 | |
4436761b | 908 | ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); |
769ea6d8 | 909 | check_warn_return(ret, "Failed to write BULK_IN_DLY: %d\n", ret); |
2f7ca802 SG |
910 | |
911 | ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf); | |
769ea6d8 SG |
912 | check_warn_return(ret, "Failed to read BULK_IN_DLY: %d\n", ret); |
913 | ||
a475f603 JP |
914 | netif_dbg(dev, ifup, dev->net, |
915 | "Read Value from BULK_IN_DLY after writing: 0x%08x\n", | |
916 | read_buf); | |
2f7ca802 SG |
917 | |
918 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 SG |
919 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
920 | ||
1e1d7412 JP |
921 | netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG: 0x%08x\n", |
922 | read_buf); | |
2f7ca802 SG |
923 | |
924 | if (turbo_mode) | |
925 | read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); | |
926 | ||
927 | read_buf &= ~HW_CFG_RXDOFF_; | |
928 | ||
929 | /* set Rx data offset=2, Make IP header aligns on word boundary. */ | |
930 | read_buf |= NET_IP_ALIGN << 9; | |
931 | ||
932 | ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); | |
769ea6d8 | 933 | check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret); |
2f7ca802 SG |
934 | |
935 | ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); | |
769ea6d8 SG |
936 | check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); |
937 | ||
a475f603 JP |
938 | netif_dbg(dev, ifup, dev->net, |
939 | "Read Value from HW_CFG after writing: 0x%08x\n", read_buf); | |
2f7ca802 | 940 | |
4436761b | 941 | ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); |
769ea6d8 | 942 | check_warn_return(ret, "Failed to write INT_STS: %d\n", ret); |
2f7ca802 SG |
943 | |
944 | ret = smsc95xx_read_reg(dev, ID_REV, &read_buf); | |
769ea6d8 | 945 | check_warn_return(ret, "Failed to read ID_REV: %d\n", ret); |
a475f603 | 946 | netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf); |
2f7ca802 | 947 | |
f293501c SG |
948 | /* Configure GPIO pins as LED outputs */ |
949 | write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED | | |
950 | LED_GPIO_CFG_FDX_LED; | |
951 | ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf); | |
769ea6d8 | 952 | check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d\n", ret); |
f293501c | 953 | |
2f7ca802 | 954 | /* Init Tx */ |
4436761b | 955 | ret = smsc95xx_write_reg(dev, FLOW, 0); |
769ea6d8 | 956 | check_warn_return(ret, "Failed to write FLOW: %d\n", ret); |
2f7ca802 | 957 | |
4436761b | 958 | ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT); |
769ea6d8 | 959 | check_warn_return(ret, "Failed to write AFC_CFG: %d\n", ret); |
2f7ca802 SG |
960 | |
961 | /* Don't need mac_cr_lock during initialisation */ | |
962 | ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr); | |
769ea6d8 | 963 | check_warn_return(ret, "Failed to read MAC_CR: %d\n", ret); |
2f7ca802 SG |
964 | |
965 | /* Init Rx */ | |
966 | /* Set Vlan */ | |
4436761b | 967 | ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q); |
769ea6d8 | 968 | check_warn_return(ret, "Failed to write VLAN1: %d\n", ret); |
2f7ca802 | 969 | |
f7b29271 | 970 | /* Enable or disable checksum offload engines */ |
769ea6d8 | 971 | ret = smsc95xx_set_features(dev->net, dev->net->features); |
1e1d7412 | 972 | check_warn_return(ret, "Failed to set checksum offload features\n"); |
2f7ca802 SG |
973 | |
974 | smsc95xx_set_multicast(dev->net); | |
975 | ||
769ea6d8 | 976 | ret = smsc95xx_phy_initialize(dev); |
1e1d7412 | 977 | check_warn_return(ret, "Failed to init PHY\n"); |
2f7ca802 SG |
978 | |
979 | ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf); | |
769ea6d8 | 980 | check_warn_return(ret, "Failed to read INT_EP_CTL: %d\n", ret); |
2f7ca802 SG |
981 | |
982 | /* enable PHY interrupts */ | |
983 | read_buf |= INT_EP_CTL_PHY_INT_; | |
984 | ||
985 | ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf); | |
769ea6d8 | 986 | check_warn_return(ret, "Failed to write INT_EP_CTL: %d\n", ret); |
2f7ca802 | 987 | |
769ea6d8 | 988 | ret = smsc95xx_start_tx_path(dev); |
1e1d7412 | 989 | check_warn_return(ret, "Failed to start TX path\n"); |
769ea6d8 | 990 | |
ec32115d | 991 | ret = smsc95xx_start_rx_path(dev, 0); |
1e1d7412 | 992 | check_warn_return(ret, "Failed to start RX path\n"); |
2f7ca802 | 993 | |
a475f603 | 994 | netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n"); |
2f7ca802 SG |
995 | return 0; |
996 | } | |
997 | ||
63e77b39 SH |
998 | static const struct net_device_ops smsc95xx_netdev_ops = { |
999 | .ndo_open = usbnet_open, | |
1000 | .ndo_stop = usbnet_stop, | |
1001 | .ndo_start_xmit = usbnet_start_xmit, | |
1002 | .ndo_tx_timeout = usbnet_tx_timeout, | |
1003 | .ndo_change_mtu = usbnet_change_mtu, | |
1004 | .ndo_set_mac_address = eth_mac_addr, | |
1005 | .ndo_validate_addr = eth_validate_addr, | |
1006 | .ndo_do_ioctl = smsc95xx_ioctl, | |
afc4b13d | 1007 | .ndo_set_rx_mode = smsc95xx_set_multicast, |
78e47fe4 | 1008 | .ndo_set_features = smsc95xx_set_features, |
63e77b39 SH |
1009 | }; |
1010 | ||
2f7ca802 SG |
1011 | static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf) |
1012 | { | |
1013 | struct smsc95xx_priv *pdata = NULL; | |
bbd9f9ee | 1014 | u32 val; |
2f7ca802 SG |
1015 | int ret; |
1016 | ||
1017 | printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n"); | |
1018 | ||
1019 | ret = usbnet_get_endpoints(dev, intf); | |
769ea6d8 | 1020 | check_warn_return(ret, "usbnet_get_endpoints failed: %d\n", ret); |
2f7ca802 SG |
1021 | |
1022 | dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv), | |
1023 | GFP_KERNEL); | |
1024 | ||
1025 | pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
1026 | if (!pdata) { | |
60b86755 | 1027 | netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n"); |
2f7ca802 SG |
1028 | return -ENOMEM; |
1029 | } | |
1030 | ||
1031 | spin_lock_init(&pdata->mac_cr_lock); | |
1032 | ||
78e47fe4 MM |
1033 | if (DEFAULT_TX_CSUM_ENABLE) |
1034 | dev->net->features |= NETIF_F_HW_CSUM; | |
1035 | if (DEFAULT_RX_CSUM_ENABLE) | |
1036 | dev->net->features |= NETIF_F_RXCSUM; | |
1037 | ||
1038 | dev->net->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM; | |
2f7ca802 | 1039 | |
f4e8ab7c BB |
1040 | smsc95xx_init_mac_address(dev); |
1041 | ||
2f7ca802 SG |
1042 | /* Init all registers */ |
1043 | ret = smsc95xx_reset(dev); | |
1044 | ||
bbd9f9ee SG |
1045 | /* detect device revision as different features may be available */ |
1046 | ret = smsc95xx_read_reg(dev, ID_REV, &val); | |
1047 | check_warn_return(ret, "Failed to read ID_REV: %d\n", ret); | |
1048 | val >>= 16; | |
9ebca507 SG |
1049 | |
1050 | if ((val == ID_REV_CHIP_ID_9500A_) || (val == ID_REV_CHIP_ID_9530_) || | |
1051 | (val == ID_REV_CHIP_ID_89530_) || (val == ID_REV_CHIP_ID_9730_)) | |
1052 | pdata->features = (FEATURE_8_WAKEUP_FILTERS | | |
1053 | FEATURE_PHY_NLP_CROSSOVER | | |
1054 | FEATURE_AUTOSUSPEND); | |
1055 | else if (val == ID_REV_CHIP_ID_9512_) | |
1056 | pdata->features = FEATURE_8_WAKEUP_FILTERS; | |
bbd9f9ee | 1057 | |
63e77b39 | 1058 | dev->net->netdev_ops = &smsc95xx_netdev_ops; |
2f7ca802 | 1059 | dev->net->ethtool_ops = &smsc95xx_ethtool_ops; |
2f7ca802 | 1060 | dev->net->flags |= IFF_MULTICAST; |
78e47fe4 | 1061 | dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM; |
9bbf5660 | 1062 | dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len; |
2f7ca802 SG |
1063 | return 0; |
1064 | } | |
1065 | ||
1066 | static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf) | |
1067 | { | |
1068 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
1069 | if (pdata) { | |
a475f603 | 1070 | netif_dbg(dev, ifdown, dev->net, "free pdata\n"); |
2f7ca802 SG |
1071 | kfree(pdata); |
1072 | pdata = NULL; | |
1073 | dev->data[0] = 0; | |
1074 | } | |
1075 | } | |
1076 | ||
068bb1a7 | 1077 | static u32 smsc_crc(const u8 *buffer, size_t len, int filter) |
bbd9f9ee | 1078 | { |
068bb1a7 SG |
1079 | u32 crc = bitrev16(crc16(0xFFFF, buffer, len)); |
1080 | return crc << ((filter % 2) * 16); | |
bbd9f9ee SG |
1081 | } |
1082 | ||
e5e3af83 SG |
1083 | static int smsc95xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask) |
1084 | { | |
1085 | struct mii_if_info *mii = &dev->mii; | |
1086 | int ret; | |
1087 | ||
1e1d7412 | 1088 | netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n"); |
e5e3af83 SG |
1089 | |
1090 | /* read to clear */ | |
1091 | ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC); | |
1e1d7412 | 1092 | check_warn_return(ret, "Error reading PHY_INT_SRC\n"); |
e5e3af83 SG |
1093 | |
1094 | /* enable interrupt source */ | |
1095 | ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK); | |
1e1d7412 | 1096 | check_warn_return(ret, "Error reading PHY_INT_MASK\n"); |
e5e3af83 SG |
1097 | |
1098 | ret |= mask; | |
1099 | ||
1100 | smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret); | |
1101 | ||
1102 | return 0; | |
1103 | } | |
1104 | ||
1105 | static int smsc95xx_link_ok_nopm(struct usbnet *dev) | |
1106 | { | |
1107 | struct mii_if_info *mii = &dev->mii; | |
1108 | int ret; | |
1109 | ||
1110 | /* first, a dummy read, needed to latch some MII phys */ | |
1111 | ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR); | |
1e1d7412 | 1112 | check_warn_return(ret, "Error reading MII_BMSR\n"); |
e5e3af83 SG |
1113 | |
1114 | ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR); | |
1e1d7412 | 1115 | check_warn_return(ret, "Error reading MII_BMSR\n"); |
e5e3af83 SG |
1116 | |
1117 | return !!(ret & BMSR_LSTATUS); | |
1118 | } | |
1119 | ||
319b95b5 SG |
1120 | static int smsc95xx_enter_suspend0(struct usbnet *dev) |
1121 | { | |
1122 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
1123 | u32 val; | |
1124 | int ret; | |
1125 | ||
1126 | ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); | |
1e1d7412 | 1127 | check_warn_return(ret, "Error reading PM_CTRL\n"); |
319b95b5 SG |
1128 | |
1129 | val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_)); | |
1130 | val |= PM_CTL_SUS_MODE_0; | |
1131 | ||
1132 | ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); | |
1e1d7412 | 1133 | check_warn_return(ret, "Error writing PM_CTRL\n"); |
319b95b5 SG |
1134 | |
1135 | /* clear wol status */ | |
1136 | val &= ~PM_CTL_WUPS_; | |
1137 | val |= PM_CTL_WUPS_WOL_; | |
1138 | ||
1139 | /* enable energy detection */ | |
1140 | if (pdata->wolopts & WAKE_PHY) | |
1141 | val |= PM_CTL_WUPS_ED_; | |
1142 | ||
1143 | ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); | |
1e1d7412 | 1144 | check_warn_return(ret, "Error writing PM_CTRL\n"); |
319b95b5 SG |
1145 | |
1146 | /* read back PM_CTRL */ | |
1147 | ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); | |
1e1d7412 | 1148 | check_warn_return(ret, "Error reading PM_CTRL\n"); |
319b95b5 | 1149 | |
319b95b5 SG |
1150 | return 0; |
1151 | } | |
1152 | ||
1153 | static int smsc95xx_enter_suspend1(struct usbnet *dev) | |
1154 | { | |
1155 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
1156 | struct mii_if_info *mii = &dev->mii; | |
1157 | u32 val; | |
1158 | int ret; | |
1159 | ||
1160 | /* reconfigure link pulse detection timing for | |
1161 | * compatibility with non-standard link partners | |
1162 | */ | |
1163 | if (pdata->features & FEATURE_PHY_NLP_CROSSOVER) | |
1164 | smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_EDPD_CONFIG, | |
1165 | PHY_EDPD_CONFIG_DEFAULT); | |
1166 | ||
1167 | /* enable energy detect power-down mode */ | |
1168 | ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_MODE_CTRL_STS); | |
1e1d7412 | 1169 | check_warn_return(ret, "Error reading PHY_MODE_CTRL_STS\n"); |
319b95b5 SG |
1170 | |
1171 | ret |= MODE_CTRL_STS_EDPWRDOWN_; | |
1172 | ||
1173 | smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_MODE_CTRL_STS, ret); | |
1174 | ||
1175 | /* enter SUSPEND1 mode */ | |
1176 | ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); | |
1e1d7412 | 1177 | check_warn_return(ret, "Error reading PM_CTRL\n"); |
319b95b5 SG |
1178 | |
1179 | val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_); | |
1180 | val |= PM_CTL_SUS_MODE_1; | |
1181 | ||
1182 | ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); | |
1e1d7412 | 1183 | check_warn_return(ret, "Error writing PM_CTRL\n"); |
319b95b5 SG |
1184 | |
1185 | /* clear wol status, enable energy detection */ | |
1186 | val &= ~PM_CTL_WUPS_; | |
1187 | val |= (PM_CTL_WUPS_ED_ | PM_CTL_ED_EN_); | |
1188 | ||
1189 | ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); | |
1e1d7412 | 1190 | check_warn_return(ret, "Error writing PM_CTRL\n"); |
319b95b5 | 1191 | |
319b95b5 SG |
1192 | return 0; |
1193 | } | |
1194 | ||
1195 | static int smsc95xx_enter_suspend2(struct usbnet *dev) | |
1196 | { | |
1197 | u32 val; | |
1198 | int ret; | |
1199 | ||
1200 | ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); | |
1e1d7412 | 1201 | check_warn_return(ret, "Error reading PM_CTRL\n"); |
319b95b5 SG |
1202 | |
1203 | val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_); | |
1204 | val |= PM_CTL_SUS_MODE_2; | |
1205 | ||
1206 | ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); | |
1e1d7412 | 1207 | check_warn_return(ret, "Error writing PM_CTRL\n"); |
319b95b5 SG |
1208 | |
1209 | return 0; | |
1210 | } | |
1211 | ||
b5a04475 SG |
1212 | static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message) |
1213 | { | |
1214 | struct usbnet *dev = usb_get_intfdata(intf); | |
e0e474a8 | 1215 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); |
e5e3af83 | 1216 | u32 val, link_up; |
b5a04475 | 1217 | int ret; |
b5a04475 | 1218 | |
b5a04475 | 1219 | ret = usbnet_suspend(intf, message); |
1e1d7412 | 1220 | check_warn_return(ret, "usbnet_suspend error\n"); |
b5a04475 | 1221 | |
e5e3af83 SG |
1222 | /* determine if link is up using only _nopm functions */ |
1223 | link_up = smsc95xx_link_ok_nopm(dev); | |
1224 | ||
1225 | /* if no wol options set, or if link is down and we're not waking on | |
1226 | * PHY activity, enter lowest power SUSPEND2 mode | |
1227 | */ | |
1228 | if (!(pdata->wolopts & SUPPORTED_WAKE) || | |
1229 | !(link_up || (pdata->wolopts & WAKE_PHY))) { | |
1e1d7412 | 1230 | netdev_info(dev->net, "entering SUSPEND2 mode\n"); |
e0e474a8 SG |
1231 | |
1232 | /* disable energy detect (link up) & wake up events */ | |
ec32115d | 1233 | ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); |
3b9f7d8c | 1234 | check_warn_goto_done(ret, "Error reading WUCSR\n"); |
e0e474a8 SG |
1235 | |
1236 | val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_); | |
1237 | ||
ec32115d | 1238 | ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); |
3b9f7d8c | 1239 | check_warn_goto_done(ret, "Error writing WUCSR\n"); |
e0e474a8 | 1240 | |
ec32115d | 1241 | ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); |
3b9f7d8c | 1242 | check_warn_goto_done(ret, "Error reading PM_CTRL\n"); |
e0e474a8 SG |
1243 | |
1244 | val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_); | |
1245 | ||
ec32115d | 1246 | ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); |
3b9f7d8c | 1247 | check_warn_goto_done(ret, "Error writing PM_CTRL\n"); |
e0e474a8 | 1248 | |
3b9f7d8c SG |
1249 | ret = smsc95xx_enter_suspend2(dev); |
1250 | goto done; | |
e0e474a8 SG |
1251 | } |
1252 | ||
e5e3af83 SG |
1253 | if (pdata->wolopts & WAKE_PHY) { |
1254 | ret = smsc95xx_enable_phy_wakeup_interrupts(dev, | |
1255 | (PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_LINK_DOWN_)); | |
3b9f7d8c | 1256 | check_warn_goto_done(ret, "error enabling PHY wakeup ints\n"); |
e5e3af83 SG |
1257 | |
1258 | /* if link is down then configure EDPD and enter SUSPEND1, | |
1259 | * otherwise enter SUSPEND0 below | |
1260 | */ | |
1261 | if (!link_up) { | |
1e1d7412 | 1262 | netdev_info(dev->net, "entering SUSPEND1 mode\n"); |
3b9f7d8c SG |
1263 | ret = smsc95xx_enter_suspend1(dev); |
1264 | goto done; | |
e5e3af83 SG |
1265 | } |
1266 | } | |
1267 | ||
bbd9f9ee | 1268 | if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) { |
eed9a729 | 1269 | u32 *filter_mask = kzalloc(sizeof(u32) * 32, GFP_KERNEL); |
06a221be ML |
1270 | u32 command[2]; |
1271 | u32 offset[2]; | |
1272 | u32 crc[4]; | |
9ebca507 SG |
1273 | int wuff_filter_count = |
1274 | (pdata->features & FEATURE_8_WAKEUP_FILTERS) ? | |
1275 | LAN9500A_WUFF_NUM : LAN9500_WUFF_NUM; | |
bbd9f9ee SG |
1276 | int i, filter = 0; |
1277 | ||
eed9a729 SG |
1278 | if (!filter_mask) { |
1279 | netdev_warn(dev->net, "Unable to allocate filter_mask\n"); | |
3b9f7d8c SG |
1280 | ret = -ENOMEM; |
1281 | goto done; | |
eed9a729 SG |
1282 | } |
1283 | ||
06a221be ML |
1284 | memset(command, 0, sizeof(command)); |
1285 | memset(offset, 0, sizeof(offset)); | |
1286 | memset(crc, 0, sizeof(crc)); | |
1287 | ||
bbd9f9ee SG |
1288 | if (pdata->wolopts & WAKE_BCAST) { |
1289 | const u8 bcast[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; | |
1e1d7412 | 1290 | netdev_info(dev->net, "enabling broadcast detection\n"); |
bbd9f9ee SG |
1291 | filter_mask[filter * 4] = 0x003F; |
1292 | filter_mask[filter * 4 + 1] = 0x00; | |
1293 | filter_mask[filter * 4 + 2] = 0x00; | |
1294 | filter_mask[filter * 4 + 3] = 0x00; | |
1295 | command[filter/4] |= 0x05UL << ((filter % 4) * 8); | |
1296 | offset[filter/4] |= 0x00 << ((filter % 4) * 8); | |
1297 | crc[filter/2] |= smsc_crc(bcast, 6, filter); | |
1298 | filter++; | |
1299 | } | |
1300 | ||
1301 | if (pdata->wolopts & WAKE_MCAST) { | |
1302 | const u8 mcast[] = {0x01, 0x00, 0x5E}; | |
1e1d7412 | 1303 | netdev_info(dev->net, "enabling multicast detection\n"); |
bbd9f9ee SG |
1304 | filter_mask[filter * 4] = 0x0007; |
1305 | filter_mask[filter * 4 + 1] = 0x00; | |
1306 | filter_mask[filter * 4 + 2] = 0x00; | |
1307 | filter_mask[filter * 4 + 3] = 0x00; | |
1308 | command[filter/4] |= 0x09UL << ((filter % 4) * 8); | |
1309 | offset[filter/4] |= 0x00 << ((filter % 4) * 8); | |
1310 | crc[filter/2] |= smsc_crc(mcast, 3, filter); | |
1311 | filter++; | |
1312 | } | |
1313 | ||
1314 | if (pdata->wolopts & WAKE_ARP) { | |
1315 | const u8 arp[] = {0x08, 0x06}; | |
1e1d7412 | 1316 | netdev_info(dev->net, "enabling ARP detection\n"); |
bbd9f9ee SG |
1317 | filter_mask[filter * 4] = 0x0003; |
1318 | filter_mask[filter * 4 + 1] = 0x00; | |
1319 | filter_mask[filter * 4 + 2] = 0x00; | |
1320 | filter_mask[filter * 4 + 3] = 0x00; | |
1321 | command[filter/4] |= 0x05UL << ((filter % 4) * 8); | |
1322 | offset[filter/4] |= 0x0C << ((filter % 4) * 8); | |
1323 | crc[filter/2] |= smsc_crc(arp, 2, filter); | |
1324 | filter++; | |
1325 | } | |
1326 | ||
1327 | if (pdata->wolopts & WAKE_UCAST) { | |
1e1d7412 | 1328 | netdev_info(dev->net, "enabling unicast detection\n"); |
bbd9f9ee SG |
1329 | filter_mask[filter * 4] = 0x003F; |
1330 | filter_mask[filter * 4 + 1] = 0x00; | |
1331 | filter_mask[filter * 4 + 2] = 0x00; | |
1332 | filter_mask[filter * 4 + 3] = 0x00; | |
1333 | command[filter/4] |= 0x01UL << ((filter % 4) * 8); | |
1334 | offset[filter/4] |= 0x00 << ((filter % 4) * 8); | |
1335 | crc[filter/2] |= smsc_crc(dev->net->dev_addr, ETH_ALEN, filter); | |
1336 | filter++; | |
1337 | } | |
1338 | ||
9ebca507 | 1339 | for (i = 0; i < (wuff_filter_count * 4); i++) { |
ec32115d | 1340 | ret = smsc95xx_write_reg_nopm(dev, WUFF, filter_mask[i]); |
06a221be ML |
1341 | if (ret < 0) |
1342 | kfree(filter_mask); | |
3b9f7d8c | 1343 | check_warn_goto_done(ret, "Error writing WUFF\n"); |
bbd9f9ee | 1344 | } |
06a221be | 1345 | kfree(filter_mask); |
bbd9f9ee | 1346 | |
9ebca507 | 1347 | for (i = 0; i < (wuff_filter_count / 4); i++) { |
ec32115d | 1348 | ret = smsc95xx_write_reg_nopm(dev, WUFF, command[i]); |
3b9f7d8c | 1349 | check_warn_goto_done(ret, "Error writing WUFF\n"); |
bbd9f9ee SG |
1350 | } |
1351 | ||
9ebca507 | 1352 | for (i = 0; i < (wuff_filter_count / 4); i++) { |
ec32115d | 1353 | ret = smsc95xx_write_reg_nopm(dev, WUFF, offset[i]); |
3b9f7d8c | 1354 | check_warn_goto_done(ret, "Error writing WUFF\n"); |
bbd9f9ee SG |
1355 | } |
1356 | ||
9ebca507 | 1357 | for (i = 0; i < (wuff_filter_count / 2); i++) { |
ec32115d | 1358 | ret = smsc95xx_write_reg_nopm(dev, WUFF, crc[i]); |
3b9f7d8c | 1359 | check_warn_goto_done(ret, "Error writing WUFF\n"); |
bbd9f9ee SG |
1360 | } |
1361 | ||
1362 | /* clear any pending pattern match packet status */ | |
ec32115d | 1363 | ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); |
3b9f7d8c | 1364 | check_warn_goto_done(ret, "Error reading WUCSR\n"); |
bbd9f9ee SG |
1365 | |
1366 | val |= WUCSR_WUFR_; | |
1367 | ||
ec32115d | 1368 | ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); |
3b9f7d8c | 1369 | check_warn_goto_done(ret, "Error writing WUCSR\n"); |
bbd9f9ee SG |
1370 | } |
1371 | ||
e0e474a8 SG |
1372 | if (pdata->wolopts & WAKE_MAGIC) { |
1373 | /* clear any pending magic packet status */ | |
ec32115d | 1374 | ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); |
3b9f7d8c | 1375 | check_warn_goto_done(ret, "Error reading WUCSR\n"); |
e0e474a8 SG |
1376 | |
1377 | val |= WUCSR_MPR_; | |
1378 | ||
ec32115d | 1379 | ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); |
3b9f7d8c | 1380 | check_warn_goto_done(ret, "Error writing WUCSR\n"); |
e0e474a8 SG |
1381 | } |
1382 | ||
bbd9f9ee | 1383 | /* enable/disable wakeup sources */ |
ec32115d | 1384 | ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); |
3b9f7d8c | 1385 | check_warn_goto_done(ret, "Error reading WUCSR\n"); |
e0e474a8 | 1386 | |
bbd9f9ee | 1387 | if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) { |
1e1d7412 | 1388 | netdev_info(dev->net, "enabling pattern match wakeup\n"); |
bbd9f9ee SG |
1389 | val |= WUCSR_WAKE_EN_; |
1390 | } else { | |
1e1d7412 | 1391 | netdev_info(dev->net, "disabling pattern match wakeup\n"); |
bbd9f9ee SG |
1392 | val &= ~WUCSR_WAKE_EN_; |
1393 | } | |
1394 | ||
e0e474a8 | 1395 | if (pdata->wolopts & WAKE_MAGIC) { |
1e1d7412 | 1396 | netdev_info(dev->net, "enabling magic packet wakeup\n"); |
e0e474a8 SG |
1397 | val |= WUCSR_MPEN_; |
1398 | } else { | |
1e1d7412 | 1399 | netdev_info(dev->net, "disabling magic packet wakeup\n"); |
e0e474a8 SG |
1400 | val &= ~WUCSR_MPEN_; |
1401 | } | |
1402 | ||
ec32115d | 1403 | ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); |
3b9f7d8c | 1404 | check_warn_goto_done(ret, "Error writing WUCSR\n"); |
e0e474a8 SG |
1405 | |
1406 | /* enable wol wakeup source */ | |
ec32115d | 1407 | ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); |
3b9f7d8c | 1408 | check_warn_goto_done(ret, "Error reading PM_CTRL\n"); |
e0e474a8 SG |
1409 | |
1410 | val |= PM_CTL_WOL_EN_; | |
1411 | ||
e5e3af83 SG |
1412 | /* phy energy detect wakeup source */ |
1413 | if (pdata->wolopts & WAKE_PHY) | |
1414 | val |= PM_CTL_ED_EN_; | |
1415 | ||
ec32115d | 1416 | ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); |
3b9f7d8c | 1417 | check_warn_goto_done(ret, "Error writing PM_CTRL\n"); |
e0e474a8 | 1418 | |
bbd9f9ee | 1419 | /* enable receiver to enable frame reception */ |
ec32115d | 1420 | smsc95xx_start_rx_path(dev, 1); |
e0e474a8 SG |
1421 | |
1422 | /* some wol options are enabled, so enter SUSPEND0 */ | |
1e1d7412 | 1423 | netdev_info(dev->net, "entering SUSPEND0 mode\n"); |
3b9f7d8c SG |
1424 | ret = smsc95xx_enter_suspend0(dev); |
1425 | ||
1426 | done: | |
1427 | if (ret) | |
1428 | usbnet_resume(intf); | |
1429 | return ret; | |
e0e474a8 SG |
1430 | } |
1431 | ||
1432 | static int smsc95xx_resume(struct usb_interface *intf) | |
1433 | { | |
1434 | struct usbnet *dev = usb_get_intfdata(intf); | |
1435 | struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); | |
1436 | int ret; | |
1437 | u32 val; | |
1438 | ||
1439 | BUG_ON(!dev); | |
1440 | ||
bbd9f9ee | 1441 | if (pdata->wolopts) { |
bbd9f9ee | 1442 | /* clear wake-up sources */ |
ec32115d | 1443 | ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); |
1e1d7412 | 1444 | check_warn_return(ret, "Error reading WUCSR\n"); |
e0e474a8 | 1445 | |
bbd9f9ee | 1446 | val &= ~(WUCSR_WAKE_EN_ | WUCSR_MPEN_); |
e0e474a8 | 1447 | |
ec32115d | 1448 | ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); |
1e1d7412 | 1449 | check_warn_return(ret, "Error writing WUCSR\n"); |
e0e474a8 SG |
1450 | |
1451 | /* clear wake-up status */ | |
ec32115d | 1452 | ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); |
1e1d7412 | 1453 | check_warn_return(ret, "Error reading PM_CTRL\n"); |
e0e474a8 SG |
1454 | |
1455 | val &= ~PM_CTL_WOL_EN_; | |
1456 | val |= PM_CTL_WUPS_; | |
1457 | ||
ec32115d | 1458 | ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); |
1e1d7412 | 1459 | check_warn_return(ret, "Error writing PM_CTRL\n"); |
e0e474a8 SG |
1460 | } |
1461 | ||
af3d7c1e | 1462 | ret = usbnet_resume(intf); |
1e1d7412 | 1463 | check_warn_return(ret, "usbnet_resume error\n"); |
e0e474a8 | 1464 | |
b5a04475 SG |
1465 | return 0; |
1466 | } | |
1467 | ||
2f7ca802 SG |
1468 | static void smsc95xx_rx_csum_offload(struct sk_buff *skb) |
1469 | { | |
1470 | skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2); | |
1471 | skb->ip_summed = CHECKSUM_COMPLETE; | |
1472 | skb_trim(skb, skb->len - 2); | |
1473 | } | |
1474 | ||
1475 | static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) | |
1476 | { | |
2f7ca802 SG |
1477 | while (skb->len > 0) { |
1478 | u32 header, align_count; | |
1479 | struct sk_buff *ax_skb; | |
1480 | unsigned char *packet; | |
1481 | u16 size; | |
1482 | ||
1483 | memcpy(&header, skb->data, sizeof(header)); | |
1484 | le32_to_cpus(&header); | |
1485 | skb_pull(skb, 4 + NET_IP_ALIGN); | |
1486 | packet = skb->data; | |
1487 | ||
1488 | /* get the packet length */ | |
1489 | size = (u16)((header & RX_STS_FL_) >> 16); | |
1490 | align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4; | |
1491 | ||
1492 | if (unlikely(header & RX_STS_ES_)) { | |
a475f603 JP |
1493 | netif_dbg(dev, rx_err, dev->net, |
1494 | "Error header=0x%08x\n", header); | |
80667ac1 HX |
1495 | dev->net->stats.rx_errors++; |
1496 | dev->net->stats.rx_dropped++; | |
2f7ca802 SG |
1497 | |
1498 | if (header & RX_STS_CRC_) { | |
80667ac1 | 1499 | dev->net->stats.rx_crc_errors++; |
2f7ca802 SG |
1500 | } else { |
1501 | if (header & (RX_STS_TL_ | RX_STS_RF_)) | |
80667ac1 | 1502 | dev->net->stats.rx_frame_errors++; |
2f7ca802 SG |
1503 | |
1504 | if ((header & RX_STS_LE_) && | |
1505 | (!(header & RX_STS_FT_))) | |
80667ac1 | 1506 | dev->net->stats.rx_length_errors++; |
2f7ca802 SG |
1507 | } |
1508 | } else { | |
1509 | /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */ | |
1510 | if (unlikely(size > (ETH_FRAME_LEN + 12))) { | |
a475f603 JP |
1511 | netif_dbg(dev, rx_err, dev->net, |
1512 | "size err header=0x%08x\n", header); | |
2f7ca802 SG |
1513 | return 0; |
1514 | } | |
1515 | ||
1516 | /* last frame in this batch */ | |
1517 | if (skb->len == size) { | |
78e47fe4 | 1518 | if (dev->net->features & NETIF_F_RXCSUM) |
2f7ca802 | 1519 | smsc95xx_rx_csum_offload(skb); |
df18acca | 1520 | skb_trim(skb, skb->len - 4); /* remove fcs */ |
2f7ca802 SG |
1521 | skb->truesize = size + sizeof(struct sk_buff); |
1522 | ||
1523 | return 1; | |
1524 | } | |
1525 | ||
1526 | ax_skb = skb_clone(skb, GFP_ATOMIC); | |
1527 | if (unlikely(!ax_skb)) { | |
60b86755 | 1528 | netdev_warn(dev->net, "Error allocating skb\n"); |
2f7ca802 SG |
1529 | return 0; |
1530 | } | |
1531 | ||
1532 | ax_skb->len = size; | |
1533 | ax_skb->data = packet; | |
1534 | skb_set_tail_pointer(ax_skb, size); | |
1535 | ||
78e47fe4 | 1536 | if (dev->net->features & NETIF_F_RXCSUM) |
2f7ca802 | 1537 | smsc95xx_rx_csum_offload(ax_skb); |
df18acca | 1538 | skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */ |
2f7ca802 SG |
1539 | ax_skb->truesize = size + sizeof(struct sk_buff); |
1540 | ||
1541 | usbnet_skb_return(dev, ax_skb); | |
1542 | } | |
1543 | ||
1544 | skb_pull(skb, size); | |
1545 | ||
1546 | /* padding bytes before the next frame starts */ | |
1547 | if (skb->len) | |
1548 | skb_pull(skb, align_count); | |
1549 | } | |
1550 | ||
1551 | if (unlikely(skb->len < 0)) { | |
60b86755 | 1552 | netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len); |
2f7ca802 SG |
1553 | return 0; |
1554 | } | |
1555 | ||
1556 | return 1; | |
1557 | } | |
1558 | ||
f7b29271 SG |
1559 | static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb) |
1560 | { | |
55508d60 MM |
1561 | u16 low_16 = (u16)skb_checksum_start_offset(skb); |
1562 | u16 high_16 = low_16 + skb->csum_offset; | |
f7b29271 SG |
1563 | return (high_16 << 16) | low_16; |
1564 | } | |
1565 | ||
2f7ca802 SG |
1566 | static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev, |
1567 | struct sk_buff *skb, gfp_t flags) | |
1568 | { | |
78e47fe4 | 1569 | bool csum = skb->ip_summed == CHECKSUM_PARTIAL; |
f7b29271 | 1570 | int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD; |
2f7ca802 SG |
1571 | u32 tx_cmd_a, tx_cmd_b; |
1572 | ||
f7b29271 SG |
1573 | /* We do not advertise SG, so skbs should be already linearized */ |
1574 | BUG_ON(skb_shinfo(skb)->nr_frags); | |
1575 | ||
1576 | if (skb_headroom(skb) < overhead) { | |
2f7ca802 | 1577 | struct sk_buff *skb2 = skb_copy_expand(skb, |
f7b29271 | 1578 | overhead, 0, flags); |
2f7ca802 SG |
1579 | dev_kfree_skb_any(skb); |
1580 | skb = skb2; | |
1581 | if (!skb) | |
1582 | return NULL; | |
1583 | } | |
1584 | ||
f7b29271 | 1585 | if (csum) { |
11bc3088 SG |
1586 | if (skb->len <= 45) { |
1587 | /* workaround - hardware tx checksum does not work | |
1588 | * properly with extremely small packets */ | |
55508d60 | 1589 | long csstart = skb_checksum_start_offset(skb); |
11bc3088 SG |
1590 | __wsum calc = csum_partial(skb->data + csstart, |
1591 | skb->len - csstart, 0); | |
1592 | *((__sum16 *)(skb->data + csstart | |
1593 | + skb->csum_offset)) = csum_fold(calc); | |
1594 | ||
1595 | csum = false; | |
1596 | } else { | |
1597 | u32 csum_preamble = smsc95xx_calc_csum_preamble(skb); | |
1598 | skb_push(skb, 4); | |
00acda68 | 1599 | cpu_to_le32s(&csum_preamble); |
11bc3088 SG |
1600 | memcpy(skb->data, &csum_preamble, 4); |
1601 | } | |
f7b29271 SG |
1602 | } |
1603 | ||
2f7ca802 SG |
1604 | skb_push(skb, 4); |
1605 | tx_cmd_b = (u32)(skb->len - 4); | |
f7b29271 SG |
1606 | if (csum) |
1607 | tx_cmd_b |= TX_CMD_B_CSUM_ENABLE; | |
2f7ca802 SG |
1608 | cpu_to_le32s(&tx_cmd_b); |
1609 | memcpy(skb->data, &tx_cmd_b, 4); | |
1610 | ||
1611 | skb_push(skb, 4); | |
1612 | tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ | | |
1613 | TX_CMD_A_LAST_SEG_; | |
1614 | cpu_to_le32s(&tx_cmd_a); | |
1615 | memcpy(skb->data, &tx_cmd_a, 4); | |
1616 | ||
1617 | return skb; | |
1618 | } | |
1619 | ||
1620 | static const struct driver_info smsc95xx_info = { | |
1621 | .description = "smsc95xx USB 2.0 Ethernet", | |
1622 | .bind = smsc95xx_bind, | |
1623 | .unbind = smsc95xx_unbind, | |
1624 | .link_reset = smsc95xx_link_reset, | |
1625 | .reset = smsc95xx_reset, | |
1626 | .rx_fixup = smsc95xx_rx_fixup, | |
1627 | .tx_fixup = smsc95xx_tx_fixup, | |
1628 | .status = smsc95xx_status, | |
07d69d42 | 1629 | .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR, |
2f7ca802 SG |
1630 | }; |
1631 | ||
1632 | static const struct usb_device_id products[] = { | |
1633 | { | |
1634 | /* SMSC9500 USB Ethernet Device */ | |
1635 | USB_DEVICE(0x0424, 0x9500), | |
1636 | .driver_info = (unsigned long) &smsc95xx_info, | |
1637 | }, | |
6f41d12b SG |
1638 | { |
1639 | /* SMSC9505 USB Ethernet Device */ | |
1640 | USB_DEVICE(0x0424, 0x9505), | |
1641 | .driver_info = (unsigned long) &smsc95xx_info, | |
1642 | }, | |
1643 | { | |
1644 | /* SMSC9500A USB Ethernet Device */ | |
1645 | USB_DEVICE(0x0424, 0x9E00), | |
1646 | .driver_info = (unsigned long) &smsc95xx_info, | |
1647 | }, | |
1648 | { | |
1649 | /* SMSC9505A USB Ethernet Device */ | |
1650 | USB_DEVICE(0x0424, 0x9E01), | |
1651 | .driver_info = (unsigned long) &smsc95xx_info, | |
1652 | }, | |
726474b8 SG |
1653 | { |
1654 | /* SMSC9512/9514 USB Hub & Ethernet Device */ | |
1655 | USB_DEVICE(0x0424, 0xec00), | |
1656 | .driver_info = (unsigned long) &smsc95xx_info, | |
1657 | }, | |
6f41d12b SG |
1658 | { |
1659 | /* SMSC9500 USB Ethernet Device (SAL10) */ | |
1660 | USB_DEVICE(0x0424, 0x9900), | |
1661 | .driver_info = (unsigned long) &smsc95xx_info, | |
1662 | }, | |
1663 | { | |
1664 | /* SMSC9505 USB Ethernet Device (SAL10) */ | |
1665 | USB_DEVICE(0x0424, 0x9901), | |
1666 | .driver_info = (unsigned long) &smsc95xx_info, | |
1667 | }, | |
1668 | { | |
1669 | /* SMSC9500A USB Ethernet Device (SAL10) */ | |
1670 | USB_DEVICE(0x0424, 0x9902), | |
1671 | .driver_info = (unsigned long) &smsc95xx_info, | |
1672 | }, | |
1673 | { | |
1674 | /* SMSC9505A USB Ethernet Device (SAL10) */ | |
1675 | USB_DEVICE(0x0424, 0x9903), | |
1676 | .driver_info = (unsigned long) &smsc95xx_info, | |
1677 | }, | |
1678 | { | |
1679 | /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */ | |
1680 | USB_DEVICE(0x0424, 0x9904), | |
1681 | .driver_info = (unsigned long) &smsc95xx_info, | |
1682 | }, | |
1683 | { | |
1684 | /* SMSC9500A USB Ethernet Device (HAL) */ | |
1685 | USB_DEVICE(0x0424, 0x9905), | |
1686 | .driver_info = (unsigned long) &smsc95xx_info, | |
1687 | }, | |
1688 | { | |
1689 | /* SMSC9505A USB Ethernet Device (HAL) */ | |
1690 | USB_DEVICE(0x0424, 0x9906), | |
1691 | .driver_info = (unsigned long) &smsc95xx_info, | |
1692 | }, | |
1693 | { | |
1694 | /* SMSC9500 USB Ethernet Device (Alternate ID) */ | |
1695 | USB_DEVICE(0x0424, 0x9907), | |
1696 | .driver_info = (unsigned long) &smsc95xx_info, | |
1697 | }, | |
1698 | { | |
1699 | /* SMSC9500A USB Ethernet Device (Alternate ID) */ | |
1700 | USB_DEVICE(0x0424, 0x9908), | |
1701 | .driver_info = (unsigned long) &smsc95xx_info, | |
1702 | }, | |
1703 | { | |
1704 | /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */ | |
1705 | USB_DEVICE(0x0424, 0x9909), | |
1706 | .driver_info = (unsigned long) &smsc95xx_info, | |
1707 | }, | |
88edaa41 SG |
1708 | { |
1709 | /* SMSC LAN9530 USB Ethernet Device */ | |
1710 | USB_DEVICE(0x0424, 0x9530), | |
1711 | .driver_info = (unsigned long) &smsc95xx_info, | |
1712 | }, | |
1713 | { | |
1714 | /* SMSC LAN9730 USB Ethernet Device */ | |
1715 | USB_DEVICE(0x0424, 0x9730), | |
1716 | .driver_info = (unsigned long) &smsc95xx_info, | |
1717 | }, | |
1718 | { | |
1719 | /* SMSC LAN89530 USB Ethernet Device */ | |
1720 | USB_DEVICE(0x0424, 0x9E08), | |
1721 | .driver_info = (unsigned long) &smsc95xx_info, | |
1722 | }, | |
2f7ca802 SG |
1723 | { }, /* END */ |
1724 | }; | |
1725 | MODULE_DEVICE_TABLE(usb, products); | |
1726 | ||
1727 | static struct usb_driver smsc95xx_driver = { | |
1728 | .name = "smsc95xx", | |
1729 | .id_table = products, | |
1730 | .probe = usbnet_probe, | |
b5a04475 | 1731 | .suspend = smsc95xx_suspend, |
e0e474a8 SG |
1732 | .resume = smsc95xx_resume, |
1733 | .reset_resume = smsc95xx_resume, | |
2f7ca802 | 1734 | .disconnect = usbnet_disconnect, |
e1f12eb6 | 1735 | .disable_hub_initiated_lpm = 1, |
2f7ca802 SG |
1736 | }; |
1737 | ||
d632eb1b | 1738 | module_usb_driver(smsc95xx_driver); |
2f7ca802 SG |
1739 | |
1740 | MODULE_AUTHOR("Nancy Lin"); | |
90b24cfb | 1741 | MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>"); |
2f7ca802 SG |
1742 | MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices"); |
1743 | MODULE_LICENSE("GPL"); |