Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ac718b69 | 2 | /* |
c7de7dec | 3 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 4 | */ |
5 | ||
ac718b69 | 6 | #include <linux/signal.h> |
7 | #include <linux/slab.h> | |
8 | #include <linux/module.h> | |
ac718b69 | 9 | #include <linux/netdevice.h> |
10 | #include <linux/etherdevice.h> | |
11 | #include <linux/mii.h> | |
12 | #include <linux/ethtool.h> | |
13 | #include <linux/usb.h> | |
14 | #include <linux/crc32.h> | |
15 | #include <linux/if_vlan.h> | |
16 | #include <linux/uaccess.h> | |
ebc2ec48 | 17 | #include <linux/list.h> |
5bd23881 | 18 | #include <linux/ip.h> |
19 | #include <linux/ipv6.h> | |
6128d1bb | 20 | #include <net/ip6_checksum.h> |
4c4a6b1b | 21 | #include <uapi/linux/mdio.h> |
22 | #include <linux/mdio.h> | |
d9a28c5b | 23 | #include <linux/usb/cdc.h> |
5ee3c60c | 24 | #include <linux/suspend.h> |
252df8b8 | 25 | #include <linux/atomic.h> |
34ee32c9 | 26 | #include <linux/acpi.h> |
9370f2d0 HW |
27 | #include <linux/firmware.h> |
28 | #include <crypto/hash.h> | |
c1aedf01 | 29 | #include <linux/usb/r8152.h> |
ac718b69 | 30 | |
d0942473 | 31 | /* Information for net-next */ |
c2198943 | 32 | #define NETNEXT_VERSION "12" |
d0942473 | 33 | |
34 | /* Information for net */ | |
cdf0b86b | 35 | #define NET_VERSION "13" |
d0942473 | 36 | |
37 | #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION | |
ac718b69 | 38 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 39 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 40 | #define MODULENAME "r8152" |
41 | ||
42 | #define R8152_PHY_ID 32 | |
43 | ||
44 | #define PLA_IDR 0xc000 | |
45 | #define PLA_RCR 0xc010 | |
195aae32 | 46 | #define PLA_RCR1 0xc012 |
ac718b69 | 47 | #define PLA_RMS 0xc016 |
48 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
195aae32 | 49 | #define PLA_RXFIFO_FULL 0xc0a2 |
ac718b69 | 50 | #define PLA_RXFIFO_CTRL1 0xc0a4 |
195aae32 | 51 | #define PLA_RX_FIFO_FULL 0xc0a6 |
ac718b69 | 52 | #define PLA_RXFIFO_CTRL2 0xc0a8 |
195aae32 | 53 | #define PLA_RX_FIFO_EMPTY 0xc0aa |
65bab84c | 54 | #define PLA_DMY_REG0 0xc0b0 |
ac718b69 | 55 | #define PLA_FMC 0xc0b4 |
56 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 57 | #define PLA_TEREDO_CFG 0xc0bc |
65b82d69 | 58 | #define PLA_TEREDO_WAKE_BASE 0xc0c4 |
ac718b69 | 59 | #define PLA_MAR 0xcd00 |
43779f8d | 60 | #define PLA_BACKUP 0xd000 |
59c0b47a | 61 | #define PLA_BDC_CR 0xd1a0 |
43779f8d | 62 | #define PLA_TEREDO_TIMER 0xd2cc |
63 | #define PLA_REALWOW_TIMER 0xd2e8 | |
9370f2d0 | 64 | #define PLA_UPHY_TIMER 0xd388 |
13e04fbf HW |
65 | #define PLA_SUSPEND_FLAG 0xd38a |
66 | #define PLA_INDICATE_FALG 0xd38c | |
9370f2d0 HW |
67 | #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */ |
68 | #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */ | |
13e04fbf | 69 | #define PLA_EXTRA_STATUS 0xd398 |
195aae32 HW |
70 | #define PLA_GPHY_CTRL 0xd3ae |
71 | #define PLA_POL_GPIO_CTRL 0xdc6a | |
65b82d69 | 72 | #define PLA_EFUSE_DATA 0xdd00 |
73 | #define PLA_EFUSE_CMD 0xdd02 | |
ac718b69 | 74 | #define PLA_LEDSEL 0xdd90 |
75 | #define PLA_LED_FEATURE 0xdd92 | |
76 | #define PLA_PHYAR 0xde00 | |
43779f8d | 77 | #define PLA_BOOT_CTRL 0xe004 |
19813162 | 78 | #define PLA_LWAKE_CTRL_REG 0xe007 |
ac718b69 | 79 | #define PLA_GPHY_INTR_IMR 0xe022 |
80 | #define PLA_EEE_CR 0xe040 | |
195aae32 HW |
81 | #define PLA_EEE_TXTWSYS 0xe04c |
82 | #define PLA_EEE_TXTWSYS_2P5G 0xe058 | |
ac718b69 | 83 | #define PLA_EEEP_CR 0xe080 |
84 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 85 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
86 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
87 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
88 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 89 | #define PLA_TCR0 0xe610 |
90 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 91 | #define PLA_MTPS 0xe615 |
ac718b69 | 92 | #define PLA_TXFIFO_CTRL 0xe618 |
195aae32 | 93 | #define PLA_TXFIFO_FULL 0xe61a |
4f1d4d54 | 94 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 95 | #define PLA_CR 0xe813 |
96 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 97 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
98 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 99 | #define PLA_CONFIG5 0xe822 |
100 | #define PLA_PHY_PWR 0xe84c | |
101 | #define PLA_OOB_CTRL 0xe84f | |
102 | #define PLA_CPCR 0xe854 | |
103 | #define PLA_MISC_0 0xe858 | |
104 | #define PLA_MISC_1 0xe85a | |
105 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 106 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 107 | #define PLA_SFF_STS_7 0xe8de |
108 | #define PLA_PHYSTATUS 0xe908 | |
19813162 | 109 | #define PLA_CONFIG6 0xe90a /* CONFIG6 */ |
195aae32 | 110 | #define PLA_USB_CFG 0xe952 |
ac718b69 | 111 | #define PLA_BP_BA 0xfc26 |
112 | #define PLA_BP_0 0xfc28 | |
113 | #define PLA_BP_1 0xfc2a | |
114 | #define PLA_BP_2 0xfc2c | |
115 | #define PLA_BP_3 0xfc2e | |
116 | #define PLA_BP_4 0xfc30 | |
117 | #define PLA_BP_5 0xfc32 | |
118 | #define PLA_BP_6 0xfc34 | |
119 | #define PLA_BP_7 0xfc36 | |
43779f8d | 120 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 121 | |
65bab84c | 122 | #define USB_USB2PHY 0xb41e |
aa475d93 | 123 | #define USB_SSPHYLINK1 0xb426 |
65bab84c | 124 | #define USB_SSPHYLINK2 0xb428 |
195aae32 | 125 | #define USB_L1_CTRL 0xb45e |
43779f8d | 126 | #define USB_U2P3_CTRL 0xb460 |
65bab84c | 127 | #define USB_CSR_DUMMY1 0xb464 |
128 | #define USB_CSR_DUMMY2 0xb466 | |
ac718b69 | 129 | #define USB_DEV_STAT 0xb808 |
65bab84c | 130 | #define USB_CONNECT_TIMER 0xcbf8 |
65b82d69 | 131 | #define USB_MSC_TIMER 0xcbfc |
65bab84c | 132 | #define USB_BURST_SIZE 0xcfc0 |
9370f2d0 HW |
133 | #define USB_FW_FIX_EN0 0xcfca |
134 | #define USB_FW_FIX_EN1 0xcfcc | |
65b82d69 | 135 | #define USB_LPM_CONFIG 0xcfd8 |
195aae32 | 136 | #define USB_ECM_OPTION 0xcfee |
9370f2d0 | 137 | #define USB_CSTMR 0xcfef /* RTL8153A */ |
195aae32 HW |
138 | #define USB_MISC_2 0xcfff |
139 | #define USB_ECM_OP 0xd26b | |
140 | #define USB_GPHY_CTRL 0xd284 | |
141 | #define USB_SPEED_OPTION 0xd32a | |
9370f2d0 HW |
142 | #define USB_FW_CTRL 0xd334 /* RTL8153B */ |
143 | #define USB_FC_TIMER 0xd340 | |
ac718b69 | 144 | #define USB_USB_CTRL 0xd406 |
145 | #define USB_PHY_CTRL 0xd408 | |
146 | #define USB_TX_AGG 0xd40a | |
147 | #define USB_RX_BUF_TH 0xd40c | |
148 | #define USB_USB_TIMER 0xd428 | |
464ec10a | 149 | #define USB_RX_EARLY_TIMEOUT 0xd42c |
150 | #define USB_RX_EARLY_SIZE 0xd42e | |
65b82d69 | 151 | #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ |
152 | #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ | |
ac718b69 | 153 | #define USB_TX_DMA 0xd434 |
65b82d69 | 154 | #define USB_UPT_RXDMA_OWN 0xd437 |
195aae32 | 155 | #define USB_UPHY3_MDCMDIO 0xd480 |
43779f8d | 156 | #define USB_TOLERANCE 0xd490 |
157 | #define USB_LPM_CTRL 0xd41a | |
93fe9b18 | 158 | #define USB_BMU_RESET 0xd4b0 |
195aae32 | 159 | #define USB_BMU_CONFIG 0xd4b4 |
65b82d69 | 160 | #define USB_U1U2_TIMER 0xd4da |
9370f2d0 | 161 | #define USB_FW_TASK 0xd4e8 /* RTL8153B */ |
195aae32 | 162 | #define USB_RX_AGGR_NUM 0xd4ee |
ac718b69 | 163 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 164 | #define USB_POWER_CUT 0xd80a |
65b82d69 | 165 | #define USB_MISC_0 0xd81a |
9c27369f | 166 | #define USB_MISC_1 0xd81f |
43779f8d | 167 | #define USB_AFE_CTRL2 0xd824 |
195aae32 | 168 | #define USB_UPHY_XTAL 0xd826 |
65b82d69 | 169 | #define USB_UPS_CFG 0xd842 |
170 | #define USB_UPS_FLAGS 0xd848 | |
9370f2d0 | 171 | #define USB_WDT1_CTRL 0xe404 |
43779f8d | 172 | #define USB_WDT11_CTRL 0xe43c |
9370f2d0 HW |
173 | #define USB_BP_BA PLA_BP_BA |
174 | #define USB_BP_0 PLA_BP_0 | |
175 | #define USB_BP_1 PLA_BP_1 | |
176 | #define USB_BP_2 PLA_BP_2 | |
177 | #define USB_BP_3 PLA_BP_3 | |
178 | #define USB_BP_4 PLA_BP_4 | |
179 | #define USB_BP_5 PLA_BP_5 | |
180 | #define USB_BP_6 PLA_BP_6 | |
181 | #define USB_BP_7 PLA_BP_7 | |
182 | #define USB_BP_EN PLA_BP_EN /* RTL8153A */ | |
183 | #define USB_BP_8 0xfc38 /* RTL8153B */ | |
65b82d69 | 184 | #define USB_BP_9 0xfc3a |
185 | #define USB_BP_10 0xfc3c | |
186 | #define USB_BP_11 0xfc3e | |
187 | #define USB_BP_12 0xfc40 | |
188 | #define USB_BP_13 0xfc42 | |
189 | #define USB_BP_14 0xfc44 | |
190 | #define USB_BP_15 0xfc46 | |
191 | #define USB_BP2_EN 0xfc48 | |
ac718b69 | 192 | |
193 | /* OCP Registers */ | |
194 | #define OCP_ALDPS_CONFIG 0x2010 | |
195 | #define OCP_EEE_CONFIG1 0x2080 | |
196 | #define OCP_EEE_CONFIG2 0x2092 | |
197 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 198 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 199 | #define OCP_EEE_AR 0xa41a |
200 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 201 | #define OCP_PHY_STATUS 0xa420 |
65b82d69 | 202 | #define OCP_NCTL_CFG 0xa42c |
43779f8d | 203 | #define OCP_POWER_CFG 0xa430 |
204 | #define OCP_EEE_CFG 0xa432 | |
205 | #define OCP_SRAM_ADDR 0xa436 | |
206 | #define OCP_SRAM_DATA 0xa438 | |
207 | #define OCP_DOWN_SPEED 0xa442 | |
df35d283 | 208 | #define OCP_EEE_ABLE 0xa5c4 |
4c4a6b1b | 209 | #define OCP_EEE_ADV 0xa5d0 |
df35d283 | 210 | #define OCP_EEE_LPABLE 0xa5d2 |
195aae32 HW |
211 | #define OCP_10GBT_CTRL 0xa5d4 |
212 | #define OCP_10GBT_STAT 0xa5d6 | |
213 | #define OCP_EEE_ADV2 0xa6d4 | |
2dd49e0f | 214 | #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ |
65b82d69 | 215 | #define OCP_PHY_PATCH_STAT 0xb800 |
216 | #define OCP_PHY_PATCH_CMD 0xb820 | |
af14288f | 217 | #define OCP_PHY_LOCK 0xb82e |
65b82d69 | 218 | #define OCP_ADC_IOFFSET 0xbcfc |
43779f8d | 219 | #define OCP_ADC_CFG 0xbc06 |
65b82d69 | 220 | #define OCP_SYSCLK_CFG 0xc416 |
43779f8d | 221 | |
222 | /* SRAM Register */ | |
65b82d69 | 223 | #define SRAM_GREEN_CFG 0x8011 |
43779f8d | 224 | #define SRAM_LPF_CFG 0x8012 |
195aae32 | 225 | #define SRAM_GPHY_FW_VER 0x801e |
43779f8d | 226 | #define SRAM_10M_AMP1 0x8080 |
227 | #define SRAM_10M_AMP2 0x8082 | |
228 | #define SRAM_IMPEDANCE 0x8084 | |
af14288f | 229 | #define SRAM_PHY_LOCK 0xb82e |
ac718b69 | 230 | |
231 | /* PLA_RCR */ | |
232 | #define RCR_AAP 0x00000001 | |
233 | #define RCR_APM 0x00000002 | |
234 | #define RCR_AM 0x00000004 | |
235 | #define RCR_AB 0x00000008 | |
236 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
195aae32 HW |
237 | #define SLOT_EN BIT(11) |
238 | ||
239 | /* PLA_RCR1 */ | |
240 | #define OUTER_VLAN BIT(7) | |
241 | #define INNER_VLAN BIT(6) | |
ac718b69 | 242 | |
243 | /* PLA_RXFIFO_CTRL0 */ | |
244 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
245 | #define RXFIFO_THR1_OOB 0x01800003 | |
246 | ||
195aae32 HW |
247 | /* PLA_RXFIFO_FULL */ |
248 | #define RXFIFO_FULL_MASK 0xfff | |
249 | ||
ac718b69 | 250 | /* PLA_RXFIFO_CTRL1 */ |
251 | #define RXFIFO_THR2_FULL 0x00000060 | |
252 | #define RXFIFO_THR2_HIGH 0x00000038 | |
253 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 254 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 255 | |
256 | /* PLA_RXFIFO_CTRL2 */ | |
257 | #define RXFIFO_THR3_FULL 0x00000078 | |
258 | #define RXFIFO_THR3_HIGH 0x00000048 | |
259 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 260 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 261 | |
262 | /* PLA_TXFIFO_CTRL */ | |
263 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 264 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 265 | |
65bab84c | 266 | /* PLA_DMY_REG0 */ |
267 | #define ECM_ALDPS 0x0002 | |
268 | ||
ac718b69 | 269 | /* PLA_FMC */ |
270 | #define FMC_FCR_MCU_EN 0x0001 | |
271 | ||
272 | /* PLA_EEEP_CR */ | |
273 | #define EEEP_CR_EEEP_TX 0x0002 | |
274 | ||
43779f8d | 275 | /* PLA_WDT6_CTRL */ |
276 | #define WDT6_SET_MODE 0x0010 | |
277 | ||
ac718b69 | 278 | /* PLA_TCR0 */ |
279 | #define TCR0_TX_EMPTY 0x0800 | |
280 | #define TCR0_AUTO_FIFO 0x0080 | |
281 | ||
282 | /* PLA_TCR1 */ | |
283 | #define VERSION_MASK 0x7cf0 | |
5133bcc7 HW |
284 | #define IFG_MASK (BIT(3) | BIT(9) | BIT(8)) |
285 | #define IFG_144NS BIT(9) | |
286 | #define IFG_96NS (BIT(9) | BIT(8)) | |
ac718b69 | 287 | |
69b4b7a4 | 288 | /* PLA_MTPS */ |
289 | #define MTPS_JUMBO (12 * 1024 / 64) | |
290 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
291 | ||
4f1d4d54 | 292 | /* PLA_RSTTALLY */ |
293 | #define TALLY_RESET 0x0001 | |
294 | ||
ac718b69 | 295 | /* PLA_CR */ |
296 | #define CR_RST 0x10 | |
297 | #define CR_RE 0x08 | |
298 | #define CR_TE 0x04 | |
299 | ||
300 | /* PLA_CRWECR */ | |
301 | #define CRWECR_NORAML 0x00 | |
302 | #define CRWECR_CONFIG 0xc0 | |
303 | ||
304 | /* PLA_OOB_CTRL */ | |
305 | #define NOW_IS_OOB 0x80 | |
306 | #define TXFIFO_EMPTY 0x20 | |
307 | #define RXFIFO_EMPTY 0x10 | |
308 | #define LINK_LIST_READY 0x02 | |
309 | #define DIS_MCU_CLROOB 0x01 | |
310 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
311 | ||
312 | /* PLA_MISC_1 */ | |
313 | #define RXDY_GATED_EN 0x0008 | |
314 | ||
315 | /* PLA_SFF_STS_7 */ | |
316 | #define RE_INIT_LL 0x8000 | |
317 | #define MCU_BORW_EN 0x4000 | |
318 | ||
319 | /* PLA_CPCR */ | |
195aae32 | 320 | #define FLOW_CTRL_EN BIT(0) |
ac718b69 | 321 | #define CPCR_RX_VLAN 0x0040 |
322 | ||
323 | /* PLA_CFG_WOL */ | |
324 | #define MAGIC_EN 0x0001 | |
325 | ||
43779f8d | 326 | /* PLA_TEREDO_CFG */ |
327 | #define TEREDO_SEL 0x8000 | |
328 | #define TEREDO_WAKE_MASK 0x7f00 | |
329 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
330 | #define OOB_TEREDO_EN 0x0001 | |
331 | ||
59c0b47a | 332 | /* PLA_BDC_CR */ |
ac718b69 | 333 | #define ALDPS_PROXY_MODE 0x0001 |
334 | ||
65b82d69 | 335 | /* PLA_EFUSE_CMD */ |
336 | #define EFUSE_READ_CMD BIT(15) | |
337 | #define EFUSE_DATA_BIT16 BIT(7) | |
338 | ||
21ff2e89 | 339 | /* PLA_CONFIG34 */ |
340 | #define LINK_ON_WAKE_EN 0x0010 | |
341 | #define LINK_OFF_WAKE_EN 0x0008 | |
342 | ||
19813162 HW |
343 | /* PLA_CONFIG6 */ |
344 | #define LANWAKE_CLR_EN BIT(0) | |
345 | ||
195aae32 HW |
346 | /* PLA_USB_CFG */ |
347 | #define EN_XG_LIP BIT(1) | |
348 | #define EN_G_LIP BIT(2) | |
349 | ||
ac718b69 | 350 | /* PLA_CONFIG5 */ |
21ff2e89 | 351 | #define BWF_EN 0x0040 |
352 | #define MWF_EN 0x0020 | |
353 | #define UWF_EN 0x0010 | |
ac718b69 | 354 | #define LAN_WAKE_EN 0x0002 |
355 | ||
356 | /* PLA_LED_FEATURE */ | |
357 | #define LED_MODE_MASK 0x0700 | |
358 | ||
359 | /* PLA_PHY_PWR */ | |
360 | #define TX_10M_IDLE_EN 0x0080 | |
361 | #define PFM_PWM_SWITCH 0x0040 | |
d7f1b596 | 362 | #define TEST_IO_OFF BIT(4) |
ac718b69 | 363 | |
364 | /* PLA_MAC_PWR_CTRL */ | |
365 | #define D3_CLK_GATED_EN 0x00004000 | |
366 | #define MCU_CLK_RATIO 0x07010f07 | |
367 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 368 | #define ALDPS_SPDWN_RATIO 0x0f87 |
369 | ||
370 | /* PLA_MAC_PWR_CTRL2 */ | |
371 | #define EEE_SPDWN_RATIO 0x8007 | |
65b82d69 | 372 | #define MAC_CLK_SPDWN_EN BIT(15) |
195aae32 | 373 | #define EEE_SPDWN_RATIO_MASK 0xff |
43779f8d | 374 | |
375 | /* PLA_MAC_PWR_CTRL3 */ | |
08997b5e | 376 | #define PLA_MCU_SPDWN_EN BIT(14) |
43779f8d | 377 | #define PKT_AVAIL_SPDWN_EN 0x0100 |
378 | #define SUSPEND_SPDWN_EN 0x0004 | |
379 | #define U1U2_SPDWN_EN 0x0002 | |
380 | #define L1_SPDWN_EN 0x0001 | |
381 | ||
382 | /* PLA_MAC_PWR_CTRL4 */ | |
383 | #define PWRSAVE_SPDWN_EN 0x1000 | |
384 | #define RXDV_SPDWN_EN 0x0800 | |
385 | #define TX10MIDLE_EN 0x0100 | |
195aae32 | 386 | #define IDLE_SPDWN_EN BIT(6) |
43779f8d | 387 | #define TP100_SPDWN_EN 0x0020 |
388 | #define TP500_SPDWN_EN 0x0010 | |
389 | #define TP1000_SPDWN_EN 0x0008 | |
390 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 391 | |
392 | /* PLA_GPHY_INTR_IMR */ | |
393 | #define GPHY_STS_MSK 0x0001 | |
394 | #define SPEED_DOWN_MSK 0x0002 | |
395 | #define SPDWN_RXDV_MSK 0x0004 | |
396 | #define SPDWN_LINKCHG_MSK 0x0008 | |
397 | ||
398 | /* PLA_PHYAR */ | |
399 | #define PHYAR_FLAG 0x80000000 | |
400 | ||
401 | /* PLA_EEE_CR */ | |
402 | #define EEE_RX_EN 0x0001 | |
403 | #define EEE_TX_EN 0x0002 | |
404 | ||
43779f8d | 405 | /* PLA_BOOT_CTRL */ |
406 | #define AUTOLOAD_DONE 0x0002 | |
407 | ||
19813162 HW |
408 | /* PLA_LWAKE_CTRL_REG */ |
409 | #define LANWAKE_PIN BIT(7) | |
410 | ||
13e04fbf HW |
411 | /* PLA_SUSPEND_FLAG */ |
412 | #define LINK_CHG_EVENT BIT(0) | |
413 | ||
414 | /* PLA_INDICATE_FALG */ | |
415 | #define UPCOMING_RUNTIME_D3 BIT(0) | |
416 | ||
9370f2d0 HW |
417 | /* PLA_MACDBG_PRE and PLA_MACDBG_POST */ |
418 | #define DEBUG_OE BIT(0) | |
419 | #define DEBUG_LTSSM 0x0082 | |
420 | ||
13e04fbf | 421 | /* PLA_EXTRA_STATUS */ |
a3914272 | 422 | #define CUR_LINK_OK BIT(15) |
9370f2d0 | 423 | #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */ |
13e04fbf | 424 | #define LINK_CHANGE_FLAG BIT(8) |
a3914272 | 425 | #define POLL_LINK_CHG BIT(0) |
13e04fbf | 426 | |
195aae32 HW |
427 | /* PLA_GPHY_CTRL */ |
428 | #define GPHY_FLASH BIT(1) | |
429 | ||
430 | /* PLA_POL_GPIO_CTRL */ | |
431 | #define DACK_DET_EN BIT(15) | |
432 | #define POL_GPHY_PATCH BIT(4) | |
433 | ||
65bab84c | 434 | /* USB_USB2PHY */ |
435 | #define USB2PHY_SUSPEND 0x0001 | |
436 | #define USB2PHY_L1 0x0002 | |
437 | ||
aa475d93 HW |
438 | /* USB_SSPHYLINK1 */ |
439 | #define DELAY_PHY_PWR_CHG BIT(1) | |
440 | ||
65bab84c | 441 | /* USB_SSPHYLINK2 */ |
442 | #define pwd_dn_scale_mask 0x3ffe | |
443 | #define pwd_dn_scale(x) ((x) << 1) | |
444 | ||
445 | /* USB_CSR_DUMMY1 */ | |
446 | #define DYNAMIC_BURST 0x0001 | |
447 | ||
448 | /* USB_CSR_DUMMY2 */ | |
449 | #define EP4_FULL_FC 0x0001 | |
450 | ||
ac718b69 | 451 | /* USB_DEV_STAT */ |
452 | #define STAT_SPEED_MASK 0x0006 | |
453 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 454 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 455 | |
9370f2d0 HW |
456 | /* USB_FW_FIX_EN0 */ |
457 | #define FW_FIX_SUSPEND BIT(14) | |
458 | ||
459 | /* USB_FW_FIX_EN1 */ | |
460 | #define FW_IP_RESET_EN BIT(9) | |
461 | ||
65b82d69 | 462 | /* USB_LPM_CONFIG */ |
463 | #define LPM_U1U2_EN BIT(0) | |
464 | ||
ac718b69 | 465 | /* USB_TX_AGG */ |
466 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
467 | ||
468 | /* USB_RX_BUF_TH */ | |
43779f8d | 469 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 470 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 471 | #define RX_THR_SLOW 0xffff0180 |
65b82d69 | 472 | #define RX_THR_B 0x00010001 |
ac718b69 | 473 | |
474 | /* USB_TX_DMA */ | |
475 | #define TEST_MODE_DISABLE 0x00000001 | |
476 | #define TX_SIZE_ADJUST1 0x00000100 | |
477 | ||
93fe9b18 | 478 | /* USB_BMU_RESET */ |
479 | #define BMU_RESET_EP_IN 0x01 | |
480 | #define BMU_RESET_EP_OUT 0x02 | |
481 | ||
195aae32 HW |
482 | /* USB_BMU_CONFIG */ |
483 | #define ACT_ODMA BIT(1) | |
484 | ||
65b82d69 | 485 | /* USB_UPT_RXDMA_OWN */ |
486 | #define OWN_UPDATE BIT(0) | |
487 | #define OWN_CLEAR BIT(1) | |
488 | ||
9370f2d0 HW |
489 | /* USB_FW_TASK */ |
490 | #define FC_PATCH_TASK BIT(1) | |
491 | ||
195aae32 HW |
492 | /* USB_RX_AGGR_NUM */ |
493 | #define RX_AGGR_NUM_MASK 0x1ff | |
494 | ||
ac718b69 | 495 | /* USB_UPS_CTRL */ |
496 | #define POWER_CUT 0x0100 | |
497 | ||
498 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 499 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 500 | |
195aae32 HW |
501 | /* USB_ECM_OPTION */ |
502 | #define BYPASS_MAC_RESET BIT(5) | |
503 | ||
9370f2d0 HW |
504 | /* USB_CSTMR */ |
505 | #define FORCE_SUPER BIT(0) | |
506 | ||
195aae32 HW |
507 | /* USB_MISC_2 */ |
508 | #define UPS_FORCE_PWR_DOWN BIT(0) | |
509 | ||
510 | /* USB_ECM_OP */ | |
511 | #define EN_ALL_SPEED BIT(0) | |
512 | ||
513 | /* USB_GPHY_CTRL */ | |
514 | #define GPHY_PATCH_DONE BIT(2) | |
515 | #define BYPASS_FLASH BIT(5) | |
516 | #define BACKUP_RESTRORE BIT(6) | |
517 | ||
518 | /* USB_SPEED_OPTION */ | |
519 | #define RG_PWRDN_EN BIT(8) | |
520 | #define ALL_SPEED_OFF BIT(9) | |
521 | ||
9370f2d0 HW |
522 | /* USB_FW_CTRL */ |
523 | #define FLOW_CTRL_PATCH_OPT BIT(1) | |
195aae32 HW |
524 | #define AUTO_SPEEDUP BIT(3) |
525 | #define FLOW_CTRL_PATCH_2 BIT(8) | |
9370f2d0 HW |
526 | |
527 | /* USB_FC_TIMER */ | |
528 | #define CTRL_TIMER_EN BIT(15) | |
529 | ||
ac718b69 | 530 | /* USB_USB_CTRL */ |
195aae32 | 531 | #define CDC_ECM_EN BIT(3) |
ac718b69 | 532 | #define RX_AGG_DISABLE 0x0010 |
e90fba8d | 533 | #define RX_ZERO_EN 0x0080 |
ac718b69 | 534 | |
43779f8d | 535 | /* USB_U2P3_CTRL */ |
536 | #define U2P3_ENABLE 0x0001 | |
195aae32 | 537 | #define RX_DETECT8 BIT(3) |
43779f8d | 538 | |
539 | /* USB_POWER_CUT */ | |
540 | #define PWR_EN 0x0001 | |
541 | #define PHASE2_EN 0x0008 | |
65b82d69 | 542 | #define UPS_EN BIT(4) |
543 | #define USP_PREWAKE BIT(5) | |
43779f8d | 544 | |
545 | /* USB_MISC_0 */ | |
546 | #define PCUT_STATUS 0x0001 | |
547 | ||
464ec10a | 548 | /* USB_RX_EARLY_TIMEOUT */ |
549 | #define COALESCE_SUPER 85000U | |
550 | #define COALESCE_HIGH 250000U | |
551 | #define COALESCE_SLOW 524280U | |
43779f8d | 552 | |
9370f2d0 HW |
553 | /* USB_WDT1_CTRL */ |
554 | #define WTD1_EN BIT(0) | |
555 | ||
43779f8d | 556 | /* USB_WDT11_CTRL */ |
557 | #define TIMER11_EN 0x0001 | |
558 | ||
559 | /* USB_LPM_CTRL */ | |
65bab84c | 560 | /* bit 4 ~ 5: fifo empty boundary */ |
561 | #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ | |
562 | /* bit 2 ~ 3: LMP timer */ | |
43779f8d | 563 | #define LPM_TIMER_MASK 0x0c |
564 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
565 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
65bab84c | 566 | #define ROK_EXIT_LPM 0x02 |
43779f8d | 567 | |
568 | /* USB_AFE_CTRL2 */ | |
569 | #define SEN_VAL_MASK 0xf800 | |
570 | #define SEN_VAL_NORMAL 0xa000 | |
571 | #define SEL_RXIDLE 0x0100 | |
572 | ||
195aae32 HW |
573 | /* USB_UPHY_XTAL */ |
574 | #define OOBS_POLLING BIT(8) | |
575 | ||
65b82d69 | 576 | /* USB_UPS_CFG */ |
577 | #define SAW_CNT_1MS_MASK 0x0fff | |
195aae32 | 578 | #define MID_REVERSE BIT(5) /* RTL8156A */ |
65b82d69 | 579 | |
580 | /* USB_UPS_FLAGS */ | |
581 | #define UPS_FLAGS_R_TUNE BIT(0) | |
582 | #define UPS_FLAGS_EN_10M_CKDIV BIT(1) | |
583 | #define UPS_FLAGS_250M_CKDIV BIT(2) | |
584 | #define UPS_FLAGS_EN_ALDPS BIT(3) | |
585 | #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) | |
195aae32 | 586 | #define UPS_FLAGS_SPEED_MASK (0xf << 16) |
65b82d69 | 587 | #define ups_flags_speed(x) ((x) << 16) |
588 | #define UPS_FLAGS_EN_EEE BIT(20) | |
589 | #define UPS_FLAGS_EN_500M_EEE BIT(21) | |
590 | #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) | |
0e5b36bc | 591 | #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23) |
65b82d69 | 592 | #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) |
593 | #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) | |
594 | #define UPS_FLAGS_EN_GREEN BIT(26) | |
595 | #define UPS_FLAGS_EN_FLOW_CTR BIT(27) | |
596 | ||
597 | enum spd_duplex { | |
0e5b36bc | 598 | NWAY_10M_HALF, |
65b82d69 | 599 | NWAY_10M_FULL, |
600 | NWAY_100M_HALF, | |
601 | NWAY_100M_FULL, | |
602 | NWAY_1000M_FULL, | |
603 | FORCE_10M_HALF, | |
604 | FORCE_10M_FULL, | |
605 | FORCE_100M_HALF, | |
606 | FORCE_100M_FULL, | |
195aae32 HW |
607 | FORCE_1000M_FULL, |
608 | NWAY_2500M_FULL, | |
65b82d69 | 609 | }; |
610 | ||
ac718b69 | 611 | /* OCP_ALDPS_CONFIG */ |
612 | #define ENPWRSAVE 0x8000 | |
613 | #define ENPDNPS 0x0200 | |
614 | #define LINKENA 0x0100 | |
615 | #define DIS_SDSAVE 0x0010 | |
616 | ||
43779f8d | 617 | /* OCP_PHY_STATUS */ |
618 | #define PHY_STAT_MASK 0x0007 | |
c564b871 | 619 | #define PHY_STAT_EXT_INIT 2 |
43779f8d | 620 | #define PHY_STAT_LAN_ON 3 |
621 | #define PHY_STAT_PWRDN 5 | |
622 | ||
65b82d69 | 623 | /* OCP_NCTL_CFG */ |
624 | #define PGA_RETURN_EN BIT(1) | |
625 | ||
43779f8d | 626 | /* OCP_POWER_CFG */ |
627 | #define EEE_CLKDIV_EN 0x8000 | |
628 | #define EN_ALDPS 0x0004 | |
629 | #define EN_10M_PLLOFF 0x0001 | |
630 | ||
ac718b69 | 631 | /* OCP_EEE_CONFIG1 */ |
632 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
633 | #define RG_MATCLR_EN 0x4000 | |
634 | #define EEE_10_CAP 0x2000 | |
635 | #define EEE_NWAY_EN 0x1000 | |
636 | #define TX_QUIET_EN 0x0200 | |
637 | #define RX_QUIET_EN 0x0100 | |
d24f6134 | 638 | #define sd_rise_time_mask 0x0070 |
4c4a6b1b | 639 | #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ |
ac718b69 | 640 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
641 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
642 | ||
643 | /* OCP_EEE_CONFIG2 */ | |
644 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
645 | #define RG_DACQUIET_EN 0x0400 | |
646 | #define RG_LDVQUIET_EN 0x0200 | |
647 | #define RG_CKRSEL 0x0020 | |
648 | #define RG_EEEPRG_EN 0x0010 | |
649 | ||
650 | /* OCP_EEE_CONFIG3 */ | |
d24f6134 | 651 | #define fast_snr_mask 0xff80 |
4c4a6b1b | 652 | #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ |
ac718b69 | 653 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
654 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
655 | ||
656 | /* OCP_EEE_AR */ | |
657 | /* bit[15:14] function */ | |
658 | #define FUN_ADDR 0x0000 | |
659 | #define FUN_DATA 0x4000 | |
660 | /* bit[4:0] device addr */ | |
ac718b69 | 661 | |
43779f8d | 662 | /* OCP_EEE_CFG */ |
663 | #define CTAP_SHORT_EN 0x0040 | |
664 | #define EEE10_EN 0x0010 | |
665 | ||
666 | /* OCP_DOWN_SPEED */ | |
65b82d69 | 667 | #define EN_EEE_CMODE BIT(14) |
668 | #define EN_EEE_1000 BIT(13) | |
669 | #define EN_EEE_100 BIT(12) | |
670 | #define EN_10M_CLKDIV BIT(11) | |
43779f8d | 671 | #define EN_10M_BGOFF 0x0080 |
672 | ||
195aae32 HW |
673 | /* OCP_10GBT_CTRL */ |
674 | #define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */ | |
675 | ||
2dd49e0f | 676 | /* OCP_PHY_STATE */ |
677 | #define TXDIS_STATE 0x01 | |
678 | #define ABD_STATE 0x02 | |
679 | ||
65b82d69 | 680 | /* OCP_PHY_PATCH_STAT */ |
681 | #define PATCH_READY BIT(6) | |
682 | ||
683 | /* OCP_PHY_PATCH_CMD */ | |
684 | #define PATCH_REQUEST BIT(4) | |
685 | ||
af14288f HW |
686 | /* OCP_PHY_LOCK */ |
687 | #define PATCH_LOCK BIT(0) | |
688 | ||
43779f8d | 689 | /* OCP_ADC_CFG */ |
690 | #define CKADSEL_L 0x0100 | |
691 | #define ADC_EN 0x0080 | |
692 | #define EN_EMI_L 0x0040 | |
693 | ||
65b82d69 | 694 | /* OCP_SYSCLK_CFG */ |
195aae32 HW |
695 | #define sysclk_div_expo(x) (min(x, 5) << 8) |
696 | #define clk_div_expo(x) (min(x, 5) << 4) | |
65b82d69 | 697 | |
698 | /* SRAM_GREEN_CFG */ | |
699 | #define GREEN_ETH_EN BIT(15) | |
700 | #define R_TUNE_EN BIT(11) | |
701 | ||
43779f8d | 702 | /* SRAM_LPF_CFG */ |
703 | #define LPF_AUTO_TUNE 0x8000 | |
704 | ||
705 | /* SRAM_10M_AMP1 */ | |
706 | #define GDAC_IB_UPALL 0x0008 | |
707 | ||
708 | /* SRAM_10M_AMP2 */ | |
709 | #define AMP_DN 0x0200 | |
710 | ||
711 | /* SRAM_IMPEDANCE */ | |
712 | #define RX_DRIVING_MASK 0x6000 | |
713 | ||
af14288f HW |
714 | /* SRAM_PHY_LOCK */ |
715 | #define PHY_PATCH_LOCK 0x0001 | |
716 | ||
34ee32c9 ML |
717 | /* MAC PASSTHRU */ |
718 | #define AD_MASK 0xfee0 | |
9c27369f | 719 | #define BND_MASK 0x0004 |
8e29d23e | 720 | #define BD_MASK 0x0001 |
34ee32c9 ML |
721 | #define EFUSE 0xcfdb |
722 | #define PASS_THRU_MASK 0x1 | |
723 | ||
9370f2d0 HW |
724 | #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */ |
725 | ||
ac718b69 | 726 | enum rtl_register_content { |
195aae32 HW |
727 | _2500bps = BIT(10), |
728 | _1250bps = BIT(9), | |
729 | _500bps = BIT(8), | |
730 | _tx_flow = BIT(6), | |
731 | _rx_flow = BIT(5), | |
43779f8d | 732 | _1000bps = 0x10, |
ac718b69 | 733 | _100bps = 0x08, |
734 | _10bps = 0x04, | |
735 | LINK_STATUS = 0x02, | |
736 | FULL_DUP = 0x01, | |
737 | }; | |
738 | ||
195aae32 HW |
739 | #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS)) |
740 | #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow)) | |
741 | ||
1764bcd9 | 742 | #define RTL8152_MAX_TX 4 |
ebc2ec48 | 743 | #define RTL8152_MAX_RX 10 |
40a82917 | 744 | #define INTBUFSIZE 2 |
8e1f51bd | 745 | #define TX_ALIGN 4 |
746 | #define RX_ALIGN 8 | |
40a82917 | 747 | |
e4a5017a | 748 | #define RTL8152_RX_MAX_PENDING 4096 |
47922fcd HW |
749 | #define RTL8152_RXFG_HEADSZ 256 |
750 | ||
40a82917 | 751 | #define INTR_LINK 0x0004 |
ebc2ec48 | 752 | |
b65c0c9b | 753 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) |
69b4b7a4 | 754 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 755 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
67ce1a80 HW |
756 | #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN) |
757 | #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN) | |
758 | #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN) | |
ac718b69 | 759 | |
760 | /* rtl8152 flags */ | |
761 | enum rtl8152_flags { | |
762 | RTL8152_UNPLUG = 0, | |
ac718b69 | 763 | RTL8152_SET_RX_MODE, |
40a82917 | 764 | WORK_ENABLE, |
765 | RTL8152_LINK_CHG, | |
9a4be1bd | 766 | SELECTIVE_SUSPEND, |
aa66a5f1 | 767 | PHY_RESET, |
d2187f8e | 768 | SCHEDULE_TASKLET, |
65b82d69 | 769 | GREEN_ETHERNET, |
baf33d7a | 770 | RX_EPROTO, |
ac718b69 | 771 | }; |
772 | ||
b4b771fd | 773 | #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082 |
f01cdcf8 | 774 | #define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c |
b4b771fd | 775 | #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387 |
f01cdcf8 | 776 | #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062 |
b4b771fd | 777 | |
4f1d4d54 | 778 | struct tally_counter { |
779 | __le64 tx_packets; | |
780 | __le64 rx_packets; | |
781 | __le64 tx_errors; | |
782 | __le32 rx_errors; | |
783 | __le16 rx_missed; | |
784 | __le16 align_errors; | |
785 | __le32 tx_one_collision; | |
786 | __le32 tx_multi_collision; | |
787 | __le64 rx_unicast; | |
788 | __le64 rx_broadcast; | |
789 | __le32 rx_multicast; | |
790 | __le16 tx_aborted; | |
f37119c5 | 791 | __le16 tx_underrun; |
4f1d4d54 | 792 | }; |
793 | ||
ac718b69 | 794 | struct rx_desc { |
500b6d7e | 795 | __le32 opts1; |
ac718b69 | 796 | #define RX_LEN_MASK 0x7fff |
565cab0a | 797 | |
500b6d7e | 798 | __le32 opts2; |
f5aaaa6d | 799 | #define RD_UDP_CS BIT(23) |
800 | #define RD_TCP_CS BIT(22) | |
801 | #define RD_IPV6_CS BIT(20) | |
802 | #define RD_IPV4_CS BIT(19) | |
565cab0a | 803 | |
500b6d7e | 804 | __le32 opts3; |
f5aaaa6d | 805 | #define IPF BIT(23) /* IP checksum fail */ |
806 | #define UDPF BIT(22) /* UDP checksum fail */ | |
807 | #define TCPF BIT(21) /* TCP checksum fail */ | |
808 | #define RX_VLAN_TAG BIT(16) | |
565cab0a | 809 | |
500b6d7e | 810 | __le32 opts4; |
811 | __le32 opts5; | |
812 | __le32 opts6; | |
ac718b69 | 813 | }; |
814 | ||
815 | struct tx_desc { | |
500b6d7e | 816 | __le32 opts1; |
f5aaaa6d | 817 | #define TX_FS BIT(31) /* First segment of a packet */ |
818 | #define TX_LS BIT(30) /* Final segment of a packet */ | |
819 | #define GTSENDV4 BIT(28) | |
820 | #define GTSENDV6 BIT(27) | |
60c89071 | 821 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 822 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 823 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 824 | |
500b6d7e | 825 | __le32 opts2; |
f5aaaa6d | 826 | #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ |
827 | #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ | |
828 | #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ | |
829 | #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ | |
60c89071 | 830 | #define MSS_SHIFT 17 |
831 | #define MSS_MAX 0x7ffU | |
832 | #define TCPHO_SHIFT 17 | |
6128d1bb | 833 | #define TCPHO_MAX 0x7ffU |
f5aaaa6d | 834 | #define TX_VLAN_TAG BIT(16) |
ac718b69 | 835 | }; |
836 | ||
dff4e8ad | 837 | struct r8152; |
838 | ||
ebc2ec48 | 839 | struct rx_agg { |
252df8b8 | 840 | struct list_head list, info_list; |
ebc2ec48 | 841 | struct urb *urb; |
dff4e8ad | 842 | struct r8152 *context; |
d55d7089 | 843 | struct page *page; |
ebc2ec48 | 844 | void *buffer; |
ebc2ec48 | 845 | }; |
846 | ||
847 | struct tx_agg { | |
848 | struct list_head list; | |
849 | struct urb *urb; | |
dff4e8ad | 850 | struct r8152 *context; |
ebc2ec48 | 851 | void *buffer; |
852 | void *head; | |
853 | u32 skb_num; | |
854 | u32 skb_len; | |
855 | }; | |
856 | ||
ac718b69 | 857 | struct r8152 { |
858 | unsigned long flags; | |
859 | struct usb_device *udev; | |
d823ab68 | 860 | struct napi_struct napi; |
40a82917 | 861 | struct usb_interface *intf; |
ac718b69 | 862 | struct net_device *netdev; |
40a82917 | 863 | struct urb *intr_urb; |
ebc2ec48 | 864 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
47922fcd | 865 | struct list_head rx_info, rx_used; |
ebc2ec48 | 866 | struct list_head rx_done, tx_free; |
d823ab68 | 867 | struct sk_buff_head tx_queue, rx_queue; |
ebc2ec48 | 868 | spinlock_t rx_lock, tx_lock; |
a028a9e0 | 869 | struct delayed_work schedule, hw_phy_work; |
ac718b69 | 870 | struct mii_if_info mii; |
b5403273 | 871 | struct mutex control; /* use for hw setting */ |
5ee3c60c | 872 | #ifdef CONFIG_PM_SLEEP |
873 | struct notifier_block pm_notifier; | |
874 | #endif | |
d2187f8e | 875 | struct tasklet_struct tx_tl; |
c81229c9 | 876 | |
877 | struct rtl_ops { | |
151ea094 PM |
878 | void (*init)(struct r8152 *tp); |
879 | int (*enable)(struct r8152 *tp); | |
880 | void (*disable)(struct r8152 *tp); | |
881 | void (*up)(struct r8152 *tp); | |
882 | void (*down)(struct r8152 *tp); | |
883 | void (*unload)(struct r8152 *tp); | |
884 | int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee); | |
885 | int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee); | |
886 | bool (*in_nway)(struct r8152 *tp); | |
887 | void (*hw_phy_cfg)(struct r8152 *tp); | |
2609af19 | 888 | void (*autosuspend_en)(struct r8152 *tp, bool enable); |
67ce1a80 | 889 | void (*change_mtu)(struct r8152 *tp); |
c81229c9 | 890 | } rtl_ops; |
891 | ||
0e5b36bc | 892 | struct ups_info { |
195aae32 | 893 | u32 r_tune:1; |
0e5b36bc HW |
894 | u32 _10m_ckdiv:1; |
895 | u32 _250m_ckdiv:1; | |
896 | u32 aldps:1; | |
897 | u32 lite_mode:2; | |
898 | u32 speed_duplex:4; | |
899 | u32 eee:1; | |
900 | u32 eee_lite:1; | |
901 | u32 eee_ckdiv:1; | |
902 | u32 eee_plloff_100:1; | |
903 | u32 eee_plloff_giga:1; | |
904 | u32 eee_cmod_lv:1; | |
905 | u32 green:1; | |
906 | u32 flow_control:1; | |
907 | u32 ctap_short_off:1; | |
908 | } ups_info; | |
909 | ||
9370f2d0 HW |
910 | #define RTL_VER_SIZE 32 |
911 | ||
912 | struct rtl_fw { | |
913 | const char *fw_name; | |
914 | const struct firmware *fw; | |
915 | ||
916 | char version[RTL_VER_SIZE]; | |
917 | int (*pre_fw)(struct r8152 *tp); | |
918 | int (*post_fw)(struct r8152 *tp); | |
919 | ||
920 | bool retry; | |
921 | } rtl_fw; | |
922 | ||
252df8b8 HW |
923 | atomic_t rx_count; |
924 | ||
f4a93be6 | 925 | bool eee_en; |
40a82917 | 926 | int intr_interval; |
21ff2e89 | 927 | u32 saved_wolopts; |
ac718b69 | 928 | u32 msg_enable; |
dd1b119c | 929 | u32 tx_qlen; |
464ec10a | 930 | u32 coalesce; |
771efeda | 931 | u32 advertising; |
ec5791c2 | 932 | u32 rx_buf_sz; |
e4a5017a HW |
933 | u32 rx_copybreak; |
934 | u32 rx_pending; | |
195aae32 | 935 | u32 fc_pause_on, fc_pause_off; |
e4a5017a | 936 | |
b67fda9a HW |
937 | unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out; |
938 | ||
195aae32 | 939 | u32 support_2500full:1; |
9c68011b HW |
940 | u32 lenovo_macpassthru:1; |
941 | u32 dell_tb_rx_agg_bug:1; | |
ac718b69 | 942 | u16 ocp_base; |
aa7e26b6 | 943 | u16 speed; |
f4a93be6 | 944 | u16 eee_adv; |
40a82917 | 945 | u8 *intr_buff; |
ac718b69 | 946 | u8 version; |
aa7e26b6 | 947 | u8 duplex; |
948 | u8 autoneg; | |
ac718b69 | 949 | }; |
950 | ||
9370f2d0 HW |
951 | /** |
952 | * struct fw_block - block type and total length | |
953 | * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA, | |
954 | * RTL_FW_USB and so on. | |
955 | * @length: total length of the current block. | |
956 | */ | |
957 | struct fw_block { | |
958 | __le32 type; | |
959 | __le32 length; | |
960 | } __packed; | |
961 | ||
962 | /** | |
963 | * struct fw_header - header of the firmware file | |
964 | * @checksum: checksum of sha256 which is calculated from the whole file | |
965 | * except the checksum field of the file. That is, calculate sha256 | |
966 | * from the version field to the end of the file. | |
967 | * @version: version of this firmware. | |
968 | * @blocks: the first firmware block of the file | |
969 | */ | |
970 | struct fw_header { | |
971 | u8 checksum[32]; | |
972 | char version[RTL_VER_SIZE]; | |
ee3bc9c2 | 973 | struct fw_block blocks[]; |
9370f2d0 HW |
974 | } __packed; |
975 | ||
a8a7be17 HW |
976 | enum rtl8152_fw_flags { |
977 | FW_FLAGS_USB = 0, | |
978 | FW_FLAGS_PLA, | |
979 | FW_FLAGS_START, | |
980 | FW_FLAGS_STOP, | |
981 | FW_FLAGS_NC, | |
4a51b0e8 HW |
982 | FW_FLAGS_NC1, |
983 | FW_FLAGS_NC2, | |
984 | FW_FLAGS_UC2, | |
985 | FW_FLAGS_UC, | |
986 | FW_FLAGS_SPEED_UP, | |
987 | FW_FLAGS_VER, | |
a8a7be17 HW |
988 | }; |
989 | ||
4a51b0e8 HW |
990 | enum rtl8152_fw_fixup_cmd { |
991 | FW_FIXUP_AND = 0, | |
992 | FW_FIXUP_OR, | |
993 | FW_FIXUP_NOT, | |
994 | FW_FIXUP_XOR, | |
995 | }; | |
996 | ||
997 | struct fw_phy_set { | |
998 | __le16 addr; | |
999 | __le16 data; | |
1000 | } __packed; | |
1001 | ||
1002 | struct fw_phy_speed_up { | |
1003 | struct fw_block blk_hdr; | |
1004 | __le16 fw_offset; | |
1005 | __le16 version; | |
1006 | __le16 fw_reg; | |
1007 | __le16 reserved; | |
1008 | char info[]; | |
1009 | } __packed; | |
1010 | ||
1011 | struct fw_phy_ver { | |
1012 | struct fw_block blk_hdr; | |
1013 | struct fw_phy_set ver; | |
1014 | __le32 reserved; | |
1015 | } __packed; | |
1016 | ||
1017 | struct fw_phy_fixup { | |
1018 | struct fw_block blk_hdr; | |
1019 | struct fw_phy_set setting; | |
1020 | __le16 bit_cmd; | |
1021 | __le16 reserved; | |
1022 | } __packed; | |
1023 | ||
1024 | struct fw_phy_union { | |
1025 | struct fw_block blk_hdr; | |
1026 | __le16 fw_offset; | |
1027 | __le16 fw_reg; | |
1028 | struct fw_phy_set pre_set[2]; | |
1029 | struct fw_phy_set bp[8]; | |
1030 | struct fw_phy_set bp_en; | |
1031 | u8 pre_num; | |
1032 | u8 bp_num; | |
1033 | char info[]; | |
1034 | } __packed; | |
1035 | ||
9370f2d0 | 1036 | /** |
a66edaaf | 1037 | * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB. |
9370f2d0 | 1038 | * The layout of the firmware block is: |
a66edaaf | 1039 | * <struct fw_mac> + <info> + <firmware data>. |
34e653ef | 1040 | * @blk_hdr: firmware descriptor (type, length) |
9370f2d0 | 1041 | * @fw_offset: offset of the firmware binary data. The start address of |
a66edaaf | 1042 | * the data would be the address of struct fw_mac + @fw_offset. |
9370f2d0 HW |
1043 | * @fw_reg: the register to load the firmware. Depends on chip. |
1044 | * @bp_ba_addr: the register to write break point base address. Depends on | |
1045 | * chip. | |
1046 | * @bp_ba_value: break point base address. Depends on chip. | |
1047 | * @bp_en_addr: the register to write break point enabled mask. Depends | |
1048 | * on chip. | |
1049 | * @bp_en_value: break point enabled mask. Depends on the firmware. | |
1050 | * @bp_start: the start register of break points. Depends on chip. | |
1051 | * @bp_num: the break point number which needs to be set for this firmware. | |
1052 | * Depends on the firmware. | |
1053 | * @bp: break points. Depends on firmware. | |
34e653ef | 1054 | * @reserved: reserved space (unused) |
9370f2d0 HW |
1055 | * @fw_ver_reg: the register to store the fw version. |
1056 | * @fw_ver_data: the firmware version of the current type. | |
1057 | * @info: additional information for debugging, and is followed by the | |
1058 | * binary data of firmware. | |
1059 | */ | |
a66edaaf | 1060 | struct fw_mac { |
9370f2d0 HW |
1061 | struct fw_block blk_hdr; |
1062 | __le16 fw_offset; | |
1063 | __le16 fw_reg; | |
1064 | __le16 bp_ba_addr; | |
1065 | __le16 bp_ba_value; | |
1066 | __le16 bp_en_addr; | |
1067 | __le16 bp_en_value; | |
1068 | __le16 bp_start; | |
1069 | __le16 bp_num; | |
1070 | __le16 bp[16]; /* any value determined by firmware */ | |
1071 | __le32 reserved; | |
1072 | __le16 fw_ver_reg; | |
1073 | u8 fw_ver_data; | |
ee3bc9c2 | 1074 | char info[]; |
9370f2d0 HW |
1075 | } __packed; |
1076 | ||
af14288f HW |
1077 | /** |
1078 | * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START. | |
1079 | * This is used to set patch key when loading the firmware of PHY. | |
34e653ef | 1080 | * @blk_hdr: firmware descriptor (type, length) |
af14288f HW |
1081 | * @key_reg: the register to write the patch key. |
1082 | * @key_data: patch key. | |
34e653ef | 1083 | * @reserved: reserved space (unused) |
af14288f HW |
1084 | */ |
1085 | struct fw_phy_patch_key { | |
1086 | struct fw_block blk_hdr; | |
1087 | __le16 key_reg; | |
1088 | __le16 key_data; | |
1089 | __le32 reserved; | |
1090 | } __packed; | |
1091 | ||
1092 | /** | |
1093 | * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC. | |
1094 | * The layout of the firmware block is: | |
1095 | * <struct fw_phy_nc> + <info> + <firmware data>. | |
34e653ef | 1096 | * @blk_hdr: firmware descriptor (type, length) |
af14288f HW |
1097 | * @fw_offset: offset of the firmware binary data. The start address of |
1098 | * the data would be the address of struct fw_phy_nc + @fw_offset. | |
1099 | * @fw_reg: the register to load the firmware. Depends on chip. | |
1100 | * @ba_reg: the register to write the base address. Depends on chip. | |
1101 | * @ba_data: base address. Depends on chip. | |
1102 | * @patch_en_addr: the register of enabling patch mode. Depends on chip. | |
1103 | * @patch_en_value: patch mode enabled mask. Depends on the firmware. | |
1104 | * @mode_reg: the regitster of switching the mode. | |
9f07814d LJ |
1105 | * @mode_pre: the mode needing to be set before loading the firmware. |
1106 | * @mode_post: the mode to be set when finishing to load the firmware. | |
34e653ef | 1107 | * @reserved: reserved space (unused) |
af14288f HW |
1108 | * @bp_start: the start register of break points. Depends on chip. |
1109 | * @bp_num: the break point number which needs to be set for this firmware. | |
1110 | * Depends on the firmware. | |
1111 | * @bp: break points. Depends on firmware. | |
1112 | * @info: additional information for debugging, and is followed by the | |
1113 | * binary data of firmware. | |
1114 | */ | |
1115 | struct fw_phy_nc { | |
1116 | struct fw_block blk_hdr; | |
1117 | __le16 fw_offset; | |
1118 | __le16 fw_reg; | |
1119 | __le16 ba_reg; | |
1120 | __le16 ba_data; | |
1121 | __le16 patch_en_addr; | |
1122 | __le16 patch_en_value; | |
1123 | __le16 mode_reg; | |
1124 | __le16 mode_pre; | |
1125 | __le16 mode_post; | |
1126 | __le16 reserved; | |
1127 | __le16 bp_start; | |
1128 | __le16 bp_num; | |
1129 | __le16 bp[4]; | |
ee3bc9c2 | 1130 | char info[]; |
af14288f HW |
1131 | } __packed; |
1132 | ||
9370f2d0 HW |
1133 | enum rtl_fw_type { |
1134 | RTL_FW_END = 0, | |
1135 | RTL_FW_PLA, | |
1136 | RTL_FW_USB, | |
af14288f HW |
1137 | RTL_FW_PHY_START, |
1138 | RTL_FW_PHY_STOP, | |
1139 | RTL_FW_PHY_NC, | |
4a51b0e8 HW |
1140 | RTL_FW_PHY_FIXUP, |
1141 | RTL_FW_PHY_UNION_NC, | |
1142 | RTL_FW_PHY_UNION_NC1, | |
1143 | RTL_FW_PHY_UNION_NC2, | |
1144 | RTL_FW_PHY_UNION_UC2, | |
1145 | RTL_FW_PHY_UNION_UC, | |
1146 | RTL_FW_PHY_UNION_MISC, | |
1147 | RTL_FW_PHY_SPEED_UP, | |
1148 | RTL_FW_PHY_VER, | |
9370f2d0 HW |
1149 | }; |
1150 | ||
ac718b69 | 1151 | enum rtl_version { |
1152 | RTL_VER_UNKNOWN = 0, | |
1153 | RTL_VER_01, | |
43779f8d | 1154 | RTL_VER_02, |
1155 | RTL_VER_03, | |
1156 | RTL_VER_04, | |
1157 | RTL_VER_05, | |
fb02eb4a | 1158 | RTL_VER_06, |
c27b32c2 | 1159 | RTL_VER_07, |
65b82d69 | 1160 | RTL_VER_08, |
1161 | RTL_VER_09, | |
195aae32 HW |
1162 | |
1163 | RTL_TEST_01, | |
1164 | RTL_VER_10, | |
1165 | RTL_VER_11, | |
1166 | RTL_VER_12, | |
1167 | RTL_VER_13, | |
1168 | RTL_VER_14, | |
1169 | RTL_VER_15, | |
1170 | ||
43779f8d | 1171 | RTL_VER_MAX |
ac718b69 | 1172 | }; |
1173 | ||
60c89071 | 1174 | enum tx_csum_stat { |
1175 | TX_CSUM_SUCCESS = 0, | |
1176 | TX_CSUM_TSO, | |
1177 | TX_CSUM_NONE | |
1178 | }; | |
1179 | ||
771efeda HW |
1180 | #define RTL_ADVERTISED_10_HALF BIT(0) |
1181 | #define RTL_ADVERTISED_10_FULL BIT(1) | |
1182 | #define RTL_ADVERTISED_100_HALF BIT(2) | |
1183 | #define RTL_ADVERTISED_100_FULL BIT(3) | |
1184 | #define RTL_ADVERTISED_1000_HALF BIT(4) | |
1185 | #define RTL_ADVERTISED_1000_FULL BIT(5) | |
195aae32 | 1186 | #define RTL_ADVERTISED_2500_FULL BIT(6) |
771efeda | 1187 | |
ac718b69 | 1188 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
1189 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
1190 | */ | |
1191 | static const int multicast_filter_limit = 32; | |
52aec126 | 1192 | static unsigned int agg_buf_sz = 16384; |
ac718b69 | 1193 | |
67ce1a80 | 1194 | #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc)) |
60c89071 | 1195 | |
ac718b69 | 1196 | static |
1197 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
1198 | { | |
31787f53 | 1199 | int ret; |
1200 | void *tmp; | |
1201 | ||
1202 | tmp = kmalloc(size, GFP_KERNEL); | |
1203 | if (!tmp) | |
1204 | return -ENOMEM; | |
1205 | ||
b67fda9a | 1206 | ret = usb_control_msg(tp->udev, tp->pipe_ctrl_in, |
b209af99 | 1207 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
1208 | value, index, tmp, size, 500); | |
f53a7ad1 PM |
1209 | if (ret < 0) |
1210 | memset(data, 0xff, size); | |
1211 | else | |
1212 | memcpy(data, tmp, size); | |
31787f53 | 1213 | |
31787f53 | 1214 | kfree(tmp); |
1215 | ||
1216 | return ret; | |
ac718b69 | 1217 | } |
1218 | ||
1219 | static | |
1220 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
1221 | { | |
31787f53 | 1222 | int ret; |
1223 | void *tmp; | |
1224 | ||
c4438f03 | 1225 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 1226 | if (!tmp) |
1227 | return -ENOMEM; | |
1228 | ||
b67fda9a | 1229 | ret = usb_control_msg(tp->udev, tp->pipe_ctrl_out, |
b209af99 | 1230 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
1231 | value, index, tmp, size, 500); | |
31787f53 | 1232 | |
1233 | kfree(tmp); | |
db8515ef | 1234 | |
31787f53 | 1235 | return ret; |
ac718b69 | 1236 | } |
1237 | ||
ffa9fec3 HW |
1238 | static void rtl_set_unplug(struct r8152 *tp) |
1239 | { | |
1240 | if (tp->udev->state == USB_STATE_NOTATTACHED) { | |
1241 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1242 | smp_mb__after_atomic(); | |
1243 | } | |
1244 | } | |
1245 | ||
ac718b69 | 1246 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, |
b209af99 | 1247 | void *data, u16 type) |
ac718b69 | 1248 | { |
45f4a19f | 1249 | u16 limit = 64; |
1250 | int ret = 0; | |
ac718b69 | 1251 | |
1252 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1253 | return -ENODEV; | |
1254 | ||
1255 | /* both size and indix must be 4 bytes align */ | |
1256 | if ((size & 3) || !size || (index & 3) || !data) | |
1257 | return -EPERM; | |
1258 | ||
1259 | if ((u32)index + (u32)size > 0xffff) | |
1260 | return -EPERM; | |
1261 | ||
1262 | while (size) { | |
1263 | if (size > limit) { | |
1264 | ret = get_registers(tp, index, type, limit, data); | |
1265 | if (ret < 0) | |
1266 | break; | |
1267 | ||
1268 | index += limit; | |
1269 | data += limit; | |
1270 | size -= limit; | |
1271 | } else { | |
1272 | ret = get_registers(tp, index, type, size, data); | |
1273 | if (ret < 0) | |
1274 | break; | |
1275 | ||
1276 | index += size; | |
1277 | data += size; | |
1278 | size = 0; | |
1279 | break; | |
1280 | } | |
1281 | } | |
1282 | ||
67610496 | 1283 | if (ret == -ENODEV) |
ffa9fec3 | 1284 | rtl_set_unplug(tp); |
67610496 | 1285 | |
ac718b69 | 1286 | return ret; |
1287 | } | |
1288 | ||
1289 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
b209af99 | 1290 | u16 size, void *data, u16 type) |
ac718b69 | 1291 | { |
45f4a19f | 1292 | int ret; |
1293 | u16 byteen_start, byteen_end, byen; | |
1294 | u16 limit = 512; | |
ac718b69 | 1295 | |
1296 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1297 | return -ENODEV; | |
1298 | ||
1299 | /* both size and indix must be 4 bytes align */ | |
1300 | if ((size & 3) || !size || (index & 3) || !data) | |
1301 | return -EPERM; | |
1302 | ||
1303 | if ((u32)index + (u32)size > 0xffff) | |
1304 | return -EPERM; | |
1305 | ||
1306 | byteen_start = byteen & BYTE_EN_START_MASK; | |
1307 | byteen_end = byteen & BYTE_EN_END_MASK; | |
1308 | ||
1309 | byen = byteen_start | (byteen_start << 4); | |
1310 | ret = set_registers(tp, index, type | byen, 4, data); | |
1311 | if (ret < 0) | |
1312 | goto error1; | |
1313 | ||
1314 | index += 4; | |
1315 | data += 4; | |
1316 | size -= 4; | |
1317 | ||
1318 | if (size) { | |
1319 | size -= 4; | |
1320 | ||
1321 | while (size) { | |
1322 | if (size > limit) { | |
1323 | ret = set_registers(tp, index, | |
b209af99 | 1324 | type | BYTE_EN_DWORD, |
1325 | limit, data); | |
ac718b69 | 1326 | if (ret < 0) |
1327 | goto error1; | |
1328 | ||
1329 | index += limit; | |
1330 | data += limit; | |
1331 | size -= limit; | |
1332 | } else { | |
1333 | ret = set_registers(tp, index, | |
b209af99 | 1334 | type | BYTE_EN_DWORD, |
1335 | size, data); | |
ac718b69 | 1336 | if (ret < 0) |
1337 | goto error1; | |
1338 | ||
1339 | index += size; | |
1340 | data += size; | |
1341 | size = 0; | |
1342 | break; | |
1343 | } | |
1344 | } | |
1345 | ||
1346 | byen = byteen_end | (byteen_end >> 4); | |
1347 | ret = set_registers(tp, index, type | byen, 4, data); | |
1348 | if (ret < 0) | |
1349 | goto error1; | |
1350 | } | |
1351 | ||
1352 | error1: | |
67610496 | 1353 | if (ret == -ENODEV) |
ffa9fec3 | 1354 | rtl_set_unplug(tp); |
67610496 | 1355 | |
ac718b69 | 1356 | return ret; |
1357 | } | |
1358 | ||
1359 | static inline | |
1360 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
1361 | { | |
1362 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
1363 | } | |
1364 | ||
1365 | static inline | |
1366 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
1367 | { | |
1368 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
1369 | } | |
1370 | ||
ac718b69 | 1371 | static inline |
1372 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
1373 | { | |
1374 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
1375 | } | |
1376 | ||
1377 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
1378 | { | |
c8826de8 | 1379 | __le32 data; |
ac718b69 | 1380 | |
c8826de8 | 1381 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 1382 | |
1383 | return __le32_to_cpu(data); | |
1384 | } | |
1385 | ||
1386 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
1387 | { | |
c8826de8 | 1388 | __le32 tmp = __cpu_to_le32(data); |
1389 | ||
1390 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 1391 | } |
1392 | ||
1393 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
1394 | { | |
1395 | u32 data; | |
c8826de8 | 1396 | __le32 tmp; |
d8fbd274 | 1397 | u16 byen = BYTE_EN_WORD; |
ac718b69 | 1398 | u8 shift = index & 2; |
1399 | ||
1400 | index &= ~3; | |
d8fbd274 | 1401 | byen <<= shift; |
ac718b69 | 1402 | |
d8fbd274 | 1403 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); |
ac718b69 | 1404 | |
c8826de8 | 1405 | data = __le32_to_cpu(tmp); |
ac718b69 | 1406 | data >>= (shift * 8); |
1407 | data &= 0xffff; | |
1408 | ||
1409 | return (u16)data; | |
1410 | } | |
1411 | ||
1412 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
1413 | { | |
c8826de8 | 1414 | u32 mask = 0xffff; |
1415 | __le32 tmp; | |
ac718b69 | 1416 | u16 byen = BYTE_EN_WORD; |
1417 | u8 shift = index & 2; | |
1418 | ||
1419 | data &= mask; | |
1420 | ||
1421 | if (index & 2) { | |
1422 | byen <<= shift; | |
1423 | mask <<= (shift * 8); | |
1424 | data <<= (shift * 8); | |
1425 | index &= ~3; | |
1426 | } | |
1427 | ||
c8826de8 | 1428 | tmp = __cpu_to_le32(data); |
ac718b69 | 1429 | |
c8826de8 | 1430 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 1431 | } |
1432 | ||
1433 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
1434 | { | |
1435 | u32 data; | |
c8826de8 | 1436 | __le32 tmp; |
ac718b69 | 1437 | u8 shift = index & 3; |
1438 | ||
1439 | index &= ~3; | |
1440 | ||
c8826de8 | 1441 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 1442 | |
c8826de8 | 1443 | data = __le32_to_cpu(tmp); |
ac718b69 | 1444 | data >>= (shift * 8); |
1445 | data &= 0xff; | |
1446 | ||
1447 | return (u8)data; | |
1448 | } | |
1449 | ||
1450 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
1451 | { | |
c8826de8 | 1452 | u32 mask = 0xff; |
1453 | __le32 tmp; | |
ac718b69 | 1454 | u16 byen = BYTE_EN_BYTE; |
1455 | u8 shift = index & 3; | |
1456 | ||
1457 | data &= mask; | |
1458 | ||
1459 | if (index & 3) { | |
1460 | byen <<= shift; | |
1461 | mask <<= (shift * 8); | |
1462 | data <<= (shift * 8); | |
1463 | index &= ~3; | |
1464 | } | |
1465 | ||
c8826de8 | 1466 | tmp = __cpu_to_le32(data); |
ac718b69 | 1467 | |
c8826de8 | 1468 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 1469 | } |
1470 | ||
ac244d3e | 1471 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 1472 | { |
1473 | u16 ocp_base, ocp_index; | |
1474 | ||
1475 | ocp_base = addr & 0xf000; | |
1476 | if (ocp_base != tp->ocp_base) { | |
1477 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
1478 | tp->ocp_base = ocp_base; | |
1479 | } | |
1480 | ||
1481 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 1482 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 1483 | } |
1484 | ||
ac244d3e | 1485 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 1486 | { |
ac244d3e | 1487 | u16 ocp_base, ocp_index; |
ac718b69 | 1488 | |
ac244d3e | 1489 | ocp_base = addr & 0xf000; |
1490 | if (ocp_base != tp->ocp_base) { | |
1491 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
1492 | tp->ocp_base = ocp_base; | |
ac718b69 | 1493 | } |
ac244d3e | 1494 | |
1495 | ocp_index = (addr & 0x0fff) | 0xb000; | |
1496 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 1497 | } |
1498 | ||
ac244d3e | 1499 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 1500 | { |
ac244d3e | 1501 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
1502 | } | |
ac718b69 | 1503 | |
ac244d3e | 1504 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
1505 | { | |
1506 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 1507 | } |
1508 | ||
43779f8d | 1509 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
1510 | { | |
1511 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
1512 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
1513 | } | |
1514 | ||
65b82d69 | 1515 | static u16 sram_read(struct r8152 *tp, u16 addr) |
1516 | { | |
1517 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
1518 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
1519 | } | |
1520 | ||
ac718b69 | 1521 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
1522 | { | |
1523 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 1524 | int ret; |
ac718b69 | 1525 | |
6871438c | 1526 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1527 | return -ENODEV; | |
1528 | ||
ac718b69 | 1529 | if (phy_id != R8152_PHY_ID) |
1530 | return -EINVAL; | |
1531 | ||
9a4be1bd | 1532 | ret = r8152_mdio_read(tp, reg); |
1533 | ||
9a4be1bd | 1534 | return ret; |
ac718b69 | 1535 | } |
1536 | ||
1537 | static | |
1538 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
1539 | { | |
1540 | struct r8152 *tp = netdev_priv(netdev); | |
1541 | ||
6871438c | 1542 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1543 | return; | |
1544 | ||
ac718b69 | 1545 | if (phy_id != R8152_PHY_ID) |
1546 | return; | |
1547 | ||
1548 | r8152_mdio_write(tp, reg, val); | |
1549 | } | |
1550 | ||
b209af99 | 1551 | static int |
1552 | r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
ebc2ec48 | 1553 | |
80fd850b HW |
1554 | static int |
1555 | rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, | |
1556 | u32 advertising); | |
1557 | ||
776ac63a TI |
1558 | static int __rtl8152_set_mac_address(struct net_device *netdev, void *p, |
1559 | bool in_resume) | |
8ba789ab | 1560 | { |
1561 | struct r8152 *tp = netdev_priv(netdev); | |
1562 | struct sockaddr *addr = p; | |
ea6a7112 | 1563 | int ret = -EADDRNOTAVAIL; |
8ba789ab | 1564 | |
1565 | if (!is_valid_ether_addr(addr->sa_data)) | |
ea6a7112 | 1566 | goto out1; |
1567 | ||
776ac63a TI |
1568 | if (!in_resume) { |
1569 | ret = usb_autopm_get_interface(tp->intf); | |
1570 | if (ret < 0) | |
1571 | goto out1; | |
1572 | } | |
8ba789ab | 1573 | |
b5403273 | 1574 | mutex_lock(&tp->control); |
1575 | ||
49ed8dde | 1576 | eth_hw_addr_set(netdev, addr->sa_data); |
8ba789ab | 1577 | |
1578 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1579 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
1580 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1581 | ||
b5403273 | 1582 | mutex_unlock(&tp->control); |
1583 | ||
776ac63a TI |
1584 | if (!in_resume) |
1585 | usb_autopm_put_interface(tp->intf); | |
ea6a7112 | 1586 | out1: |
1587 | return ret; | |
8ba789ab | 1588 | } |
1589 | ||
776ac63a TI |
1590 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
1591 | { | |
1592 | return __rtl8152_set_mac_address(netdev, p, false); | |
1593 | } | |
1594 | ||
9c27369f | 1595 | /* Devices containing proper chips can support a persistent |
34ee32c9 ML |
1596 | * host system provided MAC address. |
1597 | * Examples of this are Dell TB15 and Dell WD15 docks | |
1598 | */ | |
1599 | static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) | |
1600 | { | |
1601 | acpi_status status; | |
1602 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1603 | union acpi_object *obj; | |
1604 | int ret = -EINVAL; | |
1605 | u32 ocp_data; | |
1606 | unsigned char buf[6]; | |
9647722b KHF |
1607 | char *mac_obj_name; |
1608 | acpi_object_type mac_obj_type; | |
1609 | int mac_strlen; | |
1610 | ||
9c68011b | 1611 | if (tp->lenovo_macpassthru) { |
9647722b KHF |
1612 | mac_obj_name = "\\MACA"; |
1613 | mac_obj_type = ACPI_TYPE_STRING; | |
1614 | mac_strlen = 0x16; | |
9c27369f | 1615 | } else { |
9647722b KHF |
1616 | /* test for -AD variant of RTL8153 */ |
1617 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
1618 | if ((ocp_data & AD_MASK) == 0x1000) { | |
1619 | /* test for MAC address pass-through bit */ | |
1620 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); | |
1621 | if ((ocp_data & PASS_THRU_MASK) != 1) { | |
1622 | netif_dbg(tp, probe, tp->netdev, | |
1623 | "No efuse for RTL8153-AD MAC pass through\n"); | |
1624 | return -ENODEV; | |
1625 | } | |
1626 | } else { | |
1627 | /* test for RTL8153-BND and RTL8153-BD */ | |
1628 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); | |
1629 | if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { | |
1630 | netif_dbg(tp, probe, tp->netdev, | |
1631 | "Invalid variant for MAC pass through\n"); | |
1632 | return -ENODEV; | |
1633 | } | |
9c27369f | 1634 | } |
9647722b KHF |
1635 | |
1636 | mac_obj_name = "\\_SB.AMAC"; | |
1637 | mac_obj_type = ACPI_TYPE_BUFFER; | |
1638 | mac_strlen = 0x17; | |
9c27369f | 1639 | } |
34ee32c9 ML |
1640 | |
1641 | /* returns _AUXMAC_#AABBCCDDEEFF# */ | |
9647722b | 1642 | status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer); |
34ee32c9 ML |
1643 | obj = (union acpi_object *)buffer.pointer; |
1644 | if (!ACPI_SUCCESS(status)) | |
1645 | return -ENODEV; | |
9647722b | 1646 | if (obj->type != mac_obj_type || obj->string.length != mac_strlen) { |
34ee32c9 | 1647 | netif_warn(tp, probe, tp->netdev, |
53700f0c | 1648 | "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", |
34ee32c9 ML |
1649 | obj->type, obj->string.length); |
1650 | goto amacout; | |
1651 | } | |
9647722b | 1652 | |
34ee32c9 ML |
1653 | if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || |
1654 | strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { | |
1655 | netif_warn(tp, probe, tp->netdev, | |
1656 | "Invalid header when reading pass-thru MAC addr\n"); | |
1657 | goto amacout; | |
1658 | } | |
1659 | ret = hex2bin(buf, obj->string.pointer + 9, 6); | |
1660 | if (!(ret == 0 && is_valid_ether_addr(buf))) { | |
1661 | netif_warn(tp, probe, tp->netdev, | |
53700f0c | 1662 | "Invalid MAC for pass-thru MAC addr: %d, %pM\n", |
1663 | ret, buf); | |
34ee32c9 ML |
1664 | ret = -EINVAL; |
1665 | goto amacout; | |
1666 | } | |
1667 | memcpy(sa->sa_data, buf, 6); | |
34ee32c9 ML |
1668 | netif_info(tp, probe, tp->netdev, |
1669 | "Using pass-thru MAC addr %pM\n", sa->sa_data); | |
1670 | ||
1671 | amacout: | |
1672 | kfree(obj); | |
1673 | return ret; | |
1674 | } | |
1675 | ||
25766271 | 1676 | static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa) |
ac718b69 | 1677 | { |
1678 | struct net_device *dev = tp->netdev; | |
8a91c824 | 1679 | int ret; |
ac718b69 | 1680 | |
a6cbcb77 CW |
1681 | sa->sa_family = dev->type; |
1682 | ||
b9b40ee4 | 1683 | ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data); |
acb6d377 TR |
1684 | if (ret < 0) { |
1685 | if (tp->version == RTL_VER_01) { | |
1686 | ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data); | |
1687 | } else { | |
1688 | /* if device doesn't support MAC pass through this will | |
1689 | * be expected to be non-zero | |
1690 | */ | |
1691 | ret = vendor_mac_passthru_addr_read(tp, sa); | |
1692 | if (ret < 0) | |
1693 | ret = pla_ocp_read(tp, PLA_BACKUP, 8, | |
1694 | sa->sa_data); | |
1695 | } | |
34ee32c9 | 1696 | } |
8a91c824 | 1697 | |
1698 | if (ret < 0) { | |
179bb6d7 | 1699 | netif_err(tp, probe, dev, "Get ether addr fail\n"); |
25766271 | 1700 | } else if (!is_valid_ether_addr(sa->sa_data)) { |
179bb6d7 | 1701 | netif_err(tp, probe, dev, "Invalid ether addr %pM\n", |
25766271 | 1702 | sa->sa_data); |
179bb6d7 | 1703 | eth_hw_addr_random(dev); |
25766271 | 1704 | ether_addr_copy(sa->sa_data, dev->dev_addr); |
179bb6d7 | 1705 | netif_info(tp, probe, dev, "Random ether addr %pM\n", |
25766271 ML |
1706 | sa->sa_data); |
1707 | return 0; | |
ac718b69 | 1708 | } |
179bb6d7 | 1709 | |
1710 | return ret; | |
ac718b69 | 1711 | } |
1712 | ||
776ac63a | 1713 | static int set_ethernet_addr(struct r8152 *tp, bool in_resume) |
25766271 ML |
1714 | { |
1715 | struct net_device *dev = tp->netdev; | |
1716 | struct sockaddr sa; | |
1717 | int ret; | |
1718 | ||
1719 | ret = determine_ethernet_addr(tp, &sa); | |
1720 | if (ret < 0) | |
1721 | return ret; | |
1722 | ||
1723 | if (tp->version == RTL_VER_01) | |
af804e6d | 1724 | eth_hw_addr_set(dev, sa.sa_data); |
25766271 | 1725 | else |
776ac63a | 1726 | ret = __rtl8152_set_mac_address(dev, &sa, in_resume); |
25766271 ML |
1727 | |
1728 | return ret; | |
1729 | } | |
1730 | ||
ac718b69 | 1731 | static void read_bulk_callback(struct urb *urb) |
1732 | { | |
ac718b69 | 1733 | struct net_device *netdev; |
ac718b69 | 1734 | int status = urb->status; |
ebc2ec48 | 1735 | struct rx_agg *agg; |
1736 | struct r8152 *tp; | |
ed7aa30e | 1737 | unsigned long flags; |
ac718b69 | 1738 | |
ebc2ec48 | 1739 | agg = urb->context; |
1740 | if (!agg) | |
1741 | return; | |
1742 | ||
1743 | tp = agg->context; | |
ac718b69 | 1744 | if (!tp) |
1745 | return; | |
ebc2ec48 | 1746 | |
ac718b69 | 1747 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1748 | return; | |
ebc2ec48 | 1749 | |
1750 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1751 | return; | |
1752 | ||
ac718b69 | 1753 | netdev = tp->netdev; |
7559fb2f | 1754 | |
1755 | /* When link down, the driver would cancel all bulks. */ | |
1756 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1757 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1758 | return; |
1759 | ||
9a4be1bd | 1760 | usb_mark_last_busy(tp->udev); |
1761 | ||
ac718b69 | 1762 | switch (status) { |
1763 | case 0: | |
ebc2ec48 | 1764 | if (urb->actual_length < ETH_ZLEN) |
1765 | break; | |
1766 | ||
ed7aa30e | 1767 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 1768 | list_add_tail(&agg->list, &tp->rx_done); |
ed7aa30e | 1769 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
d823ab68 | 1770 | napi_schedule(&tp->napi); |
ebc2ec48 | 1771 | return; |
ac718b69 | 1772 | case -ESHUTDOWN: |
ffa9fec3 | 1773 | rtl_set_unplug(tp); |
ac718b69 | 1774 | netif_device_detach(tp->netdev); |
ebc2ec48 | 1775 | return; |
baf33d7a HW |
1776 | case -EPROTO: |
1777 | urb->actual_length = 0; | |
1778 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1779 | list_add_tail(&agg->list, &tp->rx_done); | |
1780 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1781 | set_bit(RX_EPROTO, &tp->flags); | |
1782 | schedule_delayed_work(&tp->schedule, 1); | |
1783 | return; | |
ac718b69 | 1784 | case -ENOENT: |
1785 | return; /* the urb is in unlink state */ | |
1786 | case -ETIME: | |
4a8deae2 HW |
1787 | if (net_ratelimit()) |
1788 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1789 | break; |
ac718b69 | 1790 | default: |
4a8deae2 HW |
1791 | if (net_ratelimit()) |
1792 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1793 | break; |
ac718b69 | 1794 | } |
1795 | ||
a0fccd48 | 1796 | r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1797 | } |
1798 | ||
ebc2ec48 | 1799 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1800 | { |
ebc2ec48 | 1801 | struct net_device_stats *stats; |
d104eafa | 1802 | struct net_device *netdev; |
ebc2ec48 | 1803 | struct tx_agg *agg; |
ac718b69 | 1804 | struct r8152 *tp; |
ed7aa30e | 1805 | unsigned long flags; |
ebc2ec48 | 1806 | int status = urb->status; |
ac718b69 | 1807 | |
ebc2ec48 | 1808 | agg = urb->context; |
1809 | if (!agg) | |
ac718b69 | 1810 | return; |
1811 | ||
ebc2ec48 | 1812 | tp = agg->context; |
1813 | if (!tp) | |
1814 | return; | |
1815 | ||
d104eafa | 1816 | netdev = tp->netdev; |
05e0f1aa | 1817 | stats = &netdev->stats; |
ebc2ec48 | 1818 | if (status) { |
4a8deae2 | 1819 | if (net_ratelimit()) |
d104eafa | 1820 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1821 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1822 | } else { |
ebc2ec48 | 1823 | stats->tx_packets += agg->skb_num; |
1824 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1825 | } |
1826 | ||
ed7aa30e | 1827 | spin_lock_irqsave(&tp->tx_lock, flags); |
ebc2ec48 | 1828 | list_add_tail(&agg->list, &tp->tx_free); |
ed7aa30e | 1829 | spin_unlock_irqrestore(&tp->tx_lock, flags); |
ebc2ec48 | 1830 | |
9a4be1bd | 1831 | usb_autopm_put_interface_async(tp->intf); |
1832 | ||
d104eafa | 1833 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1834 | return; |
1835 | ||
1836 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1837 | return; | |
1838 | ||
1839 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1840 | return; | |
1841 | ||
1842 | if (!skb_queue_empty(&tp->tx_queue)) | |
d2187f8e | 1843 | tasklet_schedule(&tp->tx_tl); |
ac718b69 | 1844 | } |
1845 | ||
40a82917 | 1846 | static void intr_callback(struct urb *urb) |
1847 | { | |
1848 | struct r8152 *tp; | |
500b6d7e | 1849 | __le16 *d; |
40a82917 | 1850 | int status = urb->status; |
1851 | int res; | |
1852 | ||
1853 | tp = urb->context; | |
1854 | if (!tp) | |
1855 | return; | |
1856 | ||
1857 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1858 | return; | |
1859 | ||
1860 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1861 | return; | |
1862 | ||
1863 | switch (status) { | |
1864 | case 0: /* success */ | |
1865 | break; | |
1866 | case -ECONNRESET: /* unlink */ | |
1867 | case -ESHUTDOWN: | |
1868 | netif_device_detach(tp->netdev); | |
df561f66 | 1869 | fallthrough; |
40a82917 | 1870 | case -ENOENT: |
d59c876d | 1871 | case -EPROTO: |
1872 | netif_info(tp, intr, tp->netdev, | |
1873 | "Stop submitting intr, status %d\n", status); | |
40a82917 | 1874 | return; |
1875 | case -EOVERFLOW: | |
1876 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1877 | goto resubmit; | |
1878 | /* -EPIPE: should clear the halt */ | |
1879 | default: | |
1880 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1881 | goto resubmit; | |
1882 | } | |
1883 | ||
1884 | d = urb->transfer_buffer; | |
1885 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
51d979fa | 1886 | if (!netif_carrier_ok(tp->netdev)) { |
40a82917 | 1887 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1888 | schedule_delayed_work(&tp->schedule, 0); | |
1889 | } | |
1890 | } else { | |
51d979fa | 1891 | if (netif_carrier_ok(tp->netdev)) { |
2f25abe6 | 1892 | netif_stop_queue(tp->netdev); |
40a82917 | 1893 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1894 | schedule_delayed_work(&tp->schedule, 0); | |
1895 | } | |
1896 | } | |
1897 | ||
1898 | resubmit: | |
1899 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
67610496 | 1900 | if (res == -ENODEV) { |
ffa9fec3 | 1901 | rtl_set_unplug(tp); |
40a82917 | 1902 | netif_device_detach(tp->netdev); |
67610496 | 1903 | } else if (res) { |
40a82917 | 1904 | netif_err(tp, intr, tp->netdev, |
4a8deae2 | 1905 | "can't resubmit intr, status %d\n", res); |
67610496 | 1906 | } |
40a82917 | 1907 | } |
1908 | ||
ebc2ec48 | 1909 | static inline void *rx_agg_align(void *data) |
1910 | { | |
8e1f51bd | 1911 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1912 | } |
1913 | ||
1914 | static inline void *tx_agg_align(void *data) | |
1915 | { | |
8e1f51bd | 1916 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1917 | } |
1918 | ||
252df8b8 HW |
1919 | static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg) |
1920 | { | |
1921 | list_del(&agg->info_list); | |
1922 | ||
1923 | usb_free_urb(agg->urb); | |
47922fcd | 1924 | put_page(agg->page); |
252df8b8 HW |
1925 | kfree(agg); |
1926 | ||
1927 | atomic_dec(&tp->rx_count); | |
1928 | } | |
1929 | ||
1930 | static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags) | |
1931 | { | |
1932 | struct net_device *netdev = tp->netdev; | |
1933 | int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
d55d7089 | 1934 | unsigned int order = get_order(tp->rx_buf_sz); |
252df8b8 HW |
1935 | struct rx_agg *rx_agg; |
1936 | unsigned long flags; | |
252df8b8 HW |
1937 | |
1938 | rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node); | |
1939 | if (!rx_agg) | |
1940 | return NULL; | |
1941 | ||
47922fcd | 1942 | rx_agg->page = alloc_pages(mflags | __GFP_COMP, order); |
d55d7089 | 1943 | if (!rx_agg->page) |
252df8b8 HW |
1944 | goto free_rx; |
1945 | ||
d55d7089 | 1946 | rx_agg->buffer = page_address(rx_agg->page); |
252df8b8 HW |
1947 | |
1948 | rx_agg->urb = usb_alloc_urb(0, mflags); | |
1949 | if (!rx_agg->urb) | |
1950 | goto free_buf; | |
1951 | ||
1952 | rx_agg->context = tp; | |
1953 | ||
1954 | INIT_LIST_HEAD(&rx_agg->list); | |
1955 | INIT_LIST_HEAD(&rx_agg->info_list); | |
1956 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1957 | list_add_tail(&rx_agg->info_list, &tp->rx_info); | |
1958 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1959 | ||
1960 | atomic_inc(&tp->rx_count); | |
1961 | ||
1962 | return rx_agg; | |
1963 | ||
1964 | free_buf: | |
d55d7089 | 1965 | __free_pages(rx_agg->page, order); |
252df8b8 HW |
1966 | free_rx: |
1967 | kfree(rx_agg); | |
1968 | return NULL; | |
1969 | } | |
1970 | ||
ebc2ec48 | 1971 | static void free_all_mem(struct r8152 *tp) |
1972 | { | |
252df8b8 HW |
1973 | struct rx_agg *agg, *agg_next; |
1974 | unsigned long flags; | |
ebc2ec48 | 1975 | int i; |
1976 | ||
252df8b8 | 1977 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 1978 | |
252df8b8 HW |
1979 | list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list) |
1980 | free_rx_agg(tp, agg); | |
1981 | ||
1982 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1983 | ||
1984 | WARN_ON(atomic_read(&tp->rx_count)); | |
ebc2ec48 | 1985 | |
1986 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1987 | usb_free_urb(tp->tx_info[i].urb); |
1988 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1989 | |
9629e3c0 | 1990 | kfree(tp->tx_info[i].buffer); |
1991 | tp->tx_info[i].buffer = NULL; | |
1992 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1993 | } |
40a82917 | 1994 | |
9629e3c0 | 1995 | usb_free_urb(tp->intr_urb); |
1996 | tp->intr_urb = NULL; | |
40a82917 | 1997 | |
9629e3c0 | 1998 | kfree(tp->intr_buff); |
1999 | tp->intr_buff = NULL; | |
ebc2ec48 | 2000 | } |
2001 | ||
2002 | static int alloc_all_mem(struct r8152 *tp) | |
2003 | { | |
2004 | struct net_device *netdev = tp->netdev; | |
40a82917 | 2005 | struct usb_interface *intf = tp->intf; |
2006 | struct usb_host_interface *alt = intf->cur_altsetting; | |
2007 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 2008 | int node, i; |
ebc2ec48 | 2009 | |
2010 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
2011 | ||
2012 | spin_lock_init(&tp->rx_lock); | |
2013 | spin_lock_init(&tp->tx_lock); | |
252df8b8 | 2014 | INIT_LIST_HEAD(&tp->rx_info); |
ebc2ec48 | 2015 | INIT_LIST_HEAD(&tp->tx_free); |
98d068ab | 2016 | INIT_LIST_HEAD(&tp->rx_done); |
ebc2ec48 | 2017 | skb_queue_head_init(&tp->tx_queue); |
d823ab68 | 2018 | skb_queue_head_init(&tp->rx_queue); |
252df8b8 | 2019 | atomic_set(&tp->rx_count, 0); |
ebc2ec48 | 2020 | |
2021 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
252df8b8 | 2022 | if (!alloc_rx_agg(tp, GFP_KERNEL)) |
ebc2ec48 | 2023 | goto err1; |
ebc2ec48 | 2024 | } |
2025 | ||
2026 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
252df8b8 HW |
2027 | struct urb *urb; |
2028 | u8 *buf; | |
2029 | ||
52aec126 | 2030 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 2031 | if (!buf) |
2032 | goto err1; | |
2033 | ||
2034 | if (buf != tx_agg_align(buf)) { | |
2035 | kfree(buf); | |
52aec126 | 2036 | buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, |
8e1f51bd | 2037 | node); |
ebc2ec48 | 2038 | if (!buf) |
2039 | goto err1; | |
2040 | } | |
2041 | ||
2042 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
2043 | if (!urb) { | |
2044 | kfree(buf); | |
2045 | goto err1; | |
2046 | } | |
2047 | ||
2048 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
2049 | tp->tx_info[i].context = tp; | |
2050 | tp->tx_info[i].urb = urb; | |
2051 | tp->tx_info[i].buffer = buf; | |
2052 | tp->tx_info[i].head = tx_agg_align(buf); | |
2053 | ||
2054 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
2055 | } | |
2056 | ||
40a82917 | 2057 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
2058 | if (!tp->intr_urb) | |
2059 | goto err1; | |
2060 | ||
2061 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
2062 | if (!tp->intr_buff) | |
2063 | goto err1; | |
2064 | ||
2065 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
b67fda9a | 2066 | usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr, |
b209af99 | 2067 | tp->intr_buff, INTBUFSIZE, intr_callback, |
2068 | tp, tp->intr_interval); | |
40a82917 | 2069 | |
ebc2ec48 | 2070 | return 0; |
2071 | ||
2072 | err1: | |
2073 | free_all_mem(tp); | |
2074 | return -ENOMEM; | |
2075 | } | |
2076 | ||
0de98f6c | 2077 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
2078 | { | |
2079 | struct tx_agg *agg = NULL; | |
2080 | unsigned long flags; | |
2081 | ||
21949ab7 | 2082 | if (list_empty(&tp->tx_free)) |
2083 | return NULL; | |
2084 | ||
0de98f6c | 2085 | spin_lock_irqsave(&tp->tx_lock, flags); |
2086 | if (!list_empty(&tp->tx_free)) { | |
2087 | struct list_head *cursor; | |
2088 | ||
2089 | cursor = tp->tx_free.next; | |
2090 | list_del_init(cursor); | |
2091 | agg = list_entry(cursor, struct tx_agg, list); | |
2092 | } | |
2093 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
2094 | ||
2095 | return agg; | |
2096 | } | |
2097 | ||
b209af99 | 2098 | /* r8152_csum_workaround() |
c01ebd6c | 2099 | * The hw limits the value of the transport offset. When the offset is out of |
6128d1bb | 2100 | * range, calculate the checksum by sw. |
2101 | */ | |
2102 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
2103 | struct sk_buff_head *list) | |
2104 | { | |
2105 | if (skb_shinfo(skb)->gso_size) { | |
2106 | netdev_features_t features = tp->netdev->features; | |
1d7a7438 | 2107 | struct sk_buff *segs, *seg, *next; |
6128d1bb | 2108 | struct sk_buff_head seg_list; |
6128d1bb | 2109 | |
a91d45f1 | 2110 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 2111 | segs = skb_gso_segment(skb, features); |
2112 | if (IS_ERR(segs) || !segs) | |
2113 | goto drop; | |
2114 | ||
2115 | __skb_queue_head_init(&seg_list); | |
2116 | ||
1d7a7438 JD |
2117 | skb_list_walk_safe(segs, seg, next) { |
2118 | skb_mark_not_on_list(seg); | |
2119 | __skb_queue_tail(&seg_list, seg); | |
2120 | } | |
6128d1bb | 2121 | |
2122 | skb_queue_splice(&seg_list, list); | |
2123 | dev_kfree_skb(skb); | |
2124 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
2125 | if (skb_checksum_help(skb) < 0) | |
2126 | goto drop; | |
2127 | ||
2128 | __skb_queue_head(list, skb); | |
2129 | } else { | |
2130 | struct net_device_stats *stats; | |
2131 | ||
2132 | drop: | |
2133 | stats = &tp->netdev->stats; | |
2134 | stats->tx_dropped++; | |
2135 | dev_kfree_skb(skb); | |
2136 | } | |
2137 | } | |
2138 | ||
c5554298 | 2139 | static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) |
2140 | { | |
df8a39de | 2141 | if (skb_vlan_tag_present(skb)) { |
c5554298 | 2142 | u32 opts2; |
2143 | ||
df8a39de | 2144 | opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); |
c5554298 | 2145 | desc->opts2 |= cpu_to_le32(opts2); |
2146 | } | |
2147 | } | |
2148 | ||
2149 | static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) | |
2150 | { | |
2151 | u32 opts2 = le32_to_cpu(desc->opts2); | |
2152 | ||
2153 | if (opts2 & RX_VLAN_TAG) | |
2154 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
2155 | swab16(opts2 & 0xffff)); | |
2156 | } | |
2157 | ||
60c89071 | 2158 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
057cc8c9 | 2159 | struct sk_buff *skb, u32 len) |
60c89071 | 2160 | { |
2161 | u32 mss = skb_shinfo(skb)->gso_size; | |
2162 | u32 opts1, opts2 = 0; | |
2163 | int ret = TX_CSUM_SUCCESS; | |
2164 | ||
2165 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
2166 | ||
2167 | opts1 = len | TX_FS | TX_LS; | |
2168 | ||
2169 | if (mss) { | |
057cc8c9 HW |
2170 | u32 transport_offset = (u32)skb_transport_offset(skb); |
2171 | ||
6128d1bb | 2172 | if (transport_offset > GTTCPHO_MAX) { |
2173 | netif_warn(tp, tx_err, tp->netdev, | |
2174 | "Invalid transport offset 0x%x for TSO\n", | |
2175 | transport_offset); | |
2176 | ret = TX_CSUM_TSO; | |
2177 | goto unavailable; | |
2178 | } | |
2179 | ||
6e74d174 | 2180 | switch (vlan_get_protocol(skb)) { |
60c89071 | 2181 | case htons(ETH_P_IP): |
2182 | opts1 |= GTSENDV4; | |
2183 | break; | |
2184 | ||
6128d1bb | 2185 | case htons(ETH_P_IPV6): |
2344120d | 2186 | if (skb_cow_head(skb, 0)) { |
fcb308d5 | 2187 | ret = TX_CSUM_TSO; |
2188 | goto unavailable; | |
2189 | } | |
2344120d | 2190 | tcp_v6_gso_csum_prep(skb); |
6128d1bb | 2191 | opts1 |= GTSENDV6; |
6128d1bb | 2192 | break; |
2193 | ||
60c89071 | 2194 | default: |
2195 | WARN_ON_ONCE(1); | |
2196 | break; | |
2197 | } | |
2198 | ||
2199 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
2200 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
2201 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
057cc8c9 | 2202 | u32 transport_offset = (u32)skb_transport_offset(skb); |
60c89071 | 2203 | u8 ip_protocol; |
5bd23881 | 2204 | |
6128d1bb | 2205 | if (transport_offset > TCPHO_MAX) { |
2206 | netif_warn(tp, tx_err, tp->netdev, | |
2207 | "Invalid transport offset 0x%x\n", | |
2208 | transport_offset); | |
2209 | ret = TX_CSUM_NONE; | |
2210 | goto unavailable; | |
2211 | } | |
2212 | ||
6e74d174 | 2213 | switch (vlan_get_protocol(skb)) { |
5bd23881 | 2214 | case htons(ETH_P_IP): |
2215 | opts2 |= IPV4_CS; | |
2216 | ip_protocol = ip_hdr(skb)->protocol; | |
2217 | break; | |
2218 | ||
2219 | case htons(ETH_P_IPV6): | |
2220 | opts2 |= IPV6_CS; | |
2221 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
2222 | break; | |
2223 | ||
2224 | default: | |
2225 | ip_protocol = IPPROTO_RAW; | |
2226 | break; | |
2227 | } | |
2228 | ||
60c89071 | 2229 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 2230 | opts2 |= TCP_CS; |
60c89071 | 2231 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 2232 | opts2 |= UDP_CS; |
60c89071 | 2233 | else |
5bd23881 | 2234 | WARN_ON_ONCE(1); |
5bd23881 | 2235 | |
60c89071 | 2236 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 2237 | } |
60c89071 | 2238 | |
2239 | desc->opts2 = cpu_to_le32(opts2); | |
2240 | desc->opts1 = cpu_to_le32(opts1); | |
2241 | ||
6128d1bb | 2242 | unavailable: |
60c89071 | 2243 | return ret; |
5bd23881 | 2244 | } |
2245 | ||
b1379d9a | 2246 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
2247 | { | |
d84130a1 | 2248 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 2249 | int remain, ret; |
b1379d9a | 2250 | u8 *tx_data; |
2251 | ||
d84130a1 | 2252 | __skb_queue_head_init(&skb_head); |
0c3121fc | 2253 | spin_lock(&tx_queue->lock); |
d84130a1 | 2254 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 2255 | spin_unlock(&tx_queue->lock); |
d84130a1 | 2256 | |
b1379d9a | 2257 | tx_data = agg->head; |
b209af99 | 2258 | agg->skb_num = 0; |
2259 | agg->skb_len = 0; | |
52aec126 | 2260 | remain = agg_buf_sz; |
b1379d9a | 2261 | |
7937f9e5 | 2262 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 2263 | struct tx_desc *tx_desc; |
2264 | struct sk_buff *skb; | |
2265 | unsigned int len; | |
2266 | ||
d84130a1 | 2267 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 2268 | if (!skb) |
2269 | break; | |
2270 | ||
60c89071 | 2271 | len = skb->len + sizeof(*tx_desc); |
2272 | ||
2273 | if (len > remain) { | |
d84130a1 | 2274 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 2275 | break; |
2276 | } | |
2277 | ||
7937f9e5 | 2278 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 2279 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 2280 | |
057cc8c9 | 2281 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) { |
6128d1bb | 2282 | r8152_csum_workaround(tp, skb, &skb_head); |
2283 | continue; | |
2284 | } | |
60c89071 | 2285 | |
c5554298 | 2286 | rtl_tx_vlan_tag(tx_desc, skb); |
2287 | ||
b1379d9a | 2288 | tx_data += sizeof(*tx_desc); |
2289 | ||
60c89071 | 2290 | len = skb->len; |
2291 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
2292 | struct net_device_stats *stats = &tp->netdev->stats; | |
2293 | ||
2294 | stats->tx_dropped++; | |
2295 | dev_kfree_skb_any(skb); | |
2296 | tx_data -= sizeof(*tx_desc); | |
2297 | continue; | |
2298 | } | |
2299 | ||
2300 | tx_data += len; | |
b1379d9a | 2301 | agg->skb_len += len; |
4c27bf3c | 2302 | agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; |
60c89071 | 2303 | |
b1379d9a | 2304 | dev_kfree_skb_any(skb); |
2305 | ||
52aec126 | 2306 | remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
0b165514 | 2307 | |
9c68011b | 2308 | if (tp->dell_tb_rx_agg_bug) |
0b165514 | 2309 | break; |
b1379d9a | 2310 | } |
2311 | ||
d84130a1 | 2312 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 2313 | spin_lock(&tx_queue->lock); |
d84130a1 | 2314 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 2315 | spin_unlock(&tx_queue->lock); |
d84130a1 | 2316 | } |
2317 | ||
0c3121fc | 2318 | netif_tx_lock(tp->netdev); |
dd1b119c | 2319 | |
2320 | if (netif_queue_stopped(tp->netdev) && | |
2321 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
2322 | netif_wake_queue(tp->netdev); | |
2323 | ||
0c3121fc | 2324 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 2325 | |
0c3121fc | 2326 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 2327 | if (ret < 0) |
2328 | goto out_tx_fill; | |
dd1b119c | 2329 | |
b67fda9a | 2330 | usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out, |
b1379d9a | 2331 | agg->head, (int)(tx_data - (u8 *)agg->head), |
2332 | (usb_complete_t)write_bulk_callback, agg); | |
2333 | ||
0c3121fc | 2334 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 2335 | if (ret < 0) |
0c3121fc | 2336 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 2337 | |
2338 | out_tx_fill: | |
2339 | return ret; | |
b1379d9a | 2340 | } |
2341 | ||
565cab0a | 2342 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
2343 | { | |
2344 | u8 checksum = CHECKSUM_NONE; | |
2345 | u32 opts2, opts3; | |
2346 | ||
19c0f40d | 2347 | if (!(tp->netdev->features & NETIF_F_RXCSUM)) |
565cab0a | 2348 | goto return_result; |
2349 | ||
2350 | opts2 = le32_to_cpu(rx_desc->opts2); | |
2351 | opts3 = le32_to_cpu(rx_desc->opts3); | |
2352 | ||
2353 | if (opts2 & RD_IPV4_CS) { | |
2354 | if (opts3 & IPF) | |
2355 | checksum = CHECKSUM_NONE; | |
ea6499e1 HW |
2356 | else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) |
2357 | checksum = CHECKSUM_UNNECESSARY; | |
2358 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
565cab0a | 2359 | checksum = CHECKSUM_UNNECESSARY; |
b9a321b4 | 2360 | } else if (opts2 & RD_IPV6_CS) { |
6128d1bb | 2361 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) |
2362 | checksum = CHECKSUM_UNNECESSARY; | |
2363 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
2364 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 2365 | } |
2366 | ||
2367 | return_result: | |
2368 | return checksum; | |
2369 | } | |
2370 | ||
47922fcd HW |
2371 | static inline bool rx_count_exceed(struct r8152 *tp) |
2372 | { | |
2373 | return atomic_read(&tp->rx_count) > RTL8152_MAX_RX; | |
2374 | } | |
2375 | ||
2376 | static inline int agg_offset(struct rx_agg *agg, void *addr) | |
2377 | { | |
2378 | return (int)(addr - agg->buffer); | |
2379 | } | |
2380 | ||
2381 | static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags) | |
2382 | { | |
2383 | struct rx_agg *agg, *agg_next, *agg_free = NULL; | |
2384 | unsigned long flags; | |
2385 | ||
2386 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2387 | ||
2388 | list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) { | |
2389 | if (page_count(agg->page) == 1) { | |
2390 | if (!agg_free) { | |
2391 | list_del_init(&agg->list); | |
2392 | agg_free = agg; | |
2393 | continue; | |
2394 | } | |
2395 | if (rx_count_exceed(tp)) { | |
2396 | list_del_init(&agg->list); | |
2397 | free_rx_agg(tp, agg); | |
2398 | } | |
2399 | break; | |
2400 | } | |
2401 | } | |
2402 | ||
2403 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2404 | ||
e4a5017a | 2405 | if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending) |
47922fcd HW |
2406 | agg_free = alloc_rx_agg(tp, mflags); |
2407 | ||
2408 | return agg_free; | |
2409 | } | |
2410 | ||
d823ab68 | 2411 | static int rx_bottom(struct r8152 *tp, int budget) |
ebc2ec48 | 2412 | { |
a5a4f468 | 2413 | unsigned long flags; |
d84130a1 | 2414 | struct list_head *cursor, *next, rx_queue; |
e1a2ca92 | 2415 | int ret = 0, work_done = 0; |
ce594e98 | 2416 | struct napi_struct *napi = &tp->napi; |
d823ab68 | 2417 | |
2418 | if (!skb_queue_empty(&tp->rx_queue)) { | |
2419 | while (work_done < budget) { | |
2420 | struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); | |
2421 | struct net_device *netdev = tp->netdev; | |
2422 | struct net_device_stats *stats = &netdev->stats; | |
2423 | unsigned int pkt_len; | |
2424 | ||
2425 | if (!skb) | |
2426 | break; | |
2427 | ||
2428 | pkt_len = skb->len; | |
ce594e98 | 2429 | napi_gro_receive(napi, skb); |
d823ab68 | 2430 | work_done++; |
2431 | stats->rx_packets++; | |
2432 | stats->rx_bytes += pkt_len; | |
2433 | } | |
2434 | } | |
ebc2ec48 | 2435 | |
d84130a1 | 2436 | if (list_empty(&tp->rx_done)) |
d823ab68 | 2437 | goto out1; |
d84130a1 | 2438 | |
baf33d7a | 2439 | clear_bit(RX_EPROTO, &tp->flags); |
d84130a1 | 2440 | INIT_LIST_HEAD(&rx_queue); |
a5a4f468 | 2441 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 2442 | list_splice_init(&tp->rx_done, &rx_queue); |
2443 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2444 | ||
2445 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 2446 | struct rx_desc *rx_desc; |
47922fcd | 2447 | struct rx_agg *agg, *agg_free; |
43a4478d | 2448 | int len_used = 0; |
2449 | struct urb *urb; | |
2450 | u8 *rx_data; | |
43a4478d | 2451 | |
ebc2ec48 | 2452 | list_del_init(cursor); |
ebc2ec48 | 2453 | |
2454 | agg = list_entry(cursor, struct rx_agg, list); | |
2455 | urb = agg->urb; | |
baf33d7a | 2456 | if (urb->status != 0 || urb->actual_length < ETH_ZLEN) |
0de98f6c | 2457 | goto submit; |
ebc2ec48 | 2458 | |
47922fcd HW |
2459 | agg_free = rtl_get_free_rx(tp, GFP_ATOMIC); |
2460 | ||
d55d7089 HW |
2461 | rx_desc = agg->buffer; |
2462 | rx_data = agg->buffer; | |
7937f9e5 | 2463 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 2464 | |
7937f9e5 | 2465 | while (urb->actual_length > len_used) { |
43a4478d | 2466 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 2467 | struct net_device_stats *stats = &netdev->stats; |
47922fcd | 2468 | unsigned int pkt_len, rx_frag_head_sz; |
43a4478d | 2469 | struct sk_buff *skb; |
2470 | ||
f62c4f38 | 2471 | /* limit the skb numbers for rx_queue */ |
74544458 | 2472 | if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) |
2473 | break; | |
2474 | ||
7937f9e5 | 2475 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 2476 | if (pkt_len < ETH_ZLEN) |
2477 | break; | |
2478 | ||
7937f9e5 | 2479 | len_used += pkt_len; |
2480 | if (urb->actual_length < len_used) | |
2481 | break; | |
2482 | ||
b65c0c9b | 2483 | pkt_len -= ETH_FCS_LEN; |
ebc2ec48 | 2484 | rx_data += sizeof(struct rx_desc); |
2485 | ||
e4a5017a | 2486 | if (!agg_free || tp->rx_copybreak > pkt_len) |
47922fcd HW |
2487 | rx_frag_head_sz = pkt_len; |
2488 | else | |
e4a5017a | 2489 | rx_frag_head_sz = tp->rx_copybreak; |
47922fcd HW |
2490 | |
2491 | skb = napi_alloc_skb(napi, rx_frag_head_sz); | |
ebc2ec48 | 2492 | if (!skb) { |
2493 | stats->rx_dropped++; | |
5e2f7485 | 2494 | goto find_next_rx; |
ebc2ec48 | 2495 | } |
565cab0a | 2496 | |
2497 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
47922fcd HW |
2498 | memcpy(skb->data, rx_data, rx_frag_head_sz); |
2499 | skb_put(skb, rx_frag_head_sz); | |
2500 | pkt_len -= rx_frag_head_sz; | |
2501 | rx_data += rx_frag_head_sz; | |
2502 | if (pkt_len) { | |
2503 | skb_add_rx_frag(skb, 0, agg->page, | |
2504 | agg_offset(agg, rx_data), | |
2505 | pkt_len, | |
2506 | SKB_DATA_ALIGN(pkt_len)); | |
2507 | get_page(agg->page); | |
2508 | } | |
2509 | ||
ebc2ec48 | 2510 | skb->protocol = eth_type_trans(skb, netdev); |
c5554298 | 2511 | rtl_rx_vlan_tag(rx_desc, skb); |
d823ab68 | 2512 | if (work_done < budget) { |
d823ab68 | 2513 | work_done++; |
2514 | stats->rx_packets++; | |
47922fcd | 2515 | stats->rx_bytes += skb->len; |
6636fb31 | 2516 | napi_gro_receive(napi, skb); |
d823ab68 | 2517 | } else { |
2518 | __skb_queue_tail(&tp->rx_queue, skb); | |
2519 | } | |
ebc2ec48 | 2520 | |
5e2f7485 | 2521 | find_next_rx: |
b65c0c9b | 2522 | rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); |
ebc2ec48 | 2523 | rx_desc = (struct rx_desc *)rx_data; |
47922fcd | 2524 | len_used = agg_offset(agg, rx_data); |
7937f9e5 | 2525 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 2526 | } |
2527 | ||
47922fcd HW |
2528 | WARN_ON(!agg_free && page_count(agg->page) > 1); |
2529 | ||
2530 | if (agg_free) { | |
2531 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2532 | if (page_count(agg->page) == 1) { | |
2533 | list_add(&agg_free->list, &tp->rx_used); | |
2534 | } else { | |
2535 | list_add_tail(&agg->list, &tp->rx_used); | |
2536 | agg = agg_free; | |
2537 | urb = agg->urb; | |
2538 | } | |
2539 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2540 | } | |
2541 | ||
0de98f6c | 2542 | submit: |
e1a2ca92 | 2543 | if (!ret) { |
2544 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); | |
2545 | } else { | |
2546 | urb->actual_length = 0; | |
2547 | list_add_tail(&agg->list, next); | |
2548 | } | |
2549 | } | |
2550 | ||
2551 | if (!list_empty(&rx_queue)) { | |
2552 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2553 | list_splice_tail(&rx_queue, &tp->rx_done); | |
2554 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 2555 | } |
d823ab68 | 2556 | |
2557 | out1: | |
2558 | return work_done; | |
ebc2ec48 | 2559 | } |
2560 | ||
2561 | static void tx_bottom(struct r8152 *tp) | |
2562 | { | |
ebc2ec48 | 2563 | int res; |
2564 | ||
b1379d9a | 2565 | do { |
c01ebd6c | 2566 | struct net_device *netdev = tp->netdev; |
b1379d9a | 2567 | struct tx_agg *agg; |
ebc2ec48 | 2568 | |
b1379d9a | 2569 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 2570 | break; |
2571 | ||
b1379d9a | 2572 | agg = r8152_get_tx_agg(tp); |
2573 | if (!agg) | |
ebc2ec48 | 2574 | break; |
ebc2ec48 | 2575 | |
b1379d9a | 2576 | res = r8152_tx_agg_fill(tp, agg); |
c01ebd6c PM |
2577 | if (!res) |
2578 | continue; | |
ebc2ec48 | 2579 | |
c01ebd6c PM |
2580 | if (res == -ENODEV) { |
2581 | rtl_set_unplug(tp); | |
2582 | netif_device_detach(netdev); | |
2583 | } else { | |
2584 | struct net_device_stats *stats = &netdev->stats; | |
2585 | unsigned long flags; | |
05e0f1aa | 2586 | |
c01ebd6c PM |
2587 | netif_warn(tp, tx_err, netdev, |
2588 | "failed tx_urb %d\n", res); | |
2589 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 2590 | |
c01ebd6c PM |
2591 | spin_lock_irqsave(&tp->tx_lock, flags); |
2592 | list_add_tail(&agg->list, &tp->tx_free); | |
2593 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
ebc2ec48 | 2594 | } |
b1379d9a | 2595 | } while (res == 0); |
ebc2ec48 | 2596 | } |
2597 | ||
f3163f1c | 2598 | static void bottom_half(struct tasklet_struct *t) |
ac718b69 | 2599 | { |
f3163f1c | 2600 | struct r8152 *tp = from_tasklet(tp, t, tx_tl); |
d2187f8e | 2601 | |
ebc2ec48 | 2602 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2603 | return; | |
2604 | ||
2605 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 2606 | return; |
ebc2ec48 | 2607 | |
7559fb2f | 2608 | /* When link down, the driver would cancel all bulks. */ |
2609 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 2610 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 2611 | return; |
ebc2ec48 | 2612 | |
d2187f8e | 2613 | clear_bit(SCHEDULE_TASKLET, &tp->flags); |
9451a11c | 2614 | |
0c3121fc | 2615 | tx_bottom(tp); |
ebc2ec48 | 2616 | } |
2617 | ||
d823ab68 | 2618 | static int r8152_poll(struct napi_struct *napi, int budget) |
2619 | { | |
2620 | struct r8152 *tp = container_of(napi, struct r8152, napi); | |
2621 | int work_done; | |
2622 | ||
2623 | work_done = rx_bottom(tp, budget); | |
d823ab68 | 2624 | |
2625 | if (work_done < budget) { | |
a3307f9b | 2626 | if (!napi_complete_done(napi, work_done)) |
2627 | goto out; | |
d823ab68 | 2628 | if (!list_empty(&tp->rx_done)) |
2629 | napi_schedule(napi); | |
2630 | } | |
2631 | ||
a3307f9b | 2632 | out: |
d823ab68 | 2633 | return work_done; |
2634 | } | |
2635 | ||
ebc2ec48 | 2636 | static |
2637 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
2638 | { | |
a0fccd48 | 2639 | int ret; |
2640 | ||
ef827a5b | 2641 | /* The rx would be stopped, so skip submitting */ |
2642 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || | |
2643 | !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) | |
2644 | return 0; | |
2645 | ||
b67fda9a | 2646 | usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in, |
d55d7089 | 2647 | agg->buffer, tp->rx_buf_sz, |
b209af99 | 2648 | (usb_complete_t)read_bulk_callback, agg); |
ebc2ec48 | 2649 | |
a0fccd48 | 2650 | ret = usb_submit_urb(agg->urb, mem_flags); |
2651 | if (ret == -ENODEV) { | |
ffa9fec3 | 2652 | rtl_set_unplug(tp); |
a0fccd48 | 2653 | netif_device_detach(tp->netdev); |
2654 | } else if (ret) { | |
2655 | struct urb *urb = agg->urb; | |
2656 | unsigned long flags; | |
2657 | ||
2658 | urb->actual_length = 0; | |
2659 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2660 | list_add_tail(&agg->list, &tp->rx_done); | |
2661 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
d823ab68 | 2662 | |
2663 | netif_err(tp, rx_err, tp->netdev, | |
2664 | "Couldn't submit rx[%p], ret = %d\n", agg, ret); | |
2665 | ||
2666 | napi_schedule(&tp->napi); | |
a0fccd48 | 2667 | } |
2668 | ||
2669 | return ret; | |
ac718b69 | 2670 | } |
2671 | ||
00a5e360 | 2672 | static void rtl_drop_queued_tx(struct r8152 *tp) |
2673 | { | |
2674 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 2675 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 2676 | struct sk_buff *skb; |
2677 | ||
d84130a1 | 2678 | if (skb_queue_empty(tx_queue)) |
2679 | return; | |
2680 | ||
2681 | __skb_queue_head_init(&skb_head); | |
2685d410 | 2682 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 2683 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 2684 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 2685 | |
2686 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 2687 | dev_kfree_skb(skb); |
2688 | stats->tx_dropped++; | |
2689 | } | |
2690 | } | |
2691 | ||
0290bd29 | 2692 | static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue) |
ac718b69 | 2693 | { |
2694 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 2695 | |
4a8deae2 | 2696 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
37608f3e | 2697 | |
2698 | usb_queue_reset_device(tp->intf); | |
ac718b69 | 2699 | } |
2700 | ||
2701 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
2702 | { | |
2703 | struct r8152 *tp = netdev_priv(netdev); | |
2704 | ||
51d979fa | 2705 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 2706 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 2707 | schedule_delayed_work(&tp->schedule, 0); |
2708 | } | |
ac718b69 | 2709 | } |
2710 | ||
2711 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
2712 | { | |
2713 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 2714 | u32 mc_filter[2]; /* Multicast hash filter */ |
2715 | __le32 tmp[2]; | |
ac718b69 | 2716 | u32 ocp_data; |
2717 | ||
ac718b69 | 2718 | netif_stop_queue(netdev); |
2719 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2720 | ocp_data &= ~RCR_ACPT_ALL; | |
2721 | ocp_data |= RCR_AB | RCR_APM; | |
2722 | ||
2723 | if (netdev->flags & IFF_PROMISC) { | |
2724 | /* Unconditionally log net taps. */ | |
2725 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
2726 | ocp_data |= RCR_AM | RCR_AAP; | |
b209af99 | 2727 | mc_filter[1] = 0xffffffff; |
2728 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 2729 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
2730 | (netdev->flags & IFF_ALLMULTI)) { | |
2731 | /* Too many to filter perfectly -- accept all multicasts. */ | |
2732 | ocp_data |= RCR_AM; | |
b209af99 | 2733 | mc_filter[1] = 0xffffffff; |
2734 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 2735 | } else { |
2736 | struct netdev_hw_addr *ha; | |
2737 | ||
b209af99 | 2738 | mc_filter[1] = 0; |
2739 | mc_filter[0] = 0; | |
ac718b69 | 2740 | netdev_for_each_mc_addr(ha, netdev) { |
2741 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
b209af99 | 2742 | |
ac718b69 | 2743 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
2744 | ocp_data |= RCR_AM; | |
2745 | } | |
2746 | } | |
2747 | ||
31787f53 | 2748 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
2749 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 2750 | |
31787f53 | 2751 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 2752 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
2753 | netif_wake_queue(netdev); | |
ac718b69 | 2754 | } |
2755 | ||
a5e31255 | 2756 | static netdev_features_t |
2757 | rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, | |
2758 | netdev_features_t features) | |
2759 | { | |
2760 | u32 mss = skb_shinfo(skb)->gso_size; | |
2761 | int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; | |
a5e31255 | 2762 | |
057cc8c9 HW |
2763 | if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && |
2764 | skb_transport_offset(skb) > max_offset) | |
a188222b | 2765 | features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); |
a5e31255 | 2766 | else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) |
2767 | features &= ~NETIF_F_GSO_MASK; | |
2768 | ||
2769 | return features; | |
2770 | } | |
2771 | ||
ac718b69 | 2772 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, |
b209af99 | 2773 | struct net_device *netdev) |
ac718b69 | 2774 | { |
2775 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 2776 | |
ebc2ec48 | 2777 | skb_tx_timestamp(skb); |
ac718b69 | 2778 | |
61598788 | 2779 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 2780 | |
0c3121fc | 2781 | if (!list_empty(&tp->tx_free)) { |
2782 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
d2187f8e | 2783 | set_bit(SCHEDULE_TASKLET, &tp->flags); |
0c3121fc | 2784 | schedule_delayed_work(&tp->schedule, 0); |
2785 | } else { | |
2786 | usb_mark_last_busy(tp->udev); | |
d2187f8e | 2787 | tasklet_schedule(&tp->tx_tl); |
0c3121fc | 2788 | } |
b209af99 | 2789 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { |
dd1b119c | 2790 | netif_stop_queue(netdev); |
b209af99 | 2791 | } |
dd1b119c | 2792 | |
ac718b69 | 2793 | return NETDEV_TX_OK; |
2794 | } | |
2795 | ||
2796 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
2797 | { | |
195aae32 | 2798 | u32 ocp_data; |
ac718b69 | 2799 | |
2800 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
2801 | ocp_data &= ~FMC_FCR_MCU_EN; | |
2802 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2803 | ocp_data |= FMC_FCR_MCU_EN; | |
2804 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2805 | } | |
2806 | ||
2807 | static void rtl8152_nic_reset(struct r8152 *tp) | |
2808 | { | |
195aae32 HW |
2809 | u32 ocp_data; |
2810 | int i; | |
ac718b69 | 2811 | |
195aae32 HW |
2812 | switch (tp->version) { |
2813 | case RTL_TEST_01: | |
2814 | case RTL_VER_10: | |
2815 | case RTL_VER_11: | |
2816 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
2817 | ocp_data &= ~CR_TE; | |
2818 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
2819 | ||
2820 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); | |
2821 | ocp_data &= ~BMU_RESET_EP_IN; | |
2822 | ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
2823 | ||
2824 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
2825 | ocp_data |= CDC_ECM_EN; | |
2826 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2827 | ||
2828 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
2829 | ocp_data &= ~CR_RE; | |
2830 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
2831 | ||
2832 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); | |
2833 | ocp_data |= BMU_RESET_EP_IN; | |
2834 | ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
2835 | ||
2836 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
2837 | ocp_data &= ~CDC_ECM_EN; | |
2838 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2839 | break; | |
ac718b69 | 2840 | |
195aae32 HW |
2841 | default: |
2842 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
2843 | ||
2844 | for (i = 0; i < 1000; i++) { | |
2845 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
2846 | break; | |
2847 | usleep_range(100, 400); | |
2848 | } | |
2849 | break; | |
ac718b69 | 2850 | } |
2851 | } | |
2852 | ||
dd1b119c | 2853 | static void set_tx_qlen(struct r8152 *tp) |
2854 | { | |
67ce1a80 | 2855 | tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc)); |
dd1b119c | 2856 | } |
2857 | ||
195aae32 | 2858 | static inline u16 rtl8152_get_speed(struct r8152 *tp) |
ac718b69 | 2859 | { |
195aae32 | 2860 | return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); |
ac718b69 | 2861 | } |
2862 | ||
40fa7568 | 2863 | static void rtl_eee_plus_en(struct r8152 *tp, bool enable) |
ac718b69 | 2864 | { |
ebc2ec48 | 2865 | u32 ocp_data; |
ac718b69 | 2866 | |
40fa7568 HW |
2867 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
2868 | if (enable) | |
ebc2ec48 | 2869 | ocp_data |= EEEP_CR_EEEP_TX; |
40fa7568 | 2870 | else |
ebc2ec48 | 2871 | ocp_data &= ~EEEP_CR_EEEP_TX; |
40fa7568 HW |
2872 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2873 | } | |
2874 | ||
2875 | static void rtl_set_eee_plus(struct r8152 *tp) | |
2876 | { | |
2877 | if (rtl8152_get_speed(tp) & _10bps) | |
2878 | rtl_eee_plus_en(tp, true); | |
2879 | else | |
2880 | rtl_eee_plus_en(tp, false); | |
507605a8 | 2881 | } |
2882 | ||
00a5e360 | 2883 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
2884 | { | |
2885 | u32 ocp_data; | |
2886 | ||
2887 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
2888 | if (enable) | |
2889 | ocp_data |= RXDY_GATED_EN; | |
2890 | else | |
2891 | ocp_data &= ~RXDY_GATED_EN; | |
2892 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
2893 | } | |
2894 | ||
445f7f4d | 2895 | static int rtl_start_rx(struct r8152 *tp) |
2896 | { | |
252df8b8 HW |
2897 | struct rx_agg *agg, *agg_next; |
2898 | struct list_head tmp_list; | |
2899 | unsigned long flags; | |
47922fcd | 2900 | int ret = 0, i = 0; |
445f7f4d | 2901 | |
252df8b8 | 2902 | INIT_LIST_HEAD(&tmp_list); |
445f7f4d | 2903 | |
252df8b8 | 2904 | spin_lock_irqsave(&tp->rx_lock, flags); |
7bcf4f60 | 2905 | |
252df8b8 | 2906 | INIT_LIST_HEAD(&tp->rx_done); |
47922fcd | 2907 | INIT_LIST_HEAD(&tp->rx_used); |
7bcf4f60 | 2908 | |
252df8b8 | 2909 | list_splice_init(&tp->rx_info, &tmp_list); |
7bcf4f60 | 2910 | |
252df8b8 | 2911 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
7bcf4f60 | 2912 | |
252df8b8 HW |
2913 | list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { |
2914 | INIT_LIST_HEAD(&agg->list); | |
2915 | ||
47922fcd HW |
2916 | /* Only RTL8152_MAX_RX rx_agg need to be submitted. */ |
2917 | if (++i > RTL8152_MAX_RX) { | |
2918 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2919 | list_add_tail(&agg->list, &tp->rx_used); | |
2920 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2921 | } else if (unlikely(ret < 0)) { | |
2922 | spin_lock_irqsave(&tp->rx_lock, flags); | |
252df8b8 | 2923 | list_add_tail(&agg->list, &tp->rx_done); |
47922fcd HW |
2924 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
2925 | } else { | |
252df8b8 | 2926 | ret = r8152_submit_rx(tp, agg, GFP_KERNEL); |
47922fcd | 2927 | } |
7bcf4f60 | 2928 | } |
2929 | ||
252df8b8 HW |
2930 | spin_lock_irqsave(&tp->rx_lock, flags); |
2931 | WARN_ON(!list_empty(&tp->rx_info)); | |
2932 | list_splice(&tmp_list, &tp->rx_info); | |
2933 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2934 | ||
445f7f4d | 2935 | return ret; |
2936 | } | |
2937 | ||
2938 | static int rtl_stop_rx(struct r8152 *tp) | |
2939 | { | |
252df8b8 HW |
2940 | struct rx_agg *agg, *agg_next; |
2941 | struct list_head tmp_list; | |
2942 | unsigned long flags; | |
2943 | ||
2944 | INIT_LIST_HEAD(&tmp_list); | |
2945 | ||
2946 | /* The usb_kill_urb() couldn't be used in atomic. | |
2947 | * Therefore, move the list of rx_info to a tmp one. | |
2948 | * Then, list_for_each_entry_safe could be used without | |
2949 | * spin lock. | |
2950 | */ | |
2951 | ||
2952 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2953 | list_splice_init(&tp->rx_info, &tmp_list); | |
2954 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2955 | ||
47922fcd HW |
2956 | list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { |
2957 | /* At least RTL8152_MAX_RX rx_agg have the page_count being | |
2958 | * equal to 1, so the other ones could be freed safely. | |
2959 | */ | |
2960 | if (page_count(agg->page) > 1) | |
2961 | free_rx_agg(tp, agg); | |
2962 | else | |
2963 | usb_kill_urb(agg->urb); | |
2964 | } | |
445f7f4d | 2965 | |
252df8b8 HW |
2966 | /* Move back the list of temp to the rx_info */ |
2967 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2968 | WARN_ON(!list_empty(&tp->rx_info)); | |
2969 | list_splice(&tmp_list, &tp->rx_info); | |
2970 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
445f7f4d | 2971 | |
d823ab68 | 2972 | while (!skb_queue_empty(&tp->rx_queue)) |
2973 | dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); | |
2974 | ||
445f7f4d | 2975 | return 0; |
2976 | } | |
2977 | ||
5133bcc7 HW |
2978 | static void rtl_set_ifg(struct r8152 *tp, u16 speed) |
2979 | { | |
2980 | u32 ocp_data; | |
2981 | ||
2982 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
2983 | ocp_data &= ~IFG_MASK; | |
2984 | if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) { | |
2985 | ocp_data |= IFG_144NS; | |
2986 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); | |
2987 | ||
2988 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); | |
2989 | ocp_data &= ~TX10MIDLE_EN; | |
2990 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); | |
2991 | } else { | |
2992 | ocp_data |= IFG_96NS; | |
2993 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); | |
2994 | ||
2995 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); | |
2996 | ocp_data |= TX10MIDLE_EN; | |
2997 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); | |
2998 | } | |
2999 | } | |
3000 | ||
9fae5418 HW |
3001 | static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) |
3002 | { | |
3003 | ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, | |
3004 | OWN_UPDATE | OWN_CLEAR); | |
3005 | } | |
3006 | ||
507605a8 | 3007 | static int rtl_enable(struct r8152 *tp) |
3008 | { | |
3009 | u32 ocp_data; | |
ac718b69 | 3010 | |
3011 | r8152b_reset_packet_filter(tp); | |
3012 | ||
3013 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
3014 | ocp_data |= CR_RE | CR_TE; | |
3015 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
3016 | ||
9fae5418 HW |
3017 | switch (tp->version) { |
3018 | case RTL_VER_08: | |
3019 | case RTL_VER_09: | |
195aae32 | 3020 | case RTL_VER_14: |
9fae5418 HW |
3021 | r8153b_rx_agg_chg_indicate(tp); |
3022 | break; | |
3023 | default: | |
3024 | break; | |
3025 | } | |
3026 | ||
00a5e360 | 3027 | rxdy_gated_en(tp, false); |
ac718b69 | 3028 | |
aa2e0926 | 3029 | return 0; |
ac718b69 | 3030 | } |
3031 | ||
507605a8 | 3032 | static int rtl8152_enable(struct r8152 *tp) |
3033 | { | |
6871438c | 3034 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3035 | return -ENODEV; | |
3036 | ||
507605a8 | 3037 | set_tx_qlen(tp); |
3038 | rtl_set_eee_plus(tp); | |
3039 | ||
3040 | return rtl_enable(tp); | |
3041 | } | |
3042 | ||
464ec10a | 3043 | static void r8153_set_rx_early_timeout(struct r8152 *tp) |
43779f8d | 3044 | { |
464ec10a | 3045 | u32 ocp_data = tp->coalesce / 8; |
43779f8d | 3046 | |
65b82d69 | 3047 | switch (tp->version) { |
3048 | case RTL_VER_03: | |
3049 | case RTL_VER_04: | |
3050 | case RTL_VER_05: | |
3051 | case RTL_VER_06: | |
3052 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, | |
3053 | ocp_data); | |
3054 | break; | |
3055 | ||
3056 | case RTL_VER_08: | |
3057 | case RTL_VER_09: | |
195aae32 | 3058 | case RTL_VER_14: |
65b82d69 | 3059 | /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout |
3060 | * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. | |
3061 | */ | |
3062 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, | |
3063 | 128 / 8); | |
3064 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, | |
3065 | ocp_data); | |
65b82d69 | 3066 | break; |
3067 | ||
195aae32 HW |
3068 | case RTL_VER_10: |
3069 | case RTL_VER_11: | |
3070 | case RTL_VER_12: | |
3071 | case RTL_VER_13: | |
3072 | case RTL_VER_15: | |
3073 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, | |
3074 | 640 / 8); | |
3075 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, | |
3076 | ocp_data); | |
3077 | r8153b_rx_agg_chg_indicate(tp); | |
3078 | break; | |
3079 | ||
65b82d69 | 3080 | default: |
3081 | break; | |
3082 | } | |
464ec10a | 3083 | } |
3084 | ||
3085 | static void r8153_set_rx_early_size(struct r8152 *tp) | |
3086 | { | |
ec5791c2 | 3087 | u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu); |
464ec10a | 3088 | |
65b82d69 | 3089 | switch (tp->version) { |
3090 | case RTL_VER_03: | |
3091 | case RTL_VER_04: | |
3092 | case RTL_VER_05: | |
3093 | case RTL_VER_06: | |
3094 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, | |
3095 | ocp_data / 4); | |
3096 | break; | |
3097 | case RTL_VER_08: | |
3098 | case RTL_VER_09: | |
195aae32 HW |
3099 | case RTL_VER_14: |
3100 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, | |
3101 | ocp_data / 8); | |
3102 | break; | |
3103 | case RTL_TEST_01: | |
3104 | case RTL_VER_10: | |
3105 | case RTL_VER_11: | |
3106 | case RTL_VER_12: | |
3107 | case RTL_VER_13: | |
3108 | case RTL_VER_15: | |
65b82d69 | 3109 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, |
3110 | ocp_data / 8); | |
195aae32 | 3111 | r8153b_rx_agg_chg_indicate(tp); |
65b82d69 | 3112 | break; |
3113 | default: | |
3114 | WARN_ON_ONCE(1); | |
3115 | break; | |
3116 | } | |
43779f8d | 3117 | } |
3118 | ||
3119 | static int rtl8153_enable(struct r8152 *tp) | |
3120 | { | |
195aae32 HW |
3121 | u32 ocp_data; |
3122 | ||
6871438c | 3123 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3124 | return -ENODEV; | |
3125 | ||
43779f8d | 3126 | set_tx_qlen(tp); |
3127 | rtl_set_eee_plus(tp); | |
464ec10a | 3128 | r8153_set_rx_early_timeout(tp); |
3129 | r8153_set_rx_early_size(tp); | |
43779f8d | 3130 | |
5133bcc7 HW |
3131 | rtl_set_ifg(tp, rtl8152_get_speed(tp)); |
3132 | ||
195aae32 HW |
3133 | switch (tp->version) { |
3134 | case RTL_VER_09: | |
3135 | case RTL_VER_14: | |
f99cd20e HW |
3136 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); |
3137 | ocp_data &= ~FC_PATCH_TASK; | |
3138 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
3139 | usleep_range(1000, 2000); | |
3140 | ocp_data |= FC_PATCH_TASK; | |
3141 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
195aae32 HW |
3142 | break; |
3143 | default: | |
3144 | break; | |
f99cd20e HW |
3145 | } |
3146 | ||
43779f8d | 3147 | return rtl_enable(tp); |
3148 | } | |
3149 | ||
d70b1137 | 3150 | static void rtl_disable(struct r8152 *tp) |
ac718b69 | 3151 | { |
ebc2ec48 | 3152 | u32 ocp_data; |
3153 | int i; | |
ac718b69 | 3154 | |
6871438c | 3155 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
3156 | rtl_drop_queued_tx(tp); | |
3157 | return; | |
3158 | } | |
3159 | ||
ac718b69 | 3160 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
3161 | ocp_data &= ~RCR_ACPT_ALL; | |
3162 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3163 | ||
00a5e360 | 3164 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 3165 | |
3166 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
3167 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 3168 | |
00a5e360 | 3169 | rxdy_gated_en(tp, true); |
ac718b69 | 3170 | |
3171 | for (i = 0; i < 1000; i++) { | |
3172 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3173 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
3174 | break; | |
8ddfa077 | 3175 | usleep_range(1000, 2000); |
ac718b69 | 3176 | } |
3177 | ||
3178 | for (i = 0; i < 1000; i++) { | |
3179 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
3180 | break; | |
8ddfa077 | 3181 | usleep_range(1000, 2000); |
ac718b69 | 3182 | } |
3183 | ||
445f7f4d | 3184 | rtl_stop_rx(tp); |
ac718b69 | 3185 | |
3186 | rtl8152_nic_reset(tp); | |
3187 | } | |
3188 | ||
00a5e360 | 3189 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
3190 | { | |
3191 | u32 ocp_data; | |
3192 | ||
3193 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
3194 | if (enable) | |
3195 | ocp_data |= POWER_CUT; | |
3196 | else | |
3197 | ocp_data &= ~POWER_CUT; | |
3198 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
3199 | ||
3200 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
3201 | ocp_data &= ~RESUME_INDICATE; | |
3202 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 3203 | } |
3204 | ||
c5554298 | 3205 | static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) |
3206 | { | |
3207 | u32 ocp_data; | |
3208 | ||
195aae32 HW |
3209 | switch (tp->version) { |
3210 | case RTL_VER_01: | |
3211 | case RTL_VER_02: | |
3212 | case RTL_VER_03: | |
3213 | case RTL_VER_04: | |
3214 | case RTL_VER_05: | |
3215 | case RTL_VER_06: | |
3216 | case RTL_VER_07: | |
3217 | case RTL_VER_08: | |
3218 | case RTL_VER_09: | |
3219 | case RTL_VER_14: | |
3220 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
3221 | if (enable) | |
3222 | ocp_data |= CPCR_RX_VLAN; | |
3223 | else | |
3224 | ocp_data &= ~CPCR_RX_VLAN; | |
3225 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
3226 | break; | |
3227 | ||
3228 | case RTL_TEST_01: | |
3229 | case RTL_VER_10: | |
3230 | case RTL_VER_11: | |
3231 | case RTL_VER_12: | |
3232 | case RTL_VER_13: | |
3233 | case RTL_VER_15: | |
3234 | default: | |
3235 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1); | |
3236 | if (enable) | |
3237 | ocp_data |= OUTER_VLAN | INNER_VLAN; | |
3238 | else | |
3239 | ocp_data &= ~(OUTER_VLAN | INNER_VLAN); | |
3240 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data); | |
3241 | break; | |
3242 | } | |
c5554298 | 3243 | } |
3244 | ||
3245 | static int rtl8152_set_features(struct net_device *dev, | |
3246 | netdev_features_t features) | |
3247 | { | |
3248 | netdev_features_t changed = features ^ dev->features; | |
3249 | struct r8152 *tp = netdev_priv(dev); | |
405f8a0e | 3250 | int ret; |
3251 | ||
3252 | ret = usb_autopm_get_interface(tp->intf); | |
3253 | if (ret < 0) | |
3254 | goto out; | |
c5554298 | 3255 | |
b5403273 | 3256 | mutex_lock(&tp->control); |
3257 | ||
c5554298 | 3258 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) { |
3259 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
3260 | rtl_rx_vlan_en(tp, true); | |
3261 | else | |
3262 | rtl_rx_vlan_en(tp, false); | |
3263 | } | |
3264 | ||
b5403273 | 3265 | mutex_unlock(&tp->control); |
3266 | ||
405f8a0e | 3267 | usb_autopm_put_interface(tp->intf); |
3268 | ||
3269 | out: | |
3270 | return ret; | |
c5554298 | 3271 | } |
3272 | ||
21ff2e89 | 3273 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
3274 | ||
3275 | static u32 __rtl_get_wol(struct r8152 *tp) | |
3276 | { | |
3277 | u32 ocp_data; | |
3278 | u32 wolopts = 0; | |
3279 | ||
21ff2e89 | 3280 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); |
3281 | if (ocp_data & LINK_ON_WAKE_EN) | |
3282 | wolopts |= WAKE_PHY; | |
3283 | ||
3284 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
3285 | if (ocp_data & UWF_EN) | |
3286 | wolopts |= WAKE_UCAST; | |
3287 | if (ocp_data & BWF_EN) | |
3288 | wolopts |= WAKE_BCAST; | |
3289 | if (ocp_data & MWF_EN) | |
3290 | wolopts |= WAKE_MCAST; | |
3291 | ||
3292 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
3293 | if (ocp_data & MAGIC_EN) | |
3294 | wolopts |= WAKE_MAGIC; | |
3295 | ||
3296 | return wolopts; | |
3297 | } | |
3298 | ||
3299 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
3300 | { | |
3301 | u32 ocp_data; | |
3302 | ||
3303 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
3304 | ||
3305 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
3306 | ocp_data &= ~LINK_ON_WAKE_EN; | |
3307 | if (wolopts & WAKE_PHY) | |
3308 | ocp_data |= LINK_ON_WAKE_EN; | |
3309 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
3310 | ||
3311 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
92f7d07d | 3312 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); |
21ff2e89 | 3313 | if (wolopts & WAKE_UCAST) |
3314 | ocp_data |= UWF_EN; | |
3315 | if (wolopts & WAKE_BCAST) | |
3316 | ocp_data |= BWF_EN; | |
3317 | if (wolopts & WAKE_MCAST) | |
3318 | ocp_data |= MWF_EN; | |
21ff2e89 | 3319 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); |
3320 | ||
3321 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
3322 | ||
3323 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
3324 | ocp_data &= ~MAGIC_EN; | |
3325 | if (wolopts & WAKE_MAGIC) | |
3326 | ocp_data |= MAGIC_EN; | |
3327 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
3328 | ||
3329 | if (wolopts & WAKE_ANY) | |
3330 | device_set_wakeup_enable(&tp->udev->dev, true); | |
3331 | else | |
3332 | device_set_wakeup_enable(&tp->udev->dev, false); | |
3333 | } | |
3334 | ||
195aae32 HW |
3335 | static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable) |
3336 | { | |
3337 | u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); | |
3338 | ||
3339 | /* MAC clock speed down */ | |
3340 | if (enable) | |
3341 | ocp_data |= MAC_CLK_SPDWN_EN; | |
3342 | else | |
3343 | ocp_data &= ~MAC_CLK_SPDWN_EN; | |
3344 | ||
3345 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); | |
3346 | } | |
3347 | ||
3348 | static void r8156_mac_clk_spd(struct r8152 *tp, bool enable) | |
3349 | { | |
3350 | u32 ocp_data; | |
3351 | ||
3352 | /* MAC clock speed down */ | |
3353 | if (enable) { | |
3354 | /* aldps_spdwn_ratio, tp10_spdwn_ratio */ | |
3355 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, | |
3356 | 0x0403); | |
3357 | ||
3358 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); | |
3359 | ocp_data &= ~EEE_SPDWN_RATIO_MASK; | |
3360 | ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */ | |
3361 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); | |
3362 | } else { | |
3363 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); | |
3364 | ocp_data &= ~MAC_CLK_SPDWN_EN; | |
3365 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); | |
3366 | } | |
3367 | } | |
3368 | ||
b214396f | 3369 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
3370 | { | |
3371 | u8 u1u2[8]; | |
3372 | ||
3373 | if (enable) | |
3374 | memset(u1u2, 0xff, sizeof(u1u2)); | |
3375 | else | |
3376 | memset(u1u2, 0x00, sizeof(u1u2)); | |
3377 | ||
3378 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
3379 | } | |
3380 | ||
65b82d69 | 3381 | static void r8153b_u1u2en(struct r8152 *tp, bool enable) |
3382 | { | |
3383 | u32 ocp_data; | |
3384 | ||
3385 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); | |
3386 | if (enable) | |
3387 | ocp_data |= LPM_U1U2_EN; | |
3388 | else | |
3389 | ocp_data &= ~LPM_U1U2_EN; | |
3390 | ||
3391 | ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); | |
3392 | } | |
3393 | ||
b214396f | 3394 | static void r8153_u2p3en(struct r8152 *tp, bool enable) |
3395 | { | |
3396 | u32 ocp_data; | |
3397 | ||
3398 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
3cb3234e | 3399 | if (enable) |
b214396f | 3400 | ocp_data |= U2P3_ENABLE; |
3401 | else | |
3402 | ocp_data &= ~U2P3_ENABLE; | |
3403 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
3404 | } | |
3405 | ||
0e5b36bc | 3406 | static void r8153b_ups_flags(struct r8152 *tp) |
65b82d69 | 3407 | { |
0e5b36bc HW |
3408 | u32 ups_flags = 0; |
3409 | ||
3410 | if (tp->ups_info.green) | |
3411 | ups_flags |= UPS_FLAGS_EN_GREEN; | |
3412 | ||
3413 | if (tp->ups_info.aldps) | |
3414 | ups_flags |= UPS_FLAGS_EN_ALDPS; | |
3415 | ||
3416 | if (tp->ups_info.eee) | |
3417 | ups_flags |= UPS_FLAGS_EN_EEE; | |
3418 | ||
3419 | if (tp->ups_info.flow_control) | |
3420 | ups_flags |= UPS_FLAGS_EN_FLOW_CTR; | |
3421 | ||
3422 | if (tp->ups_info.eee_ckdiv) | |
3423 | ups_flags |= UPS_FLAGS_EN_EEE_CKDIV; | |
3424 | ||
3425 | if (tp->ups_info.eee_cmod_lv) | |
3426 | ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN; | |
3427 | ||
195aae32 HW |
3428 | if (tp->ups_info.r_tune) |
3429 | ups_flags |= UPS_FLAGS_R_TUNE; | |
3430 | ||
0e5b36bc HW |
3431 | if (tp->ups_info._10m_ckdiv) |
3432 | ups_flags |= UPS_FLAGS_EN_10M_CKDIV; | |
3433 | ||
3434 | if (tp->ups_info.eee_plloff_100) | |
3435 | ups_flags |= UPS_FLAGS_EEE_PLLOFF_100; | |
65b82d69 | 3436 | |
0e5b36bc HW |
3437 | if (tp->ups_info.eee_plloff_giga) |
3438 | ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA; | |
3439 | ||
3440 | if (tp->ups_info._250m_ckdiv) | |
3441 | ups_flags |= UPS_FLAGS_250M_CKDIV; | |
3442 | ||
3443 | if (tp->ups_info.ctap_short_off) | |
3444 | ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS; | |
3445 | ||
3446 | switch (tp->ups_info.speed_duplex) { | |
3447 | case NWAY_10M_HALF: | |
3448 | ups_flags |= ups_flags_speed(1); | |
3449 | break; | |
3450 | case NWAY_10M_FULL: | |
3451 | ups_flags |= ups_flags_speed(2); | |
3452 | break; | |
3453 | case NWAY_100M_HALF: | |
3454 | ups_flags |= ups_flags_speed(3); | |
3455 | break; | |
3456 | case NWAY_100M_FULL: | |
3457 | ups_flags |= ups_flags_speed(4); | |
3458 | break; | |
3459 | case NWAY_1000M_FULL: | |
3460 | ups_flags |= ups_flags_speed(5); | |
3461 | break; | |
3462 | case FORCE_10M_HALF: | |
3463 | ups_flags |= ups_flags_speed(6); | |
3464 | break; | |
3465 | case FORCE_10M_FULL: | |
3466 | ups_flags |= ups_flags_speed(7); | |
3467 | break; | |
3468 | case FORCE_100M_HALF: | |
3469 | ups_flags |= ups_flags_speed(8); | |
3470 | break; | |
3471 | case FORCE_100M_FULL: | |
3472 | ups_flags |= ups_flags_speed(9); | |
3473 | break; | |
3474 | default: | |
3475 | break; | |
3476 | } | |
3477 | ||
3478 | ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); | |
65b82d69 | 3479 | } |
3480 | ||
195aae32 HW |
3481 | static void r8156_ups_flags(struct r8152 *tp) |
3482 | { | |
3483 | u32 ups_flags = 0; | |
3484 | ||
3485 | if (tp->ups_info.green) | |
3486 | ups_flags |= UPS_FLAGS_EN_GREEN; | |
3487 | ||
3488 | if (tp->ups_info.aldps) | |
3489 | ups_flags |= UPS_FLAGS_EN_ALDPS; | |
3490 | ||
3491 | if (tp->ups_info.eee) | |
3492 | ups_flags |= UPS_FLAGS_EN_EEE; | |
3493 | ||
3494 | if (tp->ups_info.flow_control) | |
3495 | ups_flags |= UPS_FLAGS_EN_FLOW_CTR; | |
3496 | ||
3497 | if (tp->ups_info.eee_ckdiv) | |
3498 | ups_flags |= UPS_FLAGS_EN_EEE_CKDIV; | |
3499 | ||
3500 | if (tp->ups_info._10m_ckdiv) | |
3501 | ups_flags |= UPS_FLAGS_EN_10M_CKDIV; | |
3502 | ||
3503 | if (tp->ups_info.eee_plloff_100) | |
3504 | ups_flags |= UPS_FLAGS_EEE_PLLOFF_100; | |
3505 | ||
3506 | if (tp->ups_info.eee_plloff_giga) | |
3507 | ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA; | |
3508 | ||
3509 | if (tp->ups_info._250m_ckdiv) | |
3510 | ups_flags |= UPS_FLAGS_250M_CKDIV; | |
3511 | ||
3512 | switch (tp->ups_info.speed_duplex) { | |
3513 | case FORCE_10M_HALF: | |
3514 | ups_flags |= ups_flags_speed(0); | |
3515 | break; | |
3516 | case FORCE_10M_FULL: | |
3517 | ups_flags |= ups_flags_speed(1); | |
3518 | break; | |
3519 | case FORCE_100M_HALF: | |
3520 | ups_flags |= ups_flags_speed(2); | |
3521 | break; | |
3522 | case FORCE_100M_FULL: | |
3523 | ups_flags |= ups_flags_speed(3); | |
3524 | break; | |
3525 | case NWAY_10M_HALF: | |
3526 | ups_flags |= ups_flags_speed(4); | |
3527 | break; | |
3528 | case NWAY_10M_FULL: | |
3529 | ups_flags |= ups_flags_speed(5); | |
3530 | break; | |
3531 | case NWAY_100M_HALF: | |
3532 | ups_flags |= ups_flags_speed(6); | |
3533 | break; | |
3534 | case NWAY_100M_FULL: | |
3535 | ups_flags |= ups_flags_speed(7); | |
3536 | break; | |
3537 | case NWAY_1000M_FULL: | |
3538 | ups_flags |= ups_flags_speed(8); | |
3539 | break; | |
3540 | case NWAY_2500M_FULL: | |
3541 | ups_flags |= ups_flags_speed(9); | |
3542 | break; | |
3543 | default: | |
3544 | break; | |
3545 | } | |
3546 | ||
3547 | switch (tp->ups_info.lite_mode) { | |
3548 | case 1: | |
3549 | ups_flags |= 0 << 5; | |
3550 | break; | |
3551 | case 2: | |
3552 | ups_flags |= 2 << 5; | |
3553 | break; | |
3554 | case 0: | |
3555 | default: | |
3556 | ups_flags |= 1 << 5; | |
3557 | break; | |
3558 | } | |
3559 | ||
3560 | ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); | |
3561 | } | |
3562 | ||
40fa7568 | 3563 | static void rtl_green_en(struct r8152 *tp, bool enable) |
65b82d69 | 3564 | { |
3565 | u16 data; | |
3566 | ||
40fa7568 HW |
3567 | data = sram_read(tp, SRAM_GREEN_CFG); |
3568 | if (enable) | |
3569 | data |= GREEN_ETH_EN; | |
3570 | else | |
3571 | data &= ~GREEN_ETH_EN; | |
3572 | sram_write(tp, SRAM_GREEN_CFG, data); | |
3573 | ||
3574 | tp->ups_info.green = enable; | |
3575 | } | |
3576 | ||
3577 | static void r8153b_green_en(struct r8152 *tp, bool enable) | |
3578 | { | |
65b82d69 | 3579 | if (enable) { |
3580 | sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ | |
3581 | sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ | |
3582 | sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ | |
3583 | } else { | |
3584 | sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ | |
3585 | sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ | |
3586 | sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ | |
3587 | } | |
3588 | ||
40fa7568 | 3589 | rtl_green_en(tp, true); |
65b82d69 | 3590 | } |
3591 | ||
c564b871 | 3592 | static u16 r8153_phy_status(struct r8152 *tp, u16 desired) |
3593 | { | |
3594 | u16 data; | |
3595 | int i; | |
3596 | ||
3597 | for (i = 0; i < 500; i++) { | |
3598 | data = ocp_reg_read(tp, OCP_PHY_STATUS); | |
3599 | data &= PHY_STAT_MASK; | |
3600 | if (desired) { | |
3601 | if (data == desired) | |
3602 | break; | |
3603 | } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || | |
3604 | data == PHY_STAT_EXT_INIT) { | |
3605 | break; | |
3606 | } | |
3607 | ||
3608 | msleep(20); | |
d64c7a08 YSY |
3609 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3610 | break; | |
c564b871 | 3611 | } |
3612 | ||
3613 | return data; | |
3614 | } | |
3615 | ||
65b82d69 | 3616 | static void r8153b_ups_en(struct r8152 *tp, bool enable) |
3617 | { | |
3618 | u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
3619 | ||
3620 | if (enable) { | |
0e5b36bc HW |
3621 | r8153b_ups_flags(tp); |
3622 | ||
65b82d69 | 3623 | ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; |
3624 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3625 | ||
195aae32 HW |
3626 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); |
3627 | ocp_data |= UPS_FORCE_PWR_DOWN; | |
3628 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
3629 | } else { | |
3630 | ocp_data &= ~(UPS_EN | USP_PREWAKE); | |
3631 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3632 | ||
3633 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); | |
3634 | ocp_data &= ~UPS_FORCE_PWR_DOWN; | |
3635 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
3636 | ||
3637 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { | |
3638 | int i; | |
3639 | ||
3640 | for (i = 0; i < 500; i++) { | |
3641 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
3642 | AUTOLOAD_DONE) | |
3643 | break; | |
3644 | msleep(20); | |
3645 | } | |
3646 | ||
3647 | tp->rtl_ops.hw_phy_cfg(tp); | |
3648 | ||
3649 | rtl8152_set_speed(tp, tp->autoneg, tp->speed, | |
3650 | tp->duplex, tp->advertising); | |
3651 | } | |
3652 | } | |
3653 | } | |
3654 | ||
3655 | static void r8153c_ups_en(struct r8152 *tp, bool enable) | |
3656 | { | |
3657 | u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
3658 | ||
3659 | if (enable) { | |
3660 | r8153b_ups_flags(tp); | |
3661 | ||
3662 | ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; | |
3663 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3664 | ||
3665 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); | |
3666 | ocp_data |= UPS_FORCE_PWR_DOWN; | |
3667 | ocp_data &= ~BIT(7); | |
3668 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
65b82d69 | 3669 | } else { |
65b82d69 | 3670 | ocp_data &= ~(UPS_EN | USP_PREWAKE); |
3671 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3672 | ||
195aae32 HW |
3673 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); |
3674 | ocp_data &= ~UPS_FORCE_PWR_DOWN; | |
3675 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
65b82d69 | 3676 | |
80fd850b HW |
3677 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { |
3678 | int i; | |
65b82d69 | 3679 | |
80fd850b HW |
3680 | for (i = 0; i < 500; i++) { |
3681 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
3682 | AUTOLOAD_DONE) | |
3683 | break; | |
3684 | msleep(20); | |
3685 | } | |
65b82d69 | 3686 | |
80fd850b | 3687 | tp->rtl_ops.hw_phy_cfg(tp); |
65b82d69 | 3688 | |
80fd850b HW |
3689 | rtl8152_set_speed(tp, tp->autoneg, tp->speed, |
3690 | tp->duplex, tp->advertising); | |
65b82d69 | 3691 | } |
195aae32 HW |
3692 | |
3693 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
3694 | ||
3695 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
3696 | ocp_data |= BIT(8); | |
3697 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
3698 | ||
3699 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
3700 | } | |
3701 | } | |
3702 | ||
3703 | static void r8156_ups_en(struct r8152 *tp, bool enable) | |
3704 | { | |
3705 | u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
3706 | ||
3707 | if (enable) { | |
3708 | r8156_ups_flags(tp); | |
3709 | ||
3710 | ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; | |
3711 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3712 | ||
3713 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); | |
3714 | ocp_data |= UPS_FORCE_PWR_DOWN; | |
3715 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
3716 | ||
3717 | switch (tp->version) { | |
3718 | case RTL_VER_13: | |
3719 | case RTL_VER_15: | |
3720 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL); | |
3721 | ocp_data &= ~OOBS_POLLING; | |
3722 | ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data); | |
3723 | break; | |
3724 | default: | |
3725 | break; | |
3726 | } | |
3727 | } else { | |
3728 | ocp_data &= ~(UPS_EN | USP_PREWAKE); | |
3729 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3730 | ||
3731 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); | |
3732 | ocp_data &= ~UPS_FORCE_PWR_DOWN; | |
3733 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
3734 | ||
3735 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { | |
3736 | tp->rtl_ops.hw_phy_cfg(tp); | |
3737 | ||
3738 | rtl8152_set_speed(tp, tp->autoneg, tp->speed, | |
3739 | tp->duplex, tp->advertising); | |
3740 | } | |
65b82d69 | 3741 | } |
3742 | } | |
3743 | ||
b214396f | 3744 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
3745 | { | |
3746 | u32 ocp_data; | |
3747 | ||
3748 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
3749 | if (enable) | |
3750 | ocp_data |= PWR_EN | PHASE2_EN; | |
3751 | else | |
3752 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
3753 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3754 | ||
3755 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
3756 | ocp_data &= ~PCUT_STATUS; | |
3757 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
3758 | } | |
3759 | ||
65b82d69 | 3760 | static void r8153b_power_cut_en(struct r8152 *tp, bool enable) |
3761 | { | |
3762 | u32 ocp_data; | |
3763 | ||
3764 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
3765 | if (enable) | |
3766 | ocp_data |= PWR_EN | PHASE2_EN; | |
3767 | else | |
3768 | ocp_data &= ~PWR_EN; | |
3769 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3770 | ||
3771 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
3772 | ocp_data &= ~PCUT_STATUS; | |
3773 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
3774 | } | |
3775 | ||
13e04fbf | 3776 | static void r8153_queue_wake(struct r8152 *tp, bool enable) |
65b82d69 | 3777 | { |
3778 | u32 ocp_data; | |
3779 | ||
13e04fbf | 3780 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG); |
65b82d69 | 3781 | if (enable) |
13e04fbf | 3782 | ocp_data |= UPCOMING_RUNTIME_D3; |
65b82d69 | 3783 | else |
13e04fbf HW |
3784 | ocp_data &= ~UPCOMING_RUNTIME_D3; |
3785 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data); | |
3786 | ||
3787 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG); | |
3788 | ocp_data &= ~LINK_CHG_EVENT; | |
3789 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data); | |
65b82d69 | 3790 | |
13e04fbf HW |
3791 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); |
3792 | ocp_data &= ~LINK_CHANGE_FLAG; | |
3793 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); | |
65b82d69 | 3794 | } |
3795 | ||
7daed8dc | 3796 | static bool rtl_can_wakeup(struct r8152 *tp) |
3797 | { | |
3798 | struct usb_device *udev = tp->udev; | |
3799 | ||
3800 | return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); | |
3801 | } | |
3802 | ||
9a4be1bd | 3803 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
3804 | { | |
3805 | if (enable) { | |
3806 | u32 ocp_data; | |
3807 | ||
3808 | __rtl_set_wol(tp, WAKE_ANY); | |
3809 | ||
3810 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
3811 | ||
3812 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
3813 | ocp_data |= LINK_OFF_WAKE_EN; | |
3814 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
3815 | ||
3816 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
3817 | } else { | |
f95ae8a0 | 3818 | u32 ocp_data; |
3819 | ||
9a4be1bd | 3820 | __rtl_set_wol(tp, tp->saved_wolopts); |
f95ae8a0 | 3821 | |
3822 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
3823 | ||
3824 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
3825 | ocp_data &= ~LINK_OFF_WAKE_EN; | |
3826 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
3827 | ||
3828 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2609af19 | 3829 | } |
3830 | } | |
f95ae8a0 | 3831 | |
2609af19 | 3832 | static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) |
3833 | { | |
2609af19 | 3834 | if (enable) { |
3835 | r8153_u1u2en(tp, false); | |
3836 | r8153_u2p3en(tp, false); | |
02552754 | 3837 | rtl_runtime_suspend_enable(tp, true); |
2609af19 | 3838 | } else { |
02552754 | 3839 | rtl_runtime_suspend_enable(tp, false); |
3cb3234e | 3840 | |
3841 | switch (tp->version) { | |
3842 | case RTL_VER_03: | |
3843 | case RTL_VER_04: | |
3844 | break; | |
3845 | case RTL_VER_05: | |
3846 | case RTL_VER_06: | |
3847 | default: | |
3848 | r8153_u2p3en(tp, true); | |
3849 | break; | |
3850 | } | |
3851 | ||
b214396f | 3852 | r8153_u1u2en(tp, true); |
9a4be1bd | 3853 | } |
3854 | } | |
3855 | ||
65b82d69 | 3856 | static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) |
3857 | { | |
3858 | if (enable) { | |
13e04fbf | 3859 | r8153_queue_wake(tp, true); |
65b82d69 | 3860 | r8153b_u1u2en(tp, false); |
3861 | r8153_u2p3en(tp, false); | |
3862 | rtl_runtime_suspend_enable(tp, true); | |
3863 | r8153b_ups_en(tp, true); | |
3864 | } else { | |
3865 | r8153b_ups_en(tp, false); | |
13e04fbf | 3866 | r8153_queue_wake(tp, false); |
65b82d69 | 3867 | rtl_runtime_suspend_enable(tp, false); |
7a0ae61a | 3868 | if (tp->udev->speed >= USB_SPEED_SUPER) |
a0246daf | 3869 | r8153b_u1u2en(tp, true); |
65b82d69 | 3870 | } |
3871 | } | |
3872 | ||
195aae32 | 3873 | static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable) |
4349968a | 3874 | { |
195aae32 HW |
3875 | if (enable) { |
3876 | r8153_queue_wake(tp, true); | |
3877 | r8153b_u1u2en(tp, false); | |
3878 | r8153_u2p3en(tp, false); | |
3879 | rtl_runtime_suspend_enable(tp, true); | |
3880 | r8153c_ups_en(tp, true); | |
3881 | } else { | |
3882 | r8153c_ups_en(tp, false); | |
3883 | r8153_queue_wake(tp, false); | |
3884 | rtl_runtime_suspend_enable(tp, false); | |
3885 | r8153b_u1u2en(tp, true); | |
3886 | } | |
3887 | } | |
4349968a | 3888 | |
195aae32 HW |
3889 | static void rtl8156_runtime_enable(struct r8152 *tp, bool enable) |
3890 | { | |
3891 | if (enable) { | |
3892 | r8153_queue_wake(tp, true); | |
3893 | r8153b_u1u2en(tp, false); | |
3894 | r8153_u2p3en(tp, false); | |
3895 | rtl_runtime_suspend_enable(tp, true); | |
3896 | } else { | |
3897 | r8153_queue_wake(tp, false); | |
3898 | rtl_runtime_suspend_enable(tp, false); | |
3899 | r8153_u2p3en(tp, true); | |
3900 | if (tp->udev->speed >= USB_SPEED_SUPER) | |
3901 | r8153b_u1u2en(tp, true); | |
3902 | } | |
3903 | } | |
3904 | ||
3905 | static void r8153_teredo_off(struct r8152 *tp) | |
3906 | { | |
3907 | u32 ocp_data; | |
3908 | ||
3909 | switch (tp->version) { | |
3910 | case RTL_VER_01: | |
3911 | case RTL_VER_02: | |
3912 | case RTL_VER_03: | |
3913 | case RTL_VER_04: | |
3914 | case RTL_VER_05: | |
3915 | case RTL_VER_06: | |
3916 | case RTL_VER_07: | |
3917 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
3918 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | | |
3919 | OOB_TEREDO_EN); | |
3920 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
3921 | break; | |
65b82d69 | 3922 | |
3923 | case RTL_VER_08: | |
3924 | case RTL_VER_09: | |
195aae32 HW |
3925 | case RTL_TEST_01: |
3926 | case RTL_VER_10: | |
3927 | case RTL_VER_11: | |
3928 | case RTL_VER_12: | |
3929 | case RTL_VER_13: | |
3930 | case RTL_VER_14: | |
3931 | case RTL_VER_15: | |
3932 | default: | |
65b82d69 | 3933 | /* The bit 0 ~ 7 are relative with teredo settings. They are |
3934 | * W1C (write 1 to clear), so set all 1 to disable it. | |
3935 | */ | |
3936 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); | |
3937 | break; | |
65b82d69 | 3938 | } |
4349968a | 3939 | |
3940 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
3941 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
3942 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
3943 | } | |
3944 | ||
93fe9b18 | 3945 | static void rtl_reset_bmu(struct r8152 *tp) |
3946 | { | |
3947 | u32 ocp_data; | |
3948 | ||
3949 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); | |
3950 | ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); | |
3951 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
3952 | ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; | |
3953 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
3954 | } | |
3955 | ||
9370f2d0 HW |
3956 | /* Clear the bp to stop the firmware before loading a new one */ |
3957 | static void rtl_clear_bp(struct r8152 *tp, u16 type) | |
3958 | { | |
3959 | switch (tp->version) { | |
3960 | case RTL_VER_01: | |
3961 | case RTL_VER_02: | |
3962 | case RTL_VER_07: | |
3963 | break; | |
3964 | case RTL_VER_03: | |
3965 | case RTL_VER_04: | |
3966 | case RTL_VER_05: | |
3967 | case RTL_VER_06: | |
3968 | ocp_write_byte(tp, type, PLA_BP_EN, 0); | |
3969 | break; | |
6633fb83 HW |
3970 | case RTL_VER_14: |
3971 | ocp_write_word(tp, type, USB_BP2_EN, 0); | |
3972 | ||
3973 | ocp_write_word(tp, type, USB_BP_8, 0); | |
3974 | ocp_write_word(tp, type, USB_BP_9, 0); | |
3975 | ocp_write_word(tp, type, USB_BP_10, 0); | |
3976 | ocp_write_word(tp, type, USB_BP_11, 0); | |
3977 | ocp_write_word(tp, type, USB_BP_12, 0); | |
3978 | ocp_write_word(tp, type, USB_BP_13, 0); | |
3979 | ocp_write_word(tp, type, USB_BP_14, 0); | |
3980 | ocp_write_word(tp, type, USB_BP_15, 0); | |
3981 | break; | |
9370f2d0 HW |
3982 | case RTL_VER_08: |
3983 | case RTL_VER_09: | |
195aae32 HW |
3984 | case RTL_VER_10: |
3985 | case RTL_VER_11: | |
3986 | case RTL_VER_12: | |
3987 | case RTL_VER_13: | |
195aae32 | 3988 | case RTL_VER_15: |
9370f2d0 HW |
3989 | default: |
3990 | if (type == MCU_TYPE_USB) { | |
a876a33d | 3991 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0); |
9370f2d0 HW |
3992 | |
3993 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0); | |
3994 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0); | |
3995 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0); | |
3996 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0); | |
3997 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0); | |
3998 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0); | |
3999 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0); | |
4000 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0); | |
4001 | } else { | |
4002 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); | |
4003 | } | |
4004 | break; | |
4005 | } | |
4006 | ||
4007 | ocp_write_word(tp, type, PLA_BP_0, 0); | |
4008 | ocp_write_word(tp, type, PLA_BP_1, 0); | |
4009 | ocp_write_word(tp, type, PLA_BP_2, 0); | |
4010 | ocp_write_word(tp, type, PLA_BP_3, 0); | |
4011 | ocp_write_word(tp, type, PLA_BP_4, 0); | |
4012 | ocp_write_word(tp, type, PLA_BP_5, 0); | |
4013 | ocp_write_word(tp, type, PLA_BP_6, 0); | |
4014 | ocp_write_word(tp, type, PLA_BP_7, 0); | |
4015 | ||
4016 | /* wait 3 ms to make sure the firmware is stopped */ | |
4017 | usleep_range(3000, 6000); | |
4018 | ocp_write_word(tp, type, PLA_BP_BA, 0); | |
4019 | } | |
4020 | ||
b24edca3 HW |
4021 | static inline void rtl_reset_ocp_base(struct r8152 *tp) |
4022 | { | |
4023 | tp->ocp_base = -1; | |
4024 | } | |
4025 | ||
a08c0d30 | 4026 | static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait) |
470e3919 | 4027 | { |
a08c0d30 | 4028 | u16 data, check; |
470e3919 HW |
4029 | int i; |
4030 | ||
4031 | data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); | |
a08c0d30 | 4032 | if (request) { |
470e3919 | 4033 | data |= PATCH_REQUEST; |
a08c0d30 HW |
4034 | check = 0; |
4035 | } else { | |
470e3919 | 4036 | data &= ~PATCH_REQUEST; |
a08c0d30 HW |
4037 | check = PATCH_READY; |
4038 | } | |
470e3919 HW |
4039 | ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); |
4040 | ||
a08c0d30 HW |
4041 | for (i = 0; wait && i < 5000; i++) { |
4042 | u32 ocp_data; | |
4043 | ||
470e3919 | 4044 | usleep_range(1000, 2000); |
a08c0d30 HW |
4045 | ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT); |
4046 | if ((ocp_data & PATCH_READY) ^ check) | |
470e3919 HW |
4047 | break; |
4048 | } | |
4049 | ||
a08c0d30 HW |
4050 | if (request && wait && |
4051 | !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { | |
4052 | dev_err(&tp->intf->dev, "PHY patch request fail\n"); | |
4053 | rtl_phy_patch_request(tp, false, false); | |
470e3919 HW |
4054 | return -ETIME; |
4055 | } else { | |
4056 | return 0; | |
4057 | } | |
4058 | } | |
4059 | ||
a08c0d30 | 4060 | static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key) |
af14288f | 4061 | { |
a08c0d30 HW |
4062 | if (patch_key && key_addr) { |
4063 | sram_write(tp, key_addr, patch_key); | |
4064 | sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK); | |
4065 | } else if (key_addr) { | |
4066 | u16 data; | |
af14288f | 4067 | |
a08c0d30 | 4068 | sram_write(tp, 0x0000, 0x0000); |
af14288f | 4069 | |
a08c0d30 HW |
4070 | data = ocp_reg_read(tp, OCP_PHY_LOCK); |
4071 | data &= ~PATCH_LOCK; | |
4072 | ocp_reg_write(tp, OCP_PHY_LOCK, data); | |
4073 | ||
4074 | sram_write(tp, key_addr, 0x0000); | |
4075 | } else { | |
4076 | WARN_ON_ONCE(1); | |
4077 | } | |
af14288f HW |
4078 | } |
4079 | ||
a08c0d30 HW |
4080 | static int |
4081 | rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait) | |
af14288f | 4082 | { |
a08c0d30 HW |
4083 | if (rtl_phy_patch_request(tp, true, wait)) |
4084 | return -ETIME; | |
af14288f | 4085 | |
a08c0d30 | 4086 | rtl_patch_key_set(tp, key_addr, patch_key); |
af14288f | 4087 | |
a08c0d30 HW |
4088 | return 0; |
4089 | } | |
af14288f | 4090 | |
a08c0d30 HW |
4091 | static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait) |
4092 | { | |
4093 | rtl_patch_key_set(tp, key_addr, 0); | |
af14288f | 4094 | |
a08c0d30 | 4095 | rtl_phy_patch_request(tp, false, wait); |
af14288f | 4096 | |
af14288f HW |
4097 | return 0; |
4098 | } | |
4099 | ||
4a51b0e8 HW |
4100 | static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy) |
4101 | { | |
4102 | u16 fw_offset; | |
4103 | u32 length; | |
4104 | bool rc = false; | |
4105 | ||
4106 | switch (tp->version) { | |
4107 | case RTL_VER_01: | |
4108 | case RTL_VER_02: | |
4109 | case RTL_VER_03: | |
4110 | case RTL_VER_04: | |
4111 | case RTL_VER_05: | |
4112 | case RTL_VER_06: | |
4113 | case RTL_VER_07: | |
4114 | case RTL_VER_08: | |
4115 | case RTL_VER_09: | |
4116 | case RTL_VER_10: | |
4117 | case RTL_VER_11: | |
4118 | case RTL_VER_12: | |
4119 | case RTL_VER_14: | |
4120 | goto out; | |
4121 | case RTL_VER_13: | |
4122 | case RTL_VER_15: | |
4123 | default: | |
4124 | break; | |
4125 | } | |
4126 | ||
4127 | fw_offset = __le16_to_cpu(phy->fw_offset); | |
4128 | length = __le32_to_cpu(phy->blk_hdr.length); | |
4129 | if (fw_offset < sizeof(*phy) || length <= fw_offset) { | |
4130 | dev_err(&tp->intf->dev, "invalid fw_offset\n"); | |
4131 | goto out; | |
4132 | } | |
4133 | ||
4134 | length -= fw_offset; | |
4135 | if (length & 3) { | |
4136 | dev_err(&tp->intf->dev, "invalid block length\n"); | |
4137 | goto out; | |
4138 | } | |
4139 | ||
4140 | if (__le16_to_cpu(phy->fw_reg) != 0x9A00) { | |
4141 | dev_err(&tp->intf->dev, "invalid register to load firmware\n"); | |
4142 | goto out; | |
4143 | } | |
4144 | ||
4145 | rc = true; | |
4146 | out: | |
4147 | return rc; | |
4148 | } | |
4149 | ||
4150 | static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver) | |
4151 | { | |
4152 | bool rc = false; | |
4153 | ||
4154 | switch (tp->version) { | |
4155 | case RTL_VER_10: | |
4156 | case RTL_VER_11: | |
4157 | case RTL_VER_12: | |
4158 | case RTL_VER_13: | |
4159 | case RTL_VER_15: | |
4160 | break; | |
4161 | default: | |
4162 | goto out; | |
4163 | } | |
4164 | ||
4165 | if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) { | |
4166 | dev_err(&tp->intf->dev, "invalid block length\n"); | |
4167 | goto out; | |
4168 | } | |
4169 | ||
4170 | if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) { | |
4171 | dev_err(&tp->intf->dev, "invalid phy ver addr\n"); | |
4172 | goto out; | |
4173 | } | |
4174 | ||
4175 | rc = true; | |
4176 | out: | |
4177 | return rc; | |
4178 | } | |
4179 | ||
4180 | static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix) | |
4181 | { | |
4182 | bool rc = false; | |
4183 | ||
4184 | switch (tp->version) { | |
4185 | case RTL_VER_10: | |
4186 | case RTL_VER_11: | |
4187 | case RTL_VER_12: | |
4188 | case RTL_VER_13: | |
4189 | case RTL_VER_15: | |
4190 | break; | |
4191 | default: | |
4192 | goto out; | |
4193 | } | |
4194 | ||
4195 | if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) { | |
4196 | dev_err(&tp->intf->dev, "invalid block length\n"); | |
4197 | goto out; | |
4198 | } | |
4199 | ||
4200 | if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD || | |
4201 | __le16_to_cpu(fix->setting.data) != BIT(7)) { | |
4202 | dev_err(&tp->intf->dev, "invalid phy fixup\n"); | |
4203 | goto out; | |
4204 | } | |
4205 | ||
4206 | rc = true; | |
4207 | out: | |
4208 | return rc; | |
4209 | } | |
4210 | ||
4211 | static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy) | |
4212 | { | |
4213 | u16 fw_offset; | |
4214 | u32 length; | |
4215 | bool rc = false; | |
4216 | ||
4217 | switch (tp->version) { | |
4218 | case RTL_VER_10: | |
4219 | case RTL_VER_11: | |
4220 | case RTL_VER_12: | |
4221 | case RTL_VER_13: | |
4222 | case RTL_VER_15: | |
4223 | break; | |
4224 | default: | |
4225 | goto out; | |
4226 | } | |
4227 | ||
4228 | fw_offset = __le16_to_cpu(phy->fw_offset); | |
4229 | length = __le32_to_cpu(phy->blk_hdr.length); | |
4230 | if (fw_offset < sizeof(*phy) || length <= fw_offset) { | |
4231 | dev_err(&tp->intf->dev, "invalid fw_offset\n"); | |
4232 | goto out; | |
4233 | } | |
4234 | ||
4235 | length -= fw_offset; | |
4236 | if (length & 1) { | |
4237 | dev_err(&tp->intf->dev, "invalid block length\n"); | |
4238 | goto out; | |
4239 | } | |
4240 | ||
4241 | if (phy->pre_num > 2) { | |
4242 | dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num); | |
4243 | goto out; | |
4244 | } | |
4245 | ||
4246 | if (phy->bp_num > 8) { | |
4247 | dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num); | |
4248 | goto out; | |
4249 | } | |
4250 | ||
4251 | rc = true; | |
4252 | out: | |
4253 | return rc; | |
4254 | } | |
4255 | ||
af14288f HW |
4256 | static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy) |
4257 | { | |
4258 | u32 length; | |
4259 | u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start; | |
4260 | bool rc = false; | |
4261 | ||
4262 | switch (tp->version) { | |
4263 | case RTL_VER_04: | |
4264 | case RTL_VER_05: | |
4265 | case RTL_VER_06: | |
4266 | fw_reg = 0xa014; | |
4267 | ba_reg = 0xa012; | |
4268 | patch_en_addr = 0xa01a; | |
4269 | mode_reg = 0xb820; | |
4270 | bp_start = 0xa000; | |
4271 | break; | |
4272 | default: | |
4273 | goto out; | |
4274 | } | |
4275 | ||
4276 | fw_offset = __le16_to_cpu(phy->fw_offset); | |
4277 | if (fw_offset < sizeof(*phy)) { | |
4278 | dev_err(&tp->intf->dev, "fw_offset too small\n"); | |
4279 | goto out; | |
4280 | } | |
4281 | ||
4282 | length = __le32_to_cpu(phy->blk_hdr.length); | |
4283 | if (length < fw_offset) { | |
4284 | dev_err(&tp->intf->dev, "invalid fw_offset\n"); | |
4285 | goto out; | |
4286 | } | |
4287 | ||
4288 | length -= __le16_to_cpu(phy->fw_offset); | |
4289 | if (!length || (length & 1)) { | |
4290 | dev_err(&tp->intf->dev, "invalid block length\n"); | |
4291 | goto out; | |
4292 | } | |
4293 | ||
4294 | if (__le16_to_cpu(phy->fw_reg) != fw_reg) { | |
4295 | dev_err(&tp->intf->dev, "invalid register to load firmware\n"); | |
4296 | goto out; | |
4297 | } | |
4298 | ||
4299 | if (__le16_to_cpu(phy->ba_reg) != ba_reg) { | |
4300 | dev_err(&tp->intf->dev, "invalid base address register\n"); | |
4301 | goto out; | |
4302 | } | |
4303 | ||
4304 | if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) { | |
4305 | dev_err(&tp->intf->dev, | |
4306 | "invalid patch mode enabled register\n"); | |
4307 | goto out; | |
4308 | } | |
4309 | ||
4310 | if (__le16_to_cpu(phy->mode_reg) != mode_reg) { | |
4311 | dev_err(&tp->intf->dev, | |
4312 | "invalid register to switch the mode\n"); | |
4313 | goto out; | |
4314 | } | |
4315 | ||
4316 | if (__le16_to_cpu(phy->bp_start) != bp_start) { | |
4317 | dev_err(&tp->intf->dev, | |
4318 | "invalid start register of break point\n"); | |
4319 | goto out; | |
4320 | } | |
4321 | ||
4322 | if (__le16_to_cpu(phy->bp_num) > 4) { | |
4323 | dev_err(&tp->intf->dev, "invalid break point number\n"); | |
4324 | goto out; | |
4325 | } | |
4326 | ||
4327 | rc = true; | |
4328 | out: | |
4329 | return rc; | |
4330 | } | |
4331 | ||
a66edaaf | 4332 | static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac) |
9370f2d0 | 4333 | { |
5a16a3d9 | 4334 | u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset; |
9370f2d0 HW |
4335 | bool rc = false; |
4336 | u32 length, type; | |
4337 | int i, max_bp; | |
4338 | ||
a66edaaf | 4339 | type = __le32_to_cpu(mac->blk_hdr.type); |
9370f2d0 HW |
4340 | if (type == RTL_FW_PLA) { |
4341 | switch (tp->version) { | |
4342 | case RTL_VER_01: | |
4343 | case RTL_VER_02: | |
4344 | case RTL_VER_07: | |
4345 | fw_reg = 0xf800; | |
4346 | bp_ba_addr = PLA_BP_BA; | |
4347 | bp_en_addr = 0; | |
4348 | bp_start = PLA_BP_0; | |
4349 | max_bp = 8; | |
4350 | break; | |
4351 | case RTL_VER_03: | |
4352 | case RTL_VER_04: | |
4353 | case RTL_VER_05: | |
4354 | case RTL_VER_06: | |
4355 | case RTL_VER_08: | |
4356 | case RTL_VER_09: | |
195aae32 HW |
4357 | case RTL_VER_11: |
4358 | case RTL_VER_12: | |
4359 | case RTL_VER_13: | |
195aae32 | 4360 | case RTL_VER_15: |
9370f2d0 HW |
4361 | fw_reg = 0xf800; |
4362 | bp_ba_addr = PLA_BP_BA; | |
4363 | bp_en_addr = PLA_BP_EN; | |
4364 | bp_start = PLA_BP_0; | |
4365 | max_bp = 8; | |
4366 | break; | |
6633fb83 HW |
4367 | case RTL_VER_14: |
4368 | fw_reg = 0xf800; | |
4369 | bp_ba_addr = PLA_BP_BA; | |
4370 | bp_en_addr = USB_BP2_EN; | |
4371 | bp_start = PLA_BP_0; | |
4372 | max_bp = 16; | |
4373 | break; | |
9370f2d0 HW |
4374 | default: |
4375 | goto out; | |
4376 | } | |
4377 | } else if (type == RTL_FW_USB) { | |
4378 | switch (tp->version) { | |
4379 | case RTL_VER_03: | |
4380 | case RTL_VER_04: | |
4381 | case RTL_VER_05: | |
4382 | case RTL_VER_06: | |
4383 | fw_reg = 0xf800; | |
4384 | bp_ba_addr = USB_BP_BA; | |
4385 | bp_en_addr = USB_BP_EN; | |
4386 | bp_start = USB_BP_0; | |
4387 | max_bp = 8; | |
4388 | break; | |
4389 | case RTL_VER_08: | |
4390 | case RTL_VER_09: | |
195aae32 HW |
4391 | case RTL_VER_11: |
4392 | case RTL_VER_12: | |
4393 | case RTL_VER_13: | |
4394 | case RTL_VER_14: | |
4395 | case RTL_VER_15: | |
9370f2d0 HW |
4396 | fw_reg = 0xe600; |
4397 | bp_ba_addr = USB_BP_BA; | |
4398 | bp_en_addr = USB_BP2_EN; | |
4399 | bp_start = USB_BP_0; | |
4400 | max_bp = 16; | |
4401 | break; | |
4402 | case RTL_VER_01: | |
4403 | case RTL_VER_02: | |
4404 | case RTL_VER_07: | |
4405 | default: | |
4406 | goto out; | |
4407 | } | |
4408 | } else { | |
4409 | goto out; | |
4410 | } | |
4411 | ||
5a16a3d9 HW |
4412 | fw_offset = __le16_to_cpu(mac->fw_offset); |
4413 | if (fw_offset < sizeof(*mac)) { | |
4414 | dev_err(&tp->intf->dev, "fw_offset too small\n"); | |
4415 | goto out; | |
4416 | } | |
4417 | ||
a66edaaf | 4418 | length = __le32_to_cpu(mac->blk_hdr.length); |
5a16a3d9 | 4419 | if (length < fw_offset) { |
9370f2d0 HW |
4420 | dev_err(&tp->intf->dev, "invalid fw_offset\n"); |
4421 | goto out; | |
4422 | } | |
4423 | ||
5a16a3d9 | 4424 | length -= fw_offset; |
9370f2d0 HW |
4425 | if (length < 4 || (length & 3)) { |
4426 | dev_err(&tp->intf->dev, "invalid block length\n"); | |
4427 | goto out; | |
4428 | } | |
4429 | ||
a66edaaf | 4430 | if (__le16_to_cpu(mac->fw_reg) != fw_reg) { |
9370f2d0 HW |
4431 | dev_err(&tp->intf->dev, "invalid register to load firmware\n"); |
4432 | goto out; | |
4433 | } | |
4434 | ||
a66edaaf | 4435 | if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) { |
9370f2d0 HW |
4436 | dev_err(&tp->intf->dev, "invalid base address register\n"); |
4437 | goto out; | |
4438 | } | |
4439 | ||
a66edaaf | 4440 | if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) { |
9370f2d0 HW |
4441 | dev_err(&tp->intf->dev, "invalid enabled mask register\n"); |
4442 | goto out; | |
4443 | } | |
4444 | ||
a66edaaf | 4445 | if (__le16_to_cpu(mac->bp_start) != bp_start) { |
9370f2d0 HW |
4446 | dev_err(&tp->intf->dev, |
4447 | "invalid start register of break point\n"); | |
4448 | goto out; | |
4449 | } | |
4450 | ||
a66edaaf | 4451 | if (__le16_to_cpu(mac->bp_num) > max_bp) { |
9370f2d0 HW |
4452 | dev_err(&tp->intf->dev, "invalid break point number\n"); |
4453 | goto out; | |
4454 | } | |
4455 | ||
a66edaaf HW |
4456 | for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) { |
4457 | if (mac->bp[i]) { | |
9370f2d0 HW |
4458 | dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i); |
4459 | goto out; | |
4460 | } | |
4461 | } | |
4462 | ||
4463 | rc = true; | |
4464 | out: | |
4465 | return rc; | |
4466 | } | |
4467 | ||
4468 | /* Verify the checksum for the firmware file. It is calculated from the version | |
4469 | * field to the end of the file. Compare the result with the checksum field to | |
4470 | * make sure the file is correct. | |
4471 | */ | |
4472 | static long rtl8152_fw_verify_checksum(struct r8152 *tp, | |
4473 | struct fw_header *fw_hdr, size_t size) | |
4474 | { | |
4475 | unsigned char checksum[sizeof(fw_hdr->checksum)]; | |
4476 | struct crypto_shash *alg; | |
4477 | struct shash_desc *sdesc; | |
4478 | size_t len; | |
4479 | long rc; | |
4480 | ||
4481 | alg = crypto_alloc_shash("sha256", 0, 0); | |
4482 | if (IS_ERR(alg)) { | |
4483 | rc = PTR_ERR(alg); | |
4484 | goto out; | |
4485 | } | |
4486 | ||
4487 | if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) { | |
4488 | rc = -EFAULT; | |
4489 | dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n", | |
4490 | crypto_shash_digestsize(alg)); | |
4491 | goto free_shash; | |
4492 | } | |
4493 | ||
4494 | len = sizeof(*sdesc) + crypto_shash_descsize(alg); | |
4495 | sdesc = kmalloc(len, GFP_KERNEL); | |
4496 | if (!sdesc) { | |
4497 | rc = -ENOMEM; | |
4498 | goto free_shash; | |
4499 | } | |
4500 | sdesc->tfm = alg; | |
4501 | ||
4502 | len = size - sizeof(fw_hdr->checksum); | |
4503 | rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum); | |
4504 | kfree(sdesc); | |
4505 | if (rc) | |
4506 | goto free_shash; | |
4507 | ||
4508 | if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) { | |
4509 | dev_err(&tp->intf->dev, "checksum fail\n"); | |
4510 | rc = -EFAULT; | |
4511 | } | |
4512 | ||
4513 | free_shash: | |
4514 | crypto_free_shash(alg); | |
4515 | out: | |
4516 | return rc; | |
4517 | } | |
4518 | ||
4519 | static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw) | |
4520 | { | |
4521 | const struct firmware *fw = rtl_fw->fw; | |
4522 | struct fw_header *fw_hdr = (struct fw_header *)fw->data; | |
a8a7be17 | 4523 | unsigned long fw_flags = 0; |
9370f2d0 HW |
4524 | long ret = -EFAULT; |
4525 | int i; | |
4526 | ||
4527 | if (fw->size < sizeof(*fw_hdr)) { | |
4528 | dev_err(&tp->intf->dev, "file too small\n"); | |
4529 | goto fail; | |
4530 | } | |
4531 | ||
4532 | ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size); | |
4533 | if (ret) | |
4534 | goto fail; | |
4535 | ||
4536 | ret = -EFAULT; | |
4537 | ||
4538 | for (i = sizeof(*fw_hdr); i < fw->size;) { | |
4539 | struct fw_block *block = (struct fw_block *)&fw->data[i]; | |
4540 | u32 type; | |
4541 | ||
4542 | if ((i + sizeof(*block)) > fw->size) | |
4543 | goto fail; | |
4544 | ||
4545 | type = __le32_to_cpu(block->type); | |
4546 | switch (type) { | |
4547 | case RTL_FW_END: | |
4548 | if (__le32_to_cpu(block->length) != sizeof(*block)) | |
4549 | goto fail; | |
af14288f | 4550 | goto fw_end; |
9370f2d0 | 4551 | case RTL_FW_PLA: |
a8a7be17 | 4552 | if (test_bit(FW_FLAGS_PLA, &fw_flags)) { |
9370f2d0 HW |
4553 | dev_err(&tp->intf->dev, |
4554 | "multiple PLA firmware encountered"); | |
4555 | goto fail; | |
4556 | } | |
4557 | ||
a8a7be17 | 4558 | if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) { |
9370f2d0 | 4559 | dev_err(&tp->intf->dev, |
a66edaaf | 4560 | "check PLA firmware failed\n"); |
9370f2d0 HW |
4561 | goto fail; |
4562 | } | |
a8a7be17 | 4563 | __set_bit(FW_FLAGS_PLA, &fw_flags); |
9370f2d0 HW |
4564 | break; |
4565 | case RTL_FW_USB: | |
a8a7be17 | 4566 | if (test_bit(FW_FLAGS_USB, &fw_flags)) { |
9370f2d0 HW |
4567 | dev_err(&tp->intf->dev, |
4568 | "multiple USB firmware encountered"); | |
4569 | goto fail; | |
4570 | } | |
4571 | ||
a8a7be17 | 4572 | if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) { |
9370f2d0 | 4573 | dev_err(&tp->intf->dev, |
a66edaaf | 4574 | "check USB firmware failed\n"); |
9370f2d0 HW |
4575 | goto fail; |
4576 | } | |
a8a7be17 | 4577 | __set_bit(FW_FLAGS_USB, &fw_flags); |
af14288f HW |
4578 | break; |
4579 | case RTL_FW_PHY_START: | |
a8a7be17 HW |
4580 | if (test_bit(FW_FLAGS_START, &fw_flags) || |
4581 | test_bit(FW_FLAGS_NC, &fw_flags) || | |
4a51b0e8 HW |
4582 | test_bit(FW_FLAGS_NC1, &fw_flags) || |
4583 | test_bit(FW_FLAGS_NC2, &fw_flags) || | |
4584 | test_bit(FW_FLAGS_UC2, &fw_flags) || | |
4585 | test_bit(FW_FLAGS_UC, &fw_flags) || | |
a8a7be17 | 4586 | test_bit(FW_FLAGS_STOP, &fw_flags)) { |
af14288f HW |
4587 | dev_err(&tp->intf->dev, |
4588 | "check PHY_START fail\n"); | |
4589 | goto fail; | |
4590 | } | |
4591 | ||
a8a7be17 | 4592 | if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) { |
af14288f HW |
4593 | dev_err(&tp->intf->dev, |
4594 | "Invalid length for PHY_START\n"); | |
4595 | goto fail; | |
4596 | } | |
a8a7be17 | 4597 | __set_bit(FW_FLAGS_START, &fw_flags); |
af14288f HW |
4598 | break; |
4599 | case RTL_FW_PHY_STOP: | |
a8a7be17 HW |
4600 | if (test_bit(FW_FLAGS_STOP, &fw_flags) || |
4601 | !test_bit(FW_FLAGS_START, &fw_flags)) { | |
af14288f HW |
4602 | dev_err(&tp->intf->dev, |
4603 | "Check PHY_STOP fail\n"); | |
4604 | goto fail; | |
4605 | } | |
4606 | ||
4607 | if (__le32_to_cpu(block->length) != sizeof(*block)) { | |
4608 | dev_err(&tp->intf->dev, | |
4609 | "Invalid length for PHY_STOP\n"); | |
4610 | goto fail; | |
4611 | } | |
a8a7be17 | 4612 | __set_bit(FW_FLAGS_STOP, &fw_flags); |
af14288f HW |
4613 | break; |
4614 | case RTL_FW_PHY_NC: | |
a8a7be17 HW |
4615 | if (!test_bit(FW_FLAGS_START, &fw_flags) || |
4616 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
af14288f HW |
4617 | dev_err(&tp->intf->dev, |
4618 | "check PHY_NC fail\n"); | |
4619 | goto fail; | |
4620 | } | |
4621 | ||
a8a7be17 | 4622 | if (test_bit(FW_FLAGS_NC, &fw_flags)) { |
af14288f HW |
4623 | dev_err(&tp->intf->dev, |
4624 | "multiple PHY NC encountered\n"); | |
4625 | goto fail; | |
4626 | } | |
4627 | ||
a8a7be17 | 4628 | if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) { |
af14288f HW |
4629 | dev_err(&tp->intf->dev, |
4630 | "check PHY NC firmware failed\n"); | |
4631 | goto fail; | |
4632 | } | |
a8a7be17 | 4633 | __set_bit(FW_FLAGS_NC, &fw_flags); |
4a51b0e8 HW |
4634 | break; |
4635 | case RTL_FW_PHY_UNION_NC: | |
4636 | if (!test_bit(FW_FLAGS_START, &fw_flags) || | |
4637 | test_bit(FW_FLAGS_NC1, &fw_flags) || | |
4638 | test_bit(FW_FLAGS_NC2, &fw_flags) || | |
4639 | test_bit(FW_FLAGS_UC2, &fw_flags) || | |
4640 | test_bit(FW_FLAGS_UC, &fw_flags) || | |
4641 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
4642 | dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n"); | |
4643 | goto fail; | |
4644 | } | |
4645 | ||
4646 | if (test_bit(FW_FLAGS_NC, &fw_flags)) { | |
4647 | dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n"); | |
4648 | goto fail; | |
4649 | } | |
4650 | ||
4651 | if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { | |
4652 | dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n"); | |
4653 | goto fail; | |
4654 | } | |
4655 | __set_bit(FW_FLAGS_NC, &fw_flags); | |
4656 | break; | |
4657 | case RTL_FW_PHY_UNION_NC1: | |
4658 | if (!test_bit(FW_FLAGS_START, &fw_flags) || | |
4659 | test_bit(FW_FLAGS_NC2, &fw_flags) || | |
4660 | test_bit(FW_FLAGS_UC2, &fw_flags) || | |
4661 | test_bit(FW_FLAGS_UC, &fw_flags) || | |
4662 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
4663 | dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n"); | |
4664 | goto fail; | |
4665 | } | |
4666 | ||
4667 | if (test_bit(FW_FLAGS_NC1, &fw_flags)) { | |
4668 | dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n"); | |
4669 | goto fail; | |
4670 | } | |
4671 | ||
4672 | if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { | |
4673 | dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n"); | |
4674 | goto fail; | |
4675 | } | |
4676 | __set_bit(FW_FLAGS_NC1, &fw_flags); | |
4677 | break; | |
4678 | case RTL_FW_PHY_UNION_NC2: | |
4679 | if (!test_bit(FW_FLAGS_START, &fw_flags) || | |
4680 | test_bit(FW_FLAGS_UC2, &fw_flags) || | |
4681 | test_bit(FW_FLAGS_UC, &fw_flags) || | |
4682 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
4683 | dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n"); | |
4684 | goto fail; | |
4685 | } | |
4686 | ||
4687 | if (test_bit(FW_FLAGS_NC2, &fw_flags)) { | |
4688 | dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n"); | |
4689 | goto fail; | |
4690 | } | |
4691 | ||
4692 | if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { | |
4693 | dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n"); | |
4694 | goto fail; | |
4695 | } | |
4696 | __set_bit(FW_FLAGS_NC2, &fw_flags); | |
4697 | break; | |
4698 | case RTL_FW_PHY_UNION_UC2: | |
4699 | if (!test_bit(FW_FLAGS_START, &fw_flags) || | |
4700 | test_bit(FW_FLAGS_UC, &fw_flags) || | |
4701 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
4702 | dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n"); | |
4703 | goto fail; | |
4704 | } | |
4705 | ||
4706 | if (test_bit(FW_FLAGS_UC2, &fw_flags)) { | |
4707 | dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n"); | |
4708 | goto fail; | |
4709 | } | |
4710 | ||
4711 | if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { | |
4712 | dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n"); | |
4713 | goto fail; | |
4714 | } | |
4715 | __set_bit(FW_FLAGS_UC2, &fw_flags); | |
4716 | break; | |
4717 | case RTL_FW_PHY_UNION_UC: | |
4718 | if (!test_bit(FW_FLAGS_START, &fw_flags) || | |
4719 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
4720 | dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n"); | |
4721 | goto fail; | |
4722 | } | |
4723 | ||
4724 | if (test_bit(FW_FLAGS_UC, &fw_flags)) { | |
4725 | dev_err(&tp->intf->dev, "multiple PHY UC encountered\n"); | |
4726 | goto fail; | |
4727 | } | |
4728 | ||
4729 | if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { | |
4730 | dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n"); | |
4731 | goto fail; | |
4732 | } | |
4733 | __set_bit(FW_FLAGS_UC, &fw_flags); | |
4734 | break; | |
4735 | case RTL_FW_PHY_UNION_MISC: | |
4736 | if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { | |
4737 | dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n"); | |
4738 | goto fail; | |
4739 | } | |
4740 | break; | |
4741 | case RTL_FW_PHY_FIXUP: | |
4742 | if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) { | |
4743 | dev_err(&tp->intf->dev, "check PHY fixup failed\n"); | |
4744 | goto fail; | |
4745 | } | |
4746 | break; | |
4747 | case RTL_FW_PHY_SPEED_UP: | |
4748 | if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) { | |
4749 | dev_err(&tp->intf->dev, "multiple PHY firmware encountered"); | |
4750 | goto fail; | |
4751 | } | |
af14288f | 4752 | |
4a51b0e8 HW |
4753 | if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) { |
4754 | dev_err(&tp->intf->dev, "check PHY speed up failed\n"); | |
4755 | goto fail; | |
4756 | } | |
4757 | __set_bit(FW_FLAGS_SPEED_UP, &fw_flags); | |
4758 | break; | |
4759 | case RTL_FW_PHY_VER: | |
4760 | if (test_bit(FW_FLAGS_START, &fw_flags) || | |
4761 | test_bit(FW_FLAGS_NC, &fw_flags) || | |
4762 | test_bit(FW_FLAGS_NC1, &fw_flags) || | |
4763 | test_bit(FW_FLAGS_NC2, &fw_flags) || | |
4764 | test_bit(FW_FLAGS_UC2, &fw_flags) || | |
4765 | test_bit(FW_FLAGS_UC, &fw_flags) || | |
4766 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
4767 | dev_err(&tp->intf->dev, "Invalid order to set PHY version\n"); | |
4768 | goto fail; | |
4769 | } | |
4770 | ||
4771 | if (test_bit(FW_FLAGS_VER, &fw_flags)) { | |
4772 | dev_err(&tp->intf->dev, "multiple PHY version encountered"); | |
4773 | goto fail; | |
4774 | } | |
4775 | ||
4776 | if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) { | |
4777 | dev_err(&tp->intf->dev, "check PHY version failed\n"); | |
4778 | goto fail; | |
4779 | } | |
4780 | __set_bit(FW_FLAGS_VER, &fw_flags); | |
9370f2d0 HW |
4781 | break; |
4782 | default: | |
4783 | dev_warn(&tp->intf->dev, "Unknown type %u is found\n", | |
4784 | type); | |
4785 | break; | |
4786 | } | |
4787 | ||
4788 | /* next block */ | |
4789 | i += ALIGN(__le32_to_cpu(block->length), 8); | |
4790 | } | |
4791 | ||
af14288f | 4792 | fw_end: |
a8a7be17 | 4793 | if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) { |
af14288f HW |
4794 | dev_err(&tp->intf->dev, "without PHY_STOP\n"); |
4795 | goto fail; | |
4796 | } | |
4797 | ||
9370f2d0 HW |
4798 | return 0; |
4799 | fail: | |
4800 | return ret; | |
4801 | } | |
4802 | ||
4a51b0e8 HW |
4803 | static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait) |
4804 | { | |
4805 | u32 len; | |
4806 | u8 *data; | |
4807 | ||
b24edca3 HW |
4808 | rtl_reset_ocp_base(tp); |
4809 | ||
4a51b0e8 HW |
4810 | if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) { |
4811 | dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n"); | |
4812 | return; | |
4813 | } | |
4814 | ||
4815 | len = __le32_to_cpu(phy->blk_hdr.length); | |
4816 | len -= __le16_to_cpu(phy->fw_offset); | |
4817 | data = (u8 *)phy + __le16_to_cpu(phy->fw_offset); | |
4818 | ||
4819 | if (rtl_phy_patch_request(tp, true, wait)) | |
4820 | return; | |
4821 | ||
4822 | while (len) { | |
4823 | u32 ocp_data, size; | |
4824 | int i; | |
4825 | ||
4826 | if (len < 2048) | |
4827 | size = len; | |
4828 | else | |
4829 | size = 2048; | |
4830 | ||
4831 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL); | |
4832 | ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE; | |
4833 | ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data); | |
4834 | ||
4835 | generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB); | |
4836 | ||
4837 | data += size; | |
4838 | len -= size; | |
4839 | ||
4840 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL); | |
4841 | ocp_data |= POL_GPHY_PATCH; | |
4842 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data); | |
4843 | ||
4844 | for (i = 0; i < 1000; i++) { | |
4845 | if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH)) | |
4846 | break; | |
4847 | } | |
4848 | ||
4849 | if (i == 1000) { | |
4850 | dev_err(&tp->intf->dev, "ram code speedup mode timeout\n"); | |
f49c35b8 | 4851 | break; |
4a51b0e8 HW |
4852 | } |
4853 | } | |
4854 | ||
b24edca3 HW |
4855 | rtl_reset_ocp_base(tp); |
4856 | ||
4a51b0e8 HW |
4857 | rtl_phy_patch_request(tp, false, wait); |
4858 | ||
4859 | if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version)) | |
4860 | dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); | |
4861 | else | |
4862 | dev_err(&tp->intf->dev, "ram code speedup mode fail\n"); | |
4863 | } | |
4864 | ||
4865 | static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver) | |
4866 | { | |
4867 | u16 ver_addr, ver; | |
4868 | ||
4869 | ver_addr = __le16_to_cpu(phy_ver->ver.addr); | |
4870 | ver = __le16_to_cpu(phy_ver->ver.data); | |
4871 | ||
b24edca3 HW |
4872 | rtl_reset_ocp_base(tp); |
4873 | ||
4a51b0e8 HW |
4874 | if (sram_read(tp, ver_addr) >= ver) { |
4875 | dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n"); | |
4876 | return 0; | |
4877 | } | |
4878 | ||
4879 | sram_write(tp, ver_addr, ver); | |
4880 | ||
4881 | dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver); | |
4882 | ||
4883 | return ver; | |
4884 | } | |
4885 | ||
4886 | static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix) | |
4887 | { | |
4888 | u16 addr, data; | |
4889 | ||
b24edca3 HW |
4890 | rtl_reset_ocp_base(tp); |
4891 | ||
4a51b0e8 HW |
4892 | addr = __le16_to_cpu(fix->setting.addr); |
4893 | data = ocp_reg_read(tp, addr); | |
4894 | ||
4895 | switch (__le16_to_cpu(fix->bit_cmd)) { | |
4896 | case FW_FIXUP_AND: | |
4897 | data &= __le16_to_cpu(fix->setting.data); | |
4898 | break; | |
4899 | case FW_FIXUP_OR: | |
4900 | data |= __le16_to_cpu(fix->setting.data); | |
4901 | break; | |
4902 | case FW_FIXUP_NOT: | |
4903 | data &= ~__le16_to_cpu(fix->setting.data); | |
4904 | break; | |
4905 | case FW_FIXUP_XOR: | |
4906 | data ^= __le16_to_cpu(fix->setting.data); | |
4907 | break; | |
4908 | default: | |
4909 | return; | |
4910 | } | |
4911 | ||
4912 | ocp_reg_write(tp, addr, data); | |
4913 | ||
4914 | dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data); | |
4915 | } | |
4916 | ||
4917 | static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy) | |
4918 | { | |
4919 | __le16 *data; | |
4920 | u32 length; | |
4921 | int i, num; | |
4922 | ||
b24edca3 HW |
4923 | rtl_reset_ocp_base(tp); |
4924 | ||
4a51b0e8 HW |
4925 | num = phy->pre_num; |
4926 | for (i = 0; i < num; i++) | |
4927 | sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr), | |
4928 | __le16_to_cpu(phy->pre_set[i].data)); | |
4929 | ||
4930 | length = __le32_to_cpu(phy->blk_hdr.length); | |
4931 | length -= __le16_to_cpu(phy->fw_offset); | |
4932 | num = length / 2; | |
4933 | data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset)); | |
4934 | ||
4935 | ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg)); | |
4936 | for (i = 0; i < num; i++) | |
4937 | ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i])); | |
4938 | ||
4939 | num = phy->bp_num; | |
4940 | for (i = 0; i < num; i++) | |
4941 | sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data)); | |
4942 | ||
4943 | if (phy->bp_num && phy->bp_en.addr) | |
4944 | sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data)); | |
4945 | ||
4946 | dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); | |
4947 | } | |
4948 | ||
af14288f HW |
4949 | static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy) |
4950 | { | |
4951 | u16 mode_reg, bp_index; | |
4952 | u32 length, i, num; | |
4953 | __le16 *data; | |
4954 | ||
b24edca3 HW |
4955 | rtl_reset_ocp_base(tp); |
4956 | ||
af14288f HW |
4957 | mode_reg = __le16_to_cpu(phy->mode_reg); |
4958 | sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre)); | |
4959 | sram_write(tp, __le16_to_cpu(phy->ba_reg), | |
4960 | __le16_to_cpu(phy->ba_data)); | |
4961 | ||
4962 | length = __le32_to_cpu(phy->blk_hdr.length); | |
4963 | length -= __le16_to_cpu(phy->fw_offset); | |
4964 | num = length / 2; | |
4965 | data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset)); | |
4966 | ||
4967 | ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg)); | |
4968 | for (i = 0; i < num; i++) | |
4969 | ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i])); | |
4970 | ||
4971 | sram_write(tp, __le16_to_cpu(phy->patch_en_addr), | |
4972 | __le16_to_cpu(phy->patch_en_value)); | |
4973 | ||
4974 | bp_index = __le16_to_cpu(phy->bp_start); | |
4975 | num = __le16_to_cpu(phy->bp_num); | |
4976 | for (i = 0; i < num; i++) { | |
4977 | sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i])); | |
4978 | bp_index += 2; | |
4979 | } | |
4980 | ||
4981 | sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post)); | |
4982 | ||
4983 | dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); | |
4984 | } | |
4985 | ||
a66edaaf | 4986 | static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac) |
9370f2d0 HW |
4987 | { |
4988 | u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg; | |
4989 | u32 length; | |
4990 | u8 *data; | |
4991 | int i; | |
4992 | ||
a66edaaf | 4993 | switch (__le32_to_cpu(mac->blk_hdr.type)) { |
9370f2d0 HW |
4994 | case RTL_FW_PLA: |
4995 | type = MCU_TYPE_PLA; | |
4996 | break; | |
4997 | case RTL_FW_USB: | |
4998 | type = MCU_TYPE_USB; | |
4999 | break; | |
5000 | default: | |
5001 | return; | |
5002 | } | |
5003 | ||
4a51b0e8 HW |
5004 | fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg); |
5005 | if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) { | |
5006 | dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB"); | |
5007 | return; | |
5008 | } | |
5009 | ||
9370f2d0 HW |
5010 | rtl_clear_bp(tp, type); |
5011 | ||
5012 | /* Enable backup/restore of MACDBG. This is required after clearing PLA | |
5013 | * break points and before applying the PLA firmware. | |
5014 | */ | |
5015 | if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA && | |
5016 | !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) { | |
5017 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM); | |
5018 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM); | |
5019 | } | |
5020 | ||
a66edaaf HW |
5021 | length = __le32_to_cpu(mac->blk_hdr.length); |
5022 | length -= __le16_to_cpu(mac->fw_offset); | |
9370f2d0 | 5023 | |
a66edaaf HW |
5024 | data = (u8 *)mac; |
5025 | data += __le16_to_cpu(mac->fw_offset); | |
9370f2d0 | 5026 | |
a66edaaf | 5027 | generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data, |
9370f2d0 HW |
5028 | type); |
5029 | ||
a66edaaf HW |
5030 | ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr), |
5031 | __le16_to_cpu(mac->bp_ba_value)); | |
9370f2d0 | 5032 | |
a66edaaf HW |
5033 | bp_index = __le16_to_cpu(mac->bp_start); |
5034 | bp_num = __le16_to_cpu(mac->bp_num); | |
9370f2d0 | 5035 | for (i = 0; i < bp_num; i++) { |
a66edaaf | 5036 | ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i])); |
9370f2d0 HW |
5037 | bp_index += 2; |
5038 | } | |
5039 | ||
a66edaaf | 5040 | bp_en_addr = __le16_to_cpu(mac->bp_en_addr); |
9370f2d0 HW |
5041 | if (bp_en_addr) |
5042 | ocp_write_word(tp, type, bp_en_addr, | |
a66edaaf | 5043 | __le16_to_cpu(mac->bp_en_value)); |
9370f2d0 | 5044 | |
9370f2d0 HW |
5045 | if (fw_ver_reg) |
5046 | ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg, | |
a66edaaf | 5047 | mac->fw_ver_data); |
9370f2d0 | 5048 | |
a66edaaf | 5049 | dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info); |
9370f2d0 HW |
5050 | } |
5051 | ||
a08c0d30 | 5052 | static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut) |
9370f2d0 HW |
5053 | { |
5054 | struct rtl_fw *rtl_fw = &tp->rtl_fw; | |
8e484ebb HW |
5055 | const struct firmware *fw; |
5056 | struct fw_header *fw_hdr; | |
af14288f HW |
5057 | struct fw_phy_patch_key *key; |
5058 | u16 key_addr = 0; | |
4a51b0e8 | 5059 | int i, patch_phy = 1; |
9370f2d0 HW |
5060 | |
5061 | if (IS_ERR_OR_NULL(rtl_fw->fw)) | |
5062 | return; | |
5063 | ||
8e484ebb HW |
5064 | fw = rtl_fw->fw; |
5065 | fw_hdr = (struct fw_header *)fw->data; | |
5066 | ||
9370f2d0 HW |
5067 | if (rtl_fw->pre_fw) |
5068 | rtl_fw->pre_fw(tp); | |
5069 | ||
5070 | for (i = offsetof(struct fw_header, blocks); i < fw->size;) { | |
5071 | struct fw_block *block = (struct fw_block *)&fw->data[i]; | |
5072 | ||
5073 | switch (__le32_to_cpu(block->type)) { | |
5074 | case RTL_FW_END: | |
5075 | goto post_fw; | |
5076 | case RTL_FW_PLA: | |
5077 | case RTL_FW_USB: | |
a66edaaf | 5078 | rtl8152_fw_mac_apply(tp, (struct fw_mac *)block); |
9370f2d0 | 5079 | break; |
af14288f | 5080 | case RTL_FW_PHY_START: |
4a51b0e8 HW |
5081 | if (!patch_phy) |
5082 | break; | |
af14288f HW |
5083 | key = (struct fw_phy_patch_key *)block; |
5084 | key_addr = __le16_to_cpu(key->key_reg); | |
a08c0d30 | 5085 | rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut); |
af14288f HW |
5086 | break; |
5087 | case RTL_FW_PHY_STOP: | |
4a51b0e8 HW |
5088 | if (!patch_phy) |
5089 | break; | |
af14288f | 5090 | WARN_ON(!key_addr); |
a08c0d30 | 5091 | rtl_post_ram_code(tp, key_addr, !power_cut); |
af14288f HW |
5092 | break; |
5093 | case RTL_FW_PHY_NC: | |
5094 | rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block); | |
5095 | break; | |
4a51b0e8 HW |
5096 | case RTL_FW_PHY_VER: |
5097 | patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block); | |
5098 | break; | |
5099 | case RTL_FW_PHY_UNION_NC: | |
5100 | case RTL_FW_PHY_UNION_NC1: | |
5101 | case RTL_FW_PHY_UNION_NC2: | |
5102 | case RTL_FW_PHY_UNION_UC2: | |
5103 | case RTL_FW_PHY_UNION_UC: | |
5104 | case RTL_FW_PHY_UNION_MISC: | |
5105 | if (patch_phy) | |
5106 | rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block); | |
5107 | break; | |
5108 | case RTL_FW_PHY_FIXUP: | |
5109 | if (patch_phy) | |
5110 | rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block); | |
5111 | break; | |
5112 | case RTL_FW_PHY_SPEED_UP: | |
5113 | rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut); | |
5114 | break; | |
9370f2d0 HW |
5115 | default: |
5116 | break; | |
5117 | } | |
5118 | ||
5119 | i += ALIGN(__le32_to_cpu(block->length), 8); | |
5120 | } | |
5121 | ||
5122 | post_fw: | |
5123 | if (rtl_fw->post_fw) | |
5124 | rtl_fw->post_fw(tp); | |
5125 | ||
b24edca3 | 5126 | rtl_reset_ocp_base(tp); |
9370f2d0 HW |
5127 | strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE); |
5128 | dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version); | |
5129 | } | |
5130 | ||
5131 | static void rtl8152_release_firmware(struct r8152 *tp) | |
5132 | { | |
5133 | struct rtl_fw *rtl_fw = &tp->rtl_fw; | |
5134 | ||
5135 | if (!IS_ERR_OR_NULL(rtl_fw->fw)) { | |
5136 | release_firmware(rtl_fw->fw); | |
5137 | rtl_fw->fw = NULL; | |
5138 | } | |
5139 | } | |
5140 | ||
5141 | static int rtl8152_request_firmware(struct r8152 *tp) | |
5142 | { | |
5143 | struct rtl_fw *rtl_fw = &tp->rtl_fw; | |
5144 | long rc; | |
5145 | ||
5146 | if (rtl_fw->fw || !rtl_fw->fw_name) { | |
5147 | dev_info(&tp->intf->dev, "skip request firmware\n"); | |
5148 | rc = 0; | |
5149 | goto result; | |
5150 | } | |
5151 | ||
5152 | rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev); | |
5153 | if (rc < 0) | |
5154 | goto result; | |
5155 | ||
5156 | rc = rtl8152_check_firmware(tp, rtl_fw); | |
5157 | if (rc < 0) | |
5158 | release_firmware(rtl_fw->fw); | |
5159 | ||
5160 | result: | |
5161 | if (rc) { | |
5162 | rtl_fw->fw = ERR_PTR(rc); | |
5163 | ||
5164 | dev_warn(&tp->intf->dev, | |
5165 | "unable to load firmware patch %s (%ld)\n", | |
5166 | rtl_fw->fw_name, rc); | |
5167 | } | |
5168 | ||
5169 | return rc; | |
5170 | } | |
5171 | ||
cda9fb01 | 5172 | static void r8152_aldps_en(struct r8152 *tp, bool enable) |
4349968a | 5173 | { |
cda9fb01 | 5174 | if (enable) { |
5175 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
5176 | LINKENA | DIS_SDSAVE); | |
5177 | } else { | |
5178 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | | |
5179 | DIS_SDSAVE); | |
5180 | msleep(20); | |
5181 | } | |
4349968a | 5182 | } |
5183 | ||
e6449539 | 5184 | static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) |
5185 | { | |
5186 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); | |
5187 | ocp_reg_write(tp, OCP_EEE_DATA, reg); | |
5188 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); | |
5189 | } | |
5190 | ||
5191 | static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) | |
5192 | { | |
5193 | u16 data; | |
5194 | ||
5195 | r8152_mmd_indirect(tp, dev, reg); | |
5196 | data = ocp_reg_read(tp, OCP_EEE_DATA); | |
5197 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
5198 | ||
5199 | return data; | |
5200 | } | |
5201 | ||
5202 | static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) | |
5203 | { | |
5204 | r8152_mmd_indirect(tp, dev, reg); | |
5205 | ocp_reg_write(tp, OCP_EEE_DATA, data); | |
5206 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
5207 | } | |
5208 | ||
5209 | static void r8152_eee_en(struct r8152 *tp, bool enable) | |
5210 | { | |
5211 | u16 config1, config2, config3; | |
5212 | u32 ocp_data; | |
5213 | ||
5214 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
5215 | config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; | |
5216 | config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); | |
5217 | config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; | |
5218 | ||
5219 | if (enable) { | |
5220 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
5221 | config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; | |
5222 | config1 |= sd_rise_time(1); | |
5223 | config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; | |
5224 | config3 |= fast_snr(42); | |
5225 | } else { | |
5226 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
5227 | config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | | |
5228 | RX_QUIET_EN); | |
5229 | config1 |= sd_rise_time(7); | |
5230 | config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); | |
5231 | config3 |= fast_snr(511); | |
5232 | } | |
5233 | ||
5234 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
5235 | ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); | |
5236 | ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); | |
5237 | ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); | |
5238 | } | |
5239 | ||
e7bde56b | 5240 | static void r8153_eee_en(struct r8152 *tp, bool enable) |
e6449539 | 5241 | { |
e7bde56b HW |
5242 | u32 ocp_data; |
5243 | u16 config; | |
5244 | ||
5245 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
5246 | config = ocp_reg_read(tp, OCP_EEE_CFG); | |
5247 | ||
5248 | if (enable) { | |
5249 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
5250 | config |= EEE10_EN; | |
f4a93be6 | 5251 | } else { |
e7bde56b HW |
5252 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); |
5253 | config &= ~EEE10_EN; | |
5254 | } | |
5255 | ||
5256 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
5257 | ocp_reg_write(tp, OCP_EEE_CFG, config); | |
e7bde56b | 5258 | |
0e5b36bc | 5259 | tp->ups_info.eee = enable; |
e7bde56b HW |
5260 | } |
5261 | ||
195aae32 HW |
5262 | static void r8156_eee_en(struct r8152 *tp, bool enable) |
5263 | { | |
5264 | u16 config; | |
5265 | ||
5266 | r8153_eee_en(tp, enable); | |
5267 | ||
5268 | config = ocp_reg_read(tp, OCP_EEE_ADV2); | |
5269 | ||
5270 | if (enable) | |
5271 | config |= MDIO_EEE_2_5GT; | |
5272 | else | |
5273 | config &= ~MDIO_EEE_2_5GT; | |
5274 | ||
5275 | ocp_reg_write(tp, OCP_EEE_ADV2, config); | |
5276 | } | |
5277 | ||
e7bde56b HW |
5278 | static void rtl_eee_enable(struct r8152 *tp, bool enable) |
5279 | { | |
5280 | switch (tp->version) { | |
5281 | case RTL_VER_01: | |
5282 | case RTL_VER_02: | |
5283 | case RTL_VER_07: | |
5284 | if (enable) { | |
5285 | r8152_eee_en(tp, true); | |
5286 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, | |
5287 | tp->eee_adv); | |
5288 | } else { | |
5289 | r8152_eee_en(tp, false); | |
5290 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); | |
5291 | } | |
5292 | break; | |
5293 | case RTL_VER_03: | |
5294 | case RTL_VER_04: | |
5295 | case RTL_VER_05: | |
5296 | case RTL_VER_06: | |
e7bde56b HW |
5297 | case RTL_VER_08: |
5298 | case RTL_VER_09: | |
195aae32 | 5299 | case RTL_VER_14: |
e7bde56b | 5300 | if (enable) { |
0e5b36bc | 5301 | r8153_eee_en(tp, true); |
e7bde56b HW |
5302 | ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); |
5303 | } else { | |
0e5b36bc | 5304 | r8153_eee_en(tp, false); |
e7bde56b HW |
5305 | ocp_reg_write(tp, OCP_EEE_ADV, 0); |
5306 | } | |
5307 | break; | |
195aae32 HW |
5308 | case RTL_VER_10: |
5309 | case RTL_VER_11: | |
5310 | case RTL_VER_12: | |
5311 | case RTL_VER_13: | |
5312 | case RTL_VER_15: | |
5313 | if (enable) { | |
5314 | r8156_eee_en(tp, true); | |
5315 | ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); | |
5316 | } else { | |
5317 | r8156_eee_en(tp, false); | |
5318 | ocp_reg_write(tp, OCP_EEE_ADV, 0); | |
5319 | } | |
5320 | break; | |
e7bde56b HW |
5321 | default: |
5322 | break; | |
f4a93be6 | 5323 | } |
e6449539 | 5324 | } |
5325 | ||
5326 | static void r8152b_enable_fc(struct r8152 *tp) | |
5327 | { | |
5328 | u16 anar; | |
5329 | ||
5330 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
5331 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
5332 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
0e5b36bc HW |
5333 | |
5334 | tp->ups_info.flow_control = true; | |
e6449539 | 5335 | } |
5336 | ||
d70b1137 | 5337 | static void rtl8152_disable(struct r8152 *tp) |
5338 | { | |
cda9fb01 | 5339 | r8152_aldps_en(tp, false); |
d70b1137 | 5340 | rtl_disable(tp); |
cda9fb01 | 5341 | r8152_aldps_en(tp, true); |
d70b1137 | 5342 | } |
5343 | ||
4349968a | 5344 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
5345 | { | |
a08c0d30 | 5346 | rtl8152_apply_firmware(tp, false); |
e7bde56b | 5347 | rtl_eee_enable(tp, tp->eee_en); |
ef39df8e | 5348 | r8152_aldps_en(tp, true); |
5349 | r8152b_enable_fc(tp); | |
f0cbe0ac | 5350 | |
aa66a5f1 | 5351 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 5352 | } |
5353 | ||
5f71c840 | 5354 | static void wait_oob_link_list_ready(struct r8152 *tp) |
ac718b69 | 5355 | { |
db8515ef | 5356 | u32 ocp_data; |
5357 | int i; | |
ac718b69 | 5358 | |
5f71c840 PM |
5359 | for (i = 0; i < 1000; i++) { |
5360 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
5361 | if (ocp_data & LINK_LIST_READY) | |
5362 | break; | |
5363 | usleep_range(1000, 2000); | |
5364 | } | |
5365 | } | |
5366 | ||
195aae32 HW |
5367 | static void r8156b_wait_loading_flash(struct r8152 *tp) |
5368 | { | |
5369 | if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) && | |
5370 | !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) { | |
5371 | int i; | |
5372 | ||
5373 | for (i = 0; i < 100; i++) { | |
5374 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE) | |
5375 | break; | |
5376 | usleep_range(1000, 2000); | |
5377 | } | |
5378 | } | |
5379 | } | |
5380 | ||
5f71c840 PM |
5381 | static void r8152b_exit_oob(struct r8152 *tp) |
5382 | { | |
5383 | u32 ocp_data; | |
5384 | ||
ac718b69 | 5385 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
5386 | ocp_data &= ~RCR_ACPT_ALL; | |
5387 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
5388 | ||
00a5e360 | 5389 | rxdy_gated_en(tp, true); |
da9bd117 | 5390 | r8153_teredo_off(tp); |
ac718b69 | 5391 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); |
5392 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
5393 | ||
5394 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
5395 | ocp_data &= ~NOW_IS_OOB; | |
5396 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
5397 | ||
5398 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
5399 | ocp_data &= ~MCU_BORW_EN; | |
5400 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
5401 | ||
5f71c840 | 5402 | wait_oob_link_list_ready(tp); |
ac718b69 | 5403 | |
5404 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
5405 | ocp_data |= RE_INIT_LL; | |
5406 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
5407 | ||
5f71c840 | 5408 | wait_oob_link_list_ready(tp); |
ac718b69 | 5409 | |
5410 | rtl8152_nic_reset(tp); | |
5411 | ||
5412 | /* rx share fifo credit full threshold */ | |
5413 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
5414 | ||
a3cc465d | 5415 | if (tp->udev->speed == USB_SPEED_FULL || |
5416 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 5417 | /* rx share fifo credit near full threshold */ |
5418 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
5419 | RXFIFO_THR2_FULL); | |
5420 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
5421 | RXFIFO_THR3_FULL); | |
5422 | } else { | |
5423 | /* rx share fifo credit near full threshold */ | |
5424 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
5425 | RXFIFO_THR2_HIGH); | |
5426 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
5427 | RXFIFO_THR3_HIGH); | |
5428 | } | |
5429 | ||
5430 | /* TX share fifo free credit full threshold */ | |
195aae32 | 5431 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); |
ac718b69 | 5432 | |
5433 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 5434 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 5435 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
5436 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
5437 | ||
c5554298 | 5438 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
ac718b69 | 5439 | |
5440 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
5441 | ||
5442 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
5443 | ocp_data |= TCR0_AUTO_FIFO; | |
5444 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
5445 | } | |
5446 | ||
5447 | static void r8152b_enter_oob(struct r8152 *tp) | |
5448 | { | |
45f4a19f | 5449 | u32 ocp_data; |
ac718b69 | 5450 | |
5451 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
5452 | ocp_data &= ~NOW_IS_OOB; | |
5453 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
5454 | ||
5455 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
5456 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
5457 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
5458 | ||
d70b1137 | 5459 | rtl_disable(tp); |
ac718b69 | 5460 | |
5f71c840 | 5461 | wait_oob_link_list_ready(tp); |
ac718b69 | 5462 | |
5463 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
5464 | ocp_data |= RE_INIT_LL; | |
5465 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
5466 | ||
5f71c840 | 5467 | wait_oob_link_list_ready(tp); |
ac718b69 | 5468 | |
5469 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
5470 | ||
c5554298 | 5471 | rtl_rx_vlan_en(tp, true); |
ac718b69 | 5472 | |
59c0b47a | 5473 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); |
ac718b69 | 5474 | ocp_data |= ALDPS_PROXY_MODE; |
59c0b47a | 5475 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); |
ac718b69 | 5476 | |
5477 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
5478 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
5479 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
5480 | ||
00a5e360 | 5481 | rxdy_gated_en(tp, false); |
ac718b69 | 5482 | |
5483 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
5484 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
5485 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
5486 | } | |
5487 | ||
9370f2d0 HW |
5488 | static int r8153_pre_firmware_1(struct r8152 *tp) |
5489 | { | |
5490 | int i; | |
5491 | ||
5492 | /* Wait till the WTD timer is ready. It would take at most 104 ms. */ | |
5493 | for (i = 0; i < 104; i++) { | |
5494 | u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL); | |
5495 | ||
5496 | if (!(ocp_data & WTD1_EN)) | |
5497 | break; | |
5498 | usleep_range(1000, 2000); | |
5499 | } | |
5500 | ||
5501 | return 0; | |
5502 | } | |
5503 | ||
5504 | static int r8153_post_firmware_1(struct r8152 *tp) | |
5505 | { | |
5506 | /* set USB_BP_4 to support USB_SPEED_SUPER only */ | |
5507 | if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) | |
5508 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY); | |
5509 | ||
5510 | /* reset UPHY timer to 36 ms */ | |
5511 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16); | |
5512 | ||
5513 | return 0; | |
5514 | } | |
5515 | ||
5516 | static int r8153_pre_firmware_2(struct r8152 *tp) | |
5517 | { | |
5518 | u32 ocp_data; | |
5519 | ||
5520 | r8153_pre_firmware_1(tp); | |
5521 | ||
5522 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0); | |
5523 | ocp_data &= ~FW_FIX_SUSPEND; | |
5524 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data); | |
5525 | ||
5526 | return 0; | |
5527 | } | |
5528 | ||
5529 | static int r8153_post_firmware_2(struct r8152 *tp) | |
5530 | { | |
5531 | u32 ocp_data; | |
5532 | ||
5533 | /* enable bp0 if support USB_SPEED_SUPER only */ | |
5534 | if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) { | |
5535 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN); | |
5536 | ocp_data |= BIT(0); | |
5537 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data); | |
5538 | } | |
5539 | ||
5540 | /* reset UPHY timer to 36 ms */ | |
5541 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16); | |
5542 | ||
5543 | /* enable U3P3 check, set the counter to 4 */ | |
5544 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4); | |
5545 | ||
5546 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0); | |
5547 | ocp_data |= FW_FIX_SUSPEND; | |
5548 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data); | |
5549 | ||
5550 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
5551 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
5552 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
5553 | ||
5554 | return 0; | |
5555 | } | |
5556 | ||
5557 | static int r8153_post_firmware_3(struct r8152 *tp) | |
5558 | { | |
5559 | u32 ocp_data; | |
5560 | ||
5561 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
5562 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
5563 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
5564 | ||
5565 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); | |
5566 | ocp_data |= FW_IP_RESET_EN; | |
5567 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); | |
5568 | ||
5569 | return 0; | |
5570 | } | |
5571 | ||
5572 | static int r8153b_pre_firmware_1(struct r8152 *tp) | |
5573 | { | |
5574 | /* enable fc timer and set timer to 1 second. */ | |
5575 | ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, | |
5576 | CTRL_TIMER_EN | (1000 / 8)); | |
5577 | ||
5578 | return 0; | |
5579 | } | |
5580 | ||
5581 | static int r8153b_post_firmware_1(struct r8152 *tp) | |
5582 | { | |
5583 | u32 ocp_data; | |
5584 | ||
5585 | /* enable bp0 for RTL8153-BND */ | |
5586 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); | |
5587 | if (ocp_data & BND_MASK) { | |
5588 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN); | |
5589 | ocp_data |= BIT(0); | |
5590 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data); | |
5591 | } | |
5592 | ||
5593 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); | |
5594 | ocp_data |= FLOW_CTRL_PATCH_OPT; | |
5595 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); | |
5596 | ||
5597 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); | |
5598 | ocp_data |= FC_PATCH_TASK; | |
5599 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
5600 | ||
5601 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); | |
5602 | ocp_data |= FW_IP_RESET_EN; | |
5603 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); | |
5604 | ||
5605 | return 0; | |
5606 | } | |
5607 | ||
195aae32 HW |
5608 | static int r8153c_post_firmware_1(struct r8152 *tp) |
5609 | { | |
5610 | u32 ocp_data; | |
5611 | ||
5612 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); | |
5613 | ocp_data |= FLOW_CTRL_PATCH_2; | |
5614 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); | |
5615 | ||
5616 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); | |
5617 | ocp_data |= FC_PATCH_TASK; | |
5618 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
5619 | ||
5620 | return 0; | |
5621 | } | |
5622 | ||
4a51b0e8 HW |
5623 | static int r8156a_post_firmware_1(struct r8152 *tp) |
5624 | { | |
5625 | u32 ocp_data; | |
5626 | ||
5627 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); | |
5628 | ocp_data |= FW_IP_RESET_EN; | |
5629 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); | |
5630 | ||
5631 | /* Modify U3PHY parameter for compatibility issue */ | |
5632 | ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e); | |
5633 | ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9); | |
5634 | ||
5635 | return 0; | |
5636 | } | |
5637 | ||
e6449539 | 5638 | static void r8153_aldps_en(struct r8152 *tp, bool enable) |
5639 | { | |
5640 | u16 data; | |
5641 | ||
5642 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
5643 | if (enable) { | |
5644 | data |= EN_ALDPS; | |
5645 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
5646 | } else { | |
4214cc55 | 5647 | int i; |
5648 | ||
e6449539 | 5649 | data &= ~EN_ALDPS; |
5650 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
4214cc55 | 5651 | for (i = 0; i < 20; i++) { |
5652 | usleep_range(1000, 2000); | |
5653 | if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) | |
5654 | break; | |
5655 | } | |
e6449539 | 5656 | } |
e6449539 | 5657 | |
0e5b36bc | 5658 | tp->ups_info.aldps = enable; |
65b82d69 | 5659 | } |
5660 | ||
43779f8d | 5661 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
5662 | { | |
5663 | u32 ocp_data; | |
5664 | u16 data; | |
5665 | ||
d768c61b | 5666 | /* disable ALDPS before updating the PHY parameters */ |
5667 | r8153_aldps_en(tp, false); | |
fb02eb4a | 5668 | |
d768c61b | 5669 | /* disable EEE before updating the PHY parameters */ |
e7bde56b | 5670 | rtl_eee_enable(tp, false); |
43779f8d | 5671 | |
a08c0d30 | 5672 | rtl8152_apply_firmware(tp, false); |
9370f2d0 | 5673 | |
43779f8d | 5674 | if (tp->version == RTL_VER_03) { |
5675 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
5676 | data &= ~CTAP_SHORT_EN; | |
5677 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
5678 | } | |
5679 | ||
5680 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
5681 | data |= EEE_CLKDIV_EN; | |
5682 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
5683 | ||
5684 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
5685 | data |= EN_10M_BGOFF; | |
5686 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
5687 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
5688 | data |= EN_10M_PLLOFF; | |
5689 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
b4d99def | 5690 | sram_write(tp, SRAM_IMPEDANCE, 0x0b13); |
43779f8d | 5691 | |
5692 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
5693 | ocp_data |= PFM_PWM_SWITCH; | |
5694 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
5695 | ||
b4d99def | 5696 | /* Enable LPF corner auto tune */ |
5697 | sram_write(tp, SRAM_LPF_CFG, 0xf70f); | |
43779f8d | 5698 | |
b4d99def | 5699 | /* Adjust 10M Amplitude */ |
5700 | sram_write(tp, SRAM_10M_AMP1, 0x00af); | |
5701 | sram_write(tp, SRAM_10M_AMP2, 0x0208); | |
aa66a5f1 | 5702 | |
e7bde56b HW |
5703 | if (tp->eee_en) |
5704 | rtl_eee_enable(tp, true); | |
af0287ec | 5705 | |
ef39df8e | 5706 | r8153_aldps_en(tp, true); |
5707 | r8152b_enable_fc(tp); | |
5708 | ||
3cb3234e | 5709 | switch (tp->version) { |
5710 | case RTL_VER_03: | |
5711 | case RTL_VER_04: | |
5712 | break; | |
5713 | case RTL_VER_05: | |
5714 | case RTL_VER_06: | |
5715 | default: | |
5716 | r8153_u2p3en(tp, true); | |
5717 | break; | |
5718 | } | |
5719 | ||
aa66a5f1 | 5720 | set_bit(PHY_RESET, &tp->flags); |
43779f8d | 5721 | } |
5722 | ||
65b82d69 | 5723 | static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) |
5724 | { | |
5725 | u32 ocp_data; | |
5726 | ||
5727 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); | |
5728 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); | |
5729 | ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ | |
5730 | ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); | |
5731 | ||
5732 | return ocp_data; | |
5733 | } | |
5734 | ||
5735 | static void r8153b_hw_phy_cfg(struct r8152 *tp) | |
5736 | { | |
0e5b36bc | 5737 | u32 ocp_data; |
65b82d69 | 5738 | u16 data; |
5739 | ||
80fd850b HW |
5740 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); |
5741 | if (ocp_data & PCUT_STATUS) { | |
5742 | ocp_data &= ~PCUT_STATUS; | |
5743 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
5744 | } | |
5745 | ||
65b82d69 | 5746 | /* disable ALDPS before updating the PHY parameters */ |
0e5b36bc | 5747 | r8153_aldps_en(tp, false); |
65b82d69 | 5748 | |
5749 | /* disable EEE before updating the PHY parameters */ | |
e7bde56b | 5750 | rtl_eee_enable(tp, false); |
65b82d69 | 5751 | |
80fd850b HW |
5752 | /* U1/U2/L1 idle timer. 500 us */ |
5753 | ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); | |
5754 | ||
5755 | data = r8153_phy_status(tp, 0); | |
5756 | ||
5757 | switch (data) { | |
5758 | case PHY_STAT_PWRDN: | |
5759 | case PHY_STAT_EXT_INIT: | |
5760 | rtl8152_apply_firmware(tp, true); | |
5761 | ||
5762 | data = r8152_mdio_read(tp, MII_BMCR); | |
5763 | data &= ~BMCR_PDOWN; | |
5764 | r8152_mdio_write(tp, MII_BMCR, data); | |
5765 | break; | |
5766 | case PHY_STAT_LAN_ON: | |
5767 | default: | |
5768 | rtl8152_apply_firmware(tp, false); | |
5769 | break; | |
5770 | } | |
9370f2d0 | 5771 | |
65b82d69 | 5772 | r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); |
5773 | ||
5774 | data = sram_read(tp, SRAM_GREEN_CFG); | |
5775 | data |= R_TUNE_EN; | |
5776 | sram_write(tp, SRAM_GREEN_CFG, data); | |
5777 | data = ocp_reg_read(tp, OCP_NCTL_CFG); | |
5778 | data |= PGA_RETURN_EN; | |
5779 | ocp_reg_write(tp, OCP_NCTL_CFG, data); | |
5780 | ||
5781 | /* ADC Bias Calibration: | |
5782 | * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake | |
5783 | * bit (bit3) to rebuild the real 16-bit data. Write the data to the | |
5784 | * ADC ioffset. | |
5785 | */ | |
5786 | ocp_data = r8152_efuse_read(tp, 0x7d); | |
5787 | data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); | |
5788 | if (data != 0xffff) | |
5789 | ocp_reg_write(tp, OCP_ADC_IOFFSET, data); | |
5790 | ||
5791 | /* ups mode tx-link-pulse timing adjustment: | |
5792 | * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] | |
5793 | * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt | |
5794 | */ | |
5795 | ocp_data = ocp_reg_read(tp, 0xc426); | |
5796 | ocp_data &= 0x3fff; | |
5797 | if (ocp_data) { | |
5798 | u32 swr_cnt_1ms_ini; | |
5799 | ||
5800 | swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; | |
5801 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); | |
5802 | ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; | |
5803 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); | |
5804 | } | |
5805 | ||
5806 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
5807 | ocp_data |= PFM_PWM_SWITCH; | |
5808 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
5809 | ||
5810 | /* Advnace EEE */ | |
a08c0d30 | 5811 | if (!rtl_phy_patch_request(tp, true, true)) { |
65b82d69 | 5812 | data = ocp_reg_read(tp, OCP_POWER_CFG); |
5813 | data |= EEE_CLKDIV_EN; | |
5814 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
0e5b36bc | 5815 | tp->ups_info.eee_ckdiv = true; |
65b82d69 | 5816 | |
5817 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
5818 | data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; | |
5819 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
0e5b36bc HW |
5820 | tp->ups_info.eee_cmod_lv = true; |
5821 | tp->ups_info._10m_ckdiv = true; | |
5822 | tp->ups_info.eee_plloff_giga = true; | |
65b82d69 | 5823 | |
5824 | ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); | |
5825 | ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); | |
0e5b36bc | 5826 | tp->ups_info._250m_ckdiv = true; |
65b82d69 | 5827 | |
a08c0d30 | 5828 | rtl_phy_patch_request(tp, false, true); |
65b82d69 | 5829 | } |
5830 | ||
e7bde56b HW |
5831 | if (tp->eee_en) |
5832 | rtl_eee_enable(tp, true); | |
65b82d69 | 5833 | |
0e5b36bc HW |
5834 | r8153_aldps_en(tp, true); |
5835 | r8152b_enable_fc(tp); | |
65b82d69 | 5836 | |
5837 | set_bit(PHY_RESET, &tp->flags); | |
5838 | } | |
5839 | ||
195aae32 HW |
5840 | static void r8153c_hw_phy_cfg(struct r8152 *tp) |
5841 | { | |
5842 | r8153b_hw_phy_cfg(tp); | |
5843 | ||
5844 | tp->ups_info.r_tune = true; | |
5845 | } | |
5846 | ||
67ce1a80 HW |
5847 | static void rtl8153_change_mtu(struct r8152 *tp) |
5848 | { | |
5849 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); | |
5850 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); | |
5851 | } | |
5852 | ||
43779f8d | 5853 | static void r8153_first_init(struct r8152 *tp) |
5854 | { | |
5855 | u32 ocp_data; | |
43779f8d | 5856 | |
00a5e360 | 5857 | rxdy_gated_en(tp, true); |
43779f8d | 5858 | r8153_teredo_off(tp); |
5859 | ||
5860 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
5861 | ocp_data &= ~RCR_ACPT_ALL; | |
5862 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
5863 | ||
43779f8d | 5864 | rtl8152_nic_reset(tp); |
93fe9b18 | 5865 | rtl_reset_bmu(tp); |
43779f8d | 5866 | |
5867 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
5868 | ocp_data &= ~NOW_IS_OOB; | |
5869 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
5870 | ||
5871 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
5872 | ocp_data &= ~MCU_BORW_EN; | |
5873 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
5874 | ||
5f71c840 | 5875 | wait_oob_link_list_ready(tp); |
43779f8d | 5876 | |
5877 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
5878 | ocp_data |= RE_INIT_LL; | |
5879 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
5880 | ||
5f71c840 | 5881 | wait_oob_link_list_ready(tp); |
43779f8d | 5882 | |
c5554298 | 5883 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
43779f8d | 5884 | |
67ce1a80 | 5885 | rtl8153_change_mtu(tp); |
43779f8d | 5886 | |
5887 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
5888 | ocp_data |= TCR0_AUTO_FIFO; | |
5889 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
5890 | ||
5891 | rtl8152_nic_reset(tp); | |
5892 | ||
5893 | /* rx share fifo credit full threshold */ | |
5894 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
5895 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
5896 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
5897 | /* TX share fifo free credit full threshold */ | |
5898 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
43779f8d | 5899 | } |
5900 | ||
5901 | static void r8153_enter_oob(struct r8152 *tp) | |
5902 | { | |
5903 | u32 ocp_data; | |
43779f8d | 5904 | |
5905 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
5906 | ocp_data &= ~NOW_IS_OOB; | |
5907 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
5908 | ||
d70b1137 | 5909 | rtl_disable(tp); |
93fe9b18 | 5910 | rtl_reset_bmu(tp); |
43779f8d | 5911 | |
5f71c840 | 5912 | wait_oob_link_list_ready(tp); |
43779f8d | 5913 | |
5914 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
5915 | ocp_data |= RE_INIT_LL; | |
5916 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
5917 | ||
5f71c840 | 5918 | wait_oob_link_list_ready(tp); |
43779f8d | 5919 | |
cdf0b86b HW |
5920 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522); |
5921 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT); | |
43779f8d | 5922 | |
65b82d69 | 5923 | switch (tp->version) { |
5924 | case RTL_VER_03: | |
5925 | case RTL_VER_04: | |
5926 | case RTL_VER_05: | |
5927 | case RTL_VER_06: | |
5928 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
5929 | ocp_data &= ~TEREDO_WAKE_MASK; | |
5930 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
5931 | break; | |
5932 | ||
5933 | case RTL_VER_08: | |
5934 | case RTL_VER_09: | |
195aae32 | 5935 | case RTL_VER_14: |
65b82d69 | 5936 | /* Clear teredo wake event. bit[15:8] is the teredo wakeup |
5937 | * type. Set it to zero. bits[7:0] are the W1C bits about | |
5938 | * the events. Set them to all 1 to clear them. | |
5939 | */ | |
5940 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); | |
5941 | break; | |
5942 | ||
5943 | default: | |
5944 | break; | |
5945 | } | |
43779f8d | 5946 | |
c5554298 | 5947 | rtl_rx_vlan_en(tp, true); |
43779f8d | 5948 | |
59c0b47a | 5949 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); |
43779f8d | 5950 | ocp_data |= ALDPS_PROXY_MODE; |
59c0b47a | 5951 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); |
43779f8d | 5952 | |
5953 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
5954 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
5955 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
5956 | ||
cdf0b86b HW |
5957 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
5958 | ocp_data |= MCU_BORW_EN; | |
5959 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
5960 | ||
00a5e360 | 5961 | rxdy_gated_en(tp, false); |
43779f8d | 5962 | |
5963 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
5964 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
5965 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
5966 | } | |
5967 | ||
d70b1137 | 5968 | static void rtl8153_disable(struct r8152 *tp) |
5969 | { | |
cda9fb01 | 5970 | r8153_aldps_en(tp, false); |
d70b1137 | 5971 | rtl_disable(tp); |
93fe9b18 | 5972 | rtl_reset_bmu(tp); |
cda9fb01 | 5973 | r8153_aldps_en(tp, true); |
d70b1137 | 5974 | } |
5975 | ||
195aae32 HW |
5976 | static int rtl8156_enable(struct r8152 *tp) |
5977 | { | |
5978 | u32 ocp_data; | |
5979 | u16 speed; | |
5980 | ||
5981 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
5982 | return -ENODEV; | |
5983 | ||
5984 | set_tx_qlen(tp); | |
5985 | rtl_set_eee_plus(tp); | |
5986 | r8153_set_rx_early_timeout(tp); | |
5987 | r8153_set_rx_early_size(tp); | |
5988 | ||
5989 | speed = rtl8152_get_speed(tp); | |
5990 | rtl_set_ifg(tp, speed); | |
5991 | ||
5992 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); | |
5993 | if (speed & _2500bps) | |
5994 | ocp_data &= ~IDLE_SPDWN_EN; | |
5995 | else | |
5996 | ocp_data |= IDLE_SPDWN_EN; | |
5997 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); | |
5998 | ||
5999 | if (speed & _1000bps) | |
6000 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); | |
6001 | else if (speed & _500bps) | |
6002 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); | |
6003 | ||
6004 | if (tp->udev->speed == USB_SPEED_HIGH) { | |
6005 | /* USB 0xb45e[3:0] l1_nyet_hird */ | |
6006 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); | |
6007 | ocp_data &= ~0xf; | |
6008 | if (is_flow_control(speed)) | |
6009 | ocp_data |= 0xf; | |
6010 | else | |
6011 | ocp_data |= 0x1; | |
6012 | ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); | |
6013 | } | |
6014 | ||
6015 | return rtl_enable(tp); | |
6016 | } | |
6017 | ||
6018 | static int rtl8156b_enable(struct r8152 *tp) | |
6019 | { | |
6020 | u32 ocp_data; | |
6021 | u16 speed; | |
6022 | ||
6023 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
6024 | return -ENODEV; | |
6025 | ||
6026 | set_tx_qlen(tp); | |
6027 | rtl_set_eee_plus(tp); | |
6028 | ||
6029 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM); | |
6030 | ocp_data &= ~RX_AGGR_NUM_MASK; | |
6031 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data); | |
6032 | ||
6033 | r8153_set_rx_early_timeout(tp); | |
6034 | r8153_set_rx_early_size(tp); | |
6035 | ||
6036 | speed = rtl8152_get_speed(tp); | |
6037 | rtl_set_ifg(tp, speed); | |
6038 | ||
6039 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); | |
6040 | if (speed & _2500bps) | |
6041 | ocp_data &= ~IDLE_SPDWN_EN; | |
6042 | else | |
6043 | ocp_data |= IDLE_SPDWN_EN; | |
6044 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); | |
6045 | ||
6046 | if (tp->udev->speed == USB_SPEED_HIGH) { | |
6047 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); | |
6048 | ocp_data &= ~0xf; | |
6049 | if (is_flow_control(speed)) | |
6050 | ocp_data |= 0xf; | |
6051 | else | |
6052 | ocp_data |= 0x1; | |
6053 | ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); | |
6054 | } | |
6055 | ||
6056 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); | |
6057 | ocp_data &= ~FC_PATCH_TASK; | |
6058 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
6059 | usleep_range(1000, 2000); | |
6060 | ocp_data |= FC_PATCH_TASK; | |
6061 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
6062 | ||
6063 | return rtl_enable(tp); | |
6064 | } | |
6065 | ||
771efeda HW |
6066 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, |
6067 | u32 advertising) | |
ac718b69 | 6068 | { |
771efeda | 6069 | u16 bmcr; |
ac718b69 | 6070 | int ret = 0; |
6071 | ||
ac718b69 | 6072 | if (autoneg == AUTONEG_DISABLE) { |
771efeda HW |
6073 | if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL) |
6074 | return -EINVAL; | |
ac718b69 | 6075 | |
771efeda HW |
6076 | switch (speed) { |
6077 | case SPEED_10: | |
6078 | bmcr = BMCR_SPEED10; | |
65b82d69 | 6079 | if (duplex == DUPLEX_FULL) { |
771efeda | 6080 | bmcr |= BMCR_FULLDPLX; |
0e5b36bc | 6081 | tp->ups_info.speed_duplex = FORCE_10M_FULL; |
65b82d69 | 6082 | } else { |
0e5b36bc | 6083 | tp->ups_info.speed_duplex = FORCE_10M_HALF; |
65b82d69 | 6084 | } |
771efeda HW |
6085 | break; |
6086 | case SPEED_100: | |
6087 | bmcr = BMCR_SPEED100; | |
ac718b69 | 6088 | if (duplex == DUPLEX_FULL) { |
771efeda | 6089 | bmcr |= BMCR_FULLDPLX; |
0e5b36bc | 6090 | tp->ups_info.speed_duplex = FORCE_100M_FULL; |
ac718b69 | 6091 | } else { |
0e5b36bc | 6092 | tp->ups_info.speed_duplex = FORCE_100M_HALF; |
ac718b69 | 6093 | } |
771efeda HW |
6094 | break; |
6095 | case SPEED_1000: | |
6096 | if (tp->mii.supports_gmii) { | |
6097 | bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX; | |
0e5b36bc | 6098 | tp->ups_info.speed_duplex = NWAY_1000M_FULL; |
771efeda | 6099 | break; |
43779f8d | 6100 | } |
df561f66 | 6101 | fallthrough; |
771efeda | 6102 | default: |
ac718b69 | 6103 | ret = -EINVAL; |
6104 | goto out; | |
6105 | } | |
6106 | ||
771efeda HW |
6107 | if (duplex == DUPLEX_FULL) |
6108 | tp->mii.full_duplex = 1; | |
6109 | else | |
6110 | tp->mii.full_duplex = 0; | |
6111 | ||
6112 | tp->mii.force_media = 1; | |
6113 | } else { | |
195aae32 | 6114 | u16 orig, new1; |
771efeda HW |
6115 | u32 support; |
6116 | ||
6117 | support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | | |
6118 | RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; | |
6119 | ||
195aae32 | 6120 | if (tp->mii.supports_gmii) { |
771efeda HW |
6121 | support |= RTL_ADVERTISED_1000_FULL; |
6122 | ||
195aae32 HW |
6123 | if (tp->support_2500full) |
6124 | support |= RTL_ADVERTISED_2500_FULL; | |
6125 | } | |
6126 | ||
771efeda HW |
6127 | if (!(advertising & support)) |
6128 | return -EINVAL; | |
6129 | ||
195aae32 HW |
6130 | orig = r8152_mdio_read(tp, MII_ADVERTISE); |
6131 | new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
771efeda HW |
6132 | ADVERTISE_100HALF | ADVERTISE_100FULL); |
6133 | if (advertising & RTL_ADVERTISED_10_HALF) { | |
195aae32 | 6134 | new1 |= ADVERTISE_10HALF; |
0e5b36bc | 6135 | tp->ups_info.speed_duplex = NWAY_10M_HALF; |
771efeda HW |
6136 | } |
6137 | if (advertising & RTL_ADVERTISED_10_FULL) { | |
195aae32 | 6138 | new1 |= ADVERTISE_10FULL; |
0e5b36bc | 6139 | tp->ups_info.speed_duplex = NWAY_10M_FULL; |
771efeda HW |
6140 | } |
6141 | ||
6142 | if (advertising & RTL_ADVERTISED_100_HALF) { | |
195aae32 | 6143 | new1 |= ADVERTISE_100HALF; |
0e5b36bc | 6144 | tp->ups_info.speed_duplex = NWAY_100M_HALF; |
771efeda HW |
6145 | } |
6146 | if (advertising & RTL_ADVERTISED_100_FULL) { | |
195aae32 | 6147 | new1 |= ADVERTISE_100FULL; |
0e5b36bc | 6148 | tp->ups_info.speed_duplex = NWAY_100M_FULL; |
771efeda HW |
6149 | } |
6150 | ||
195aae32 HW |
6151 | if (orig != new1) { |
6152 | r8152_mdio_write(tp, MII_ADVERTISE, new1); | |
6153 | tp->mii.advertising = new1; | |
771efeda HW |
6154 | } |
6155 | ||
6156 | if (tp->mii.supports_gmii) { | |
195aae32 HW |
6157 | orig = r8152_mdio_read(tp, MII_CTRL1000); |
6158 | new1 = orig & ~(ADVERTISE_1000FULL | | |
771efeda HW |
6159 | ADVERTISE_1000HALF); |
6160 | ||
6161 | if (advertising & RTL_ADVERTISED_1000_FULL) { | |
195aae32 | 6162 | new1 |= ADVERTISE_1000FULL; |
0e5b36bc | 6163 | tp->ups_info.speed_duplex = NWAY_1000M_FULL; |
771efeda HW |
6164 | } |
6165 | ||
195aae32 HW |
6166 | if (orig != new1) |
6167 | r8152_mdio_write(tp, MII_CTRL1000, new1); | |
6168 | } | |
6169 | ||
6170 | if (tp->support_2500full) { | |
6171 | orig = ocp_reg_read(tp, OCP_10GBT_CTRL); | |
6172 | new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G; | |
6173 | ||
6174 | if (advertising & RTL_ADVERTISED_2500_FULL) { | |
6175 | new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G; | |
6176 | tp->ups_info.speed_duplex = NWAY_2500M_FULL; | |
6177 | } | |
6178 | ||
6179 | if (orig != new1) | |
6180 | ocp_reg_write(tp, OCP_10GBT_CTRL, new1); | |
771efeda HW |
6181 | } |
6182 | ||
ac718b69 | 6183 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
771efeda HW |
6184 | |
6185 | tp->mii.force_media = 0; | |
ac718b69 | 6186 | } |
6187 | ||
fae56178 | 6188 | if (test_and_clear_bit(PHY_RESET, &tp->flags)) |
aa66a5f1 | 6189 | bmcr |= BMCR_RESET; |
6190 | ||
ac718b69 | 6191 | r8152_mdio_write(tp, MII_BMCR, bmcr); |
6192 | ||
fae56178 | 6193 | if (bmcr & BMCR_RESET) { |
aa66a5f1 | 6194 | int i; |
6195 | ||
aa66a5f1 | 6196 | for (i = 0; i < 50; i++) { |
6197 | msleep(20); | |
6198 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
6199 | break; | |
6200 | } | |
6201 | } | |
6202 | ||
ac718b69 | 6203 | out: |
ac718b69 | 6204 | return ret; |
6205 | } | |
6206 | ||
d70b1137 | 6207 | static void rtl8152_up(struct r8152 *tp) |
6208 | { | |
6209 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
6210 | return; | |
6211 | ||
cda9fb01 | 6212 | r8152_aldps_en(tp, false); |
d70b1137 | 6213 | r8152b_exit_oob(tp); |
cda9fb01 | 6214 | r8152_aldps_en(tp, true); |
d70b1137 | 6215 | } |
6216 | ||
ac718b69 | 6217 | static void rtl8152_down(struct r8152 *tp) |
6218 | { | |
6871438c | 6219 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
6220 | rtl_drop_queued_tx(tp); | |
6221 | return; | |
6222 | } | |
6223 | ||
00a5e360 | 6224 | r8152_power_cut_en(tp, false); |
cda9fb01 | 6225 | r8152_aldps_en(tp, false); |
ac718b69 | 6226 | r8152b_enter_oob(tp); |
cda9fb01 | 6227 | r8152_aldps_en(tp, true); |
ac718b69 | 6228 | } |
6229 | ||
d70b1137 | 6230 | static void rtl8153_up(struct r8152 *tp) |
6231 | { | |
19813162 HW |
6232 | u32 ocp_data; |
6233 | ||
d70b1137 | 6234 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
6235 | return; | |
6236 | ||
b214396f | 6237 | r8153_u1u2en(tp, false); |
3cb3234e | 6238 | r8153_u2p3en(tp, false); |
cda9fb01 | 6239 | r8153_aldps_en(tp, false); |
d70b1137 | 6240 | r8153_first_init(tp); |
19813162 HW |
6241 | |
6242 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); | |
6243 | ocp_data |= LANWAKE_CLR_EN; | |
6244 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); | |
6245 | ||
6246 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG); | |
6247 | ocp_data &= ~LANWAKE_PIN; | |
6248 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); | |
6249 | ||
aa475d93 HW |
6250 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1); |
6251 | ocp_data &= ~DELAY_PHY_PWR_CHG; | |
6252 | ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data); | |
6253 | ||
cda9fb01 | 6254 | r8153_aldps_en(tp, true); |
3cb3234e | 6255 | |
6256 | switch (tp->version) { | |
6257 | case RTL_VER_03: | |
6258 | case RTL_VER_04: | |
6259 | break; | |
6260 | case RTL_VER_05: | |
6261 | case RTL_VER_06: | |
6262 | default: | |
6263 | r8153_u2p3en(tp, true); | |
6264 | break; | |
6265 | } | |
6266 | ||
b214396f | 6267 | r8153_u1u2en(tp, true); |
d70b1137 | 6268 | } |
6269 | ||
43779f8d | 6270 | static void rtl8153_down(struct r8152 *tp) |
6271 | { | |
19813162 HW |
6272 | u32 ocp_data; |
6273 | ||
6871438c | 6274 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
6275 | rtl_drop_queued_tx(tp); | |
6276 | return; | |
6277 | } | |
6278 | ||
19813162 HW |
6279 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); |
6280 | ocp_data &= ~LANWAKE_CLR_EN; | |
6281 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); | |
6282 | ||
b9702723 | 6283 | r8153_u1u2en(tp, false); |
b214396f | 6284 | r8153_u2p3en(tp, false); |
b9702723 | 6285 | r8153_power_cut_en(tp, false); |
cda9fb01 | 6286 | r8153_aldps_en(tp, false); |
43779f8d | 6287 | r8153_enter_oob(tp); |
cda9fb01 | 6288 | r8153_aldps_en(tp, true); |
43779f8d | 6289 | } |
6290 | ||
65b82d69 | 6291 | static void rtl8153b_up(struct r8152 *tp) |
6292 | { | |
08997b5e HW |
6293 | u32 ocp_data; |
6294 | ||
65b82d69 | 6295 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
6296 | return; | |
6297 | ||
6298 | r8153b_u1u2en(tp, false); | |
6299 | r8153_u2p3en(tp, false); | |
0e5b36bc | 6300 | r8153_aldps_en(tp, false); |
65b82d69 | 6301 | |
6302 | r8153_first_init(tp); | |
6303 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); | |
6304 | ||
08997b5e HW |
6305 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); |
6306 | ocp_data &= ~PLA_MCU_SPDWN_EN; | |
6307 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
6308 | ||
0e5b36bc | 6309 | r8153_aldps_en(tp, true); |
a0246daf | 6310 | |
7a0ae61a | 6311 | if (tp->udev->speed >= USB_SPEED_SUPER) |
a0246daf | 6312 | r8153b_u1u2en(tp, true); |
65b82d69 | 6313 | } |
6314 | ||
6315 | static void rtl8153b_down(struct r8152 *tp) | |
6316 | { | |
08997b5e HW |
6317 | u32 ocp_data; |
6318 | ||
65b82d69 | 6319 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
6320 | rtl_drop_queued_tx(tp); | |
6321 | return; | |
6322 | } | |
6323 | ||
08997b5e HW |
6324 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); |
6325 | ocp_data |= PLA_MCU_SPDWN_EN; | |
6326 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
6327 | ||
65b82d69 | 6328 | r8153b_u1u2en(tp, false); |
6329 | r8153_u2p3en(tp, false); | |
6330 | r8153b_power_cut_en(tp, false); | |
0e5b36bc | 6331 | r8153_aldps_en(tp, false); |
65b82d69 | 6332 | r8153_enter_oob(tp); |
0e5b36bc | 6333 | r8153_aldps_en(tp, true); |
65b82d69 | 6334 | } |
6335 | ||
195aae32 | 6336 | static void rtl8153c_change_mtu(struct r8152 *tp) |
2dd49e0f | 6337 | { |
195aae32 HW |
6338 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); |
6339 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64); | |
2dd49e0f | 6340 | |
195aae32 | 6341 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); |
2dd49e0f | 6342 | |
195aae32 HW |
6343 | /* Adjust the tx fifo free credit full threshold, otherwise |
6344 | * the fifo would be too small to send a jumbo frame packet. | |
6345 | */ | |
6346 | if (tp->netdev->mtu < 8000) | |
6347 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8); | |
2dd49e0f | 6348 | else |
195aae32 | 6349 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8); |
2dd49e0f | 6350 | } |
6351 | ||
195aae32 | 6352 | static void rtl8153c_up(struct r8152 *tp) |
2dd49e0f | 6353 | { |
195aae32 | 6354 | u32 ocp_data; |
2dd49e0f | 6355 | |
195aae32 HW |
6356 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
6357 | return; | |
ac718b69 | 6358 | |
195aae32 HW |
6359 | r8153b_u1u2en(tp, false); |
6360 | r8153_u2p3en(tp, false); | |
6361 | r8153_aldps_en(tp, false); | |
ac718b69 | 6362 | |
195aae32 HW |
6363 | rxdy_gated_en(tp, true); |
6364 | r8153_teredo_off(tp); | |
ac718b69 | 6365 | |
195aae32 HW |
6366 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
6367 | ocp_data &= ~RCR_ACPT_ALL; | |
6368 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
ac718b69 | 6369 | |
195aae32 HW |
6370 | rtl8152_nic_reset(tp); |
6371 | rtl_reset_bmu(tp); | |
a1f83fee | 6372 | |
195aae32 HW |
6373 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
6374 | ocp_data &= ~NOW_IS_OOB; | |
6375 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
9a4be1bd | 6376 | |
195aae32 HW |
6377 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
6378 | ocp_data &= ~MCU_BORW_EN; | |
6379 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
ac718b69 | 6380 | |
195aae32 | 6381 | wait_oob_link_list_ready(tp); |
b5403273 | 6382 | |
195aae32 HW |
6383 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
6384 | ocp_data |= RE_INIT_LL; | |
6385 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
ac718b69 | 6386 | |
195aae32 | 6387 | wait_oob_link_list_ready(tp); |
ac718b69 | 6388 | |
195aae32 | 6389 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
aa66a5f1 | 6390 | |
195aae32 | 6391 | rtl8153c_change_mtu(tp); |
b5403273 | 6392 | |
195aae32 | 6393 | rtl8152_nic_reset(tp); |
ac718b69 | 6394 | |
195aae32 HW |
6395 | /* rx share fifo credit full threshold */ |
6396 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02); | |
6397 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08); | |
6398 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
6399 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
a028a9e0 | 6400 | |
195aae32 | 6401 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); |
a028a9e0 | 6402 | |
195aae32 HW |
6403 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); |
6404 | ||
6405 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
6406 | ocp_data |= BIT(8); | |
6407 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
6408 | ||
6409 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
6410 | ||
6411 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); | |
6412 | ocp_data &= ~PLA_MCU_SPDWN_EN; | |
6413 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
6414 | ||
6415 | r8153_aldps_en(tp, true); | |
6416 | r8153b_u1u2en(tp, true); | |
6417 | } | |
6418 | ||
6419 | static inline u32 fc_pause_on_auto(struct r8152 *tp) | |
6420 | { | |
6421 | return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024); | |
6422 | } | |
6423 | ||
6424 | static inline u32 fc_pause_off_auto(struct r8152 *tp) | |
6425 | { | |
6426 | return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024); | |
6427 | } | |
6428 | ||
6429 | static void r8156_fc_parameter(struct r8152 *tp) | |
6430 | { | |
6431 | u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp); | |
6432 | u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp); | |
6433 | ||
6434 | switch (tp->version) { | |
6435 | case RTL_VER_10: | |
6436 | case RTL_VER_11: | |
6437 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 8); | |
6438 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 8); | |
6439 | break; | |
6440 | case RTL_VER_12: | |
6441 | case RTL_VER_13: | |
6442 | case RTL_VER_15: | |
6443 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16); | |
6444 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16); | |
6445 | break; | |
6446 | default: | |
6447 | break; | |
6448 | } | |
6449 | } | |
6450 | ||
6451 | static void rtl8156_change_mtu(struct r8152 *tp) | |
6452 | { | |
6453 | u32 rx_max_size = mtu_to_size(tp->netdev->mtu); | |
6454 | ||
6455 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size); | |
6456 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); | |
6457 | r8156_fc_parameter(tp); | |
6458 | ||
6459 | /* TX share fifo free credit full threshold */ | |
6460 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); | |
6461 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, | |
6462 | ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16); | |
6463 | } | |
6464 | ||
6465 | static void rtl8156_up(struct r8152 *tp) | |
6466 | { | |
6467 | u32 ocp_data; | |
6468 | ||
6469 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
6470 | return; | |
6471 | ||
6472 | r8153b_u1u2en(tp, false); | |
6473 | r8153_u2p3en(tp, false); | |
6474 | r8153_aldps_en(tp, false); | |
6475 | ||
6476 | rxdy_gated_en(tp, true); | |
6477 | r8153_teredo_off(tp); | |
6478 | ||
6479 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
6480 | ocp_data &= ~RCR_ACPT_ALL; | |
6481 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
6482 | ||
6483 | rtl8152_nic_reset(tp); | |
6484 | rtl_reset_bmu(tp); | |
6485 | ||
6486 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
6487 | ocp_data &= ~NOW_IS_OOB; | |
6488 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
6489 | ||
6490 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
6491 | ocp_data &= ~MCU_BORW_EN; | |
6492 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
6493 | ||
6494 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); | |
6495 | ||
6496 | rtl8156_change_mtu(tp); | |
6497 | ||
6498 | switch (tp->version) { | |
6499 | case RTL_TEST_01: | |
6500 | case RTL_VER_10: | |
6501 | case RTL_VER_11: | |
6502 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG); | |
6503 | ocp_data |= ACT_ODMA; | |
6504 | ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); | |
6505 | break; | |
6506 | default: | |
6507 | break; | |
6508 | } | |
6509 | ||
6510 | /* share FIFO settings */ | |
6511 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL); | |
6512 | ocp_data &= ~RXFIFO_FULL_MASK; | |
6513 | ocp_data |= 0x08; | |
6514 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data); | |
6515 | ||
6516 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); | |
6517 | ocp_data &= ~PLA_MCU_SPDWN_EN; | |
6518 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
6519 | ||
6520 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION); | |
6521 | ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF); | |
6522 | ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data); | |
6523 | ||
6524 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); | |
6525 | ||
6526 | if (tp->saved_wolopts != __rtl_get_wol(tp)) { | |
6527 | netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n"); | |
6528 | __rtl_set_wol(tp, tp->saved_wolopts); | |
6529 | } | |
6530 | ||
6531 | r8153_aldps_en(tp, true); | |
6532 | r8153_u2p3en(tp, true); | |
6533 | ||
6534 | if (tp->udev->speed >= USB_SPEED_SUPER) | |
6535 | r8153b_u1u2en(tp, true); | |
6536 | } | |
6537 | ||
6538 | static void rtl8156_down(struct r8152 *tp) | |
6539 | { | |
6540 | u32 ocp_data; | |
6541 | ||
6542 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { | |
6543 | rtl_drop_queued_tx(tp); | |
6544 | return; | |
6545 | } | |
6546 | ||
6547 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); | |
6548 | ocp_data |= PLA_MCU_SPDWN_EN; | |
6549 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
6550 | ||
6551 | r8153b_u1u2en(tp, false); | |
6552 | r8153_u2p3en(tp, false); | |
6553 | r8153b_power_cut_en(tp, false); | |
6554 | r8153_aldps_en(tp, false); | |
6555 | ||
6556 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
6557 | ocp_data &= ~NOW_IS_OOB; | |
6558 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
6559 | ||
6560 | rtl_disable(tp); | |
6561 | rtl_reset_bmu(tp); | |
6562 | ||
cdf0b86b HW |
6563 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522); |
6564 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT); | |
6565 | ||
195aae32 HW |
6566 | /* Clear teredo wake event. bit[15:8] is the teredo wakeup |
6567 | * type. Set it to zero. bits[7:0] are the W1C bits about | |
6568 | * the events. Set them to all 1 to clear them. | |
6569 | */ | |
6570 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); | |
6571 | ||
6572 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
6573 | ocp_data |= NOW_IS_OOB; | |
6574 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
6575 | ||
cdf0b86b HW |
6576 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
6577 | ocp_data |= MCU_BORW_EN; | |
6578 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
6579 | ||
195aae32 HW |
6580 | rtl_rx_vlan_en(tp, true); |
6581 | rxdy_gated_en(tp, false); | |
6582 | ||
6583 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
6584 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
6585 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
6586 | ||
6587 | r8153_aldps_en(tp, true); | |
6588 | } | |
6589 | ||
6590 | static bool rtl8152_in_nway(struct r8152 *tp) | |
6591 | { | |
6592 | u16 nway_state; | |
6593 | ||
6594 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); | |
6595 | tp->ocp_base = 0x2000; | |
6596 | ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ | |
6597 | nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); | |
6598 | ||
6599 | /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ | |
6600 | if (nway_state & 0xc000) | |
6601 | return false; | |
6602 | else | |
6603 | return true; | |
6604 | } | |
6605 | ||
6606 | static bool rtl8153_in_nway(struct r8152 *tp) | |
6607 | { | |
6608 | u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; | |
6609 | ||
6610 | if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) | |
6611 | return false; | |
6612 | else | |
6613 | return true; | |
6614 | } | |
6615 | ||
45bf944e HW |
6616 | static void r8156_mdio_force_mode(struct r8152 *tp) |
6617 | { | |
6618 | u16 data; | |
6619 | ||
6620 | /* Select force mode through 0xa5b4 bit 15 | |
6621 | * 0: MDIO force mode | |
6622 | * 1: MMD force mode | |
6623 | */ | |
6624 | data = ocp_reg_read(tp, 0xa5b4); | |
6625 | if (data & BIT(15)) { | |
6626 | data &= ~BIT(15); | |
6627 | ocp_reg_write(tp, 0xa5b4, data); | |
6628 | } | |
6629 | } | |
6630 | ||
195aae32 HW |
6631 | static void set_carrier(struct r8152 *tp) |
6632 | { | |
6633 | struct net_device *netdev = tp->netdev; | |
6634 | struct napi_struct *napi = &tp->napi; | |
6635 | u16 speed; | |
6636 | ||
6637 | speed = rtl8152_get_speed(tp); | |
6638 | ||
6639 | if (speed & LINK_STATUS) { | |
6640 | if (!netif_carrier_ok(netdev)) { | |
6641 | tp->rtl_ops.enable(tp); | |
6642 | netif_stop_queue(netdev); | |
6643 | napi_disable(napi); | |
6644 | netif_carrier_on(netdev); | |
6645 | rtl_start_rx(tp); | |
6646 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); | |
6647 | _rtl8152_set_rx_mode(netdev); | |
6648 | napi_enable(napi); | |
6649 | netif_wake_queue(netdev); | |
6650 | netif_info(tp, link, netdev, "carrier on\n"); | |
6651 | } else if (netif_queue_stopped(netdev) && | |
6652 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { | |
6653 | netif_wake_queue(netdev); | |
6654 | } | |
6655 | } else { | |
6656 | if (netif_carrier_ok(netdev)) { | |
6657 | netif_carrier_off(netdev); | |
6658 | tasklet_disable(&tp->tx_tl); | |
6659 | napi_disable(napi); | |
6660 | tp->rtl_ops.disable(tp); | |
6661 | napi_enable(napi); | |
6662 | tasklet_enable(&tp->tx_tl); | |
6663 | netif_info(tp, link, netdev, "carrier off\n"); | |
6664 | } | |
6665 | } | |
6666 | } | |
6667 | ||
6668 | static void rtl_work_func_t(struct work_struct *work) | |
6669 | { | |
6670 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
6671 | ||
6672 | /* If the device is unplugged or !netif_running(), the workqueue | |
6673 | * doesn't need to wake the device, and could return directly. | |
6674 | */ | |
6675 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) | |
6676 | return; | |
6677 | ||
6678 | if (usb_autopm_get_interface(tp->intf) < 0) | |
6679 | return; | |
6680 | ||
6681 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
6682 | goto out1; | |
6683 | ||
6684 | if (!mutex_trylock(&tp->control)) { | |
6685 | schedule_delayed_work(&tp->schedule, 0); | |
6686 | goto out1; | |
6687 | } | |
6688 | ||
6689 | if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) | |
6690 | set_carrier(tp); | |
6691 | ||
6692 | if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
6693 | _rtl8152_set_rx_mode(tp->netdev); | |
6694 | ||
6695 | /* don't schedule tasket before linking */ | |
6696 | if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) && | |
6697 | netif_carrier_ok(tp->netdev)) | |
6698 | tasklet_schedule(&tp->tx_tl); | |
6699 | ||
baf33d7a HW |
6700 | if (test_and_clear_bit(RX_EPROTO, &tp->flags) && |
6701 | !list_empty(&tp->rx_done)) | |
6702 | napi_schedule(&tp->napi); | |
6703 | ||
195aae32 HW |
6704 | mutex_unlock(&tp->control); |
6705 | ||
6706 | out1: | |
6707 | usb_autopm_put_interface(tp->intf); | |
6708 | } | |
6709 | ||
6710 | static void rtl_hw_phy_work_func_t(struct work_struct *work) | |
6711 | { | |
6712 | struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); | |
6713 | ||
6714 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
6715 | return; | |
6716 | ||
6717 | if (usb_autopm_get_interface(tp->intf) < 0) | |
6718 | return; | |
a028a9e0 | 6719 | |
6720 | mutex_lock(&tp->control); | |
6721 | ||
9370f2d0 HW |
6722 | if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) { |
6723 | tp->rtl_fw.retry = false; | |
6724 | tp->rtl_fw.fw = NULL; | |
6725 | ||
6726 | /* Delay execution in case request_firmware() is not ready yet. | |
6727 | */ | |
6728 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10); | |
6729 | goto ignore_once; | |
6730 | } | |
6731 | ||
a028a9e0 | 6732 | tp->rtl_ops.hw_phy_cfg(tp); |
6733 | ||
771efeda HW |
6734 | rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex, |
6735 | tp->advertising); | |
9d21c0d8 | 6736 | |
9370f2d0 | 6737 | ignore_once: |
a028a9e0 | 6738 | mutex_unlock(&tp->control); |
6739 | ||
6740 | usb_autopm_put_interface(tp->intf); | |
6741 | } | |
6742 | ||
5ee3c60c | 6743 | #ifdef CONFIG_PM_SLEEP |
6744 | static int rtl_notifier(struct notifier_block *nb, unsigned long action, | |
6745 | void *data) | |
6746 | { | |
6747 | struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); | |
6748 | ||
6749 | switch (action) { | |
6750 | case PM_HIBERNATION_PREPARE: | |
6751 | case PM_SUSPEND_PREPARE: | |
6752 | usb_autopm_get_interface(tp->intf); | |
6753 | break; | |
6754 | ||
6755 | case PM_POST_HIBERNATION: | |
6756 | case PM_POST_SUSPEND: | |
6757 | usb_autopm_put_interface(tp->intf); | |
6758 | break; | |
6759 | ||
6760 | case PM_POST_RESTORE: | |
6761 | case PM_RESTORE_PREPARE: | |
6762 | default: | |
6763 | break; | |
6764 | } | |
6765 | ||
6766 | return NOTIFY_DONE; | |
6767 | } | |
6768 | #endif | |
6769 | ||
ac718b69 | 6770 | static int rtl8152_open(struct net_device *netdev) |
6771 | { | |
6772 | struct r8152 *tp = netdev_priv(netdev); | |
6773 | int res = 0; | |
6774 | ||
9370f2d0 HW |
6775 | if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) { |
6776 | cancel_delayed_work_sync(&tp->hw_phy_work); | |
6777 | rtl_hw_phy_work_func_t(&tp->hw_phy_work.work); | |
6778 | } | |
6779 | ||
7e9da481 | 6780 | res = alloc_all_mem(tp); |
6781 | if (res) | |
6782 | goto out; | |
6783 | ||
9a4be1bd | 6784 | res = usb_autopm_get_interface(tp->intf); |
ca0a7531 GR |
6785 | if (res < 0) |
6786 | goto out_free; | |
9a4be1bd | 6787 | |
b5403273 | 6788 | mutex_lock(&tp->control); |
6789 | ||
7e9da481 | 6790 | tp->rtl_ops.up(tp); |
6791 | ||
3d55f44f | 6792 | netif_carrier_off(netdev); |
6793 | netif_start_queue(netdev); | |
6794 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 6795 | |
40a82917 | 6796 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
6797 | if (res) { | |
6798 | if (res == -ENODEV) | |
6799 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
6800 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
6801 | res); | |
ca0a7531 | 6802 | goto out_unlock; |
ac718b69 | 6803 | } |
ca0a7531 | 6804 | napi_enable(&tp->napi); |
d2187f8e | 6805 | tasklet_enable(&tp->tx_tl); |
ac718b69 | 6806 | |
b5403273 | 6807 | mutex_unlock(&tp->control); |
6808 | ||
9a4be1bd | 6809 | usb_autopm_put_interface(tp->intf); |
5ee3c60c | 6810 | #ifdef CONFIG_PM_SLEEP |
6811 | tp->pm_notifier.notifier_call = rtl_notifier; | |
6812 | register_pm_notifier(&tp->pm_notifier); | |
6813 | #endif | |
ca0a7531 | 6814 | return 0; |
ac718b69 | 6815 | |
ca0a7531 GR |
6816 | out_unlock: |
6817 | mutex_unlock(&tp->control); | |
6818 | usb_autopm_put_interface(tp->intf); | |
6819 | out_free: | |
6820 | free_all_mem(tp); | |
7e9da481 | 6821 | out: |
ac718b69 | 6822 | return res; |
6823 | } | |
6824 | ||
6825 | static int rtl8152_close(struct net_device *netdev) | |
6826 | { | |
6827 | struct r8152 *tp = netdev_priv(netdev); | |
6828 | int res = 0; | |
6829 | ||
5ee3c60c | 6830 | #ifdef CONFIG_PM_SLEEP |
6831 | unregister_pm_notifier(&tp->pm_notifier); | |
6832 | #endif | |
d2187f8e | 6833 | tasklet_disable(&tp->tx_tl); |
ac718b69 | 6834 | clear_bit(WORK_ENABLE, &tp->flags); |
3d55f44f | 6835 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 6836 | cancel_delayed_work_sync(&tp->schedule); |
84811412 | 6837 | napi_disable(&tp->napi); |
ac718b69 | 6838 | netif_stop_queue(netdev); |
9a4be1bd | 6839 | |
6840 | res = usb_autopm_get_interface(tp->intf); | |
53543db5 | 6841 | if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { |
9a4be1bd | 6842 | rtl_drop_queued_tx(tp); |
d823ab68 | 6843 | rtl_stop_rx(tp); |
9a4be1bd | 6844 | } else { |
b5403273 | 6845 | mutex_lock(&tp->control); |
6846 | ||
9a4be1bd | 6847 | tp->rtl_ops.down(tp); |
b5403273 | 6848 | |
6849 | mutex_unlock(&tp->control); | |
9c23aa51 | 6850 | } |
b5403273 | 6851 | |
9c23aa51 | 6852 | if (!res) |
9a4be1bd | 6853 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 6854 | |
7e9da481 | 6855 | free_all_mem(tp); |
6856 | ||
ac718b69 | 6857 | return res; |
6858 | } | |
6859 | ||
4f1d4d54 | 6860 | static void rtl_tally_reset(struct r8152 *tp) |
6861 | { | |
6862 | u32 ocp_data; | |
6863 | ||
6864 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
6865 | ocp_data |= TALLY_RESET; | |
6866 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
6867 | } | |
6868 | ||
ac718b69 | 6869 | static void r8152b_init(struct r8152 *tp) |
6870 | { | |
ebc2ec48 | 6871 | u32 ocp_data; |
2dd436da | 6872 | u16 data; |
ac718b69 | 6873 | |
6871438c | 6874 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
6875 | return; | |
6876 | ||
2dd436da | 6877 | data = r8152_mdio_read(tp, MII_BMCR); |
6878 | if (data & BMCR_PDOWN) { | |
6879 | data &= ~BMCR_PDOWN; | |
6880 | r8152_mdio_write(tp, MII_BMCR, data); | |
6881 | } | |
6882 | ||
cda9fb01 | 6883 | r8152_aldps_en(tp, false); |
d70b1137 | 6884 | |
ac718b69 | 6885 | if (tp->version == RTL_VER_01) { |
6886 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
6887 | ocp_data &= ~LED_MODE_MASK; | |
6888 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
6889 | } | |
6890 | ||
00a5e360 | 6891 | r8152_power_cut_en(tp, false); |
ac718b69 | 6892 | |
ac718b69 | 6893 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
6894 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
6895 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
6896 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
6897 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
6898 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
6899 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
6900 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
6901 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
6902 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
6903 | ||
4f1d4d54 | 6904 | rtl_tally_reset(tp); |
ac718b69 | 6905 | |
ebc2ec48 | 6906 | /* enable rx aggregation */ |
ac718b69 | 6907 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
e90fba8d | 6908 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); |
ac718b69 | 6909 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
6910 | } | |
6911 | ||
195aae32 HW |
6912 | static void r8153_init(struct r8152 *tp) |
6913 | { | |
6914 | u32 ocp_data; | |
6915 | u16 data; | |
6916 | int i; | |
6917 | ||
6918 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
6919 | return; | |
6920 | ||
6921 | r8153_u1u2en(tp, false); | |
6922 | ||
6923 | for (i = 0; i < 500; i++) { | |
6924 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
6925 | AUTOLOAD_DONE) | |
6926 | break; | |
6927 | ||
6928 | msleep(20); | |
6929 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
6930 | break; | |
6931 | } | |
6932 | ||
6933 | data = r8153_phy_status(tp, 0); | |
6934 | ||
6935 | if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || | |
6936 | tp->version == RTL_VER_05) | |
6937 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
6938 | ||
6939 | data = r8152_mdio_read(tp, MII_BMCR); | |
6940 | if (data & BMCR_PDOWN) { | |
6941 | data &= ~BMCR_PDOWN; | |
6942 | r8152_mdio_write(tp, MII_BMCR, data); | |
6943 | } | |
6944 | ||
6945 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
6946 | ||
6947 | r8153_u2p3en(tp, false); | |
6948 | ||
6949 | if (tp->version == RTL_VER_04) { | |
6950 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); | |
6951 | ocp_data &= ~pwd_dn_scale_mask; | |
6952 | ocp_data |= pwd_dn_scale(96); | |
6953 | ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); | |
6954 | ||
6955 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
6956 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
6957 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
6958 | } else if (tp->version == RTL_VER_05) { | |
6959 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); | |
6960 | ocp_data &= ~ECM_ALDPS; | |
6961 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); | |
6962 | ||
6963 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); | |
6964 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
6965 | ocp_data &= ~DYNAMIC_BURST; | |
6966 | else | |
6967 | ocp_data |= DYNAMIC_BURST; | |
6968 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
6969 | } else if (tp->version == RTL_VER_06) { | |
6970 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); | |
6971 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
6972 | ocp_data &= ~DYNAMIC_BURST; | |
6973 | else | |
6974 | ocp_data |= DYNAMIC_BURST; | |
6975 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
6976 | ||
6977 | r8153_queue_wake(tp, false); | |
6978 | ||
6979 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); | |
6980 | if (rtl8152_get_speed(tp) & LINK_STATUS) | |
6981 | ocp_data |= CUR_LINK_OK; | |
6982 | else | |
6983 | ocp_data &= ~CUR_LINK_OK; | |
6984 | ocp_data |= POLL_LINK_CHG; | |
6985 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); | |
6986 | } | |
6987 | ||
6988 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); | |
6989 | ocp_data |= EP4_FULL_FC; | |
6990 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); | |
6991 | ||
6992 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); | |
6993 | ocp_data &= ~TIMER11_EN; | |
6994 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
6995 | ||
6996 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
6997 | ocp_data &= ~LED_MODE_MASK; | |
6998 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
6999 | ||
7000 | ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; | |
7001 | if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) | |
7002 | ocp_data |= LPM_TIMER_500MS; | |
7003 | else | |
7004 | ocp_data |= LPM_TIMER_500US; | |
7005 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); | |
7006 | ||
7007 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
7008 | ocp_data &= ~SEN_VAL_MASK; | |
7009 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
7010 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
7011 | ||
7012 | ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); | |
7013 | ||
7014 | r8153_power_cut_en(tp, false); | |
7015 | rtl_runtime_suspend_enable(tp, false); | |
7016 | r8153_mac_clk_speed_down(tp, false); | |
7017 | r8153_u1u2en(tp, true); | |
7018 | usb_enable_lpm(tp->udev); | |
7019 | ||
7020 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); | |
7021 | ocp_data |= LANWAKE_CLR_EN; | |
7022 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); | |
7023 | ||
7024 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG); | |
7025 | ocp_data &= ~LANWAKE_PIN; | |
7026 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); | |
7027 | ||
7028 | /* rx aggregation */ | |
7029 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
7030 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
9c68011b | 7031 | if (tp->dell_tb_rx_agg_bug) |
195aae32 HW |
7032 | ocp_data |= RX_AGG_DISABLE; |
7033 | ||
7034 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
7035 | ||
7036 | rtl_tally_reset(tp); | |
7037 | ||
7038 | switch (tp->udev->speed) { | |
7039 | case USB_SPEED_SUPER: | |
7040 | case USB_SPEED_SUPER_PLUS: | |
7041 | tp->coalesce = COALESCE_SUPER; | |
7042 | break; | |
7043 | case USB_SPEED_HIGH: | |
7044 | tp->coalesce = COALESCE_HIGH; | |
7045 | break; | |
7046 | default: | |
7047 | tp->coalesce = COALESCE_SLOW; | |
7048 | break; | |
7049 | } | |
7050 | } | |
7051 | ||
7052 | static void r8153b_init(struct r8152 *tp) | |
7053 | { | |
7054 | u32 ocp_data; | |
7055 | u16 data; | |
7056 | int i; | |
7057 | ||
7058 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
7059 | return; | |
7060 | ||
7061 | r8153b_u1u2en(tp, false); | |
7062 | ||
7063 | for (i = 0; i < 500; i++) { | |
7064 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
7065 | AUTOLOAD_DONE) | |
7066 | break; | |
7067 | ||
7068 | msleep(20); | |
7069 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
7070 | break; | |
7071 | } | |
7072 | ||
7073 | data = r8153_phy_status(tp, 0); | |
7074 | ||
7075 | data = r8152_mdio_read(tp, MII_BMCR); | |
7076 | if (data & BMCR_PDOWN) { | |
7077 | data &= ~BMCR_PDOWN; | |
7078 | r8152_mdio_write(tp, MII_BMCR, data); | |
7079 | } | |
7080 | ||
7081 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
7082 | ||
7083 | r8153_u2p3en(tp, false); | |
7084 | ||
7085 | /* MSC timer = 0xfff * 8ms = 32760 ms */ | |
7086 | ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); | |
7087 | ||
7088 | r8153b_power_cut_en(tp, false); | |
7089 | r8153b_ups_en(tp, false); | |
7090 | r8153_queue_wake(tp, false); | |
7091 | rtl_runtime_suspend_enable(tp, false); | |
7092 | ||
7093 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); | |
7094 | if (rtl8152_get_speed(tp) & LINK_STATUS) | |
7095 | ocp_data |= CUR_LINK_OK; | |
7096 | else | |
7097 | ocp_data &= ~CUR_LINK_OK; | |
7098 | ocp_data |= POLL_LINK_CHG; | |
7099 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); | |
7100 | ||
7101 | if (tp->udev->speed >= USB_SPEED_SUPER) | |
7102 | r8153b_u1u2en(tp, true); | |
7103 | ||
7104 | usb_enable_lpm(tp->udev); | |
7105 | ||
7106 | /* MAC clock speed down */ | |
7107 | r8153_mac_clk_speed_down(tp, true); | |
7108 | ||
7109 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); | |
7110 | ocp_data &= ~PLA_MCU_SPDWN_EN; | |
7111 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
7112 | ||
7113 | if (tp->version == RTL_VER_09) { | |
7114 | /* Disable Test IO for 32QFN */ | |
7115 | if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) { | |
7116 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
7117 | ocp_data |= TEST_IO_OFF; | |
7118 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
7119 | } | |
7120 | } | |
7121 | ||
7122 | set_bit(GREEN_ETHERNET, &tp->flags); | |
7123 | ||
7124 | /* rx aggregation */ | |
7125 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
7126 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
7127 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
7128 | ||
7129 | rtl_tally_reset(tp); | |
7130 | ||
7131 | tp->coalesce = 15000; /* 15 us */ | |
7132 | } | |
7133 | ||
7134 | static void r8153c_init(struct r8152 *tp) | |
7135 | { | |
7136 | u32 ocp_data; | |
7137 | u16 data; | |
7138 | int i; | |
7139 | ||
7140 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
7141 | return; | |
7142 | ||
7143 | r8153b_u1u2en(tp, false); | |
7144 | ||
7145 | /* Disable spi_en */ | |
7146 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
7147 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
7148 | ocp_data &= ~BIT(3); | |
7149 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); | |
7150 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0); | |
7151 | ocp_data |= BIT(1); | |
7152 | ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data); | |
7153 | ||
7154 | for (i = 0; i < 500; i++) { | |
7155 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
7156 | AUTOLOAD_DONE) | |
7157 | break; | |
7158 | ||
7159 | msleep(20); | |
7160 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
7161 | return; | |
7162 | } | |
7163 | ||
7164 | data = r8153_phy_status(tp, 0); | |
7165 | ||
7166 | data = r8152_mdio_read(tp, MII_BMCR); | |
7167 | if (data & BMCR_PDOWN) { | |
7168 | data &= ~BMCR_PDOWN; | |
7169 | r8152_mdio_write(tp, MII_BMCR, data); | |
7170 | } | |
7171 | ||
7172 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
7173 | ||
7174 | r8153_u2p3en(tp, false); | |
7175 | ||
7176 | /* MSC timer = 0xfff * 8ms = 32760 ms */ | |
7177 | ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); | |
7178 | ||
7179 | r8153b_power_cut_en(tp, false); | |
7180 | r8153c_ups_en(tp, false); | |
7181 | r8153_queue_wake(tp, false); | |
7182 | rtl_runtime_suspend_enable(tp, false); | |
7183 | ||
7184 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); | |
7185 | if (rtl8152_get_speed(tp) & LINK_STATUS) | |
7186 | ocp_data |= CUR_LINK_OK; | |
7187 | else | |
7188 | ocp_data &= ~CUR_LINK_OK; | |
7189 | ||
7190 | ocp_data |= POLL_LINK_CHG; | |
7191 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); | |
7192 | ||
7193 | r8153b_u1u2en(tp, true); | |
7194 | ||
7195 | usb_enable_lpm(tp->udev); | |
7196 | ||
7197 | /* MAC clock speed down */ | |
7198 | r8153_mac_clk_speed_down(tp, true); | |
7199 | ||
7200 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); | |
7201 | ocp_data &= ~BIT(7); | |
7202 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
7203 | ||
7204 | set_bit(GREEN_ETHERNET, &tp->flags); | |
7205 | ||
7206 | /* rx aggregation */ | |
7207 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
7208 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
7209 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
7210 | ||
7211 | rtl_tally_reset(tp); | |
7212 | ||
7213 | tp->coalesce = 15000; /* 15 us */ | |
7214 | } | |
7215 | ||
7216 | static void r8156_hw_phy_cfg(struct r8152 *tp) | |
7217 | { | |
7218 | u32 ocp_data; | |
7219 | u16 data; | |
7220 | ||
7221 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
7222 | if (ocp_data & PCUT_STATUS) { | |
7223 | ocp_data &= ~PCUT_STATUS; | |
7224 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
7225 | } | |
7226 | ||
7227 | data = r8153_phy_status(tp, 0); | |
7228 | switch (data) { | |
7229 | case PHY_STAT_EXT_INIT: | |
7230 | rtl8152_apply_firmware(tp, true); | |
7231 | ||
7232 | data = ocp_reg_read(tp, 0xa468); | |
7233 | data &= ~(BIT(3) | BIT(1)); | |
7234 | ocp_reg_write(tp, 0xa468, data); | |
7235 | break; | |
7236 | case PHY_STAT_LAN_ON: | |
7237 | case PHY_STAT_PWRDN: | |
7238 | default: | |
7239 | rtl8152_apply_firmware(tp, false); | |
7240 | break; | |
7241 | } | |
7242 | ||
7243 | /* disable ALDPS before updating the PHY parameters */ | |
7244 | r8153_aldps_en(tp, false); | |
7245 | ||
7246 | /* disable EEE before updating the PHY parameters */ | |
7247 | rtl_eee_enable(tp, false); | |
7248 | ||
7249 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
7250 | WARN_ON_ONCE(data != PHY_STAT_LAN_ON); | |
7251 | ||
7252 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
7253 | ocp_data |= PFM_PWM_SWITCH; | |
7254 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
7255 | ||
7256 | switch (tp->version) { | |
7257 | case RTL_VER_10: | |
7258 | data = ocp_reg_read(tp, 0xad40); | |
7259 | data &= ~0x3ff; | |
7260 | data |= BIT(7) | BIT(2); | |
7261 | ocp_reg_write(tp, 0xad40, data); | |
7262 | ||
7263 | data = ocp_reg_read(tp, 0xad4e); | |
7264 | data |= BIT(4); | |
7265 | ocp_reg_write(tp, 0xad4e, data); | |
7266 | data = ocp_reg_read(tp, 0xad16); | |
7267 | data &= ~0x3ff; | |
7268 | data |= 0x6; | |
7269 | ocp_reg_write(tp, 0xad16, data); | |
7270 | data = ocp_reg_read(tp, 0xad32); | |
7271 | data &= ~0x3f; | |
7272 | data |= 6; | |
7273 | ocp_reg_write(tp, 0xad32, data); | |
7274 | data = ocp_reg_read(tp, 0xac08); | |
7275 | data &= ~(BIT(12) | BIT(8)); | |
7276 | ocp_reg_write(tp, 0xac08, data); | |
7277 | data = ocp_reg_read(tp, 0xac8a); | |
7278 | data |= BIT(12) | BIT(13) | BIT(14); | |
7279 | data &= ~BIT(15); | |
7280 | ocp_reg_write(tp, 0xac8a, data); | |
7281 | data = ocp_reg_read(tp, 0xad18); | |
7282 | data |= BIT(10); | |
7283 | ocp_reg_write(tp, 0xad18, data); | |
7284 | data = ocp_reg_read(tp, 0xad1a); | |
7285 | data |= 0x3ff; | |
7286 | ocp_reg_write(tp, 0xad1a, data); | |
7287 | data = ocp_reg_read(tp, 0xad1c); | |
7288 | data |= 0x3ff; | |
7289 | ocp_reg_write(tp, 0xad1c, data); | |
7290 | ||
7291 | data = sram_read(tp, 0x80ea); | |
7292 | data &= ~0xff00; | |
7293 | data |= 0xc400; | |
7294 | sram_write(tp, 0x80ea, data); | |
7295 | data = sram_read(tp, 0x80eb); | |
7296 | data &= ~0x0700; | |
7297 | data |= 0x0300; | |
7298 | sram_write(tp, 0x80eb, data); | |
7299 | data = sram_read(tp, 0x80f8); | |
7300 | data &= ~0xff00; | |
7301 | data |= 0x1c00; | |
7302 | sram_write(tp, 0x80f8, data); | |
7303 | data = sram_read(tp, 0x80f1); | |
7304 | data &= ~0xff00; | |
7305 | data |= 0x3000; | |
7306 | sram_write(tp, 0x80f1, data); | |
7307 | ||
7308 | data = sram_read(tp, 0x80fe); | |
7309 | data &= ~0xff00; | |
7310 | data |= 0xa500; | |
7311 | sram_write(tp, 0x80fe, data); | |
7312 | data = sram_read(tp, 0x8102); | |
7313 | data &= ~0xff00; | |
7314 | data |= 0x5000; | |
7315 | sram_write(tp, 0x8102, data); | |
7316 | data = sram_read(tp, 0x8015); | |
7317 | data &= ~0xff00; | |
7318 | data |= 0x3300; | |
7319 | sram_write(tp, 0x8015, data); | |
7320 | data = sram_read(tp, 0x8100); | |
7321 | data &= ~0xff00; | |
7322 | data |= 0x7000; | |
7323 | sram_write(tp, 0x8100, data); | |
7324 | data = sram_read(tp, 0x8014); | |
7325 | data &= ~0xff00; | |
7326 | data |= 0xf000; | |
7327 | sram_write(tp, 0x8014, data); | |
7328 | data = sram_read(tp, 0x8016); | |
7329 | data &= ~0xff00; | |
7330 | data |= 0x6500; | |
7331 | sram_write(tp, 0x8016, data); | |
7332 | data = sram_read(tp, 0x80dc); | |
7333 | data &= ~0xff00; | |
7334 | data |= 0xed00; | |
7335 | sram_write(tp, 0x80dc, data); | |
7336 | data = sram_read(tp, 0x80df); | |
7337 | data |= BIT(8); | |
7338 | sram_write(tp, 0x80df, data); | |
7339 | data = sram_read(tp, 0x80e1); | |
7340 | data &= ~BIT(8); | |
7341 | sram_write(tp, 0x80e1, data); | |
7342 | ||
7343 | data = ocp_reg_read(tp, 0xbf06); | |
7344 | data &= ~0x003f; | |
7345 | data |= 0x0038; | |
7346 | ocp_reg_write(tp, 0xbf06, data); | |
7347 | ||
7348 | sram_write(tp, 0x819f, 0xddb6); | |
7349 | ||
7350 | ocp_reg_write(tp, 0xbc34, 0x5555); | |
7351 | data = ocp_reg_read(tp, 0xbf0a); | |
7352 | data &= ~0x0e00; | |
7353 | data |= 0x0a00; | |
7354 | ocp_reg_write(tp, 0xbf0a, data); | |
7355 | ||
7356 | data = ocp_reg_read(tp, 0xbd2c); | |
7357 | data &= ~BIT(13); | |
7358 | ocp_reg_write(tp, 0xbd2c, data); | |
7359 | break; | |
7360 | case RTL_VER_11: | |
7361 | data = ocp_reg_read(tp, 0xad16); | |
7362 | data |= 0x3ff; | |
7363 | ocp_reg_write(tp, 0xad16, data); | |
7364 | data = ocp_reg_read(tp, 0xad32); | |
7365 | data &= ~0x3f; | |
7366 | data |= 6; | |
7367 | ocp_reg_write(tp, 0xad32, data); | |
7368 | data = ocp_reg_read(tp, 0xac08); | |
7369 | data &= ~(BIT(12) | BIT(8)); | |
7370 | ocp_reg_write(tp, 0xac08, data); | |
7371 | data = ocp_reg_read(tp, 0xacc0); | |
7372 | data &= ~0x3; | |
7373 | data |= BIT(1); | |
7374 | ocp_reg_write(tp, 0xacc0, data); | |
7375 | data = ocp_reg_read(tp, 0xad40); | |
7376 | data &= ~0xe7; | |
7377 | data |= BIT(6) | BIT(2); | |
7378 | ocp_reg_write(tp, 0xad40, data); | |
7379 | data = ocp_reg_read(tp, 0xac14); | |
7380 | data &= ~BIT(7); | |
7381 | ocp_reg_write(tp, 0xac14, data); | |
7382 | data = ocp_reg_read(tp, 0xac80); | |
7383 | data &= ~(BIT(8) | BIT(9)); | |
7384 | ocp_reg_write(tp, 0xac80, data); | |
7385 | data = ocp_reg_read(tp, 0xac5e); | |
7386 | data &= ~0x7; | |
7387 | data |= BIT(1); | |
7388 | ocp_reg_write(tp, 0xac5e, data); | |
7389 | ocp_reg_write(tp, 0xad4c, 0x00a8); | |
7390 | ocp_reg_write(tp, 0xac5c, 0x01ff); | |
7391 | data = ocp_reg_read(tp, 0xac8a); | |
7392 | data &= ~0xf0; | |
7393 | data |= BIT(4) | BIT(5); | |
7394 | ocp_reg_write(tp, 0xac8a, data); | |
7395 | ocp_reg_write(tp, 0xb87c, 0x8157); | |
7396 | data = ocp_reg_read(tp, 0xb87e); | |
7397 | data &= ~0xff00; | |
7398 | data |= 0x0500; | |
7399 | ocp_reg_write(tp, 0xb87e, data); | |
7400 | ocp_reg_write(tp, 0xb87c, 0x8159); | |
7401 | data = ocp_reg_read(tp, 0xb87e); | |
7402 | data &= ~0xff00; | |
7403 | data |= 0x0700; | |
7404 | ocp_reg_write(tp, 0xb87e, data); | |
7405 | ||
7406 | /* AAGC */ | |
7407 | ocp_reg_write(tp, 0xb87c, 0x80a2); | |
7408 | ocp_reg_write(tp, 0xb87e, 0x0153); | |
7409 | ocp_reg_write(tp, 0xb87c, 0x809c); | |
7410 | ocp_reg_write(tp, 0xb87e, 0x0153); | |
7411 | ||
7412 | /* EEE parameter */ | |
7413 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056); | |
7414 | ||
7415 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG); | |
7416 | ocp_data |= EN_XG_LIP | EN_G_LIP; | |
7417 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); | |
7418 | ||
7419 | sram_write(tp, 0x8257, 0x020f); /* XG PLL */ | |
7420 | sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */ | |
7421 | ||
7422 | if (rtl_phy_patch_request(tp, true, true)) | |
7423 | return; | |
7424 | ||
7425 | /* Advance EEE */ | |
7426 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); | |
7427 | ocp_data |= EEE_SPDWN_EN; | |
7428 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); | |
7429 | ||
7430 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
7431 | data &= ~(EN_EEE_100 | EN_EEE_1000); | |
7432 | data |= EN_10M_CLKDIV; | |
7433 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
7434 | tp->ups_info._10m_ckdiv = true; | |
7435 | tp->ups_info.eee_plloff_100 = false; | |
7436 | tp->ups_info.eee_plloff_giga = false; | |
7437 | ||
7438 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
7439 | data &= ~EEE_CLKDIV_EN; | |
7440 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
7441 | tp->ups_info.eee_ckdiv = false; | |
7442 | ||
7443 | ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); | |
7444 | ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5)); | |
7445 | tp->ups_info._250m_ckdiv = false; | |
7446 | ||
7447 | rtl_phy_patch_request(tp, false, true); | |
7448 | ||
7449 | /* enable ADC Ibias Cal */ | |
7450 | data = ocp_reg_read(tp, 0xd068); | |
7451 | data |= BIT(13); | |
7452 | ocp_reg_write(tp, 0xd068, data); | |
7453 | ||
7454 | /* enable Thermal Sensor */ | |
7455 | data = sram_read(tp, 0x81a2); | |
7456 | data &= ~BIT(8); | |
7457 | sram_write(tp, 0x81a2, data); | |
7458 | data = ocp_reg_read(tp, 0xb54c); | |
7459 | data &= ~0xff00; | |
7460 | data |= 0xdb00; | |
7461 | ocp_reg_write(tp, 0xb54c, data); | |
7462 | ||
7463 | /* Nway 2.5G Lite */ | |
7464 | data = ocp_reg_read(tp, 0xa454); | |
7465 | data &= ~BIT(0); | |
7466 | ocp_reg_write(tp, 0xa454, data); | |
7467 | ||
7468 | /* CS DSP solution */ | |
7469 | data = ocp_reg_read(tp, OCP_10GBT_CTRL); | |
7470 | data |= RTL_ADV2_5G_F_R; | |
7471 | ocp_reg_write(tp, OCP_10GBT_CTRL, data); | |
7472 | data = ocp_reg_read(tp, 0xad4e); | |
7473 | data &= ~BIT(4); | |
7474 | ocp_reg_write(tp, 0xad4e, data); | |
7475 | data = ocp_reg_read(tp, 0xa86a); | |
7476 | data &= ~BIT(0); | |
7477 | ocp_reg_write(tp, 0xa86a, data); | |
7478 | ||
7479 | /* MDI SWAP */ | |
7480 | if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) && | |
7481 | (ocp_reg_read(tp, 0xd068) & BIT(1))) { | |
7482 | u16 swap_a, swap_b; | |
7483 | ||
7484 | data = ocp_reg_read(tp, 0xd068); | |
7485 | data &= ~0x1f; | |
7486 | data |= 0x1; /* p0 */ | |
7487 | ocp_reg_write(tp, 0xd068, data); | |
7488 | swap_a = ocp_reg_read(tp, 0xd06a); | |
7489 | data &= ~0x18; | |
7490 | data |= 0x18; /* p3 */ | |
7491 | ocp_reg_write(tp, 0xd068, data); | |
7492 | swap_b = ocp_reg_read(tp, 0xd06a); | |
7493 | data &= ~0x18; /* p0 */ | |
7494 | ocp_reg_write(tp, 0xd068, data); | |
7495 | ocp_reg_write(tp, 0xd06a, | |
7496 | (swap_a & ~0x7ff) | (swap_b & 0x7ff)); | |
7497 | data |= 0x18; /* p3 */ | |
7498 | ocp_reg_write(tp, 0xd068, data); | |
7499 | ocp_reg_write(tp, 0xd06a, | |
7500 | (swap_b & ~0x7ff) | (swap_a & 0x7ff)); | |
7501 | data &= ~0x18; | |
7502 | data |= 0x08; /* p1 */ | |
7503 | ocp_reg_write(tp, 0xd068, data); | |
7504 | swap_a = ocp_reg_read(tp, 0xd06a); | |
7505 | data &= ~0x18; | |
7506 | data |= 0x10; /* p2 */ | |
7507 | ocp_reg_write(tp, 0xd068, data); | |
7508 | swap_b = ocp_reg_read(tp, 0xd06a); | |
7509 | data &= ~0x18; | |
7510 | data |= 0x08; /* p1 */ | |
7511 | ocp_reg_write(tp, 0xd068, data); | |
7512 | ocp_reg_write(tp, 0xd06a, | |
7513 | (swap_a & ~0x7ff) | (swap_b & 0x7ff)); | |
7514 | data &= ~0x18; | |
7515 | data |= 0x10; /* p2 */ | |
7516 | ocp_reg_write(tp, 0xd068, data); | |
7517 | ocp_reg_write(tp, 0xd06a, | |
7518 | (swap_b & ~0x7ff) | (swap_a & 0x7ff)); | |
7519 | swap_a = ocp_reg_read(tp, 0xbd5a); | |
7520 | swap_b = ocp_reg_read(tp, 0xbd5c); | |
7521 | ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) | | |
7522 | ((swap_b & 0x1f) << 8) | | |
7523 | ((swap_b >> 8) & 0x1f)); | |
7524 | ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) | | |
7525 | ((swap_a & 0x1f) << 8) | | |
7526 | ((swap_a >> 8) & 0x1f)); | |
7527 | swap_a = ocp_reg_read(tp, 0xbc18); | |
7528 | swap_b = ocp_reg_read(tp, 0xbc1a); | |
7529 | ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) | | |
7530 | ((swap_b & 0x1f) << 8) | | |
7531 | ((swap_b >> 8) & 0x1f)); | |
7532 | ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) | | |
7533 | ((swap_a & 0x1f) << 8) | | |
7534 | ((swap_a >> 8) & 0x1f)); | |
7535 | } | |
7536 | break; | |
7537 | default: | |
7538 | break; | |
7539 | } | |
7540 | ||
7541 | rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); | |
7542 | ||
7543 | data = ocp_reg_read(tp, 0xa428); | |
7544 | data &= ~BIT(9); | |
7545 | ocp_reg_write(tp, 0xa428, data); | |
7546 | data = ocp_reg_read(tp, 0xa5ea); | |
7547 | data &= ~BIT(0); | |
7548 | ocp_reg_write(tp, 0xa5ea, data); | |
7549 | tp->ups_info.lite_mode = 0; | |
7550 | ||
7551 | if (tp->eee_en) | |
7552 | rtl_eee_enable(tp, true); | |
7553 | ||
7554 | r8153_aldps_en(tp, true); | |
7555 | r8152b_enable_fc(tp); | |
7556 | r8153_u2p3en(tp, true); | |
7557 | ||
7558 | set_bit(PHY_RESET, &tp->flags); | |
7559 | } | |
7560 | ||
7561 | static void r8156b_hw_phy_cfg(struct r8152 *tp) | |
7562 | { | |
7563 | u32 ocp_data; | |
7564 | u16 data; | |
7565 | ||
7566 | switch (tp->version) { | |
7567 | case RTL_VER_12: | |
7568 | ocp_reg_write(tp, 0xbf86, 0x9000); | |
7569 | data = ocp_reg_read(tp, 0xc402); | |
7570 | data |= BIT(10); | |
7571 | ocp_reg_write(tp, 0xc402, data); | |
7572 | data &= ~BIT(10); | |
7573 | ocp_reg_write(tp, 0xc402, data); | |
7574 | ocp_reg_write(tp, 0xbd86, 0x1010); | |
7575 | ocp_reg_write(tp, 0xbd88, 0x1010); | |
7576 | data = ocp_reg_read(tp, 0xbd4e); | |
7577 | data &= ~(BIT(10) | BIT(11)); | |
7578 | data |= BIT(11); | |
7579 | ocp_reg_write(tp, 0xbd4e, data); | |
7580 | data = ocp_reg_read(tp, 0xbf46); | |
7581 | data &= ~0xf00; | |
7582 | data |= 0x700; | |
7583 | ocp_reg_write(tp, 0xbf46, data); | |
7584 | break; | |
7585 | case RTL_VER_13: | |
7586 | case RTL_VER_15: | |
7587 | r8156b_wait_loading_flash(tp); | |
7588 | break; | |
7589 | default: | |
7590 | break; | |
7591 | } | |
7592 | ||
7593 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
7594 | if (ocp_data & PCUT_STATUS) { | |
7595 | ocp_data &= ~PCUT_STATUS; | |
7596 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
7597 | } | |
7598 | ||
7599 | data = r8153_phy_status(tp, 0); | |
7600 | switch (data) { | |
7601 | case PHY_STAT_EXT_INIT: | |
7602 | rtl8152_apply_firmware(tp, true); | |
7603 | ||
7604 | data = ocp_reg_read(tp, 0xa466); | |
7605 | data &= ~BIT(0); | |
7606 | ocp_reg_write(tp, 0xa466, data); | |
7607 | ||
7608 | data = ocp_reg_read(tp, 0xa468); | |
7609 | data &= ~(BIT(3) | BIT(1)); | |
7610 | ocp_reg_write(tp, 0xa468, data); | |
7611 | break; | |
7612 | case PHY_STAT_LAN_ON: | |
7613 | case PHY_STAT_PWRDN: | |
7614 | default: | |
7615 | rtl8152_apply_firmware(tp, false); | |
7616 | break; | |
7617 | } | |
7618 | ||
7619 | data = r8152_mdio_read(tp, MII_BMCR); | |
7620 | if (data & BMCR_PDOWN) { | |
7621 | data &= ~BMCR_PDOWN; | |
7622 | r8152_mdio_write(tp, MII_BMCR, data); | |
7623 | } | |
7624 | ||
7625 | /* disable ALDPS before updating the PHY parameters */ | |
7626 | r8153_aldps_en(tp, false); | |
7627 | ||
7628 | /* disable EEE before updating the PHY parameters */ | |
7629 | rtl_eee_enable(tp, false); | |
7630 | ||
7631 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
7632 | WARN_ON_ONCE(data != PHY_STAT_LAN_ON); | |
7633 | ||
7634 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
7635 | ocp_data |= PFM_PWM_SWITCH; | |
7636 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
7637 | ||
7638 | switch (tp->version) { | |
7639 | case RTL_VER_12: | |
7640 | data = ocp_reg_read(tp, 0xbc08); | |
7641 | data |= BIT(3) | BIT(2); | |
7642 | ocp_reg_write(tp, 0xbc08, data); | |
7643 | ||
7644 | data = sram_read(tp, 0x8fff); | |
7645 | data &= ~0xff00; | |
7646 | data |= 0x0400; | |
7647 | sram_write(tp, 0x8fff, data); | |
7648 | ||
7649 | data = ocp_reg_read(tp, 0xacda); | |
7650 | data |= 0xff00; | |
7651 | ocp_reg_write(tp, 0xacda, data); | |
7652 | data = ocp_reg_read(tp, 0xacde); | |
7653 | data |= 0xf000; | |
7654 | ocp_reg_write(tp, 0xacde, data); | |
7655 | ocp_reg_write(tp, 0xac8c, 0x0ffc); | |
7656 | ocp_reg_write(tp, 0xac46, 0xb7b4); | |
7657 | ocp_reg_write(tp, 0xac50, 0x0fbc); | |
7658 | ocp_reg_write(tp, 0xac3c, 0x9240); | |
7659 | ocp_reg_write(tp, 0xac4e, 0x0db4); | |
7660 | ocp_reg_write(tp, 0xacc6, 0x0707); | |
7661 | ocp_reg_write(tp, 0xacc8, 0xa0d3); | |
7662 | ocp_reg_write(tp, 0xad08, 0x0007); | |
7663 | ||
7664 | ocp_reg_write(tp, 0xb87c, 0x8560); | |
7665 | ocp_reg_write(tp, 0xb87e, 0x19cc); | |
7666 | ocp_reg_write(tp, 0xb87c, 0x8562); | |
7667 | ocp_reg_write(tp, 0xb87e, 0x19cc); | |
7668 | ocp_reg_write(tp, 0xb87c, 0x8564); | |
7669 | ocp_reg_write(tp, 0xb87e, 0x19cc); | |
7670 | ocp_reg_write(tp, 0xb87c, 0x8566); | |
7671 | ocp_reg_write(tp, 0xb87e, 0x147d); | |
7672 | ocp_reg_write(tp, 0xb87c, 0x8568); | |
7673 | ocp_reg_write(tp, 0xb87e, 0x147d); | |
7674 | ocp_reg_write(tp, 0xb87c, 0x856a); | |
7675 | ocp_reg_write(tp, 0xb87e, 0x147d); | |
7676 | ocp_reg_write(tp, 0xb87c, 0x8ffe); | |
7677 | ocp_reg_write(tp, 0xb87e, 0x0907); | |
7678 | ocp_reg_write(tp, 0xb87c, 0x80d6); | |
7679 | ocp_reg_write(tp, 0xb87e, 0x2801); | |
7680 | ocp_reg_write(tp, 0xb87c, 0x80f2); | |
7681 | ocp_reg_write(tp, 0xb87e, 0x2801); | |
7682 | ocp_reg_write(tp, 0xb87c, 0x80f4); | |
7683 | ocp_reg_write(tp, 0xb87e, 0x6077); | |
7684 | ocp_reg_write(tp, 0xb506, 0x01e7); | |
7685 | ||
7686 | ocp_reg_write(tp, 0xb87c, 0x8013); | |
7687 | ocp_reg_write(tp, 0xb87e, 0x0700); | |
7688 | ocp_reg_write(tp, 0xb87c, 0x8fb9); | |
7689 | ocp_reg_write(tp, 0xb87e, 0x2801); | |
7690 | ocp_reg_write(tp, 0xb87c, 0x8fba); | |
7691 | ocp_reg_write(tp, 0xb87e, 0x0100); | |
7692 | ocp_reg_write(tp, 0xb87c, 0x8fbc); | |
7693 | ocp_reg_write(tp, 0xb87e, 0x1900); | |
7694 | ocp_reg_write(tp, 0xb87c, 0x8fbe); | |
7695 | ocp_reg_write(tp, 0xb87e, 0xe100); | |
7696 | ocp_reg_write(tp, 0xb87c, 0x8fc0); | |
7697 | ocp_reg_write(tp, 0xb87e, 0x0800); | |
7698 | ocp_reg_write(tp, 0xb87c, 0x8fc2); | |
7699 | ocp_reg_write(tp, 0xb87e, 0xe500); | |
7700 | ocp_reg_write(tp, 0xb87c, 0x8fc4); | |
7701 | ocp_reg_write(tp, 0xb87e, 0x0f00); | |
7702 | ocp_reg_write(tp, 0xb87c, 0x8fc6); | |
7703 | ocp_reg_write(tp, 0xb87e, 0xf100); | |
7704 | ocp_reg_write(tp, 0xb87c, 0x8fc8); | |
7705 | ocp_reg_write(tp, 0xb87e, 0x0400); | |
7706 | ocp_reg_write(tp, 0xb87c, 0x8fca); | |
7707 | ocp_reg_write(tp, 0xb87e, 0xf300); | |
7708 | ocp_reg_write(tp, 0xb87c, 0x8fcc); | |
7709 | ocp_reg_write(tp, 0xb87e, 0xfd00); | |
7710 | ocp_reg_write(tp, 0xb87c, 0x8fce); | |
7711 | ocp_reg_write(tp, 0xb87e, 0xff00); | |
7712 | ocp_reg_write(tp, 0xb87c, 0x8fd0); | |
7713 | ocp_reg_write(tp, 0xb87e, 0xfb00); | |
7714 | ocp_reg_write(tp, 0xb87c, 0x8fd2); | |
7715 | ocp_reg_write(tp, 0xb87e, 0x0100); | |
7716 | ocp_reg_write(tp, 0xb87c, 0x8fd4); | |
7717 | ocp_reg_write(tp, 0xb87e, 0xf400); | |
7718 | ocp_reg_write(tp, 0xb87c, 0x8fd6); | |
7719 | ocp_reg_write(tp, 0xb87e, 0xff00); | |
7720 | ocp_reg_write(tp, 0xb87c, 0x8fd8); | |
7721 | ocp_reg_write(tp, 0xb87e, 0xf600); | |
7722 | ||
7723 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG); | |
7724 | ocp_data |= EN_XG_LIP | EN_G_LIP; | |
7725 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); | |
7726 | ocp_reg_write(tp, 0xb87c, 0x813d); | |
7727 | ocp_reg_write(tp, 0xb87e, 0x390e); | |
7728 | ocp_reg_write(tp, 0xb87c, 0x814f); | |
7729 | ocp_reg_write(tp, 0xb87e, 0x790e); | |
7730 | ocp_reg_write(tp, 0xb87c, 0x80b0); | |
7731 | ocp_reg_write(tp, 0xb87e, 0x0f31); | |
7732 | data = ocp_reg_read(tp, 0xbf4c); | |
7733 | data |= BIT(1); | |
7734 | ocp_reg_write(tp, 0xbf4c, data); | |
7735 | data = ocp_reg_read(tp, 0xbcca); | |
7736 | data |= BIT(9) | BIT(8); | |
7737 | ocp_reg_write(tp, 0xbcca, data); | |
7738 | ocp_reg_write(tp, 0xb87c, 0x8141); | |
7739 | ocp_reg_write(tp, 0xb87e, 0x320e); | |
7740 | ocp_reg_write(tp, 0xb87c, 0x8153); | |
7741 | ocp_reg_write(tp, 0xb87e, 0x720e); | |
7742 | ocp_reg_write(tp, 0xb87c, 0x8529); | |
7743 | ocp_reg_write(tp, 0xb87e, 0x050e); | |
7744 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
7745 | data &= ~CTAP_SHORT_EN; | |
7746 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
7747 | ||
7748 | sram_write(tp, 0x816c, 0xc4a0); | |
7749 | sram_write(tp, 0x8170, 0xc4a0); | |
7750 | sram_write(tp, 0x8174, 0x04a0); | |
7751 | sram_write(tp, 0x8178, 0x04a0); | |
7752 | sram_write(tp, 0x817c, 0x0719); | |
7753 | sram_write(tp, 0x8ff4, 0x0400); | |
7754 | sram_write(tp, 0x8ff1, 0x0404); | |
7755 | ||
7756 | ocp_reg_write(tp, 0xbf4a, 0x001b); | |
7757 | ocp_reg_write(tp, 0xb87c, 0x8033); | |
7758 | ocp_reg_write(tp, 0xb87e, 0x7c13); | |
7759 | ocp_reg_write(tp, 0xb87c, 0x8037); | |
7760 | ocp_reg_write(tp, 0xb87e, 0x7c13); | |
7761 | ocp_reg_write(tp, 0xb87c, 0x803b); | |
7762 | ocp_reg_write(tp, 0xb87e, 0xfc32); | |
7763 | ocp_reg_write(tp, 0xb87c, 0x803f); | |
7764 | ocp_reg_write(tp, 0xb87e, 0x7c13); | |
7765 | ocp_reg_write(tp, 0xb87c, 0x8043); | |
7766 | ocp_reg_write(tp, 0xb87e, 0x7c13); | |
7767 | ocp_reg_write(tp, 0xb87c, 0x8047); | |
7768 | ocp_reg_write(tp, 0xb87e, 0x7c13); | |
7769 | ||
7770 | ocp_reg_write(tp, 0xb87c, 0x8145); | |
7771 | ocp_reg_write(tp, 0xb87e, 0x370e); | |
7772 | ocp_reg_write(tp, 0xb87c, 0x8157); | |
7773 | ocp_reg_write(tp, 0xb87e, 0x770e); | |
7774 | ocp_reg_write(tp, 0xb87c, 0x8169); | |
7775 | ocp_reg_write(tp, 0xb87e, 0x0d0a); | |
7776 | ocp_reg_write(tp, 0xb87c, 0x817b); | |
7777 | ocp_reg_write(tp, 0xb87e, 0x1d0a); | |
7778 | ||
7779 | data = sram_read(tp, 0x8217); | |
7780 | data &= ~0xff00; | |
7781 | data |= 0x5000; | |
7782 | sram_write(tp, 0x8217, data); | |
7783 | data = sram_read(tp, 0x821a); | |
7784 | data &= ~0xff00; | |
7785 | data |= 0x5000; | |
7786 | sram_write(tp, 0x821a, data); | |
7787 | sram_write(tp, 0x80da, 0x0403); | |
7788 | data = sram_read(tp, 0x80dc); | |
7789 | data &= ~0xff00; | |
7790 | data |= 0x1000; | |
7791 | sram_write(tp, 0x80dc, data); | |
7792 | sram_write(tp, 0x80b3, 0x0384); | |
7793 | sram_write(tp, 0x80b7, 0x2007); | |
7794 | data = sram_read(tp, 0x80ba); | |
7795 | data &= ~0xff00; | |
7796 | data |= 0x6c00; | |
7797 | sram_write(tp, 0x80ba, data); | |
7798 | sram_write(tp, 0x80b5, 0xf009); | |
7799 | data = sram_read(tp, 0x80bd); | |
7800 | data &= ~0xff00; | |
7801 | data |= 0x9f00; | |
7802 | sram_write(tp, 0x80bd, data); | |
7803 | sram_write(tp, 0x80c7, 0xf083); | |
7804 | sram_write(tp, 0x80dd, 0x03f0); | |
7805 | data = sram_read(tp, 0x80df); | |
7806 | data &= ~0xff00; | |
7807 | data |= 0x1000; | |
7808 | sram_write(tp, 0x80df, data); | |
7809 | sram_write(tp, 0x80cb, 0x2007); | |
7810 | data = sram_read(tp, 0x80ce); | |
7811 | data &= ~0xff00; | |
7812 | data |= 0x6c00; | |
7813 | sram_write(tp, 0x80ce, data); | |
7814 | sram_write(tp, 0x80c9, 0x8009); | |
7815 | data = sram_read(tp, 0x80d1); | |
7816 | data &= ~0xff00; | |
7817 | data |= 0x8000; | |
7818 | sram_write(tp, 0x80d1, data); | |
7819 | sram_write(tp, 0x80a3, 0x200a); | |
7820 | sram_write(tp, 0x80a5, 0xf0ad); | |
7821 | sram_write(tp, 0x809f, 0x6073); | |
7822 | sram_write(tp, 0x80a1, 0x000b); | |
7823 | data = sram_read(tp, 0x80a9); | |
7824 | data &= ~0xff00; | |
7825 | data |= 0xc000; | |
7826 | sram_write(tp, 0x80a9, data); | |
7827 | ||
7828 | if (rtl_phy_patch_request(tp, true, true)) | |
7829 | return; | |
7830 | ||
7831 | data = ocp_reg_read(tp, 0xb896); | |
7832 | data &= ~BIT(0); | |
7833 | ocp_reg_write(tp, 0xb896, data); | |
7834 | data = ocp_reg_read(tp, 0xb892); | |
7835 | data &= ~0xff00; | |
7836 | ocp_reg_write(tp, 0xb892, data); | |
7837 | ocp_reg_write(tp, 0xb88e, 0xc23e); | |
7838 | ocp_reg_write(tp, 0xb890, 0x0000); | |
7839 | ocp_reg_write(tp, 0xb88e, 0xc240); | |
7840 | ocp_reg_write(tp, 0xb890, 0x0103); | |
7841 | ocp_reg_write(tp, 0xb88e, 0xc242); | |
7842 | ocp_reg_write(tp, 0xb890, 0x0507); | |
7843 | ocp_reg_write(tp, 0xb88e, 0xc244); | |
7844 | ocp_reg_write(tp, 0xb890, 0x090b); | |
7845 | ocp_reg_write(tp, 0xb88e, 0xc246); | |
7846 | ocp_reg_write(tp, 0xb890, 0x0c0e); | |
7847 | ocp_reg_write(tp, 0xb88e, 0xc248); | |
7848 | ocp_reg_write(tp, 0xb890, 0x1012); | |
7849 | ocp_reg_write(tp, 0xb88e, 0xc24a); | |
7850 | ocp_reg_write(tp, 0xb890, 0x1416); | |
7851 | data = ocp_reg_read(tp, 0xb896); | |
7852 | data |= BIT(0); | |
7853 | ocp_reg_write(tp, 0xb896, data); | |
7854 | ||
7855 | rtl_phy_patch_request(tp, false, true); | |
7856 | ||
7857 | data = ocp_reg_read(tp, 0xa86a); | |
7858 | data |= BIT(0); | |
7859 | ocp_reg_write(tp, 0xa86a, data); | |
7860 | data = ocp_reg_read(tp, 0xa6f0); | |
7861 | data |= BIT(0); | |
7862 | ocp_reg_write(tp, 0xa6f0, data); | |
7863 | ||
7864 | ocp_reg_write(tp, 0xbfa0, 0xd70d); | |
7865 | ocp_reg_write(tp, 0xbfa2, 0x4100); | |
7866 | ocp_reg_write(tp, 0xbfa4, 0xe868); | |
7867 | ocp_reg_write(tp, 0xbfa6, 0xdc59); | |
7868 | ocp_reg_write(tp, 0xb54c, 0x3c18); | |
7869 | data = ocp_reg_read(tp, 0xbfa4); | |
7870 | data &= ~BIT(5); | |
7871 | ocp_reg_write(tp, 0xbfa4, data); | |
7872 | data = sram_read(tp, 0x817d); | |
7873 | data |= BIT(12); | |
7874 | sram_write(tp, 0x817d, data); | |
7875 | break; | |
7876 | case RTL_VER_13: | |
7877 | /* 2.5G INRX */ | |
7878 | data = ocp_reg_read(tp, 0xac46); | |
7879 | data &= ~0x00f0; | |
7880 | data |= 0x0090; | |
7881 | ocp_reg_write(tp, 0xac46, data); | |
7882 | data = ocp_reg_read(tp, 0xad30); | |
7883 | data &= ~0x0003; | |
7884 | data |= 0x0001; | |
7885 | ocp_reg_write(tp, 0xad30, data); | |
7886 | fallthrough; | |
7887 | case RTL_VER_15: | |
7888 | /* EEE parameter */ | |
7889 | ocp_reg_write(tp, 0xb87c, 0x80f5); | |
7890 | ocp_reg_write(tp, 0xb87e, 0x760e); | |
7891 | ocp_reg_write(tp, 0xb87c, 0x8107); | |
7892 | ocp_reg_write(tp, 0xb87e, 0x360e); | |
7893 | ocp_reg_write(tp, 0xb87c, 0x8551); | |
7894 | data = ocp_reg_read(tp, 0xb87e); | |
7895 | data &= ~0xff00; | |
7896 | data |= 0x0800; | |
7897 | ocp_reg_write(tp, 0xb87e, data); | |
7898 | ||
7899 | /* ADC_PGA parameter */ | |
7900 | data = ocp_reg_read(tp, 0xbf00); | |
7901 | data &= ~0xe000; | |
7902 | data |= 0xa000; | |
7903 | ocp_reg_write(tp, 0xbf00, data); | |
7904 | data = ocp_reg_read(tp, 0xbf46); | |
7905 | data &= ~0x0f00; | |
7906 | data |= 0x0300; | |
7907 | ocp_reg_write(tp, 0xbf46, data); | |
7908 | ||
7909 | /* Green Table-PGA, 1G full viterbi */ | |
7910 | sram_write(tp, 0x8044, 0x2417); | |
7911 | sram_write(tp, 0x804a, 0x2417); | |
7912 | sram_write(tp, 0x8050, 0x2417); | |
7913 | sram_write(tp, 0x8056, 0x2417); | |
7914 | sram_write(tp, 0x805c, 0x2417); | |
7915 | sram_write(tp, 0x8062, 0x2417); | |
7916 | sram_write(tp, 0x8068, 0x2417); | |
7917 | sram_write(tp, 0x806e, 0x2417); | |
7918 | sram_write(tp, 0x8074, 0x2417); | |
7919 | sram_write(tp, 0x807a, 0x2417); | |
7920 | ||
7921 | /* XG PLL */ | |
7922 | data = ocp_reg_read(tp, 0xbf84); | |
7923 | data &= ~0xe000; | |
7924 | data |= 0xa000; | |
7925 | ocp_reg_write(tp, 0xbf84, data); | |
7926 | break; | |
7927 | default: | |
7928 | break; | |
7929 | } | |
7930 | ||
7931 | if (rtl_phy_patch_request(tp, true, true)) | |
7932 | return; | |
7933 | ||
7934 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); | |
7935 | ocp_data |= EEE_SPDWN_EN; | |
7936 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); | |
7937 | ||
7938 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
7939 | data &= ~(EN_EEE_100 | EN_EEE_1000); | |
7940 | data |= EN_10M_CLKDIV; | |
7941 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
7942 | tp->ups_info._10m_ckdiv = true; | |
7943 | tp->ups_info.eee_plloff_100 = false; | |
7944 | tp->ups_info.eee_plloff_giga = false; | |
7945 | ||
7946 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
7947 | data &= ~EEE_CLKDIV_EN; | |
7948 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
7949 | tp->ups_info.eee_ckdiv = false; | |
7950 | ||
7951 | rtl_phy_patch_request(tp, false, true); | |
7952 | ||
7953 | rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); | |
7954 | ||
7955 | data = ocp_reg_read(tp, 0xa428); | |
7956 | data &= ~BIT(9); | |
7957 | ocp_reg_write(tp, 0xa428, data); | |
7958 | data = ocp_reg_read(tp, 0xa5ea); | |
7959 | data &= ~BIT(0); | |
7960 | ocp_reg_write(tp, 0xa5ea, data); | |
7961 | tp->ups_info.lite_mode = 0; | |
7962 | ||
7963 | if (tp->eee_en) | |
7964 | rtl_eee_enable(tp, true); | |
7965 | ||
7966 | r8153_aldps_en(tp, true); | |
7967 | r8152b_enable_fc(tp); | |
7968 | r8153_u2p3en(tp, true); | |
7969 | ||
7970 | set_bit(PHY_RESET, &tp->flags); | |
7971 | } | |
7972 | ||
7973 | static void r8156_init(struct r8152 *tp) | |
43779f8d | 7974 | { |
7975 | u32 ocp_data; | |
2dd436da | 7976 | u16 data; |
43779f8d | 7977 | int i; |
7978 | ||
6871438c | 7979 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
7980 | return; | |
7981 | ||
195aae32 HW |
7982 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); |
7983 | ocp_data &= ~EN_ALL_SPEED; | |
7984 | ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); | |
7985 | ||
7986 | ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); | |
7987 | ||
7988 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); | |
7989 | ocp_data |= BYPASS_MAC_RESET; | |
7990 | ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); | |
7991 | ||
7992 | r8153b_u1u2en(tp, false); | |
43779f8d | 7993 | |
7994 | for (i = 0; i < 500; i++) { | |
7995 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
7996 | AUTOLOAD_DONE) | |
7997 | break; | |
d64c7a08 | 7998 | |
43779f8d | 7999 | msleep(20); |
d64c7a08 | 8000 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
195aae32 | 8001 | return; |
43779f8d | 8002 | } |
8003 | ||
c564b871 | 8004 | data = r8153_phy_status(tp, 0); |
195aae32 HW |
8005 | if (data == PHY_STAT_EXT_INIT) { |
8006 | data = ocp_reg_read(tp, 0xa468); | |
8007 | data &= ~(BIT(3) | BIT(1)); | |
8008 | ocp_reg_write(tp, 0xa468, data); | |
8009 | } | |
2dd436da | 8010 | |
8011 | data = r8152_mdio_read(tp, MII_BMCR); | |
8012 | if (data & BMCR_PDOWN) { | |
8013 | data &= ~BMCR_PDOWN; | |
8014 | r8152_mdio_write(tp, MII_BMCR, data); | |
8015 | } | |
8016 | ||
c564b871 | 8017 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); |
195aae32 | 8018 | WARN_ON_ONCE(data != PHY_STAT_LAN_ON); |
2dd436da | 8019 | |
b9702723 | 8020 | r8153_u2p3en(tp, false); |
43779f8d | 8021 | |
195aae32 HW |
8022 | /* MSC timer = 0xfff * 8ms = 32760 ms */ |
8023 | ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); | |
65bab84c | 8024 | |
195aae32 HW |
8025 | /* U1/U2/L1 idle timer. 500 us */ |
8026 | ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); | |
a3914272 | 8027 | |
195aae32 HW |
8028 | r8153b_power_cut_en(tp, false); |
8029 | r8156_ups_en(tp, false); | |
8030 | r8153_queue_wake(tp, false); | |
8031 | rtl_runtime_suspend_enable(tp, false); | |
a3914272 | 8032 | |
195aae32 HW |
8033 | if (tp->udev->speed >= USB_SPEED_SUPER) |
8034 | r8153b_u1u2en(tp, true); | |
65bab84c | 8035 | |
195aae32 | 8036 | usb_enable_lpm(tp->udev); |
65bab84c | 8037 | |
195aae32 | 8038 | r8156_mac_clk_spd(tp, true); |
43779f8d | 8039 | |
195aae32 HW |
8040 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); |
8041 | ocp_data &= ~PLA_MCU_SPDWN_EN; | |
8042 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
43779f8d | 8043 | |
195aae32 HW |
8044 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); |
8045 | if (rtl8152_get_speed(tp) & LINK_STATUS) | |
8046 | ocp_data |= CUR_LINK_OK; | |
34203e25 | 8047 | else |
195aae32 HW |
8048 | ocp_data &= ~CUR_LINK_OK; |
8049 | ocp_data |= POLL_LINK_CHG; | |
8050 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); | |
19813162 | 8051 | |
195aae32 | 8052 | set_bit(GREEN_ETHERNET, &tp->flags); |
19813162 | 8053 | |
e31f6367 | 8054 | /* rx aggregation */ |
8055 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
8056 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
8057 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
43779f8d | 8058 | |
195aae32 HW |
8059 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG); |
8060 | ocp_data |= ACT_ODMA; | |
8061 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); | |
8062 | ||
45bf944e | 8063 | r8156_mdio_force_mode(tp); |
4f1d4d54 | 8064 | rtl_tally_reset(tp); |
49d10347 | 8065 | |
195aae32 | 8066 | tp->coalesce = 15000; /* 15 us */ |
43779f8d | 8067 | } |
8068 | ||
195aae32 | 8069 | static void r8156b_init(struct r8152 *tp) |
65b82d69 | 8070 | { |
8071 | u32 ocp_data; | |
8072 | u16 data; | |
8073 | int i; | |
8074 | ||
8075 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
8076 | return; | |
8077 | ||
195aae32 HW |
8078 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); |
8079 | ocp_data &= ~EN_ALL_SPEED; | |
8080 | ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); | |
8081 | ||
8082 | ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); | |
8083 | ||
8084 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); | |
8085 | ocp_data |= BYPASS_MAC_RESET; | |
8086 | ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); | |
8087 | ||
8088 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
8089 | ocp_data |= RX_DETECT8; | |
8090 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
8091 | ||
65b82d69 | 8092 | r8153b_u1u2en(tp, false); |
8093 | ||
195aae32 HW |
8094 | switch (tp->version) { |
8095 | case RTL_VER_13: | |
8096 | case RTL_VER_15: | |
8097 | r8156b_wait_loading_flash(tp); | |
8098 | break; | |
8099 | default: | |
8100 | break; | |
8101 | } | |
8102 | ||
65b82d69 | 8103 | for (i = 0; i < 500; i++) { |
8104 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
8105 | AUTOLOAD_DONE) | |
8106 | break; | |
d64c7a08 | 8107 | |
65b82d69 | 8108 | msleep(20); |
d64c7a08 | 8109 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
195aae32 | 8110 | return; |
65b82d69 | 8111 | } |
8112 | ||
8113 | data = r8153_phy_status(tp, 0); | |
195aae32 HW |
8114 | if (data == PHY_STAT_EXT_INIT) { |
8115 | data = ocp_reg_read(tp, 0xa468); | |
8116 | data &= ~(BIT(3) | BIT(1)); | |
8117 | ocp_reg_write(tp, 0xa468, data); | |
8118 | ||
8119 | data = ocp_reg_read(tp, 0xa466); | |
8120 | data &= ~BIT(0); | |
8121 | ocp_reg_write(tp, 0xa466, data); | |
8122 | } | |
65b82d69 | 8123 | |
8124 | data = r8152_mdio_read(tp, MII_BMCR); | |
8125 | if (data & BMCR_PDOWN) { | |
8126 | data &= ~BMCR_PDOWN; | |
8127 | r8152_mdio_write(tp, MII_BMCR, data); | |
8128 | } | |
8129 | ||
8130 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
8131 | ||
8132 | r8153_u2p3en(tp, false); | |
8133 | ||
8134 | /* MSC timer = 0xfff * 8ms = 32760 ms */ | |
8135 | ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); | |
8136 | ||
195aae32 HW |
8137 | /* U1/U2/L1 idle timer. 500 us */ |
8138 | ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); | |
8139 | ||
65b82d69 | 8140 | r8153b_power_cut_en(tp, false); |
195aae32 | 8141 | r8156_ups_en(tp, false); |
13e04fbf | 8142 | r8153_queue_wake(tp, false); |
65b82d69 | 8143 | rtl_runtime_suspend_enable(tp, false); |
a3914272 | 8144 | |
7a0ae61a | 8145 | if (tp->udev->speed >= USB_SPEED_SUPER) |
a0246daf | 8146 | r8153b_u1u2en(tp, true); |
7a0ae61a | 8147 | |
65b82d69 | 8148 | usb_enable_lpm(tp->udev); |
8149 | ||
195aae32 HW |
8150 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR); |
8151 | ocp_data &= ~SLOT_EN; | |
8152 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
8153 | ||
8154 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
8155 | ocp_data |= FLOW_CTRL_EN; | |
8156 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
8157 | ||
8158 | /* enable fc timer and set timer to 600 ms. */ | |
8159 | ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, | |
8160 | CTRL_TIMER_EN | (600 / 8)); | |
8161 | ||
8162 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); | |
8163 | if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN)) | |
8164 | ocp_data |= FLOW_CTRL_PATCH_2; | |
8165 | ocp_data &= ~AUTO_SPEEDUP; | |
8166 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); | |
8167 | ||
8168 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); | |
8169 | ocp_data |= FC_PATCH_TASK; | |
8170 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
8171 | ||
8172 | r8156_mac_clk_spd(tp, true); | |
65b82d69 | 8173 | |
08997b5e HW |
8174 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); |
8175 | ocp_data &= ~PLA_MCU_SPDWN_EN; | |
8176 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
8177 | ||
195aae32 HW |
8178 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); |
8179 | if (rtl8152_get_speed(tp) & LINK_STATUS) | |
8180 | ocp_data |= CUR_LINK_OK; | |
8181 | else | |
8182 | ocp_data &= ~CUR_LINK_OK; | |
8183 | ocp_data |= POLL_LINK_CHG; | |
8184 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); | |
d7f1b596 | 8185 | |
65b82d69 | 8186 | set_bit(GREEN_ETHERNET, &tp->flags); |
8187 | ||
8188 | /* rx aggregation */ | |
8189 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
8190 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
8191 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
8192 | ||
45bf944e | 8193 | r8156_mdio_force_mode(tp); |
65b82d69 | 8194 | rtl_tally_reset(tp); |
8195 | ||
8196 | tp->coalesce = 15000; /* 15 us */ | |
8197 | } | |
8198 | ||
1a44fb38 HW |
8199 | static bool rtl_check_vendor_ok(struct usb_interface *intf) |
8200 | { | |
8201 | struct usb_host_interface *alt = intf->cur_altsetting; | |
8202 | struct usb_endpoint_descriptor *in, *out, *intr; | |
8203 | ||
8204 | if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) { | |
8205 | dev_err(&intf->dev, "Expected endpoints are not found\n"); | |
8206 | return false; | |
8207 | } | |
8208 | ||
8209 | /* Check Rx endpoint address */ | |
8210 | if (usb_endpoint_num(in) != 1) { | |
8211 | dev_err(&intf->dev, "Invalid Rx endpoint address\n"); | |
8212 | return false; | |
8213 | } | |
8214 | ||
8215 | /* Check Tx endpoint address */ | |
8216 | if (usb_endpoint_num(out) != 2) { | |
8217 | dev_err(&intf->dev, "Invalid Tx endpoint address\n"); | |
8218 | return false; | |
8219 | } | |
8220 | ||
8221 | /* Check interrupt endpoint address */ | |
8222 | if (usb_endpoint_num(intr) != 3) { | |
8223 | dev_err(&intf->dev, "Invalid interrupt endpoint address\n"); | |
8224 | return false; | |
8225 | } | |
8226 | ||
8227 | return true; | |
8228 | } | |
8229 | ||
c2198943 HW |
8230 | static bool rtl_vendor_mode(struct usb_interface *intf) |
8231 | { | |
8232 | struct usb_host_interface *alt = intf->cur_altsetting; | |
8233 | struct usb_device *udev; | |
8234 | struct usb_host_config *c; | |
8235 | int i, num_configs; | |
8236 | ||
8237 | if (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC) | |
1a44fb38 | 8238 | return rtl_check_vendor_ok(intf); |
c2198943 HW |
8239 | |
8240 | /* The vendor mode is not always config #1, so to find it out. */ | |
8241 | udev = interface_to_usbdev(intf); | |
8242 | c = udev->config; | |
8243 | num_configs = udev->descriptor.bNumConfigurations; | |
1a44fb38 HW |
8244 | if (num_configs < 2) |
8245 | return false; | |
8246 | ||
c2198943 HW |
8247 | for (i = 0; i < num_configs; (i++, c++)) { |
8248 | struct usb_interface_descriptor *desc = NULL; | |
8249 | ||
8250 | if (c->desc.bNumInterfaces > 0) | |
8251 | desc = &c->intf_cache[0]->altsetting->desc; | |
8252 | else | |
8253 | continue; | |
8254 | ||
8255 | if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) { | |
8256 | usb_driver_set_configuration(udev, c->desc.bConfigurationValue); | |
8257 | break; | |
8258 | } | |
8259 | } | |
8260 | ||
1a44fb38 HW |
8261 | if (i == num_configs) |
8262 | dev_err(&intf->dev, "Unexpected Device\n"); | |
c2198943 HW |
8263 | |
8264 | return false; | |
8265 | } | |
8266 | ||
e501139a | 8267 | static int rtl8152_pre_reset(struct usb_interface *intf) |
8268 | { | |
8269 | struct r8152 *tp = usb_get_intfdata(intf); | |
8270 | struct net_device *netdev; | |
8271 | ||
8272 | if (!tp) | |
8273 | return 0; | |
8274 | ||
8275 | netdev = tp->netdev; | |
8276 | if (!netif_running(netdev)) | |
8277 | return 0; | |
8278 | ||
de9bf29d | 8279 | netif_stop_queue(netdev); |
d2187f8e | 8280 | tasklet_disable(&tp->tx_tl); |
e501139a | 8281 | clear_bit(WORK_ENABLE, &tp->flags); |
8282 | usb_kill_urb(tp->intr_urb); | |
8283 | cancel_delayed_work_sync(&tp->schedule); | |
5b1d9c17 | 8284 | napi_disable(&tp->napi); |
e501139a | 8285 | if (netif_carrier_ok(netdev)) { |
e501139a | 8286 | mutex_lock(&tp->control); |
8287 | tp->rtl_ops.disable(tp); | |
8288 | mutex_unlock(&tp->control); | |
8289 | } | |
8290 | ||
8291 | return 0; | |
8292 | } | |
8293 | ||
8294 | static int rtl8152_post_reset(struct usb_interface *intf) | |
8295 | { | |
8296 | struct r8152 *tp = usb_get_intfdata(intf); | |
8297 | struct net_device *netdev; | |
25766271 | 8298 | struct sockaddr sa; |
e501139a | 8299 | |
8300 | if (!tp) | |
8301 | return 0; | |
8302 | ||
f62c4f38 | 8303 | /* reset the MAC address in case of policy change */ |
25766271 ML |
8304 | if (determine_ethernet_addr(tp, &sa) >= 0) { |
8305 | rtnl_lock(); | |
8306 | dev_set_mac_address (tp->netdev, &sa, NULL); | |
8307 | rtnl_unlock(); | |
8308 | } | |
8309 | ||
e501139a | 8310 | netdev = tp->netdev; |
8311 | if (!netif_running(netdev)) | |
8312 | return 0; | |
8313 | ||
8314 | set_bit(WORK_ENABLE, &tp->flags); | |
8315 | if (netif_carrier_ok(netdev)) { | |
8316 | mutex_lock(&tp->control); | |
8317 | tp->rtl_ops.enable(tp); | |
2c561b2b | 8318 | rtl_start_rx(tp); |
aece4770 | 8319 | _rtl8152_set_rx_mode(netdev); |
e501139a | 8320 | mutex_unlock(&tp->control); |
e501139a | 8321 | } |
8322 | ||
8323 | napi_enable(&tp->napi); | |
d2187f8e | 8324 | tasklet_enable(&tp->tx_tl); |
de9bf29d | 8325 | netif_wake_queue(netdev); |
2c561b2b | 8326 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
e501139a | 8327 | |
7489bdad | 8328 | if (!list_empty(&tp->rx_done)) |
8329 | napi_schedule(&tp->napi); | |
e501139a | 8330 | |
8331 | return 0; | |
43779f8d | 8332 | } |
8333 | ||
2dd49e0f | 8334 | static bool delay_autosuspend(struct r8152 *tp) |
8335 | { | |
8336 | bool sw_linking = !!netif_carrier_ok(tp->netdev); | |
8337 | bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); | |
8338 | ||
8339 | /* This means a linking change occurs and the driver doesn't detect it, | |
8340 | * yet. If the driver has disabled tx/rx and hw is linking on, the | |
8341 | * device wouldn't wake up by receiving any packet. | |
8342 | */ | |
8343 | if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) | |
8344 | return true; | |
8345 | ||
8346 | /* If the linking down is occurred by nway, the device may miss the | |
8347 | * linking change event. And it wouldn't wake when linking on. | |
8348 | */ | |
8349 | if (!sw_linking && tp->rtl_ops.in_nway(tp)) | |
8350 | return true; | |
6a0b76c0 | 8351 | else if (!skb_queue_empty(&tp->tx_queue)) |
8352 | return true; | |
2dd49e0f | 8353 | else |
8354 | return false; | |
8355 | } | |
8356 | ||
21cbd0ec | 8357 | static int rtl8152_runtime_resume(struct r8152 *tp) |
8358 | { | |
8359 | struct net_device *netdev = tp->netdev; | |
8360 | ||
8361 | if (netif_running(netdev) && netdev->flags & IFF_UP) { | |
8362 | struct napi_struct *napi = &tp->napi; | |
8363 | ||
8364 | tp->rtl_ops.autosuspend_en(tp, false); | |
8365 | napi_disable(napi); | |
8366 | set_bit(WORK_ENABLE, &tp->flags); | |
8367 | ||
8368 | if (netif_carrier_ok(netdev)) { | |
8369 | if (rtl8152_get_speed(tp) & LINK_STATUS) { | |
8370 | rtl_start_rx(tp); | |
8371 | } else { | |
8372 | netif_carrier_off(netdev); | |
8373 | tp->rtl_ops.disable(tp); | |
8374 | netif_info(tp, link, netdev, "linking down\n"); | |
8375 | } | |
8376 | } | |
8377 | ||
8378 | napi_enable(napi); | |
8379 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
8380 | smp_mb__after_atomic(); | |
8381 | ||
8382 | if (!list_empty(&tp->rx_done)) | |
8383 | napi_schedule(&tp->napi); | |
8384 | ||
8385 | usb_submit_urb(tp->intr_urb, GFP_NOIO); | |
8386 | } else { | |
8387 | if (netdev->flags & IFF_UP) | |
8388 | tp->rtl_ops.autosuspend_en(tp, false); | |
8389 | ||
8390 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
8391 | } | |
8392 | ||
8393 | return 0; | |
8394 | } | |
8395 | ||
8396 | static int rtl8152_system_resume(struct r8152 *tp) | |
8397 | { | |
8398 | struct net_device *netdev = tp->netdev; | |
8399 | ||
8400 | netif_device_attach(netdev); | |
8401 | ||
5b1d9c17 | 8402 | if (netif_running(netdev) && (netdev->flags & IFF_UP)) { |
21cbd0ec | 8403 | tp->rtl_ops.up(tp); |
8404 | netif_carrier_off(netdev); | |
8405 | set_bit(WORK_ENABLE, &tp->flags); | |
8406 | usb_submit_urb(tp->intr_urb, GFP_NOIO); | |
8407 | } | |
8408 | ||
8409 | return 0; | |
8410 | } | |
8411 | ||
a9c54ad2 | 8412 | static int rtl8152_runtime_suspend(struct r8152 *tp) |
ac718b69 | 8413 | { |
6cc69f2a | 8414 | struct net_device *netdev = tp->netdev; |
8415 | int ret = 0; | |
ac718b69 | 8416 | |
c79515e4 HW |
8417 | if (!tp->rtl_ops.autosuspend_en) |
8418 | return -EBUSY; | |
8419 | ||
26afec39 | 8420 | set_bit(SELECTIVE_SUSPEND, &tp->flags); |
8421 | smp_mb__after_atomic(); | |
8422 | ||
8fb28061 | 8423 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
75dc692e | 8424 | u32 rcr = 0; |
8425 | ||
75dc692e | 8426 | if (netif_carrier_ok(netdev)) { |
8427 | u32 ocp_data; | |
8428 | ||
8429 | rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
8430 | ocp_data = rcr & ~RCR_ACPT_ALL; | |
8431 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
8432 | rxdy_gated_en(tp, true); | |
8433 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, | |
8434 | PLA_OOB_CTRL); | |
8435 | if (!(ocp_data & RXFIFO_EMPTY)) { | |
8436 | rxdy_gated_en(tp, false); | |
8437 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); | |
26afec39 | 8438 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
8439 | smp_mb__after_atomic(); | |
75dc692e | 8440 | ret = -EBUSY; |
8441 | goto out1; | |
8442 | } | |
8443 | } | |
8444 | ||
8fb28061 | 8445 | clear_bit(WORK_ENABLE, &tp->flags); |
8446 | usb_kill_urb(tp->intr_urb); | |
75dc692e | 8447 | |
8fb28061 | 8448 | tp->rtl_ops.autosuspend_en(tp, true); |
75dc692e | 8449 | |
8450 | if (netif_carrier_ok(netdev)) { | |
ce594e98 | 8451 | struct napi_struct *napi = &tp->napi; |
8452 | ||
8453 | napi_disable(napi); | |
75dc692e | 8454 | rtl_stop_rx(tp); |
8455 | rxdy_gated_en(tp, false); | |
8456 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); | |
ce594e98 | 8457 | napi_enable(napi); |
75dc692e | 8458 | } |
bd882982 | 8459 | |
8460 | if (delay_autosuspend(tp)) { | |
8461 | rtl8152_runtime_resume(tp); | |
8462 | ret = -EBUSY; | |
8463 | } | |
6cc69f2a | 8464 | } |
ac718b69 | 8465 | |
8fb28061 | 8466 | out1: |
8467 | return ret; | |
8468 | } | |
8469 | ||
8470 | static int rtl8152_system_suspend(struct r8152 *tp) | |
8471 | { | |
8472 | struct net_device *netdev = tp->netdev; | |
8fb28061 | 8473 | |
8474 | netif_device_detach(netdev); | |
8475 | ||
e3bd1a81 | 8476 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
ce594e98 | 8477 | struct napi_struct *napi = &tp->napi; |
8478 | ||
ac718b69 | 8479 | clear_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 8480 | usb_kill_urb(tp->intr_urb); |
d2187f8e | 8481 | tasklet_disable(&tp->tx_tl); |
ce594e98 | 8482 | napi_disable(napi); |
8fb28061 | 8483 | cancel_delayed_work_sync(&tp->schedule); |
8484 | tp->rtl_ops.down(tp); | |
ce594e98 | 8485 | napi_enable(napi); |
d2187f8e | 8486 | tasklet_enable(&tp->tx_tl); |
ac718b69 | 8487 | } |
8fb28061 | 8488 | |
f741917e | 8489 | return 0; |
8fb28061 | 8490 | } |
8491 | ||
8492 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) | |
8493 | { | |
8494 | struct r8152 *tp = usb_get_intfdata(intf); | |
8495 | int ret; | |
8496 | ||
8497 | mutex_lock(&tp->control); | |
8498 | ||
8499 | if (PMSG_IS_AUTO(message)) | |
a9c54ad2 | 8500 | ret = rtl8152_runtime_suspend(tp); |
8fb28061 | 8501 | else |
8502 | ret = rtl8152_system_suspend(tp); | |
8503 | ||
b5403273 | 8504 | mutex_unlock(&tp->control); |
8505 | ||
6cc69f2a | 8506 | return ret; |
ac718b69 | 8507 | } |
8508 | ||
8509 | static int rtl8152_resume(struct usb_interface *intf) | |
8510 | { | |
8511 | struct r8152 *tp = usb_get_intfdata(intf); | |
21cbd0ec | 8512 | int ret; |
ac718b69 | 8513 | |
b5403273 | 8514 | mutex_lock(&tp->control); |
8515 | ||
b24edca3 HW |
8516 | rtl_reset_ocp_base(tp); |
8517 | ||
21cbd0ec | 8518 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) |
8519 | ret = rtl8152_runtime_resume(tp); | |
8520 | else | |
8521 | ret = rtl8152_system_resume(tp); | |
ac718b69 | 8522 | |
b5403273 | 8523 | mutex_unlock(&tp->control); |
8524 | ||
21cbd0ec | 8525 | return ret; |
ac718b69 | 8526 | } |
8527 | ||
7ec2541a | 8528 | static int rtl8152_reset_resume(struct usb_interface *intf) |
8529 | { | |
8530 | struct r8152 *tp = usb_get_intfdata(intf); | |
8531 | ||
8532 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
b24edca3 | 8533 | rtl_reset_ocp_base(tp); |
befb2de1 | 8534 | tp->rtl_ops.init(tp); |
8535 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); | |
776ac63a | 8536 | set_ethernet_addr(tp, true); |
7ec2541a | 8537 | return rtl8152_resume(intf); |
8538 | } | |
8539 | ||
21ff2e89 | 8540 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
8541 | { | |
8542 | struct r8152 *tp = netdev_priv(dev); | |
8543 | ||
9a4be1bd | 8544 | if (usb_autopm_get_interface(tp->intf) < 0) |
8545 | return; | |
8546 | ||
7daed8dc | 8547 | if (!rtl_can_wakeup(tp)) { |
8548 | wol->supported = 0; | |
8549 | wol->wolopts = 0; | |
8550 | } else { | |
8551 | mutex_lock(&tp->control); | |
8552 | wol->supported = WAKE_ANY; | |
8553 | wol->wolopts = __rtl_get_wol(tp); | |
8554 | mutex_unlock(&tp->control); | |
8555 | } | |
b5403273 | 8556 | |
9a4be1bd | 8557 | usb_autopm_put_interface(tp->intf); |
21ff2e89 | 8558 | } |
8559 | ||
8560 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
8561 | { | |
8562 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 8563 | int ret; |
8564 | ||
7daed8dc | 8565 | if (!rtl_can_wakeup(tp)) |
8566 | return -EOPNOTSUPP; | |
8567 | ||
f2750df1 FF |
8568 | if (wol->wolopts & ~WAKE_ANY) |
8569 | return -EINVAL; | |
8570 | ||
9a4be1bd | 8571 | ret = usb_autopm_get_interface(tp->intf); |
8572 | if (ret < 0) | |
8573 | goto out_set_wol; | |
21ff2e89 | 8574 | |
b5403273 | 8575 | mutex_lock(&tp->control); |
8576 | ||
21ff2e89 | 8577 | __rtl_set_wol(tp, wol->wolopts); |
8578 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
8579 | ||
b5403273 | 8580 | mutex_unlock(&tp->control); |
8581 | ||
9a4be1bd | 8582 | usb_autopm_put_interface(tp->intf); |
8583 | ||
8584 | out_set_wol: | |
8585 | return ret; | |
21ff2e89 | 8586 | } |
8587 | ||
a5ec27c1 | 8588 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
8589 | { | |
8590 | struct r8152 *tp = netdev_priv(dev); | |
8591 | ||
8592 | return tp->msg_enable; | |
8593 | } | |
8594 | ||
8595 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
8596 | { | |
8597 | struct r8152 *tp = netdev_priv(dev); | |
8598 | ||
8599 | tp->msg_enable = value; | |
8600 | } | |
8601 | ||
ac718b69 | 8602 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
8603 | struct ethtool_drvinfo *info) | |
8604 | { | |
8605 | struct r8152 *tp = netdev_priv(netdev); | |
8606 | ||
b0b46c77 | 8607 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
8608 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
ac718b69 | 8609 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
9370f2d0 HW |
8610 | if (!IS_ERR_OR_NULL(tp->rtl_fw.fw)) |
8611 | strlcpy(info->fw_version, tp->rtl_fw.version, | |
8612 | sizeof(info->fw_version)); | |
ac718b69 | 8613 | } |
8614 | ||
8615 | static | |
06144dcf PR |
8616 | int rtl8152_get_link_ksettings(struct net_device *netdev, |
8617 | struct ethtool_link_ksettings *cmd) | |
ac718b69 | 8618 | { |
8619 | struct r8152 *tp = netdev_priv(netdev); | |
8d4a4d72 | 8620 | int ret; |
ac718b69 | 8621 | |
8622 | if (!tp->mii.mdio_read) | |
8623 | return -EOPNOTSUPP; | |
8624 | ||
8d4a4d72 | 8625 | ret = usb_autopm_get_interface(tp->intf); |
8626 | if (ret < 0) | |
8627 | goto out; | |
8628 | ||
b5403273 | 8629 | mutex_lock(&tp->control); |
8630 | ||
82c01a84 | 8631 | mii_ethtool_get_link_ksettings(&tp->mii, cmd); |
8d4a4d72 | 8632 | |
195aae32 HW |
8633 | linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, |
8634 | cmd->link_modes.supported, tp->support_2500full); | |
8635 | ||
8636 | if (tp->support_2500full) { | |
8637 | linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, | |
8638 | cmd->link_modes.advertising, | |
8639 | ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G); | |
8640 | ||
8641 | linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, | |
8642 | cmd->link_modes.lp_advertising, | |
8643 | ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G); | |
8644 | ||
8645 | if (is_speed_2500(rtl8152_get_speed(tp))) | |
8646 | cmd->base.speed = SPEED_2500; | |
8647 | } | |
8648 | ||
b5403273 | 8649 | mutex_unlock(&tp->control); |
8650 | ||
8d4a4d72 | 8651 | usb_autopm_put_interface(tp->intf); |
8652 | ||
8653 | out: | |
8654 | return ret; | |
ac718b69 | 8655 | } |
8656 | ||
06144dcf PR |
8657 | static int rtl8152_set_link_ksettings(struct net_device *dev, |
8658 | const struct ethtool_link_ksettings *cmd) | |
ac718b69 | 8659 | { |
8660 | struct r8152 *tp = netdev_priv(dev); | |
771efeda | 8661 | u32 advertising = 0; |
9a4be1bd | 8662 | int ret; |
8663 | ||
8664 | ret = usb_autopm_get_interface(tp->intf); | |
8665 | if (ret < 0) | |
8666 | goto out; | |
ac718b69 | 8667 | |
771efeda HW |
8668 | if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, |
8669 | cmd->link_modes.advertising)) | |
8670 | advertising |= RTL_ADVERTISED_10_HALF; | |
8671 | ||
8672 | if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, | |
8673 | cmd->link_modes.advertising)) | |
8674 | advertising |= RTL_ADVERTISED_10_FULL; | |
8675 | ||
8676 | if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, | |
8677 | cmd->link_modes.advertising)) | |
8678 | advertising |= RTL_ADVERTISED_100_HALF; | |
8679 | ||
8680 | if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, | |
8681 | cmd->link_modes.advertising)) | |
8682 | advertising |= RTL_ADVERTISED_100_FULL; | |
8683 | ||
8684 | if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, | |
8685 | cmd->link_modes.advertising)) | |
8686 | advertising |= RTL_ADVERTISED_1000_HALF; | |
8687 | ||
8688 | if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, | |
8689 | cmd->link_modes.advertising)) | |
8690 | advertising |= RTL_ADVERTISED_1000_FULL; | |
8691 | ||
195aae32 HW |
8692 | if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, |
8693 | cmd->link_modes.advertising)) | |
8694 | advertising |= RTL_ADVERTISED_2500_FULL; | |
8695 | ||
b5403273 | 8696 | mutex_lock(&tp->control); |
8697 | ||
06144dcf | 8698 | ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, |
771efeda | 8699 | cmd->base.duplex, advertising); |
aa7e26b6 | 8700 | if (!ret) { |
06144dcf PR |
8701 | tp->autoneg = cmd->base.autoneg; |
8702 | tp->speed = cmd->base.speed; | |
8703 | tp->duplex = cmd->base.duplex; | |
771efeda | 8704 | tp->advertising = advertising; |
aa7e26b6 | 8705 | } |
9a4be1bd | 8706 | |
b5403273 | 8707 | mutex_unlock(&tp->control); |
8708 | ||
9a4be1bd | 8709 | usb_autopm_put_interface(tp->intf); |
8710 | ||
8711 | out: | |
8712 | return ret; | |
ac718b69 | 8713 | } |
8714 | ||
4f1d4d54 | 8715 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
8716 | "tx_packets", | |
8717 | "rx_packets", | |
8718 | "tx_errors", | |
8719 | "rx_errors", | |
8720 | "rx_missed", | |
8721 | "align_errors", | |
8722 | "tx_single_collisions", | |
8723 | "tx_multi_collisions", | |
8724 | "rx_unicast", | |
8725 | "rx_broadcast", | |
8726 | "rx_multicast", | |
8727 | "tx_aborted", | |
8728 | "tx_underrun", | |
8729 | }; | |
8730 | ||
8731 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
8732 | { | |
8733 | switch (sset) { | |
8734 | case ETH_SS_STATS: | |
8735 | return ARRAY_SIZE(rtl8152_gstrings); | |
8736 | default: | |
8737 | return -EOPNOTSUPP; | |
8738 | } | |
8739 | } | |
8740 | ||
8741 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
8742 | struct ethtool_stats *stats, u64 *data) | |
8743 | { | |
8744 | struct r8152 *tp = netdev_priv(dev); | |
8745 | struct tally_counter tally; | |
8746 | ||
0b030244 | 8747 | if (usb_autopm_get_interface(tp->intf) < 0) |
8748 | return; | |
8749 | ||
4f1d4d54 | 8750 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
8751 | ||
0b030244 | 8752 | usb_autopm_put_interface(tp->intf); |
8753 | ||
4f1d4d54 | 8754 | data[0] = le64_to_cpu(tally.tx_packets); |
8755 | data[1] = le64_to_cpu(tally.rx_packets); | |
8756 | data[2] = le64_to_cpu(tally.tx_errors); | |
8757 | data[3] = le32_to_cpu(tally.rx_errors); | |
8758 | data[4] = le16_to_cpu(tally.rx_missed); | |
8759 | data[5] = le16_to_cpu(tally.align_errors); | |
8760 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
8761 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
8762 | data[8] = le64_to_cpu(tally.rx_unicast); | |
8763 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
8764 | data[10] = le32_to_cpu(tally.rx_multicast); | |
8765 | data[11] = le16_to_cpu(tally.tx_aborted); | |
f37119c5 | 8766 | data[12] = le16_to_cpu(tally.tx_underrun); |
4f1d4d54 | 8767 | } |
8768 | ||
8769 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
8770 | { | |
8771 | switch (stringset) { | |
8772 | case ETH_SS_STATS: | |
99718abd | 8773 | memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings)); |
4f1d4d54 | 8774 | break; |
8775 | } | |
8776 | } | |
8777 | ||
df35d283 | 8778 | static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) |
8779 | { | |
f4a93be6 | 8780 | u32 lp, adv, supported = 0; |
df35d283 | 8781 | u16 val; |
8782 | ||
8783 | val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); | |
8784 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
8785 | ||
8786 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); | |
8787 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
8788 | ||
8789 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); | |
8790 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
8791 | ||
f4a93be6 | 8792 | eee->eee_enabled = tp->eee_en; |
df35d283 | 8793 | eee->eee_active = !!(supported & adv & lp); |
8794 | eee->supported = supported; | |
f4a93be6 | 8795 | eee->advertised = tp->eee_adv; |
df35d283 | 8796 | eee->lp_advertised = lp; |
8797 | ||
8798 | return 0; | |
8799 | } | |
8800 | ||
8801 | static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
8802 | { | |
8803 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
8804 | ||
f4a93be6 HW |
8805 | tp->eee_en = eee->eee_enabled; |
8806 | tp->eee_adv = val; | |
df35d283 | 8807 | |
e7bde56b | 8808 | rtl_eee_enable(tp, tp->eee_en); |
df35d283 | 8809 | |
8810 | return 0; | |
8811 | } | |
8812 | ||
8813 | static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
8814 | { | |
f4a93be6 | 8815 | u32 lp, adv, supported = 0; |
df35d283 | 8816 | u16 val; |
8817 | ||
8818 | val = ocp_reg_read(tp, OCP_EEE_ABLE); | |
8819 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
8820 | ||
8821 | val = ocp_reg_read(tp, OCP_EEE_ADV); | |
8822 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
8823 | ||
8824 | val = ocp_reg_read(tp, OCP_EEE_LPABLE); | |
8825 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
8826 | ||
f4a93be6 | 8827 | eee->eee_enabled = tp->eee_en; |
df35d283 | 8828 | eee->eee_active = !!(supported & adv & lp); |
8829 | eee->supported = supported; | |
f4a93be6 | 8830 | eee->advertised = tp->eee_adv; |
df35d283 | 8831 | eee->lp_advertised = lp; |
8832 | ||
8833 | return 0; | |
8834 | } | |
8835 | ||
df35d283 | 8836 | static int |
8837 | rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) | |
8838 | { | |
8839 | struct r8152 *tp = netdev_priv(net); | |
8840 | int ret; | |
8841 | ||
c79515e4 HW |
8842 | if (!tp->rtl_ops.eee_get) { |
8843 | ret = -EOPNOTSUPP; | |
8844 | goto out; | |
8845 | } | |
8846 | ||
df35d283 | 8847 | ret = usb_autopm_get_interface(tp->intf); |
8848 | if (ret < 0) | |
8849 | goto out; | |
8850 | ||
b5403273 | 8851 | mutex_lock(&tp->control); |
8852 | ||
df35d283 | 8853 | ret = tp->rtl_ops.eee_get(tp, edata); |
8854 | ||
b5403273 | 8855 | mutex_unlock(&tp->control); |
8856 | ||
df35d283 | 8857 | usb_autopm_put_interface(tp->intf); |
8858 | ||
8859 | out: | |
8860 | return ret; | |
8861 | } | |
8862 | ||
8863 | static int | |
8864 | rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) | |
8865 | { | |
8866 | struct r8152 *tp = netdev_priv(net); | |
8867 | int ret; | |
8868 | ||
c79515e4 HW |
8869 | if (!tp->rtl_ops.eee_set) { |
8870 | ret = -EOPNOTSUPP; | |
8871 | goto out; | |
8872 | } | |
8873 | ||
df35d283 | 8874 | ret = usb_autopm_get_interface(tp->intf); |
8875 | if (ret < 0) | |
8876 | goto out; | |
8877 | ||
b5403273 | 8878 | mutex_lock(&tp->control); |
8879 | ||
df35d283 | 8880 | ret = tp->rtl_ops.eee_set(tp, edata); |
9d31a7b9 | 8881 | if (!ret) |
8882 | ret = mii_nway_restart(&tp->mii); | |
df35d283 | 8883 | |
b5403273 | 8884 | mutex_unlock(&tp->control); |
8885 | ||
df35d283 | 8886 | usb_autopm_put_interface(tp->intf); |
8887 | ||
8888 | out: | |
8889 | return ret; | |
8890 | } | |
8891 | ||
8884f507 | 8892 | static int rtl8152_nway_reset(struct net_device *dev) |
8893 | { | |
8894 | struct r8152 *tp = netdev_priv(dev); | |
8895 | int ret; | |
8896 | ||
8897 | ret = usb_autopm_get_interface(tp->intf); | |
8898 | if (ret < 0) | |
8899 | goto out; | |
8900 | ||
8901 | mutex_lock(&tp->control); | |
8902 | ||
8903 | ret = mii_nway_restart(&tp->mii); | |
8904 | ||
8905 | mutex_unlock(&tp->control); | |
8906 | ||
8907 | usb_autopm_put_interface(tp->intf); | |
8908 | ||
8909 | out: | |
8910 | return ret; | |
8911 | } | |
8912 | ||
efb3dd88 | 8913 | static int rtl8152_get_coalesce(struct net_device *netdev, |
f3ccfda1 YM |
8914 | struct ethtool_coalesce *coalesce, |
8915 | struct kernel_ethtool_coalesce *kernel_coal, | |
8916 | struct netlink_ext_ack *extack) | |
efb3dd88 | 8917 | { |
8918 | struct r8152 *tp = netdev_priv(netdev); | |
8919 | ||
8920 | switch (tp->version) { | |
8921 | case RTL_VER_01: | |
8922 | case RTL_VER_02: | |
c27b32c2 | 8923 | case RTL_VER_07: |
efb3dd88 | 8924 | return -EOPNOTSUPP; |
8925 | default: | |
8926 | break; | |
8927 | } | |
8928 | ||
8929 | coalesce->rx_coalesce_usecs = tp->coalesce; | |
8930 | ||
8931 | return 0; | |
8932 | } | |
8933 | ||
8934 | static int rtl8152_set_coalesce(struct net_device *netdev, | |
f3ccfda1 YM |
8935 | struct ethtool_coalesce *coalesce, |
8936 | struct kernel_ethtool_coalesce *kernel_coal, | |
8937 | struct netlink_ext_ack *extack) | |
efb3dd88 | 8938 | { |
8939 | struct r8152 *tp = netdev_priv(netdev); | |
8940 | int ret; | |
8941 | ||
8942 | switch (tp->version) { | |
8943 | case RTL_VER_01: | |
8944 | case RTL_VER_02: | |
c27b32c2 | 8945 | case RTL_VER_07: |
efb3dd88 | 8946 | return -EOPNOTSUPP; |
8947 | default: | |
8948 | break; | |
8949 | } | |
8950 | ||
8951 | if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) | |
8952 | return -EINVAL; | |
8953 | ||
8954 | ret = usb_autopm_get_interface(tp->intf); | |
8955 | if (ret < 0) | |
8956 | return ret; | |
8957 | ||
8958 | mutex_lock(&tp->control); | |
8959 | ||
8960 | if (tp->coalesce != coalesce->rx_coalesce_usecs) { | |
8961 | tp->coalesce = coalesce->rx_coalesce_usecs; | |
8962 | ||
9fae5418 HW |
8963 | if (netif_running(netdev) && netif_carrier_ok(netdev)) { |
8964 | netif_stop_queue(netdev); | |
8965 | napi_disable(&tp->napi); | |
8966 | tp->rtl_ops.disable(tp); | |
8967 | tp->rtl_ops.enable(tp); | |
8968 | rtl_start_rx(tp); | |
8969 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); | |
8970 | _rtl8152_set_rx_mode(netdev); | |
8971 | napi_enable(&tp->napi); | |
8972 | netif_wake_queue(netdev); | |
8973 | } | |
efb3dd88 | 8974 | } |
8975 | ||
8976 | mutex_unlock(&tp->control); | |
8977 | ||
8978 | usb_autopm_put_interface(tp->intf); | |
8979 | ||
8980 | return ret; | |
8981 | } | |
8982 | ||
e4a5017a HW |
8983 | static int rtl8152_get_tunable(struct net_device *netdev, |
8984 | const struct ethtool_tunable *tunable, void *d) | |
8985 | { | |
8986 | struct r8152 *tp = netdev_priv(netdev); | |
8987 | ||
8988 | switch (tunable->id) { | |
8989 | case ETHTOOL_RX_COPYBREAK: | |
8990 | *(u32 *)d = tp->rx_copybreak; | |
8991 | break; | |
8992 | default: | |
8993 | return -EOPNOTSUPP; | |
8994 | } | |
8995 | ||
8996 | return 0; | |
8997 | } | |
8998 | ||
8999 | static int rtl8152_set_tunable(struct net_device *netdev, | |
9000 | const struct ethtool_tunable *tunable, | |
9001 | const void *d) | |
9002 | { | |
9003 | struct r8152 *tp = netdev_priv(netdev); | |
9004 | u32 val; | |
9005 | ||
9006 | switch (tunable->id) { | |
9007 | case ETHTOOL_RX_COPYBREAK: | |
9008 | val = *(u32 *)d; | |
9009 | if (val < ETH_ZLEN) { | |
9010 | netif_err(tp, rx_err, netdev, | |
9011 | "Invalid rx copy break value\n"); | |
9012 | return -EINVAL; | |
9013 | } | |
9014 | ||
9015 | if (tp->rx_copybreak != val) { | |
5b1d9c17 HW |
9016 | if (netdev->flags & IFF_UP) { |
9017 | mutex_lock(&tp->control); | |
9018 | napi_disable(&tp->napi); | |
9019 | tp->rx_copybreak = val; | |
9020 | napi_enable(&tp->napi); | |
9021 | mutex_unlock(&tp->control); | |
9022 | } else { | |
9023 | tp->rx_copybreak = val; | |
9024 | } | |
e4a5017a HW |
9025 | } |
9026 | break; | |
9027 | default: | |
9028 | return -EOPNOTSUPP; | |
9029 | } | |
9030 | ||
9031 | return 0; | |
9032 | } | |
9033 | ||
9034 | static void rtl8152_get_ringparam(struct net_device *netdev, | |
74624944 HC |
9035 | struct ethtool_ringparam *ring, |
9036 | struct kernel_ethtool_ringparam *kernel_ring, | |
9037 | struct netlink_ext_ack *extack) | |
e4a5017a HW |
9038 | { |
9039 | struct r8152 *tp = netdev_priv(netdev); | |
9040 | ||
9041 | ring->rx_max_pending = RTL8152_RX_MAX_PENDING; | |
9042 | ring->rx_pending = tp->rx_pending; | |
9043 | } | |
9044 | ||
9045 | static int rtl8152_set_ringparam(struct net_device *netdev, | |
74624944 HC |
9046 | struct ethtool_ringparam *ring, |
9047 | struct kernel_ethtool_ringparam *kernel_ring, | |
9048 | struct netlink_ext_ack *extack) | |
e4a5017a HW |
9049 | { |
9050 | struct r8152 *tp = netdev_priv(netdev); | |
9051 | ||
9052 | if (ring->rx_pending < (RTL8152_MAX_RX * 2)) | |
9053 | return -EINVAL; | |
9054 | ||
9055 | if (tp->rx_pending != ring->rx_pending) { | |
5b1d9c17 HW |
9056 | if (netdev->flags & IFF_UP) { |
9057 | mutex_lock(&tp->control); | |
9058 | napi_disable(&tp->napi); | |
9059 | tp->rx_pending = ring->rx_pending; | |
9060 | napi_enable(&tp->napi); | |
9061 | mutex_unlock(&tp->control); | |
9062 | } else { | |
9063 | tp->rx_pending = ring->rx_pending; | |
9064 | } | |
e4a5017a HW |
9065 | } |
9066 | ||
9067 | return 0; | |
9068 | } | |
9069 | ||
163d01c5 HW |
9070 | static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) |
9071 | { | |
9072 | struct r8152 *tp = netdev_priv(netdev); | |
9073 | u16 bmcr, lcladv, rmtadv; | |
9074 | u8 cap; | |
9075 | ||
9076 | if (usb_autopm_get_interface(tp->intf) < 0) | |
9077 | return; | |
9078 | ||
9079 | mutex_lock(&tp->control); | |
9080 | ||
9081 | bmcr = r8152_mdio_read(tp, MII_BMCR); | |
9082 | lcladv = r8152_mdio_read(tp, MII_ADVERTISE); | |
9083 | rmtadv = r8152_mdio_read(tp, MII_LPA); | |
9084 | ||
9085 | mutex_unlock(&tp->control); | |
9086 | ||
9087 | usb_autopm_put_interface(tp->intf); | |
9088 | ||
9089 | if (!(bmcr & BMCR_ANENABLE)) { | |
9090 | pause->autoneg = 0; | |
9091 | pause->rx_pause = 0; | |
9092 | pause->tx_pause = 0; | |
9093 | return; | |
9094 | } | |
9095 | ||
9096 | pause->autoneg = 1; | |
9097 | ||
9098 | cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); | |
9099 | ||
9100 | if (cap & FLOW_CTRL_RX) | |
9101 | pause->rx_pause = 1; | |
9102 | ||
9103 | if (cap & FLOW_CTRL_TX) | |
9104 | pause->tx_pause = 1; | |
9105 | } | |
9106 | ||
9107 | static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) | |
9108 | { | |
9109 | struct r8152 *tp = netdev_priv(netdev); | |
9110 | u16 old, new1; | |
9111 | u8 cap = 0; | |
9112 | int ret; | |
9113 | ||
9114 | ret = usb_autopm_get_interface(tp->intf); | |
9115 | if (ret < 0) | |
9116 | return ret; | |
9117 | ||
9118 | mutex_lock(&tp->control); | |
9119 | ||
9120 | if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) { | |
9121 | ret = -EINVAL; | |
9122 | goto out; | |
9123 | } | |
9124 | ||
9125 | if (pause->rx_pause) | |
9126 | cap |= FLOW_CTRL_RX; | |
9127 | ||
9128 | if (pause->tx_pause) | |
9129 | cap |= FLOW_CTRL_TX; | |
9130 | ||
9131 | old = r8152_mdio_read(tp, MII_ADVERTISE); | |
9132 | new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap); | |
9133 | if (old != new1) | |
9134 | r8152_mdio_write(tp, MII_ADVERTISE, new1); | |
9135 | ||
9136 | out: | |
9137 | mutex_unlock(&tp->control); | |
9138 | usb_autopm_put_interface(tp->intf); | |
9139 | ||
9140 | return ret; | |
9141 | } | |
9142 | ||
407a471d | 9143 | static const struct ethtool_ops ops = { |
e52a646b | 9144 | .supported_coalesce_params = ETHTOOL_COALESCE_USECS, |
ac718b69 | 9145 | .get_drvinfo = rtl8152_get_drvinfo, |
ac718b69 | 9146 | .get_link = ethtool_op_get_link, |
8884f507 | 9147 | .nway_reset = rtl8152_nway_reset, |
a5ec27c1 | 9148 | .get_msglevel = rtl8152_get_msglevel, |
9149 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 9150 | .get_wol = rtl8152_get_wol, |
9151 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 9152 | .get_strings = rtl8152_get_strings, |
9153 | .get_sset_count = rtl8152_get_sset_count, | |
9154 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
efb3dd88 | 9155 | .get_coalesce = rtl8152_get_coalesce, |
9156 | .set_coalesce = rtl8152_set_coalesce, | |
df35d283 | 9157 | .get_eee = rtl_ethtool_get_eee, |
9158 | .set_eee = rtl_ethtool_set_eee, | |
06144dcf PR |
9159 | .get_link_ksettings = rtl8152_get_link_ksettings, |
9160 | .set_link_ksettings = rtl8152_set_link_ksettings, | |
e4a5017a HW |
9161 | .get_tunable = rtl8152_get_tunable, |
9162 | .set_tunable = rtl8152_set_tunable, | |
9163 | .get_ringparam = rtl8152_get_ringparam, | |
9164 | .set_ringparam = rtl8152_set_ringparam, | |
163d01c5 HW |
9165 | .get_pauseparam = rtl8152_get_pauseparam, |
9166 | .set_pauseparam = rtl8152_set_pauseparam, | |
ac718b69 | 9167 | }; |
9168 | ||
9169 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
9170 | { | |
9171 | struct r8152 *tp = netdev_priv(netdev); | |
9172 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 9173 | int res; |
9174 | ||
6871438c | 9175 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
9176 | return -ENODEV; | |
9177 | ||
9a4be1bd | 9178 | res = usb_autopm_get_interface(tp->intf); |
9179 | if (res < 0) | |
9180 | goto out; | |
ac718b69 | 9181 | |
9182 | switch (cmd) { | |
9183 | case SIOCGMIIPHY: | |
9184 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
9185 | break; | |
9186 | ||
9187 | case SIOCGMIIREG: | |
b5403273 | 9188 | mutex_lock(&tp->control); |
ac718b69 | 9189 | data->val_out = r8152_mdio_read(tp, data->reg_num); |
b5403273 | 9190 | mutex_unlock(&tp->control); |
ac718b69 | 9191 | break; |
9192 | ||
9193 | case SIOCSMIIREG: | |
9194 | if (!capable(CAP_NET_ADMIN)) { | |
9195 | res = -EPERM; | |
9196 | break; | |
9197 | } | |
b5403273 | 9198 | mutex_lock(&tp->control); |
ac718b69 | 9199 | r8152_mdio_write(tp, data->reg_num, data->val_in); |
b5403273 | 9200 | mutex_unlock(&tp->control); |
ac718b69 | 9201 | break; |
9202 | ||
9203 | default: | |
9204 | res = -EOPNOTSUPP; | |
9205 | } | |
9206 | ||
9a4be1bd | 9207 | usb_autopm_put_interface(tp->intf); |
9208 | ||
9209 | out: | |
ac718b69 | 9210 | return res; |
9211 | } | |
9212 | ||
69b4b7a4 | 9213 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
9214 | { | |
9215 | struct r8152 *tp = netdev_priv(dev); | |
396e2e23 | 9216 | int ret; |
69b4b7a4 | 9217 | |
9218 | switch (tp->version) { | |
9219 | case RTL_VER_01: | |
9220 | case RTL_VER_02: | |
c27b32c2 | 9221 | case RTL_VER_07: |
a52ad514 JW |
9222 | dev->mtu = new_mtu; |
9223 | return 0; | |
69b4b7a4 | 9224 | default: |
9225 | break; | |
9226 | } | |
9227 | ||
396e2e23 | 9228 | ret = usb_autopm_get_interface(tp->intf); |
9229 | if (ret < 0) | |
9230 | return ret; | |
9231 | ||
9232 | mutex_lock(&tp->control); | |
9233 | ||
69b4b7a4 | 9234 | dev->mtu = new_mtu; |
9235 | ||
210c4f70 | 9236 | if (netif_running(dev)) { |
67ce1a80 HW |
9237 | if (tp->rtl_ops.change_mtu) |
9238 | tp->rtl_ops.change_mtu(tp); | |
210c4f70 | 9239 | |
67ce1a80 HW |
9240 | if (netif_carrier_ok(dev)) { |
9241 | netif_stop_queue(dev); | |
9242 | napi_disable(&tp->napi); | |
9243 | tasklet_disable(&tp->tx_tl); | |
9244 | tp->rtl_ops.disable(tp); | |
9245 | tp->rtl_ops.enable(tp); | |
9246 | rtl_start_rx(tp); | |
9247 | tasklet_enable(&tp->tx_tl); | |
9248 | napi_enable(&tp->napi); | |
9249 | rtl8152_set_rx_mode(dev); | |
9250 | netif_wake_queue(dev); | |
9251 | } | |
210c4f70 | 9252 | } |
396e2e23 | 9253 | |
9254 | mutex_unlock(&tp->control); | |
9255 | ||
9256 | usb_autopm_put_interface(tp->intf); | |
9257 | ||
9258 | return ret; | |
69b4b7a4 | 9259 | } |
9260 | ||
ac718b69 | 9261 | static const struct net_device_ops rtl8152_netdev_ops = { |
9262 | .ndo_open = rtl8152_open, | |
9263 | .ndo_stop = rtl8152_close, | |
a7605370 | 9264 | .ndo_eth_ioctl = rtl8152_ioctl, |
ac718b69 | 9265 | .ndo_start_xmit = rtl8152_start_xmit, |
9266 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
c5554298 | 9267 | .ndo_set_features = rtl8152_set_features, |
ac718b69 | 9268 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
9269 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 9270 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 9271 | .ndo_validate_addr = eth_validate_addr, |
a5e31255 | 9272 | .ndo_features_check = rtl8152_features_check, |
ac718b69 | 9273 | }; |
9274 | ||
e3fe0b1a | 9275 | static void rtl8152_unload(struct r8152 *tp) |
9276 | { | |
6871438c | 9277 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
9278 | return; | |
9279 | ||
00a5e360 | 9280 | if (tp->version != RTL_VER_01) |
9281 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 9282 | } |
9283 | ||
43779f8d | 9284 | static void rtl8153_unload(struct r8152 *tp) |
9285 | { | |
6871438c | 9286 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
9287 | return; | |
9288 | ||
49be1723 | 9289 | r8153_power_cut_en(tp, false); |
43779f8d | 9290 | } |
9291 | ||
65b82d69 | 9292 | static void rtl8153b_unload(struct r8152 *tp) |
9293 | { | |
9294 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
9295 | return; | |
9296 | ||
9297 | r8153b_power_cut_en(tp, false); | |
9298 | } | |
9299 | ||
55b65475 | 9300 | static int rtl_ops_init(struct r8152 *tp) |
c81229c9 | 9301 | { |
9302 | struct rtl_ops *ops = &tp->rtl_ops; | |
55b65475 | 9303 | int ret = 0; |
9304 | ||
9305 | switch (tp->version) { | |
9306 | case RTL_VER_01: | |
9307 | case RTL_VER_02: | |
c27b32c2 | 9308 | case RTL_VER_07: |
55b65475 | 9309 | ops->init = r8152b_init; |
9310 | ops->enable = rtl8152_enable; | |
9311 | ops->disable = rtl8152_disable; | |
9312 | ops->up = rtl8152_up; | |
9313 | ops->down = rtl8152_down; | |
9314 | ops->unload = rtl8152_unload; | |
9315 | ops->eee_get = r8152_get_eee; | |
9316 | ops->eee_set = r8152_set_eee; | |
2dd49e0f | 9317 | ops->in_nway = rtl8152_in_nway; |
a028a9e0 | 9318 | ops->hw_phy_cfg = r8152b_hw_phy_cfg; |
2609af19 | 9319 | ops->autosuspend_en = rtl_runtime_suspend_enable; |
ec5791c2 | 9320 | tp->rx_buf_sz = 16 * 1024; |
f4a93be6 HW |
9321 | tp->eee_en = true; |
9322 | tp->eee_adv = MDIO_EEE_100TX; | |
43779f8d | 9323 | break; |
9324 | ||
55b65475 | 9325 | case RTL_VER_03: |
9326 | case RTL_VER_04: | |
9327 | case RTL_VER_05: | |
fb02eb4a | 9328 | case RTL_VER_06: |
55b65475 | 9329 | ops->init = r8153_init; |
9330 | ops->enable = rtl8153_enable; | |
9331 | ops->disable = rtl8153_disable; | |
9332 | ops->up = rtl8153_up; | |
9333 | ops->down = rtl8153_down; | |
9334 | ops->unload = rtl8153_unload; | |
9335 | ops->eee_get = r8153_get_eee; | |
e7bde56b | 9336 | ops->eee_set = r8152_set_eee; |
2dd49e0f | 9337 | ops->in_nway = rtl8153_in_nway; |
a028a9e0 | 9338 | ops->hw_phy_cfg = r8153_hw_phy_cfg; |
2609af19 | 9339 | ops->autosuspend_en = rtl8153_runtime_enable; |
67ce1a80 | 9340 | ops->change_mtu = rtl8153_change_mtu; |
f91a50d8 HW |
9341 | if (tp->udev->speed < USB_SPEED_SUPER) |
9342 | tp->rx_buf_sz = 16 * 1024; | |
9343 | else | |
9344 | tp->rx_buf_sz = 32 * 1024; | |
f4a93be6 HW |
9345 | tp->eee_en = true; |
9346 | tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; | |
c81229c9 | 9347 | break; |
9348 | ||
65b82d69 | 9349 | case RTL_VER_08: |
9350 | case RTL_VER_09: | |
9351 | ops->init = r8153b_init; | |
9352 | ops->enable = rtl8153_enable; | |
0e5b36bc | 9353 | ops->disable = rtl8153_disable; |
65b82d69 | 9354 | ops->up = rtl8153b_up; |
9355 | ops->down = rtl8153b_down; | |
9356 | ops->unload = rtl8153b_unload; | |
9357 | ops->eee_get = r8153_get_eee; | |
e7bde56b | 9358 | ops->eee_set = r8152_set_eee; |
65b82d69 | 9359 | ops->in_nway = rtl8153_in_nway; |
9360 | ops->hw_phy_cfg = r8153b_hw_phy_cfg; | |
9361 | ops->autosuspend_en = rtl8153b_runtime_enable; | |
67ce1a80 | 9362 | ops->change_mtu = rtl8153_change_mtu; |
ec5791c2 | 9363 | tp->rx_buf_sz = 32 * 1024; |
f4a93be6 HW |
9364 | tp->eee_en = true; |
9365 | tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; | |
65b82d69 | 9366 | break; |
9367 | ||
195aae32 HW |
9368 | case RTL_VER_11: |
9369 | tp->eee_en = true; | |
9370 | tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; | |
9371 | fallthrough; | |
9372 | case RTL_VER_10: | |
9373 | ops->init = r8156_init; | |
9374 | ops->enable = rtl8156_enable; | |
9375 | ops->disable = rtl8153_disable; | |
9376 | ops->up = rtl8156_up; | |
9377 | ops->down = rtl8156_down; | |
9378 | ops->unload = rtl8153_unload; | |
9379 | ops->eee_get = r8153_get_eee; | |
9380 | ops->eee_set = r8152_set_eee; | |
9381 | ops->in_nway = rtl8153_in_nway; | |
9382 | ops->hw_phy_cfg = r8156_hw_phy_cfg; | |
9383 | ops->autosuspend_en = rtl8156_runtime_enable; | |
9384 | ops->change_mtu = rtl8156_change_mtu; | |
9385 | tp->rx_buf_sz = 48 * 1024; | |
9386 | tp->support_2500full = 1; | |
9387 | break; | |
9388 | ||
9389 | case RTL_VER_12: | |
9390 | case RTL_VER_13: | |
9391 | tp->support_2500full = 1; | |
9392 | fallthrough; | |
9393 | case RTL_VER_15: | |
9394 | tp->eee_en = true; | |
9395 | tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; | |
9396 | ops->init = r8156b_init; | |
9397 | ops->enable = rtl8156b_enable; | |
9398 | ops->disable = rtl8153_disable; | |
9399 | ops->up = rtl8156_up; | |
9400 | ops->down = rtl8156_down; | |
9401 | ops->unload = rtl8153_unload; | |
9402 | ops->eee_get = r8153_get_eee; | |
9403 | ops->eee_set = r8152_set_eee; | |
9404 | ops->in_nway = rtl8153_in_nway; | |
9405 | ops->hw_phy_cfg = r8156b_hw_phy_cfg; | |
9406 | ops->autosuspend_en = rtl8156_runtime_enable; | |
9407 | ops->change_mtu = rtl8156_change_mtu; | |
9408 | tp->rx_buf_sz = 48 * 1024; | |
9409 | break; | |
9410 | ||
9411 | case RTL_VER_14: | |
9412 | ops->init = r8153c_init; | |
9413 | ops->enable = rtl8153_enable; | |
9414 | ops->disable = rtl8153_disable; | |
9415 | ops->up = rtl8153c_up; | |
9416 | ops->down = rtl8153b_down; | |
9417 | ops->unload = rtl8153_unload; | |
9418 | ops->eee_get = r8153_get_eee; | |
9419 | ops->eee_set = r8152_set_eee; | |
9420 | ops->in_nway = rtl8153_in_nway; | |
9421 | ops->hw_phy_cfg = r8153c_hw_phy_cfg; | |
9422 | ops->autosuspend_en = rtl8153c_runtime_enable; | |
9423 | ops->change_mtu = rtl8153c_change_mtu; | |
9424 | tp->rx_buf_sz = 32 * 1024; | |
9425 | tp->eee_en = true; | |
9426 | tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; | |
9427 | break; | |
9428 | ||
c81229c9 | 9429 | default: |
55b65475 | 9430 | ret = -ENODEV; |
156c3207 | 9431 | dev_err(&tp->intf->dev, "Unknown Device\n"); |
c81229c9 | 9432 | break; |
9433 | } | |
9434 | ||
9435 | return ret; | |
9436 | } | |
9437 | ||
9370f2d0 HW |
9438 | #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw" |
9439 | #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw" | |
9440 | #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw" | |
9441 | #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw" | |
195aae32 | 9442 | #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw" |
4a51b0e8 HW |
9443 | #define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw" |
9444 | #define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw" | |
9370f2d0 HW |
9445 | |
9446 | MODULE_FIRMWARE(FIRMWARE_8153A_2); | |
9447 | MODULE_FIRMWARE(FIRMWARE_8153A_3); | |
9448 | MODULE_FIRMWARE(FIRMWARE_8153A_4); | |
9449 | MODULE_FIRMWARE(FIRMWARE_8153B_2); | |
195aae32 | 9450 | MODULE_FIRMWARE(FIRMWARE_8153C_1); |
4a51b0e8 HW |
9451 | MODULE_FIRMWARE(FIRMWARE_8156A_2); |
9452 | MODULE_FIRMWARE(FIRMWARE_8156B_2); | |
9370f2d0 HW |
9453 | |
9454 | static int rtl_fw_init(struct r8152 *tp) | |
9455 | { | |
9456 | struct rtl_fw *rtl_fw = &tp->rtl_fw; | |
9457 | ||
9458 | switch (tp->version) { | |
9459 | case RTL_VER_04: | |
9460 | rtl_fw->fw_name = FIRMWARE_8153A_2; | |
9461 | rtl_fw->pre_fw = r8153_pre_firmware_1; | |
9462 | rtl_fw->post_fw = r8153_post_firmware_1; | |
9463 | break; | |
9464 | case RTL_VER_05: | |
9465 | rtl_fw->fw_name = FIRMWARE_8153A_3; | |
9466 | rtl_fw->pre_fw = r8153_pre_firmware_2; | |
9467 | rtl_fw->post_fw = r8153_post_firmware_2; | |
9468 | break; | |
9469 | case RTL_VER_06: | |
9470 | rtl_fw->fw_name = FIRMWARE_8153A_4; | |
9471 | rtl_fw->post_fw = r8153_post_firmware_3; | |
9472 | break; | |
9473 | case RTL_VER_09: | |
9474 | rtl_fw->fw_name = FIRMWARE_8153B_2; | |
9475 | rtl_fw->pre_fw = r8153b_pre_firmware_1; | |
9476 | rtl_fw->post_fw = r8153b_post_firmware_1; | |
9477 | break; | |
4a51b0e8 HW |
9478 | case RTL_VER_11: |
9479 | rtl_fw->fw_name = FIRMWARE_8156A_2; | |
9480 | rtl_fw->post_fw = r8156a_post_firmware_1; | |
9481 | break; | |
9482 | case RTL_VER_13: | |
9483 | case RTL_VER_15: | |
9484 | rtl_fw->fw_name = FIRMWARE_8156B_2; | |
9485 | break; | |
195aae32 HW |
9486 | case RTL_VER_14: |
9487 | rtl_fw->fw_name = FIRMWARE_8153C_1; | |
9488 | rtl_fw->pre_fw = r8153b_pre_firmware_1; | |
9489 | rtl_fw->post_fw = r8153c_post_firmware_1; | |
9490 | break; | |
9370f2d0 HW |
9491 | default: |
9492 | break; | |
9493 | } | |
9494 | ||
9495 | return 0; | |
9496 | } | |
9497 | ||
c1aedf01 | 9498 | u8 rtl8152_get_version(struct usb_interface *intf) |
33928eed | 9499 | { |
9500 | struct usb_device *udev = interface_to_usbdev(intf); | |
9501 | u32 ocp_data = 0; | |
9502 | __le32 *tmp; | |
9503 | u8 version; | |
9504 | int ret; | |
9505 | ||
9506 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
9507 | if (!tmp) | |
9508 | return 0; | |
9509 | ||
9510 | ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), | |
9511 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, | |
9512 | PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); | |
9513 | if (ret > 0) | |
9514 | ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; | |
9515 | ||
9516 | kfree(tmp); | |
9517 | ||
9518 | switch (ocp_data) { | |
9519 | case 0x4c00: | |
9520 | version = RTL_VER_01; | |
9521 | break; | |
9522 | case 0x4c10: | |
9523 | version = RTL_VER_02; | |
9524 | break; | |
9525 | case 0x5c00: | |
9526 | version = RTL_VER_03; | |
9527 | break; | |
9528 | case 0x5c10: | |
9529 | version = RTL_VER_04; | |
9530 | break; | |
9531 | case 0x5c20: | |
9532 | version = RTL_VER_05; | |
9533 | break; | |
9534 | case 0x5c30: | |
9535 | version = RTL_VER_06; | |
9536 | break; | |
c27b32c2 | 9537 | case 0x4800: |
9538 | version = RTL_VER_07; | |
9539 | break; | |
65b82d69 | 9540 | case 0x6000: |
9541 | version = RTL_VER_08; | |
9542 | break; | |
9543 | case 0x6010: | |
9544 | version = RTL_VER_09; | |
9545 | break; | |
195aae32 HW |
9546 | case 0x7010: |
9547 | version = RTL_TEST_01; | |
9548 | break; | |
9549 | case 0x7020: | |
9550 | version = RTL_VER_10; | |
9551 | break; | |
9552 | case 0x7030: | |
9553 | version = RTL_VER_11; | |
9554 | break; | |
9555 | case 0x7400: | |
9556 | version = RTL_VER_12; | |
9557 | break; | |
9558 | case 0x7410: | |
9559 | version = RTL_VER_13; | |
9560 | break; | |
9561 | case 0x6400: | |
9562 | version = RTL_VER_14; | |
9563 | break; | |
9564 | case 0x7420: | |
9565 | version = RTL_VER_15; | |
9566 | break; | |
33928eed | 9567 | default: |
9568 | version = RTL_VER_UNKNOWN; | |
9569 | dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); | |
9570 | break; | |
9571 | } | |
9572 | ||
eb3c28c1 ON |
9573 | dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); |
9574 | ||
33928eed | 9575 | return version; |
9576 | } | |
c1aedf01 | 9577 | EXPORT_SYMBOL_GPL(rtl8152_get_version); |
33928eed | 9578 | |
f01cdcf8 DO |
9579 | static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev) |
9580 | { | |
9581 | int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor); | |
9582 | int product_id = le16_to_cpu(udev->descriptor.idProduct); | |
9583 | int vendor_id = le16_to_cpu(udev->descriptor.idVendor); | |
9584 | ||
9585 | if (vendor_id == VENDOR_ID_LENOVO) { | |
9586 | switch (product_id) { | |
9587 | case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2: | |
9588 | case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2: | |
9589 | case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3: | |
9590 | case DEVICE_ID_THINKPAD_USB_C_DONGLE: | |
9591 | return 1; | |
9592 | } | |
9593 | } else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) { | |
9594 | switch (product_id) { | |
9595 | case 0x8153: | |
9596 | return 1; | |
9597 | } | |
9598 | } | |
9599 | return 0; | |
9600 | } | |
9601 | ||
ac718b69 | 9602 | static int rtl8152_probe(struct usb_interface *intf, |
9603 | const struct usb_device_id *id) | |
9604 | { | |
9605 | struct usb_device *udev = interface_to_usbdev(intf); | |
c1aedf01 | 9606 | u8 version = rtl8152_get_version(intf); |
ac718b69 | 9607 | struct r8152 *tp; |
9608 | struct net_device *netdev; | |
ebc2ec48 | 9609 | int ret; |
ac718b69 | 9610 | |
33928eed | 9611 | if (version == RTL_VER_UNKNOWN) |
9612 | return -ENODEV; | |
9613 | ||
c2198943 | 9614 | if (!rtl_vendor_mode(intf)) |
10c32717 | 9615 | return -ENODEV; |
10c32717 | 9616 | |
9617 | usb_reset_device(udev); | |
ac718b69 | 9618 | netdev = alloc_etherdev(sizeof(struct r8152)); |
9619 | if (!netdev) { | |
4a8deae2 | 9620 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 9621 | return -ENOMEM; |
9622 | } | |
9623 | ||
ebc2ec48 | 9624 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 9625 | tp = netdev_priv(netdev); |
9626 | tp->msg_enable = 0x7FFF; | |
9627 | ||
e3ad412a | 9628 | tp->udev = udev; |
9629 | tp->netdev = netdev; | |
9630 | tp->intf = intf; | |
33928eed | 9631 | tp->version = version; |
9632 | ||
b67fda9a HW |
9633 | tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0); |
9634 | tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0); | |
9635 | tp->pipe_in = usb_rcvbulkpipe(udev, 1); | |
9636 | tp->pipe_out = usb_sndbulkpipe(udev, 2); | |
9637 | tp->pipe_intr = usb_rcvintpipe(udev, 3); | |
9638 | ||
33928eed | 9639 | switch (version) { |
9640 | case RTL_VER_01: | |
9641 | case RTL_VER_02: | |
c27b32c2 | 9642 | case RTL_VER_07: |
33928eed | 9643 | tp->mii.supports_gmii = 0; |
9644 | break; | |
9645 | default: | |
9646 | tp->mii.supports_gmii = 1; | |
9647 | break; | |
9648 | } | |
e3ad412a | 9649 | |
55b65475 | 9650 | ret = rtl_ops_init(tp); |
31ca1dec | 9651 | if (ret) |
9652 | goto out; | |
c81229c9 | 9653 | |
9370f2d0 HW |
9654 | rtl_fw_init(tp); |
9655 | ||
b5403273 | 9656 | mutex_init(&tp->control); |
ac718b69 | 9657 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
a028a9e0 | 9658 | INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); |
f3163f1c | 9659 | tasklet_setup(&tp->tx_tl, bottom_half); |
d2187f8e | 9660 | tasklet_disable(&tp->tx_tl); |
ac718b69 | 9661 | |
ac718b69 | 9662 | netdev->netdev_ops = &rtl8152_netdev_ops; |
9663 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 9664 | |
60c89071 | 9665 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 9666 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
c5554298 | 9667 | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | |
9668 | NETIF_F_HW_VLAN_CTAG_TX; | |
60c89071 | 9669 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 9670 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
c5554298 | 9671 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | |
ccc39faf | 9672 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; |
c5554298 | 9673 | netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
9674 | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | | |
9675 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 9676 | |
19c0f40d | 9677 | if (tp->version == RTL_VER_01) { |
9678 | netdev->features &= ~NETIF_F_RXCSUM; | |
9679 | netdev->hw_features &= ~NETIF_F_RXCSUM; | |
9680 | } | |
9681 | ||
f01cdcf8 | 9682 | tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev); |
9647722b | 9683 | |
176eb614 | 9684 | if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && |
151ea094 PM |
9685 | (!strcmp(udev->serial, "000001000000") || |
9686 | !strcmp(udev->serial, "000002000000"))) { | |
0b165514 | 9687 | dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); |
9c68011b | 9688 | tp->dell_tb_rx_agg_bug = 1; |
0b165514 KHF |
9689 | } |
9690 | ||
7ad24ea4 | 9691 | netdev->ethtool_ops = &ops; |
ee8b7a11 | 9692 | netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 9693 | |
f77f0aee JW |
9694 | /* MTU range: 68 - 1500 or 9194 */ |
9695 | netdev->min_mtu = ETH_MIN_MTU; | |
9696 | switch (tp->version) { | |
195aae32 HW |
9697 | case RTL_VER_03: |
9698 | case RTL_VER_04: | |
9699 | case RTL_VER_05: | |
9700 | case RTL_VER_06: | |
9701 | case RTL_VER_08: | |
9702 | case RTL_VER_09: | |
9703 | case RTL_VER_14: | |
9704 | netdev->max_mtu = size_to_mtu(9 * 1024); | |
9705 | break; | |
9706 | case RTL_VER_10: | |
9707 | case RTL_VER_11: | |
9708 | netdev->max_mtu = size_to_mtu(15 * 1024); | |
9709 | break; | |
9710 | case RTL_VER_12: | |
9711 | case RTL_VER_13: | |
9712 | case RTL_VER_15: | |
9713 | netdev->max_mtu = size_to_mtu(16 * 1024); | |
9714 | break; | |
f77f0aee JW |
9715 | case RTL_VER_01: |
9716 | case RTL_VER_02: | |
195aae32 | 9717 | case RTL_VER_07: |
f77f0aee | 9718 | default: |
195aae32 | 9719 | netdev->max_mtu = ETH_DATA_LEN; |
f77f0aee JW |
9720 | break; |
9721 | } | |
9722 | ||
ac718b69 | 9723 | tp->mii.dev = netdev; |
9724 | tp->mii.mdio_read = read_mii_word; | |
9725 | tp->mii.mdio_write = write_mii_word; | |
9726 | tp->mii.phy_id_mask = 0x3f; | |
9727 | tp->mii.reg_num_mask = 0x1f; | |
9728 | tp->mii.phy_id = R8152_PHY_ID; | |
ac718b69 | 9729 | |
aa7e26b6 | 9730 | tp->autoneg = AUTONEG_ENABLE; |
771efeda HW |
9731 | tp->speed = SPEED_100; |
9732 | tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | | |
9733 | RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; | |
9734 | if (tp->mii.supports_gmii) { | |
195aae32 HW |
9735 | if (tp->support_2500full && |
9736 | tp->udev->speed >= USB_SPEED_SUPER) { | |
9737 | tp->speed = SPEED_2500; | |
9738 | tp->advertising |= RTL_ADVERTISED_2500_FULL; | |
9739 | } else { | |
9740 | tp->speed = SPEED_1000; | |
9741 | } | |
771efeda HW |
9742 | tp->advertising |= RTL_ADVERTISED_1000_FULL; |
9743 | } | |
aa7e26b6 | 9744 | tp->duplex = DUPLEX_FULL; |
9745 | ||
e4a5017a HW |
9746 | tp->rx_copybreak = RTL8152_RXFG_HEADSZ; |
9747 | tp->rx_pending = 10 * RTL8152_MAX_RX; | |
9748 | ||
9a4be1bd | 9749 | intf->needs_remote_wakeup = 1; |
9750 | ||
9583a363 HW |
9751 | if (!rtl_can_wakeup(tp)) |
9752 | __rtl_set_wol(tp, 0); | |
9753 | else | |
9754 | tp->saved_wolopts = __rtl_get_wol(tp); | |
9755 | ||
c81229c9 | 9756 | tp->rtl_ops.init(tp); |
9370f2d0 HW |
9757 | #if IS_BUILTIN(CONFIG_USB_RTL8152) |
9758 | /* Retry in case request_firmware() is not ready yet. */ | |
9759 | tp->rtl_fw.retry = true; | |
9760 | #endif | |
a028a9e0 | 9761 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); |
776ac63a | 9762 | set_ethernet_addr(tp, false); |
ac718b69 | 9763 | |
ac718b69 | 9764 | usb_set_intfdata(intf, tp); |
195aae32 | 9765 | |
8ded532c JK |
9766 | netif_napi_add_weight(netdev, &tp->napi, r8152_poll, |
9767 | tp->support_2500full ? 256 : 64); | |
ac718b69 | 9768 | |
ebc2ec48 | 9769 | ret = register_netdev(netdev); |
9770 | if (ret != 0) { | |
156c3207 | 9771 | dev_err(&intf->dev, "couldn't register the device\n"); |
ebc2ec48 | 9772 | goto out1; |
ac718b69 | 9773 | } |
9774 | ||
21ff2e89 | 9775 | if (tp->saved_wolopts) |
9776 | device_set_wakeup_enable(&udev->dev, true); | |
9777 | else | |
9778 | device_set_wakeup_enable(&udev->dev, false); | |
9779 | ||
4a8deae2 | 9780 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 9781 | |
9782 | return 0; | |
9783 | ||
ac718b69 | 9784 | out1: |
d2187f8e | 9785 | tasklet_kill(&tp->tx_tl); |
ebc2ec48 | 9786 | usb_set_intfdata(intf, NULL); |
ac718b69 | 9787 | out: |
9788 | free_netdev(netdev); | |
ebc2ec48 | 9789 | return ret; |
ac718b69 | 9790 | } |
9791 | ||
ac718b69 | 9792 | static void rtl8152_disconnect(struct usb_interface *intf) |
9793 | { | |
9794 | struct r8152 *tp = usb_get_intfdata(intf); | |
9795 | ||
9796 | usb_set_intfdata(intf, NULL); | |
9797 | if (tp) { | |
ffa9fec3 | 9798 | rtl_set_unplug(tp); |
f561de33 | 9799 | |
ac718b69 | 9800 | unregister_netdev(tp->netdev); |
d2187f8e | 9801 | tasklet_kill(&tp->tx_tl); |
a028a9e0 | 9802 | cancel_delayed_work_sync(&tp->hw_phy_work); |
195aae32 HW |
9803 | if (tp->rtl_ops.unload) |
9804 | tp->rtl_ops.unload(tp); | |
9370f2d0 | 9805 | rtl8152_release_firmware(tp); |
ac718b69 | 9806 | free_netdev(tp->netdev); |
9807 | } | |
9808 | } | |
9809 | ||
55319eeb HW |
9810 | #define REALTEK_USB_DEVICE(vend, prod) { \ |
9811 | USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC), \ | |
d9a28c5b | 9812 | }, \ |
9813 | { \ | |
55319eeb HW |
9814 | USB_DEVICE_AND_INTERFACE_INFO(vend, prod, USB_CLASS_COMM, \ |
9815 | USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), \ | |
9816 | } | |
d9a28c5b | 9817 | |
ac718b69 | 9818 | /* table of devices that work with this driver */ |
9b4355fb | 9819 | static const struct usb_device_id rtl8152_table[] = { |
195aae32 | 9820 | /* Realtek */ |
55319eeb HW |
9821 | REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050), |
9822 | REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053), | |
9823 | REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152), | |
9824 | REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153), | |
9825 | REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155), | |
9826 | REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156), | |
195aae32 HW |
9827 | |
9828 | /* Microsoft */ | |
55319eeb HW |
9829 | REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab), |
9830 | REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6), | |
9831 | REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927), | |
9832 | REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101), | |
9833 | REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f), | |
9834 | REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062), | |
9835 | REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069), | |
9836 | REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082), | |
9837 | REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205), | |
9838 | REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c), | |
9839 | REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214), | |
9840 | REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e), | |
9841 | REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387), | |
9842 | REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041), | |
9843 | REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff), | |
9844 | REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601), | |
ac718b69 | 9845 | {} |
9846 | }; | |
9847 | ||
9848 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
9849 | ||
9850 | static struct usb_driver rtl8152_driver = { | |
9851 | .name = MODULENAME, | |
ebc2ec48 | 9852 | .id_table = rtl8152_table, |
ac718b69 | 9853 | .probe = rtl8152_probe, |
9854 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 9855 | .suspend = rtl8152_suspend, |
ebc2ec48 | 9856 | .resume = rtl8152_resume, |
7ec2541a | 9857 | .reset_resume = rtl8152_reset_resume, |
e501139a | 9858 | .pre_reset = rtl8152_pre_reset, |
9859 | .post_reset = rtl8152_post_reset, | |
9a4be1bd | 9860 | .supports_autosuspend = 1, |
a634782f | 9861 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 9862 | }; |
9863 | ||
b4236daa | 9864 | module_usb_driver(rtl8152_driver); |
ac718b69 | 9865 | |
9866 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
9867 | MODULE_DESCRIPTION(DRIVER_DESC); | |
9868 | MODULE_LICENSE("GPL"); | |
c961e877 | 9869 | MODULE_VERSION(DRIVER_VERSION); |