mei: mask interrupt set bit on clean reset bit
[linux-2.6-block.git] / drivers / net / usb / r8152.c
CommitLineData
ac718b69 1/*
c7de7dec 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
ac718b69 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
ac718b69 10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
ac718b69 13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
ebc2ec48 21#include <linux/list.h>
5bd23881 22#include <linux/ip.h>
23#include <linux/ipv6.h>
6128d1bb 24#include <net/ip6_checksum.h>
4c4a6b1b 25#include <uapi/linux/mdio.h>
26#include <linux/mdio.h>
d9a28c5b 27#include <linux/usb/cdc.h>
ac718b69 28
29/* Version Information */
b5403273 30#define DRIVER_VERSION "v1.07.0 (2014/10/09)"
ac718b69 31#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
44d942a9 32#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
ac718b69 33#define MODULENAME "r8152"
34
35#define R8152_PHY_ID 32
36
37#define PLA_IDR 0xc000
38#define PLA_RCR 0xc010
39#define PLA_RMS 0xc016
40#define PLA_RXFIFO_CTRL0 0xc0a0
41#define PLA_RXFIFO_CTRL1 0xc0a4
42#define PLA_RXFIFO_CTRL2 0xc0a8
43#define PLA_FMC 0xc0b4
44#define PLA_CFG_WOL 0xc0b6
43779f8d 45#define PLA_TEREDO_CFG 0xc0bc
ac718b69 46#define PLA_MAR 0xcd00
43779f8d 47#define PLA_BACKUP 0xd000
ac718b69 48#define PAL_BDC_CR 0xd1a0
43779f8d 49#define PLA_TEREDO_TIMER 0xd2cc
50#define PLA_REALWOW_TIMER 0xd2e8
ac718b69 51#define PLA_LEDSEL 0xdd90
52#define PLA_LED_FEATURE 0xdd92
53#define PLA_PHYAR 0xde00
43779f8d 54#define PLA_BOOT_CTRL 0xe004
ac718b69 55#define PLA_GPHY_INTR_IMR 0xe022
56#define PLA_EEE_CR 0xe040
57#define PLA_EEEP_CR 0xe080
58#define PLA_MAC_PWR_CTRL 0xe0c0
43779f8d 59#define PLA_MAC_PWR_CTRL2 0xe0ca
60#define PLA_MAC_PWR_CTRL3 0xe0cc
61#define PLA_MAC_PWR_CTRL4 0xe0ce
62#define PLA_WDT6_CTRL 0xe428
ac718b69 63#define PLA_TCR0 0xe610
64#define PLA_TCR1 0xe612
69b4b7a4 65#define PLA_MTPS 0xe615
ac718b69 66#define PLA_TXFIFO_CTRL 0xe618
4f1d4d54 67#define PLA_RSTTALLY 0xe800
ac718b69 68#define PLA_CR 0xe813
69#define PLA_CRWECR 0xe81c
21ff2e89 70#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
71#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
ac718b69 72#define PLA_CONFIG5 0xe822
73#define PLA_PHY_PWR 0xe84c
74#define PLA_OOB_CTRL 0xe84f
75#define PLA_CPCR 0xe854
76#define PLA_MISC_0 0xe858
77#define PLA_MISC_1 0xe85a
78#define PLA_OCP_GPHY_BASE 0xe86c
4f1d4d54 79#define PLA_TALLYCNT 0xe890
ac718b69 80#define PLA_SFF_STS_7 0xe8de
81#define PLA_PHYSTATUS 0xe908
82#define PLA_BP_BA 0xfc26
83#define PLA_BP_0 0xfc28
84#define PLA_BP_1 0xfc2a
85#define PLA_BP_2 0xfc2c
86#define PLA_BP_3 0xfc2e
87#define PLA_BP_4 0xfc30
88#define PLA_BP_5 0xfc32
89#define PLA_BP_6 0xfc34
90#define PLA_BP_7 0xfc36
43779f8d 91#define PLA_BP_EN 0xfc38
ac718b69 92
43779f8d 93#define USB_U2P3_CTRL 0xb460
ac718b69 94#define USB_DEV_STAT 0xb808
95#define USB_USB_CTRL 0xd406
96#define USB_PHY_CTRL 0xd408
97#define USB_TX_AGG 0xd40a
98#define USB_RX_BUF_TH 0xd40c
99#define USB_USB_TIMER 0xd428
43779f8d 100#define USB_RX_EARLY_AGG 0xd42c
ac718b69 101#define USB_PM_CTRL_STATUS 0xd432
102#define USB_TX_DMA 0xd434
43779f8d 103#define USB_TOLERANCE 0xd490
104#define USB_LPM_CTRL 0xd41a
ac718b69 105#define USB_UPS_CTRL 0xd800
43779f8d 106#define USB_MISC_0 0xd81a
107#define USB_POWER_CUT 0xd80a
108#define USB_AFE_CTRL2 0xd824
109#define USB_WDT11_CTRL 0xe43c
ac718b69 110#define USB_BP_BA 0xfc26
111#define USB_BP_0 0xfc28
112#define USB_BP_1 0xfc2a
113#define USB_BP_2 0xfc2c
114#define USB_BP_3 0xfc2e
115#define USB_BP_4 0xfc30
116#define USB_BP_5 0xfc32
117#define USB_BP_6 0xfc34
118#define USB_BP_7 0xfc36
43779f8d 119#define USB_BP_EN 0xfc38
ac718b69 120
121/* OCP Registers */
122#define OCP_ALDPS_CONFIG 0x2010
123#define OCP_EEE_CONFIG1 0x2080
124#define OCP_EEE_CONFIG2 0x2092
125#define OCP_EEE_CONFIG3 0x2094
ac244d3e 126#define OCP_BASE_MII 0xa400
ac718b69 127#define OCP_EEE_AR 0xa41a
128#define OCP_EEE_DATA 0xa41c
43779f8d 129#define OCP_PHY_STATUS 0xa420
130#define OCP_POWER_CFG 0xa430
131#define OCP_EEE_CFG 0xa432
132#define OCP_SRAM_ADDR 0xa436
133#define OCP_SRAM_DATA 0xa438
134#define OCP_DOWN_SPEED 0xa442
df35d283 135#define OCP_EEE_ABLE 0xa5c4
4c4a6b1b 136#define OCP_EEE_ADV 0xa5d0
df35d283 137#define OCP_EEE_LPABLE 0xa5d2
43779f8d 138#define OCP_ADC_CFG 0xbc06
139
140/* SRAM Register */
141#define SRAM_LPF_CFG 0x8012
142#define SRAM_10M_AMP1 0x8080
143#define SRAM_10M_AMP2 0x8082
144#define SRAM_IMPEDANCE 0x8084
ac718b69 145
146/* PLA_RCR */
147#define RCR_AAP 0x00000001
148#define RCR_APM 0x00000002
149#define RCR_AM 0x00000004
150#define RCR_AB 0x00000008
151#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
152
153/* PLA_RXFIFO_CTRL0 */
154#define RXFIFO_THR1_NORMAL 0x00080002
155#define RXFIFO_THR1_OOB 0x01800003
156
157/* PLA_RXFIFO_CTRL1 */
158#define RXFIFO_THR2_FULL 0x00000060
159#define RXFIFO_THR2_HIGH 0x00000038
160#define RXFIFO_THR2_OOB 0x0000004a
43779f8d 161#define RXFIFO_THR2_NORMAL 0x00a0
ac718b69 162
163/* PLA_RXFIFO_CTRL2 */
164#define RXFIFO_THR3_FULL 0x00000078
165#define RXFIFO_THR3_HIGH 0x00000048
166#define RXFIFO_THR3_OOB 0x0000005a
43779f8d 167#define RXFIFO_THR3_NORMAL 0x0110
ac718b69 168
169/* PLA_TXFIFO_CTRL */
170#define TXFIFO_THR_NORMAL 0x00400008
43779f8d 171#define TXFIFO_THR_NORMAL2 0x01000008
ac718b69 172
173/* PLA_FMC */
174#define FMC_FCR_MCU_EN 0x0001
175
176/* PLA_EEEP_CR */
177#define EEEP_CR_EEEP_TX 0x0002
178
43779f8d 179/* PLA_WDT6_CTRL */
180#define WDT6_SET_MODE 0x0010
181
ac718b69 182/* PLA_TCR0 */
183#define TCR0_TX_EMPTY 0x0800
184#define TCR0_AUTO_FIFO 0x0080
185
186/* PLA_TCR1 */
187#define VERSION_MASK 0x7cf0
188
69b4b7a4 189/* PLA_MTPS */
190#define MTPS_JUMBO (12 * 1024 / 64)
191#define MTPS_DEFAULT (6 * 1024 / 64)
192
4f1d4d54 193/* PLA_RSTTALLY */
194#define TALLY_RESET 0x0001
195
ac718b69 196/* PLA_CR */
197#define CR_RST 0x10
198#define CR_RE 0x08
199#define CR_TE 0x04
200
201/* PLA_CRWECR */
202#define CRWECR_NORAML 0x00
203#define CRWECR_CONFIG 0xc0
204
205/* PLA_OOB_CTRL */
206#define NOW_IS_OOB 0x80
207#define TXFIFO_EMPTY 0x20
208#define RXFIFO_EMPTY 0x10
209#define LINK_LIST_READY 0x02
210#define DIS_MCU_CLROOB 0x01
211#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
212
213/* PLA_MISC_1 */
214#define RXDY_GATED_EN 0x0008
215
216/* PLA_SFF_STS_7 */
217#define RE_INIT_LL 0x8000
218#define MCU_BORW_EN 0x4000
219
220/* PLA_CPCR */
221#define CPCR_RX_VLAN 0x0040
222
223/* PLA_CFG_WOL */
224#define MAGIC_EN 0x0001
225
43779f8d 226/* PLA_TEREDO_CFG */
227#define TEREDO_SEL 0x8000
228#define TEREDO_WAKE_MASK 0x7f00
229#define TEREDO_RS_EVENT_MASK 0x00fe
230#define OOB_TEREDO_EN 0x0001
231
ac718b69 232/* PAL_BDC_CR */
233#define ALDPS_PROXY_MODE 0x0001
234
21ff2e89 235/* PLA_CONFIG34 */
236#define LINK_ON_WAKE_EN 0x0010
237#define LINK_OFF_WAKE_EN 0x0008
238
ac718b69 239/* PLA_CONFIG5 */
21ff2e89 240#define BWF_EN 0x0040
241#define MWF_EN 0x0020
242#define UWF_EN 0x0010
ac718b69 243#define LAN_WAKE_EN 0x0002
244
245/* PLA_LED_FEATURE */
246#define LED_MODE_MASK 0x0700
247
248/* PLA_PHY_PWR */
249#define TX_10M_IDLE_EN 0x0080
250#define PFM_PWM_SWITCH 0x0040
251
252/* PLA_MAC_PWR_CTRL */
253#define D3_CLK_GATED_EN 0x00004000
254#define MCU_CLK_RATIO 0x07010f07
255#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
43779f8d 256#define ALDPS_SPDWN_RATIO 0x0f87
257
258/* PLA_MAC_PWR_CTRL2 */
259#define EEE_SPDWN_RATIO 0x8007
260
261/* PLA_MAC_PWR_CTRL3 */
262#define PKT_AVAIL_SPDWN_EN 0x0100
263#define SUSPEND_SPDWN_EN 0x0004
264#define U1U2_SPDWN_EN 0x0002
265#define L1_SPDWN_EN 0x0001
266
267/* PLA_MAC_PWR_CTRL4 */
268#define PWRSAVE_SPDWN_EN 0x1000
269#define RXDV_SPDWN_EN 0x0800
270#define TX10MIDLE_EN 0x0100
271#define TP100_SPDWN_EN 0x0020
272#define TP500_SPDWN_EN 0x0010
273#define TP1000_SPDWN_EN 0x0008
274#define EEE_SPDWN_EN 0x0001
ac718b69 275
276/* PLA_GPHY_INTR_IMR */
277#define GPHY_STS_MSK 0x0001
278#define SPEED_DOWN_MSK 0x0002
279#define SPDWN_RXDV_MSK 0x0004
280#define SPDWN_LINKCHG_MSK 0x0008
281
282/* PLA_PHYAR */
283#define PHYAR_FLAG 0x80000000
284
285/* PLA_EEE_CR */
286#define EEE_RX_EN 0x0001
287#define EEE_TX_EN 0x0002
288
43779f8d 289/* PLA_BOOT_CTRL */
290#define AUTOLOAD_DONE 0x0002
291
ac718b69 292/* USB_DEV_STAT */
293#define STAT_SPEED_MASK 0x0006
294#define STAT_SPEED_HIGH 0x0000
a3cc465d 295#define STAT_SPEED_FULL 0x0002
ac718b69 296
297/* USB_TX_AGG */
298#define TX_AGG_MAX_THRESHOLD 0x03
299
300/* USB_RX_BUF_TH */
43779f8d 301#define RX_THR_SUPPER 0x0c350180
8e1f51bd 302#define RX_THR_HIGH 0x7a120180
43779f8d 303#define RX_THR_SLOW 0xffff0180
ac718b69 304
305/* USB_TX_DMA */
306#define TEST_MODE_DISABLE 0x00000001
307#define TX_SIZE_ADJUST1 0x00000100
308
309/* USB_UPS_CTRL */
310#define POWER_CUT 0x0100
311
312/* USB_PM_CTRL_STATUS */
8e1f51bd 313#define RESUME_INDICATE 0x0001
ac718b69 314
315/* USB_USB_CTRL */
316#define RX_AGG_DISABLE 0x0010
317
43779f8d 318/* USB_U2P3_CTRL */
319#define U2P3_ENABLE 0x0001
320
321/* USB_POWER_CUT */
322#define PWR_EN 0x0001
323#define PHASE2_EN 0x0008
324
325/* USB_MISC_0 */
326#define PCUT_STATUS 0x0001
327
328/* USB_RX_EARLY_AGG */
329#define EARLY_AGG_SUPPER 0x0e832981
330#define EARLY_AGG_HIGH 0x0e837a12
331#define EARLY_AGG_SLOW 0x0e83ffff
332
333/* USB_WDT11_CTRL */
334#define TIMER11_EN 0x0001
335
336/* USB_LPM_CTRL */
337#define LPM_TIMER_MASK 0x0c
338#define LPM_TIMER_500MS 0x04 /* 500 ms */
339#define LPM_TIMER_500US 0x0c /* 500 us */
340
341/* USB_AFE_CTRL2 */
342#define SEN_VAL_MASK 0xf800
343#define SEN_VAL_NORMAL 0xa000
344#define SEL_RXIDLE 0x0100
345
ac718b69 346/* OCP_ALDPS_CONFIG */
347#define ENPWRSAVE 0x8000
348#define ENPDNPS 0x0200
349#define LINKENA 0x0100
350#define DIS_SDSAVE 0x0010
351
43779f8d 352/* OCP_PHY_STATUS */
353#define PHY_STAT_MASK 0x0007
354#define PHY_STAT_LAN_ON 3
355#define PHY_STAT_PWRDN 5
356
357/* OCP_POWER_CFG */
358#define EEE_CLKDIV_EN 0x8000
359#define EN_ALDPS 0x0004
360#define EN_10M_PLLOFF 0x0001
361
ac718b69 362/* OCP_EEE_CONFIG1 */
363#define RG_TXLPI_MSK_HFDUP 0x8000
364#define RG_MATCLR_EN 0x4000
365#define EEE_10_CAP 0x2000
366#define EEE_NWAY_EN 0x1000
367#define TX_QUIET_EN 0x0200
368#define RX_QUIET_EN 0x0100
d24f6134 369#define sd_rise_time_mask 0x0070
4c4a6b1b 370#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
ac718b69 371#define RG_RXLPI_MSK_HFDUP 0x0008
372#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
373
374/* OCP_EEE_CONFIG2 */
375#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
376#define RG_DACQUIET_EN 0x0400
377#define RG_LDVQUIET_EN 0x0200
378#define RG_CKRSEL 0x0020
379#define RG_EEEPRG_EN 0x0010
380
381/* OCP_EEE_CONFIG3 */
d24f6134 382#define fast_snr_mask 0xff80
4c4a6b1b 383#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
ac718b69 384#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
385#define MSK_PH 0x0006 /* bit 0 ~ 3 */
386
387/* OCP_EEE_AR */
388/* bit[15:14] function */
389#define FUN_ADDR 0x0000
390#define FUN_DATA 0x4000
391/* bit[4:0] device addr */
ac718b69 392
43779f8d 393/* OCP_EEE_CFG */
394#define CTAP_SHORT_EN 0x0040
395#define EEE10_EN 0x0010
396
397/* OCP_DOWN_SPEED */
398#define EN_10M_BGOFF 0x0080
399
43779f8d 400/* OCP_ADC_CFG */
401#define CKADSEL_L 0x0100
402#define ADC_EN 0x0080
403#define EN_EMI_L 0x0040
404
405/* SRAM_LPF_CFG */
406#define LPF_AUTO_TUNE 0x8000
407
408/* SRAM_10M_AMP1 */
409#define GDAC_IB_UPALL 0x0008
410
411/* SRAM_10M_AMP2 */
412#define AMP_DN 0x0200
413
414/* SRAM_IMPEDANCE */
415#define RX_DRIVING_MASK 0x6000
416
ac718b69 417enum rtl_register_content {
43779f8d 418 _1000bps = 0x10,
ac718b69 419 _100bps = 0x08,
420 _10bps = 0x04,
421 LINK_STATUS = 0x02,
422 FULL_DUP = 0x01,
423};
424
1764bcd9 425#define RTL8152_MAX_TX 4
ebc2ec48 426#define RTL8152_MAX_RX 10
40a82917 427#define INTBUFSIZE 2
8e1f51bd 428#define CRC_SIZE 4
429#define TX_ALIGN 4
430#define RX_ALIGN 8
40a82917 431
432#define INTR_LINK 0x0004
ebc2ec48 433
ac718b69 434#define RTL8152_REQT_READ 0xc0
435#define RTL8152_REQT_WRITE 0x40
436#define RTL8152_REQ_GET_REGS 0x05
437#define RTL8152_REQ_SET_REGS 0x05
438
439#define BYTE_EN_DWORD 0xff
440#define BYTE_EN_WORD 0x33
441#define BYTE_EN_BYTE 0x11
442#define BYTE_EN_SIX_BYTES 0x3f
443#define BYTE_EN_START_MASK 0x0f
444#define BYTE_EN_END_MASK 0xf0
445
69b4b7a4 446#define RTL8153_MAX_PACKET 9216 /* 9K */
447#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
ac718b69 448#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
69b4b7a4 449#define RTL8153_RMS RTL8153_MAX_PACKET
b8125404 450#define RTL8152_TX_TIMEOUT (5 * HZ)
ac718b69 451
452/* rtl8152 flags */
453enum rtl8152_flags {
454 RTL8152_UNPLUG = 0,
ac718b69 455 RTL8152_SET_RX_MODE,
40a82917 456 WORK_ENABLE,
457 RTL8152_LINK_CHG,
9a4be1bd 458 SELECTIVE_SUSPEND,
aa66a5f1 459 PHY_RESET,
0c3121fc 460 SCHEDULE_TASKLET,
ac718b69 461};
462
463/* Define these values to match your device */
464#define VENDOR_ID_REALTEK 0x0bda
43779f8d 465#define VENDOR_ID_SAMSUNG 0x04e8
ac718b69 466
467#define MCU_TYPE_PLA 0x0100
468#define MCU_TYPE_USB 0x0000
469
4f1d4d54 470struct tally_counter {
471 __le64 tx_packets;
472 __le64 rx_packets;
473 __le64 tx_errors;
474 __le32 rx_errors;
475 __le16 rx_missed;
476 __le16 align_errors;
477 __le32 tx_one_collision;
478 __le32 tx_multi_collision;
479 __le64 rx_unicast;
480 __le64 rx_broadcast;
481 __le32 rx_multicast;
482 __le16 tx_aborted;
f37119c5 483 __le16 tx_underrun;
4f1d4d54 484};
485
ac718b69 486struct rx_desc {
500b6d7e 487 __le32 opts1;
ac718b69 488#define RX_LEN_MASK 0x7fff
565cab0a 489
500b6d7e 490 __le32 opts2;
565cab0a 491#define RD_UDP_CS (1 << 23)
492#define RD_TCP_CS (1 << 22)
6128d1bb 493#define RD_IPV6_CS (1 << 20)
565cab0a 494#define RD_IPV4_CS (1 << 19)
495
500b6d7e 496 __le32 opts3;
565cab0a 497#define IPF (1 << 23) /* IP checksum fail */
498#define UDPF (1 << 22) /* UDP checksum fail */
499#define TCPF (1 << 21) /* TCP checksum fail */
c5554298 500#define RX_VLAN_TAG (1 << 16)
565cab0a 501
500b6d7e 502 __le32 opts4;
503 __le32 opts5;
504 __le32 opts6;
ac718b69 505};
506
507struct tx_desc {
500b6d7e 508 __le32 opts1;
ac718b69 509#define TX_FS (1 << 31) /* First segment of a packet */
510#define TX_LS (1 << 30) /* Final segment of a packet */
60c89071 511#define GTSENDV4 (1 << 28)
6128d1bb 512#define GTSENDV6 (1 << 27)
60c89071 513#define GTTCPHO_SHIFT 18
6128d1bb 514#define GTTCPHO_MAX 0x7fU
60c89071 515#define TX_LEN_MAX 0x3ffffU
5bd23881 516
500b6d7e 517 __le32 opts2;
5bd23881 518#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
519#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
520#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
521#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
60c89071 522#define MSS_SHIFT 17
523#define MSS_MAX 0x7ffU
524#define TCPHO_SHIFT 17
6128d1bb 525#define TCPHO_MAX 0x7ffU
c5554298 526#define TX_VLAN_TAG (1 << 16)
ac718b69 527};
528
dff4e8ad 529struct r8152;
530
ebc2ec48 531struct rx_agg {
532 struct list_head list;
533 struct urb *urb;
dff4e8ad 534 struct r8152 *context;
ebc2ec48 535 void *buffer;
536 void *head;
537};
538
539struct tx_agg {
540 struct list_head list;
541 struct urb *urb;
dff4e8ad 542 struct r8152 *context;
ebc2ec48 543 void *buffer;
544 void *head;
545 u32 skb_num;
546 u32 skb_len;
547};
548
ac718b69 549struct r8152 {
550 unsigned long flags;
551 struct usb_device *udev;
552 struct tasklet_struct tl;
40a82917 553 struct usb_interface *intf;
ac718b69 554 struct net_device *netdev;
40a82917 555 struct urb *intr_urb;
ebc2ec48 556 struct tx_agg tx_info[RTL8152_MAX_TX];
557 struct rx_agg rx_info[RTL8152_MAX_RX];
558 struct list_head rx_done, tx_free;
559 struct sk_buff_head tx_queue;
560 spinlock_t rx_lock, tx_lock;
ac718b69 561 struct delayed_work schedule;
562 struct mii_if_info mii;
b5403273 563 struct mutex control; /* use for hw setting */
c81229c9 564
565 struct rtl_ops {
566 void (*init)(struct r8152 *);
567 int (*enable)(struct r8152 *);
568 void (*disable)(struct r8152 *);
7e9da481 569 void (*up)(struct r8152 *);
c81229c9 570 void (*down)(struct r8152 *);
571 void (*unload)(struct r8152 *);
df35d283 572 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
573 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
c81229c9 574 } rtl_ops;
575
40a82917 576 int intr_interval;
21ff2e89 577 u32 saved_wolopts;
ac718b69 578 u32 msg_enable;
dd1b119c 579 u32 tx_qlen;
ac718b69 580 u16 ocp_base;
40a82917 581 u8 *intr_buff;
ac718b69 582 u8 version;
583 u8 speed;
584};
585
586enum rtl_version {
587 RTL_VER_UNKNOWN = 0,
588 RTL_VER_01,
43779f8d 589 RTL_VER_02,
590 RTL_VER_03,
591 RTL_VER_04,
592 RTL_VER_05,
593 RTL_VER_MAX
ac718b69 594};
595
60c89071 596enum tx_csum_stat {
597 TX_CSUM_SUCCESS = 0,
598 TX_CSUM_TSO,
599 TX_CSUM_NONE
600};
601
ac718b69 602/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
603 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
604 */
605static const int multicast_filter_limit = 32;
52aec126 606static unsigned int agg_buf_sz = 16384;
ac718b69 607
52aec126 608#define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
60c89071 609 VLAN_ETH_HLEN - VLAN_HLEN)
610
ac718b69 611static
612int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
613{
31787f53 614 int ret;
615 void *tmp;
616
617 tmp = kmalloc(size, GFP_KERNEL);
618 if (!tmp)
619 return -ENOMEM;
620
621 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
b209af99 622 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
623 value, index, tmp, size, 500);
31787f53 624
625 memcpy(data, tmp, size);
626 kfree(tmp);
627
628 return ret;
ac718b69 629}
630
631static
632int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
633{
31787f53 634 int ret;
635 void *tmp;
636
c4438f03 637 tmp = kmemdup(data, size, GFP_KERNEL);
31787f53 638 if (!tmp)
639 return -ENOMEM;
640
31787f53 641 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
b209af99 642 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
643 value, index, tmp, size, 500);
31787f53 644
645 kfree(tmp);
db8515ef 646
31787f53 647 return ret;
ac718b69 648}
649
650static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
b209af99 651 void *data, u16 type)
ac718b69 652{
45f4a19f 653 u16 limit = 64;
654 int ret = 0;
ac718b69 655
656 if (test_bit(RTL8152_UNPLUG, &tp->flags))
657 return -ENODEV;
658
659 /* both size and indix must be 4 bytes align */
660 if ((size & 3) || !size || (index & 3) || !data)
661 return -EPERM;
662
663 if ((u32)index + (u32)size > 0xffff)
664 return -EPERM;
665
666 while (size) {
667 if (size > limit) {
668 ret = get_registers(tp, index, type, limit, data);
669 if (ret < 0)
670 break;
671
672 index += limit;
673 data += limit;
674 size -= limit;
675 } else {
676 ret = get_registers(tp, index, type, size, data);
677 if (ret < 0)
678 break;
679
680 index += size;
681 data += size;
682 size = 0;
683 break;
684 }
685 }
686
67610496 687 if (ret == -ENODEV)
688 set_bit(RTL8152_UNPLUG, &tp->flags);
689
ac718b69 690 return ret;
691}
692
693static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
b209af99 694 u16 size, void *data, u16 type)
ac718b69 695{
45f4a19f 696 int ret;
697 u16 byteen_start, byteen_end, byen;
698 u16 limit = 512;
ac718b69 699
700 if (test_bit(RTL8152_UNPLUG, &tp->flags))
701 return -ENODEV;
702
703 /* both size and indix must be 4 bytes align */
704 if ((size & 3) || !size || (index & 3) || !data)
705 return -EPERM;
706
707 if ((u32)index + (u32)size > 0xffff)
708 return -EPERM;
709
710 byteen_start = byteen & BYTE_EN_START_MASK;
711 byteen_end = byteen & BYTE_EN_END_MASK;
712
713 byen = byteen_start | (byteen_start << 4);
714 ret = set_registers(tp, index, type | byen, 4, data);
715 if (ret < 0)
716 goto error1;
717
718 index += 4;
719 data += 4;
720 size -= 4;
721
722 if (size) {
723 size -= 4;
724
725 while (size) {
726 if (size > limit) {
727 ret = set_registers(tp, index,
b209af99 728 type | BYTE_EN_DWORD,
729 limit, data);
ac718b69 730 if (ret < 0)
731 goto error1;
732
733 index += limit;
734 data += limit;
735 size -= limit;
736 } else {
737 ret = set_registers(tp, index,
b209af99 738 type | BYTE_EN_DWORD,
739 size, data);
ac718b69 740 if (ret < 0)
741 goto error1;
742
743 index += size;
744 data += size;
745 size = 0;
746 break;
747 }
748 }
749
750 byen = byteen_end | (byteen_end >> 4);
751 ret = set_registers(tp, index, type | byen, 4, data);
752 if (ret < 0)
753 goto error1;
754 }
755
756error1:
67610496 757 if (ret == -ENODEV)
758 set_bit(RTL8152_UNPLUG, &tp->flags);
759
ac718b69 760 return ret;
761}
762
763static inline
764int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
765{
766 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
767}
768
769static inline
770int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
771{
772 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
773}
774
775static inline
776int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
777{
778 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
779}
780
781static inline
782int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
783{
784 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
785}
786
787static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
788{
c8826de8 789 __le32 data;
ac718b69 790
c8826de8 791 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 792
793 return __le32_to_cpu(data);
794}
795
796static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
797{
c8826de8 798 __le32 tmp = __cpu_to_le32(data);
799
800 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 801}
802
803static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
804{
805 u32 data;
c8826de8 806 __le32 tmp;
ac718b69 807 u8 shift = index & 2;
808
809 index &= ~3;
810
c8826de8 811 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 812
c8826de8 813 data = __le32_to_cpu(tmp);
ac718b69 814 data >>= (shift * 8);
815 data &= 0xffff;
816
817 return (u16)data;
818}
819
820static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
821{
c8826de8 822 u32 mask = 0xffff;
823 __le32 tmp;
ac718b69 824 u16 byen = BYTE_EN_WORD;
825 u8 shift = index & 2;
826
827 data &= mask;
828
829 if (index & 2) {
830 byen <<= shift;
831 mask <<= (shift * 8);
832 data <<= (shift * 8);
833 index &= ~3;
834 }
835
c8826de8 836 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 837
c8826de8 838 data |= __le32_to_cpu(tmp) & ~mask;
839 tmp = __cpu_to_le32(data);
ac718b69 840
c8826de8 841 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 842}
843
844static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
845{
846 u32 data;
c8826de8 847 __le32 tmp;
ac718b69 848 u8 shift = index & 3;
849
850 index &= ~3;
851
c8826de8 852 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 853
c8826de8 854 data = __le32_to_cpu(tmp);
ac718b69 855 data >>= (shift * 8);
856 data &= 0xff;
857
858 return (u8)data;
859}
860
861static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
862{
c8826de8 863 u32 mask = 0xff;
864 __le32 tmp;
ac718b69 865 u16 byen = BYTE_EN_BYTE;
866 u8 shift = index & 3;
867
868 data &= mask;
869
870 if (index & 3) {
871 byen <<= shift;
872 mask <<= (shift * 8);
873 data <<= (shift * 8);
874 index &= ~3;
875 }
876
c8826de8 877 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 878
c8826de8 879 data |= __le32_to_cpu(tmp) & ~mask;
880 tmp = __cpu_to_le32(data);
ac718b69 881
c8826de8 882 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 883}
884
ac244d3e 885static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 886{
887 u16 ocp_base, ocp_index;
888
889 ocp_base = addr & 0xf000;
890 if (ocp_base != tp->ocp_base) {
891 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
892 tp->ocp_base = ocp_base;
893 }
894
895 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 896 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 897}
898
ac244d3e 899static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 900{
ac244d3e 901 u16 ocp_base, ocp_index;
ac718b69 902
ac244d3e 903 ocp_base = addr & 0xf000;
904 if (ocp_base != tp->ocp_base) {
905 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
906 tp->ocp_base = ocp_base;
ac718b69 907 }
ac244d3e 908
909 ocp_index = (addr & 0x0fff) | 0xb000;
910 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 911}
912
ac244d3e 913static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 914{
ac244d3e 915 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
916}
ac718b69 917
ac244d3e 918static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
919{
920 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 921}
922
43779f8d 923static void sram_write(struct r8152 *tp, u16 addr, u16 data)
924{
925 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
926 ocp_reg_write(tp, OCP_SRAM_DATA, data);
927}
928
929static u16 sram_read(struct r8152 *tp, u16 addr)
930{
931 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
932 return ocp_reg_read(tp, OCP_SRAM_DATA);
933}
934
ac718b69 935static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
936{
937 struct r8152 *tp = netdev_priv(netdev);
9a4be1bd 938 int ret;
ac718b69 939
6871438c 940 if (test_bit(RTL8152_UNPLUG, &tp->flags))
941 return -ENODEV;
942
ac718b69 943 if (phy_id != R8152_PHY_ID)
944 return -EINVAL;
945
9a4be1bd 946 ret = r8152_mdio_read(tp, reg);
947
9a4be1bd 948 return ret;
ac718b69 949}
950
951static
952void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
953{
954 struct r8152 *tp = netdev_priv(netdev);
955
6871438c 956 if (test_bit(RTL8152_UNPLUG, &tp->flags))
957 return;
958
ac718b69 959 if (phy_id != R8152_PHY_ID)
960 return;
961
962 r8152_mdio_write(tp, reg, val);
963}
964
b209af99 965static int
966r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
ebc2ec48 967
8ba789ab 968static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
969{
970 struct r8152 *tp = netdev_priv(netdev);
971 struct sockaddr *addr = p;
ea6a7112 972 int ret = -EADDRNOTAVAIL;
8ba789ab 973
974 if (!is_valid_ether_addr(addr->sa_data))
ea6a7112 975 goto out1;
976
977 ret = usb_autopm_get_interface(tp->intf);
978 if (ret < 0)
979 goto out1;
8ba789ab 980
b5403273 981 mutex_lock(&tp->control);
982
8ba789ab 983 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
984
985 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
986 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
987 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
988
b5403273 989 mutex_unlock(&tp->control);
990
ea6a7112 991 usb_autopm_put_interface(tp->intf);
992out1:
993 return ret;
8ba789ab 994}
995
179bb6d7 996static int set_ethernet_addr(struct r8152 *tp)
ac718b69 997{
998 struct net_device *dev = tp->netdev;
179bb6d7 999 struct sockaddr sa;
8a91c824 1000 int ret;
ac718b69 1001
8a91c824 1002 if (tp->version == RTL_VER_01)
179bb6d7 1003 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
8a91c824 1004 else
179bb6d7 1005 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
8a91c824 1006
1007 if (ret < 0) {
179bb6d7 1008 netif_err(tp, probe, dev, "Get ether addr fail\n");
1009 } else if (!is_valid_ether_addr(sa.sa_data)) {
1010 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1011 sa.sa_data);
1012 eth_hw_addr_random(dev);
1013 ether_addr_copy(sa.sa_data, dev->dev_addr);
1014 ret = rtl8152_set_mac_address(dev, &sa);
1015 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1016 sa.sa_data);
8a91c824 1017 } else {
179bb6d7 1018 if (tp->version == RTL_VER_01)
1019 ether_addr_copy(dev->dev_addr, sa.sa_data);
1020 else
1021 ret = rtl8152_set_mac_address(dev, &sa);
ac718b69 1022 }
179bb6d7 1023
1024 return ret;
ac718b69 1025}
1026
ac718b69 1027static void read_bulk_callback(struct urb *urb)
1028{
ac718b69 1029 struct net_device *netdev;
ac718b69 1030 int status = urb->status;
ebc2ec48 1031 struct rx_agg *agg;
1032 struct r8152 *tp;
ac718b69 1033
ebc2ec48 1034 agg = urb->context;
1035 if (!agg)
1036 return;
1037
1038 tp = agg->context;
ac718b69 1039 if (!tp)
1040 return;
ebc2ec48 1041
ac718b69 1042 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1043 return;
ebc2ec48 1044
1045 if (!test_bit(WORK_ENABLE, &tp->flags))
1046 return;
1047
ac718b69 1048 netdev = tp->netdev;
7559fb2f 1049
1050 /* When link down, the driver would cancel all bulks. */
1051 /* This avoid the re-submitting bulk */
ebc2ec48 1052 if (!netif_carrier_ok(netdev))
ac718b69 1053 return;
1054
9a4be1bd 1055 usb_mark_last_busy(tp->udev);
1056
ac718b69 1057 switch (status) {
1058 case 0:
ebc2ec48 1059 if (urb->actual_length < ETH_ZLEN)
1060 break;
1061
2685d410 1062 spin_lock(&tp->rx_lock);
ebc2ec48 1063 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1064 spin_unlock(&tp->rx_lock);
ebc2ec48 1065 tasklet_schedule(&tp->tl);
1066 return;
ac718b69 1067 case -ESHUTDOWN:
1068 set_bit(RTL8152_UNPLUG, &tp->flags);
1069 netif_device_detach(tp->netdev);
ebc2ec48 1070 return;
ac718b69 1071 case -ENOENT:
1072 return; /* the urb is in unlink state */
1073 case -ETIME:
4a8deae2
HW
1074 if (net_ratelimit())
1075 netdev_warn(netdev, "maybe reset is needed?\n");
ebc2ec48 1076 break;
ac718b69 1077 default:
4a8deae2
HW
1078 if (net_ratelimit())
1079 netdev_warn(netdev, "Rx status %d\n", status);
ebc2ec48 1080 break;
ac718b69 1081 }
1082
a0fccd48 1083 r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 1084}
1085
ebc2ec48 1086static void write_bulk_callback(struct urb *urb)
ac718b69 1087{
ebc2ec48 1088 struct net_device_stats *stats;
d104eafa 1089 struct net_device *netdev;
ebc2ec48 1090 struct tx_agg *agg;
ac718b69 1091 struct r8152 *tp;
ebc2ec48 1092 int status = urb->status;
ac718b69 1093
ebc2ec48 1094 agg = urb->context;
1095 if (!agg)
ac718b69 1096 return;
1097
ebc2ec48 1098 tp = agg->context;
1099 if (!tp)
1100 return;
1101
d104eafa 1102 netdev = tp->netdev;
05e0f1aa 1103 stats = &netdev->stats;
ebc2ec48 1104 if (status) {
4a8deae2 1105 if (net_ratelimit())
d104eafa 1106 netdev_warn(netdev, "Tx status %d\n", status);
ebc2ec48 1107 stats->tx_errors += agg->skb_num;
ac718b69 1108 } else {
ebc2ec48 1109 stats->tx_packets += agg->skb_num;
1110 stats->tx_bytes += agg->skb_len;
ac718b69 1111 }
1112
2685d410 1113 spin_lock(&tp->tx_lock);
ebc2ec48 1114 list_add_tail(&agg->list, &tp->tx_free);
2685d410 1115 spin_unlock(&tp->tx_lock);
ebc2ec48 1116
9a4be1bd 1117 usb_autopm_put_interface_async(tp->intf);
1118
d104eafa 1119 if (!netif_carrier_ok(netdev))
ebc2ec48 1120 return;
1121
1122 if (!test_bit(WORK_ENABLE, &tp->flags))
1123 return;
1124
1125 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1126 return;
1127
1128 if (!skb_queue_empty(&tp->tx_queue))
0c3121fc 1129 tasklet_schedule(&tp->tl);
ac718b69 1130}
1131
40a82917 1132static void intr_callback(struct urb *urb)
1133{
1134 struct r8152 *tp;
500b6d7e 1135 __le16 *d;
40a82917 1136 int status = urb->status;
1137 int res;
1138
1139 tp = urb->context;
1140 if (!tp)
1141 return;
1142
1143 if (!test_bit(WORK_ENABLE, &tp->flags))
1144 return;
1145
1146 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1147 return;
1148
1149 switch (status) {
1150 case 0: /* success */
1151 break;
1152 case -ECONNRESET: /* unlink */
1153 case -ESHUTDOWN:
1154 netif_device_detach(tp->netdev);
1155 case -ENOENT:
d59c876d 1156 case -EPROTO:
1157 netif_info(tp, intr, tp->netdev,
1158 "Stop submitting intr, status %d\n", status);
40a82917 1159 return;
1160 case -EOVERFLOW:
1161 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1162 goto resubmit;
1163 /* -EPIPE: should clear the halt */
1164 default:
1165 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1166 goto resubmit;
1167 }
1168
1169 d = urb->transfer_buffer;
1170 if (INTR_LINK & __le16_to_cpu(d[0])) {
1171 if (!(tp->speed & LINK_STATUS)) {
1172 set_bit(RTL8152_LINK_CHG, &tp->flags);
1173 schedule_delayed_work(&tp->schedule, 0);
1174 }
1175 } else {
1176 if (tp->speed & LINK_STATUS) {
1177 set_bit(RTL8152_LINK_CHG, &tp->flags);
1178 schedule_delayed_work(&tp->schedule, 0);
1179 }
1180 }
1181
1182resubmit:
1183 res = usb_submit_urb(urb, GFP_ATOMIC);
67610496 1184 if (res == -ENODEV) {
1185 set_bit(RTL8152_UNPLUG, &tp->flags);
40a82917 1186 netif_device_detach(tp->netdev);
67610496 1187 } else if (res) {
40a82917 1188 netif_err(tp, intr, tp->netdev,
4a8deae2 1189 "can't resubmit intr, status %d\n", res);
67610496 1190 }
40a82917 1191}
1192
ebc2ec48 1193static inline void *rx_agg_align(void *data)
1194{
8e1f51bd 1195 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 1196}
1197
1198static inline void *tx_agg_align(void *data)
1199{
8e1f51bd 1200 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 1201}
1202
1203static void free_all_mem(struct r8152 *tp)
1204{
1205 int i;
1206
1207 for (i = 0; i < RTL8152_MAX_RX; i++) {
9629e3c0 1208 usb_free_urb(tp->rx_info[i].urb);
1209 tp->rx_info[i].urb = NULL;
ebc2ec48 1210
9629e3c0 1211 kfree(tp->rx_info[i].buffer);
1212 tp->rx_info[i].buffer = NULL;
1213 tp->rx_info[i].head = NULL;
ebc2ec48 1214 }
1215
1216 for (i = 0; i < RTL8152_MAX_TX; i++) {
9629e3c0 1217 usb_free_urb(tp->tx_info[i].urb);
1218 tp->tx_info[i].urb = NULL;
ebc2ec48 1219
9629e3c0 1220 kfree(tp->tx_info[i].buffer);
1221 tp->tx_info[i].buffer = NULL;
1222 tp->tx_info[i].head = NULL;
ebc2ec48 1223 }
40a82917 1224
9629e3c0 1225 usb_free_urb(tp->intr_urb);
1226 tp->intr_urb = NULL;
40a82917 1227
9629e3c0 1228 kfree(tp->intr_buff);
1229 tp->intr_buff = NULL;
ebc2ec48 1230}
1231
1232static int alloc_all_mem(struct r8152 *tp)
1233{
1234 struct net_device *netdev = tp->netdev;
40a82917 1235 struct usb_interface *intf = tp->intf;
1236 struct usb_host_interface *alt = intf->cur_altsetting;
1237 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 1238 struct urb *urb;
1239 int node, i;
1240 u8 *buf;
1241
1242 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1243
1244 spin_lock_init(&tp->rx_lock);
1245 spin_lock_init(&tp->tx_lock);
ebc2ec48 1246 INIT_LIST_HEAD(&tp->tx_free);
1247 skb_queue_head_init(&tp->tx_queue);
1248
1249 for (i = 0; i < RTL8152_MAX_RX; i++) {
52aec126 1250 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1251 if (!buf)
1252 goto err1;
1253
1254 if (buf != rx_agg_align(buf)) {
1255 kfree(buf);
52aec126 1256 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
8e1f51bd 1257 node);
ebc2ec48 1258 if (!buf)
1259 goto err1;
1260 }
1261
1262 urb = usb_alloc_urb(0, GFP_KERNEL);
1263 if (!urb) {
1264 kfree(buf);
1265 goto err1;
1266 }
1267
1268 INIT_LIST_HEAD(&tp->rx_info[i].list);
1269 tp->rx_info[i].context = tp;
1270 tp->rx_info[i].urb = urb;
1271 tp->rx_info[i].buffer = buf;
1272 tp->rx_info[i].head = rx_agg_align(buf);
1273 }
1274
1275 for (i = 0; i < RTL8152_MAX_TX; i++) {
52aec126 1276 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1277 if (!buf)
1278 goto err1;
1279
1280 if (buf != tx_agg_align(buf)) {
1281 kfree(buf);
52aec126 1282 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
8e1f51bd 1283 node);
ebc2ec48 1284 if (!buf)
1285 goto err1;
1286 }
1287
1288 urb = usb_alloc_urb(0, GFP_KERNEL);
1289 if (!urb) {
1290 kfree(buf);
1291 goto err1;
1292 }
1293
1294 INIT_LIST_HEAD(&tp->tx_info[i].list);
1295 tp->tx_info[i].context = tp;
1296 tp->tx_info[i].urb = urb;
1297 tp->tx_info[i].buffer = buf;
1298 tp->tx_info[i].head = tx_agg_align(buf);
1299
1300 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1301 }
1302
40a82917 1303 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1304 if (!tp->intr_urb)
1305 goto err1;
1306
1307 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1308 if (!tp->intr_buff)
1309 goto err1;
1310
1311 tp->intr_interval = (int)ep_intr->desc.bInterval;
1312 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
b209af99 1313 tp->intr_buff, INTBUFSIZE, intr_callback,
1314 tp, tp->intr_interval);
40a82917 1315
ebc2ec48 1316 return 0;
1317
1318err1:
1319 free_all_mem(tp);
1320 return -ENOMEM;
1321}
1322
0de98f6c 1323static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1324{
1325 struct tx_agg *agg = NULL;
1326 unsigned long flags;
1327
21949ab7 1328 if (list_empty(&tp->tx_free))
1329 return NULL;
1330
0de98f6c 1331 spin_lock_irqsave(&tp->tx_lock, flags);
1332 if (!list_empty(&tp->tx_free)) {
1333 struct list_head *cursor;
1334
1335 cursor = tp->tx_free.next;
1336 list_del_init(cursor);
1337 agg = list_entry(cursor, struct tx_agg, list);
1338 }
1339 spin_unlock_irqrestore(&tp->tx_lock, flags);
1340
1341 return agg;
1342}
1343
60c89071 1344static inline __be16 get_protocol(struct sk_buff *skb)
5bd23881 1345{
60c89071 1346 __be16 protocol;
5bd23881 1347
60c89071 1348 if (skb->protocol == htons(ETH_P_8021Q))
1349 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1350 else
1351 protocol = skb->protocol;
5bd23881 1352
60c89071 1353 return protocol;
1354}
5bd23881 1355
b209af99 1356/* r8152_csum_workaround()
6128d1bb 1357 * The hw limites the value the transport offset. When the offset is out of the
1358 * range, calculate the checksum by sw.
1359 */
1360static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1361 struct sk_buff_head *list)
1362{
1363 if (skb_shinfo(skb)->gso_size) {
1364 netdev_features_t features = tp->netdev->features;
1365 struct sk_buff_head seg_list;
1366 struct sk_buff *segs, *nskb;
1367
a91d45f1 1368 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6128d1bb 1369 segs = skb_gso_segment(skb, features);
1370 if (IS_ERR(segs) || !segs)
1371 goto drop;
1372
1373 __skb_queue_head_init(&seg_list);
1374
1375 do {
1376 nskb = segs;
1377 segs = segs->next;
1378 nskb->next = NULL;
1379 __skb_queue_tail(&seg_list, nskb);
1380 } while (segs);
1381
1382 skb_queue_splice(&seg_list, list);
1383 dev_kfree_skb(skb);
1384 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1385 if (skb_checksum_help(skb) < 0)
1386 goto drop;
1387
1388 __skb_queue_head(list, skb);
1389 } else {
1390 struct net_device_stats *stats;
1391
1392drop:
1393 stats = &tp->netdev->stats;
1394 stats->tx_dropped++;
1395 dev_kfree_skb(skb);
1396 }
1397}
1398
b209af99 1399/* msdn_giant_send_check()
6128d1bb 1400 * According to the document of microsoft, the TCP Pseudo Header excludes the
1401 * packet length for IPv6 TCP large packets.
1402 */
1403static int msdn_giant_send_check(struct sk_buff *skb)
1404{
1405 const struct ipv6hdr *ipv6h;
1406 struct tcphdr *th;
fcb308d5 1407 int ret;
1408
1409 ret = skb_cow_head(skb, 0);
1410 if (ret)
1411 return ret;
6128d1bb 1412
1413 ipv6h = ipv6_hdr(skb);
1414 th = tcp_hdr(skb);
1415
1416 th->check = 0;
1417 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1418
fcb308d5 1419 return ret;
6128d1bb 1420}
1421
c5554298 1422static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1423{
1424 if (vlan_tx_tag_present(skb)) {
1425 u32 opts2;
1426
1427 opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb));
1428 desc->opts2 |= cpu_to_le32(opts2);
1429 }
1430}
1431
1432static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1433{
1434 u32 opts2 = le32_to_cpu(desc->opts2);
1435
1436 if (opts2 & RX_VLAN_TAG)
1437 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1438 swab16(opts2 & 0xffff));
1439}
1440
60c89071 1441static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1442 struct sk_buff *skb, u32 len, u32 transport_offset)
1443{
1444 u32 mss = skb_shinfo(skb)->gso_size;
1445 u32 opts1, opts2 = 0;
1446 int ret = TX_CSUM_SUCCESS;
1447
1448 WARN_ON_ONCE(len > TX_LEN_MAX);
1449
1450 opts1 = len | TX_FS | TX_LS;
1451
1452 if (mss) {
6128d1bb 1453 if (transport_offset > GTTCPHO_MAX) {
1454 netif_warn(tp, tx_err, tp->netdev,
1455 "Invalid transport offset 0x%x for TSO\n",
1456 transport_offset);
1457 ret = TX_CSUM_TSO;
1458 goto unavailable;
1459 }
1460
60c89071 1461 switch (get_protocol(skb)) {
1462 case htons(ETH_P_IP):
1463 opts1 |= GTSENDV4;
1464 break;
1465
6128d1bb 1466 case htons(ETH_P_IPV6):
fcb308d5 1467 if (msdn_giant_send_check(skb)) {
1468 ret = TX_CSUM_TSO;
1469 goto unavailable;
1470 }
6128d1bb 1471 opts1 |= GTSENDV6;
6128d1bb 1472 break;
1473
60c89071 1474 default:
1475 WARN_ON_ONCE(1);
1476 break;
1477 }
1478
1479 opts1 |= transport_offset << GTTCPHO_SHIFT;
1480 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1481 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1482 u8 ip_protocol;
5bd23881 1483
6128d1bb 1484 if (transport_offset > TCPHO_MAX) {
1485 netif_warn(tp, tx_err, tp->netdev,
1486 "Invalid transport offset 0x%x\n",
1487 transport_offset);
1488 ret = TX_CSUM_NONE;
1489 goto unavailable;
1490 }
1491
60c89071 1492 switch (get_protocol(skb)) {
5bd23881 1493 case htons(ETH_P_IP):
1494 opts2 |= IPV4_CS;
1495 ip_protocol = ip_hdr(skb)->protocol;
1496 break;
1497
1498 case htons(ETH_P_IPV6):
1499 opts2 |= IPV6_CS;
1500 ip_protocol = ipv6_hdr(skb)->nexthdr;
1501 break;
1502
1503 default:
1504 ip_protocol = IPPROTO_RAW;
1505 break;
1506 }
1507
60c89071 1508 if (ip_protocol == IPPROTO_TCP)
5bd23881 1509 opts2 |= TCP_CS;
60c89071 1510 else if (ip_protocol == IPPROTO_UDP)
5bd23881 1511 opts2 |= UDP_CS;
60c89071 1512 else
5bd23881 1513 WARN_ON_ONCE(1);
5bd23881 1514
60c89071 1515 opts2 |= transport_offset << TCPHO_SHIFT;
5bd23881 1516 }
60c89071 1517
1518 desc->opts2 = cpu_to_le32(opts2);
1519 desc->opts1 = cpu_to_le32(opts1);
1520
6128d1bb 1521unavailable:
60c89071 1522 return ret;
5bd23881 1523}
1524
b1379d9a 1525static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1526{
d84130a1 1527 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
9a4be1bd 1528 int remain, ret;
b1379d9a 1529 u8 *tx_data;
1530
d84130a1 1531 __skb_queue_head_init(&skb_head);
0c3121fc 1532 spin_lock(&tx_queue->lock);
d84130a1 1533 skb_queue_splice_init(tx_queue, &skb_head);
0c3121fc 1534 spin_unlock(&tx_queue->lock);
d84130a1 1535
b1379d9a 1536 tx_data = agg->head;
b209af99 1537 agg->skb_num = 0;
1538 agg->skb_len = 0;
52aec126 1539 remain = agg_buf_sz;
b1379d9a 1540
7937f9e5 1541 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1542 struct tx_desc *tx_desc;
1543 struct sk_buff *skb;
1544 unsigned int len;
60c89071 1545 u32 offset;
b1379d9a 1546
d84130a1 1547 skb = __skb_dequeue(&skb_head);
b1379d9a 1548 if (!skb)
1549 break;
1550
60c89071 1551 len = skb->len + sizeof(*tx_desc);
1552
1553 if (len > remain) {
d84130a1 1554 __skb_queue_head(&skb_head, skb);
b1379d9a 1555 break;
1556 }
1557
7937f9e5 1558 tx_data = tx_agg_align(tx_data);
b1379d9a 1559 tx_desc = (struct tx_desc *)tx_data;
60c89071 1560
1561 offset = (u32)skb_transport_offset(skb);
1562
6128d1bb 1563 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1564 r8152_csum_workaround(tp, skb, &skb_head);
1565 continue;
1566 }
60c89071 1567
c5554298 1568 rtl_tx_vlan_tag(tx_desc, skb);
1569
b1379d9a 1570 tx_data += sizeof(*tx_desc);
1571
60c89071 1572 len = skb->len;
1573 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1574 struct net_device_stats *stats = &tp->netdev->stats;
1575
1576 stats->tx_dropped++;
1577 dev_kfree_skb_any(skb);
1578 tx_data -= sizeof(*tx_desc);
1579 continue;
1580 }
1581
1582 tx_data += len;
b1379d9a 1583 agg->skb_len += len;
60c89071 1584 agg->skb_num++;
1585
b1379d9a 1586 dev_kfree_skb_any(skb);
1587
52aec126 1588 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1589 }
1590
d84130a1 1591 if (!skb_queue_empty(&skb_head)) {
0c3121fc 1592 spin_lock(&tx_queue->lock);
d84130a1 1593 skb_queue_splice(&skb_head, tx_queue);
0c3121fc 1594 spin_unlock(&tx_queue->lock);
d84130a1 1595 }
1596
0c3121fc 1597 netif_tx_lock(tp->netdev);
dd1b119c 1598
1599 if (netif_queue_stopped(tp->netdev) &&
1600 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1601 netif_wake_queue(tp->netdev);
1602
0c3121fc 1603 netif_tx_unlock(tp->netdev);
9a4be1bd 1604
0c3121fc 1605 ret = usb_autopm_get_interface_async(tp->intf);
9a4be1bd 1606 if (ret < 0)
1607 goto out_tx_fill;
dd1b119c 1608
b1379d9a 1609 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1610 agg->head, (int)(tx_data - (u8 *)agg->head),
1611 (usb_complete_t)write_bulk_callback, agg);
1612
0c3121fc 1613 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
9a4be1bd 1614 if (ret < 0)
0c3121fc 1615 usb_autopm_put_interface_async(tp->intf);
9a4be1bd 1616
1617out_tx_fill:
1618 return ret;
b1379d9a 1619}
1620
565cab0a 1621static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1622{
1623 u8 checksum = CHECKSUM_NONE;
1624 u32 opts2, opts3;
1625
1626 if (tp->version == RTL_VER_01)
1627 goto return_result;
1628
1629 opts2 = le32_to_cpu(rx_desc->opts2);
1630 opts3 = le32_to_cpu(rx_desc->opts3);
1631
1632 if (opts2 & RD_IPV4_CS) {
1633 if (opts3 & IPF)
1634 checksum = CHECKSUM_NONE;
1635 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1636 checksum = CHECKSUM_NONE;
1637 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1638 checksum = CHECKSUM_NONE;
1639 else
1640 checksum = CHECKSUM_UNNECESSARY;
6128d1bb 1641 } else if (RD_IPV6_CS) {
1642 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1643 checksum = CHECKSUM_UNNECESSARY;
1644 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1645 checksum = CHECKSUM_UNNECESSARY;
565cab0a 1646 }
1647
1648return_result:
1649 return checksum;
1650}
1651
ebc2ec48 1652static void rx_bottom(struct r8152 *tp)
1653{
a5a4f468 1654 unsigned long flags;
d84130a1 1655 struct list_head *cursor, *next, rx_queue;
ebc2ec48 1656
d84130a1 1657 if (list_empty(&tp->rx_done))
1658 return;
1659
1660 INIT_LIST_HEAD(&rx_queue);
a5a4f468 1661 spin_lock_irqsave(&tp->rx_lock, flags);
d84130a1 1662 list_splice_init(&tp->rx_done, &rx_queue);
1663 spin_unlock_irqrestore(&tp->rx_lock, flags);
1664
1665 list_for_each_safe(cursor, next, &rx_queue) {
43a4478d 1666 struct rx_desc *rx_desc;
1667 struct rx_agg *agg;
43a4478d 1668 int len_used = 0;
1669 struct urb *urb;
1670 u8 *rx_data;
43a4478d 1671
ebc2ec48 1672 list_del_init(cursor);
ebc2ec48 1673
1674 agg = list_entry(cursor, struct rx_agg, list);
1675 urb = agg->urb;
0de98f6c 1676 if (urb->actual_length < ETH_ZLEN)
1677 goto submit;
ebc2ec48 1678
ebc2ec48 1679 rx_desc = agg->head;
1680 rx_data = agg->head;
7937f9e5 1681 len_used += sizeof(struct rx_desc);
ebc2ec48 1682
7937f9e5 1683 while (urb->actual_length > len_used) {
43a4478d 1684 struct net_device *netdev = tp->netdev;
05e0f1aa 1685 struct net_device_stats *stats = &netdev->stats;
7937f9e5 1686 unsigned int pkt_len;
43a4478d 1687 struct sk_buff *skb;
1688
7937f9e5 1689 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1690 if (pkt_len < ETH_ZLEN)
1691 break;
1692
7937f9e5 1693 len_used += pkt_len;
1694 if (urb->actual_length < len_used)
1695 break;
1696
8e1f51bd 1697 pkt_len -= CRC_SIZE;
ebc2ec48 1698 rx_data += sizeof(struct rx_desc);
1699
1700 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1701 if (!skb) {
1702 stats->rx_dropped++;
5e2f7485 1703 goto find_next_rx;
ebc2ec48 1704 }
565cab0a 1705
1706 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
ebc2ec48 1707 memcpy(skb->data, rx_data, pkt_len);
1708 skb_put(skb, pkt_len);
1709 skb->protocol = eth_type_trans(skb, netdev);
c5554298 1710 rtl_rx_vlan_tag(rx_desc, skb);
9d9aafa1 1711 netif_receive_skb(skb);
ebc2ec48 1712 stats->rx_packets++;
1713 stats->rx_bytes += pkt_len;
1714
5e2f7485 1715find_next_rx:
8e1f51bd 1716 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1717 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1718 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1719 len_used += sizeof(struct rx_desc);
ebc2ec48 1720 }
1721
0de98f6c 1722submit:
a0fccd48 1723 r8152_submit_rx(tp, agg, GFP_ATOMIC);
ebc2ec48 1724 }
ebc2ec48 1725}
1726
1727static void tx_bottom(struct r8152 *tp)
1728{
ebc2ec48 1729 int res;
1730
b1379d9a 1731 do {
1732 struct tx_agg *agg;
ebc2ec48 1733
b1379d9a 1734 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1735 break;
1736
b1379d9a 1737 agg = r8152_get_tx_agg(tp);
1738 if (!agg)
ebc2ec48 1739 break;
ebc2ec48 1740
b1379d9a 1741 res = r8152_tx_agg_fill(tp, agg);
1742 if (res) {
05e0f1aa 1743 struct net_device *netdev = tp->netdev;
ebc2ec48 1744
b1379d9a 1745 if (res == -ENODEV) {
67610496 1746 set_bit(RTL8152_UNPLUG, &tp->flags);
b1379d9a 1747 netif_device_detach(netdev);
1748 } else {
05e0f1aa 1749 struct net_device_stats *stats = &netdev->stats;
1750 unsigned long flags;
1751
b1379d9a 1752 netif_warn(tp, tx_err, netdev,
1753 "failed tx_urb %d\n", res);
1754 stats->tx_dropped += agg->skb_num;
db8515ef 1755
b1379d9a 1756 spin_lock_irqsave(&tp->tx_lock, flags);
1757 list_add_tail(&agg->list, &tp->tx_free);
1758 spin_unlock_irqrestore(&tp->tx_lock, flags);
1759 }
ebc2ec48 1760 }
b1379d9a 1761 } while (res == 0);
ebc2ec48 1762}
1763
1764static void bottom_half(unsigned long data)
ac718b69 1765{
1766 struct r8152 *tp;
ac718b69 1767
ebc2ec48 1768 tp = (struct r8152 *)data;
1769
1770 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1771 return;
1772
1773 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1774 return;
ebc2ec48 1775
7559fb2f 1776 /* When link down, the driver would cancel all bulks. */
1777 /* This avoid the re-submitting bulk */
ebc2ec48 1778 if (!netif_carrier_ok(tp->netdev))
ac718b69 1779 return;
ebc2ec48 1780
9451a11c 1781 clear_bit(SCHEDULE_TASKLET, &tp->flags);
1782
ebc2ec48 1783 rx_bottom(tp);
0c3121fc 1784 tx_bottom(tp);
ebc2ec48 1785}
1786
1787static
1788int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1789{
a0fccd48 1790 int ret;
1791
ebc2ec48 1792 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
52aec126 1793 agg->head, agg_buf_sz,
b209af99 1794 (usb_complete_t)read_bulk_callback, agg);
ebc2ec48 1795
a0fccd48 1796 ret = usb_submit_urb(agg->urb, mem_flags);
1797 if (ret == -ENODEV) {
1798 set_bit(RTL8152_UNPLUG, &tp->flags);
1799 netif_device_detach(tp->netdev);
1800 } else if (ret) {
1801 struct urb *urb = agg->urb;
1802 unsigned long flags;
1803
1804 urb->actual_length = 0;
1805 spin_lock_irqsave(&tp->rx_lock, flags);
1806 list_add_tail(&agg->list, &tp->rx_done);
1807 spin_unlock_irqrestore(&tp->rx_lock, flags);
1808 tasklet_schedule(&tp->tl);
1809 }
1810
1811 return ret;
ac718b69 1812}
1813
00a5e360 1814static void rtl_drop_queued_tx(struct r8152 *tp)
1815{
1816 struct net_device_stats *stats = &tp->netdev->stats;
d84130a1 1817 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
00a5e360 1818 struct sk_buff *skb;
1819
d84130a1 1820 if (skb_queue_empty(tx_queue))
1821 return;
1822
1823 __skb_queue_head_init(&skb_head);
2685d410 1824 spin_lock_bh(&tx_queue->lock);
d84130a1 1825 skb_queue_splice_init(tx_queue, &skb_head);
2685d410 1826 spin_unlock_bh(&tx_queue->lock);
d84130a1 1827
1828 while ((skb = __skb_dequeue(&skb_head))) {
00a5e360 1829 dev_kfree_skb(skb);
1830 stats->tx_dropped++;
1831 }
1832}
1833
ac718b69 1834static void rtl8152_tx_timeout(struct net_device *netdev)
1835{
1836 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1837 int i;
1838
4a8deae2 1839 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
ebc2ec48 1840 for (i = 0; i < RTL8152_MAX_TX; i++)
1841 usb_unlink_urb(tp->tx_info[i].urb);
ac718b69 1842}
1843
1844static void rtl8152_set_rx_mode(struct net_device *netdev)
1845{
1846 struct r8152 *tp = netdev_priv(netdev);
1847
40a82917 1848 if (tp->speed & LINK_STATUS) {
ac718b69 1849 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1850 schedule_delayed_work(&tp->schedule, 0);
1851 }
ac718b69 1852}
1853
1854static void _rtl8152_set_rx_mode(struct net_device *netdev)
1855{
1856 struct r8152 *tp = netdev_priv(netdev);
31787f53 1857 u32 mc_filter[2]; /* Multicast hash filter */
1858 __le32 tmp[2];
ac718b69 1859 u32 ocp_data;
1860
ac718b69 1861 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1862 netif_stop_queue(netdev);
1863 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1864 ocp_data &= ~RCR_ACPT_ALL;
1865 ocp_data |= RCR_AB | RCR_APM;
1866
1867 if (netdev->flags & IFF_PROMISC) {
1868 /* Unconditionally log net taps. */
1869 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1870 ocp_data |= RCR_AM | RCR_AAP;
b209af99 1871 mc_filter[1] = 0xffffffff;
1872 mc_filter[0] = 0xffffffff;
ac718b69 1873 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1874 (netdev->flags & IFF_ALLMULTI)) {
1875 /* Too many to filter perfectly -- accept all multicasts. */
1876 ocp_data |= RCR_AM;
b209af99 1877 mc_filter[1] = 0xffffffff;
1878 mc_filter[0] = 0xffffffff;
ac718b69 1879 } else {
1880 struct netdev_hw_addr *ha;
1881
b209af99 1882 mc_filter[1] = 0;
1883 mc_filter[0] = 0;
ac718b69 1884 netdev_for_each_mc_addr(ha, netdev) {
1885 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
b209af99 1886
ac718b69 1887 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1888 ocp_data |= RCR_AM;
1889 }
1890 }
1891
31787f53 1892 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1893 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1894
31787f53 1895 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1896 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1897 netif_wake_queue(netdev);
ac718b69 1898}
1899
a5e31255 1900static netdev_features_t
1901rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
1902 netdev_features_t features)
1903{
1904 u32 mss = skb_shinfo(skb)->gso_size;
1905 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
1906 int offset = skb_transport_offset(skb);
1907
1908 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
1909 features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
1910 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
1911 features &= ~NETIF_F_GSO_MASK;
1912
1913 return features;
1914}
1915
ac718b69 1916static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
b209af99 1917 struct net_device *netdev)
ac718b69 1918{
1919 struct r8152 *tp = netdev_priv(netdev);
ac718b69 1920
ebc2ec48 1921 skb_tx_timestamp(skb);
ac718b69 1922
61598788 1923 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 1924
0c3121fc 1925 if (!list_empty(&tp->tx_free)) {
1926 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1927 set_bit(SCHEDULE_TASKLET, &tp->flags);
1928 schedule_delayed_work(&tp->schedule, 0);
1929 } else {
1930 usb_mark_last_busy(tp->udev);
1931 tasklet_schedule(&tp->tl);
1932 }
b209af99 1933 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
dd1b119c 1934 netif_stop_queue(netdev);
b209af99 1935 }
dd1b119c 1936
ac718b69 1937 return NETDEV_TX_OK;
1938}
1939
1940static void r8152b_reset_packet_filter(struct r8152 *tp)
1941{
1942 u32 ocp_data;
1943
1944 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1945 ocp_data &= ~FMC_FCR_MCU_EN;
1946 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1947 ocp_data |= FMC_FCR_MCU_EN;
1948 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1949}
1950
1951static void rtl8152_nic_reset(struct r8152 *tp)
1952{
1953 int i;
1954
1955 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1956
1957 for (i = 0; i < 1000; i++) {
1958 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1959 break;
b209af99 1960 usleep_range(100, 400);
ac718b69 1961 }
1962}
1963
dd1b119c 1964static void set_tx_qlen(struct r8152 *tp)
1965{
1966 struct net_device *netdev = tp->netdev;
1967
52aec126 1968 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1969 sizeof(struct tx_desc));
dd1b119c 1970}
1971
ac718b69 1972static inline u8 rtl8152_get_speed(struct r8152 *tp)
1973{
1974 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1975}
1976
507605a8 1977static void rtl_set_eee_plus(struct r8152 *tp)
ac718b69 1978{
ebc2ec48 1979 u32 ocp_data;
ac718b69 1980 u8 speed;
1981
1982 speed = rtl8152_get_speed(tp);
ebc2ec48 1983 if (speed & _10bps) {
ac718b69 1984 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1985 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 1986 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1987 } else {
1988 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1989 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 1990 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1991 }
507605a8 1992}
1993
00a5e360 1994static void rxdy_gated_en(struct r8152 *tp, bool enable)
1995{
1996 u32 ocp_data;
1997
1998 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1999 if (enable)
2000 ocp_data |= RXDY_GATED_EN;
2001 else
2002 ocp_data &= ~RXDY_GATED_EN;
2003 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2004}
2005
445f7f4d 2006static int rtl_start_rx(struct r8152 *tp)
2007{
2008 int i, ret = 0;
2009
2010 INIT_LIST_HEAD(&tp->rx_done);
2011 for (i = 0; i < RTL8152_MAX_RX; i++) {
2012 INIT_LIST_HEAD(&tp->rx_info[i].list);
2013 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2014 if (ret)
2015 break;
2016 }
2017
7bcf4f60 2018 if (ret && ++i < RTL8152_MAX_RX) {
2019 struct list_head rx_queue;
2020 unsigned long flags;
2021
2022 INIT_LIST_HEAD(&rx_queue);
2023
2024 do {
2025 struct rx_agg *agg = &tp->rx_info[i++];
2026 struct urb *urb = agg->urb;
2027
2028 urb->actual_length = 0;
2029 list_add_tail(&agg->list, &rx_queue);
2030 } while (i < RTL8152_MAX_RX);
2031
2032 spin_lock_irqsave(&tp->rx_lock, flags);
2033 list_splice_tail(&rx_queue, &tp->rx_done);
2034 spin_unlock_irqrestore(&tp->rx_lock, flags);
2035 }
2036
445f7f4d 2037 return ret;
2038}
2039
2040static int rtl_stop_rx(struct r8152 *tp)
2041{
2042 int i;
2043
2044 for (i = 0; i < RTL8152_MAX_RX; i++)
2045 usb_kill_urb(tp->rx_info[i].urb);
2046
2047 return 0;
2048}
2049
507605a8 2050static int rtl_enable(struct r8152 *tp)
2051{
2052 u32 ocp_data;
ac718b69 2053
2054 r8152b_reset_packet_filter(tp);
2055
2056 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2057 ocp_data |= CR_RE | CR_TE;
2058 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2059
00a5e360 2060 rxdy_gated_en(tp, false);
ac718b69 2061
445f7f4d 2062 return rtl_start_rx(tp);
ac718b69 2063}
2064
507605a8 2065static int rtl8152_enable(struct r8152 *tp)
2066{
6871438c 2067 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2068 return -ENODEV;
2069
507605a8 2070 set_tx_qlen(tp);
2071 rtl_set_eee_plus(tp);
2072
2073 return rtl_enable(tp);
2074}
2075
43779f8d 2076static void r8153_set_rx_agg(struct r8152 *tp)
2077{
2078 u8 speed;
2079
2080 speed = rtl8152_get_speed(tp);
2081 if (speed & _1000bps) {
2082 if (tp->udev->speed == USB_SPEED_SUPER) {
2083 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2084 RX_THR_SUPPER);
2085 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2086 EARLY_AGG_SUPPER);
2087 } else {
2088 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2089 RX_THR_HIGH);
2090 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2091 EARLY_AGG_HIGH);
2092 }
2093 } else {
2094 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2095 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2096 EARLY_AGG_SLOW);
2097 }
2098}
2099
2100static int rtl8153_enable(struct r8152 *tp)
2101{
6871438c 2102 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2103 return -ENODEV;
2104
43779f8d 2105 set_tx_qlen(tp);
2106 rtl_set_eee_plus(tp);
2107 r8153_set_rx_agg(tp);
2108
2109 return rtl_enable(tp);
2110}
2111
d70b1137 2112static void rtl_disable(struct r8152 *tp)
ac718b69 2113{
ebc2ec48 2114 u32 ocp_data;
2115 int i;
ac718b69 2116
6871438c 2117 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2118 rtl_drop_queued_tx(tp);
2119 return;
2120 }
2121
ac718b69 2122 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2123 ocp_data &= ~RCR_ACPT_ALL;
2124 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2125
00a5e360 2126 rtl_drop_queued_tx(tp);
ebc2ec48 2127
2128 for (i = 0; i < RTL8152_MAX_TX; i++)
2129 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 2130
00a5e360 2131 rxdy_gated_en(tp, true);
ac718b69 2132
2133 for (i = 0; i < 1000; i++) {
2134 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2135 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2136 break;
8ddfa077 2137 usleep_range(1000, 2000);
ac718b69 2138 }
2139
2140 for (i = 0; i < 1000; i++) {
2141 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2142 break;
8ddfa077 2143 usleep_range(1000, 2000);
ac718b69 2144 }
2145
445f7f4d 2146 rtl_stop_rx(tp);
ac718b69 2147
2148 rtl8152_nic_reset(tp);
2149}
2150
00a5e360 2151static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2152{
2153 u32 ocp_data;
2154
2155 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2156 if (enable)
2157 ocp_data |= POWER_CUT;
2158 else
2159 ocp_data &= ~POWER_CUT;
2160 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2161
2162 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2163 ocp_data &= ~RESUME_INDICATE;
2164 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
00a5e360 2165}
2166
c5554298 2167static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2168{
2169 u32 ocp_data;
2170
2171 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2172 if (enable)
2173 ocp_data |= CPCR_RX_VLAN;
2174 else
2175 ocp_data &= ~CPCR_RX_VLAN;
2176 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2177}
2178
2179static int rtl8152_set_features(struct net_device *dev,
2180 netdev_features_t features)
2181{
2182 netdev_features_t changed = features ^ dev->features;
2183 struct r8152 *tp = netdev_priv(dev);
405f8a0e 2184 int ret;
2185
2186 ret = usb_autopm_get_interface(tp->intf);
2187 if (ret < 0)
2188 goto out;
c5554298 2189
b5403273 2190 mutex_lock(&tp->control);
2191
c5554298 2192 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2193 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2194 rtl_rx_vlan_en(tp, true);
2195 else
2196 rtl_rx_vlan_en(tp, false);
2197 }
2198
b5403273 2199 mutex_unlock(&tp->control);
2200
405f8a0e 2201 usb_autopm_put_interface(tp->intf);
2202
2203out:
2204 return ret;
c5554298 2205}
2206
21ff2e89 2207#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2208
2209static u32 __rtl_get_wol(struct r8152 *tp)
2210{
2211 u32 ocp_data;
2212 u32 wolopts = 0;
2213
2214 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2215 if (!(ocp_data & LAN_WAKE_EN))
2216 return 0;
2217
2218 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2219 if (ocp_data & LINK_ON_WAKE_EN)
2220 wolopts |= WAKE_PHY;
2221
2222 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2223 if (ocp_data & UWF_EN)
2224 wolopts |= WAKE_UCAST;
2225 if (ocp_data & BWF_EN)
2226 wolopts |= WAKE_BCAST;
2227 if (ocp_data & MWF_EN)
2228 wolopts |= WAKE_MCAST;
2229
2230 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2231 if (ocp_data & MAGIC_EN)
2232 wolopts |= WAKE_MAGIC;
2233
2234 return wolopts;
2235}
2236
2237static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2238{
2239 u32 ocp_data;
2240
2241 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2242
2243 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2244 ocp_data &= ~LINK_ON_WAKE_EN;
2245 if (wolopts & WAKE_PHY)
2246 ocp_data |= LINK_ON_WAKE_EN;
2247 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2248
2249 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2250 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2251 if (wolopts & WAKE_UCAST)
2252 ocp_data |= UWF_EN;
2253 if (wolopts & WAKE_BCAST)
2254 ocp_data |= BWF_EN;
2255 if (wolopts & WAKE_MCAST)
2256 ocp_data |= MWF_EN;
2257 if (wolopts & WAKE_ANY)
2258 ocp_data |= LAN_WAKE_EN;
2259 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2260
2261 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2262
2263 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2264 ocp_data &= ~MAGIC_EN;
2265 if (wolopts & WAKE_MAGIC)
2266 ocp_data |= MAGIC_EN;
2267 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2268
2269 if (wolopts & WAKE_ANY)
2270 device_set_wakeup_enable(&tp->udev->dev, true);
2271 else
2272 device_set_wakeup_enable(&tp->udev->dev, false);
2273}
2274
9a4be1bd 2275static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2276{
2277 if (enable) {
2278 u32 ocp_data;
2279
2280 __rtl_set_wol(tp, WAKE_ANY);
2281
2282 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2283
2284 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2285 ocp_data |= LINK_OFF_WAKE_EN;
2286 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2287
2288 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2289 } else {
2290 __rtl_set_wol(tp, tp->saved_wolopts);
2291 }
2292}
2293
aa66a5f1 2294static void rtl_phy_reset(struct r8152 *tp)
2295{
2296 u16 data;
2297 int i;
2298
2299 clear_bit(PHY_RESET, &tp->flags);
2300
2301 data = r8152_mdio_read(tp, MII_BMCR);
2302
2303 /* don't reset again before the previous one complete */
2304 if (data & BMCR_RESET)
2305 return;
2306
2307 data |= BMCR_RESET;
2308 r8152_mdio_write(tp, MII_BMCR, data);
2309
2310 for (i = 0; i < 50; i++) {
2311 msleep(20);
2312 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2313 break;
2314 }
2315}
2316
4349968a 2317static void r8153_teredo_off(struct r8152 *tp)
2318{
2319 u32 ocp_data;
2320
2321 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2322 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2323 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2324
2325 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2326 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2327 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2328}
2329
2330static void r8152b_disable_aldps(struct r8152 *tp)
2331{
2332 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2333 msleep(20);
2334}
2335
2336static inline void r8152b_enable_aldps(struct r8152 *tp)
2337{
2338 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2339 LINKENA | DIS_SDSAVE);
2340}
2341
d70b1137 2342static void rtl8152_disable(struct r8152 *tp)
2343{
2344 r8152b_disable_aldps(tp);
2345 rtl_disable(tp);
2346 r8152b_enable_aldps(tp);
2347}
2348
4349968a 2349static void r8152b_hw_phy_cfg(struct r8152 *tp)
2350{
f0cbe0ac 2351 u16 data;
2352
2353 data = r8152_mdio_read(tp, MII_BMCR);
2354 if (data & BMCR_PDOWN) {
2355 data &= ~BMCR_PDOWN;
2356 r8152_mdio_write(tp, MII_BMCR, data);
2357 }
2358
aa66a5f1 2359 set_bit(PHY_RESET, &tp->flags);
4349968a 2360}
2361
ac718b69 2362static void r8152b_exit_oob(struct r8152 *tp)
2363{
db8515ef 2364 u32 ocp_data;
2365 int i;
ac718b69 2366
2367 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2368 ocp_data &= ~RCR_ACPT_ALL;
2369 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2370
00a5e360 2371 rxdy_gated_en(tp, true);
da9bd117 2372 r8153_teredo_off(tp);
7e9da481 2373 r8152b_hw_phy_cfg(tp);
ac718b69 2374
2375 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2376 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2377
2378 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2379 ocp_data &= ~NOW_IS_OOB;
2380 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2381
2382 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2383 ocp_data &= ~MCU_BORW_EN;
2384 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2385
2386 for (i = 0; i < 1000; i++) {
2387 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2388 if (ocp_data & LINK_LIST_READY)
2389 break;
8ddfa077 2390 usleep_range(1000, 2000);
ac718b69 2391 }
2392
2393 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2394 ocp_data |= RE_INIT_LL;
2395 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2396
2397 for (i = 0; i < 1000; i++) {
2398 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2399 if (ocp_data & LINK_LIST_READY)
2400 break;
8ddfa077 2401 usleep_range(1000, 2000);
ac718b69 2402 }
2403
2404 rtl8152_nic_reset(tp);
2405
2406 /* rx share fifo credit full threshold */
2407 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2408
a3cc465d 2409 if (tp->udev->speed == USB_SPEED_FULL ||
2410 tp->udev->speed == USB_SPEED_LOW) {
ac718b69 2411 /* rx share fifo credit near full threshold */
2412 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2413 RXFIFO_THR2_FULL);
2414 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2415 RXFIFO_THR3_FULL);
2416 } else {
2417 /* rx share fifo credit near full threshold */
2418 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2419 RXFIFO_THR2_HIGH);
2420 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2421 RXFIFO_THR3_HIGH);
2422 }
2423
2424 /* TX share fifo free credit full threshold */
2425 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2426
2427 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 2428 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 2429 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2430 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2431
c5554298 2432 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
ac718b69 2433
2434 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2435
2436 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2437 ocp_data |= TCR0_AUTO_FIFO;
2438 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2439}
2440
2441static void r8152b_enter_oob(struct r8152 *tp)
2442{
45f4a19f 2443 u32 ocp_data;
2444 int i;
ac718b69 2445
2446 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2447 ocp_data &= ~NOW_IS_OOB;
2448 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2449
2450 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2451 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2452 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2453
d70b1137 2454 rtl_disable(tp);
ac718b69 2455
2456 for (i = 0; i < 1000; i++) {
2457 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2458 if (ocp_data & LINK_LIST_READY)
2459 break;
8ddfa077 2460 usleep_range(1000, 2000);
ac718b69 2461 }
2462
2463 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2464 ocp_data |= RE_INIT_LL;
2465 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2466
2467 for (i = 0; i < 1000; i++) {
2468 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2469 if (ocp_data & LINK_LIST_READY)
2470 break;
8ddfa077 2471 usleep_range(1000, 2000);
ac718b69 2472 }
2473
2474 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2475
c5554298 2476 rtl_rx_vlan_en(tp, true);
ac718b69 2477
2478 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2479 ocp_data |= ALDPS_PROXY_MODE;
2480 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2481
2482 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2483 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2484 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2485
00a5e360 2486 rxdy_gated_en(tp, false);
ac718b69 2487
2488 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2489 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2490 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2491}
2492
43779f8d 2493static void r8153_hw_phy_cfg(struct r8152 *tp)
2494{
2495 u32 ocp_data;
2496 u16 data;
2497
2498 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
f0cbe0ac 2499 data = r8152_mdio_read(tp, MII_BMCR);
2500 if (data & BMCR_PDOWN) {
2501 data &= ~BMCR_PDOWN;
2502 r8152_mdio_write(tp, MII_BMCR, data);
2503 }
43779f8d 2504
2505 if (tp->version == RTL_VER_03) {
2506 data = ocp_reg_read(tp, OCP_EEE_CFG);
2507 data &= ~CTAP_SHORT_EN;
2508 ocp_reg_write(tp, OCP_EEE_CFG, data);
2509 }
2510
2511 data = ocp_reg_read(tp, OCP_POWER_CFG);
2512 data |= EEE_CLKDIV_EN;
2513 ocp_reg_write(tp, OCP_POWER_CFG, data);
2514
2515 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2516 data |= EN_10M_BGOFF;
2517 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2518 data = ocp_reg_read(tp, OCP_POWER_CFG);
2519 data |= EN_10M_PLLOFF;
2520 ocp_reg_write(tp, OCP_POWER_CFG, data);
2521 data = sram_read(tp, SRAM_IMPEDANCE);
2522 data &= ~RX_DRIVING_MASK;
2523 sram_write(tp, SRAM_IMPEDANCE, data);
2524
2525 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2526 ocp_data |= PFM_PWM_SWITCH;
2527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2528
2529 data = sram_read(tp, SRAM_LPF_CFG);
2530 data |= LPF_AUTO_TUNE;
2531 sram_write(tp, SRAM_LPF_CFG, data);
2532
2533 data = sram_read(tp, SRAM_10M_AMP1);
2534 data |= GDAC_IB_UPALL;
2535 sram_write(tp, SRAM_10M_AMP1, data);
2536 data = sram_read(tp, SRAM_10M_AMP2);
2537 data |= AMP_DN;
2538 sram_write(tp, SRAM_10M_AMP2, data);
aa66a5f1 2539
2540 set_bit(PHY_RESET, &tp->flags);
43779f8d 2541}
2542
b9702723 2543static void r8153_u1u2en(struct r8152 *tp, bool enable)
43779f8d 2544{
2545 u8 u1u2[8];
2546
2547 if (enable)
2548 memset(u1u2, 0xff, sizeof(u1u2));
2549 else
2550 memset(u1u2, 0x00, sizeof(u1u2));
2551
2552 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2553}
2554
b9702723 2555static void r8153_u2p3en(struct r8152 *tp, bool enable)
43779f8d 2556{
2557 u32 ocp_data;
2558
2559 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2560 if (enable)
2561 ocp_data |= U2P3_ENABLE;
2562 else
2563 ocp_data &= ~U2P3_ENABLE;
2564 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2565}
2566
b9702723 2567static void r8153_power_cut_en(struct r8152 *tp, bool enable)
43779f8d 2568{
2569 u32 ocp_data;
2570
2571 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2572 if (enable)
2573 ocp_data |= PWR_EN | PHASE2_EN;
2574 else
2575 ocp_data &= ~(PWR_EN | PHASE2_EN);
2576 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2577
2578 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2579 ocp_data &= ~PCUT_STATUS;
2580 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2581}
2582
43779f8d 2583static void r8153_first_init(struct r8152 *tp)
2584{
2585 u32 ocp_data;
2586 int i;
2587
00a5e360 2588 rxdy_gated_en(tp, true);
43779f8d 2589 r8153_teredo_off(tp);
2590
2591 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2592 ocp_data &= ~RCR_ACPT_ALL;
2593 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2594
2595 r8153_hw_phy_cfg(tp);
2596
2597 rtl8152_nic_reset(tp);
2598
2599 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2600 ocp_data &= ~NOW_IS_OOB;
2601 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2602
2603 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2604 ocp_data &= ~MCU_BORW_EN;
2605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2606
2607 for (i = 0; i < 1000; i++) {
2608 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2609 if (ocp_data & LINK_LIST_READY)
2610 break;
8ddfa077 2611 usleep_range(1000, 2000);
43779f8d 2612 }
2613
2614 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2615 ocp_data |= RE_INIT_LL;
2616 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2617
2618 for (i = 0; i < 1000; i++) {
2619 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2620 if (ocp_data & LINK_LIST_READY)
2621 break;
8ddfa077 2622 usleep_range(1000, 2000);
43779f8d 2623 }
2624
c5554298 2625 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
43779f8d 2626
69b4b7a4 2627 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2628 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
43779f8d 2629
2630 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2631 ocp_data |= TCR0_AUTO_FIFO;
2632 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2633
2634 rtl8152_nic_reset(tp);
2635
2636 /* rx share fifo credit full threshold */
2637 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2638 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2639 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2640 /* TX share fifo free credit full threshold */
2641 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2642
9629e3c0 2643 /* rx aggregation */
43779f8d 2644 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2645 ocp_data &= ~RX_AGG_DISABLE;
2646 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2647}
2648
2649static void r8153_enter_oob(struct r8152 *tp)
2650{
2651 u32 ocp_data;
2652 int i;
2653
2654 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2655 ocp_data &= ~NOW_IS_OOB;
2656 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2657
d70b1137 2658 rtl_disable(tp);
43779f8d 2659
2660 for (i = 0; i < 1000; i++) {
2661 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2662 if (ocp_data & LINK_LIST_READY)
2663 break;
8ddfa077 2664 usleep_range(1000, 2000);
43779f8d 2665 }
2666
2667 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2668 ocp_data |= RE_INIT_LL;
2669 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2670
2671 for (i = 0; i < 1000; i++) {
2672 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2673 if (ocp_data & LINK_LIST_READY)
2674 break;
8ddfa077 2675 usleep_range(1000, 2000);
43779f8d 2676 }
2677
69b4b7a4 2678 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
43779f8d 2679
43779f8d 2680 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2681 ocp_data &= ~TEREDO_WAKE_MASK;
2682 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2683
c5554298 2684 rtl_rx_vlan_en(tp, true);
43779f8d 2685
2686 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2687 ocp_data |= ALDPS_PROXY_MODE;
2688 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2689
2690 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2691 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2692 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2693
00a5e360 2694 rxdy_gated_en(tp, false);
43779f8d 2695
2696 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2697 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2698 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2699}
2700
2701static void r8153_disable_aldps(struct r8152 *tp)
2702{
2703 u16 data;
2704
2705 data = ocp_reg_read(tp, OCP_POWER_CFG);
2706 data &= ~EN_ALDPS;
2707 ocp_reg_write(tp, OCP_POWER_CFG, data);
2708 msleep(20);
2709}
2710
2711static void r8153_enable_aldps(struct r8152 *tp)
2712{
2713 u16 data;
2714
2715 data = ocp_reg_read(tp, OCP_POWER_CFG);
2716 data |= EN_ALDPS;
2717 ocp_reg_write(tp, OCP_POWER_CFG, data);
2718}
2719
d70b1137 2720static void rtl8153_disable(struct r8152 *tp)
2721{
2722 r8153_disable_aldps(tp);
2723 rtl_disable(tp);
2724 r8153_enable_aldps(tp);
2725}
2726
ac718b69 2727static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2728{
43779f8d 2729 u16 bmcr, anar, gbcr;
ac718b69 2730 int ret = 0;
2731
2732 cancel_delayed_work_sync(&tp->schedule);
2733 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2734 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2735 ADVERTISE_100HALF | ADVERTISE_100FULL);
43779f8d 2736 if (tp->mii.supports_gmii) {
2737 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2738 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2739 } else {
2740 gbcr = 0;
2741 }
ac718b69 2742
2743 if (autoneg == AUTONEG_DISABLE) {
2744 if (speed == SPEED_10) {
2745 bmcr = 0;
2746 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2747 } else if (speed == SPEED_100) {
2748 bmcr = BMCR_SPEED100;
2749 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
43779f8d 2750 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2751 bmcr = BMCR_SPEED1000;
2752 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
ac718b69 2753 } else {
2754 ret = -EINVAL;
2755 goto out;
2756 }
2757
2758 if (duplex == DUPLEX_FULL)
2759 bmcr |= BMCR_FULLDPLX;
2760 } else {
2761 if (speed == SPEED_10) {
2762 if (duplex == DUPLEX_FULL)
2763 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2764 else
2765 anar |= ADVERTISE_10HALF;
2766 } else if (speed == SPEED_100) {
2767 if (duplex == DUPLEX_FULL) {
2768 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2769 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2770 } else {
2771 anar |= ADVERTISE_10HALF;
2772 anar |= ADVERTISE_100HALF;
2773 }
43779f8d 2774 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2775 if (duplex == DUPLEX_FULL) {
2776 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2777 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2778 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2779 } else {
2780 anar |= ADVERTISE_10HALF;
2781 anar |= ADVERTISE_100HALF;
2782 gbcr |= ADVERTISE_1000HALF;
2783 }
ac718b69 2784 } else {
2785 ret = -EINVAL;
2786 goto out;
2787 }
2788
2789 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2790 }
2791
aa66a5f1 2792 if (test_bit(PHY_RESET, &tp->flags))
2793 bmcr |= BMCR_RESET;
2794
43779f8d 2795 if (tp->mii.supports_gmii)
2796 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2797
ac718b69 2798 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2799 r8152_mdio_write(tp, MII_BMCR, bmcr);
2800
aa66a5f1 2801 if (test_bit(PHY_RESET, &tp->flags)) {
2802 int i;
2803
2804 clear_bit(PHY_RESET, &tp->flags);
2805 for (i = 0; i < 50; i++) {
2806 msleep(20);
2807 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2808 break;
2809 }
2810 }
2811
ac718b69 2812out:
ac718b69 2813
2814 return ret;
2815}
2816
d70b1137 2817static void rtl8152_up(struct r8152 *tp)
2818{
2819 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2820 return;
2821
2822 r8152b_disable_aldps(tp);
2823 r8152b_exit_oob(tp);
2824 r8152b_enable_aldps(tp);
2825}
2826
ac718b69 2827static void rtl8152_down(struct r8152 *tp)
2828{
6871438c 2829 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2830 rtl_drop_queued_tx(tp);
2831 return;
2832 }
2833
00a5e360 2834 r8152_power_cut_en(tp, false);
ac718b69 2835 r8152b_disable_aldps(tp);
2836 r8152b_enter_oob(tp);
2837 r8152b_enable_aldps(tp);
2838}
2839
d70b1137 2840static void rtl8153_up(struct r8152 *tp)
2841{
2842 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2843 return;
2844
2845 r8153_disable_aldps(tp);
2846 r8153_first_init(tp);
2847 r8153_enable_aldps(tp);
2848}
2849
43779f8d 2850static void rtl8153_down(struct r8152 *tp)
2851{
6871438c 2852 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2853 rtl_drop_queued_tx(tp);
2854 return;
2855 }
2856
b9702723 2857 r8153_u1u2en(tp, false);
2858 r8153_power_cut_en(tp, false);
43779f8d 2859 r8153_disable_aldps(tp);
2860 r8153_enter_oob(tp);
2861 r8153_enable_aldps(tp);
2862}
2863
ac718b69 2864static void set_carrier(struct r8152 *tp)
2865{
2866 struct net_device *netdev = tp->netdev;
2867 u8 speed;
2868
40a82917 2869 clear_bit(RTL8152_LINK_CHG, &tp->flags);
ac718b69 2870 speed = rtl8152_get_speed(tp);
2871
2872 if (speed & LINK_STATUS) {
2873 if (!(tp->speed & LINK_STATUS)) {
c81229c9 2874 tp->rtl_ops.enable(tp);
ac718b69 2875 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2876 netif_carrier_on(netdev);
2877 }
2878 } else {
2879 if (tp->speed & LINK_STATUS) {
2880 netif_carrier_off(netdev);
ebc2ec48 2881 tasklet_disable(&tp->tl);
c81229c9 2882 tp->rtl_ops.disable(tp);
ebc2ec48 2883 tasklet_enable(&tp->tl);
ac718b69 2884 }
2885 }
2886 tp->speed = speed;
2887}
2888
2889static void rtl_work_func_t(struct work_struct *work)
2890{
2891 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2892
a1f83fee 2893 /* If the device is unplugged or !netif_running(), the workqueue
2894 * doesn't need to wake the device, and could return directly.
2895 */
2896 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
2897 return;
2898
9a4be1bd 2899 if (usb_autopm_get_interface(tp->intf) < 0)
2900 return;
2901
ac718b69 2902 if (!test_bit(WORK_ENABLE, &tp->flags))
2903 goto out1;
2904
b5403273 2905 if (!mutex_trylock(&tp->control)) {
2906 schedule_delayed_work(&tp->schedule, 0);
2907 goto out1;
2908 }
2909
40a82917 2910 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2911 set_carrier(tp);
ac718b69 2912
2913 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2914 _rtl8152_set_rx_mode(tp->netdev);
2915
0c3121fc 2916 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2917 (tp->speed & LINK_STATUS)) {
2918 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2919 tasklet_schedule(&tp->tl);
2920 }
aa66a5f1 2921
2922 if (test_bit(PHY_RESET, &tp->flags))
2923 rtl_phy_reset(tp);
2924
b5403273 2925 mutex_unlock(&tp->control);
2926
ac718b69 2927out1:
9a4be1bd 2928 usb_autopm_put_interface(tp->intf);
ac718b69 2929}
2930
2931static int rtl8152_open(struct net_device *netdev)
2932{
2933 struct r8152 *tp = netdev_priv(netdev);
2934 int res = 0;
2935
7e9da481 2936 res = alloc_all_mem(tp);
2937 if (res)
2938 goto out;
2939
f4c7476b 2940 /* set speed to 0 to avoid autoresume try to submit rx */
2941 tp->speed = 0;
2942
9a4be1bd 2943 res = usb_autopm_get_interface(tp->intf);
2944 if (res < 0) {
2945 free_all_mem(tp);
2946 goto out;
2947 }
2948
b5403273 2949 mutex_lock(&tp->control);
2950
9a4be1bd 2951 /* The WORK_ENABLE may be set when autoresume occurs */
2952 if (test_bit(WORK_ENABLE, &tp->flags)) {
2953 clear_bit(WORK_ENABLE, &tp->flags);
2954 usb_kill_urb(tp->intr_urb);
2955 cancel_delayed_work_sync(&tp->schedule);
f4c7476b 2956
2957 /* disable the tx/rx, if the workqueue has enabled them. */
9a4be1bd 2958 if (tp->speed & LINK_STATUS)
2959 tp->rtl_ops.disable(tp);
2960 }
2961
7e9da481 2962 tp->rtl_ops.up(tp);
2963
3d55f44f 2964 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2965 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2966 DUPLEX_FULL);
2967 tp->speed = 0;
2968 netif_carrier_off(netdev);
2969 netif_start_queue(netdev);
2970 set_bit(WORK_ENABLE, &tp->flags);
db8515ef 2971
40a82917 2972 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2973 if (res) {
2974 if (res == -ENODEV)
2975 netif_device_detach(tp->netdev);
4a8deae2
HW
2976 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2977 res);
7e9da481 2978 free_all_mem(tp);
93ffbeab 2979 } else {
2980 tasklet_enable(&tp->tl);
ac718b69 2981 }
2982
b5403273 2983 mutex_unlock(&tp->control);
2984
9a4be1bd 2985 usb_autopm_put_interface(tp->intf);
ac718b69 2986
7e9da481 2987out:
ac718b69 2988 return res;
2989}
2990
2991static int rtl8152_close(struct net_device *netdev)
2992{
2993 struct r8152 *tp = netdev_priv(netdev);
2994 int res = 0;
2995
93ffbeab 2996 tasklet_disable(&tp->tl);
ac718b69 2997 clear_bit(WORK_ENABLE, &tp->flags);
3d55f44f 2998 usb_kill_urb(tp->intr_urb);
ac718b69 2999 cancel_delayed_work_sync(&tp->schedule);
3000 netif_stop_queue(netdev);
9a4be1bd 3001
3002 res = usb_autopm_get_interface(tp->intf);
3003 if (res < 0) {
3004 rtl_drop_queued_tx(tp);
3005 } else {
b5403273 3006 mutex_lock(&tp->control);
3007
b209af99 3008 /* The autosuspend may have been enabled and wouldn't
9a4be1bd 3009 * be disable when autoresume occurs, because the
3010 * netif_running() would be false.
3011 */
923e1ee3 3012 rtl_runtime_suspend_enable(tp, false);
9a4be1bd 3013
9a4be1bd 3014 tp->rtl_ops.down(tp);
b5403273 3015
3016 mutex_unlock(&tp->control);
3017
9a4be1bd 3018 usb_autopm_put_interface(tp->intf);
3019 }
ac718b69 3020
7e9da481 3021 free_all_mem(tp);
3022
ac718b69 3023 return res;
3024}
3025
d24f6134 3026static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3027{
3028 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3029 ocp_reg_write(tp, OCP_EEE_DATA, reg);
3030 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3031}
3032
3033static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3034{
3035 u16 data;
3036
3037 r8152_mmd_indirect(tp, dev, reg);
3038 data = ocp_reg_read(tp, OCP_EEE_DATA);
3039 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3040
3041 return data;
3042}
3043
3044static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
ac718b69 3045{
d24f6134 3046 r8152_mmd_indirect(tp, dev, reg);
3047 ocp_reg_write(tp, OCP_EEE_DATA, data);
3048 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3049}
3050
3051static void r8152_eee_en(struct r8152 *tp, bool enable)
3052{
3053 u16 config1, config2, config3;
45f4a19f 3054 u32 ocp_data;
ac718b69 3055
3056 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3057 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3058 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3059 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3060
3061 if (enable) {
3062 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3063 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3064 config1 |= sd_rise_time(1);
3065 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3066 config3 |= fast_snr(42);
3067 } else {
3068 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3069 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3070 RX_QUIET_EN);
3071 config1 |= sd_rise_time(7);
3072 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3073 config3 |= fast_snr(511);
3074 }
3075
ac718b69 3076 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3077 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3078 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3079 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
ac718b69 3080}
3081
d24f6134 3082static void r8152b_enable_eee(struct r8152 *tp)
3083{
3084 r8152_eee_en(tp, true);
3085 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3086}
3087
3088static void r8153_eee_en(struct r8152 *tp, bool enable)
43779f8d 3089{
3090 u32 ocp_data;
d24f6134 3091 u16 config;
43779f8d 3092
3093 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3094 config = ocp_reg_read(tp, OCP_EEE_CFG);
3095
3096 if (enable) {
3097 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3098 config |= EEE10_EN;
3099 } else {
3100 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3101 config &= ~EEE10_EN;
3102 }
3103
43779f8d 3104 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3105 ocp_reg_write(tp, OCP_EEE_CFG, config);
3106}
3107
3108static void r8153_enable_eee(struct r8152 *tp)
3109{
3110 r8153_eee_en(tp, true);
3111 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
43779f8d 3112}
3113
ac718b69 3114static void r8152b_enable_fc(struct r8152 *tp)
3115{
3116 u16 anar;
3117
3118 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3119 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3120 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3121}
3122
4f1d4d54 3123static void rtl_tally_reset(struct r8152 *tp)
3124{
3125 u32 ocp_data;
3126
3127 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3128 ocp_data |= TALLY_RESET;
3129 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3130}
3131
ac718b69 3132static void r8152b_init(struct r8152 *tp)
3133{
ebc2ec48 3134 u32 ocp_data;
ac718b69 3135
6871438c 3136 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3137 return;
3138
d70b1137 3139 r8152b_disable_aldps(tp);
3140
ac718b69 3141 if (tp->version == RTL_VER_01) {
3142 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3143 ocp_data &= ~LED_MODE_MASK;
3144 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3145 }
3146
00a5e360 3147 r8152_power_cut_en(tp, false);
ac718b69 3148
ac718b69 3149 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3150 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3151 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3152 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3153 ocp_data &= ~MCU_CLK_RATIO_MASK;
3154 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3155 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3156 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3157 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3158 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3159
3160 r8152b_enable_eee(tp);
3161 r8152b_enable_aldps(tp);
3162 r8152b_enable_fc(tp);
4f1d4d54 3163 rtl_tally_reset(tp);
ac718b69 3164
ebc2ec48 3165 /* enable rx aggregation */
ac718b69 3166 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ebc2ec48 3167 ocp_data &= ~RX_AGG_DISABLE;
ac718b69 3168 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3169}
3170
43779f8d 3171static void r8153_init(struct r8152 *tp)
3172{
3173 u32 ocp_data;
3174 int i;
3175
6871438c 3176 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3177 return;
3178
d70b1137 3179 r8153_disable_aldps(tp);
b9702723 3180 r8153_u1u2en(tp, false);
43779f8d 3181
3182 for (i = 0; i < 500; i++) {
3183 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3184 AUTOLOAD_DONE)
3185 break;
3186 msleep(20);
3187 }
3188
3189 for (i = 0; i < 500; i++) {
3190 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3191 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3192 break;
3193 msleep(20);
3194 }
3195
b9702723 3196 r8153_u2p3en(tp, false);
43779f8d 3197
3198 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3199 ocp_data &= ~TIMER11_EN;
3200 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3201
43779f8d 3202 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3203 ocp_data &= ~LED_MODE_MASK;
3204 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3205
3206 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3207 ocp_data &= ~LPM_TIMER_MASK;
3208 if (tp->udev->speed == USB_SPEED_SUPER)
3209 ocp_data |= LPM_TIMER_500US;
3210 else
3211 ocp_data |= LPM_TIMER_500MS;
3212 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3213
3214 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3215 ocp_data &= ~SEN_VAL_MASK;
3216 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3217 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3218
b9702723 3219 r8153_power_cut_en(tp, false);
3220 r8153_u1u2en(tp, true);
43779f8d 3221
43779f8d 3222 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3223 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3224 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3225 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3226 U1U2_SPDWN_EN | L1_SPDWN_EN);
3227 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3228 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3229 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3230 EEE_SPDWN_EN);
3231
3232 r8153_enable_eee(tp);
3233 r8153_enable_aldps(tp);
3234 r8152b_enable_fc(tp);
4f1d4d54 3235 rtl_tally_reset(tp);
43779f8d 3236}
3237
ac718b69 3238static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3239{
3240 struct r8152 *tp = usb_get_intfdata(intf);
6cc69f2a 3241 struct net_device *netdev = tp->netdev;
3242 int ret = 0;
ac718b69 3243
b5403273 3244 mutex_lock(&tp->control);
3245
6cc69f2a 3246 if (PMSG_IS_AUTO(message)) {
3247 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3248 ret = -EBUSY;
3249 goto out1;
3250 }
3251
9a4be1bd 3252 set_bit(SELECTIVE_SUSPEND, &tp->flags);
6cc69f2a 3253 } else {
3254 netif_device_detach(netdev);
3255 }
ac718b69 3256
e3bd1a81 3257 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
ac718b69 3258 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 3259 usb_kill_urb(tp->intr_urb);
445f7f4d 3260 tasklet_disable(&tp->tl);
9a4be1bd 3261 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
445f7f4d 3262 rtl_stop_rx(tp);
9a4be1bd 3263 rtl_runtime_suspend_enable(tp, true);
3264 } else {
6cc69f2a 3265 cancel_delayed_work_sync(&tp->schedule);
9a4be1bd 3266 tp->rtl_ops.down(tp);
9a4be1bd 3267 }
445f7f4d 3268 tasklet_enable(&tp->tl);
ac718b69 3269 }
6cc69f2a 3270out1:
b5403273 3271 mutex_unlock(&tp->control);
3272
6cc69f2a 3273 return ret;
ac718b69 3274}
3275
3276static int rtl8152_resume(struct usb_interface *intf)
3277{
3278 struct r8152 *tp = usb_get_intfdata(intf);
3279
b5403273 3280 mutex_lock(&tp->control);
3281
9a4be1bd 3282 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3283 tp->rtl_ops.init(tp);
3284 netif_device_attach(tp->netdev);
3285 }
3286
ac718b69 3287 if (netif_running(tp->netdev)) {
9a4be1bd 3288 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3289 rtl_runtime_suspend_enable(tp, false);
3290 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
445f7f4d 3291 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3292 if (tp->speed & LINK_STATUS)
445f7f4d 3293 rtl_start_rx(tp);
9a4be1bd 3294 } else {
3295 tp->rtl_ops.up(tp);
3296 rtl8152_set_speed(tp, AUTONEG_ENABLE,
b209af99 3297 tp->mii.supports_gmii ?
3298 SPEED_1000 : SPEED_100,
3299 DUPLEX_FULL);
445f7f4d 3300 tp->speed = 0;
3301 netif_carrier_off(tp->netdev);
3302 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3303 }
40a82917 3304 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
923e1ee3 3305 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3306 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
ac718b69 3307 }
3308
b5403273 3309 mutex_unlock(&tp->control);
3310
ac718b69 3311 return 0;
3312}
3313
21ff2e89 3314static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3315{
3316 struct r8152 *tp = netdev_priv(dev);
3317
9a4be1bd 3318 if (usb_autopm_get_interface(tp->intf) < 0)
3319 return;
3320
b5403273 3321 mutex_lock(&tp->control);
3322
21ff2e89 3323 wol->supported = WAKE_ANY;
3324 wol->wolopts = __rtl_get_wol(tp);
9a4be1bd 3325
b5403273 3326 mutex_unlock(&tp->control);
3327
9a4be1bd 3328 usb_autopm_put_interface(tp->intf);
21ff2e89 3329}
3330
3331static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3332{
3333 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3334 int ret;
3335
3336 ret = usb_autopm_get_interface(tp->intf);
3337 if (ret < 0)
3338 goto out_set_wol;
21ff2e89 3339
b5403273 3340 mutex_lock(&tp->control);
3341
21ff2e89 3342 __rtl_set_wol(tp, wol->wolopts);
3343 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3344
b5403273 3345 mutex_unlock(&tp->control);
3346
9a4be1bd 3347 usb_autopm_put_interface(tp->intf);
3348
3349out_set_wol:
3350 return ret;
21ff2e89 3351}
3352
a5ec27c1 3353static u32 rtl8152_get_msglevel(struct net_device *dev)
3354{
3355 struct r8152 *tp = netdev_priv(dev);
3356
3357 return tp->msg_enable;
3358}
3359
3360static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3361{
3362 struct r8152 *tp = netdev_priv(dev);
3363
3364 tp->msg_enable = value;
3365}
3366
ac718b69 3367static void rtl8152_get_drvinfo(struct net_device *netdev,
3368 struct ethtool_drvinfo *info)
3369{
3370 struct r8152 *tp = netdev_priv(netdev);
3371
b0b46c77 3372 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3373 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
ac718b69 3374 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3375}
3376
3377static
3378int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3379{
3380 struct r8152 *tp = netdev_priv(netdev);
8d4a4d72 3381 int ret;
ac718b69 3382
3383 if (!tp->mii.mdio_read)
3384 return -EOPNOTSUPP;
3385
8d4a4d72 3386 ret = usb_autopm_get_interface(tp->intf);
3387 if (ret < 0)
3388 goto out;
3389
b5403273 3390 mutex_lock(&tp->control);
3391
8d4a4d72 3392 ret = mii_ethtool_gset(&tp->mii, cmd);
3393
b5403273 3394 mutex_unlock(&tp->control);
3395
8d4a4d72 3396 usb_autopm_put_interface(tp->intf);
3397
3398out:
3399 return ret;
ac718b69 3400}
3401
3402static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3403{
3404 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3405 int ret;
3406
3407 ret = usb_autopm_get_interface(tp->intf);
3408 if (ret < 0)
3409 goto out;
ac718b69 3410
b5403273 3411 mutex_lock(&tp->control);
3412
9a4be1bd 3413 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3414
b5403273 3415 mutex_unlock(&tp->control);
3416
9a4be1bd 3417 usb_autopm_put_interface(tp->intf);
3418
3419out:
3420 return ret;
ac718b69 3421}
3422
4f1d4d54 3423static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3424 "tx_packets",
3425 "rx_packets",
3426 "tx_errors",
3427 "rx_errors",
3428 "rx_missed",
3429 "align_errors",
3430 "tx_single_collisions",
3431 "tx_multi_collisions",
3432 "rx_unicast",
3433 "rx_broadcast",
3434 "rx_multicast",
3435 "tx_aborted",
3436 "tx_underrun",
3437};
3438
3439static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3440{
3441 switch (sset) {
3442 case ETH_SS_STATS:
3443 return ARRAY_SIZE(rtl8152_gstrings);
3444 default:
3445 return -EOPNOTSUPP;
3446 }
3447}
3448
3449static void rtl8152_get_ethtool_stats(struct net_device *dev,
3450 struct ethtool_stats *stats, u64 *data)
3451{
3452 struct r8152 *tp = netdev_priv(dev);
3453 struct tally_counter tally;
3454
0b030244 3455 if (usb_autopm_get_interface(tp->intf) < 0)
3456 return;
3457
4f1d4d54 3458 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3459
0b030244 3460 usb_autopm_put_interface(tp->intf);
3461
4f1d4d54 3462 data[0] = le64_to_cpu(tally.tx_packets);
3463 data[1] = le64_to_cpu(tally.rx_packets);
3464 data[2] = le64_to_cpu(tally.tx_errors);
3465 data[3] = le32_to_cpu(tally.rx_errors);
3466 data[4] = le16_to_cpu(tally.rx_missed);
3467 data[5] = le16_to_cpu(tally.align_errors);
3468 data[6] = le32_to_cpu(tally.tx_one_collision);
3469 data[7] = le32_to_cpu(tally.tx_multi_collision);
3470 data[8] = le64_to_cpu(tally.rx_unicast);
3471 data[9] = le64_to_cpu(tally.rx_broadcast);
3472 data[10] = le32_to_cpu(tally.rx_multicast);
3473 data[11] = le16_to_cpu(tally.tx_aborted);
f37119c5 3474 data[12] = le16_to_cpu(tally.tx_underrun);
4f1d4d54 3475}
3476
3477static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3478{
3479 switch (stringset) {
3480 case ETH_SS_STATS:
3481 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3482 break;
3483 }
3484}
3485
df35d283 3486static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3487{
3488 u32 ocp_data, lp, adv, supported = 0;
3489 u16 val;
3490
3491 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3492 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3493
3494 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3495 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3496
3497 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3498 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3499
3500 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3501 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3502
3503 eee->eee_enabled = !!ocp_data;
3504 eee->eee_active = !!(supported & adv & lp);
3505 eee->supported = supported;
3506 eee->advertised = adv;
3507 eee->lp_advertised = lp;
3508
3509 return 0;
3510}
3511
3512static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3513{
3514 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3515
3516 r8152_eee_en(tp, eee->eee_enabled);
3517
3518 if (!eee->eee_enabled)
3519 val = 0;
3520
3521 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3522
3523 return 0;
3524}
3525
3526static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3527{
3528 u32 ocp_data, lp, adv, supported = 0;
3529 u16 val;
3530
3531 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3532 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3533
3534 val = ocp_reg_read(tp, OCP_EEE_ADV);
3535 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3536
3537 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3538 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3539
3540 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3541 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3542
3543 eee->eee_enabled = !!ocp_data;
3544 eee->eee_active = !!(supported & adv & lp);
3545 eee->supported = supported;
3546 eee->advertised = adv;
3547 eee->lp_advertised = lp;
3548
3549 return 0;
3550}
3551
3552static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3553{
3554 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3555
3556 r8153_eee_en(tp, eee->eee_enabled);
3557
3558 if (!eee->eee_enabled)
3559 val = 0;
3560
3561 ocp_reg_write(tp, OCP_EEE_ADV, val);
3562
3563 return 0;
3564}
3565
3566static int
3567rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3568{
3569 struct r8152 *tp = netdev_priv(net);
3570 int ret;
3571
3572 ret = usb_autopm_get_interface(tp->intf);
3573 if (ret < 0)
3574 goto out;
3575
b5403273 3576 mutex_lock(&tp->control);
3577
df35d283 3578 ret = tp->rtl_ops.eee_get(tp, edata);
3579
b5403273 3580 mutex_unlock(&tp->control);
3581
df35d283 3582 usb_autopm_put_interface(tp->intf);
3583
3584out:
3585 return ret;
3586}
3587
3588static int
3589rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3590{
3591 struct r8152 *tp = netdev_priv(net);
3592 int ret;
3593
3594 ret = usb_autopm_get_interface(tp->intf);
3595 if (ret < 0)
3596 goto out;
3597
b5403273 3598 mutex_lock(&tp->control);
3599
df35d283 3600 ret = tp->rtl_ops.eee_set(tp, edata);
9d31a7b9 3601 if (!ret)
3602 ret = mii_nway_restart(&tp->mii);
df35d283 3603
b5403273 3604 mutex_unlock(&tp->control);
3605
df35d283 3606 usb_autopm_put_interface(tp->intf);
3607
3608out:
3609 return ret;
3610}
3611
8884f507 3612static int rtl8152_nway_reset(struct net_device *dev)
3613{
3614 struct r8152 *tp = netdev_priv(dev);
3615 int ret;
3616
3617 ret = usb_autopm_get_interface(tp->intf);
3618 if (ret < 0)
3619 goto out;
3620
3621 mutex_lock(&tp->control);
3622
3623 ret = mii_nway_restart(&tp->mii);
3624
3625 mutex_unlock(&tp->control);
3626
3627 usb_autopm_put_interface(tp->intf);
3628
3629out:
3630 return ret;
3631}
3632
ac718b69 3633static struct ethtool_ops ops = {
3634 .get_drvinfo = rtl8152_get_drvinfo,
3635 .get_settings = rtl8152_get_settings,
3636 .set_settings = rtl8152_set_settings,
3637 .get_link = ethtool_op_get_link,
8884f507 3638 .nway_reset = rtl8152_nway_reset,
a5ec27c1 3639 .get_msglevel = rtl8152_get_msglevel,
3640 .set_msglevel = rtl8152_set_msglevel,
21ff2e89 3641 .get_wol = rtl8152_get_wol,
3642 .set_wol = rtl8152_set_wol,
4f1d4d54 3643 .get_strings = rtl8152_get_strings,
3644 .get_sset_count = rtl8152_get_sset_count,
3645 .get_ethtool_stats = rtl8152_get_ethtool_stats,
df35d283 3646 .get_eee = rtl_ethtool_get_eee,
3647 .set_eee = rtl_ethtool_set_eee,
ac718b69 3648};
3649
3650static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3651{
3652 struct r8152 *tp = netdev_priv(netdev);
3653 struct mii_ioctl_data *data = if_mii(rq);
9a4be1bd 3654 int res;
3655
6871438c 3656 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3657 return -ENODEV;
3658
9a4be1bd 3659 res = usb_autopm_get_interface(tp->intf);
3660 if (res < 0)
3661 goto out;
ac718b69 3662
3663 switch (cmd) {
3664 case SIOCGMIIPHY:
3665 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3666 break;
3667
3668 case SIOCGMIIREG:
b5403273 3669 mutex_lock(&tp->control);
ac718b69 3670 data->val_out = r8152_mdio_read(tp, data->reg_num);
b5403273 3671 mutex_unlock(&tp->control);
ac718b69 3672 break;
3673
3674 case SIOCSMIIREG:
3675 if (!capable(CAP_NET_ADMIN)) {
3676 res = -EPERM;
3677 break;
3678 }
b5403273 3679 mutex_lock(&tp->control);
ac718b69 3680 r8152_mdio_write(tp, data->reg_num, data->val_in);
b5403273 3681 mutex_unlock(&tp->control);
ac718b69 3682 break;
3683
3684 default:
3685 res = -EOPNOTSUPP;
3686 }
3687
9a4be1bd 3688 usb_autopm_put_interface(tp->intf);
3689
3690out:
ac718b69 3691 return res;
3692}
3693
69b4b7a4 3694static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3695{
3696 struct r8152 *tp = netdev_priv(dev);
3697
3698 switch (tp->version) {
3699 case RTL_VER_01:
3700 case RTL_VER_02:
3701 return eth_change_mtu(dev, new_mtu);
3702 default:
3703 break;
3704 }
3705
3706 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3707 return -EINVAL;
3708
3709 dev->mtu = new_mtu;
3710
3711 return 0;
3712}
3713
ac718b69 3714static const struct net_device_ops rtl8152_netdev_ops = {
3715 .ndo_open = rtl8152_open,
3716 .ndo_stop = rtl8152_close,
3717 .ndo_do_ioctl = rtl8152_ioctl,
3718 .ndo_start_xmit = rtl8152_start_xmit,
3719 .ndo_tx_timeout = rtl8152_tx_timeout,
c5554298 3720 .ndo_set_features = rtl8152_set_features,
ac718b69 3721 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3722 .ndo_set_mac_address = rtl8152_set_mac_address,
69b4b7a4 3723 .ndo_change_mtu = rtl8152_change_mtu,
ac718b69 3724 .ndo_validate_addr = eth_validate_addr,
a5e31255 3725 .ndo_features_check = rtl8152_features_check,
ac718b69 3726};
3727
3728static void r8152b_get_version(struct r8152 *tp)
3729{
3730 u32 ocp_data;
3731 u16 version;
3732
3733 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3734 version = (u16)(ocp_data & VERSION_MASK);
3735
3736 switch (version) {
3737 case 0x4c00:
3738 tp->version = RTL_VER_01;
3739 break;
3740 case 0x4c10:
3741 tp->version = RTL_VER_02;
3742 break;
43779f8d 3743 case 0x5c00:
3744 tp->version = RTL_VER_03;
3745 tp->mii.supports_gmii = 1;
3746 break;
3747 case 0x5c10:
3748 tp->version = RTL_VER_04;
3749 tp->mii.supports_gmii = 1;
3750 break;
3751 case 0x5c20:
3752 tp->version = RTL_VER_05;
3753 tp->mii.supports_gmii = 1;
3754 break;
ac718b69 3755 default:
3756 netif_info(tp, probe, tp->netdev,
3757 "Unknown version 0x%04x\n", version);
3758 break;
3759 }
3760}
3761
e3fe0b1a 3762static void rtl8152_unload(struct r8152 *tp)
3763{
6871438c 3764 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3765 return;
3766
00a5e360 3767 if (tp->version != RTL_VER_01)
3768 r8152_power_cut_en(tp, true);
e3fe0b1a 3769}
3770
43779f8d 3771static void rtl8153_unload(struct r8152 *tp)
3772{
6871438c 3773 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3774 return;
3775
49be1723 3776 r8153_power_cut_en(tp, false);
43779f8d 3777}
3778
55b65475 3779static int rtl_ops_init(struct r8152 *tp)
c81229c9 3780{
3781 struct rtl_ops *ops = &tp->rtl_ops;
55b65475 3782 int ret = 0;
3783
3784 switch (tp->version) {
3785 case RTL_VER_01:
3786 case RTL_VER_02:
3787 ops->init = r8152b_init;
3788 ops->enable = rtl8152_enable;
3789 ops->disable = rtl8152_disable;
3790 ops->up = rtl8152_up;
3791 ops->down = rtl8152_down;
3792 ops->unload = rtl8152_unload;
3793 ops->eee_get = r8152_get_eee;
3794 ops->eee_set = r8152_set_eee;
43779f8d 3795 break;
3796
55b65475 3797 case RTL_VER_03:
3798 case RTL_VER_04:
3799 case RTL_VER_05:
3800 ops->init = r8153_init;
3801 ops->enable = rtl8153_enable;
3802 ops->disable = rtl8153_disable;
3803 ops->up = rtl8153_up;
3804 ops->down = rtl8153_down;
3805 ops->unload = rtl8153_unload;
3806 ops->eee_get = r8153_get_eee;
3807 ops->eee_set = r8153_set_eee;
c81229c9 3808 break;
3809
3810 default:
55b65475 3811 ret = -ENODEV;
3812 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
c81229c9 3813 break;
3814 }
3815
3816 return ret;
3817}
3818
ac718b69 3819static int rtl8152_probe(struct usb_interface *intf,
3820 const struct usb_device_id *id)
3821{
3822 struct usb_device *udev = interface_to_usbdev(intf);
3823 struct r8152 *tp;
3824 struct net_device *netdev;
ebc2ec48 3825 int ret;
ac718b69 3826
10c32717 3827 if (udev->actconfig->desc.bConfigurationValue != 1) {
3828 usb_driver_set_configuration(udev, 1);
3829 return -ENODEV;
3830 }
3831
3832 usb_reset_device(udev);
ac718b69 3833 netdev = alloc_etherdev(sizeof(struct r8152));
3834 if (!netdev) {
4a8deae2 3835 dev_err(&intf->dev, "Out of memory\n");
ac718b69 3836 return -ENOMEM;
3837 }
3838
ebc2ec48 3839 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 3840 tp = netdev_priv(netdev);
3841 tp->msg_enable = 0x7FFF;
3842
e3ad412a 3843 tp->udev = udev;
3844 tp->netdev = netdev;
3845 tp->intf = intf;
3846
82cf94cb 3847 r8152b_get_version(tp);
55b65475 3848 ret = rtl_ops_init(tp);
31ca1dec 3849 if (ret)
3850 goto out;
c81229c9 3851
ebc2ec48 3852 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
b5403273 3853 mutex_init(&tp->control);
ac718b69 3854 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3855
ac718b69 3856 netdev->netdev_ops = &rtl8152_netdev_ops;
3857 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 3858
60c89071 3859 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 3860 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
c5554298 3861 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3862 NETIF_F_HW_VLAN_CTAG_TX;
60c89071 3863 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 3864 NETIF_F_TSO | NETIF_F_FRAGLIST |
c5554298 3865 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3866 NETIF_F_HW_VLAN_CTAG_RX |
3867 NETIF_F_HW_VLAN_CTAG_TX;
3868 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3869 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3870 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
db8515ef 3871
7ad24ea4 3872 netdev->ethtool_ops = &ops;
60c89071 3873 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
ac718b69 3874
3875 tp->mii.dev = netdev;
3876 tp->mii.mdio_read = read_mii_word;
3877 tp->mii.mdio_write = write_mii_word;
3878 tp->mii.phy_id_mask = 0x3f;
3879 tp->mii.reg_num_mask = 0x1f;
3880 tp->mii.phy_id = R8152_PHY_ID;
ac718b69 3881
9a4be1bd 3882 intf->needs_remote_wakeup = 1;
3883
c81229c9 3884 tp->rtl_ops.init(tp);
ac718b69 3885 set_ethernet_addr(tp);
3886
ac718b69 3887 usb_set_intfdata(intf, tp);
ac718b69 3888
ebc2ec48 3889 ret = register_netdev(netdev);
3890 if (ret != 0) {
4a8deae2 3891 netif_err(tp, probe, netdev, "couldn't register the device\n");
ebc2ec48 3892 goto out1;
ac718b69 3893 }
3894
21ff2e89 3895 tp->saved_wolopts = __rtl_get_wol(tp);
3896 if (tp->saved_wolopts)
3897 device_set_wakeup_enable(&udev->dev, true);
3898 else
3899 device_set_wakeup_enable(&udev->dev, false);
3900
93ffbeab 3901 tasklet_disable(&tp->tl);
3902
4a8deae2 3903 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
ac718b69 3904
3905 return 0;
3906
ac718b69 3907out1:
ebc2ec48 3908 usb_set_intfdata(intf, NULL);
93ffbeab 3909 tasklet_kill(&tp->tl);
ac718b69 3910out:
3911 free_netdev(netdev);
ebc2ec48 3912 return ret;
ac718b69 3913}
3914
ac718b69 3915static void rtl8152_disconnect(struct usb_interface *intf)
3916{
3917 struct r8152 *tp = usb_get_intfdata(intf);
3918
3919 usb_set_intfdata(intf, NULL);
3920 if (tp) {
f561de33 3921 struct usb_device *udev = tp->udev;
3922
3923 if (udev->state == USB_STATE_NOTATTACHED)
3924 set_bit(RTL8152_UNPLUG, &tp->flags);
3925
ac718b69 3926 tasklet_kill(&tp->tl);
3927 unregister_netdev(tp->netdev);
c81229c9 3928 tp->rtl_ops.unload(tp);
ac718b69 3929 free_netdev(tp->netdev);
3930 }
3931}
3932
d9a28c5b 3933#define REALTEK_USB_DEVICE(vend, prod) \
3934 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
3935 USB_DEVICE_ID_MATCH_INT_CLASS, \
3936 .idVendor = (vend), \
3937 .idProduct = (prod), \
3938 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
3939}, \
3940{ \
3941 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
3942 USB_DEVICE_ID_MATCH_DEVICE, \
3943 .idVendor = (vend), \
3944 .idProduct = (prod), \
3945 .bInterfaceClass = USB_CLASS_COMM, \
3946 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
3947 .bInterfaceProtocol = USB_CDC_PROTO_NONE
3948
ac718b69 3949/* table of devices that work with this driver */
3950static struct usb_device_id rtl8152_table[] = {
d9a28c5b 3951 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
3952 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
3953 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
ac718b69 3954 {}
3955};
3956
3957MODULE_DEVICE_TABLE(usb, rtl8152_table);
3958
3959static struct usb_driver rtl8152_driver = {
3960 .name = MODULENAME,
ebc2ec48 3961 .id_table = rtl8152_table,
ac718b69 3962 .probe = rtl8152_probe,
3963 .disconnect = rtl8152_disconnect,
ac718b69 3964 .suspend = rtl8152_suspend,
ebc2ec48 3965 .resume = rtl8152_resume,
3966 .reset_resume = rtl8152_resume,
9a4be1bd 3967 .supports_autosuspend = 1,
a634782f 3968 .disable_hub_initiated_lpm = 1,
ac718b69 3969};
3970
b4236daa 3971module_usb_driver(rtl8152_driver);
ac718b69 3972
3973MODULE_AUTHOR(DRIVER_AUTHOR);
3974MODULE_DESCRIPTION(DRIVER_DESC);
3975MODULE_LICENSE("GPL");