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asix: Factor out common code
[linux-2.6-block.git] / drivers / net / usb / asix_devices.c
CommitLineData
2e55cc72
DB		 1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
933a27d3 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
2e55cc72 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
933a27d3 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
2e55cc72
DB		 6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
607740bc 23#include "asix.h"
933a27d3
DH		 24
25#define PHY_MODE_MARVELL 0x0000
26#define MII_MARVELL_LED_CTRL 0x0018
27#define MII_MARVELL_STATUS 0x001b
28#define MII_MARVELL_CTRL 0x0014
29
30#define MARVELL_LED_MANUAL 0x0019
31
32#define MARVELL_STATUS_HWCFG 0x0004
33
34#define MARVELL_CTRL_TXDELAY 0x0002
35#define MARVELL_CTRL_RXDELAY 0x0080
2e55cc72 36
3486140e 37#define PHY_MODE_RTL8211CL 0x000C
610d885d 38
2e55cc72 39struct ax88172_int_data {
51bf2976 40 __le16 res1;
2e55cc72 41 u8 link;
51bf2976 42 __le16 res2;
2e55cc72 43 u8 status;
51bf2976 44 __le16 res3;
ba2d3587 45} __packed;
2e55cc72 46
933a27d3
DH		 47static void asix_status(struct usbnet *dev, struct urb *urb)
48{
49 struct ax88172_int_data *event;
50 int link;
51
52 if (urb->actual_length < 8)
53 return;
54
55 event = urb->transfer_buffer;
56 link = event->link & 0x01;
57 if (netif_carrier_ok(dev->net) != link) {
58 if (link) {
59 netif_carrier_on(dev->net);
60 usbnet_defer_kevent (dev, EVENT_LINK_RESET );
61 } else
62 netif_carrier_off(dev->net);
60b86755 63 netdev_dbg(dev->net, "Link Status is: %d\n", link);
933a27d3
DH		 64 }
65}
66
933a27d3
DH		 67/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
68static u32 asix_get_phyid(struct usbnet *dev)
2e55cc72 69{
933a27d3
DH		 70 int phy_reg;
71 u32 phy_id;
a77929a2 72 int i;
2e55cc72 73
a77929a2
GG		 74 /* Poll for the rare case the FW or phy isn't ready yet. */
75 for (i = 0; i < 100; i++) {
76 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
77 if (phy_reg != 0 && phy_reg != 0xFFFF)
78 break;
79 mdelay(1);
80 }
81
82 if (phy_reg <= 0 || phy_reg == 0xFFFF)
933a27d3 83 return 0;
2e55cc72 84
933a27d3 85 phy_id = (phy_reg & 0xffff) << 16;
2e55cc72 86
933a27d3
DH		 87 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
88 if (phy_reg < 0)
89 return 0;
90
91 phy_id |= (phy_reg & 0xffff);
92
93 return phy_id;
2e55cc72
DB		 94}
95
933a27d3
DH		 96static u32 asix_get_link(struct net_device *net)
97{
98 struct usbnet *dev = netdev_priv(net);
99
100 return mii_link_ok(&dev->mii);
101}
102
103static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
104{
105 struct usbnet *dev = netdev_priv(net);
106
107 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
108}
109
110/* We need to override some ethtool_ops so we require our
111 own structure so we don't interfere with other usbnet
112 devices that may be connected at the same time. */
0fc0b732 113static const struct ethtool_ops ax88172_ethtool_ops = {
933a27d3
DH		 114 .get_drvinfo = asix_get_drvinfo,
115 .get_link = asix_get_link,
933a27d3 116 .get_msglevel = usbnet_get_msglevel,
2e55cc72 117 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 118 .get_wol = asix_get_wol,
119 .set_wol = asix_set_wol,
120 .get_eeprom_len = asix_get_eeprom_len,
121 .get_eeprom = asix_get_eeprom,
c41286fd
AB		 122 .get_settings = usbnet_get_settings,
123 .set_settings = usbnet_set_settings,
124 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 125};
126
933a27d3 127static void ax88172_set_multicast(struct net_device *net)
2e55cc72
DB		 128{
129 struct usbnet *dev = netdev_priv(net);
933a27d3
DH		 130 struct asix_data *data = (struct asix_data *)&dev->data;
131 u8 rx_ctl = 0x8c;
2e55cc72 132
933a27d3
DH		 133 if (net->flags & IFF_PROMISC) {
134 rx_ctl |= 0x01;
8e95a202 135 } else if (net->flags & IFF_ALLMULTI ||
4cd24eaf 136 netdev_mc_count(net) > AX_MAX_MCAST) {
933a27d3 137 rx_ctl |= 0x02;
4cd24eaf 138 } else if (netdev_mc_empty(net)) {
933a27d3
DH		 139 /* just broadcast and directed */
140 } else {
141 /* We use the 20 byte dev->data
142 * for our 8 byte filter buffer
143 * to avoid allocating memory that
144 * is tricky to free later */
22bedad3 145 struct netdev_hw_addr *ha;
933a27d3 146 u32 crc_bits;
933a27d3
DH		 147
148 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
149
150 /* Build the multicast hash filter. */
22bedad3
JP		 151 netdev_for_each_mc_addr(ha, net) {
152 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
933a27d3
DH		 153 data->multi_filter[crc_bits >> 3] |=
154 1 << (crc_bits & 7);
933a27d3
DH		 155 }
156
157 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
158 AX_MCAST_FILTER_SIZE, data->multi_filter);
159
160 rx_ctl |= 0x10;
161 }
162
163 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
164}
165
166static int ax88172_link_reset(struct usbnet *dev)
167{
168 u8 mode;
8ae6daca 169 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 170
171 mii_check_media(&dev->mii, 1, 1);
172 mii_ethtool_gset(&dev->mii, &ecmd);
173 mode = AX88172_MEDIUM_DEFAULT;
174
175 if (ecmd.duplex != DUPLEX_FULL)
176 mode |= ~AX88172_MEDIUM_FD;
177
8ae6daca
DD		 178 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
179 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3
DH		 180
181 asix_write_medium_mode(dev, mode);
182
183 return 0;
2e55cc72
DB		 184}
185
1703338c
SH		 186static const struct net_device_ops ax88172_netdev_ops = {
187 .ndo_open = usbnet_open,
188 .ndo_stop = usbnet_stop,
189 .ndo_start_xmit = usbnet_start_xmit,
190 .ndo_tx_timeout = usbnet_tx_timeout,
191 .ndo_change_mtu = usbnet_change_mtu,
192 .ndo_set_mac_address = eth_mac_addr,
193 .ndo_validate_addr = eth_validate_addr,
194 .ndo_do_ioctl = asix_ioctl,
afc4b13d 195 .ndo_set_rx_mode = ax88172_set_multicast,
1703338c
SH		 196};
197
48b1be6a 198static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
2e55cc72
DB		 199{
200 int ret = 0;
51bf2976 201 u8 buf[ETH_ALEN];
2e55cc72
DB		 202 int i;
203 unsigned long gpio_bits = dev->driver_info->data;
933a27d3
DH		 204 struct asix_data *data = (struct asix_data *)&dev->data;
205
206 data->eeprom_len = AX88172_EEPROM_LEN;
2e55cc72
DB		 207
208 usbnet_get_endpoints(dev,intf);
209
2e55cc72
DB		 210 /* Toggle the GPIOs in a manufacturer/model specific way */
211 for (i = 2; i >= 0; i--) {
83e1b918
GG		 212 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
213 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL);
214 if (ret < 0)
51bf2976 215 goto out;
2e55cc72
DB		 216 msleep(5);
217 }
218
83e1b918
GG		 219 ret = asix_write_rx_ctl(dev, 0x80);
220 if (ret < 0)
51bf2976 221 goto out;
2e55cc72
DB		 222
223 /* Get the MAC address */
83e1b918
GG		 224 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
225 if (ret < 0) {
2e55cc72 226 dbg("read AX_CMD_READ_NODE_ID failed: %d", ret);
51bf2976 227 goto out;
2e55cc72
DB		 228 }
229 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
230
2e55cc72
DB		 231 /* Initialize MII structure */
232 dev->mii.dev = dev->net;
48b1be6a
DH		 233 dev->mii.mdio_read = asix_mdio_read;
234 dev->mii.mdio_write = asix_mdio_write;
2e55cc72
DB		 235 dev->mii.phy_id_mask = 0x3f;
236 dev->mii.reg_num_mask = 0x1f;
933a27d3 237 dev->mii.phy_id = asix_get_phy_addr(dev);
2e55cc72 238
1703338c 239 dev->net->netdev_ops = &ax88172_netdev_ops;
48b1be6a 240 dev->net->ethtool_ops = &ax88172_ethtool_ops;
95162d65
ED		 241 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
242 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
2e55cc72 243
933a27d3
DH		 244 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
245 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 246 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
247 mii_nway_restart(&dev->mii);
248
249 return 0;
51bf2976
AV		 250
251out:
2e55cc72
DB		 252 return ret;
253}
254
0fc0b732 255static const struct ethtool_ops ax88772_ethtool_ops = {
48b1be6a 256 .get_drvinfo = asix_get_drvinfo,
933a27d3 257 .get_link = asix_get_link,
2e55cc72
DB		 258 .get_msglevel = usbnet_get_msglevel,
259 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 260 .get_wol = asix_get_wol,
261 .set_wol = asix_set_wol,
262 .get_eeprom_len = asix_get_eeprom_len,
263 .get_eeprom = asix_get_eeprom,
c41286fd
AB		 264 .get_settings = usbnet_get_settings,
265 .set_settings = usbnet_set_settings,
266 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 267};
268
933a27d3
DH		 269static int ax88772_link_reset(struct usbnet *dev)
270{
271 u16 mode;
8ae6daca 272 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 273
274 mii_check_media(&dev->mii, 1, 1);
275 mii_ethtool_gset(&dev->mii, &ecmd);
276 mode = AX88772_MEDIUM_DEFAULT;
277
8ae6daca 278 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
933a27d3
DH		 279 mode &= ~AX_MEDIUM_PS;
280
281 if (ecmd.duplex != DUPLEX_FULL)
282 mode &= ~AX_MEDIUM_FD;
283
8ae6daca
DD		 284 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
285 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3
DH		 286
287 asix_write_medium_mode(dev, mode);
288
289 return 0;
290}
291
4ad1438f 292static int ax88772_reset(struct usbnet *dev)
2e55cc72 293{
8ef66bdc 294 struct asix_data *data = (struct asix_data *)&dev->data;
d0ffff8f 295 int ret, embd_phy;
933a27d3 296 u16 rx_ctl;
2e55cc72 297
83e1b918
GG		 298 ret = asix_write_gpio(dev,
299 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5);
300 if (ret < 0)
51bf2976 301 goto out;
2e55cc72 302
d0ffff8f 303 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
4ad1438f 304
83e1b918
GG		 305 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
306 if (ret < 0) {
2e55cc72 307 dbg("Select PHY #1 failed: %d", ret);
51bf2976 308 goto out;
2e55cc72
DB		 309 }
310
83e1b918
GG		 311 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
312 if (ret < 0)
51bf2976 313 goto out;
2e55cc72
DB		 314
315 msleep(150);
83e1b918
GG		 316
317 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
318 if (ret < 0)
51bf2976 319 goto out;
2e55cc72
DB		 320
321 msleep(150);
4ad1438f 322
d0ffff8f 323 if (embd_phy) {
83e1b918
GG		 324 ret = asix_sw_reset(dev, AX_SWRESET_IPRL);
325 if (ret < 0)
51bf2976 326 goto out;
83e1b918
GG		 327 } else {
328 ret = asix_sw_reset(dev, AX_SWRESET_PRTE);
329 if (ret < 0)
51bf2976 330 goto out;
d0ffff8f 331 }
2e55cc72
DB		 332
333 msleep(150);
933a27d3
DH		 334 rx_ctl = asix_read_rx_ctl(dev);
335 dbg("RX_CTL is 0x%04x after software reset", rx_ctl);
83e1b918
GG		 336 ret = asix_write_rx_ctl(dev, 0x0000);
337 if (ret < 0)
51bf2976 338 goto out;
2e55cc72 339
933a27d3
DH		 340 rx_ctl = asix_read_rx_ctl(dev);
341 dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl);
342
83e1b918
GG		 343 ret = asix_sw_reset(dev, AX_SWRESET_PRL);
344 if (ret < 0)
51bf2976 345 goto out;
2e55cc72 346
2e55cc72 347 msleep(150);
48b1be6a 348
83e1b918
GG		 349 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL);
350 if (ret < 0)
51bf2976 351 goto out;
2e55cc72 352
48b1be6a 353 msleep(150);
2e55cc72 354
933a27d3
DH		 355 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
356 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 357 ADVERTISE_ALL | ADVERTISE_CSMA);
358 mii_nway_restart(&dev->mii);
359
83e1b918
GG		 360 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT);
361 if (ret < 0)
51bf2976 362 goto out;
2e55cc72 363
83e1b918 364 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
2e55cc72 365 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
83e1b918
GG		 366 AX88772_IPG2_DEFAULT, 0, NULL);
367 if (ret < 0) {
2e55cc72 368 dbg("Write IPG,IPG1,IPG2 failed: %d", ret);
51bf2976 369 goto out;
2e55cc72 370 }
2e55cc72 371
8ef66bdc
JK		 372 /* Rewrite MAC address */
373 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
374 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
375 data->mac_addr);
376 if (ret < 0)
377 goto out;
378
2e55cc72 379 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
83e1b918
GG		 380 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
381 if (ret < 0)
51bf2976 382 goto out;
2e55cc72 383
933a27d3
DH		 384 rx_ctl = asix_read_rx_ctl(dev);
385 dbg("RX_CTL is 0x%04x after all initializations", rx_ctl);
386
387 rx_ctl = asix_read_medium_status(dev);
388 dbg("Medium Status is 0x%04x after all initializations", rx_ctl);
389
4ad1438f
GG		 390 return 0;
391
392out:
393 return ret;
394
395}
396
397static const struct net_device_ops ax88772_netdev_ops = {
398 .ndo_open = usbnet_open,
399 .ndo_stop = usbnet_stop,
400 .ndo_start_xmit = usbnet_start_xmit,
401 .ndo_tx_timeout = usbnet_tx_timeout,
402 .ndo_change_mtu = usbnet_change_mtu,
403 .ndo_set_mac_address = asix_set_mac_address,
404 .ndo_validate_addr = eth_validate_addr,
405 .ndo_do_ioctl = asix_ioctl,
406 .ndo_set_rx_mode = asix_set_multicast,
407};
408
409static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
410{
d3665188 411 int ret, embd_phy;
4ad1438f
GG		 412 struct asix_data *data = (struct asix_data *)&dev->data;
413 u8 buf[ETH_ALEN];
414 u32 phyid;
415
416 data->eeprom_len = AX88772_EEPROM_LEN;
417
418 usbnet_get_endpoints(dev,intf);
419
420 /* Get the MAC address */
83e1b918
GG		 421 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
422 if (ret < 0) {
4ad1438f 423 dbg("Failed to read MAC address: %d", ret);
83e1b918 424 return ret;
4ad1438f
GG		 425 }
426 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
427
428 /* Initialize MII structure */
429 dev->mii.dev = dev->net;
430 dev->mii.mdio_read = asix_mdio_read;
431 dev->mii.mdio_write = asix_mdio_write;
432 dev->mii.phy_id_mask = 0x1f;
433 dev->mii.reg_num_mask = 0x1f;
434 dev->mii.phy_id = asix_get_phy_addr(dev);
435
4ad1438f
GG		 436 dev->net->netdev_ops = &ax88772_netdev_ops;
437 dev->net->ethtool_ops = &ax88772_ethtool_ops;
95162d65
ED		 438 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
439 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
4ad1438f 440
d3665188
GG		 441 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
442
443 /* Reset the PHY to normal operation mode */
444 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
445 if (ret < 0) {
446 dbg("Select PHY #1 failed: %d", ret);
447 return ret;
448 }
449
450 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
83e1b918
GG		 451 if (ret < 0)
452 return ret;
4ad1438f 453
d3665188
GG		 454 msleep(150);
455
456 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
457 if (ret < 0)
458 return ret;
459
460 msleep(150);
461
462 ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE);
463
464 /* Read PHYID register *AFTER* the PHY was reset properly */
465 phyid = asix_get_phyid(dev);
466 dbg("PHYID=0x%08x", phyid);
467
2e55cc72
DB		 468 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
469 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
470 /* hard_mtu is still the default - the device does not support
471 jumbo eth frames */
472 dev->rx_urb_size = 2048;
473 }
83e1b918 474
2e55cc72 475 return 0;
2e55cc72
DB		 476}
477
bc689c97 478static const struct ethtool_ops ax88178_ethtool_ops = {
933a27d3
DH		 479 .get_drvinfo = asix_get_drvinfo,
480 .get_link = asix_get_link,
933a27d3
DH		 481 .get_msglevel = usbnet_get_msglevel,
482 .set_msglevel = usbnet_set_msglevel,
483 .get_wol = asix_get_wol,
484 .set_wol = asix_set_wol,
485 .get_eeprom_len = asix_get_eeprom_len,
486 .get_eeprom = asix_get_eeprom,
c41286fd
AB		 487 .get_settings = usbnet_get_settings,
488 .set_settings = usbnet_set_settings,
489 .nway_reset = usbnet_nway_reset,
933a27d3
DH		 490};
491
492static int marvell_phy_init(struct usbnet *dev)
2e55cc72 493{
933a27d3
DH		 494 struct asix_data *data = (struct asix_data *)&dev->data;
495 u16 reg;
2e55cc72 496
60b86755 497 netdev_dbg(dev->net, "marvell_phy_init()\n");
2e55cc72 498
933a27d3 499 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
60b86755 500 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
2e55cc72 501
933a27d3
DH		 502 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
503 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
2e55cc72 504
933a27d3
DH		 505 if (data->ledmode) {
506 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
507 MII_MARVELL_LED_CTRL);
60b86755 508 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
2e55cc72 509
933a27d3
DH		 510 reg &= 0xf8ff;
511 reg |= (1 + 0x0100);
512 asix_mdio_write(dev->net, dev->mii.phy_id,
513 MII_MARVELL_LED_CTRL, reg);
2e55cc72 514
933a27d3
DH		 515 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
516 MII_MARVELL_LED_CTRL);
60b86755 517 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
933a27d3
DH		 518 reg &= 0xfc0f;
519 }
2e55cc72 520
933a27d3
DH		 521 return 0;
522}
523
610d885d
GG		 524static int rtl8211cl_phy_init(struct usbnet *dev)
525{
526 struct asix_data *data = (struct asix_data *)&dev->data;
527
528 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
529
530 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
531 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
532 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
533 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
534 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
535
536 if (data->ledmode == 12) {
537 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
538 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
539 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
540 }
541
542 return 0;
543}
544
933a27d3
DH		 545static int marvell_led_status(struct usbnet *dev, u16 speed)
546{
547 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
548
60b86755 549 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
933a27d3
DH		 550
551 /* Clear out the center LED bits - 0x03F0 */
552 reg &= 0xfc0f;
553
554 switch (speed) {
555 case SPEED_1000:
556 reg |= 0x03e0;
557 break;
558 case SPEED_100:
559 reg |= 0x03b0;
560 break;
561 default:
562 reg |= 0x02f0;
2e55cc72
DB		 563 }
564
60b86755 565 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
933a27d3
DH		 566 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
567
568 return 0;
569}
570
610d885d
GG		 571static int ax88178_reset(struct usbnet *dev)
572{
573 struct asix_data *data = (struct asix_data *)&dev->data;
574 int ret;
575 __le16 eeprom;
576 u8 status;
577 int gpio0 = 0;
b2d3ad29 578 u32 phyid;
610d885d
GG		 579
580 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status);
581 dbg("GPIO Status: 0x%04x", status);
582
583 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
584 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
585 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
586
587 dbg("EEPROM index 0x17 is 0x%04x", eeprom);
588
589 if (eeprom == cpu_to_le16(0xffff)) {
590 data->phymode = PHY_MODE_MARVELL;
591 data->ledmode = 0;
592 gpio0 = 1;
593 } else {
b2d3ad29 594 data->phymode = le16_to_cpu(eeprom) & 0x7F;
610d885d
GG		 595 data->ledmode = le16_to_cpu(eeprom) >> 8;
596 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
597 }
598 dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode);
599
b2d3ad29 600 /* Power up external GigaPHY through AX88178 GPIO pin */
610d885d
GG		 601 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
602 if ((le16_to_cpu(eeprom) >> 8) != 1) {
603 asix_write_gpio(dev, 0x003c, 30);
604 asix_write_gpio(dev, 0x001c, 300);
605 asix_write_gpio(dev, 0x003c, 30);
606 } else {
607 dbg("gpio phymode == 1 path");
608 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
609 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
610 }
611
b2d3ad29
GG		 612 /* Read PHYID register *AFTER* powering up PHY */
613 phyid = asix_get_phyid(dev);
614 dbg("PHYID=0x%08x", phyid);
615
616 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
617 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL);
618
610d885d
GG		 619 asix_sw_reset(dev, 0);
620 msleep(150);
621
622 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
623 msleep(150);
624
625 asix_write_rx_ctl(dev, 0);
626
627 if (data->phymode == PHY_MODE_MARVELL) {
628 marvell_phy_init(dev);
629 msleep(60);
630 } else if (data->phymode == PHY_MODE_RTL8211CL)
631 rtl8211cl_phy_init(dev);
632
633 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
634 BMCR_RESET | BMCR_ANENABLE);
635 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
636 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
637 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
638 ADVERTISE_1000FULL);
639
640 mii_nway_restart(&dev->mii);
641
83e1b918
GG		 642 ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT);
643 if (ret < 0)
644 return ret;
610d885d 645
71bc5d94
JK		 646 /* Rewrite MAC address */
647 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
648 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
649 data->mac_addr);
650 if (ret < 0)
651 return ret;
652
83e1b918
GG		 653 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
654 if (ret < 0)
655 return ret;
610d885d
GG		 656
657 return 0;
610d885d
GG		 658}
659
933a27d3
DH		 660static int ax88178_link_reset(struct usbnet *dev)
661{
662 u16 mode;
8ae6daca 663 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3 664 struct asix_data *data = (struct asix_data *)&dev->data;
8ae6daca 665 u32 speed;
933a27d3 666
60b86755 667 netdev_dbg(dev->net, "ax88178_link_reset()\n");
933a27d3
DH		 668
669 mii_check_media(&dev->mii, 1, 1);
670 mii_ethtool_gset(&dev->mii, &ecmd);
671 mode = AX88178_MEDIUM_DEFAULT;
8ae6daca 672 speed = ethtool_cmd_speed(&ecmd);
933a27d3 673
8ae6daca 674 if (speed == SPEED_1000)
a7f75c0c 675 mode |= AX_MEDIUM_GM;
8ae6daca 676 else if (speed == SPEED_100)
933a27d3
DH		 677 mode |= AX_MEDIUM_PS;
678 else
679 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
680
a7f75c0c
PK		 681 mode |= AX_MEDIUM_ENCK;
682
933a27d3
DH		 683 if (ecmd.duplex == DUPLEX_FULL)
684 mode |= AX_MEDIUM_FD;
685 else
686 mode &= ~AX_MEDIUM_FD;
687
8ae6daca
DD		 688 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
689 speed, ecmd.duplex, mode);
933a27d3
DH		 690
691 asix_write_medium_mode(dev, mode);
692
693 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
8ae6daca 694 marvell_led_status(dev, speed);
933a27d3
DH		 695
696 return 0;
697}
698
699static void ax88178_set_mfb(struct usbnet *dev)
700{
701 u16 mfb = AX_RX_CTL_MFB_16384;
702 u16 rxctl;
703 u16 medium;
704 int old_rx_urb_size = dev->rx_urb_size;
705
706 if (dev->hard_mtu < 2048) {
707 dev->rx_urb_size = 2048;
708 mfb = AX_RX_CTL_MFB_2048;
709 } else if (dev->hard_mtu < 4096) {
710 dev->rx_urb_size = 4096;
711 mfb = AX_RX_CTL_MFB_4096;
712 } else if (dev->hard_mtu < 8192) {
713 dev->rx_urb_size = 8192;
714 mfb = AX_RX_CTL_MFB_8192;
715 } else if (dev->hard_mtu < 16384) {
716 dev->rx_urb_size = 16384;
717 mfb = AX_RX_CTL_MFB_16384;
2e55cc72 718 }
933a27d3
DH		 719
720 rxctl = asix_read_rx_ctl(dev);
721 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
722
723 medium = asix_read_medium_status(dev);
724 if (dev->net->mtu > 1500)
725 medium |= AX_MEDIUM_JFE;
726 else
727 medium &= ~AX_MEDIUM_JFE;
728 asix_write_medium_mode(dev, medium);
729
730 if (dev->rx_urb_size > old_rx_urb_size)
731 usbnet_unlink_rx_urbs(dev);
2e55cc72
DB		 732}
733
933a27d3 734static int ax88178_change_mtu(struct net_device *net, int new_mtu)
2e55cc72 735{
933a27d3
DH		 736 struct usbnet *dev = netdev_priv(net);
737 int ll_mtu = new_mtu + net->hard_header_len + 4;
2e55cc72 738
60b86755 739 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
2e55cc72 740
933a27d3
DH		 741 if (new_mtu <= 0 || ll_mtu > 16384)
742 return -EINVAL;
743
744 if ((ll_mtu % dev->maxpacket) == 0)
745 return -EDOM;
746
747 net->mtu = new_mtu;
748 dev->hard_mtu = net->mtu + net->hard_header_len;
749 ax88178_set_mfb(dev);
750
751 return 0;
752}
753
1703338c
SH		 754static const struct net_device_ops ax88178_netdev_ops = {
755 .ndo_open = usbnet_open,
756 .ndo_stop = usbnet_stop,
757 .ndo_start_xmit = usbnet_start_xmit,
758 .ndo_tx_timeout = usbnet_tx_timeout,
7f29a3ba 759 .ndo_set_mac_address = asix_set_mac_address,
1703338c 760 .ndo_validate_addr = eth_validate_addr,
afc4b13d 761 .ndo_set_rx_mode = asix_set_multicast,
1703338c
SH		 762 .ndo_do_ioctl = asix_ioctl,
763 .ndo_change_mtu = ax88178_change_mtu,
764};
765
933a27d3
DH		 766static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
767{
933a27d3 768 int ret;
51bf2976 769 u8 buf[ETH_ALEN];
79de9efd
GG		 770 struct asix_data *data = (struct asix_data *)&dev->data;
771
772 data->eeprom_len = AX88772_EEPROM_LEN;
933a27d3
DH		 773
774 usbnet_get_endpoints(dev,intf);
775
933a27d3 776 /* Get the MAC address */
83e1b918
GG		 777 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
778 if (ret < 0) {
933a27d3 779 dbg("Failed to read MAC address: %d", ret);
83e1b918 780 return ret;
2e55cc72 781 }
933a27d3 782 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
2e55cc72 783
933a27d3
DH		 784 /* Initialize MII structure */
785 dev->mii.dev = dev->net;
786 dev->mii.mdio_read = asix_mdio_read;
787 dev->mii.mdio_write = asix_mdio_write;
788 dev->mii.phy_id_mask = 0x1f;
789 dev->mii.reg_num_mask = 0xff;
790 dev->mii.supports_gmii = 1;
933a27d3 791 dev->mii.phy_id = asix_get_phy_addr(dev);
1703338c
SH		 792
793 dev->net->netdev_ops = &ax88178_netdev_ops;
933a27d3 794 dev->net->ethtool_ops = &ax88178_ethtool_ops;
2e55cc72 795
b2d3ad29
GG		 796 /* Blink LEDS so users know driver saw dongle */
797 asix_sw_reset(dev, 0);
798 msleep(150);
2e55cc72 799
b2d3ad29
GG		 800 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
801 msleep(150);
933a27d3
DH		 802
803 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
804 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
805 /* hard_mtu is still the default - the device does not support
806 jumbo eth frames */
807 dev->rx_urb_size = 2048;
808 }
933a27d3 809
83e1b918 810 return 0;
2e55cc72
DB		 811}
812
813static const struct driver_info ax8817x_info = {
814 .description = "ASIX AX8817x USB 2.0 Ethernet",
48b1be6a
DH		 815 .bind = ax88172_bind,
816 .status = asix_status,
2e55cc72
DB		 817 .link_reset = ax88172_link_reset,
818 .reset = ax88172_link_reset,
37e8273c 819 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 820 .data = 0x00130103,
821};
822
823static const struct driver_info dlink_dub_e100_info = {
824 .description = "DLink DUB-E100 USB Ethernet",
48b1be6a
DH		 825 .bind = ax88172_bind,
826 .status = asix_status,
2e55cc72
DB		 827 .link_reset = ax88172_link_reset,
828 .reset = ax88172_link_reset,
37e8273c 829 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 830 .data = 0x009f9d9f,
831};
832
833static const struct driver_info netgear_fa120_info = {
834 .description = "Netgear FA-120 USB Ethernet",
48b1be6a
DH		 835 .bind = ax88172_bind,
836 .status = asix_status,
2e55cc72
DB		 837 .link_reset = ax88172_link_reset,
838 .reset = ax88172_link_reset,
37e8273c 839 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 840 .data = 0x00130103,
841};
842
843static const struct driver_info hawking_uf200_info = {
844 .description = "Hawking UF200 USB Ethernet",
48b1be6a
DH		 845 .bind = ax88172_bind,
846 .status = asix_status,
2e55cc72
DB		 847 .link_reset = ax88172_link_reset,
848 .reset = ax88172_link_reset,
37e8273c 849 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 850 .data = 0x001f1d1f,
851};
852
853static const struct driver_info ax88772_info = {
854 .description = "ASIX AX88772 USB 2.0 Ethernet",
855 .bind = ax88772_bind,
48b1be6a 856 .status = asix_status,
2e55cc72 857 .link_reset = ax88772_link_reset,
4ad1438f 858 .reset = ax88772_reset,
a9e0aca4 859 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
933a27d3
DH		 860 .rx_fixup = asix_rx_fixup,
861 .tx_fixup = asix_tx_fixup,
862};
863
864static const struct driver_info ax88178_info = {
865 .description = "ASIX AX88178 USB 2.0 Ethernet",
866 .bind = ax88178_bind,
867 .status = asix_status,
868 .link_reset = ax88178_link_reset,
610d885d 869 .reset = ax88178_reset,
37e8273c 870 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR,
933a27d3
DH		 871 .rx_fixup = asix_rx_fixup,
872 .tx_fixup = asix_tx_fixup,
2e55cc72
DB		 873};
874
875static const struct usb_device_id products [] = {
876{
877 // Linksys USB200M
878 USB_DEVICE (0x077b, 0x2226),
879 .driver_info = (unsigned long) &ax8817x_info,
880}, {
881 // Netgear FA120
882 USB_DEVICE (0x0846, 0x1040),
883 .driver_info = (unsigned long) &netgear_fa120_info,
884}, {
885 // DLink DUB-E100
886 USB_DEVICE (0x2001, 0x1a00),
887 .driver_info = (unsigned long) &dlink_dub_e100_info,
888}, {
889 // Intellinet, ST Lab USB Ethernet
890 USB_DEVICE (0x0b95, 0x1720),
891 .driver_info = (unsigned long) &ax8817x_info,
892}, {
893 // Hawking UF200, TrendNet TU2-ET100
894 USB_DEVICE (0x07b8, 0x420a),
895 .driver_info = (unsigned long) &hawking_uf200_info,
896}, {
39c4b38c
DH		 897 // Billionton Systems, USB2AR
898 USB_DEVICE (0x08dd, 0x90ff),
899 .driver_info = (unsigned long) &ax8817x_info,
2e55cc72
DB		 900}, {
901 // ATEN UC210T
902 USB_DEVICE (0x0557, 0x2009),
903 .driver_info = (unsigned long) &ax8817x_info,
904}, {
905 // Buffalo LUA-U2-KTX
906 USB_DEVICE (0x0411, 0x003d),
907 .driver_info = (unsigned long) &ax8817x_info,
ac7b77f1
MD		 908}, {
909 // Buffalo LUA-U2-GT 10/100/1000
910 USB_DEVICE (0x0411, 0x006e),
911 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 912}, {
913 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
914 USB_DEVICE (0x6189, 0x182d),
915 .driver_info = (unsigned long) &ax8817x_info,
4e503919
JN		 916}, {
917 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
918 USB_DEVICE (0x0df6, 0x0056),
919 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 920}, {
921 // corega FEther USB2-TX
922 USB_DEVICE (0x07aa, 0x0017),
923 .driver_info = (unsigned long) &ax8817x_info,
924}, {
925 // Surecom EP-1427X-2
926 USB_DEVICE (0x1189, 0x0893),
927 .driver_info = (unsigned long) &ax8817x_info,
928}, {
929 // goodway corp usb gwusb2e
930 USB_DEVICE (0x1631, 0x6200),
931 .driver_info = (unsigned long) &ax8817x_info,
39c4b38c
DH		 932}, {
933 // JVC MP-PRX1 Port Replicator
934 USB_DEVICE (0x04f1, 0x3008),
935 .driver_info = (unsigned long) &ax8817x_info,
30885909
MV		 936}, {
937 // ASIX AX88772B 10/100
938 USB_DEVICE (0x0b95, 0x772b),
939 .driver_info = (unsigned long) &ax88772_info,
2e55cc72
DB		 940}, {
941 // ASIX AX88772 10/100
39c4b38c
DH		 942 USB_DEVICE (0x0b95, 0x7720),
943 .driver_info = (unsigned long) &ax88772_info,
7327413c
EW		 944}, {
945 // ASIX AX88178 10/100/1000
946 USB_DEVICE (0x0b95, 0x1780),
933a27d3 947 .driver_info = (unsigned long) &ax88178_info,
f4680d3d
AE		 948}, {
949 // Logitec LAN-GTJ/U2A
950 USB_DEVICE (0x0789, 0x0160),
951 .driver_info = (unsigned long) &ax88178_info,
5e0f76c6
DH		 952}, {
953 // Linksys USB200M Rev 2
954 USB_DEVICE (0x13b1, 0x0018),
955 .driver_info = (unsigned long) &ax88772_info,
5732ce84
DH		 956}, {
957 // 0Q0 cable ethernet
958 USB_DEVICE (0x1557, 0x7720),
959 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 960}, {
961 // DLink DUB-E100 H/W Ver B1
962 USB_DEVICE (0x07d1, 0x3c05),
963 .driver_info = (unsigned long) &ax88772_info,
b923e7fc
DH		 964}, {
965 // DLink DUB-E100 H/W Ver B1 Alternate
966 USB_DEVICE (0x2001, 0x3c05),
967 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 968}, {
969 // Linksys USB1000
970 USB_DEVICE (0x1737, 0x0039),
971 .driver_info = (unsigned long) &ax88178_info,
b29cf31d
YH		 972}, {
973 // IO-DATA ETG-US2
974 USB_DEVICE (0x04bb, 0x0930),
975 .driver_info = (unsigned long) &ax88178_info,
2ed22bc2
DH		 976}, {
977 // Belkin F5D5055
978 USB_DEVICE(0x050d, 0x5055),
979 .driver_info = (unsigned long) &ax88178_info,
3d60efb5
AN		 980}, {
981 // Apple USB Ethernet Adapter
982 USB_DEVICE(0x05ac, 0x1402),
983 .driver_info = (unsigned long) &ax88772_info,
ccf95402
JC		 984}, {
985 // Cables-to-Go USB Ethernet Adapter
986 USB_DEVICE(0x0b95, 0x772a),
987 .driver_info = (unsigned long) &ax88772_info,
fef7cc08
GKH		 988}, {
989 // ABOCOM for pci
990 USB_DEVICE(0x14ea, 0xab11),
991 .driver_info = (unsigned long) &ax88178_info,
992}, {
993 // ASIX 88772a
994 USB_DEVICE(0x0db0, 0xa877),
995 .driver_info = (unsigned long) &ax88772_info,
e8303a3b
AJ		 996}, {
997 // Asus USB Ethernet Adapter
998 USB_DEVICE (0x0b95, 0x7e2b),
999 .driver_info = (unsigned long) &ax88772_info,
2e55cc72
DB		 1000},
1001 { }, // END
1002};
1003MODULE_DEVICE_TABLE(usb, products);
1004
1005static struct usb_driver asix_driver = {
83e1b918 1006 .name = DRIVER_NAME,
2e55cc72
DB		 1007 .id_table = products,
1008 .probe = usbnet_probe,
1009 .suspend = usbnet_suspend,
1010 .resume = usbnet_resume,
1011 .disconnect = usbnet_disconnect,
a11a6544 1012 .supports_autosuspend = 1,
e1f12eb6 1013 .disable_hub_initiated_lpm = 1,
2e55cc72
DB		 1014};
1015
d632eb1b 1016module_usb_driver(asix_driver);
2e55cc72
DB		 1017
1018MODULE_AUTHOR("David Hollis");
4ad1438f 1019MODULE_VERSION(DRIVER_VERSION);
2e55cc72
DB		 1020MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1021MODULE_LICENSE("GPL");
1022
Linux 6.x block layer and io_uring tree(s)