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net: asix: init ASIX AX88772B MAC from EEPROM
[linux-2.6-block.git] / drivers / net / usb / asix_devices.c
CommitLineData
2e55cc72
DB		 1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
933a27d3 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
2e55cc72 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
933a27d3 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
2e55cc72
DB		 6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
607740bc 23#include "asix.h"
933a27d3
DH		 24
25#define PHY_MODE_MARVELL 0x0000
26#define MII_MARVELL_LED_CTRL 0x0018
27#define MII_MARVELL_STATUS 0x001b
28#define MII_MARVELL_CTRL 0x0014
29
30#define MARVELL_LED_MANUAL 0x0019
31
32#define MARVELL_STATUS_HWCFG 0x0004
33
34#define MARVELL_CTRL_TXDELAY 0x0002
35#define MARVELL_CTRL_RXDELAY 0x0080
2e55cc72 36
3486140e 37#define PHY_MODE_RTL8211CL 0x000C
610d885d 38
2e55cc72 39struct ax88172_int_data {
51bf2976 40 __le16 res1;
2e55cc72 41 u8 link;
51bf2976 42 __le16 res2;
2e55cc72 43 u8 status;
51bf2976 44 __le16 res3;
ba2d3587 45} __packed;
2e55cc72 46
933a27d3
DH		 47static void asix_status(struct usbnet *dev, struct urb *urb)
48{
49 struct ax88172_int_data *event;
50 int link;
51
52 if (urb->actual_length < 8)
53 return;
54
55 event = urb->transfer_buffer;
56 link = event->link & 0x01;
57 if (netif_carrier_ok(dev->net) != link) {
58 if (link) {
59 netif_carrier_on(dev->net);
60 usbnet_defer_kevent (dev, EVENT_LINK_RESET );
61 } else
62 netif_carrier_off(dev->net);
60b86755 63 netdev_dbg(dev->net, "Link Status is: %d\n", link);
933a27d3
DH		 64 }
65}
66
452b5ecd
JCPV		 67static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
68{
69 if (is_valid_ether_addr(addr)) {
70 memcpy(dev->net->dev_addr, addr, ETH_ALEN);
71 } else {
72 netdev_info(dev->net, "invalid hw address, using random\n");
73 eth_hw_addr_random(dev->net);
74 }
75}
76
933a27d3
DH		 77/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
78static u32 asix_get_phyid(struct usbnet *dev)
2e55cc72 79{
933a27d3
DH		 80 int phy_reg;
81 u32 phy_id;
a77929a2 82 int i;
2e55cc72 83
a77929a2
GG		 84 /* Poll for the rare case the FW or phy isn't ready yet. */
85 for (i = 0; i < 100; i++) {
86 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
87 if (phy_reg != 0 && phy_reg != 0xFFFF)
88 break;
89 mdelay(1);
90 }
91
92 if (phy_reg <= 0 || phy_reg == 0xFFFF)
933a27d3 93 return 0;
2e55cc72 94
933a27d3 95 phy_id = (phy_reg & 0xffff) << 16;
2e55cc72 96
933a27d3
DH		 97 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
98 if (phy_reg < 0)
99 return 0;
100
101 phy_id |= (phy_reg & 0xffff);
102
103 return phy_id;
2e55cc72
DB		 104}
105
933a27d3
DH		 106static u32 asix_get_link(struct net_device *net)
107{
108 struct usbnet *dev = netdev_priv(net);
109
110 return mii_link_ok(&dev->mii);
111}
112
113static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
114{
115 struct usbnet *dev = netdev_priv(net);
116
117 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
118}
119
120/* We need to override some ethtool_ops so we require our
121 own structure so we don't interfere with other usbnet
122 devices that may be connected at the same time. */
0fc0b732 123static const struct ethtool_ops ax88172_ethtool_ops = {
933a27d3
DH		 124 .get_drvinfo = asix_get_drvinfo,
125 .get_link = asix_get_link,
933a27d3 126 .get_msglevel = usbnet_get_msglevel,
2e55cc72 127 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 128 .get_wol = asix_get_wol,
129 .set_wol = asix_set_wol,
130 .get_eeprom_len = asix_get_eeprom_len,
131 .get_eeprom = asix_get_eeprom,
cb7b24cd 132 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 133 .get_settings = usbnet_get_settings,
134 .set_settings = usbnet_set_settings,
135 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 136};
137
933a27d3 138static void ax88172_set_multicast(struct net_device *net)
2e55cc72
DB		 139{
140 struct usbnet *dev = netdev_priv(net);
933a27d3
DH		 141 struct asix_data *data = (struct asix_data *)&dev->data;
142 u8 rx_ctl = 0x8c;
2e55cc72 143
933a27d3
DH		 144 if (net->flags & IFF_PROMISC) {
145 rx_ctl |= 0x01;
8e95a202 146 } else if (net->flags & IFF_ALLMULTI ||
4cd24eaf 147 netdev_mc_count(net) > AX_MAX_MCAST) {
933a27d3 148 rx_ctl |= 0x02;
4cd24eaf 149 } else if (netdev_mc_empty(net)) {
933a27d3
DH		 150 /* just broadcast and directed */
151 } else {
152 /* We use the 20 byte dev->data
153 * for our 8 byte filter buffer
154 * to avoid allocating memory that
155 * is tricky to free later */
22bedad3 156 struct netdev_hw_addr *ha;
933a27d3 157 u32 crc_bits;
933a27d3
DH		 158
159 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
160
161 /* Build the multicast hash filter. */
22bedad3
JP		 162 netdev_for_each_mc_addr(ha, net) {
163 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
933a27d3
DH		 164 data->multi_filter[crc_bits >> 3] |=
165 1 << (crc_bits & 7);
933a27d3
DH		 166 }
167
168 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
169 AX_MCAST_FILTER_SIZE, data->multi_filter);
170
171 rx_ctl |= 0x10;
172 }
173
174 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
175}
176
177static int ax88172_link_reset(struct usbnet *dev)
178{
179 u8 mode;
8ae6daca 180 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 181
182 mii_check_media(&dev->mii, 1, 1);
183 mii_ethtool_gset(&dev->mii, &ecmd);
184 mode = AX88172_MEDIUM_DEFAULT;
185
186 if (ecmd.duplex != DUPLEX_FULL)
187 mode |= ~AX88172_MEDIUM_FD;
188
8ae6daca
DD		 189 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
190 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3
DH		 191
192 asix_write_medium_mode(dev, mode);
193
194 return 0;
2e55cc72
DB		 195}
196
1703338c
SH		 197static const struct net_device_ops ax88172_netdev_ops = {
198 .ndo_open = usbnet_open,
199 .ndo_stop = usbnet_stop,
200 .ndo_start_xmit = usbnet_start_xmit,
201 .ndo_tx_timeout = usbnet_tx_timeout,
202 .ndo_change_mtu = usbnet_change_mtu,
203 .ndo_set_mac_address = eth_mac_addr,
204 .ndo_validate_addr = eth_validate_addr,
205 .ndo_do_ioctl = asix_ioctl,
afc4b13d 206 .ndo_set_rx_mode = ax88172_set_multicast,
1703338c
SH		 207};
208
48b1be6a 209static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
2e55cc72
DB		 210{
211 int ret = 0;
51bf2976 212 u8 buf[ETH_ALEN];
2e55cc72
DB		 213 int i;
214 unsigned long gpio_bits = dev->driver_info->data;
215
216 usbnet_get_endpoints(dev,intf);
217
2e55cc72
DB		 218 /* Toggle the GPIOs in a manufacturer/model specific way */
219 for (i = 2; i >= 0; i--) {
83e1b918
GG		 220 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
221 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL);
222 if (ret < 0)
51bf2976 223 goto out;
2e55cc72
DB		 224 msleep(5);
225 }
226
83e1b918
GG		 227 ret = asix_write_rx_ctl(dev, 0x80);
228 if (ret < 0)
51bf2976 229 goto out;
2e55cc72
DB		 230
231 /* Get the MAC address */
83e1b918
GG		 232 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
233 if (ret < 0) {
49ae25b0
GKH		 234 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
235 ret);
51bf2976 236 goto out;
2e55cc72 237 }
452b5ecd
JCPV		 238
239 asix_set_netdev_dev_addr(dev, buf);
2e55cc72 240
2e55cc72
DB		 241 /* Initialize MII structure */
242 dev->mii.dev = dev->net;
48b1be6a
DH		 243 dev->mii.mdio_read = asix_mdio_read;
244 dev->mii.mdio_write = asix_mdio_write;
2e55cc72
DB		 245 dev->mii.phy_id_mask = 0x3f;
246 dev->mii.reg_num_mask = 0x1f;
933a27d3 247 dev->mii.phy_id = asix_get_phy_addr(dev);
2e55cc72 248
1703338c 249 dev->net->netdev_ops = &ax88172_netdev_ops;
48b1be6a 250 dev->net->ethtool_ops = &ax88172_ethtool_ops;
95162d65
ED		 251 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
252 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
2e55cc72 253
933a27d3
DH		 254 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
255 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 256 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
257 mii_nway_restart(&dev->mii);
258
259 return 0;
51bf2976
AV		 260
261out:
2e55cc72
DB		 262 return ret;
263}
264
0fc0b732 265static const struct ethtool_ops ax88772_ethtool_ops = {
48b1be6a 266 .get_drvinfo = asix_get_drvinfo,
933a27d3 267 .get_link = asix_get_link,
2e55cc72
DB		 268 .get_msglevel = usbnet_get_msglevel,
269 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 270 .get_wol = asix_get_wol,
271 .set_wol = asix_set_wol,
272 .get_eeprom_len = asix_get_eeprom_len,
273 .get_eeprom = asix_get_eeprom,
cb7b24cd 274 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 275 .get_settings = usbnet_get_settings,
276 .set_settings = usbnet_set_settings,
277 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 278};
279
933a27d3
DH		 280static int ax88772_link_reset(struct usbnet *dev)
281{
282 u16 mode;
8ae6daca 283 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 284
285 mii_check_media(&dev->mii, 1, 1);
286 mii_ethtool_gset(&dev->mii, &ecmd);
287 mode = AX88772_MEDIUM_DEFAULT;
288
8ae6daca 289 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
933a27d3
DH		 290 mode &= ~AX_MEDIUM_PS;
291
292 if (ecmd.duplex != DUPLEX_FULL)
293 mode &= ~AX_MEDIUM_FD;
294
8ae6daca
DD		 295 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
296 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3
DH		 297
298 asix_write_medium_mode(dev, mode);
299
300 return 0;
301}
302
4ad1438f 303static int ax88772_reset(struct usbnet *dev)
2e55cc72 304{
8ef66bdc 305 struct asix_data *data = (struct asix_data *)&dev->data;
d0ffff8f 306 int ret, embd_phy;
933a27d3 307 u16 rx_ctl;
2e55cc72 308
83e1b918
GG		 309 ret = asix_write_gpio(dev,
310 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5);
311 if (ret < 0)
51bf2976 312 goto out;
2e55cc72 313
d0ffff8f 314 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
4ad1438f 315
83e1b918
GG		 316 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
317 if (ret < 0) {
49ae25b0 318 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
51bf2976 319 goto out;
2e55cc72
DB		 320 }
321
83e1b918
GG		 322 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
323 if (ret < 0)
51bf2976 324 goto out;
2e55cc72
DB		 325
326 msleep(150);
83e1b918
GG		 327
328 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
329 if (ret < 0)
51bf2976 330 goto out;
2e55cc72
DB		 331
332 msleep(150);
4ad1438f 333
d0ffff8f 334 if (embd_phy) {
83e1b918
GG		 335 ret = asix_sw_reset(dev, AX_SWRESET_IPRL);
336 if (ret < 0)
51bf2976 337 goto out;
83e1b918
GG		 338 } else {
339 ret = asix_sw_reset(dev, AX_SWRESET_PRTE);
340 if (ret < 0)
51bf2976 341 goto out;
d0ffff8f 342 }
2e55cc72
DB		 343
344 msleep(150);
933a27d3 345 rx_ctl = asix_read_rx_ctl(dev);
49ae25b0 346 netdev_dbg(dev->net, "RX_CTL is 0x%04x after software reset\n", rx_ctl);
83e1b918
GG		 347 ret = asix_write_rx_ctl(dev, 0x0000);
348 if (ret < 0)
51bf2976 349 goto out;
2e55cc72 350
933a27d3 351 rx_ctl = asix_read_rx_ctl(dev);
49ae25b0 352 netdev_dbg(dev->net, "RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
933a27d3 353
83e1b918
GG		 354 ret = asix_sw_reset(dev, AX_SWRESET_PRL);
355 if (ret < 0)
51bf2976 356 goto out;
2e55cc72 357
2e55cc72 358 msleep(150);
48b1be6a 359
83e1b918
GG		 360 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL);
361 if (ret < 0)
51bf2976 362 goto out;
2e55cc72 363
48b1be6a 364 msleep(150);
2e55cc72 365
933a27d3
DH		 366 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
367 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 368 ADVERTISE_ALL | ADVERTISE_CSMA);
369 mii_nway_restart(&dev->mii);
370
83e1b918
GG		 371 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT);
372 if (ret < 0)
51bf2976 373 goto out;
2e55cc72 374
83e1b918 375 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
2e55cc72 376 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
83e1b918
GG		 377 AX88772_IPG2_DEFAULT, 0, NULL);
378 if (ret < 0) {
49ae25b0 379 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
51bf2976 380 goto out;
2e55cc72 381 }
2e55cc72 382
8ef66bdc
JK		 383 /* Rewrite MAC address */
384 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
385 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
386 data->mac_addr);
387 if (ret < 0)
388 goto out;
389
2e55cc72 390 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
83e1b918
GG		 391 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
392 if (ret < 0)
51bf2976 393 goto out;
2e55cc72 394
933a27d3 395 rx_ctl = asix_read_rx_ctl(dev);
49ae25b0
GKH		 396 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
397 rx_ctl);
933a27d3
DH		 398
399 rx_ctl = asix_read_medium_status(dev);
49ae25b0
GKH		 400 netdev_dbg(dev->net,
401 "Medium Status is 0x%04x after all initializations\n",
402 rx_ctl);
933a27d3 403
4ad1438f
GG		 404 return 0;
405
406out:
407 return ret;
408
409}
410
411static const struct net_device_ops ax88772_netdev_ops = {
412 .ndo_open = usbnet_open,
413 .ndo_stop = usbnet_stop,
414 .ndo_start_xmit = usbnet_start_xmit,
415 .ndo_tx_timeout = usbnet_tx_timeout,
416 .ndo_change_mtu = usbnet_change_mtu,
417 .ndo_set_mac_address = asix_set_mac_address,
418 .ndo_validate_addr = eth_validate_addr,
419 .ndo_do_ioctl = asix_ioctl,
420 .ndo_set_rx_mode = asix_set_multicast,
421};
422
423static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
424{
5620df65 425 int ret, embd_phy, i;
4ad1438f
GG		 426 u8 buf[ETH_ALEN];
427 u32 phyid;
428
4ad1438f
GG		 429 usbnet_get_endpoints(dev,intf);
430
431 /* Get the MAC address */
5620df65
LS		 432 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
433 for (i = 0; i < (ETH_ALEN >> 1); i++) {
434 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x04 + i,
435 0, 2, buf + i * 2);
436 if (ret < 0)
437 break;
438 }
439 } else {
440 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
441 0, 0, ETH_ALEN, buf);
442 }
443
83e1b918 444 if (ret < 0) {
49ae25b0 445 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
83e1b918 446 return ret;
4ad1438f 447 }
452b5ecd
JCPV		 448
449 asix_set_netdev_dev_addr(dev, buf);
4ad1438f
GG		 450
451 /* Initialize MII structure */
452 dev->mii.dev = dev->net;
453 dev->mii.mdio_read = asix_mdio_read;
454 dev->mii.mdio_write = asix_mdio_write;
455 dev->mii.phy_id_mask = 0x1f;
456 dev->mii.reg_num_mask = 0x1f;
457 dev->mii.phy_id = asix_get_phy_addr(dev);
458
4ad1438f
GG		 459 dev->net->netdev_ops = &ax88772_netdev_ops;
460 dev->net->ethtool_ops = &ax88772_ethtool_ops;
95162d65
ED		 461 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
462 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
4ad1438f 463
d3665188
GG		 464 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
465
466 /* Reset the PHY to normal operation mode */
467 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
468 if (ret < 0) {
49ae25b0 469 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
d3665188
GG		 470 return ret;
471 }
472
473 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
83e1b918
GG		 474 if (ret < 0)
475 return ret;
4ad1438f 476
d3665188
GG		 477 msleep(150);
478
479 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
480 if (ret < 0)
481 return ret;
482
483 msleep(150);
484
485 ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE);
486
487 /* Read PHYID register *AFTER* the PHY was reset properly */
488 phyid = asix_get_phyid(dev);
49ae25b0 489 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
d3665188 490
2e55cc72
DB		 491 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
492 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
493 /* hard_mtu is still the default - the device does not support
494 jumbo eth frames */
495 dev->rx_urb_size = 2048;
496 }
83e1b918 497
2e55cc72 498 return 0;
2e55cc72
DB		 499}
500
bc689c97 501static const struct ethtool_ops ax88178_ethtool_ops = {
933a27d3
DH		 502 .get_drvinfo = asix_get_drvinfo,
503 .get_link = asix_get_link,
933a27d3
DH		 504 .get_msglevel = usbnet_get_msglevel,
505 .set_msglevel = usbnet_set_msglevel,
506 .get_wol = asix_get_wol,
507 .set_wol = asix_set_wol,
508 .get_eeprom_len = asix_get_eeprom_len,
509 .get_eeprom = asix_get_eeprom,
cb7b24cd 510 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 511 .get_settings = usbnet_get_settings,
512 .set_settings = usbnet_set_settings,
513 .nway_reset = usbnet_nway_reset,
933a27d3
DH		 514};
515
516static int marvell_phy_init(struct usbnet *dev)
2e55cc72 517{
933a27d3
DH		 518 struct asix_data *data = (struct asix_data *)&dev->data;
519 u16 reg;
2e55cc72 520
60b86755 521 netdev_dbg(dev->net, "marvell_phy_init()\n");
2e55cc72 522
933a27d3 523 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
60b86755 524 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
2e55cc72 525
933a27d3
DH		 526 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
527 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
2e55cc72 528
933a27d3
DH		 529 if (data->ledmode) {
530 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
531 MII_MARVELL_LED_CTRL);
60b86755 532 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
2e55cc72 533
933a27d3
DH		 534 reg &= 0xf8ff;
535 reg |= (1 + 0x0100);
536 asix_mdio_write(dev->net, dev->mii.phy_id,
537 MII_MARVELL_LED_CTRL, reg);
2e55cc72 538
933a27d3
DH		 539 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
540 MII_MARVELL_LED_CTRL);
60b86755 541 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
933a27d3
DH		 542 reg &= 0xfc0f;
543 }
2e55cc72 544
933a27d3
DH		 545 return 0;
546}
547
610d885d
GG		 548static int rtl8211cl_phy_init(struct usbnet *dev)
549{
550 struct asix_data *data = (struct asix_data *)&dev->data;
551
552 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
553
554 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
555 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
556 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
557 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
558 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
559
560 if (data->ledmode == 12) {
561 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
562 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
563 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
564 }
565
566 return 0;
567}
568
933a27d3
DH		 569static int marvell_led_status(struct usbnet *dev, u16 speed)
570{
571 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
572
60b86755 573 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
933a27d3
DH		 574
575 /* Clear out the center LED bits - 0x03F0 */
576 reg &= 0xfc0f;
577
578 switch (speed) {
579 case SPEED_1000:
580 reg |= 0x03e0;
581 break;
582 case SPEED_100:
583 reg |= 0x03b0;
584 break;
585 default:
586 reg |= 0x02f0;
2e55cc72
DB		 587 }
588
60b86755 589 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
933a27d3
DH		 590 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
591
592 return 0;
593}
594
610d885d
GG		 595static int ax88178_reset(struct usbnet *dev)
596{
597 struct asix_data *data = (struct asix_data *)&dev->data;
598 int ret;
599 __le16 eeprom;
600 u8 status;
601 int gpio0 = 0;
b2d3ad29 602 u32 phyid;
610d885d
GG		 603
604 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status);
49ae25b0 605 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
610d885d
GG		 606
607 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
608 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
609 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
610
49ae25b0 611 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
610d885d
GG		 612
613 if (eeprom == cpu_to_le16(0xffff)) {
614 data->phymode = PHY_MODE_MARVELL;
615 data->ledmode = 0;
616 gpio0 = 1;
617 } else {
b2d3ad29 618 data->phymode = le16_to_cpu(eeprom) & 0x7F;
610d885d
GG		 619 data->ledmode = le16_to_cpu(eeprom) >> 8;
620 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
621 }
49ae25b0 622 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
610d885d 623
b2d3ad29 624 /* Power up external GigaPHY through AX88178 GPIO pin */
610d885d
GG		 625 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
626 if ((le16_to_cpu(eeprom) >> 8) != 1) {
627 asix_write_gpio(dev, 0x003c, 30);
628 asix_write_gpio(dev, 0x001c, 300);
629 asix_write_gpio(dev, 0x003c, 30);
630 } else {
49ae25b0 631 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
610d885d
GG		 632 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
633 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
634 }
635
b2d3ad29
GG		 636 /* Read PHYID register *AFTER* powering up PHY */
637 phyid = asix_get_phyid(dev);
49ae25b0 638 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
b2d3ad29
GG		 639
640 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
641 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL);
642
610d885d
GG		 643 asix_sw_reset(dev, 0);
644 msleep(150);
645
646 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
647 msleep(150);
648
649 asix_write_rx_ctl(dev, 0);
650
651 if (data->phymode == PHY_MODE_MARVELL) {
652 marvell_phy_init(dev);
653 msleep(60);
654 } else if (data->phymode == PHY_MODE_RTL8211CL)
655 rtl8211cl_phy_init(dev);
656
657 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
658 BMCR_RESET | BMCR_ANENABLE);
659 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
660 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
661 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
662 ADVERTISE_1000FULL);
663
664 mii_nway_restart(&dev->mii);
665
83e1b918
GG		 666 ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT);
667 if (ret < 0)
668 return ret;
610d885d 669
71bc5d94
JK		 670 /* Rewrite MAC address */
671 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
672 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
673 data->mac_addr);
674 if (ret < 0)
675 return ret;
676
83e1b918
GG		 677 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
678 if (ret < 0)
679 return ret;
610d885d
GG		 680
681 return 0;
610d885d
GG		 682}
683
933a27d3
DH		 684static int ax88178_link_reset(struct usbnet *dev)
685{
686 u16 mode;
8ae6daca 687 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3 688 struct asix_data *data = (struct asix_data *)&dev->data;
8ae6daca 689 u32 speed;
933a27d3 690
60b86755 691 netdev_dbg(dev->net, "ax88178_link_reset()\n");
933a27d3
DH		 692
693 mii_check_media(&dev->mii, 1, 1);
694 mii_ethtool_gset(&dev->mii, &ecmd);
695 mode = AX88178_MEDIUM_DEFAULT;
8ae6daca 696 speed = ethtool_cmd_speed(&ecmd);
933a27d3 697
8ae6daca 698 if (speed == SPEED_1000)
a7f75c0c 699 mode |= AX_MEDIUM_GM;
8ae6daca 700 else if (speed == SPEED_100)
933a27d3
DH		 701 mode |= AX_MEDIUM_PS;
702 else
703 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
704
a7f75c0c
PK		 705 mode |= AX_MEDIUM_ENCK;
706
933a27d3
DH		 707 if (ecmd.duplex == DUPLEX_FULL)
708 mode |= AX_MEDIUM_FD;
709 else
710 mode &= ~AX_MEDIUM_FD;
711
8ae6daca
DD		 712 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
713 speed, ecmd.duplex, mode);
933a27d3
DH		 714
715 asix_write_medium_mode(dev, mode);
716
717 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
8ae6daca 718 marvell_led_status(dev, speed);
933a27d3
DH		 719
720 return 0;
721}
722
723static void ax88178_set_mfb(struct usbnet *dev)
724{
725 u16 mfb = AX_RX_CTL_MFB_16384;
726 u16 rxctl;
727 u16 medium;
728 int old_rx_urb_size = dev->rx_urb_size;
729
730 if (dev->hard_mtu < 2048) {
731 dev->rx_urb_size = 2048;
732 mfb = AX_RX_CTL_MFB_2048;
733 } else if (dev->hard_mtu < 4096) {
734 dev->rx_urb_size = 4096;
735 mfb = AX_RX_CTL_MFB_4096;
736 } else if (dev->hard_mtu < 8192) {
737 dev->rx_urb_size = 8192;
738 mfb = AX_RX_CTL_MFB_8192;
739 } else if (dev->hard_mtu < 16384) {
740 dev->rx_urb_size = 16384;
741 mfb = AX_RX_CTL_MFB_16384;
2e55cc72 742 }
933a27d3
DH		 743
744 rxctl = asix_read_rx_ctl(dev);
745 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
746
747 medium = asix_read_medium_status(dev);
748 if (dev->net->mtu > 1500)
749 medium |= AX_MEDIUM_JFE;
750 else
751 medium &= ~AX_MEDIUM_JFE;
752 asix_write_medium_mode(dev, medium);
753
754 if (dev->rx_urb_size > old_rx_urb_size)
755 usbnet_unlink_rx_urbs(dev);
2e55cc72
DB		 756}
757
933a27d3 758static int ax88178_change_mtu(struct net_device *net, int new_mtu)
2e55cc72 759{
933a27d3
DH		 760 struct usbnet *dev = netdev_priv(net);
761 int ll_mtu = new_mtu + net->hard_header_len + 4;
2e55cc72 762
60b86755 763 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
2e55cc72 764
933a27d3
DH		 765 if (new_mtu <= 0 || ll_mtu > 16384)
766 return -EINVAL;
767
768 if ((ll_mtu % dev->maxpacket) == 0)
769 return -EDOM;
770
771 net->mtu = new_mtu;
772 dev->hard_mtu = net->mtu + net->hard_header_len;
773 ax88178_set_mfb(dev);
774
775 return 0;
776}
777
1703338c
SH		 778static const struct net_device_ops ax88178_netdev_ops = {
779 .ndo_open = usbnet_open,
780 .ndo_stop = usbnet_stop,
781 .ndo_start_xmit = usbnet_start_xmit,
782 .ndo_tx_timeout = usbnet_tx_timeout,
7f29a3ba 783 .ndo_set_mac_address = asix_set_mac_address,
1703338c 784 .ndo_validate_addr = eth_validate_addr,
afc4b13d 785 .ndo_set_rx_mode = asix_set_multicast,
1703338c
SH		 786 .ndo_do_ioctl = asix_ioctl,
787 .ndo_change_mtu = ax88178_change_mtu,
788};
789
933a27d3
DH		 790static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
791{
933a27d3 792 int ret;
51bf2976 793 u8 buf[ETH_ALEN];
933a27d3
DH		 794
795 usbnet_get_endpoints(dev,intf);
796
933a27d3 797 /* Get the MAC address */
83e1b918
GG		 798 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
799 if (ret < 0) {
49ae25b0 800 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
83e1b918 801 return ret;
2e55cc72 802 }
452b5ecd
JCPV		 803
804 asix_set_netdev_dev_addr(dev, buf);
2e55cc72 805
933a27d3
DH		 806 /* Initialize MII structure */
807 dev->mii.dev = dev->net;
808 dev->mii.mdio_read = asix_mdio_read;
809 dev->mii.mdio_write = asix_mdio_write;
810 dev->mii.phy_id_mask = 0x1f;
811 dev->mii.reg_num_mask = 0xff;
812 dev->mii.supports_gmii = 1;
933a27d3 813 dev->mii.phy_id = asix_get_phy_addr(dev);
1703338c
SH		 814
815 dev->net->netdev_ops = &ax88178_netdev_ops;
933a27d3 816 dev->net->ethtool_ops = &ax88178_ethtool_ops;
2e55cc72 817
b2d3ad29
GG		 818 /* Blink LEDS so users know driver saw dongle */
819 asix_sw_reset(dev, 0);
820 msleep(150);
2e55cc72 821
b2d3ad29
GG		 822 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
823 msleep(150);
933a27d3
DH		 824
825 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
826 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
827 /* hard_mtu is still the default - the device does not support
828 jumbo eth frames */
829 dev->rx_urb_size = 2048;
830 }
933a27d3 831
83e1b918 832 return 0;
2e55cc72
DB		 833}
834
835static const struct driver_info ax8817x_info = {
836 .description = "ASIX AX8817x USB 2.0 Ethernet",
48b1be6a
DH		 837 .bind = ax88172_bind,
838 .status = asix_status,
2e55cc72
DB		 839 .link_reset = ax88172_link_reset,
840 .reset = ax88172_link_reset,
37e8273c 841 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 842 .data = 0x00130103,
843};
844
845static const struct driver_info dlink_dub_e100_info = {
846 .description = "DLink DUB-E100 USB Ethernet",
48b1be6a
DH		 847 .bind = ax88172_bind,
848 .status = asix_status,
2e55cc72
DB		 849 .link_reset = ax88172_link_reset,
850 .reset = ax88172_link_reset,
37e8273c 851 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 852 .data = 0x009f9d9f,
853};
854
855static const struct driver_info netgear_fa120_info = {
856 .description = "Netgear FA-120 USB Ethernet",
48b1be6a
DH		 857 .bind = ax88172_bind,
858 .status = asix_status,
2e55cc72
DB		 859 .link_reset = ax88172_link_reset,
860 .reset = ax88172_link_reset,
37e8273c 861 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 862 .data = 0x00130103,
863};
864
865static const struct driver_info hawking_uf200_info = {
866 .description = "Hawking UF200 USB Ethernet",
48b1be6a
DH		 867 .bind = ax88172_bind,
868 .status = asix_status,
2e55cc72
DB		 869 .link_reset = ax88172_link_reset,
870 .reset = ax88172_link_reset,
37e8273c 871 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 872 .data = 0x001f1d1f,
873};
874
875static const struct driver_info ax88772_info = {
876 .description = "ASIX AX88772 USB 2.0 Ethernet",
877 .bind = ax88772_bind,
48b1be6a 878 .status = asix_status,
2e55cc72 879 .link_reset = ax88772_link_reset,
4ad1438f 880 .reset = ax88772_reset,
a9e0aca4 881 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
933a27d3
DH		 882 .rx_fixup = asix_rx_fixup,
883 .tx_fixup = asix_tx_fixup,
884};
885
5620df65
LS		 886static const struct driver_info ax88772b_info = {
887 .description = "ASIX AX88772B USB 2.0 Ethernet",
888 .bind = ax88772_bind,
889 .status = asix_status,
890 .link_reset = ax88772_link_reset,
891 .reset = ax88772_reset,
892 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
893 FLAG_MULTI_PACKET,
894 .rx_fixup = asix_rx_fixup,
895 .tx_fixup = asix_tx_fixup,
896 .data = FLAG_EEPROM_MAC,
897};
898
933a27d3
DH		 899static const struct driver_info ax88178_info = {
900 .description = "ASIX AX88178 USB 2.0 Ethernet",
901 .bind = ax88178_bind,
902 .status = asix_status,
903 .link_reset = ax88178_link_reset,
610d885d 904 .reset = ax88178_reset,
37e8273c 905 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR,
933a27d3
DH		 906 .rx_fixup = asix_rx_fixup,
907 .tx_fixup = asix_tx_fixup,
2e55cc72
DB		 908};
909
16626b0c
CR		 910extern const struct driver_info ax88172a_info;
911
2e55cc72
DB		 912static const struct usb_device_id products [] = {
913{
914 // Linksys USB200M
915 USB_DEVICE (0x077b, 0x2226),
916 .driver_info = (unsigned long) &ax8817x_info,
917}, {
918 // Netgear FA120
919 USB_DEVICE (0x0846, 0x1040),
920 .driver_info = (unsigned long) &netgear_fa120_info,
921}, {
922 // DLink DUB-E100
923 USB_DEVICE (0x2001, 0x1a00),
924 .driver_info = (unsigned long) &dlink_dub_e100_info,
925}, {
926 // Intellinet, ST Lab USB Ethernet
927 USB_DEVICE (0x0b95, 0x1720),
928 .driver_info = (unsigned long) &ax8817x_info,
929}, {
930 // Hawking UF200, TrendNet TU2-ET100
931 USB_DEVICE (0x07b8, 0x420a),
932 .driver_info = (unsigned long) &hawking_uf200_info,
933}, {
39c4b38c
DH		 934 // Billionton Systems, USB2AR
935 USB_DEVICE (0x08dd, 0x90ff),
936 .driver_info = (unsigned long) &ax8817x_info,
2e55cc72
DB		 937}, {
938 // ATEN UC210T
939 USB_DEVICE (0x0557, 0x2009),
940 .driver_info = (unsigned long) &ax8817x_info,
941}, {
942 // Buffalo LUA-U2-KTX
943 USB_DEVICE (0x0411, 0x003d),
944 .driver_info = (unsigned long) &ax8817x_info,
ac7b77f1
MD		 945}, {
946 // Buffalo LUA-U2-GT 10/100/1000
947 USB_DEVICE (0x0411, 0x006e),
948 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 949}, {
950 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
951 USB_DEVICE (0x6189, 0x182d),
952 .driver_info = (unsigned long) &ax8817x_info,
4e503919
JN		 953}, {
954 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
955 USB_DEVICE (0x0df6, 0x0056),
956 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 957}, {
958 // corega FEther USB2-TX
959 USB_DEVICE (0x07aa, 0x0017),
960 .driver_info = (unsigned long) &ax8817x_info,
961}, {
962 // Surecom EP-1427X-2
963 USB_DEVICE (0x1189, 0x0893),
964 .driver_info = (unsigned long) &ax8817x_info,
965}, {
966 // goodway corp usb gwusb2e
967 USB_DEVICE (0x1631, 0x6200),
968 .driver_info = (unsigned long) &ax8817x_info,
39c4b38c
DH		 969}, {
970 // JVC MP-PRX1 Port Replicator
971 USB_DEVICE (0x04f1, 0x3008),
972 .driver_info = (unsigned long) &ax8817x_info,
66dc81ec
QP		 973}, {
974 // Lenovo U2L100P 10/100
975 USB_DEVICE (0x17ef, 0x7203),
976 .driver_info = (unsigned long) &ax88772_info,
30885909
MV		 977}, {
978 // ASIX AX88772B 10/100
979 USB_DEVICE (0x0b95, 0x772b),
5620df65 980 .driver_info = (unsigned long) &ax88772b_info,
2e55cc72
DB		 981}, {
982 // ASIX AX88772 10/100
39c4b38c
DH		 983 USB_DEVICE (0x0b95, 0x7720),
984 .driver_info = (unsigned long) &ax88772_info,
7327413c
EW		 985}, {
986 // ASIX AX88178 10/100/1000
987 USB_DEVICE (0x0b95, 0x1780),
933a27d3 988 .driver_info = (unsigned long) &ax88178_info,
f4680d3d
AE		 989}, {
990 // Logitec LAN-GTJ/U2A
991 USB_DEVICE (0x0789, 0x0160),
992 .driver_info = (unsigned long) &ax88178_info,
5e0f76c6
DH		 993}, {
994 // Linksys USB200M Rev 2
995 USB_DEVICE (0x13b1, 0x0018),
996 .driver_info = (unsigned long) &ax88772_info,
5732ce84
DH		 997}, {
998 // 0Q0 cable ethernet
999 USB_DEVICE (0x1557, 0x7720),
1000 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1001}, {
1002 // DLink DUB-E100 H/W Ver B1
1003 USB_DEVICE (0x07d1, 0x3c05),
1004 .driver_info = (unsigned long) &ax88772_info,
b923e7fc
DH		 1005}, {
1006 // DLink DUB-E100 H/W Ver B1 Alternate
1007 USB_DEVICE (0x2001, 0x3c05),
1008 .driver_info = (unsigned long) &ax88772_info,
ed3770a9
S		 1009}, {
1010 // DLink DUB-E100 H/W Ver C1
1011 USB_DEVICE (0x2001, 0x1a02),
1012 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1013}, {
1014 // Linksys USB1000
1015 USB_DEVICE (0x1737, 0x0039),
1016 .driver_info = (unsigned long) &ax88178_info,
b29cf31d
YH		 1017}, {
1018 // IO-DATA ETG-US2
1019 USB_DEVICE (0x04bb, 0x0930),
1020 .driver_info = (unsigned long) &ax88178_info,
2ed22bc2
DH		 1021}, {
1022 // Belkin F5D5055
1023 USB_DEVICE(0x050d, 0x5055),
1024 .driver_info = (unsigned long) &ax88178_info,
3d60efb5
AN		 1025}, {
1026 // Apple USB Ethernet Adapter
1027 USB_DEVICE(0x05ac, 0x1402),
1028 .driver_info = (unsigned long) &ax88772_info,
ccf95402
JC		 1029}, {
1030 // Cables-to-Go USB Ethernet Adapter
1031 USB_DEVICE(0x0b95, 0x772a),
1032 .driver_info = (unsigned long) &ax88772_info,
fef7cc08
GKH		 1033}, {
1034 // ABOCOM for pci
1035 USB_DEVICE(0x14ea, 0xab11),
1036 .driver_info = (unsigned long) &ax88178_info,
1037}, {
1038 // ASIX 88772a
1039 USB_DEVICE(0x0db0, 0xa877),
1040 .driver_info = (unsigned long) &ax88772_info,
e8303a3b
AJ		 1041}, {
1042 // Asus USB Ethernet Adapter
1043 USB_DEVICE (0x0b95, 0x7e2b),
1044 .driver_info = (unsigned long) &ax88772_info,
16626b0c
CR		 1045}, {
1046 /* ASIX 88172a demo board */
1047 USB_DEVICE(0x0b95, 0x172a),
1048 .driver_info = (unsigned long) &ax88172a_info,
2e55cc72
DB		 1049},
1050 { }, // END
1051};
1052MODULE_DEVICE_TABLE(usb, products);
1053
1054static struct usb_driver asix_driver = {
83e1b918 1055 .name = DRIVER_NAME,
2e55cc72
DB		 1056 .id_table = products,
1057 .probe = usbnet_probe,
1058 .suspend = usbnet_suspend,
1059 .resume = usbnet_resume,
1060 .disconnect = usbnet_disconnect,
a11a6544 1061 .supports_autosuspend = 1,
e1f12eb6 1062 .disable_hub_initiated_lpm = 1,
2e55cc72
DB		 1063};
1064
d632eb1b 1065module_usb_driver(asix_driver);
2e55cc72
DB		 1066
1067MODULE_AUTHOR("David Hollis");
4ad1438f 1068MODULE_VERSION(DRIVER_VERSION);
2e55cc72
DB		 1069MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1070MODULE_LICENSE("GPL");
1071
Linux 6.x block layer and io_uring tree(s)