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2e55cc72 DB |
1 | /* |
2 | * ASIX AX8817X based USB 2.0 Ethernet Devices | |
933a27d3 | 3 | * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> |
2e55cc72 | 4 | * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> |
933a27d3 | 5 | * Copyright (C) 2006 James Painter <jamie.painter@iname.com> |
2e55cc72 DB |
6 | * Copyright (c) 2002-2003 TiVo Inc. |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | // #define DEBUG // error path messages, extra info | |
24 | // #define VERBOSE // more; success messages | |
25 | ||
2e55cc72 DB |
26 | #include <linux/module.h> |
27 | #include <linux/kmod.h> | |
2e55cc72 DB |
28 | #include <linux/init.h> |
29 | #include <linux/netdevice.h> | |
30 | #include <linux/etherdevice.h> | |
31 | #include <linux/ethtool.h> | |
32 | #include <linux/workqueue.h> | |
33 | #include <linux/mii.h> | |
34 | #include <linux/usb.h> | |
35 | #include <linux/crc32.h> | |
3692e94f | 36 | #include <linux/usb/usbnet.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
2e55cc72 | 38 | |
933a27d3 DH |
39 | #define DRIVER_VERSION "14-Jun-2006" |
40 | static const char driver_name [] = "asix"; | |
41 | ||
2e55cc72 DB |
42 | /* ASIX AX8817X based USB 2.0 Ethernet Devices */ |
43 | ||
44 | #define AX_CMD_SET_SW_MII 0x06 | |
45 | #define AX_CMD_READ_MII_REG 0x07 | |
46 | #define AX_CMD_WRITE_MII_REG 0x08 | |
47 | #define AX_CMD_SET_HW_MII 0x0a | |
48 | #define AX_CMD_READ_EEPROM 0x0b | |
49 | #define AX_CMD_WRITE_EEPROM 0x0c | |
50 | #define AX_CMD_WRITE_ENABLE 0x0d | |
51 | #define AX_CMD_WRITE_DISABLE 0x0e | |
933a27d3 | 52 | #define AX_CMD_READ_RX_CTL 0x0f |
2e55cc72 DB |
53 | #define AX_CMD_WRITE_RX_CTL 0x10 |
54 | #define AX_CMD_READ_IPG012 0x11 | |
55 | #define AX_CMD_WRITE_IPG0 0x12 | |
56 | #define AX_CMD_WRITE_IPG1 0x13 | |
933a27d3 | 57 | #define AX_CMD_READ_NODE_ID 0x13 |
7f29a3ba | 58 | #define AX_CMD_WRITE_NODE_ID 0x14 |
2e55cc72 DB |
59 | #define AX_CMD_WRITE_IPG2 0x14 |
60 | #define AX_CMD_WRITE_MULTI_FILTER 0x16 | |
933a27d3 | 61 | #define AX88172_CMD_READ_NODE_ID 0x17 |
2e55cc72 DB |
62 | #define AX_CMD_READ_PHY_ID 0x19 |
63 | #define AX_CMD_READ_MEDIUM_STATUS 0x1a | |
64 | #define AX_CMD_WRITE_MEDIUM_MODE 0x1b | |
65 | #define AX_CMD_READ_MONITOR_MODE 0x1c | |
66 | #define AX_CMD_WRITE_MONITOR_MODE 0x1d | |
933a27d3 | 67 | #define AX_CMD_READ_GPIOS 0x1e |
2e55cc72 DB |
68 | #define AX_CMD_WRITE_GPIOS 0x1f |
69 | #define AX_CMD_SW_RESET 0x20 | |
70 | #define AX_CMD_SW_PHY_STATUS 0x21 | |
71 | #define AX_CMD_SW_PHY_SELECT 0x22 | |
2e55cc72 DB |
72 | |
73 | #define AX_MONITOR_MODE 0x01 | |
74 | #define AX_MONITOR_LINK 0x02 | |
75 | #define AX_MONITOR_MAGIC 0x04 | |
76 | #define AX_MONITOR_HSFS 0x10 | |
77 | ||
78 | /* AX88172 Medium Status Register values */ | |
933a27d3 DH |
79 | #define AX88172_MEDIUM_FD 0x02 |
80 | #define AX88172_MEDIUM_TX 0x04 | |
81 | #define AX88172_MEDIUM_FC 0x10 | |
82 | #define AX88172_MEDIUM_DEFAULT \ | |
83 | ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC ) | |
2e55cc72 DB |
84 | |
85 | #define AX_MCAST_FILTER_SIZE 8 | |
86 | #define AX_MAX_MCAST 64 | |
87 | ||
2e55cc72 DB |
88 | #define AX_SWRESET_CLEAR 0x00 |
89 | #define AX_SWRESET_RR 0x01 | |
90 | #define AX_SWRESET_RT 0x02 | |
91 | #define AX_SWRESET_PRTE 0x04 | |
92 | #define AX_SWRESET_PRL 0x08 | |
93 | #define AX_SWRESET_BZ 0x10 | |
94 | #define AX_SWRESET_IPRL 0x20 | |
95 | #define AX_SWRESET_IPPD 0x40 | |
96 | ||
97 | #define AX88772_IPG0_DEFAULT 0x15 | |
98 | #define AX88772_IPG1_DEFAULT 0x0c | |
99 | #define AX88772_IPG2_DEFAULT 0x12 | |
100 | ||
933a27d3 DH |
101 | /* AX88772 & AX88178 Medium Mode Register */ |
102 | #define AX_MEDIUM_PF 0x0080 | |
103 | #define AX_MEDIUM_JFE 0x0040 | |
104 | #define AX_MEDIUM_TFC 0x0020 | |
105 | #define AX_MEDIUM_RFC 0x0010 | |
106 | #define AX_MEDIUM_ENCK 0x0008 | |
107 | #define AX_MEDIUM_AC 0x0004 | |
108 | #define AX_MEDIUM_FD 0x0002 | |
109 | #define AX_MEDIUM_GM 0x0001 | |
110 | #define AX_MEDIUM_SM 0x1000 | |
111 | #define AX_MEDIUM_SBP 0x0800 | |
112 | #define AX_MEDIUM_PS 0x0200 | |
113 | #define AX_MEDIUM_RE 0x0100 | |
114 | ||
115 | #define AX88178_MEDIUM_DEFAULT \ | |
116 | (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ | |
117 | AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ | |
118 | AX_MEDIUM_RE ) | |
2e55cc72 | 119 | |
933a27d3 DH |
120 | #define AX88772_MEDIUM_DEFAULT \ |
121 | (AX_MEDIUM_FD | AX_MEDIUM_RFC | \ | |
122 | AX_MEDIUM_TFC | AX_MEDIUM_PS | \ | |
123 | AX_MEDIUM_AC | AX_MEDIUM_RE ) | |
124 | ||
125 | /* AX88772 & AX88178 RX_CTL values */ | |
126 | #define AX_RX_CTL_SO 0x0080 | |
127 | #define AX_RX_CTL_AP 0x0020 | |
128 | #define AX_RX_CTL_AM 0x0010 | |
129 | #define AX_RX_CTL_AB 0x0008 | |
130 | #define AX_RX_CTL_SEP 0x0004 | |
131 | #define AX_RX_CTL_AMALL 0x0002 | |
132 | #define AX_RX_CTL_PRO 0x0001 | |
133 | #define AX_RX_CTL_MFB_2048 0x0000 | |
134 | #define AX_RX_CTL_MFB_4096 0x0100 | |
135 | #define AX_RX_CTL_MFB_8192 0x0200 | |
136 | #define AX_RX_CTL_MFB_16384 0x0300 | |
137 | ||
138 | #define AX_DEFAULT_RX_CTL \ | |
139 | (AX_RX_CTL_SO | AX_RX_CTL_AB ) | |
140 | ||
141 | /* GPIO 0 .. 2 toggles */ | |
142 | #define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */ | |
143 | #define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */ | |
144 | #define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */ | |
145 | #define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */ | |
146 | #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ | |
147 | #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ | |
148 | #define AX_GPIO_RESERVED 0x40 /* Reserved */ | |
149 | #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ | |
150 | ||
151 | #define AX_EEPROM_MAGIC 0xdeadbeef | |
152 | #define AX88172_EEPROM_LEN 0x40 | |
153 | #define AX88772_EEPROM_LEN 0xff | |
154 | ||
155 | #define PHY_MODE_MARVELL 0x0000 | |
156 | #define MII_MARVELL_LED_CTRL 0x0018 | |
157 | #define MII_MARVELL_STATUS 0x001b | |
158 | #define MII_MARVELL_CTRL 0x0014 | |
159 | ||
160 | #define MARVELL_LED_MANUAL 0x0019 | |
161 | ||
162 | #define MARVELL_STATUS_HWCFG 0x0004 | |
163 | ||
164 | #define MARVELL_CTRL_TXDELAY 0x0002 | |
165 | #define MARVELL_CTRL_RXDELAY 0x0080 | |
2e55cc72 DB |
166 | |
167 | /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */ | |
48b1be6a | 168 | struct asix_data { |
2e55cc72 | 169 | u8 multi_filter[AX_MCAST_FILTER_SIZE]; |
7f29a3ba | 170 | u8 mac_addr[ETH_ALEN]; |
933a27d3 DH |
171 | u8 phymode; |
172 | u8 ledmode; | |
173 | u8 eeprom_len; | |
2e55cc72 DB |
174 | }; |
175 | ||
176 | struct ax88172_int_data { | |
51bf2976 | 177 | __le16 res1; |
2e55cc72 | 178 | u8 link; |
51bf2976 | 179 | __le16 res2; |
2e55cc72 | 180 | u8 status; |
51bf2976 | 181 | __le16 res3; |
2e55cc72 DB |
182 | } __attribute__ ((packed)); |
183 | ||
48b1be6a | 184 | static int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, |
2e55cc72 DB |
185 | u16 size, void *data) |
186 | { | |
51bf2976 AV |
187 | void *buf; |
188 | int err = -ENOMEM; | |
189 | ||
60b86755 JP |
190 | netdev_dbg(dev->net, "asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", |
191 | cmd, value, index, size); | |
51bf2976 AV |
192 | |
193 | buf = kmalloc(size, GFP_KERNEL); | |
194 | if (!buf) | |
195 | goto out; | |
196 | ||
197 | err = usb_control_msg( | |
2e55cc72 DB |
198 | dev->udev, |
199 | usb_rcvctrlpipe(dev->udev, 0), | |
200 | cmd, | |
201 | USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
202 | value, | |
203 | index, | |
51bf2976 | 204 | buf, |
2e55cc72 DB |
205 | size, |
206 | USB_CTRL_GET_TIMEOUT); | |
94d43363 | 207 | if (err == size) |
51bf2976 | 208 | memcpy(data, buf, size); |
94d43363 RD |
209 | else if (err >= 0) |
210 | err = -EINVAL; | |
51bf2976 AV |
211 | kfree(buf); |
212 | ||
213 | out: | |
214 | return err; | |
2e55cc72 DB |
215 | } |
216 | ||
48b1be6a | 217 | static int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, |
2e55cc72 DB |
218 | u16 size, void *data) |
219 | { | |
51bf2976 AV |
220 | void *buf = NULL; |
221 | int err = -ENOMEM; | |
222 | ||
60b86755 JP |
223 | netdev_dbg(dev->net, "asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", |
224 | cmd, value, index, size); | |
51bf2976 AV |
225 | |
226 | if (data) { | |
99bf2366 | 227 | buf = kmemdup(data, size, GFP_KERNEL); |
51bf2976 AV |
228 | if (!buf) |
229 | goto out; | |
51bf2976 AV |
230 | } |
231 | ||
232 | err = usb_control_msg( | |
2e55cc72 DB |
233 | dev->udev, |
234 | usb_sndctrlpipe(dev->udev, 0), | |
235 | cmd, | |
236 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
237 | value, | |
238 | index, | |
51bf2976 | 239 | buf, |
2e55cc72 DB |
240 | size, |
241 | USB_CTRL_SET_TIMEOUT); | |
51bf2976 AV |
242 | kfree(buf); |
243 | ||
244 | out: | |
245 | return err; | |
2e55cc72 DB |
246 | } |
247 | ||
7d12e780 | 248 | static void asix_async_cmd_callback(struct urb *urb) |
2e55cc72 DB |
249 | { |
250 | struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)urb->context; | |
c94cb314 | 251 | int status = urb->status; |
2e55cc72 | 252 | |
c94cb314 | 253 | if (status < 0) |
48b1be6a | 254 | printk(KERN_DEBUG "asix_async_cmd_callback() failed with %d", |
c94cb314 | 255 | status); |
2e55cc72 DB |
256 | |
257 | kfree(req); | |
258 | usb_free_urb(urb); | |
259 | } | |
260 | ||
933a27d3 DH |
261 | static void |
262 | asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, u16 index, | |
263 | u16 size, void *data) | |
264 | { | |
265 | struct usb_ctrlrequest *req; | |
266 | int status; | |
267 | struct urb *urb; | |
268 | ||
60b86755 JP |
269 | netdev_dbg(dev->net, "asix_write_cmd_async() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", |
270 | cmd, value, index, size); | |
933a27d3 | 271 | if ((urb = usb_alloc_urb(0, GFP_ATOMIC)) == NULL) { |
60b86755 | 272 | netdev_err(dev->net, "Error allocating URB in write_cmd_async!\n"); |
933a27d3 DH |
273 | return; |
274 | } | |
275 | ||
276 | if ((req = kmalloc(sizeof(struct usb_ctrlrequest), GFP_ATOMIC)) == NULL) { | |
60b86755 | 277 | netdev_err(dev->net, "Failed to allocate memory for control request\n"); |
933a27d3 DH |
278 | usb_free_urb(urb); |
279 | return; | |
280 | } | |
281 | ||
282 | req->bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE; | |
283 | req->bRequest = cmd; | |
9aa742ef ON |
284 | req->wValue = cpu_to_le16(value); |
285 | req->wIndex = cpu_to_le16(index); | |
286 | req->wLength = cpu_to_le16(size); | |
933a27d3 DH |
287 | |
288 | usb_fill_control_urb(urb, dev->udev, | |
289 | usb_sndctrlpipe(dev->udev, 0), | |
290 | (void *)req, data, size, | |
291 | asix_async_cmd_callback, req); | |
292 | ||
293 | if((status = usb_submit_urb(urb, GFP_ATOMIC)) < 0) { | |
60b86755 JP |
294 | netdev_err(dev->net, "Error submitting the control message: status=%d\n", |
295 | status); | |
933a27d3 DH |
296 | kfree(req); |
297 | usb_free_urb(urb); | |
298 | } | |
299 | } | |
300 | ||
301 | static int asix_rx_fixup(struct usbnet *dev, struct sk_buff *skb) | |
302 | { | |
303 | u8 *head; | |
304 | u32 header; | |
305 | char *packet; | |
306 | struct sk_buff *ax_skb; | |
307 | u16 size; | |
308 | ||
309 | head = (u8 *) skb->data; | |
310 | memcpy(&header, head, sizeof(header)); | |
311 | le32_to_cpus(&header); | |
312 | packet = head + sizeof(header); | |
313 | ||
314 | skb_pull(skb, 4); | |
315 | ||
316 | while (skb->len > 0) { | |
317 | if ((short)(header & 0x0000ffff) != | |
318 | ~((short)((header & 0xffff0000) >> 16))) { | |
60b86755 | 319 | netdev_err(dev->net, "asix_rx_fixup() Bad Header Length\n"); |
933a27d3 DH |
320 | } |
321 | /* get the packet length */ | |
322 | size = (u16) (header & 0x0000ffff); | |
323 | ||
3f78d1f2 | 324 | if ((skb->len) - ((size + 1) & 0xfffe) == 0) { |
f925b130 | 325 | u8 alignment = (unsigned long)skb->data & 0x3; |
3f78d1f2 NJ |
326 | if (alignment != 0x2) { |
327 | /* | |
328 | * not 16bit aligned so use the room provided by | |
329 | * the 32 bit header to align the data | |
330 | * | |
331 | * note we want 16bit alignment as MAC header is | |
332 | * 14bytes thus ip header will be aligned on | |
333 | * 32bit boundary so accessing ipheader elements | |
334 | * using a cast to struct ip header wont cause | |
335 | * an unaligned accesses. | |
336 | */ | |
337 | u8 realignment = (alignment + 2) & 0x3; | |
338 | memmove(skb->data - realignment, | |
339 | skb->data, | |
340 | size); | |
341 | skb->data -= realignment; | |
342 | skb_set_tail_pointer(skb, size); | |
343 | } | |
933a27d3 | 344 | return 2; |
3f78d1f2 NJ |
345 | } |
346 | ||
933a27d3 | 347 | if (size > ETH_FRAME_LEN) { |
60b86755 JP |
348 | netdev_err(dev->net, "asix_rx_fixup() Bad RX Length %d\n", |
349 | size); | |
933a27d3 DH |
350 | return 0; |
351 | } | |
352 | ax_skb = skb_clone(skb, GFP_ATOMIC); | |
353 | if (ax_skb) { | |
f925b130 | 354 | u8 alignment = (unsigned long)packet & 0x3; |
933a27d3 | 355 | ax_skb->len = size; |
3f78d1f2 NJ |
356 | |
357 | if (alignment != 0x2) { | |
358 | /* | |
359 | * not 16bit aligned use the room provided by | |
360 | * the 32 bit header to align the data | |
361 | */ | |
362 | u8 realignment = (alignment + 2) & 0x3; | |
363 | memmove(packet - realignment, packet, size); | |
364 | packet -= realignment; | |
365 | } | |
933a27d3 | 366 | ax_skb->data = packet; |
27a884dc | 367 | skb_set_tail_pointer(ax_skb, size); |
933a27d3 DH |
368 | usbnet_skb_return(dev, ax_skb); |
369 | } else { | |
370 | return 0; | |
371 | } | |
372 | ||
373 | skb_pull(skb, (size + 1) & 0xfffe); | |
374 | ||
375 | if (skb->len == 0) | |
376 | break; | |
377 | ||
378 | head = (u8 *) skb->data; | |
379 | memcpy(&header, head, sizeof(header)); | |
380 | le32_to_cpus(&header); | |
381 | packet = head + sizeof(header); | |
382 | skb_pull(skb, 4); | |
383 | } | |
384 | ||
385 | if (skb->len < 0) { | |
60b86755 JP |
386 | netdev_err(dev->net, "asix_rx_fixup() Bad SKB Length %d\n", |
387 | skb->len); | |
933a27d3 DH |
388 | return 0; |
389 | } | |
390 | return 1; | |
391 | } | |
392 | ||
393 | static struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb, | |
394 | gfp_t flags) | |
395 | { | |
396 | int padlen; | |
397 | int headroom = skb_headroom(skb); | |
398 | int tailroom = skb_tailroom(skb); | |
399 | u32 packet_len; | |
400 | u32 padbytes = 0xffff0000; | |
401 | ||
402 | padlen = ((skb->len + 4) % 512) ? 0 : 4; | |
403 | ||
8e95a202 JP |
404 | if ((!skb_cloned(skb)) && |
405 | ((headroom + tailroom) >= (4 + padlen))) { | |
933a27d3 DH |
406 | if ((headroom < 4) || (tailroom < padlen)) { |
407 | skb->data = memmove(skb->head + 4, skb->data, skb->len); | |
27a884dc | 408 | skb_set_tail_pointer(skb, skb->len); |
933a27d3 DH |
409 | } |
410 | } else { | |
411 | struct sk_buff *skb2; | |
412 | skb2 = skb_copy_expand(skb, 4, padlen, flags); | |
413 | dev_kfree_skb_any(skb); | |
414 | skb = skb2; | |
415 | if (!skb) | |
416 | return NULL; | |
417 | } | |
418 | ||
419 | skb_push(skb, 4); | |
420 | packet_len = (((skb->len - 4) ^ 0x0000ffff) << 16) + (skb->len - 4); | |
57e4f041 | 421 | cpu_to_le32s(&packet_len); |
27d7ff46 | 422 | skb_copy_to_linear_data(skb, &packet_len, sizeof(packet_len)); |
933a27d3 DH |
423 | |
424 | if ((skb->len % 512) == 0) { | |
57e4f041 | 425 | cpu_to_le32s(&padbytes); |
27a884dc | 426 | memcpy(skb_tail_pointer(skb), &padbytes, sizeof(padbytes)); |
933a27d3 DH |
427 | skb_put(skb, sizeof(padbytes)); |
428 | } | |
429 | return skb; | |
430 | } | |
431 | ||
432 | static void asix_status(struct usbnet *dev, struct urb *urb) | |
433 | { | |
434 | struct ax88172_int_data *event; | |
435 | int link; | |
436 | ||
437 | if (urb->actual_length < 8) | |
438 | return; | |
439 | ||
440 | event = urb->transfer_buffer; | |
441 | link = event->link & 0x01; | |
442 | if (netif_carrier_ok(dev->net) != link) { | |
443 | if (link) { | |
444 | netif_carrier_on(dev->net); | |
445 | usbnet_defer_kevent (dev, EVENT_LINK_RESET ); | |
446 | } else | |
447 | netif_carrier_off(dev->net); | |
60b86755 | 448 | netdev_dbg(dev->net, "Link Status is: %d\n", link); |
933a27d3 DH |
449 | } |
450 | } | |
451 | ||
48b1be6a DH |
452 | static inline int asix_set_sw_mii(struct usbnet *dev) |
453 | { | |
454 | int ret; | |
455 | ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL); | |
456 | if (ret < 0) | |
60b86755 | 457 | netdev_err(dev->net, "Failed to enable software MII access\n"); |
48b1be6a DH |
458 | return ret; |
459 | } | |
460 | ||
461 | static inline int asix_set_hw_mii(struct usbnet *dev) | |
462 | { | |
463 | int ret; | |
464 | ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL); | |
465 | if (ret < 0) | |
60b86755 | 466 | netdev_err(dev->net, "Failed to enable hardware MII access\n"); |
48b1be6a DH |
467 | return ret; |
468 | } | |
469 | ||
933a27d3 | 470 | static inline int asix_get_phy_addr(struct usbnet *dev) |
48b1be6a | 471 | { |
51bf2976 AV |
472 | u8 buf[2]; |
473 | int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf); | |
48b1be6a | 474 | |
60b86755 | 475 | netdev_dbg(dev->net, "asix_get_phy_addr()\n"); |
933a27d3 | 476 | |
51bf2976 | 477 | if (ret < 0) { |
60b86755 | 478 | netdev_err(dev->net, "Error reading PHYID register: %02x\n", ret); |
51bf2976 | 479 | goto out; |
48b1be6a | 480 | } |
60b86755 JP |
481 | netdev_dbg(dev->net, "asix_get_phy_addr() returning 0x%04x\n", |
482 | *((__le16 *)buf)); | |
51bf2976 AV |
483 | ret = buf[1]; |
484 | ||
485 | out: | |
48b1be6a DH |
486 | return ret; |
487 | } | |
488 | ||
489 | static int asix_sw_reset(struct usbnet *dev, u8 flags) | |
490 | { | |
491 | int ret; | |
492 | ||
493 | ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL); | |
494 | if (ret < 0) | |
60b86755 | 495 | netdev_err(dev->net, "Failed to send software reset: %02x\n", ret); |
933a27d3 DH |
496 | |
497 | return ret; | |
498 | } | |
48b1be6a | 499 | |
933a27d3 DH |
500 | static u16 asix_read_rx_ctl(struct usbnet *dev) |
501 | { | |
51bf2976 AV |
502 | __le16 v; |
503 | int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, &v); | |
933a27d3 | 504 | |
51bf2976 | 505 | if (ret < 0) { |
60b86755 | 506 | netdev_err(dev->net, "Error reading RX_CTL register: %02x\n", ret); |
51bf2976 | 507 | goto out; |
933a27d3 | 508 | } |
51bf2976 AV |
509 | ret = le16_to_cpu(v); |
510 | out: | |
48b1be6a DH |
511 | return ret; |
512 | } | |
513 | ||
514 | static int asix_write_rx_ctl(struct usbnet *dev, u16 mode) | |
515 | { | |
516 | int ret; | |
517 | ||
60b86755 | 518 | netdev_dbg(dev->net, "asix_write_rx_ctl() - mode = 0x%04x\n", mode); |
48b1be6a DH |
519 | ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL); |
520 | if (ret < 0) | |
60b86755 JP |
521 | netdev_err(dev->net, "Failed to write RX_CTL mode to 0x%04x: %02x\n", |
522 | mode, ret); | |
48b1be6a DH |
523 | |
524 | return ret; | |
525 | } | |
526 | ||
933a27d3 | 527 | static u16 asix_read_medium_status(struct usbnet *dev) |
2e55cc72 | 528 | { |
51bf2976 AV |
529 | __le16 v; |
530 | int ret = asix_read_cmd(dev, AX_CMD_READ_MEDIUM_STATUS, 0, 0, 2, &v); | |
2e55cc72 | 531 | |
51bf2976 | 532 | if (ret < 0) { |
60b86755 JP |
533 | netdev_err(dev->net, "Error reading Medium Status register: %02x\n", |
534 | ret); | |
51bf2976 | 535 | goto out; |
2e55cc72 | 536 | } |
51bf2976 AV |
537 | ret = le16_to_cpu(v); |
538 | out: | |
933a27d3 | 539 | return ret; |
2e55cc72 DB |
540 | } |
541 | ||
933a27d3 | 542 | static int asix_write_medium_mode(struct usbnet *dev, u16 mode) |
2e55cc72 | 543 | { |
933a27d3 | 544 | int ret; |
2e55cc72 | 545 | |
60b86755 | 546 | netdev_dbg(dev->net, "asix_write_medium_mode() - mode = 0x%04x\n", mode); |
933a27d3 DH |
547 | ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, 0, NULL); |
548 | if (ret < 0) | |
60b86755 JP |
549 | netdev_err(dev->net, "Failed to write Medium Mode mode to 0x%04x: %02x\n", |
550 | mode, ret); | |
2e55cc72 | 551 | |
933a27d3 DH |
552 | return ret; |
553 | } | |
2e55cc72 | 554 | |
933a27d3 DH |
555 | static int asix_write_gpio(struct usbnet *dev, u16 value, int sleep) |
556 | { | |
557 | int ret; | |
2e55cc72 | 558 | |
60b86755 | 559 | netdev_dbg(dev->net, "asix_write_gpio() - value = 0x%04x\n", value); |
933a27d3 DH |
560 | ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL); |
561 | if (ret < 0) | |
60b86755 JP |
562 | netdev_err(dev->net, "Failed to write GPIO value 0x%04x: %02x\n", |
563 | value, ret); | |
2e55cc72 | 564 | |
933a27d3 DH |
565 | if (sleep) |
566 | msleep(sleep); | |
567 | ||
568 | return ret; | |
2e55cc72 DB |
569 | } |
570 | ||
933a27d3 DH |
571 | /* |
572 | * AX88772 & AX88178 have a 16-bit RX_CTL value | |
573 | */ | |
48b1be6a | 574 | static void asix_set_multicast(struct net_device *net) |
2e55cc72 DB |
575 | { |
576 | struct usbnet *dev = netdev_priv(net); | |
48b1be6a | 577 | struct asix_data *data = (struct asix_data *)&dev->data; |
933a27d3 | 578 | u16 rx_ctl = AX_DEFAULT_RX_CTL; |
2e55cc72 DB |
579 | |
580 | if (net->flags & IFF_PROMISC) { | |
933a27d3 | 581 | rx_ctl |= AX_RX_CTL_PRO; |
8e95a202 | 582 | } else if (net->flags & IFF_ALLMULTI || |
4cd24eaf | 583 | netdev_mc_count(net) > AX_MAX_MCAST) { |
933a27d3 | 584 | rx_ctl |= AX_RX_CTL_AMALL; |
4cd24eaf | 585 | } else if (netdev_mc_empty(net)) { |
2e55cc72 DB |
586 | /* just broadcast and directed */ |
587 | } else { | |
588 | /* We use the 20 byte dev->data | |
589 | * for our 8 byte filter buffer | |
590 | * to avoid allocating memory that | |
591 | * is tricky to free later */ | |
22bedad3 | 592 | struct netdev_hw_addr *ha; |
2e55cc72 | 593 | u32 crc_bits; |
2e55cc72 DB |
594 | |
595 | memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); | |
596 | ||
597 | /* Build the multicast hash filter. */ | |
22bedad3 JP |
598 | netdev_for_each_mc_addr(ha, net) { |
599 | crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
2e55cc72 DB |
600 | data->multi_filter[crc_bits >> 3] |= |
601 | 1 << (crc_bits & 7); | |
2e55cc72 DB |
602 | } |
603 | ||
48b1be6a | 604 | asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, |
2e55cc72 DB |
605 | AX_MCAST_FILTER_SIZE, data->multi_filter); |
606 | ||
933a27d3 | 607 | rx_ctl |= AX_RX_CTL_AM; |
2e55cc72 DB |
608 | } |
609 | ||
48b1be6a | 610 | asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); |
2e55cc72 DB |
611 | } |
612 | ||
48b1be6a | 613 | static int asix_mdio_read(struct net_device *netdev, int phy_id, int loc) |
2e55cc72 DB |
614 | { |
615 | struct usbnet *dev = netdev_priv(netdev); | |
51bf2976 | 616 | __le16 res; |
2e55cc72 | 617 | |
a9fc6338 | 618 | mutex_lock(&dev->phy_mutex); |
48b1be6a DH |
619 | asix_set_sw_mii(dev); |
620 | asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, | |
51bf2976 | 621 | (__u16)loc, 2, &res); |
48b1be6a | 622 | asix_set_hw_mii(dev); |
a9fc6338 | 623 | mutex_unlock(&dev->phy_mutex); |
2e55cc72 | 624 | |
60b86755 JP |
625 | netdev_dbg(dev->net, "asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n", |
626 | phy_id, loc, le16_to_cpu(res)); | |
2e55cc72 | 627 | |
51bf2976 | 628 | return le16_to_cpu(res); |
2e55cc72 DB |
629 | } |
630 | ||
631 | static void | |
48b1be6a | 632 | asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val) |
2e55cc72 DB |
633 | { |
634 | struct usbnet *dev = netdev_priv(netdev); | |
51bf2976 | 635 | __le16 res = cpu_to_le16(val); |
2e55cc72 | 636 | |
60b86755 JP |
637 | netdev_dbg(dev->net, "asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n", |
638 | phy_id, loc, val); | |
a9fc6338 | 639 | mutex_lock(&dev->phy_mutex); |
48b1be6a | 640 | asix_set_sw_mii(dev); |
51bf2976 | 641 | asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, &res); |
48b1be6a | 642 | asix_set_hw_mii(dev); |
a9fc6338 | 643 | mutex_unlock(&dev->phy_mutex); |
2e55cc72 DB |
644 | } |
645 | ||
933a27d3 DH |
646 | /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ |
647 | static u32 asix_get_phyid(struct usbnet *dev) | |
2e55cc72 | 648 | { |
933a27d3 DH |
649 | int phy_reg; |
650 | u32 phy_id; | |
2e55cc72 | 651 | |
933a27d3 DH |
652 | phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); |
653 | if (phy_reg < 0) | |
654 | return 0; | |
2e55cc72 | 655 | |
933a27d3 | 656 | phy_id = (phy_reg & 0xffff) << 16; |
2e55cc72 | 657 | |
933a27d3 DH |
658 | phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); |
659 | if (phy_reg < 0) | |
660 | return 0; | |
661 | ||
662 | phy_id |= (phy_reg & 0xffff); | |
663 | ||
664 | return phy_id; | |
2e55cc72 DB |
665 | } |
666 | ||
667 | static void | |
48b1be6a | 668 | asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) |
2e55cc72 DB |
669 | { |
670 | struct usbnet *dev = netdev_priv(net); | |
671 | u8 opt; | |
672 | ||
48b1be6a | 673 | if (asix_read_cmd(dev, AX_CMD_READ_MONITOR_MODE, 0, 0, 1, &opt) < 0) { |
2e55cc72 DB |
674 | wolinfo->supported = 0; |
675 | wolinfo->wolopts = 0; | |
676 | return; | |
677 | } | |
678 | wolinfo->supported = WAKE_PHY | WAKE_MAGIC; | |
679 | wolinfo->wolopts = 0; | |
680 | if (opt & AX_MONITOR_MODE) { | |
681 | if (opt & AX_MONITOR_LINK) | |
682 | wolinfo->wolopts |= WAKE_PHY; | |
683 | if (opt & AX_MONITOR_MAGIC) | |
684 | wolinfo->wolopts |= WAKE_MAGIC; | |
685 | } | |
686 | } | |
687 | ||
688 | static int | |
48b1be6a | 689 | asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) |
2e55cc72 DB |
690 | { |
691 | struct usbnet *dev = netdev_priv(net); | |
692 | u8 opt = 0; | |
2e55cc72 DB |
693 | |
694 | if (wolinfo->wolopts & WAKE_PHY) | |
695 | opt |= AX_MONITOR_LINK; | |
696 | if (wolinfo->wolopts & WAKE_MAGIC) | |
697 | opt |= AX_MONITOR_MAGIC; | |
698 | if (opt != 0) | |
699 | opt |= AX_MONITOR_MODE; | |
700 | ||
48b1be6a | 701 | if (asix_write_cmd(dev, AX_CMD_WRITE_MONITOR_MODE, |
51bf2976 | 702 | opt, 0, 0, NULL) < 0) |
2e55cc72 DB |
703 | return -EINVAL; |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
48b1be6a | 708 | static int asix_get_eeprom_len(struct net_device *net) |
2e55cc72 | 709 | { |
933a27d3 DH |
710 | struct usbnet *dev = netdev_priv(net); |
711 | struct asix_data *data = (struct asix_data *)&dev->data; | |
712 | ||
713 | return data->eeprom_len; | |
2e55cc72 DB |
714 | } |
715 | ||
48b1be6a | 716 | static int asix_get_eeprom(struct net_device *net, |
2e55cc72 DB |
717 | struct ethtool_eeprom *eeprom, u8 *data) |
718 | { | |
719 | struct usbnet *dev = netdev_priv(net); | |
51bf2976 | 720 | __le16 *ebuf = (__le16 *)data; |
2e55cc72 DB |
721 | int i; |
722 | ||
723 | /* Crude hack to ensure that we don't overwrite memory | |
724 | * if an odd length is supplied | |
725 | */ | |
726 | if (eeprom->len % 2) | |
727 | return -EINVAL; | |
728 | ||
729 | eeprom->magic = AX_EEPROM_MAGIC; | |
730 | ||
731 | /* ax8817x returns 2 bytes from eeprom on read */ | |
732 | for (i=0; i < eeprom->len / 2; i++) { | |
48b1be6a | 733 | if (asix_read_cmd(dev, AX_CMD_READ_EEPROM, |
2e55cc72 DB |
734 | eeprom->offset + i, 0, 2, &ebuf[i]) < 0) |
735 | return -EINVAL; | |
736 | } | |
737 | return 0; | |
738 | } | |
739 | ||
48b1be6a | 740 | static void asix_get_drvinfo (struct net_device *net, |
2e55cc72 DB |
741 | struct ethtool_drvinfo *info) |
742 | { | |
933a27d3 DH |
743 | struct usbnet *dev = netdev_priv(net); |
744 | struct asix_data *data = (struct asix_data *)&dev->data; | |
745 | ||
2e55cc72 DB |
746 | /* Inherit standard device info */ |
747 | usbnet_get_drvinfo(net, info); | |
933a27d3 DH |
748 | strncpy (info->driver, driver_name, sizeof info->driver); |
749 | strncpy (info->version, DRIVER_VERSION, sizeof info->version); | |
750 | info->eedump_len = data->eeprom_len; | |
2e55cc72 DB |
751 | } |
752 | ||
933a27d3 DH |
753 | static u32 asix_get_link(struct net_device *net) |
754 | { | |
755 | struct usbnet *dev = netdev_priv(net); | |
756 | ||
757 | return mii_link_ok(&dev->mii); | |
758 | } | |
759 | ||
760 | static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) | |
761 | { | |
762 | struct usbnet *dev = netdev_priv(net); | |
763 | ||
764 | return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); | |
765 | } | |
766 | ||
7f29a3ba JK |
767 | static int asix_set_mac_address(struct net_device *net, void *p) |
768 | { | |
769 | struct usbnet *dev = netdev_priv(net); | |
770 | struct asix_data *data = (struct asix_data *)&dev->data; | |
771 | struct sockaddr *addr = p; | |
772 | ||
773 | if (netif_running(net)) | |
774 | return -EBUSY; | |
775 | if (!is_valid_ether_addr(addr->sa_data)) | |
776 | return -EADDRNOTAVAIL; | |
777 | ||
778 | memcpy(net->dev_addr, addr->sa_data, ETH_ALEN); | |
779 | ||
780 | /* We use the 20 byte dev->data | |
781 | * for our 6 byte mac buffer | |
782 | * to avoid allocating memory that | |
783 | * is tricky to free later */ | |
784 | memcpy(data->mac_addr, addr->sa_data, ETH_ALEN); | |
785 | asix_write_cmd_async(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, | |
786 | data->mac_addr); | |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
933a27d3 DH |
791 | /* We need to override some ethtool_ops so we require our |
792 | own structure so we don't interfere with other usbnet | |
793 | devices that may be connected at the same time. */ | |
0fc0b732 | 794 | static const struct ethtool_ops ax88172_ethtool_ops = { |
933a27d3 DH |
795 | .get_drvinfo = asix_get_drvinfo, |
796 | .get_link = asix_get_link, | |
933a27d3 | 797 | .get_msglevel = usbnet_get_msglevel, |
2e55cc72 | 798 | .set_msglevel = usbnet_set_msglevel, |
48b1be6a DH |
799 | .get_wol = asix_get_wol, |
800 | .set_wol = asix_set_wol, | |
801 | .get_eeprom_len = asix_get_eeprom_len, | |
802 | .get_eeprom = asix_get_eeprom, | |
c41286fd AB |
803 | .get_settings = usbnet_get_settings, |
804 | .set_settings = usbnet_set_settings, | |
805 | .nway_reset = usbnet_nway_reset, | |
2e55cc72 DB |
806 | }; |
807 | ||
933a27d3 | 808 | static void ax88172_set_multicast(struct net_device *net) |
2e55cc72 DB |
809 | { |
810 | struct usbnet *dev = netdev_priv(net); | |
933a27d3 DH |
811 | struct asix_data *data = (struct asix_data *)&dev->data; |
812 | u8 rx_ctl = 0x8c; | |
2e55cc72 | 813 | |
933a27d3 DH |
814 | if (net->flags & IFF_PROMISC) { |
815 | rx_ctl |= 0x01; | |
8e95a202 | 816 | } else if (net->flags & IFF_ALLMULTI || |
4cd24eaf | 817 | netdev_mc_count(net) > AX_MAX_MCAST) { |
933a27d3 | 818 | rx_ctl |= 0x02; |
4cd24eaf | 819 | } else if (netdev_mc_empty(net)) { |
933a27d3 DH |
820 | /* just broadcast and directed */ |
821 | } else { | |
822 | /* We use the 20 byte dev->data | |
823 | * for our 8 byte filter buffer | |
824 | * to avoid allocating memory that | |
825 | * is tricky to free later */ | |
22bedad3 | 826 | struct netdev_hw_addr *ha; |
933a27d3 | 827 | u32 crc_bits; |
933a27d3 DH |
828 | |
829 | memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); | |
830 | ||
831 | /* Build the multicast hash filter. */ | |
22bedad3 JP |
832 | netdev_for_each_mc_addr(ha, net) { |
833 | crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
933a27d3 DH |
834 | data->multi_filter[crc_bits >> 3] |= |
835 | 1 << (crc_bits & 7); | |
933a27d3 DH |
836 | } |
837 | ||
838 | asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, | |
839 | AX_MCAST_FILTER_SIZE, data->multi_filter); | |
840 | ||
841 | rx_ctl |= 0x10; | |
842 | } | |
843 | ||
844 | asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); | |
845 | } | |
846 | ||
847 | static int ax88172_link_reset(struct usbnet *dev) | |
848 | { | |
849 | u8 mode; | |
850 | struct ethtool_cmd ecmd; | |
851 | ||
852 | mii_check_media(&dev->mii, 1, 1); | |
853 | mii_ethtool_gset(&dev->mii, &ecmd); | |
854 | mode = AX88172_MEDIUM_DEFAULT; | |
855 | ||
856 | if (ecmd.duplex != DUPLEX_FULL) | |
857 | mode |= ~AX88172_MEDIUM_FD; | |
858 | ||
60b86755 JP |
859 | netdev_dbg(dev->net, "ax88172_link_reset() speed: %d duplex: %d setting mode to 0x%04x\n", |
860 | ecmd.speed, ecmd.duplex, mode); | |
933a27d3 DH |
861 | |
862 | asix_write_medium_mode(dev, mode); | |
863 | ||
864 | return 0; | |
2e55cc72 DB |
865 | } |
866 | ||
1703338c SH |
867 | static const struct net_device_ops ax88172_netdev_ops = { |
868 | .ndo_open = usbnet_open, | |
869 | .ndo_stop = usbnet_stop, | |
870 | .ndo_start_xmit = usbnet_start_xmit, | |
871 | .ndo_tx_timeout = usbnet_tx_timeout, | |
872 | .ndo_change_mtu = usbnet_change_mtu, | |
873 | .ndo_set_mac_address = eth_mac_addr, | |
874 | .ndo_validate_addr = eth_validate_addr, | |
875 | .ndo_do_ioctl = asix_ioctl, | |
876 | .ndo_set_multicast_list = ax88172_set_multicast, | |
877 | }; | |
878 | ||
48b1be6a | 879 | static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) |
2e55cc72 DB |
880 | { |
881 | int ret = 0; | |
51bf2976 | 882 | u8 buf[ETH_ALEN]; |
2e55cc72 DB |
883 | int i; |
884 | unsigned long gpio_bits = dev->driver_info->data; | |
933a27d3 DH |
885 | struct asix_data *data = (struct asix_data *)&dev->data; |
886 | ||
887 | data->eeprom_len = AX88172_EEPROM_LEN; | |
2e55cc72 DB |
888 | |
889 | usbnet_get_endpoints(dev,intf); | |
890 | ||
2e55cc72 DB |
891 | /* Toggle the GPIOs in a manufacturer/model specific way */ |
892 | for (i = 2; i >= 0; i--) { | |
48b1be6a | 893 | if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, |
2e55cc72 | 894 | (gpio_bits >> (i * 8)) & 0xff, 0, 0, |
51bf2976 AV |
895 | NULL)) < 0) |
896 | goto out; | |
2e55cc72 DB |
897 | msleep(5); |
898 | } | |
899 | ||
933a27d3 | 900 | if ((ret = asix_write_rx_ctl(dev, 0x80)) < 0) |
51bf2976 | 901 | goto out; |
2e55cc72 DB |
902 | |
903 | /* Get the MAC address */ | |
933a27d3 | 904 | if ((ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, |
51bf2976 | 905 | 0, 0, ETH_ALEN, buf)) < 0) { |
2e55cc72 | 906 | dbg("read AX_CMD_READ_NODE_ID failed: %d", ret); |
51bf2976 | 907 | goto out; |
2e55cc72 DB |
908 | } |
909 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); | |
910 | ||
2e55cc72 DB |
911 | /* Initialize MII structure */ |
912 | dev->mii.dev = dev->net; | |
48b1be6a DH |
913 | dev->mii.mdio_read = asix_mdio_read; |
914 | dev->mii.mdio_write = asix_mdio_write; | |
2e55cc72 DB |
915 | dev->mii.phy_id_mask = 0x3f; |
916 | dev->mii.reg_num_mask = 0x1f; | |
933a27d3 | 917 | dev->mii.phy_id = asix_get_phy_addr(dev); |
2e55cc72 | 918 | |
1703338c | 919 | dev->net->netdev_ops = &ax88172_netdev_ops; |
48b1be6a | 920 | dev->net->ethtool_ops = &ax88172_ethtool_ops; |
2e55cc72 | 921 | |
933a27d3 DH |
922 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
923 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
2e55cc72 DB |
924 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); |
925 | mii_nway_restart(&dev->mii); | |
926 | ||
927 | return 0; | |
51bf2976 AV |
928 | |
929 | out: | |
2e55cc72 DB |
930 | return ret; |
931 | } | |
932 | ||
0fc0b732 | 933 | static const struct ethtool_ops ax88772_ethtool_ops = { |
48b1be6a | 934 | .get_drvinfo = asix_get_drvinfo, |
933a27d3 | 935 | .get_link = asix_get_link, |
2e55cc72 DB |
936 | .get_msglevel = usbnet_get_msglevel, |
937 | .set_msglevel = usbnet_set_msglevel, | |
48b1be6a DH |
938 | .get_wol = asix_get_wol, |
939 | .set_wol = asix_set_wol, | |
940 | .get_eeprom_len = asix_get_eeprom_len, | |
941 | .get_eeprom = asix_get_eeprom, | |
c41286fd AB |
942 | .get_settings = usbnet_get_settings, |
943 | .set_settings = usbnet_set_settings, | |
944 | .nway_reset = usbnet_nway_reset, | |
2e55cc72 DB |
945 | }; |
946 | ||
933a27d3 DH |
947 | static int ax88772_link_reset(struct usbnet *dev) |
948 | { | |
949 | u16 mode; | |
950 | struct ethtool_cmd ecmd; | |
951 | ||
952 | mii_check_media(&dev->mii, 1, 1); | |
953 | mii_ethtool_gset(&dev->mii, &ecmd); | |
954 | mode = AX88772_MEDIUM_DEFAULT; | |
955 | ||
956 | if (ecmd.speed != SPEED_100) | |
957 | mode &= ~AX_MEDIUM_PS; | |
958 | ||
959 | if (ecmd.duplex != DUPLEX_FULL) | |
960 | mode &= ~AX_MEDIUM_FD; | |
961 | ||
60b86755 JP |
962 | netdev_dbg(dev->net, "ax88772_link_reset() speed: %d duplex: %d setting mode to 0x%04x\n", |
963 | ecmd.speed, ecmd.duplex, mode); | |
933a27d3 DH |
964 | |
965 | asix_write_medium_mode(dev, mode); | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
1703338c SH |
970 | static const struct net_device_ops ax88772_netdev_ops = { |
971 | .ndo_open = usbnet_open, | |
972 | .ndo_stop = usbnet_stop, | |
973 | .ndo_start_xmit = usbnet_start_xmit, | |
974 | .ndo_tx_timeout = usbnet_tx_timeout, | |
975 | .ndo_change_mtu = usbnet_change_mtu, | |
7f29a3ba | 976 | .ndo_set_mac_address = asix_set_mac_address, |
1703338c SH |
977 | .ndo_validate_addr = eth_validate_addr, |
978 | .ndo_do_ioctl = asix_ioctl, | |
979 | .ndo_set_multicast_list = asix_set_multicast, | |
980 | }; | |
981 | ||
2e55cc72 DB |
982 | static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) |
983 | { | |
d0ffff8f | 984 | int ret, embd_phy; |
933a27d3 DH |
985 | u16 rx_ctl; |
986 | struct asix_data *data = (struct asix_data *)&dev->data; | |
51bf2976 | 987 | u8 buf[ETH_ALEN]; |
933a27d3 DH |
988 | u32 phyid; |
989 | ||
990 | data->eeprom_len = AX88772_EEPROM_LEN; | |
2e55cc72 DB |
991 | |
992 | usbnet_get_endpoints(dev,intf); | |
993 | ||
933a27d3 DH |
994 | if ((ret = asix_write_gpio(dev, |
995 | AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5)) < 0) | |
51bf2976 | 996 | goto out; |
2e55cc72 | 997 | |
d0ffff8f AS |
998 | /* 0x10 is the phy id of the embedded 10/100 ethernet phy */ |
999 | embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0); | |
48b1be6a | 1000 | if ((ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, |
51bf2976 | 1001 | embd_phy, 0, 0, NULL)) < 0) { |
2e55cc72 | 1002 | dbg("Select PHY #1 failed: %d", ret); |
51bf2976 | 1003 | goto out; |
2e55cc72 DB |
1004 | } |
1005 | ||
d0ffff8f | 1006 | if ((ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL)) < 0) |
51bf2976 | 1007 | goto out; |
2e55cc72 DB |
1008 | |
1009 | msleep(150); | |
48b1be6a | 1010 | if ((ret = asix_sw_reset(dev, AX_SWRESET_CLEAR)) < 0) |
51bf2976 | 1011 | goto out; |
2e55cc72 DB |
1012 | |
1013 | msleep(150); | |
d0ffff8f AS |
1014 | if (embd_phy) { |
1015 | if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL)) < 0) | |
51bf2976 | 1016 | goto out; |
d0ffff8f AS |
1017 | } |
1018 | else { | |
1019 | if ((ret = asix_sw_reset(dev, AX_SWRESET_PRTE)) < 0) | |
51bf2976 | 1020 | goto out; |
d0ffff8f | 1021 | } |
2e55cc72 DB |
1022 | |
1023 | msleep(150); | |
933a27d3 DH |
1024 | rx_ctl = asix_read_rx_ctl(dev); |
1025 | dbg("RX_CTL is 0x%04x after software reset", rx_ctl); | |
1026 | if ((ret = asix_write_rx_ctl(dev, 0x0000)) < 0) | |
51bf2976 | 1027 | goto out; |
2e55cc72 | 1028 | |
933a27d3 DH |
1029 | rx_ctl = asix_read_rx_ctl(dev); |
1030 | dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl); | |
1031 | ||
2e55cc72 | 1032 | /* Get the MAC address */ |
933a27d3 | 1033 | if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, |
2e55cc72 DB |
1034 | 0, 0, ETH_ALEN, buf)) < 0) { |
1035 | dbg("Failed to read MAC address: %d", ret); | |
51bf2976 | 1036 | goto out; |
2e55cc72 DB |
1037 | } |
1038 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); | |
1039 | ||
2e55cc72 DB |
1040 | /* Initialize MII structure */ |
1041 | dev->mii.dev = dev->net; | |
48b1be6a DH |
1042 | dev->mii.mdio_read = asix_mdio_read; |
1043 | dev->mii.mdio_write = asix_mdio_write; | |
933a27d3 DH |
1044 | dev->mii.phy_id_mask = 0x1f; |
1045 | dev->mii.reg_num_mask = 0x1f; | |
933a27d3 DH |
1046 | dev->mii.phy_id = asix_get_phy_addr(dev); |
1047 | ||
1048 | phyid = asix_get_phyid(dev); | |
1049 | dbg("PHYID=0x%08x", phyid); | |
2e55cc72 | 1050 | |
48b1be6a | 1051 | if ((ret = asix_sw_reset(dev, AX_SWRESET_PRL)) < 0) |
51bf2976 | 1052 | goto out; |
2e55cc72 | 1053 | |
2e55cc72 | 1054 | msleep(150); |
48b1be6a DH |
1055 | |
1056 | if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL)) < 0) | |
51bf2976 | 1057 | goto out; |
2e55cc72 | 1058 | |
48b1be6a | 1059 | msleep(150); |
2e55cc72 | 1060 | |
1703338c | 1061 | dev->net->netdev_ops = &ax88772_netdev_ops; |
2e55cc72 DB |
1062 | dev->net->ethtool_ops = &ax88772_ethtool_ops; |
1063 | ||
933a27d3 DH |
1064 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
1065 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
2e55cc72 DB |
1066 | ADVERTISE_ALL | ADVERTISE_CSMA); |
1067 | mii_nway_restart(&dev->mii); | |
1068 | ||
933a27d3 | 1069 | if ((ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT)) < 0) |
51bf2976 | 1070 | goto out; |
2e55cc72 | 1071 | |
48b1be6a | 1072 | if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, |
2e55cc72 | 1073 | AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, |
51bf2976 | 1074 | AX88772_IPG2_DEFAULT, 0, NULL)) < 0) { |
2e55cc72 | 1075 | dbg("Write IPG,IPG1,IPG2 failed: %d", ret); |
51bf2976 | 1076 | goto out; |
2e55cc72 | 1077 | } |
2e55cc72 DB |
1078 | |
1079 | /* Set RX_CTL to default values with 2k buffer, and enable cactus */ | |
933a27d3 | 1080 | if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0) |
51bf2976 | 1081 | goto out; |
2e55cc72 | 1082 | |
933a27d3 DH |
1083 | rx_ctl = asix_read_rx_ctl(dev); |
1084 | dbg("RX_CTL is 0x%04x after all initializations", rx_ctl); | |
1085 | ||
1086 | rx_ctl = asix_read_medium_status(dev); | |
1087 | dbg("Medium Status is 0x%04x after all initializations", rx_ctl); | |
1088 | ||
2e55cc72 DB |
1089 | /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ |
1090 | if (dev->driver_info->flags & FLAG_FRAMING_AX) { | |
1091 | /* hard_mtu is still the default - the device does not support | |
1092 | jumbo eth frames */ | |
1093 | dev->rx_urb_size = 2048; | |
1094 | } | |
2e55cc72 DB |
1095 | return 0; |
1096 | ||
51bf2976 | 1097 | out: |
2e55cc72 DB |
1098 | return ret; |
1099 | } | |
1100 | ||
933a27d3 DH |
1101 | static struct ethtool_ops ax88178_ethtool_ops = { |
1102 | .get_drvinfo = asix_get_drvinfo, | |
1103 | .get_link = asix_get_link, | |
933a27d3 DH |
1104 | .get_msglevel = usbnet_get_msglevel, |
1105 | .set_msglevel = usbnet_set_msglevel, | |
1106 | .get_wol = asix_get_wol, | |
1107 | .set_wol = asix_set_wol, | |
1108 | .get_eeprom_len = asix_get_eeprom_len, | |
1109 | .get_eeprom = asix_get_eeprom, | |
c41286fd AB |
1110 | .get_settings = usbnet_get_settings, |
1111 | .set_settings = usbnet_set_settings, | |
1112 | .nway_reset = usbnet_nway_reset, | |
933a27d3 DH |
1113 | }; |
1114 | ||
1115 | static int marvell_phy_init(struct usbnet *dev) | |
2e55cc72 | 1116 | { |
933a27d3 DH |
1117 | struct asix_data *data = (struct asix_data *)&dev->data; |
1118 | u16 reg; | |
2e55cc72 | 1119 | |
60b86755 | 1120 | netdev_dbg(dev->net, "marvell_phy_init()\n"); |
2e55cc72 | 1121 | |
933a27d3 | 1122 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); |
60b86755 | 1123 | netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); |
2e55cc72 | 1124 | |
933a27d3 DH |
1125 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, |
1126 | MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); | |
2e55cc72 | 1127 | |
933a27d3 DH |
1128 | if (data->ledmode) { |
1129 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, | |
1130 | MII_MARVELL_LED_CTRL); | |
60b86755 | 1131 | netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); |
2e55cc72 | 1132 | |
933a27d3 DH |
1133 | reg &= 0xf8ff; |
1134 | reg |= (1 + 0x0100); | |
1135 | asix_mdio_write(dev->net, dev->mii.phy_id, | |
1136 | MII_MARVELL_LED_CTRL, reg); | |
2e55cc72 | 1137 | |
933a27d3 DH |
1138 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, |
1139 | MII_MARVELL_LED_CTRL); | |
60b86755 | 1140 | netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); |
933a27d3 DH |
1141 | reg &= 0xfc0f; |
1142 | } | |
2e55cc72 | 1143 | |
933a27d3 DH |
1144 | return 0; |
1145 | } | |
1146 | ||
1147 | static int marvell_led_status(struct usbnet *dev, u16 speed) | |
1148 | { | |
1149 | u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); | |
1150 | ||
60b86755 | 1151 | netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); |
933a27d3 DH |
1152 | |
1153 | /* Clear out the center LED bits - 0x03F0 */ | |
1154 | reg &= 0xfc0f; | |
1155 | ||
1156 | switch (speed) { | |
1157 | case SPEED_1000: | |
1158 | reg |= 0x03e0; | |
1159 | break; | |
1160 | case SPEED_100: | |
1161 | reg |= 0x03b0; | |
1162 | break; | |
1163 | default: | |
1164 | reg |= 0x02f0; | |
2e55cc72 DB |
1165 | } |
1166 | ||
60b86755 | 1167 | netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); |
933a27d3 DH |
1168 | asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); |
1169 | ||
1170 | return 0; | |
1171 | } | |
1172 | ||
1173 | static int ax88178_link_reset(struct usbnet *dev) | |
1174 | { | |
1175 | u16 mode; | |
1176 | struct ethtool_cmd ecmd; | |
1177 | struct asix_data *data = (struct asix_data *)&dev->data; | |
1178 | ||
60b86755 | 1179 | netdev_dbg(dev->net, "ax88178_link_reset()\n"); |
933a27d3 DH |
1180 | |
1181 | mii_check_media(&dev->mii, 1, 1); | |
1182 | mii_ethtool_gset(&dev->mii, &ecmd); | |
1183 | mode = AX88178_MEDIUM_DEFAULT; | |
1184 | ||
1185 | if (ecmd.speed == SPEED_1000) | |
a7f75c0c | 1186 | mode |= AX_MEDIUM_GM; |
933a27d3 DH |
1187 | else if (ecmd.speed == SPEED_100) |
1188 | mode |= AX_MEDIUM_PS; | |
1189 | else | |
1190 | mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); | |
1191 | ||
a7f75c0c PK |
1192 | mode |= AX_MEDIUM_ENCK; |
1193 | ||
933a27d3 DH |
1194 | if (ecmd.duplex == DUPLEX_FULL) |
1195 | mode |= AX_MEDIUM_FD; | |
1196 | else | |
1197 | mode &= ~AX_MEDIUM_FD; | |
1198 | ||
60b86755 JP |
1199 | netdev_dbg(dev->net, "ax88178_link_reset() speed: %d duplex: %d setting mode to 0x%04x\n", |
1200 | ecmd.speed, ecmd.duplex, mode); | |
933a27d3 DH |
1201 | |
1202 | asix_write_medium_mode(dev, mode); | |
1203 | ||
1204 | if (data->phymode == PHY_MODE_MARVELL && data->ledmode) | |
1205 | marvell_led_status(dev, ecmd.speed); | |
1206 | ||
1207 | return 0; | |
1208 | } | |
1209 | ||
1210 | static void ax88178_set_mfb(struct usbnet *dev) | |
1211 | { | |
1212 | u16 mfb = AX_RX_CTL_MFB_16384; | |
1213 | u16 rxctl; | |
1214 | u16 medium; | |
1215 | int old_rx_urb_size = dev->rx_urb_size; | |
1216 | ||
1217 | if (dev->hard_mtu < 2048) { | |
1218 | dev->rx_urb_size = 2048; | |
1219 | mfb = AX_RX_CTL_MFB_2048; | |
1220 | } else if (dev->hard_mtu < 4096) { | |
1221 | dev->rx_urb_size = 4096; | |
1222 | mfb = AX_RX_CTL_MFB_4096; | |
1223 | } else if (dev->hard_mtu < 8192) { | |
1224 | dev->rx_urb_size = 8192; | |
1225 | mfb = AX_RX_CTL_MFB_8192; | |
1226 | } else if (dev->hard_mtu < 16384) { | |
1227 | dev->rx_urb_size = 16384; | |
1228 | mfb = AX_RX_CTL_MFB_16384; | |
2e55cc72 | 1229 | } |
933a27d3 DH |
1230 | |
1231 | rxctl = asix_read_rx_ctl(dev); | |
1232 | asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb); | |
1233 | ||
1234 | medium = asix_read_medium_status(dev); | |
1235 | if (dev->net->mtu > 1500) | |
1236 | medium |= AX_MEDIUM_JFE; | |
1237 | else | |
1238 | medium &= ~AX_MEDIUM_JFE; | |
1239 | asix_write_medium_mode(dev, medium); | |
1240 | ||
1241 | if (dev->rx_urb_size > old_rx_urb_size) | |
1242 | usbnet_unlink_rx_urbs(dev); | |
2e55cc72 DB |
1243 | } |
1244 | ||
933a27d3 | 1245 | static int ax88178_change_mtu(struct net_device *net, int new_mtu) |
2e55cc72 | 1246 | { |
933a27d3 DH |
1247 | struct usbnet *dev = netdev_priv(net); |
1248 | int ll_mtu = new_mtu + net->hard_header_len + 4; | |
2e55cc72 | 1249 | |
60b86755 | 1250 | netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); |
2e55cc72 | 1251 | |
933a27d3 DH |
1252 | if (new_mtu <= 0 || ll_mtu > 16384) |
1253 | return -EINVAL; | |
1254 | ||
1255 | if ((ll_mtu % dev->maxpacket) == 0) | |
1256 | return -EDOM; | |
1257 | ||
1258 | net->mtu = new_mtu; | |
1259 | dev->hard_mtu = net->mtu + net->hard_header_len; | |
1260 | ax88178_set_mfb(dev); | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
1703338c SH |
1265 | static const struct net_device_ops ax88178_netdev_ops = { |
1266 | .ndo_open = usbnet_open, | |
1267 | .ndo_stop = usbnet_stop, | |
1268 | .ndo_start_xmit = usbnet_start_xmit, | |
1269 | .ndo_tx_timeout = usbnet_tx_timeout, | |
7f29a3ba | 1270 | .ndo_set_mac_address = asix_set_mac_address, |
1703338c SH |
1271 | .ndo_validate_addr = eth_validate_addr, |
1272 | .ndo_set_multicast_list = asix_set_multicast, | |
1273 | .ndo_do_ioctl = asix_ioctl, | |
1274 | .ndo_change_mtu = ax88178_change_mtu, | |
1275 | }; | |
1276 | ||
933a27d3 DH |
1277 | static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) |
1278 | { | |
1279 | struct asix_data *data = (struct asix_data *)&dev->data; | |
1280 | int ret; | |
51bf2976 AV |
1281 | u8 buf[ETH_ALEN]; |
1282 | __le16 eeprom; | |
1283 | u8 status; | |
933a27d3 DH |
1284 | int gpio0 = 0; |
1285 | u32 phyid; | |
1286 | ||
1287 | usbnet_get_endpoints(dev,intf); | |
1288 | ||
51bf2976 AV |
1289 | asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status); |
1290 | dbg("GPIO Status: 0x%04x", status); | |
933a27d3 DH |
1291 | |
1292 | asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL); | |
1293 | asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom); | |
1294 | asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL); | |
1295 | ||
1296 | dbg("EEPROM index 0x17 is 0x%04x", eeprom); | |
1297 | ||
51bf2976 | 1298 | if (eeprom == cpu_to_le16(0xffff)) { |
933a27d3 DH |
1299 | data->phymode = PHY_MODE_MARVELL; |
1300 | data->ledmode = 0; | |
1301 | gpio0 = 1; | |
2e55cc72 | 1302 | } else { |
51bf2976 AV |
1303 | data->phymode = le16_to_cpu(eeprom) & 7; |
1304 | data->ledmode = le16_to_cpu(eeprom) >> 8; | |
1305 | gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; | |
2e55cc72 | 1306 | } |
933a27d3 | 1307 | dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode); |
2e55cc72 | 1308 | |
933a27d3 | 1309 | asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40); |
51bf2976 | 1310 | if ((le16_to_cpu(eeprom) >> 8) != 1) { |
933a27d3 DH |
1311 | asix_write_gpio(dev, 0x003c, 30); |
1312 | asix_write_gpio(dev, 0x001c, 300); | |
1313 | asix_write_gpio(dev, 0x003c, 30); | |
1314 | } else { | |
1315 | dbg("gpio phymode == 1 path"); | |
1316 | asix_write_gpio(dev, AX_GPIO_GPO1EN, 30); | |
1317 | asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30); | |
1318 | } | |
2e55cc72 | 1319 | |
933a27d3 DH |
1320 | asix_sw_reset(dev, 0); |
1321 | msleep(150); | |
1322 | ||
1323 | asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD); | |
1324 | msleep(150); | |
1325 | ||
1326 | asix_write_rx_ctl(dev, 0); | |
1327 | ||
1328 | /* Get the MAC address */ | |
933a27d3 DH |
1329 | if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, |
1330 | 0, 0, ETH_ALEN, buf)) < 0) { | |
1331 | dbg("Failed to read MAC address: %d", ret); | |
51bf2976 | 1332 | goto out; |
2e55cc72 | 1333 | } |
933a27d3 | 1334 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); |
2e55cc72 | 1335 | |
933a27d3 DH |
1336 | /* Initialize MII structure */ |
1337 | dev->mii.dev = dev->net; | |
1338 | dev->mii.mdio_read = asix_mdio_read; | |
1339 | dev->mii.mdio_write = asix_mdio_write; | |
1340 | dev->mii.phy_id_mask = 0x1f; | |
1341 | dev->mii.reg_num_mask = 0xff; | |
1342 | dev->mii.supports_gmii = 1; | |
933a27d3 | 1343 | dev->mii.phy_id = asix_get_phy_addr(dev); |
1703338c SH |
1344 | |
1345 | dev->net->netdev_ops = &ax88178_netdev_ops; | |
933a27d3 | 1346 | dev->net->ethtool_ops = &ax88178_ethtool_ops; |
2e55cc72 | 1347 | |
933a27d3 DH |
1348 | phyid = asix_get_phyid(dev); |
1349 | dbg("PHYID=0x%08x", phyid); | |
2e55cc72 | 1350 | |
933a27d3 DH |
1351 | if (data->phymode == PHY_MODE_MARVELL) { |
1352 | marvell_phy_init(dev); | |
1353 | msleep(60); | |
1354 | } | |
1355 | ||
1356 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, | |
1357 | BMCR_RESET | BMCR_ANENABLE); | |
1358 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
1359 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
1360 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, | |
1361 | ADVERTISE_1000FULL); | |
1362 | ||
1363 | mii_nway_restart(&dev->mii); | |
1364 | ||
1365 | if ((ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT)) < 0) | |
51bf2976 | 1366 | goto out; |
933a27d3 DH |
1367 | |
1368 | if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0) | |
51bf2976 | 1369 | goto out; |
933a27d3 DH |
1370 | |
1371 | /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ | |
1372 | if (dev->driver_info->flags & FLAG_FRAMING_AX) { | |
1373 | /* hard_mtu is still the default - the device does not support | |
1374 | jumbo eth frames */ | |
1375 | dev->rx_urb_size = 2048; | |
1376 | } | |
2e55cc72 | 1377 | return 0; |
933a27d3 | 1378 | |
51bf2976 | 1379 | out: |
933a27d3 | 1380 | return ret; |
2e55cc72 DB |
1381 | } |
1382 | ||
1383 | static const struct driver_info ax8817x_info = { | |
1384 | .description = "ASIX AX8817x USB 2.0 Ethernet", | |
48b1be6a DH |
1385 | .bind = ax88172_bind, |
1386 | .status = asix_status, | |
2e55cc72 DB |
1387 | .link_reset = ax88172_link_reset, |
1388 | .reset = ax88172_link_reset, | |
37e8273c | 1389 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
1390 | .data = 0x00130103, |
1391 | }; | |
1392 | ||
1393 | static const struct driver_info dlink_dub_e100_info = { | |
1394 | .description = "DLink DUB-E100 USB Ethernet", | |
48b1be6a DH |
1395 | .bind = ax88172_bind, |
1396 | .status = asix_status, | |
2e55cc72 DB |
1397 | .link_reset = ax88172_link_reset, |
1398 | .reset = ax88172_link_reset, | |
37e8273c | 1399 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
1400 | .data = 0x009f9d9f, |
1401 | }; | |
1402 | ||
1403 | static const struct driver_info netgear_fa120_info = { | |
1404 | .description = "Netgear FA-120 USB Ethernet", | |
48b1be6a DH |
1405 | .bind = ax88172_bind, |
1406 | .status = asix_status, | |
2e55cc72 DB |
1407 | .link_reset = ax88172_link_reset, |
1408 | .reset = ax88172_link_reset, | |
37e8273c | 1409 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
1410 | .data = 0x00130103, |
1411 | }; | |
1412 | ||
1413 | static const struct driver_info hawking_uf200_info = { | |
1414 | .description = "Hawking UF200 USB Ethernet", | |
48b1be6a DH |
1415 | .bind = ax88172_bind, |
1416 | .status = asix_status, | |
2e55cc72 DB |
1417 | .link_reset = ax88172_link_reset, |
1418 | .reset = ax88172_link_reset, | |
37e8273c | 1419 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
1420 | .data = 0x001f1d1f, |
1421 | }; | |
1422 | ||
1423 | static const struct driver_info ax88772_info = { | |
1424 | .description = "ASIX AX88772 USB 2.0 Ethernet", | |
1425 | .bind = ax88772_bind, | |
48b1be6a | 1426 | .status = asix_status, |
2e55cc72 DB |
1427 | .link_reset = ax88772_link_reset, |
1428 | .reset = ax88772_link_reset, | |
37e8273c | 1429 | .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR, |
933a27d3 DH |
1430 | .rx_fixup = asix_rx_fixup, |
1431 | .tx_fixup = asix_tx_fixup, | |
1432 | }; | |
1433 | ||
1434 | static const struct driver_info ax88178_info = { | |
1435 | .description = "ASIX AX88178 USB 2.0 Ethernet", | |
1436 | .bind = ax88178_bind, | |
1437 | .status = asix_status, | |
1438 | .link_reset = ax88178_link_reset, | |
1439 | .reset = ax88178_link_reset, | |
37e8273c | 1440 | .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR, |
933a27d3 DH |
1441 | .rx_fixup = asix_rx_fixup, |
1442 | .tx_fixup = asix_tx_fixup, | |
2e55cc72 DB |
1443 | }; |
1444 | ||
1445 | static const struct usb_device_id products [] = { | |
1446 | { | |
1447 | // Linksys USB200M | |
1448 | USB_DEVICE (0x077b, 0x2226), | |
1449 | .driver_info = (unsigned long) &ax8817x_info, | |
1450 | }, { | |
1451 | // Netgear FA120 | |
1452 | USB_DEVICE (0x0846, 0x1040), | |
1453 | .driver_info = (unsigned long) &netgear_fa120_info, | |
1454 | }, { | |
1455 | // DLink DUB-E100 | |
1456 | USB_DEVICE (0x2001, 0x1a00), | |
1457 | .driver_info = (unsigned long) &dlink_dub_e100_info, | |
1458 | }, { | |
1459 | // Intellinet, ST Lab USB Ethernet | |
1460 | USB_DEVICE (0x0b95, 0x1720), | |
1461 | .driver_info = (unsigned long) &ax8817x_info, | |
1462 | }, { | |
1463 | // Hawking UF200, TrendNet TU2-ET100 | |
1464 | USB_DEVICE (0x07b8, 0x420a), | |
1465 | .driver_info = (unsigned long) &hawking_uf200_info, | |
1466 | }, { | |
39c4b38c DH |
1467 | // Billionton Systems, USB2AR |
1468 | USB_DEVICE (0x08dd, 0x90ff), | |
1469 | .driver_info = (unsigned long) &ax8817x_info, | |
2e55cc72 DB |
1470 | }, { |
1471 | // ATEN UC210T | |
1472 | USB_DEVICE (0x0557, 0x2009), | |
1473 | .driver_info = (unsigned long) &ax8817x_info, | |
1474 | }, { | |
1475 | // Buffalo LUA-U2-KTX | |
1476 | USB_DEVICE (0x0411, 0x003d), | |
1477 | .driver_info = (unsigned long) &ax8817x_info, | |
ac7b77f1 MD |
1478 | }, { |
1479 | // Buffalo LUA-U2-GT 10/100/1000 | |
1480 | USB_DEVICE (0x0411, 0x006e), | |
1481 | .driver_info = (unsigned long) &ax88178_info, | |
2e55cc72 DB |
1482 | }, { |
1483 | // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" | |
1484 | USB_DEVICE (0x6189, 0x182d), | |
1485 | .driver_info = (unsigned long) &ax8817x_info, | |
1486 | }, { | |
1487 | // corega FEther USB2-TX | |
1488 | USB_DEVICE (0x07aa, 0x0017), | |
1489 | .driver_info = (unsigned long) &ax8817x_info, | |
1490 | }, { | |
1491 | // Surecom EP-1427X-2 | |
1492 | USB_DEVICE (0x1189, 0x0893), | |
1493 | .driver_info = (unsigned long) &ax8817x_info, | |
1494 | }, { | |
1495 | // goodway corp usb gwusb2e | |
1496 | USB_DEVICE (0x1631, 0x6200), | |
1497 | .driver_info = (unsigned long) &ax8817x_info, | |
39c4b38c DH |
1498 | }, { |
1499 | // JVC MP-PRX1 Port Replicator | |
1500 | USB_DEVICE (0x04f1, 0x3008), | |
1501 | .driver_info = (unsigned long) &ax8817x_info, | |
2e55cc72 DB |
1502 | }, { |
1503 | // ASIX AX88772 10/100 | |
39c4b38c DH |
1504 | USB_DEVICE (0x0b95, 0x7720), |
1505 | .driver_info = (unsigned long) &ax88772_info, | |
7327413c EW |
1506 | }, { |
1507 | // ASIX AX88178 10/100/1000 | |
1508 | USB_DEVICE (0x0b95, 0x1780), | |
933a27d3 | 1509 | .driver_info = (unsigned long) &ax88178_info, |
5e0f76c6 DH |
1510 | }, { |
1511 | // Linksys USB200M Rev 2 | |
1512 | USB_DEVICE (0x13b1, 0x0018), | |
1513 | .driver_info = (unsigned long) &ax88772_info, | |
5732ce84 DH |
1514 | }, { |
1515 | // 0Q0 cable ethernet | |
1516 | USB_DEVICE (0x1557, 0x7720), | |
1517 | .driver_info = (unsigned long) &ax88772_info, | |
933a27d3 DH |
1518 | }, { |
1519 | // DLink DUB-E100 H/W Ver B1 | |
1520 | USB_DEVICE (0x07d1, 0x3c05), | |
1521 | .driver_info = (unsigned long) &ax88772_info, | |
b923e7fc DH |
1522 | }, { |
1523 | // DLink DUB-E100 H/W Ver B1 Alternate | |
1524 | USB_DEVICE (0x2001, 0x3c05), | |
1525 | .driver_info = (unsigned long) &ax88772_info, | |
933a27d3 DH |
1526 | }, { |
1527 | // Linksys USB1000 | |
1528 | USB_DEVICE (0x1737, 0x0039), | |
1529 | .driver_info = (unsigned long) &ax88178_info, | |
b29cf31d YH |
1530 | }, { |
1531 | // IO-DATA ETG-US2 | |
1532 | USB_DEVICE (0x04bb, 0x0930), | |
1533 | .driver_info = (unsigned long) &ax88178_info, | |
2ed22bc2 DH |
1534 | }, { |
1535 | // Belkin F5D5055 | |
1536 | USB_DEVICE(0x050d, 0x5055), | |
1537 | .driver_info = (unsigned long) &ax88178_info, | |
3d60efb5 AN |
1538 | }, { |
1539 | // Apple USB Ethernet Adapter | |
1540 | USB_DEVICE(0x05ac, 0x1402), | |
1541 | .driver_info = (unsigned long) &ax88772_info, | |
ccf95402 JC |
1542 | }, { |
1543 | // Cables-to-Go USB Ethernet Adapter | |
1544 | USB_DEVICE(0x0b95, 0x772a), | |
1545 | .driver_info = (unsigned long) &ax88772_info, | |
fef7cc08 GKH |
1546 | }, { |
1547 | // ABOCOM for pci | |
1548 | USB_DEVICE(0x14ea, 0xab11), | |
1549 | .driver_info = (unsigned long) &ax88178_info, | |
1550 | }, { | |
1551 | // ASIX 88772a | |
1552 | USB_DEVICE(0x0db0, 0xa877), | |
1553 | .driver_info = (unsigned long) &ax88772_info, | |
2e55cc72 DB |
1554 | }, |
1555 | { }, // END | |
1556 | }; | |
1557 | MODULE_DEVICE_TABLE(usb, products); | |
1558 | ||
1559 | static struct usb_driver asix_driver = { | |
2e55cc72 DB |
1560 | .name = "asix", |
1561 | .id_table = products, | |
1562 | .probe = usbnet_probe, | |
1563 | .suspend = usbnet_suspend, | |
1564 | .resume = usbnet_resume, | |
1565 | .disconnect = usbnet_disconnect, | |
a11a6544 | 1566 | .supports_autosuspend = 1, |
2e55cc72 DB |
1567 | }; |
1568 | ||
1569 | static int __init asix_init(void) | |
1570 | { | |
1571 | return usb_register(&asix_driver); | |
1572 | } | |
1573 | module_init(asix_init); | |
1574 | ||
1575 | static void __exit asix_exit(void) | |
1576 | { | |
1577 | usb_deregister(&asix_driver); | |
1578 | } | |
1579 | module_exit(asix_exit); | |
1580 | ||
1581 | MODULE_AUTHOR("David Hollis"); | |
1582 | MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); | |
1583 | MODULE_LICENSE("GPL"); | |
1584 |