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fsl_pq_mido: Set the first UCC as the mii management interface master
[linux-2.6-block.git] / drivers / net / ucc_geth.c
CommitLineData
ce973b14 1/*
4e19b5c1 2 * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
ce973b14
LY		 3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
18a8e864 5 * Li Yang <leoli@freescale.com>
ce973b14
LY		 6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
ce973b14
LY		 10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/slab.h>
19#include <linux/stddef.h>
20#include <linux/interrupt.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/spinlock.h>
25#include <linux/mm.h>
ce973b14 26#include <linux/dma-mapping.h>
ce973b14 27#include <linux/mii.h>
728de4c9 28#include <linux/phy.h>
df19b6b0 29#include <linux/workqueue.h>
0b9da337 30#include <linux/of_mdio.h>
55b6c8e9 31#include <linux/of_platform.h>
ce973b14
LY		 32
33#include <asm/uaccess.h>
34#include <asm/irq.h>
35#include <asm/io.h>
36#include <asm/immap_qe.h>
37#include <asm/qe.h>
38#include <asm/ucc.h>
39#include <asm/ucc_fast.h>
40
41#include "ucc_geth.h"
1577ecef 42#include "fsl_pq_mdio.h"
ce973b14
LY		 43
44#undef DEBUG
45
ce973b14
LY		 46#define ugeth_printk(level, format, arg...) \
47 printk(level format "\n", ## arg)
48
49#define ugeth_dbg(format, arg...) \
50 ugeth_printk(KERN_DEBUG , format , ## arg)
51#define ugeth_err(format, arg...) \
52 ugeth_printk(KERN_ERR , format , ## arg)
53#define ugeth_info(format, arg...) \
54 ugeth_printk(KERN_INFO , format , ## arg)
55#define ugeth_warn(format, arg...) \
56 ugeth_printk(KERN_WARNING , format , ## arg)
57
58#ifdef UGETH_VERBOSE_DEBUG
59#define ugeth_vdbg ugeth_dbg
60#else
61#define ugeth_vdbg(fmt, args...) do { } while (0)
62#endif /* UGETH_VERBOSE_DEBUG */
890de95e 63#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
ce973b14 64
88a15f2e 65
ce973b14
LY		 66static DEFINE_SPINLOCK(ugeth_lock);
67
890de95e
LY		 68static struct {
69 u32 msg_enable;
70} debug = { -1 };
71
72module_param_named(debug, debug.msg_enable, int, 0);
73MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
74
18a8e864 75static struct ucc_geth_info ugeth_primary_info = {
ce973b14
LY		 76 .uf_info = {
77 .bd_mem_part = MEM_PART_SYSTEM,
78 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
79 .max_rx_buf_length = 1536,
728de4c9 80 /* adjusted at startup if max-speed 1000 */
ce973b14
LY		 81 .urfs = UCC_GETH_URFS_INIT,
82 .urfet = UCC_GETH_URFET_INIT,
83 .urfset = UCC_GETH_URFSET_INIT,
84 .utfs = UCC_GETH_UTFS_INIT,
85 .utfet = UCC_GETH_UTFET_INIT,
86 .utftt = UCC_GETH_UTFTT_INIT,
ce973b14
LY		 87 .ufpt = 256,
88 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
89 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
90 .tenc = UCC_FAST_TX_ENCODING_NRZ,
91 .renc = UCC_FAST_RX_ENCODING_NRZ,
92 .tcrc = UCC_FAST_16_BIT_CRC,
93 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
94 },
95 .numQueuesTx = 1,
96 .numQueuesRx = 1,
97 .extendedFilteringChainPointer = ((uint32_t) NULL),
98 .typeorlen = 3072 /*1536 */ ,
99 .nonBackToBackIfgPart1 = 0x40,
100 .nonBackToBackIfgPart2 = 0x60,
101 .miminumInterFrameGapEnforcement = 0x50,
102 .backToBackInterFrameGap = 0x60,
103 .mblinterval = 128,
104 .nortsrbytetime = 5,
105 .fracsiz = 1,
106 .strictpriorityq = 0xff,
107 .altBebTruncation = 0xa,
108 .excessDefer = 1,
109 .maxRetransmission = 0xf,
110 .collisionWindow = 0x37,
111 .receiveFlowControl = 1,
ac421852 112 .transmitFlowControl = 1,
ce973b14
LY		 113 .maxGroupAddrInHash = 4,
114 .maxIndAddrInHash = 4,
115 .prel = 7,
116 .maxFrameLength = 1518,
117 .minFrameLength = 64,
118 .maxD1Length = 1520,
119 .maxD2Length = 1520,
120 .vlantype = 0x8100,
121 .ecamptr = ((uint32_t) NULL),
122 .eventRegMask = UCCE_OTHER,
123 .pausePeriod = 0xf000,
124 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
125 .bdRingLenTx = {
126 TX_BD_RING_LEN,
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN},
134
135 .bdRingLenRx = {
136 RX_BD_RING_LEN,
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN},
144
145 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
146 .largestexternallookupkeysize =
147 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
ac421852
LY		 148 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
ce973b14
LY		 151 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
152 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
153 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
154 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
155 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
ffea31ed
JT		 156 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
157 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
ce973b14
LY		 158 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
159 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160};
161
18a8e864 162static struct ucc_geth_info ugeth_info[8];
ce973b14
LY		 163
164#ifdef DEBUG
165static void mem_disp(u8 *addr, int size)
166{
167 u8 *i;
168 int size16Aling = (size >> 4) << 4;
169 int size4Aling = (size >> 2) << 2;
170 int notAlign = 0;
171 if (size % 16)
172 notAlign = 1;
173
174 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
175 printk("0x%08x: %08x %08x %08x %08x\r\n",
176 (u32) i,
177 *((u32 *) (i)),
178 *((u32 *) (i + 4)),
179 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
180 if (notAlign == 1)
181 printk("0x%08x: ", (u32) i);
182 for (; (u32) i < (u32) addr + size4Aling; i += 4)
183 printk("%08x ", *((u32 *) (i)));
184 for (; (u32) i < (u32) addr + size; i++)
185 printk("%02x", *((u8 *) (i)));
186 if (notAlign == 1)
187 printk("\r\n");
188}
189#endif /* DEBUG */
190
ce973b14
LY		 191static struct list_head *dequeue(struct list_head *lh)
192{
193 unsigned long flags;
194
1083cfe1 195 spin_lock_irqsave(&ugeth_lock, flags);
ce973b14
LY		 196 if (!list_empty(lh)) {
197 struct list_head *node = lh->next;
198 list_del(node);
1083cfe1 199 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 200 return node;
201 } else {
1083cfe1 202 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 203 return NULL;
204 }
205}
206
6fee40e9
AF		 207static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
208 u8 __iomem *bd)
ce973b14
LY		 209{
210 struct sk_buff *skb = NULL;
211
212 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
213 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
214
215 if (skb == NULL)
216 return NULL;
217
218 /* We need the data buffer to be aligned properly. We will reserve
219 * as many bytes as needed to align the data properly
220 */
221 skb_reserve(skb,
222 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
223 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
224 1)));
225
da1aa63e 226 skb->dev = ugeth->ndev;
ce973b14 227
6fee40e9 228 out_be32(&((struct qe_bd __iomem *)bd)->buf,
da1aa63e 229 dma_map_single(ugeth->dev,
ce973b14
LY		 230 skb->data,
231 ugeth->ug_info->uf_info.max_rx_buf_length +
232 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
233 DMA_FROM_DEVICE));
234
6fee40e9
AF		 235 out_be32((u32 __iomem *)bd,
236 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
ce973b14
LY		 237
238 return skb;
239}
240
18a8e864 241static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
ce973b14 242{
6fee40e9 243 u8 __iomem *bd;
ce973b14
LY		 244 u32 bd_status;
245 struct sk_buff *skb;
246 int i;
247
248 bd = ugeth->p_rx_bd_ring[rxQ];
249 i = 0;
250
251 do {
6fee40e9 252 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 253 skb = get_new_skb(ugeth, bd);
254
255 if (!skb) /* If can not allocate data buffer,
256 abort. Cleanup will be elsewhere */
257 return -ENOMEM;
258
259 ugeth->rx_skbuff[rxQ][i] = skb;
260
261 /* advance the BD pointer */
18a8e864 262 bd += sizeof(struct qe_bd);
ce973b14
LY		 263 i++;
264 } while (!(bd_status & R_W));
265
266 return 0;
267}
268
18a8e864 269static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 270 u32 *p_start,
ce973b14
LY		 271 u8 num_entries,
272 u32 thread_size,
273 u32 thread_alignment,
18a8e864 274 enum qe_risc_allocation risc,
ce973b14
LY		 275 int skip_page_for_first_entry)
276{
277 u32 init_enet_offset;
278 u8 i;
279 int snum;
280
281 for (i = 0; i < num_entries; i++) {
282 if ((snum = qe_get_snum()) < 0) {
890de95e
LY		 283 if (netif_msg_ifup(ugeth))
284 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
ce973b14
LY		 285 return snum;
286 }
287 if ((i == 0) && skip_page_for_first_entry)
288 /* First entry of Rx does not have page */
289 init_enet_offset = 0;
290 else {
291 init_enet_offset =
292 qe_muram_alloc(thread_size, thread_alignment);
4c35630c 293 if (IS_ERR_VALUE(init_enet_offset)) {
890de95e
LY		 294 if (netif_msg_ifup(ugeth))
295 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
ce973b14
LY		 296 qe_put_snum((u8) snum);
297 return -ENOMEM;
298 }
299 }
300 *(p_start++) =
301 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
302 | risc;
303 }
304
305 return 0;
306}
307
18a8e864 308static int return_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 309 u32 *p_start,
ce973b14 310 u8 num_entries,
18a8e864 311 enum qe_risc_allocation risc,
ce973b14
LY		 312 int skip_page_for_first_entry)
313{
314 u32 init_enet_offset;
315 u8 i;
316 int snum;
317
318 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 319 u32 val = *p_start;
320
ce973b14
LY		 321 /* Check that this entry was actually valid --
322 needed in case failed in allocations */
6fee40e9 323 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 324 snum =
6fee40e9 325 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 326 ENET_INIT_PARAM_SNUM_SHIFT;
327 qe_put_snum((u8) snum);
328 if (!((i == 0) && skip_page_for_first_entry)) {
329 /* First entry of Rx does not have page */
330 init_enet_offset =
6fee40e9 331 (val & ENET_INIT_PARAM_PTR_MASK);
ce973b14
LY		 332 qe_muram_free(init_enet_offset);
333 }
6fee40e9 334 *p_start++ = 0;
ce973b14
LY		 335 }
336 }
337
338 return 0;
339}
340
341#ifdef DEBUG
18a8e864 342static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 343 u32 __iomem *p_start,
ce973b14
LY		 344 u8 num_entries,
345 u32 thread_size,
18a8e864 346 enum qe_risc_allocation risc,
ce973b14
LY		 347 int skip_page_for_first_entry)
348{
349 u32 init_enet_offset;
350 u8 i;
351 int snum;
352
353 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 354 u32 val = in_be32(p_start);
355
ce973b14
LY		 356 /* Check that this entry was actually valid --
357 needed in case failed in allocations */
6fee40e9 358 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 359 snum =
6fee40e9 360 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 361 ENET_INIT_PARAM_SNUM_SHIFT;
362 qe_put_snum((u8) snum);
363 if (!((i == 0) && skip_page_for_first_entry)) {
364 /* First entry of Rx does not have page */
365 init_enet_offset =
366 (in_be32(p_start) &
367 ENET_INIT_PARAM_PTR_MASK);
368 ugeth_info("Init enet entry %d:", i);
369 ugeth_info("Base address: 0x%08x",
370 (u32)
371 qe_muram_addr(init_enet_offset));
372 mem_disp(qe_muram_addr(init_enet_offset),
373 thread_size);
374 }
375 p_start++;
376 }
377 }
378
379 return 0;
380}
381#endif
382
18a8e864 383static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
ce973b14
LY		 384{
385 kfree(enet_addr_cont);
386}
387
df19b6b0 388static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
18a8e864
LY		 389{
390 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
391 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
392 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
393}
394
18a8e864 395static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
ce973b14 396{
6fee40e9 397 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 398
399 if (!(paddr_num < NUM_OF_PADDRS)) {
b39d66a8 400 ugeth_warn("%s: Illagel paddr_num.", __func__);
ce973b14
LY		 401 return -EINVAL;
402 }
403
404 p_82xx_addr_filt =
6fee40e9 405 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 406 addressfiltering;
407
408 /* Writing address ff.ff.ff.ff.ff.ff disables address
409 recognition for this register */
410 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
411 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
412 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
413
414 return 0;
415}
416
18a8e864
LY		 417static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
418 u8 *p_enet_addr)
ce973b14 419{
6fee40e9 420 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 421 u32 cecr_subblock;
422
423 p_82xx_addr_filt =
6fee40e9 424 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 425 addressfiltering;
426
427 cecr_subblock =
428 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
429
430 /* Ethernet frames are defined in Little Endian mode,
431 therefor to insert */
432 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
18a8e864
LY		 433
434 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
ce973b14
LY		 435
436 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
18a8e864 437 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 438}
439
440#ifdef CONFIG_UGETH_MAGIC_PACKET
18a8e864 441static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
ce973b14 442{
18a8e864 443 struct ucc_fast_private *uccf;
6fee40e9 444 struct ucc_geth __iomem *ug_regs;
ce973b14
LY		 445
446 uccf = ugeth->uccf;
447 ug_regs = ugeth->ug_regs;
448
449 /* Enable interrupts for magic packet detection */
3bc53427 450 setbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
ce973b14
LY		 451
452 /* Enable magic packet detection */
3bc53427 453 setbits32(&ug_regs->maccfg2, MACCFG2_MPE);
ce973b14
LY		 454}
455
18a8e864 456static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
ce973b14 457{
18a8e864 458 struct ucc_fast_private *uccf;
6fee40e9 459 struct ucc_geth __iomem *ug_regs;
ce973b14
LY		 460
461 uccf = ugeth->uccf;
462 ug_regs = ugeth->ug_regs;
463
464 /* Disable interrupts for magic packet detection */
3bc53427 465 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
ce973b14
LY		 466
467 /* Disable magic packet detection */
3bc53427 468 clrbits32(&ug_regs->maccfg2, MACCFG2_MPE);
ce973b14
LY		 469}
470#endif /* MAGIC_PACKET */
471
18a8e864 472static inline int compare_addr(u8 **addr1, u8 **addr2)
ce973b14
LY		 473{
474 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
475}
476
477#ifdef DEBUG
18a8e864
LY		 478static void get_statistics(struct ucc_geth_private *ugeth,
479 struct ucc_geth_tx_firmware_statistics *
ce973b14 480 tx_firmware_statistics,
18a8e864 481 struct ucc_geth_rx_firmware_statistics *
ce973b14 482 rx_firmware_statistics,
18a8e864 483 struct ucc_geth_hardware_statistics *hardware_statistics)
ce973b14 484{
6fee40e9
AF		 485 struct ucc_fast __iomem *uf_regs;
486 struct ucc_geth __iomem *ug_regs;
18a8e864
LY		 487 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
488 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
ce973b14
LY		 489
490 ug_regs = ugeth->ug_regs;
6fee40e9 491 uf_regs = (struct ucc_fast __iomem *) ug_regs;
ce973b14
LY		 492 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
493 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
494
495 /* Tx firmware only if user handed pointer and driver actually
496 gathers Tx firmware statistics */
497 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
498 tx_firmware_statistics->sicoltx =
499 in_be32(&p_tx_fw_statistics_pram->sicoltx);
500 tx_firmware_statistics->mulcoltx =
501 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
502 tx_firmware_statistics->latecoltxfr =
503 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
504 tx_firmware_statistics->frabortduecol =
505 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
506 tx_firmware_statistics->frlostinmactxer =
507 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
508 tx_firmware_statistics->carriersenseertx =
509 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
510 tx_firmware_statistics->frtxok =
511 in_be32(&p_tx_fw_statistics_pram->frtxok);
512 tx_firmware_statistics->txfrexcessivedefer =
513 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
514 tx_firmware_statistics->txpkts256 =
515 in_be32(&p_tx_fw_statistics_pram->txpkts256);
516 tx_firmware_statistics->txpkts512 =
517 in_be32(&p_tx_fw_statistics_pram->txpkts512);
518 tx_firmware_statistics->txpkts1024 =
519 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
520 tx_firmware_statistics->txpktsjumbo =
521 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
522 }
523
524 /* Rx firmware only if user handed pointer and driver actually
525 * gathers Rx firmware statistics */
526 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
527 int i;
528 rx_firmware_statistics->frrxfcser =
529 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
530 rx_firmware_statistics->fraligner =
531 in_be32(&p_rx_fw_statistics_pram->fraligner);
532 rx_firmware_statistics->inrangelenrxer =
533 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
534 rx_firmware_statistics->outrangelenrxer =
535 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
536 rx_firmware_statistics->frtoolong =
537 in_be32(&p_rx_fw_statistics_pram->frtoolong);
538 rx_firmware_statistics->runt =
539 in_be32(&p_rx_fw_statistics_pram->runt);
540 rx_firmware_statistics->verylongevent =
541 in_be32(&p_rx_fw_statistics_pram->verylongevent);
542 rx_firmware_statistics->symbolerror =
543 in_be32(&p_rx_fw_statistics_pram->symbolerror);
544 rx_firmware_statistics->dropbsy =
545 in_be32(&p_rx_fw_statistics_pram->dropbsy);
546 for (i = 0; i < 0x8; i++)
547 rx_firmware_statistics->res0[i] =
548 p_rx_fw_statistics_pram->res0[i];
549 rx_firmware_statistics->mismatchdrop =
550 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
551 rx_firmware_statistics->underpkts =
552 in_be32(&p_rx_fw_statistics_pram->underpkts);
553 rx_firmware_statistics->pkts256 =
554 in_be32(&p_rx_fw_statistics_pram->pkts256);
555 rx_firmware_statistics->pkts512 =
556 in_be32(&p_rx_fw_statistics_pram->pkts512);
557 rx_firmware_statistics->pkts1024 =
558 in_be32(&p_rx_fw_statistics_pram->pkts1024);
559 rx_firmware_statistics->pktsjumbo =
560 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
561 rx_firmware_statistics->frlossinmacer =
562 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
563 rx_firmware_statistics->pausefr =
564 in_be32(&p_rx_fw_statistics_pram->pausefr);
565 for (i = 0; i < 0x4; i++)
566 rx_firmware_statistics->res1[i] =
567 p_rx_fw_statistics_pram->res1[i];
568 rx_firmware_statistics->removevlan =
569 in_be32(&p_rx_fw_statistics_pram->removevlan);
570 rx_firmware_statistics->replacevlan =
571 in_be32(&p_rx_fw_statistics_pram->replacevlan);
572 rx_firmware_statistics->insertvlan =
573 in_be32(&p_rx_fw_statistics_pram->insertvlan);
574 }
575
576 /* Hardware only if user handed pointer and driver actually
577 gathers hardware statistics */
3bc53427
TT		 578 if (hardware_statistics &&
579 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
ce973b14
LY		 580 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
581 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
582 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
583 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
584 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
585 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
586 hardware_statistics->txok = in_be32(&ug_regs->txok);
587 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
588 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
589 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
590 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
591 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
592 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
593 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
594 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
595 }
596}
597
18a8e864 598static void dump_bds(struct ucc_geth_private *ugeth)
ce973b14
LY		 599{
600 int i;
601 int length;
602
603 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
604 if (ugeth->p_tx_bd_ring[i]) {
605 length =
606 (ugeth->ug_info->bdRingLenTx[i] *
18a8e864 607 sizeof(struct qe_bd));
ce973b14
LY		 608 ugeth_info("TX BDs[%d]", i);
609 mem_disp(ugeth->p_tx_bd_ring[i], length);
610 }
611 }
612 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
613 if (ugeth->p_rx_bd_ring[i]) {
614 length =
615 (ugeth->ug_info->bdRingLenRx[i] *
18a8e864 616 sizeof(struct qe_bd));
ce973b14
LY		 617 ugeth_info("RX BDs[%d]", i);
618 mem_disp(ugeth->p_rx_bd_ring[i], length);
619 }
620 }
621}
622
18a8e864 623static void dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 624{
625 int i;
626
627 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
628 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
629
630 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
631 (u32) & ugeth->ug_regs->maccfg1,
632 in_be32(&ugeth->ug_regs->maccfg1));
633 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
634 (u32) & ugeth->ug_regs->maccfg2,
635 in_be32(&ugeth->ug_regs->maccfg2));
636 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
637 (u32) & ugeth->ug_regs->ipgifg,
638 in_be32(&ugeth->ug_regs->ipgifg));
639 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
640 (u32) & ugeth->ug_regs->hafdup,
641 in_be32(&ugeth->ug_regs->hafdup));
ce973b14
LY		 642 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
643 (u32) & ugeth->ug_regs->ifctl,
644 in_be32(&ugeth->ug_regs->ifctl));
645 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
646 (u32) & ugeth->ug_regs->ifstat,
647 in_be32(&ugeth->ug_regs->ifstat));
648 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
649 (u32) & ugeth->ug_regs->macstnaddr1,
650 in_be32(&ugeth->ug_regs->macstnaddr1));
651 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
652 (u32) & ugeth->ug_regs->macstnaddr2,
653 in_be32(&ugeth->ug_regs->macstnaddr2));
654 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
655 (u32) & ugeth->ug_regs->uempr,
656 in_be32(&ugeth->ug_regs->uempr));
657 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
658 (u32) & ugeth->ug_regs->utbipar,
659 in_be32(&ugeth->ug_regs->utbipar));
660 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
661 (u32) & ugeth->ug_regs->uescr,
662 in_be16(&ugeth->ug_regs->uescr));
663 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
664 (u32) & ugeth->ug_regs->tx64,
665 in_be32(&ugeth->ug_regs->tx64));
666 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
667 (u32) & ugeth->ug_regs->tx127,
668 in_be32(&ugeth->ug_regs->tx127));
669 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
670 (u32) & ugeth->ug_regs->tx255,
671 in_be32(&ugeth->ug_regs->tx255));
672 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
673 (u32) & ugeth->ug_regs->rx64,
674 in_be32(&ugeth->ug_regs->rx64));
675 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
676 (u32) & ugeth->ug_regs->rx127,
677 in_be32(&ugeth->ug_regs->rx127));
678 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
679 (u32) & ugeth->ug_regs->rx255,
680 in_be32(&ugeth->ug_regs->rx255));
681 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
682 (u32) & ugeth->ug_regs->txok,
683 in_be32(&ugeth->ug_regs->txok));
684 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
685 (u32) & ugeth->ug_regs->txcf,
686 in_be16(&ugeth->ug_regs->txcf));
687 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
688 (u32) & ugeth->ug_regs->tmca,
689 in_be32(&ugeth->ug_regs->tmca));
690 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
691 (u32) & ugeth->ug_regs->tbca,
692 in_be32(&ugeth->ug_regs->tbca));
693 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
694 (u32) & ugeth->ug_regs->rxfok,
695 in_be32(&ugeth->ug_regs->rxfok));
696 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
697 (u32) & ugeth->ug_regs->rxbok,
698 in_be32(&ugeth->ug_regs->rxbok));
699 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
700 (u32) & ugeth->ug_regs->rbyt,
701 in_be32(&ugeth->ug_regs->rbyt));
702 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
703 (u32) & ugeth->ug_regs->rmca,
704 in_be32(&ugeth->ug_regs->rmca));
705 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
706 (u32) & ugeth->ug_regs->rbca,
707 in_be32(&ugeth->ug_regs->rbca));
708 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
709 (u32) & ugeth->ug_regs->scar,
710 in_be32(&ugeth->ug_regs->scar));
711 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
712 (u32) & ugeth->ug_regs->scam,
713 in_be32(&ugeth->ug_regs->scam));
714
715 if (ugeth->p_thread_data_tx) {
716 int numThreadsTxNumerical;
717 switch (ugeth->ug_info->numThreadsTx) {
718 case UCC_GETH_NUM_OF_THREADS_1:
719 numThreadsTxNumerical = 1;
720 break;
721 case UCC_GETH_NUM_OF_THREADS_2:
722 numThreadsTxNumerical = 2;
723 break;
724 case UCC_GETH_NUM_OF_THREADS_4:
725 numThreadsTxNumerical = 4;
726 break;
727 case UCC_GETH_NUM_OF_THREADS_6:
728 numThreadsTxNumerical = 6;
729 break;
730 case UCC_GETH_NUM_OF_THREADS_8:
731 numThreadsTxNumerical = 8;
732 break;
733 default:
734 numThreadsTxNumerical = 0;
735 break;
736 }
737
738 ugeth_info("Thread data TXs:");
739 ugeth_info("Base address: 0x%08x",
740 (u32) ugeth->p_thread_data_tx);
741 for (i = 0; i < numThreadsTxNumerical; i++) {
742 ugeth_info("Thread data TX[%d]:", i);
743 ugeth_info("Base address: 0x%08x",
744 (u32) & ugeth->p_thread_data_tx[i]);
745 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
18a8e864 746 sizeof(struct ucc_geth_thread_data_tx));
ce973b14
LY		 747 }
748 }
749 if (ugeth->p_thread_data_rx) {
750 int numThreadsRxNumerical;
751 switch (ugeth->ug_info->numThreadsRx) {
752 case UCC_GETH_NUM_OF_THREADS_1:
753 numThreadsRxNumerical = 1;
754 break;
755 case UCC_GETH_NUM_OF_THREADS_2:
756 numThreadsRxNumerical = 2;
757 break;
758 case UCC_GETH_NUM_OF_THREADS_4:
759 numThreadsRxNumerical = 4;
760 break;
761 case UCC_GETH_NUM_OF_THREADS_6:
762 numThreadsRxNumerical = 6;
763 break;
764 case UCC_GETH_NUM_OF_THREADS_8:
765 numThreadsRxNumerical = 8;
766 break;
767 default:
768 numThreadsRxNumerical = 0;
769 break;
770 }
771
772 ugeth_info("Thread data RX:");
773 ugeth_info("Base address: 0x%08x",
774 (u32) ugeth->p_thread_data_rx);
775 for (i = 0; i < numThreadsRxNumerical; i++) {
776 ugeth_info("Thread data RX[%d]:", i);
777 ugeth_info("Base address: 0x%08x",
778 (u32) & ugeth->p_thread_data_rx[i]);
779 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
18a8e864 780 sizeof(struct ucc_geth_thread_data_rx));
ce973b14
LY		 781 }
782 }
783 if (ugeth->p_exf_glbl_param) {
784 ugeth_info("EXF global param:");
785 ugeth_info("Base address: 0x%08x",
786 (u32) ugeth->p_exf_glbl_param);
787 mem_disp((u8 *) ugeth->p_exf_glbl_param,
788 sizeof(*ugeth->p_exf_glbl_param));
789 }
790 if (ugeth->p_tx_glbl_pram) {
791 ugeth_info("TX global param:");
792 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
793 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
794 (u32) & ugeth->p_tx_glbl_pram->temoder,
795 in_be16(&ugeth->p_tx_glbl_pram->temoder));
796 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
797 (u32) & ugeth->p_tx_glbl_pram->sqptr,
798 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
799 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
800 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
801 in_be32(&ugeth->p_tx_glbl_pram->
802 schedulerbasepointer));
803 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
804 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
805 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
806 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
807 (u32) & ugeth->p_tx_glbl_pram->tstate,
808 in_be32(&ugeth->p_tx_glbl_pram->tstate));
809 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
810 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
811 ugeth->p_tx_glbl_pram->iphoffset[0]);
812 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
813 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
814 ugeth->p_tx_glbl_pram->iphoffset[1]);
815 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
816 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
817 ugeth->p_tx_glbl_pram->iphoffset[2]);
818 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
819 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
820 ugeth->p_tx_glbl_pram->iphoffset[3]);
821 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
822 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
823 ugeth->p_tx_glbl_pram->iphoffset[4]);
824 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
825 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
826 ugeth->p_tx_glbl_pram->iphoffset[5]);
827 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
828 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
829 ugeth->p_tx_glbl_pram->iphoffset[6]);
830 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
831 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
832 ugeth->p_tx_glbl_pram->iphoffset[7]);
833 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
834 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
835 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
836 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
837 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
838 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
839 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
840 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
841 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
842 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
843 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
844 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
845 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
846 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
847 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
848 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
849 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
850 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
851 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
852 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
853 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
854 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
855 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
856 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
857 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
858 (u32) & ugeth->p_tx_glbl_pram->tqptr,
859 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
860 }
861 if (ugeth->p_rx_glbl_pram) {
862 ugeth_info("RX global param:");
863 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
864 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
865 (u32) & ugeth->p_rx_glbl_pram->remoder,
866 in_be32(&ugeth->p_rx_glbl_pram->remoder));
867 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
868 (u32) & ugeth->p_rx_glbl_pram->rqptr,
869 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
870 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
871 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
872 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
873 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
874 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
875 ugeth->p_rx_glbl_pram->rxgstpack);
876 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
877 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
878 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
879 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
880 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
881 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
882 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
883 (u32) & ugeth->p_rx_glbl_pram->rstate,
884 ugeth->p_rx_glbl_pram->rstate);
885 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
886 (u32) & ugeth->p_rx_glbl_pram->mrblr,
887 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
888 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
889 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
890 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
891 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
892 (u32) & ugeth->p_rx_glbl_pram->mflr,
893 in_be16(&ugeth->p_rx_glbl_pram->mflr));
894 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
895 (u32) & ugeth->p_rx_glbl_pram->minflr,
896 in_be16(&ugeth->p_rx_glbl_pram->minflr));
897 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
898 (u32) & ugeth->p_rx_glbl_pram->maxd1,
899 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
900 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
901 (u32) & ugeth->p_rx_glbl_pram->maxd2,
902 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
903 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
904 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
905 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
906 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
907 (u32) & ugeth->p_rx_glbl_pram->l2qt,
908 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
909 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
910 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
911 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
912 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
913 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
914 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
915 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
916 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
917 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
918 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
919 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
920 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
921 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
922 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
923 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
924 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
925 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
926 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
927 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
928 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
929 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
930 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
931 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
932 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
933 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
934 (u32) & ugeth->p_rx_glbl_pram->vlantype,
935 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
936 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
937 (u32) & ugeth->p_rx_glbl_pram->vlantci,
938 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
939 for (i = 0; i < 64; i++)
940 ugeth_info
941 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
942 i,
943 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
944 ugeth->p_rx_glbl_pram->addressfiltering[i]);
945 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
946 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
947 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
948 }
949 if (ugeth->p_send_q_mem_reg) {
950 ugeth_info("Send Q memory registers:");
951 ugeth_info("Base address: 0x%08x",
952 (u32) ugeth->p_send_q_mem_reg);
953 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
954 ugeth_info("SQQD[%d]:", i);
955 ugeth_info("Base address: 0x%08x",
956 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
957 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
18a8e864 958 sizeof(struct ucc_geth_send_queue_qd));
ce973b14
LY		 959 }
960 }
961 if (ugeth->p_scheduler) {
962 ugeth_info("Scheduler:");
963 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
964 mem_disp((u8 *) ugeth->p_scheduler,
965 sizeof(*ugeth->p_scheduler));
966 }
967 if (ugeth->p_tx_fw_statistics_pram) {
968 ugeth_info("TX FW statistics pram:");
969 ugeth_info("Base address: 0x%08x",
970 (u32) ugeth->p_tx_fw_statistics_pram);
971 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
972 sizeof(*ugeth->p_tx_fw_statistics_pram));
973 }
974 if (ugeth->p_rx_fw_statistics_pram) {
975 ugeth_info("RX FW statistics pram:");
976 ugeth_info("Base address: 0x%08x",
977 (u32) ugeth->p_rx_fw_statistics_pram);
978 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
979 sizeof(*ugeth->p_rx_fw_statistics_pram));
980 }
981 if (ugeth->p_rx_irq_coalescing_tbl) {
982 ugeth_info("RX IRQ coalescing tables:");
983 ugeth_info("Base address: 0x%08x",
984 (u32) ugeth->p_rx_irq_coalescing_tbl);
985 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
986 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
987 ugeth_info("Base address: 0x%08x",
988 (u32) & ugeth->p_rx_irq_coalescing_tbl->
989 coalescingentry[i]);
990 ugeth_info
991 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
992 (u32) & ugeth->p_rx_irq_coalescing_tbl->
993 coalescingentry[i].interruptcoalescingmaxvalue,
994 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
995 coalescingentry[i].
996 interruptcoalescingmaxvalue));
997 ugeth_info
998 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
999 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1000 coalescingentry[i].interruptcoalescingcounter,
1001 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1002 coalescingentry[i].
1003 interruptcoalescingcounter));
1004 }
1005 }
1006 if (ugeth->p_rx_bd_qs_tbl) {
1007 ugeth_info("RX BD QS tables:");
1008 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1009 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1010 ugeth_info("RX BD QS table[%d]:", i);
1011 ugeth_info("Base address: 0x%08x",
1012 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1013 ugeth_info
1014 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1015 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1016 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1017 ugeth_info
1018 ("bdptr : addr - 0x%08x, val - 0x%08x",
1019 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1020 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1021 ugeth_info
1022 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1023 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1024 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1025 externalbdbaseptr));
1026 ugeth_info
1027 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1028 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1029 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1030 ugeth_info("ucode RX Prefetched BDs:");
1031 ugeth_info("Base address: 0x%08x",
1032 (u32)
1033 qe_muram_addr(in_be32
1034 (&ugeth->p_rx_bd_qs_tbl[i].
1035 bdbaseptr)));
1036 mem_disp((u8 *)
1037 qe_muram_addr(in_be32
1038 (&ugeth->p_rx_bd_qs_tbl[i].
1039 bdbaseptr)),
18a8e864 1040 sizeof(struct ucc_geth_rx_prefetched_bds));
ce973b14
LY		 1041 }
1042 }
1043 if (ugeth->p_init_enet_param_shadow) {
1044 int size;
1045 ugeth_info("Init enet param shadow:");
1046 ugeth_info("Base address: 0x%08x",
1047 (u32) ugeth->p_init_enet_param_shadow);
1048 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1049 sizeof(*ugeth->p_init_enet_param_shadow));
1050
18a8e864 1051 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 1052 if (ugeth->ug_info->rxExtendedFiltering) {
1053 size +=
1054 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1055 if (ugeth->ug_info->largestexternallookupkeysize ==
1056 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1057 size +=
1058 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1059 if (ugeth->ug_info->largestexternallookupkeysize ==
1060 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1061 size +=
1062 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1063 }
1064
1065 dump_init_enet_entries(ugeth,
1066 &(ugeth->p_init_enet_param_shadow->
1067 txthread[0]),
1068 ENET_INIT_PARAM_MAX_ENTRIES_TX,
18a8e864 1069 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 1070 ugeth->ug_info->riscTx, 0);
1071 dump_init_enet_entries(ugeth,
1072 &(ugeth->p_init_enet_param_shadow->
1073 rxthread[0]),
1074 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1075 ugeth->ug_info->riscRx, 1);
1076 }
1077}
1078#endif /* DEBUG */
1079
6fee40e9
AF		 1080static void init_default_reg_vals(u32 __iomem *upsmr_register,
1081 u32 __iomem *maccfg1_register,
1082 u32 __iomem *maccfg2_register)
ce973b14
LY		 1083{
1084 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1085 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1086 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1087}
1088
1089static int init_half_duplex_params(int alt_beb,
1090 int back_pressure_no_backoff,
1091 int no_backoff,
1092 int excess_defer,
1093 u8 alt_beb_truncation,
1094 u8 max_retransmissions,
1095 u8 collision_window,
6fee40e9 1096 u32 __iomem *hafdup_register)
ce973b14
LY		 1097{
1098 u32 value = 0;
1099
1100 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1101 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1102 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1103 return -EINVAL;
1104
1105 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1106
1107 if (alt_beb)
1108 value |= HALFDUP_ALT_BEB;
1109 if (back_pressure_no_backoff)
1110 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1111 if (no_backoff)
1112 value |= HALFDUP_NO_BACKOFF;
1113 if (excess_defer)
1114 value |= HALFDUP_EXCESSIVE_DEFER;
1115
1116 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1117
1118 value |= collision_window;
1119
1120 out_be32(hafdup_register, value);
1121 return 0;
1122}
1123
1124static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1125 u8 non_btb_ipg,
1126 u8 min_ifg,
1127 u8 btb_ipg,
6fee40e9 1128 u32 __iomem *ipgifg_register)
ce973b14
LY		 1129{
1130 u32 value = 0;
1131
1132 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1133 IPG part 2 */
1134 if (non_btb_cs_ipg > non_btb_ipg)
1135 return -EINVAL;
1136
1137 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1138 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1139 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1140 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1141 return -EINVAL;
1142
1143 value |=
1144 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1145 IPGIFG_NBTB_CS_IPG_MASK);
1146 value |=
1147 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1148 IPGIFG_NBTB_IPG_MASK);
1149 value |=
1150 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1151 IPGIFG_MIN_IFG_MASK);
1152 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1153
1154 out_be32(ipgifg_register, value);
1155 return 0;
1156}
1157
ac421852 1158int init_flow_control_params(u32 automatic_flow_control_mode,
ce973b14
LY		 1159 int rx_flow_control_enable,
1160 int tx_flow_control_enable,
1161 u16 pause_period,
1162 u16 extension_field,
6fee40e9
AF		 1163 u32 __iomem *upsmr_register,
1164 u32 __iomem *uempr_register,
1165 u32 __iomem *maccfg1_register)
ce973b14
LY		 1166{
1167 u32 value = 0;
1168
1169 /* Set UEMPR register */
1170 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1171 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1172 out_be32(uempr_register, value);
1173
1174 /* Set UPSMR register */
3bc53427 1175 setbits32(upsmr_register, automatic_flow_control_mode);
ce973b14
LY		 1176
1177 value = in_be32(maccfg1_register);
1178 if (rx_flow_control_enable)
1179 value |= MACCFG1_FLOW_RX;
1180 if (tx_flow_control_enable)
1181 value |= MACCFG1_FLOW_TX;
1182 out_be32(maccfg1_register, value);
1183
1184 return 0;
1185}
1186
1187static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1188 int auto_zero_hardware_statistics,
6fee40e9
AF		 1189 u32 __iomem *upsmr_register,
1190 u16 __iomem *uescr_register)
ce973b14 1191{
ce973b14 1192 u16 uescr_value = 0;
3bc53427 1193
ce973b14 1194 /* Enable hardware statistics gathering if requested */
3bc53427
TT		 1195 if (enable_hardware_statistics)
1196 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
ce973b14
LY		 1197
1198 /* Clear hardware statistics counters */
1199 uescr_value = in_be16(uescr_register);
1200 uescr_value |= UESCR_CLRCNT;
1201 /* Automatically zero hardware statistics counters on read,
1202 if requested */
1203 if (auto_zero_hardware_statistics)
1204 uescr_value |= UESCR_AUTOZ;
1205 out_be16(uescr_register, uescr_value);
1206
1207 return 0;
1208}
1209
1210static int init_firmware_statistics_gathering_mode(int
1211 enable_tx_firmware_statistics,
1212 int enable_rx_firmware_statistics,
6fee40e9 1213 u32 __iomem *tx_rmon_base_ptr,
ce973b14 1214 u32 tx_firmware_statistics_structure_address,
6fee40e9 1215 u32 __iomem *rx_rmon_base_ptr,
ce973b14 1216 u32 rx_firmware_statistics_structure_address,
6fee40e9
AF		 1217 u16 __iomem *temoder_register,
1218 u32 __iomem *remoder_register)
ce973b14
LY		 1219{
1220 /* Note: this function does not check if */
1221 /* the parameters it receives are NULL */
ce973b14
LY		 1222
1223 if (enable_tx_firmware_statistics) {
1224 out_be32(tx_rmon_base_ptr,
1225 tx_firmware_statistics_structure_address);
3bc53427 1226 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
ce973b14
LY		 1227 }
1228
1229 if (enable_rx_firmware_statistics) {
1230 out_be32(rx_rmon_base_ptr,
1231 rx_firmware_statistics_structure_address);
3bc53427 1232 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
ce973b14
LY		 1233 }
1234
1235 return 0;
1236}
1237
1238static int init_mac_station_addr_regs(u8 address_byte_0,
1239 u8 address_byte_1,
1240 u8 address_byte_2,
1241 u8 address_byte_3,
1242 u8 address_byte_4,
1243 u8 address_byte_5,
6fee40e9
AF		 1244 u32 __iomem *macstnaddr1_register,
1245 u32 __iomem *macstnaddr2_register)
ce973b14
LY		 1246{
1247 u32 value = 0;
1248
1249 /* Example: for a station address of 0x12345678ABCD, */
1250 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1251
1252 /* MACSTNADDR1 Register: */
1253
1254 /* 0 7 8 15 */
1255 /* station address byte 5 station address byte 4 */
1256 /* 16 23 24 31 */
1257 /* station address byte 3 station address byte 2 */
1258 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1259 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1260 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1261 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1262
1263 out_be32(macstnaddr1_register, value);
1264
1265 /* MACSTNADDR2 Register: */
1266
1267 /* 0 7 8 15 */
1268 /* station address byte 1 station address byte 0 */
1269 /* 16 23 24 31 */
1270 /* reserved reserved */
1271 value = 0;
1272 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1273 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1274
1275 out_be32(macstnaddr2_register, value);
1276
1277 return 0;
1278}
1279
ce973b14 1280static int init_check_frame_length_mode(int length_check,
6fee40e9 1281 u32 __iomem *maccfg2_register)
ce973b14
LY		 1282{
1283 u32 value = 0;
1284
1285 value = in_be32(maccfg2_register);
1286
1287 if (length_check)
1288 value |= MACCFG2_LC;
1289 else
1290 value &= ~MACCFG2_LC;
1291
1292 out_be32(maccfg2_register, value);
1293 return 0;
1294}
1295
1296static int init_preamble_length(u8 preamble_length,
6fee40e9 1297 u32 __iomem *maccfg2_register)
ce973b14 1298{
ce973b14
LY		 1299 if ((preamble_length < 3) || (preamble_length > 7))
1300 return -EINVAL;
1301
3bc53427
TT		 1302 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1303 preamble_length << MACCFG2_PREL_SHIFT);
1304
ce973b14
LY		 1305 return 0;
1306}
1307
ce973b14
LY		 1308static int init_rx_parameters(int reject_broadcast,
1309 int receive_short_frames,
6fee40e9 1310 int promiscuous, u32 __iomem *upsmr_register)
ce973b14
LY		 1311{
1312 u32 value = 0;
1313
1314 value = in_be32(upsmr_register);
1315
1316 if (reject_broadcast)
3bc53427 1317 value |= UCC_GETH_UPSMR_BRO;
ce973b14 1318 else
3bc53427 1319 value &= ~UCC_GETH_UPSMR_BRO;
ce973b14
LY		 1320
1321 if (receive_short_frames)
3bc53427 1322 value |= UCC_GETH_UPSMR_RSH;
ce973b14 1323 else
3bc53427 1324 value &= ~UCC_GETH_UPSMR_RSH;
ce973b14
LY		 1325
1326 if (promiscuous)
3bc53427 1327 value |= UCC_GETH_UPSMR_PRO;
ce973b14 1328 else
3bc53427 1329 value &= ~UCC_GETH_UPSMR_PRO;
ce973b14
LY		 1330
1331 out_be32(upsmr_register, value);
1332
1333 return 0;
1334}
1335
1336static int init_max_rx_buff_len(u16 max_rx_buf_len,
6fee40e9 1337 u16 __iomem *mrblr_register)
ce973b14
LY		 1338{
1339 /* max_rx_buf_len value must be a multiple of 128 */
1340 if ((max_rx_buf_len == 0)
1341 || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1342 return -EINVAL;
1343
1344 out_be16(mrblr_register, max_rx_buf_len);
1345 return 0;
1346}
1347
1348static int init_min_frame_len(u16 min_frame_length,
6fee40e9
AF		 1349 u16 __iomem *minflr_register,
1350 u16 __iomem *mrblr_register)
ce973b14
LY		 1351{
1352 u16 mrblr_value = 0;
1353
1354 mrblr_value = in_be16(mrblr_register);
1355 if (min_frame_length >= (mrblr_value - 4))
1356 return -EINVAL;
1357
1358 out_be16(minflr_register, min_frame_length);
1359 return 0;
1360}
1361
18a8e864 1362static int adjust_enet_interface(struct ucc_geth_private *ugeth)
ce973b14 1363{
18a8e864 1364 struct ucc_geth_info *ug_info;
6fee40e9
AF		 1365 struct ucc_geth __iomem *ug_regs;
1366 struct ucc_fast __iomem *uf_regs;
728de4c9
KP		 1367 int ret_val;
1368 u32 upsmr, maccfg2, tbiBaseAddress;
ce973b14
LY		 1369 u16 value;
1370
b39d66a8 1371 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 1372
1373 ug_info = ugeth->ug_info;
1374 ug_regs = ugeth->ug_regs;
1375 uf_regs = ugeth->uccf->uf_regs;
1376
ce973b14
LY		 1377 /* Set MACCFG2 */
1378 maccfg2 = in_be32(&ug_regs->maccfg2);
1379 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
728de4c9
KP		 1380 if ((ugeth->max_speed == SPEED_10) ||
1381 (ugeth->max_speed == SPEED_100))
ce973b14 1382 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
728de4c9 1383 else if (ugeth->max_speed == SPEED_1000)
ce973b14
LY		 1384 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1385 maccfg2 |= ug_info->padAndCrc;
1386 out_be32(&ug_regs->maccfg2, maccfg2);
1387
1388 /* Set UPSMR */
1389 upsmr = in_be32(&uf_regs->upsmr);
3bc53427
TT		 1390 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1391 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
728de4c9
KP		 1392 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1393 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1394 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1395 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1396 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9 1397 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
cef309cf
HS		 1398 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1399 upsmr |= UCC_GETH_UPSMR_RPM;
728de4c9
KP		 1400 switch (ugeth->max_speed) {
1401 case SPEED_10:
3bc53427 1402 upsmr |= UCC_GETH_UPSMR_R10M;
728de4c9
KP		 1403 /* FALLTHROUGH */
1404 case SPEED_100:
1405 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
3bc53427 1406 upsmr |= UCC_GETH_UPSMR_RMM;
728de4c9
KP		 1407 }
1408 }
1409 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1410 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
3bc53427 1411 upsmr |= UCC_GETH_UPSMR_TBIM;
728de4c9 1412 }
ce973b14
LY		 1413 out_be32(&uf_regs->upsmr, upsmr);
1414
ce973b14
LY		 1415 /* Disable autonegotiation in tbi mode, because by default it
1416 comes up in autonegotiation mode. */
1417 /* Note that this depends on proper setting in utbipar register. */
728de4c9
KP		 1418 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1419 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
ce973b14
LY		 1420 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1421 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1422 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
728de4c9
KP		 1423 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1424 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
ce973b14 1425 value &= ~0x1000; /* Turn off autonegotiation */
728de4c9
KP		 1426 ugeth->phydev->bus->write(ugeth->phydev->bus,
1427 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
ce973b14
LY		 1428 }
1429
1430 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1431
1432 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1433 if (ret_val != 0) {
890de95e
LY		 1434 if (netif_msg_probe(ugeth))
1435 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
b39d66a8 1436 __func__);
ce973b14
LY		 1437 return ret_val;
1438 }
1439
1440 return 0;
1441}
1442
1443/* Called every time the controller might need to be made
1444 * aware of new link state. The PHY code conveys this
1445 * information through variables in the ugeth structure, and this
1446 * function converts those variables into the appropriate
1447 * register values, and can bring down the device if needed.
1448 */
728de4c9 1449
ce973b14
LY		 1450static void adjust_link(struct net_device *dev)
1451{
18a8e864 1452 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9
AF		 1453 struct ucc_geth __iomem *ug_regs;
1454 struct ucc_fast __iomem *uf_regs;
728de4c9
KP		 1455 struct phy_device *phydev = ugeth->phydev;
1456 unsigned long flags;
1457 int new_state = 0;
ce973b14
LY		 1458
1459 ug_regs = ugeth->ug_regs;
728de4c9 1460 uf_regs = ugeth->uccf->uf_regs;
ce973b14 1461
728de4c9
KP		 1462 spin_lock_irqsave(&ugeth->lock, flags);
1463
1464 if (phydev->link) {
1465 u32 tempval = in_be32(&ug_regs->maccfg2);
1466 u32 upsmr = in_be32(&uf_regs->upsmr);
ce973b14
LY		 1467 /* Now we make sure that we can be in full duplex mode.
1468 * If not, we operate in half-duplex mode. */
728de4c9
KP		 1469 if (phydev->duplex != ugeth->oldduplex) {
1470 new_state = 1;
1471 if (!(phydev->duplex))
ce973b14 1472 tempval &= ~(MACCFG2_FDX);
728de4c9 1473 else
ce973b14 1474 tempval |= MACCFG2_FDX;
728de4c9 1475 ugeth->oldduplex = phydev->duplex;
ce973b14
LY		 1476 }
1477
728de4c9
KP		 1478 if (phydev->speed != ugeth->oldspeed) {
1479 new_state = 1;
1480 switch (phydev->speed) {
1481 case SPEED_1000:
1482 tempval = ((tempval &
1483 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1484 MACCFG2_INTERFACE_MODE_BYTE);
a1862a53 1485 break;
728de4c9
KP		 1486 case SPEED_100:
1487 case SPEED_10:
1488 tempval = ((tempval &
1489 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1490 MACCFG2_INTERFACE_MODE_NIBBLE);
1491 /* if reduced mode, re-set UPSMR.R10M */
1492 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1493 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1494 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1495 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1496 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9
KP		 1497 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1498 if (phydev->speed == SPEED_10)
3bc53427 1499 upsmr |= UCC_GETH_UPSMR_R10M;
728de4c9 1500 else
3bc53427 1501 upsmr &= ~UCC_GETH_UPSMR_R10M;
728de4c9 1502 }
ce973b14
LY		 1503 break;
1504 default:
728de4c9
KP		 1505 if (netif_msg_link(ugeth))
1506 ugeth_warn(
1507 "%s: Ack! Speed (%d) is not 10/100/1000!",
1508 dev->name, phydev->speed);
ce973b14
LY		 1509 break;
1510 }
728de4c9 1511 ugeth->oldspeed = phydev->speed;
ce973b14
LY		 1512 }
1513
728de4c9
KP		 1514 out_be32(&ug_regs->maccfg2, tempval);
1515 out_be32(&uf_regs->upsmr, upsmr);
1516
ce973b14 1517 if (!ugeth->oldlink) {
728de4c9 1518 new_state = 1;
ce973b14 1519 ugeth->oldlink = 1;
ce973b14 1520 }
728de4c9
KP		 1521 } else if (ugeth->oldlink) {
1522 new_state = 1;
ce973b14
LY		 1523 ugeth->oldlink = 0;
1524 ugeth->oldspeed = 0;
1525 ugeth->oldduplex = -1;
ce973b14 1526 }
728de4c9
KP		 1527
1528 if (new_state && netif_msg_link(ugeth))
1529 phy_print_status(phydev);
1530
1531 spin_unlock_irqrestore(&ugeth->lock, flags);
ce973b14
LY		 1532}
1533
1534/* Configure the PHY for dev.
1535 * returns 0 if success. -1 if failure
1536 */
1537static int init_phy(struct net_device *dev)
1538{
728de4c9 1539 struct ucc_geth_private *priv = netdev_priv(dev);
61fa9dcf 1540 struct ucc_geth_info *ug_info = priv->ug_info;
728de4c9 1541 struct phy_device *phydev;
ce973b14 1542
728de4c9
KP		 1543 priv->oldlink = 0;
1544 priv->oldspeed = 0;
1545 priv->oldduplex = -1;
ce973b14 1546
0b9da337
GL		 1547 if (!ug_info->phy_node)
1548 return 0;
ce973b14 1549
0b9da337
GL		 1550 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1551 priv->phy_interface);
1552 if (!phydev) {
728de4c9 1553 printk("%s: Could not attach to PHY\n", dev->name);
0b9da337 1554 return -ENODEV;
ce973b14
LY		 1555 }
1556
728de4c9 1557 phydev->supported &= (ADVERTISED_10baseT_Half |
ce973b14
LY		 1558 ADVERTISED_10baseT_Full |
1559 ADVERTISED_100baseT_Half |
728de4c9 1560 ADVERTISED_100baseT_Full);
ce973b14 1561
728de4c9
KP		 1562 if (priv->max_speed == SPEED_1000)
1563 phydev->supported |= ADVERTISED_1000baseT_Full;
ce973b14 1564
728de4c9 1565 phydev->advertising = phydev->supported;
68dc44af 1566
728de4c9 1567 priv->phydev = phydev;
ce973b14
LY		 1568
1569 return 0;
ce973b14
LY		 1570}
1571
728de4c9 1572
ce973b14 1573
18a8e864 1574static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
ce973b14 1575{
18a8e864 1576 struct ucc_fast_private *uccf;
ce973b14
LY		 1577 u32 cecr_subblock;
1578 u32 temp;
b3431c64 1579 int i = 10;
ce973b14
LY		 1580
1581 uccf = ugeth->uccf;
1582
1583 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
3bc53427
TT		 1584 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1585 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
ce973b14
LY		 1586
1587 /* Issue host command */
1588 cecr_subblock =
1589 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1590 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
18a8e864 1591 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 1592
1593 /* Wait for command to complete */
1594 do {
b3431c64 1595 msleep(10);
ce973b14 1596 temp = in_be32(uccf->p_ucce);
3bc53427 1597 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
ce973b14
LY		 1598
1599 uccf->stopped_tx = 1;
1600
1601 return 0;
1602}
1603
18a8e864 1604static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
ce973b14 1605{
18a8e864 1606 struct ucc_fast_private *uccf;
ce973b14
LY		 1607 u32 cecr_subblock;
1608 u8 temp;
b3431c64 1609 int i = 10;
ce973b14
LY		 1610
1611 uccf = ugeth->uccf;
1612
1613 /* Clear acknowledge bit */
6fee40e9 1614 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
ce973b14 1615 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
6fee40e9 1616 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
ce973b14
LY		 1617
1618 /* Keep issuing command and checking acknowledge bit until
1619 it is asserted, according to spec */
1620 do {
1621 /* Issue host command */
1622 cecr_subblock =
1623 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1624 ucc_num);
1625 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
18a8e864 1626 QE_CR_PROTOCOL_ETHERNET, 0);
b3431c64 1627 msleep(10);
6fee40e9 1628 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
b3431c64 1629 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
ce973b14
LY		 1630
1631 uccf->stopped_rx = 1;
1632
1633 return 0;
1634}
1635
18a8e864 1636static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
ce973b14 1637{
18a8e864 1638 struct ucc_fast_private *uccf;
ce973b14
LY		 1639 u32 cecr_subblock;
1640
1641 uccf = ugeth->uccf;
1642
1643 cecr_subblock =
1644 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 1645 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 1646 uccf->stopped_tx = 0;
1647
1648 return 0;
1649}
1650
18a8e864 1651static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
ce973b14 1652{
18a8e864 1653 struct ucc_fast_private *uccf;
ce973b14
LY		 1654 u32 cecr_subblock;
1655
1656 uccf = ugeth->uccf;
1657
1658 cecr_subblock =
1659 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 1660 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 1661 0);
1662 uccf->stopped_rx = 0;
1663
1664 return 0;
1665}
1666
18a8e864 1667static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
ce973b14 1668{
18a8e864 1669 struct ucc_fast_private *uccf;
ce973b14
LY		 1670 int enabled_tx, enabled_rx;
1671
1672 uccf = ugeth->uccf;
1673
1674 /* check if the UCC number is in range. */
1675 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
890de95e 1676 if (netif_msg_probe(ugeth))
b39d66a8 1677 ugeth_err("%s: ucc_num out of range.", __func__);
ce973b14
LY		 1678 return -EINVAL;
1679 }
1680
1681 enabled_tx = uccf->enabled_tx;
1682 enabled_rx = uccf->enabled_rx;
1683
1684 /* Get Tx and Rx going again, in case this channel was actively
1685 disabled. */
1686 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1687 ugeth_restart_tx(ugeth);
1688 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1689 ugeth_restart_rx(ugeth);
1690
1691 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1692
1693 return 0;
1694
1695}
1696
18a8e864 1697static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
ce973b14 1698{
18a8e864 1699 struct ucc_fast_private *uccf;
ce973b14
LY		 1700
1701 uccf = ugeth->uccf;
1702
1703 /* check if the UCC number is in range. */
1704 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
890de95e 1705 if (netif_msg_probe(ugeth))
b39d66a8 1706 ugeth_err("%s: ucc_num out of range.", __func__);
ce973b14
LY		 1707 return -EINVAL;
1708 }
1709
1710 /* Stop any transmissions */
1711 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1712 ugeth_graceful_stop_tx(ugeth);
1713
1714 /* Stop any receptions */
1715 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1716 ugeth_graceful_stop_rx(ugeth);
1717
1718 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1719
1720 return 0;
1721}
1722
18a8e864 1723static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 1724{
1725#ifdef DEBUG
1726 ucc_fast_dump_regs(ugeth->uccf);
1727 dump_regs(ugeth);
1728 dump_bds(ugeth);
1729#endif
1730}
1731
18a8e864 1732static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
ce973b14 1733 ugeth,
18a8e864 1734 enum enet_addr_type
ce973b14
LY		 1735 enet_addr_type)
1736{
6fee40e9 1737 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
18a8e864
LY		 1738 struct ucc_fast_private *uccf;
1739 enum comm_dir comm_dir;
ce973b14
LY		 1740 struct list_head *p_lh;
1741 u16 i, num;
6fee40e9
AF		 1742 u32 __iomem *addr_h;
1743 u32 __iomem *addr_l;
ce973b14
LY		 1744 u8 *p_counter;
1745
1746 uccf = ugeth->uccf;
1747
1748 p_82xx_addr_filt =
6fee40e9
AF		 1749 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1750 ugeth->p_rx_glbl_pram->addressfiltering;
ce973b14
LY		 1751
1752 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1753 addr_h = &(p_82xx_addr_filt->gaddr_h);
1754 addr_l = &(p_82xx_addr_filt->gaddr_l);
1755 p_lh = &ugeth->group_hash_q;
1756 p_counter = &(ugeth->numGroupAddrInHash);
1757 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1758 addr_h = &(p_82xx_addr_filt->iaddr_h);
1759 addr_l = &(p_82xx_addr_filt->iaddr_l);
1760 p_lh = &ugeth->ind_hash_q;
1761 p_counter = &(ugeth->numIndAddrInHash);
1762 } else
1763 return -EINVAL;
1764
1765 comm_dir = 0;
1766 if (uccf->enabled_tx)
1767 comm_dir |= COMM_DIR_TX;
1768 if (uccf->enabled_rx)
1769 comm_dir |= COMM_DIR_RX;
1770 if (comm_dir)
1771 ugeth_disable(ugeth, comm_dir);
1772
1773 /* Clear the hash table. */
1774 out_be32(addr_h, 0x00000000);
1775 out_be32(addr_l, 0x00000000);
1776
1777 if (!p_lh)
1778 return 0;
1779
1780 num = *p_counter;
1781
1782 /* Delete all remaining CQ elements */
1783 for (i = 0; i < num; i++)
1784 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1785
1786 *p_counter = 0;
1787
1788 if (comm_dir)
1789 ugeth_enable(ugeth, comm_dir);
1790
1791 return 0;
1792}
1793
18a8e864 1794static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
ce973b14
LY		 1795 u8 paddr_num)
1796{
1797 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1798 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1799}
1800
18a8e864 1801static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
ce973b14
LY		 1802{
1803 u16 i, j;
6fee40e9 1804 u8 __iomem *bd;
ce973b14
LY		 1805
1806 if (!ugeth)
1807 return;
1808
80a9fad8 1809 if (ugeth->uccf) {
ce973b14 1810 ucc_fast_free(ugeth->uccf);
80a9fad8
AV		 1811 ugeth->uccf = NULL;
1812 }
ce973b14
LY		 1813
1814 if (ugeth->p_thread_data_tx) {
1815 qe_muram_free(ugeth->thread_dat_tx_offset);
1816 ugeth->p_thread_data_tx = NULL;
1817 }
1818 if (ugeth->p_thread_data_rx) {
1819 qe_muram_free(ugeth->thread_dat_rx_offset);
1820 ugeth->p_thread_data_rx = NULL;
1821 }
1822 if (ugeth->p_exf_glbl_param) {
1823 qe_muram_free(ugeth->exf_glbl_param_offset);
1824 ugeth->p_exf_glbl_param = NULL;
1825 }
1826 if (ugeth->p_rx_glbl_pram) {
1827 qe_muram_free(ugeth->rx_glbl_pram_offset);
1828 ugeth->p_rx_glbl_pram = NULL;
1829 }
1830 if (ugeth->p_tx_glbl_pram) {
1831 qe_muram_free(ugeth->tx_glbl_pram_offset);
1832 ugeth->p_tx_glbl_pram = NULL;
1833 }
1834 if (ugeth->p_send_q_mem_reg) {
1835 qe_muram_free(ugeth->send_q_mem_reg_offset);
1836 ugeth->p_send_q_mem_reg = NULL;
1837 }
1838 if (ugeth->p_scheduler) {
1839 qe_muram_free(ugeth->scheduler_offset);
1840 ugeth->p_scheduler = NULL;
1841 }
1842 if (ugeth->p_tx_fw_statistics_pram) {
1843 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1844 ugeth->p_tx_fw_statistics_pram = NULL;
1845 }
1846 if (ugeth->p_rx_fw_statistics_pram) {
1847 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1848 ugeth->p_rx_fw_statistics_pram = NULL;
1849 }
1850 if (ugeth->p_rx_irq_coalescing_tbl) {
1851 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1852 ugeth->p_rx_irq_coalescing_tbl = NULL;
1853 }
1854 if (ugeth->p_rx_bd_qs_tbl) {
1855 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1856 ugeth->p_rx_bd_qs_tbl = NULL;
1857 }
1858 if (ugeth->p_init_enet_param_shadow) {
1859 return_init_enet_entries(ugeth,
1860 &(ugeth->p_init_enet_param_shadow->
1861 rxthread[0]),
1862 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1863 ugeth->ug_info->riscRx, 1);
1864 return_init_enet_entries(ugeth,
1865 &(ugeth->p_init_enet_param_shadow->
1866 txthread[0]),
1867 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1868 ugeth->ug_info->riscTx, 0);
1869 kfree(ugeth->p_init_enet_param_shadow);
1870 ugeth->p_init_enet_param_shadow = NULL;
1871 }
1872 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1873 bd = ugeth->p_tx_bd_ring[i];
3a8205ea
NIP		 1874 if (!bd)
1875 continue;
ce973b14
LY		 1876 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1877 if (ugeth->tx_skbuff[i][j]) {
da1aa63e 1878 dma_unmap_single(ugeth->dev,
6fee40e9
AF		 1879 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1880 (in_be32((u32 __iomem *)bd) &
ce973b14
LY		 1881 BD_LENGTH_MASK),
1882 DMA_TO_DEVICE);
1883 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1884 ugeth->tx_skbuff[i][j] = NULL;
1885 }
1886 }
1887
1888 kfree(ugeth->tx_skbuff[i]);
1889
1890 if (ugeth->p_tx_bd_ring[i]) {
1891 if (ugeth->ug_info->uf_info.bd_mem_part ==
1892 MEM_PART_SYSTEM)
1893 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1894 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1895 MEM_PART_MURAM)
1896 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1897 ugeth->p_tx_bd_ring[i] = NULL;
1898 }
1899 }
1900 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1901 if (ugeth->p_rx_bd_ring[i]) {
1902 /* Return existing data buffers in ring */
1903 bd = ugeth->p_rx_bd_ring[i];
1904 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1905 if (ugeth->rx_skbuff[i][j]) {
da1aa63e 1906 dma_unmap_single(ugeth->dev,
6fee40e9 1907 in_be32(&((struct qe_bd __iomem *)bd)->buf),
18a8e864
LY		 1908 ugeth->ug_info->
1909 uf_info.max_rx_buf_length +
1910 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1911 DMA_FROM_DEVICE);
1912 dev_kfree_skb_any(
1913 ugeth->rx_skbuff[i][j]);
ce973b14
LY		 1914 ugeth->rx_skbuff[i][j] = NULL;
1915 }
18a8e864 1916 bd += sizeof(struct qe_bd);
ce973b14
LY		 1917 }
1918
1919 kfree(ugeth->rx_skbuff[i]);
1920
1921 if (ugeth->ug_info->uf_info.bd_mem_part ==
1922 MEM_PART_SYSTEM)
1923 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1924 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1925 MEM_PART_MURAM)
1926 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1927 ugeth->p_rx_bd_ring[i] = NULL;
1928 }
1929 }
1930 while (!list_empty(&ugeth->group_hash_q))
1931 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1932 (dequeue(&ugeth->group_hash_q)));
1933 while (!list_empty(&ugeth->ind_hash_q))
1934 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1935 (dequeue(&ugeth->ind_hash_q)));
3e73fc9a
AV		 1936 if (ugeth->ug_regs) {
1937 iounmap(ugeth->ug_regs);
1938 ugeth->ug_regs = NULL;
1939 }
ce973b14
LY		 1940}
1941
1942static void ucc_geth_set_multi(struct net_device *dev)
1943{
18a8e864 1944 struct ucc_geth_private *ugeth;
ce973b14 1945 struct dev_mc_list *dmi;
6fee40e9
AF		 1946 struct ucc_fast __iomem *uf_regs;
1947 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
9030b3dd 1948 int i;
ce973b14
LY		 1949
1950 ugeth = netdev_priv(dev);
1951
1952 uf_regs = ugeth->uccf->uf_regs;
1953
1954 if (dev->flags & IFF_PROMISC) {
3bc53427 1955 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
ce973b14 1956 } else {
3bc53427 1957 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
ce973b14
LY		 1958
1959 p_82xx_addr_filt =
6fee40e9 1960 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 1961 p_rx_glbl_pram->addressfiltering;
1962
1963 if (dev->flags & IFF_ALLMULTI) {
1964 /* Catch all multicast addresses, so set the
1965 * filter to all 1's.
1966 */
1967 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
1968 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
1969 } else {
1970 /* Clear filter and add the addresses in the list.
1971 */
1972 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
1973 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
1974
1975 dmi = dev->mc_list;
1976
1977 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
1978
1979 /* Only support group multicast for now.
1980 */
1981 if (!(dmi->dmi_addr[0] & 1))
1982 continue;
1983
ce973b14
LY		 1984 /* Ask CPM to run CRC and set bit in
1985 * filter mask.
1986 */
9030b3dd 1987 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
ce973b14
LY		 1988 }
1989 }
1990 }
1991}
1992
18a8e864 1993static void ucc_geth_stop(struct ucc_geth_private *ugeth)
ce973b14 1994{
6fee40e9 1995 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
728de4c9 1996 struct phy_device *phydev = ugeth->phydev;
ce973b14 1997
b39d66a8 1998 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 1999
2000 /* Disable the controller */
2001 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2002
2003 /* Tell the kernel the link is down */
728de4c9 2004 phy_stop(phydev);
ce973b14
LY		 2005
2006 /* Mask all interrupts */
c6f5047b 2007 out_be32(ugeth->uccf->p_uccm, 0x00000000);
ce973b14
LY		 2008
2009 /* Clear all interrupts */
2010 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2011
2012 /* Disable Rx and Tx */
3bc53427 2013 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
ce973b14 2014
79675900
AV		 2015 phy_disconnect(ugeth->phydev);
2016 ugeth->phydev = NULL;
2017
ce973b14
LY		 2018 ucc_geth_memclean(ugeth);
2019}
2020
728de4c9 2021static int ucc_struct_init(struct ucc_geth_private *ugeth)
ce973b14 2022{
18a8e864
LY		 2023 struct ucc_geth_info *ug_info;
2024 struct ucc_fast_info *uf_info;
728de4c9 2025 int i;
ce973b14
LY		 2026
2027 ug_info = ugeth->ug_info;
2028 uf_info = &ug_info->uf_info;
2029
2030 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2031 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
890de95e
LY		 2032 if (netif_msg_probe(ugeth))
2033 ugeth_err("%s: Bad memory partition value.",
b39d66a8 2034 __func__);
ce973b14
LY		 2035 return -EINVAL;
2036 }
2037
2038 /* Rx BD lengths */
2039 for (i = 0; i < ug_info->numQueuesRx; i++) {
2040 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2041 (ug_info->bdRingLenRx[i] %
2042 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
890de95e
LY		 2043 if (netif_msg_probe(ugeth))
2044 ugeth_err
2045 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
b39d66a8 2046 __func__);
ce973b14
LY		 2047 return -EINVAL;
2048 }
2049 }
2050
2051 /* Tx BD lengths */
2052 for (i = 0; i < ug_info->numQueuesTx; i++) {
2053 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
890de95e
LY		 2054 if (netif_msg_probe(ugeth))
2055 ugeth_err
2056 ("%s: Tx BD ring length must be no smaller than 2.",
b39d66a8 2057 __func__);
ce973b14
LY		 2058 return -EINVAL;
2059 }
2060 }
2061
2062 /* mrblr */
2063 if ((uf_info->max_rx_buf_length == 0) ||
2064 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
890de95e
LY		 2065 if (netif_msg_probe(ugeth))
2066 ugeth_err
2067 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
b39d66a8 2068 __func__);
ce973b14
LY		 2069 return -EINVAL;
2070 }
2071
2072 /* num Tx queues */
2073 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
890de95e 2074 if (netif_msg_probe(ugeth))
b39d66a8 2075 ugeth_err("%s: number of tx queues too large.", __func__);
ce973b14
LY		 2076 return -EINVAL;
2077 }
2078
2079 /* num Rx queues */
2080 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
890de95e 2081 if (netif_msg_probe(ugeth))
b39d66a8 2082 ugeth_err("%s: number of rx queues too large.", __func__);
ce973b14
LY		 2083 return -EINVAL;
2084 }
2085
2086 /* l2qt */
2087 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2088 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
890de95e
LY		 2089 if (netif_msg_probe(ugeth))
2090 ugeth_err
2091 ("%s: VLAN priority table entry must not be"
2092 " larger than number of Rx queues.",
b39d66a8 2093 __func__);
ce973b14
LY		 2094 return -EINVAL;
2095 }
2096 }
2097
2098 /* l3qt */
2099 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2100 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
890de95e
LY		 2101 if (netif_msg_probe(ugeth))
2102 ugeth_err
2103 ("%s: IP priority table entry must not be"
2104 " larger than number of Rx queues.",
b39d66a8 2105 __func__);
ce973b14
LY		 2106 return -EINVAL;
2107 }
2108 }
2109
2110 if (ug_info->cam && !ug_info->ecamptr) {
890de95e
LY		 2111 if (netif_msg_probe(ugeth))
2112 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
b39d66a8 2113 __func__);
ce973b14
LY		 2114 return -EINVAL;
2115 }
2116
2117 if ((ug_info->numStationAddresses !=
2118 UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2119 && ug_info->rxExtendedFiltering) {
890de95e
LY		 2120 if (netif_msg_probe(ugeth))
2121 ugeth_err("%s: Number of station addresses greater than 1 "
2122 "not allowed in extended parsing mode.",
b39d66a8 2123 __func__);
ce973b14
LY		 2124 return -EINVAL;
2125 }
2126
2127 /* Generate uccm_mask for receive */
2128 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2129 for (i = 0; i < ug_info->numQueuesRx; i++)
3bc53427 2130 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
ce973b14
LY		 2131
2132 for (i = 0; i < ug_info->numQueuesTx; i++)
3bc53427 2133 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
ce973b14 2134 /* Initialize the general fast UCC block. */
728de4c9 2135 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
890de95e 2136 if (netif_msg_probe(ugeth))
b39d66a8 2137 ugeth_err("%s: Failed to init uccf.", __func__);
ce973b14
LY		 2138 return -ENOMEM;
2139 }
728de4c9 2140
3e73fc9a
AV		 2141 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2142 if (!ugeth->ug_regs) {
2143 if (netif_msg_probe(ugeth))
2144 ugeth_err("%s: Failed to ioremap regs.", __func__);
2145 return -ENOMEM;
2146 }
728de4c9
KP		 2147
2148 return 0;
2149}
2150
2151static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2152{
6fee40e9
AF		 2153 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2154 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
728de4c9
KP		 2155 struct ucc_fast_private *uccf;
2156 struct ucc_geth_info *ug_info;
2157 struct ucc_fast_info *uf_info;
6fee40e9
AF		 2158 struct ucc_fast __iomem *uf_regs;
2159 struct ucc_geth __iomem *ug_regs;
728de4c9
KP		 2160 int ret_val = -EINVAL;
2161 u32 remoder = UCC_GETH_REMODER_INIT;
3bc53427 2162 u32 init_enet_pram_offset, cecr_subblock, command;
728de4c9
KP		 2163 u32 ifstat, i, j, size, l2qt, l3qt, length;
2164 u16 temoder = UCC_GETH_TEMODER_INIT;
2165 u16 test;
2166 u8 function_code = 0;
6fee40e9
AF		 2167 u8 __iomem *bd;
2168 u8 __iomem *endOfRing;
728de4c9
KP		 2169 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2170
b39d66a8 2171 ugeth_vdbg("%s: IN", __func__);
728de4c9
KP		 2172 uccf = ugeth->uccf;
2173 ug_info = ugeth->ug_info;
2174 uf_info = &ug_info->uf_info;
2175 uf_regs = uccf->uf_regs;
2176 ug_regs = ugeth->ug_regs;
ce973b14
LY		 2177
2178 switch (ug_info->numThreadsRx) {
2179 case UCC_GETH_NUM_OF_THREADS_1:
2180 numThreadsRxNumerical = 1;
2181 break;
2182 case UCC_GETH_NUM_OF_THREADS_2:
2183 numThreadsRxNumerical = 2;
2184 break;
2185 case UCC_GETH_NUM_OF_THREADS_4:
2186 numThreadsRxNumerical = 4;
2187 break;
2188 case UCC_GETH_NUM_OF_THREADS_6:
2189 numThreadsRxNumerical = 6;
2190 break;
2191 case UCC_GETH_NUM_OF_THREADS_8:
2192 numThreadsRxNumerical = 8;
2193 break;
2194 default:
890de95e
LY		 2195 if (netif_msg_ifup(ugeth))
2196 ugeth_err("%s: Bad number of Rx threads value.",
b39d66a8 2197 __func__);
ce973b14
LY		 2198 return -EINVAL;
2199 break;
2200 }
2201
2202 switch (ug_info->numThreadsTx) {
2203 case UCC_GETH_NUM_OF_THREADS_1:
2204 numThreadsTxNumerical = 1;
2205 break;
2206 case UCC_GETH_NUM_OF_THREADS_2:
2207 numThreadsTxNumerical = 2;
2208 break;
2209 case UCC_GETH_NUM_OF_THREADS_4:
2210 numThreadsTxNumerical = 4;
2211 break;
2212 case UCC_GETH_NUM_OF_THREADS_6:
2213 numThreadsTxNumerical = 6;
2214 break;
2215 case UCC_GETH_NUM_OF_THREADS_8:
2216 numThreadsTxNumerical = 8;
2217 break;
2218 default:
890de95e
LY		 2219 if (netif_msg_ifup(ugeth))
2220 ugeth_err("%s: Bad number of Tx threads value.",
b39d66a8 2221 __func__);
ce973b14
LY		 2222 return -EINVAL;
2223 break;
2224 }
2225
2226 /* Calculate rx_extended_features */
2227 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2228 ug_info->ipAddressAlignment ||
2229 (ug_info->numStationAddresses !=
2230 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2231
2232 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2233 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2234 || (ug_info->vlanOperationNonTagged !=
2235 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2236
ce973b14
LY		 2237 init_default_reg_vals(&uf_regs->upsmr,
2238 &ug_regs->maccfg1, &ug_regs->maccfg2);
2239
2240 /* Set UPSMR */
2241 /* For more details see the hardware spec. */
2242 init_rx_parameters(ug_info->bro,
2243 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2244
2245 /* We're going to ignore other registers for now, */
2246 /* except as needed to get up and running */
2247
2248 /* Set MACCFG1 */
2249 /* For more details see the hardware spec. */
2250 init_flow_control_params(ug_info->aufc,
2251 ug_info->receiveFlowControl,
ac421852 2252 ug_info->transmitFlowControl,
ce973b14
LY		 2253 ug_info->pausePeriod,
2254 ug_info->extensionField,
2255 &uf_regs->upsmr,
2256 &ug_regs->uempr, &ug_regs->maccfg1);
2257
3bc53427 2258 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
ce973b14
LY		 2259
2260 /* Set IPGIFG */
2261 /* For more details see the hardware spec. */
2262 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2263 ug_info->nonBackToBackIfgPart2,
2264 ug_info->
2265 miminumInterFrameGapEnforcement,
2266 ug_info->backToBackInterFrameGap,
2267 &ug_regs->ipgifg);
2268 if (ret_val != 0) {
890de95e
LY		 2269 if (netif_msg_ifup(ugeth))
2270 ugeth_err("%s: IPGIFG initialization parameter too large.",
b39d66a8 2271 __func__);
ce973b14
LY		 2272 return ret_val;
2273 }
2274
2275 /* Set HAFDUP */
2276 /* For more details see the hardware spec. */
2277 ret_val = init_half_duplex_params(ug_info->altBeb,
2278 ug_info->backPressureNoBackoff,
2279 ug_info->noBackoff,
2280 ug_info->excessDefer,
2281 ug_info->altBebTruncation,
2282 ug_info->maxRetransmission,
2283 ug_info->collisionWindow,
2284 &ug_regs->hafdup);
2285 if (ret_val != 0) {
890de95e
LY		 2286 if (netif_msg_ifup(ugeth))
2287 ugeth_err("%s: Half Duplex initialization parameter too large.",
b39d66a8 2288 __func__);
ce973b14
LY		 2289 return ret_val;
2290 }
2291
2292 /* Set IFSTAT */
2293 /* For more details see the hardware spec. */
2294 /* Read only - resets upon read */
2295 ifstat = in_be32(&ug_regs->ifstat);
2296
2297 /* Clear UEMPR */
2298 /* For more details see the hardware spec. */
2299 out_be32(&ug_regs->uempr, 0);
2300
2301 /* Set UESCR */
2302 /* For more details see the hardware spec. */
2303 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2304 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2305 0, &uf_regs->upsmr, &ug_regs->uescr);
2306
2307 /* Allocate Tx bds */
2308 for (j = 0; j < ug_info->numQueuesTx; j++) {
2309 /* Allocate in multiple of
2310 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2311 according to spec */
18a8e864 2312 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
ce973b14
LY		 2313 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2314 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
18a8e864 2315 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
ce973b14
LY		 2316 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2317 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2318 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2319 u32 align = 4;
2320 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2321 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2322 ugeth->tx_bd_ring_offset[j] =
6fee40e9 2323 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
04b588d7 2324
ce973b14
LY		 2325 if (ugeth->tx_bd_ring_offset[j] != 0)
2326 ugeth->p_tx_bd_ring[j] =
6fee40e9 2327 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
ce973b14
LY		 2328 align) & ~(align - 1));
2329 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2330 ugeth->tx_bd_ring_offset[j] =
2331 qe_muram_alloc(length,
2332 UCC_GETH_TX_BD_RING_ALIGNMENT);
4c35630c 2333 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
ce973b14 2334 ugeth->p_tx_bd_ring[j] =
6fee40e9 2335 (u8 __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2336 tx_bd_ring_offset[j]);
2337 }
2338 if (!ugeth->p_tx_bd_ring[j]) {
890de95e
LY		 2339 if (netif_msg_ifup(ugeth))
2340 ugeth_err
2341 ("%s: Can not allocate memory for Tx bd rings.",
b39d66a8 2342 __func__);
ce973b14
LY		 2343 return -ENOMEM;
2344 }
2345 /* Zero unused end of bd ring, according to spec */
6fee40e9
AF		 2346 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2347 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
18a8e864 2348 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
ce973b14
LY		 2349 }
2350
2351 /* Allocate Rx bds */
2352 for (j = 0; j < ug_info->numQueuesRx; j++) {
18a8e864 2353 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
ce973b14
LY		 2354 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2355 u32 align = 4;
2356 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2357 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2358 ugeth->rx_bd_ring_offset[j] =
6fee40e9 2359 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
ce973b14
LY		 2360 if (ugeth->rx_bd_ring_offset[j] != 0)
2361 ugeth->p_rx_bd_ring[j] =
6fee40e9 2362 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
ce973b14
LY		 2363 align) & ~(align - 1));
2364 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2365 ugeth->rx_bd_ring_offset[j] =
2366 qe_muram_alloc(length,
2367 UCC_GETH_RX_BD_RING_ALIGNMENT);
4c35630c 2368 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
ce973b14 2369 ugeth->p_rx_bd_ring[j] =
6fee40e9 2370 (u8 __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2371 rx_bd_ring_offset[j]);
2372 }
2373 if (!ugeth->p_rx_bd_ring[j]) {
890de95e
LY		 2374 if (netif_msg_ifup(ugeth))
2375 ugeth_err
2376 ("%s: Can not allocate memory for Rx bd rings.",
b39d66a8 2377 __func__);
ce973b14
LY		 2378 return -ENOMEM;
2379 }
2380 }
2381
2382 /* Init Tx bds */
2383 for (j = 0; j < ug_info->numQueuesTx; j++) {
2384 /* Setup the skbuff rings */
04b588d7
AD		 2385 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2386 ugeth->ug_info->bdRingLenTx[j],
2387 GFP_KERNEL);
ce973b14
LY		 2388
2389 if (ugeth->tx_skbuff[j] == NULL) {
890de95e
LY		 2390 if (netif_msg_ifup(ugeth))
2391 ugeth_err("%s: Could not allocate tx_skbuff",
b39d66a8 2392 __func__);
ce973b14
LY		 2393 return -ENOMEM;
2394 }
2395
2396 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2397 ugeth->tx_skbuff[j][i] = NULL;
2398
2399 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2400 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2401 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
18a8e864 2402 /* clear bd buffer */
6fee40e9 2403 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
18a8e864 2404 /* set bd status and length */
6fee40e9 2405 out_be32((u32 __iomem *)bd, 0);
18a8e864 2406 bd += sizeof(struct qe_bd);
ce973b14 2407 }
18a8e864
LY		 2408 bd -= sizeof(struct qe_bd);
2409 /* set bd status and length */
6fee40e9 2410 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
ce973b14
LY		 2411 }
2412
2413 /* Init Rx bds */
2414 for (j = 0; j < ug_info->numQueuesRx; j++) {
2415 /* Setup the skbuff rings */
04b588d7
AD		 2416 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2417 ugeth->ug_info->bdRingLenRx[j],
2418 GFP_KERNEL);
ce973b14
LY		 2419
2420 if (ugeth->rx_skbuff[j] == NULL) {
890de95e
LY		 2421 if (netif_msg_ifup(ugeth))
2422 ugeth_err("%s: Could not allocate rx_skbuff",
b39d66a8 2423 __func__);
ce973b14
LY		 2424 return -ENOMEM;
2425 }
2426
2427 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2428 ugeth->rx_skbuff[j][i] = NULL;
2429
2430 ugeth->skb_currx[j] = 0;
2431 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2432 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
18a8e864 2433 /* set bd status and length */
6fee40e9 2434 out_be32((u32 __iomem *)bd, R_I);
18a8e864 2435 /* clear bd buffer */
6fee40e9 2436 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
18a8e864 2437 bd += sizeof(struct qe_bd);
ce973b14 2438 }
18a8e864
LY		 2439 bd -= sizeof(struct qe_bd);
2440 /* set bd status and length */
6fee40e9 2441 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
ce973b14
LY		 2442 }
2443
2444 /*
2445 * Global PRAM
2446 */
2447 /* Tx global PRAM */
2448 /* Allocate global tx parameter RAM page */
2449 ugeth->tx_glbl_pram_offset =
18a8e864 2450 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
ce973b14 2451 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2452 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
890de95e
LY		 2453 if (netif_msg_ifup(ugeth))
2454 ugeth_err
2455 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
b39d66a8 2456 __func__);
ce973b14
LY		 2457 return -ENOMEM;
2458 }
2459 ugeth->p_tx_glbl_pram =
6fee40e9 2460 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2461 tx_glbl_pram_offset);
2462 /* Zero out p_tx_glbl_pram */
6fee40e9 2463 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
ce973b14
LY		 2464
2465 /* Fill global PRAM */
2466
2467 /* TQPTR */
2468 /* Size varies with number of Tx threads */
2469 ugeth->thread_dat_tx_offset =
2470 qe_muram_alloc(numThreadsTxNumerical *
18a8e864 2471 sizeof(struct ucc_geth_thread_data_tx) +
ce973b14
LY		 2472 32 * (numThreadsTxNumerical == 1),
2473 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2474 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
890de95e
LY		 2475 if (netif_msg_ifup(ugeth))
2476 ugeth_err
2477 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
b39d66a8 2478 __func__);
ce973b14
LY		 2479 return -ENOMEM;
2480 }
2481
2482 ugeth->p_thread_data_tx =
6fee40e9 2483 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2484 thread_dat_tx_offset);
2485 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2486
2487 /* vtagtable */
2488 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2489 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2490 ug_info->vtagtable[i]);
2491
2492 /* iphoffset */
2493 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
6fee40e9
AF		 2494 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2495 ug_info->iphoffset[i]);
ce973b14
LY		 2496
2497 /* SQPTR */
2498 /* Size varies with number of Tx queues */
2499 ugeth->send_q_mem_reg_offset =
2500 qe_muram_alloc(ug_info->numQueuesTx *
18a8e864 2501 sizeof(struct ucc_geth_send_queue_qd),
ce973b14 2502 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
4c35630c 2503 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
890de95e
LY		 2504 if (netif_msg_ifup(ugeth))
2505 ugeth_err
2506 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
b39d66a8 2507 __func__);
ce973b14
LY		 2508 return -ENOMEM;
2509 }
2510
2511 ugeth->p_send_q_mem_reg =
6fee40e9 2512 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2513 send_q_mem_reg_offset);
2514 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2515
2516 /* Setup the table */
2517 /* Assume BD rings are already established */
2518 for (i = 0; i < ug_info->numQueuesTx; i++) {
2519 endOfRing =
2520 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
18a8e864 2521 1) * sizeof(struct qe_bd);
ce973b14
LY		 2522 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2523 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2524 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2525 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2526 last_bd_completed_address,
2527 (u32) virt_to_phys(endOfRing));
2528 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2529 MEM_PART_MURAM) {
2530 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2531 (u32) immrbar_virt_to_phys(ugeth->
2532 p_tx_bd_ring[i]));
2533 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2534 last_bd_completed_address,
2535 (u32) immrbar_virt_to_phys(endOfRing));
2536 }
2537 }
2538
2539 /* schedulerbasepointer */
2540
2541 if (ug_info->numQueuesTx > 1) {
2542 /* scheduler exists only if more than 1 tx queue */
2543 ugeth->scheduler_offset =
18a8e864 2544 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
ce973b14 2545 UCC_GETH_SCHEDULER_ALIGNMENT);
4c35630c 2546 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
890de95e
LY		 2547 if (netif_msg_ifup(ugeth))
2548 ugeth_err
2549 ("%s: Can not allocate DPRAM memory for p_scheduler.",
b39d66a8 2550 __func__);
ce973b14
LY		 2551 return -ENOMEM;
2552 }
2553
2554 ugeth->p_scheduler =
6fee40e9 2555 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2556 scheduler_offset);
2557 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2558 ugeth->scheduler_offset);
2559 /* Zero out p_scheduler */
6fee40e9 2560 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
ce973b14
LY		 2561
2562 /* Set values in scheduler */
2563 out_be32(&ugeth->p_scheduler->mblinterval,
2564 ug_info->mblinterval);
2565 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2566 ug_info->nortsrbytetime);
6fee40e9
AF		 2567 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2568 out_8(&ugeth->p_scheduler->strictpriorityq,
2569 ug_info->strictpriorityq);
2570 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2571 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
ce973b14 2572 for (i = 0; i < NUM_TX_QUEUES; i++)
6fee40e9
AF		 2573 out_8(&ugeth->p_scheduler->weightfactor[i],
2574 ug_info->weightfactor[i]);
ce973b14
LY		 2575
2576 /* Set pointers to cpucount registers in scheduler */
2577 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2578 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2579 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2580 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2581 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2582 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2583 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2584 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2585 }
2586
2587 /* schedulerbasepointer */
2588 /* TxRMON_PTR (statistics) */
2589 if (ug_info->
2590 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2591 ugeth->tx_fw_statistics_pram_offset =
2592 qe_muram_alloc(sizeof
18a8e864 2593 (struct ucc_geth_tx_firmware_statistics_pram),
ce973b14 2594 UCC_GETH_TX_STATISTICS_ALIGNMENT);
4c35630c 2595 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
890de95e
LY		 2596 if (netif_msg_ifup(ugeth))
2597 ugeth_err
2598 ("%s: Can not allocate DPRAM memory for"
2599 " p_tx_fw_statistics_pram.",
b39d66a8 2600 __func__);
ce973b14
LY		 2601 return -ENOMEM;
2602 }
2603 ugeth->p_tx_fw_statistics_pram =
6fee40e9 2604 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2605 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2606 /* Zero out p_tx_fw_statistics_pram */
6fee40e9 2607 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
18a8e864 2608 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
ce973b14
LY		 2609 }
2610
2611 /* temoder */
2612 /* Already has speed set */
2613
2614 if (ug_info->numQueuesTx > 1)
2615 temoder |= TEMODER_SCHEDULER_ENABLE;
2616 if (ug_info->ipCheckSumGenerate)
2617 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2618 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2619 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2620
2621 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2622
2623 /* Function code register value to be used later */
6b0b594b 2624 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
ce973b14
LY		 2625 /* Required for QE */
2626
2627 /* function code register */
2628 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2629
2630 /* Rx global PRAM */
2631 /* Allocate global rx parameter RAM page */
2632 ugeth->rx_glbl_pram_offset =
18a8e864 2633 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
ce973b14 2634 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2635 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
890de95e
LY		 2636 if (netif_msg_ifup(ugeth))
2637 ugeth_err
2638 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
b39d66a8 2639 __func__);
ce973b14
LY		 2640 return -ENOMEM;
2641 }
2642 ugeth->p_rx_glbl_pram =
6fee40e9 2643 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2644 rx_glbl_pram_offset);
2645 /* Zero out p_rx_glbl_pram */
6fee40e9 2646 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
ce973b14
LY		 2647
2648 /* Fill global PRAM */
2649
2650 /* RQPTR */
2651 /* Size varies with number of Rx threads */
2652 ugeth->thread_dat_rx_offset =
2653 qe_muram_alloc(numThreadsRxNumerical *
18a8e864 2654 sizeof(struct ucc_geth_thread_data_rx),
ce973b14 2655 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2656 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
890de95e
LY		 2657 if (netif_msg_ifup(ugeth))
2658 ugeth_err
2659 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
b39d66a8 2660 __func__);
ce973b14
LY		 2661 return -ENOMEM;
2662 }
2663
2664 ugeth->p_thread_data_rx =
6fee40e9 2665 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2666 thread_dat_rx_offset);
2667 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2668
2669 /* typeorlen */
2670 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2671
2672 /* rxrmonbaseptr (statistics) */
2673 if (ug_info->
2674 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2675 ugeth->rx_fw_statistics_pram_offset =
2676 qe_muram_alloc(sizeof
18a8e864 2677 (struct ucc_geth_rx_firmware_statistics_pram),
ce973b14 2678 UCC_GETH_RX_STATISTICS_ALIGNMENT);
4c35630c 2679 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
890de95e
LY		 2680 if (netif_msg_ifup(ugeth))
2681 ugeth_err
2682 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2683 " p_rx_fw_statistics_pram.", __func__);
ce973b14
LY		 2684 return -ENOMEM;
2685 }
2686 ugeth->p_rx_fw_statistics_pram =
6fee40e9 2687 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2688 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2689 /* Zero out p_rx_fw_statistics_pram */
6fee40e9 2690 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
18a8e864 2691 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
ce973b14
LY		 2692 }
2693
2694 /* intCoalescingPtr */
2695
2696 /* Size varies with number of Rx queues */
2697 ugeth->rx_irq_coalescing_tbl_offset =
2698 qe_muram_alloc(ug_info->numQueuesRx *
7563907e
MB		 2699 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2700 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
4c35630c 2701 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
890de95e
LY		 2702 if (netif_msg_ifup(ugeth))
2703 ugeth_err
2704 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2705 " p_rx_irq_coalescing_tbl.", __func__);
ce973b14
LY		 2706 return -ENOMEM;
2707 }
2708
2709 ugeth->p_rx_irq_coalescing_tbl =
6fee40e9 2710 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
ce973b14
LY		 2711 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2712 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2713 ugeth->rx_irq_coalescing_tbl_offset);
2714
2715 /* Fill interrupt coalescing table */
2716 for (i = 0; i < ug_info->numQueuesRx; i++) {
2717 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2718 interruptcoalescingmaxvalue,
2719 ug_info->interruptcoalescingmaxvalue[i]);
2720 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2721 interruptcoalescingcounter,
2722 ug_info->interruptcoalescingmaxvalue[i]);
2723 }
2724
2725 /* MRBLR */
2726 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2727 &ugeth->p_rx_glbl_pram->mrblr);
2728 /* MFLR */
2729 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2730 /* MINFLR */
2731 init_min_frame_len(ug_info->minFrameLength,
2732 &ugeth->p_rx_glbl_pram->minflr,
2733 &ugeth->p_rx_glbl_pram->mrblr);
2734 /* MAXD1 */
2735 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2736 /* MAXD2 */
2737 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2738
2739 /* l2qt */
2740 l2qt = 0;
2741 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2742 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2743 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2744
2745 /* l3qt */
2746 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2747 l3qt = 0;
2748 for (i = 0; i < 8; i++)
2749 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
18a8e864 2750 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
ce973b14
LY		 2751 }
2752
2753 /* vlantype */
2754 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2755
2756 /* vlantci */
2757 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2758
2759 /* ecamptr */
2760 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2761
2762 /* RBDQPTR */
2763 /* Size varies with number of Rx queues */
2764 ugeth->rx_bd_qs_tbl_offset =
2765 qe_muram_alloc(ug_info->numQueuesRx *
18a8e864
LY		 2766 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2767 sizeof(struct ucc_geth_rx_prefetched_bds)),
ce973b14 2768 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
4c35630c 2769 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
890de95e
LY		 2770 if (netif_msg_ifup(ugeth))
2771 ugeth_err
2772 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
b39d66a8 2773 __func__);
ce973b14
LY		 2774 return -ENOMEM;
2775 }
2776
2777 ugeth->p_rx_bd_qs_tbl =
6fee40e9 2778 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2779 rx_bd_qs_tbl_offset);
2780 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2781 /* Zero out p_rx_bd_qs_tbl */
6fee40e9 2782 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
ce973b14 2783 0,
18a8e864
LY		 2784 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2785 sizeof(struct ucc_geth_rx_prefetched_bds)));
ce973b14
LY		 2786
2787 /* Setup the table */
2788 /* Assume BD rings are already established */
2789 for (i = 0; i < ug_info->numQueuesRx; i++) {
2790 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2791 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2792 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2793 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2794 MEM_PART_MURAM) {
2795 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2796 (u32) immrbar_virt_to_phys(ugeth->
2797 p_rx_bd_ring[i]));
2798 }
2799 /* rest of fields handled by QE */
2800 }
2801
2802 /* remoder */
2803 /* Already has speed set */
2804
2805 if (ugeth->rx_extended_features)
2806 remoder |= REMODER_RX_EXTENDED_FEATURES;
2807 if (ug_info->rxExtendedFiltering)
2808 remoder |= REMODER_RX_EXTENDED_FILTERING;
2809 if (ug_info->dynamicMaxFrameLength)
2810 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2811 if (ug_info->dynamicMinFrameLength)
2812 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2813 remoder |=
2814 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2815 remoder |=
2816 ug_info->
2817 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2818 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2819 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2820 if (ug_info->ipCheckSumCheck)
2821 remoder |= REMODER_IP_CHECKSUM_CHECK;
2822 if (ug_info->ipAddressAlignment)
2823 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2824 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2825
2826 /* Note that this function must be called */
2827 /* ONLY AFTER p_tx_fw_statistics_pram */
2828 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2829 init_firmware_statistics_gathering_mode((ug_info->
2830 statisticsMode &
2831 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2832 (ug_info->statisticsMode &
2833 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2834 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2835 ugeth->tx_fw_statistics_pram_offset,
2836 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2837 ugeth->rx_fw_statistics_pram_offset,
2838 &ugeth->p_tx_glbl_pram->temoder,
2839 &ugeth->p_rx_glbl_pram->remoder);
2840
2841 /* function code register */
6fee40e9 2842 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
ce973b14
LY		 2843
2844 /* initialize extended filtering */
2845 if (ug_info->rxExtendedFiltering) {
2846 if (!ug_info->extendedFilteringChainPointer) {
890de95e
LY		 2847 if (netif_msg_ifup(ugeth))
2848 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
b39d66a8 2849 __func__);
ce973b14
LY		 2850 return -EINVAL;
2851 }
2852
2853 /* Allocate memory for extended filtering Mode Global
2854 Parameters */
2855 ugeth->exf_glbl_param_offset =
18a8e864 2856 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
ce973b14 2857 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
4c35630c 2858 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
890de95e
LY		 2859 if (netif_msg_ifup(ugeth))
2860 ugeth_err
2861 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2862 " p_exf_glbl_param.", __func__);
ce973b14
LY		 2863 return -ENOMEM;
2864 }
2865
2866 ugeth->p_exf_glbl_param =
6fee40e9 2867 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2868 exf_glbl_param_offset);
2869 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2870 ugeth->exf_glbl_param_offset);
2871 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2872 (u32) ug_info->extendedFilteringChainPointer);
2873
2874 } else { /* initialize 82xx style address filtering */
2875
2876 /* Init individual address recognition registers to disabled */
2877
2878 for (j = 0; j < NUM_OF_PADDRS; j++)
2879 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2880
ce973b14 2881 p_82xx_addr_filt =
6fee40e9 2882 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 2883 p_rx_glbl_pram->addressfiltering;
2884
2885 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2886 ENET_ADDR_TYPE_GROUP);
2887 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2888 ENET_ADDR_TYPE_INDIVIDUAL);
2889 }
2890
2891 /*
2892 * Initialize UCC at QE level
2893 */
2894
2895 command = QE_INIT_TX_RX;
2896
2897 /* Allocate shadow InitEnet command parameter structure.
2898 * This is needed because after the InitEnet command is executed,
2899 * the structure in DPRAM is released, because DPRAM is a premium
2900 * resource.
2901 * This shadow structure keeps a copy of what was done so that the
2902 * allocated resources can be released when the channel is freed.
2903 */
2904 if (!(ugeth->p_init_enet_param_shadow =
04b588d7 2905 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
890de95e
LY		 2906 if (netif_msg_ifup(ugeth))
2907 ugeth_err
2908 ("%s: Can not allocate memory for"
b39d66a8 2909 " p_UccInitEnetParamShadows.", __func__);
ce973b14
LY		 2910 return -ENOMEM;
2911 }
2912 /* Zero out *p_init_enet_param_shadow */
2913 memset((char *)ugeth->p_init_enet_param_shadow,
18a8e864 2914 0, sizeof(struct ucc_geth_init_pram));
ce973b14
LY		 2915
2916 /* Fill shadow InitEnet command parameter structure */
2917
2918 ugeth->p_init_enet_param_shadow->resinit1 =
2919 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2920 ugeth->p_init_enet_param_shadow->resinit2 =
2921 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2922 ugeth->p_init_enet_param_shadow->resinit3 =
2923 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2924 ugeth->p_init_enet_param_shadow->resinit4 =
2925 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2926 ugeth->p_init_enet_param_shadow->resinit5 =
2927 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2928 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2929 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2930 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2931 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2932
2933 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2934 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2935 if ((ug_info->largestexternallookupkeysize !=
2936 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
2937 && (ug_info->largestexternallookupkeysize !=
2938 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2939 && (ug_info->largestexternallookupkeysize !=
2940 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
890de95e
LY		 2941 if (netif_msg_ifup(ugeth))
2942 ugeth_err("%s: Invalid largest External Lookup Key Size.",
b39d66a8 2943 __func__);
ce973b14
LY		 2944 return -EINVAL;
2945 }
2946 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2947 ug_info->largestexternallookupkeysize;
18a8e864 2948 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 2949 if (ug_info->rxExtendedFiltering) {
2950 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2951 if (ug_info->largestexternallookupkeysize ==
2952 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2953 size +=
2954 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2955 if (ug_info->largestexternallookupkeysize ==
2956 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
2957 size +=
2958 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
2959 }
2960
2961 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
2962 p_init_enet_param_shadow->rxthread[0]),
2963 (u8) (numThreadsRxNumerical + 1)
2964 /* Rx needs one extra for terminator */
2965 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
2966 ug_info->riscRx, 1)) != 0) {
890de95e
LY		 2967 if (netif_msg_ifup(ugeth))
2968 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
b39d66a8 2969 __func__);
ce973b14
LY		 2970 return ret_val;
2971 }
2972
2973 ugeth->p_init_enet_param_shadow->txglobal =
2974 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
2975 if ((ret_val =
2976 fill_init_enet_entries(ugeth,
2977 &(ugeth->p_init_enet_param_shadow->
2978 txthread[0]), numThreadsTxNumerical,
18a8e864 2979 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 2980 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
2981 ug_info->riscTx, 0)) != 0) {
890de95e
LY		 2982 if (netif_msg_ifup(ugeth))
2983 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
b39d66a8 2984 __func__);
ce973b14
LY		 2985 return ret_val;
2986 }
2987
2988 /* Load Rx bds with buffers */
2989 for (i = 0; i < ug_info->numQueuesRx; i++) {
2990 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
890de95e
LY		 2991 if (netif_msg_ifup(ugeth))
2992 ugeth_err("%s: Can not fill Rx bds with buffers.",
b39d66a8 2993 __func__);
ce973b14
LY		 2994 return ret_val;
2995 }
2996 }
2997
2998 /* Allocate InitEnet command parameter structure */
18a8e864 2999 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
4c35630c 3000 if (IS_ERR_VALUE(init_enet_pram_offset)) {
890de95e
LY		 3001 if (netif_msg_ifup(ugeth))
3002 ugeth_err
3003 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
b39d66a8 3004 __func__);
ce973b14
LY		 3005 return -ENOMEM;
3006 }
3007 p_init_enet_pram =
6fee40e9 3008 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
ce973b14
LY		 3009
3010 /* Copy shadow InitEnet command parameter structure into PRAM */
6fee40e9
AF		 3011 out_8(&p_init_enet_pram->resinit1,
3012 ugeth->p_init_enet_param_shadow->resinit1);
3013 out_8(&p_init_enet_pram->resinit2,
3014 ugeth->p_init_enet_param_shadow->resinit2);
3015 out_8(&p_init_enet_pram->resinit3,
3016 ugeth->p_init_enet_param_shadow->resinit3);
3017 out_8(&p_init_enet_pram->resinit4,
3018 ugeth->p_init_enet_param_shadow->resinit4);
ce973b14
LY		 3019 out_be16(&p_init_enet_pram->resinit5,
3020 ugeth->p_init_enet_param_shadow->resinit5);
6fee40e9
AF		 3021 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3022 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
ce973b14
LY		 3023 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3024 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3025 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3026 out_be32(&p_init_enet_pram->rxthread[i],
3027 ugeth->p_init_enet_param_shadow->rxthread[i]);
3028 out_be32(&p_init_enet_pram->txglobal,
3029 ugeth->p_init_enet_param_shadow->txglobal);
3030 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3031 out_be32(&p_init_enet_pram->txthread[i],
3032 ugeth->p_init_enet_param_shadow->txthread[i]);
3033
3034 /* Issue QE command */
3035 cecr_subblock =
3036 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 3037 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 3038 init_enet_pram_offset);
3039
3040 /* Free InitEnet command parameter */
3041 qe_muram_free(init_enet_pram_offset);
3042
3043 return 0;
3044}
3045
ce973b14
LY		 3046/* This is called by the kernel when a frame is ready for transmission. */
3047/* It is pointed to by the dev->hard_start_xmit function pointer */
3048static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3049{
18a8e864 3050 struct ucc_geth_private *ugeth = netdev_priv(dev);
d5b9049d
MR		 3051#ifdef CONFIG_UGETH_TX_ON_DEMAND
3052 struct ucc_fast_private *uccf;
3053#endif
6fee40e9 3054 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3055 u32 bd_status;
3056 u8 txQ = 0;
3057
b39d66a8 3058 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 3059
3060 spin_lock_irq(&ugeth->lock);
3061
09f75cd7 3062 dev->stats.tx_bytes += skb->len;
ce973b14
LY		 3063
3064 /* Start from the next BD that should be filled */
3065 bd = ugeth->txBd[txQ];
6fee40e9 3066 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3067 /* Save the skb pointer so we can free it later */
3068 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3069
3070 /* Update the current skb pointer (wrapping if this was the last) */
3071 ugeth->skb_curtx[txQ] =
3072 (ugeth->skb_curtx[txQ] +
3073 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3074
3075 /* set up the buffer descriptor */
6fee40e9 3076 out_be32(&((struct qe_bd __iomem *)bd)->buf,
da1aa63e 3077 dma_map_single(ugeth->dev, skb->data,
7f80202b 3078 skb->len, DMA_TO_DEVICE));
ce973b14 3079
18a8e864 3080 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
ce973b14
LY		 3081
3082 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3083
18a8e864 3084 /* set bd status and length */
6fee40e9 3085 out_be32((u32 __iomem *)bd, bd_status);
ce973b14
LY		 3086
3087 dev->trans_start = jiffies;
3088
3089 /* Move to next BD in the ring */
3090 if (!(bd_status & T_W))
a394f013 3091 bd += sizeof(struct qe_bd);
ce973b14 3092 else
a394f013 3093 bd = ugeth->p_tx_bd_ring[txQ];
ce973b14
LY		 3094
3095 /* If the next BD still needs to be cleaned up, then the bds
3096 are full. We need to tell the kernel to stop sending us stuff. */
3097 if (bd == ugeth->confBd[txQ]) {
3098 if (!netif_queue_stopped(dev))
3099 netif_stop_queue(dev);
3100 }
3101
a394f013
LY		 3102 ugeth->txBd[txQ] = bd;
3103
ce973b14
LY		 3104 if (ugeth->p_scheduler) {
3105 ugeth->cpucount[txQ]++;
3106 /* Indicate to QE that there are more Tx bds ready for
3107 transmission */
3108 /* This is done by writing a running counter of the bd
3109 count to the scheduler PRAM. */
3110 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3111 }
3112
d5b9049d
MR		 3113#ifdef CONFIG_UGETH_TX_ON_DEMAND
3114 uccf = ugeth->uccf;
3115 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3116#endif
ce973b14
LY		 3117 spin_unlock_irq(&ugeth->lock);
3118
6f6881b8 3119 return 0;
ce973b14
LY		 3120}
3121
18a8e864 3122static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
ce973b14
LY		 3123{
3124 struct sk_buff *skb;
6fee40e9 3125 u8 __iomem *bd;
ce973b14
LY		 3126 u16 length, howmany = 0;
3127 u32 bd_status;
3128 u8 *bdBuffer;
4b8fdefa 3129 struct net_device *dev;
ce973b14 3130
b39d66a8 3131 ugeth_vdbg("%s: IN", __func__);
ce973b14 3132
da1aa63e 3133 dev = ugeth->ndev;
88a15f2e 3134
ce973b14
LY		 3135 /* collect received buffers */
3136 bd = ugeth->rxBd[rxQ];
3137
6fee40e9 3138 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3139
3140 /* while there are received buffers and BD is full (~R_E) */
3141 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
6fee40e9 3142 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
ce973b14
LY		 3143 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3144 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3145
3146 /* determine whether buffer is first, last, first and last
3147 (single buffer frame) or middle (not first and not last) */
3148 if (!skb ||
3149 (!(bd_status & (R_F | R_L))) ||
3150 (bd_status & R_ERRORS_FATAL)) {
890de95e
LY		 3151 if (netif_msg_rx_err(ugeth))
3152 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
b39d66a8 3153 __func__, __LINE__, (u32) skb);
ce973b14
LY		 3154 if (skb)
3155 dev_kfree_skb_any(skb);
3156
3157 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
09f75cd7 3158 dev->stats.rx_dropped++;
ce973b14 3159 } else {
09f75cd7 3160 dev->stats.rx_packets++;
ce973b14
LY		 3161 howmany++;
3162
3163 /* Prep the skb for the packet */
3164 skb_put(skb, length);
3165
3166 /* Tell the skb what kind of packet this is */
da1aa63e 3167 skb->protocol = eth_type_trans(skb, ugeth->ndev);
ce973b14 3168
09f75cd7 3169 dev->stats.rx_bytes += length;
ce973b14 3170 /* Send the packet up the stack */
ce973b14 3171 netif_receive_skb(skb);
ce973b14
LY		 3172 }
3173
ce973b14
LY		 3174 skb = get_new_skb(ugeth, bd);
3175 if (!skb) {
890de95e 3176 if (netif_msg_rx_err(ugeth))
b39d66a8 3177 ugeth_warn("%s: No Rx Data Buffer", __func__);
09f75cd7 3178 dev->stats.rx_dropped++;
ce973b14
LY		 3179 break;
3180 }
3181
3182 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3183
3184 /* update to point at the next skb */
3185 ugeth->skb_currx[rxQ] =
3186 (ugeth->skb_currx[rxQ] +
3187 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3188
3189 if (bd_status & R_W)
3190 bd = ugeth->p_rx_bd_ring[rxQ];
3191 else
18a8e864 3192 bd += sizeof(struct qe_bd);
ce973b14 3193
6fee40e9 3194 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3195 }
3196
3197 ugeth->rxBd[rxQ] = bd;
ce973b14
LY		 3198 return howmany;
3199}
3200
3201static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3202{
3203 /* Start from the next BD that should be filled */
18a8e864 3204 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9 3205 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3206 u32 bd_status;
3207
3208 bd = ugeth->confBd[txQ];
6fee40e9 3209 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3210
3211 /* Normal processing. */
3212 while ((bd_status & T_R) == 0) {
3213 /* BD contains already transmitted buffer. */
3214 /* Handle the transmitted buffer and release */
3215 /* the BD to be used with the current frame */
3216
a394f013 3217 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
ce973b14
LY		 3218 break;
3219
09f75cd7 3220 dev->stats.tx_packets++;
ce973b14
LY		 3221
3222 /* Free the sk buffer associated with this TxBD */
0cededf3 3223 dev_kfree_skb(ugeth->
ce973b14
LY		 3224 tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3225 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3226 ugeth->skb_dirtytx[txQ] =
3227 (ugeth->skb_dirtytx[txQ] +
3228 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3229
3230 /* We freed a buffer, so now we can restart transmission */
3231 if (netif_queue_stopped(dev))
3232 netif_wake_queue(dev);
3233
3234 /* Advance the confirmation BD pointer */
3235 if (!(bd_status & T_W))
a394f013 3236 bd += sizeof(struct qe_bd);
ce973b14 3237 else
a394f013 3238 bd = ugeth->p_tx_bd_ring[txQ];
6fee40e9 3239 bd_status = in_be32((u32 __iomem *)bd);
ce973b14 3240 }
a394f013 3241 ugeth->confBd[txQ] = bd;
ce973b14
LY		 3242 return 0;
3243}
3244
bea3348e 3245static int ucc_geth_poll(struct napi_struct *napi, int budget)
ce973b14 3246{
bea3348e 3247 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
702ff12c 3248 struct ucc_geth_info *ug_info;
bea3348e 3249 int howmany, i;
ce973b14 3250
702ff12c
MR		 3251 ug_info = ugeth->ug_info;
3252
702ff12c 3253 howmany = 0;
bea3348e
SH		 3254 for (i = 0; i < ug_info->numQueuesRx; i++)
3255 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
702ff12c 3256
0cededf3
JT		 3257 /* Tx event processing */
3258 spin_lock(&ugeth->lock);
3259 for (i = 0; i < ug_info->numQueuesTx; i++)
3260 ucc_geth_tx(ugeth->ndev, i);
3261 spin_unlock(&ugeth->lock);
3262
bea3348e 3263 if (howmany < budget) {
288379f0 3264 napi_complete(napi);
0cededf3 3265 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
702ff12c 3266 }
ce973b14 3267
bea3348e 3268 return howmany;
ce973b14 3269}
ce973b14 3270
7d12e780 3271static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
ce973b14 3272{
06efcad0 3273 struct net_device *dev = info;
18a8e864
LY		 3274 struct ucc_geth_private *ugeth = netdev_priv(dev);
3275 struct ucc_fast_private *uccf;
3276 struct ucc_geth_info *ug_info;
702ff12c
MR		 3277 register u32 ucce;
3278 register u32 uccm;
ce973b14 3279
b39d66a8 3280 ugeth_vdbg("%s: IN", __func__);
ce973b14 3281
ce973b14
LY		 3282 uccf = ugeth->uccf;
3283 ug_info = ugeth->ug_info;
3284
702ff12c
MR		 3285 /* read and clear events */
3286 ucce = (u32) in_be32(uccf->p_ucce);
3287 uccm = (u32) in_be32(uccf->p_uccm);
3288 ucce &= uccm;
3289 out_be32(uccf->p_ucce, ucce);
ce973b14 3290
702ff12c 3291 /* check for receive events that require processing */
0cededf3 3292 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
288379f0 3293 if (napi_schedule_prep(&ugeth->napi)) {
0cededf3 3294 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
702ff12c 3295 out_be32(uccf->p_uccm, uccm);
288379f0 3296 __napi_schedule(&ugeth->napi);
702ff12c 3297 }
702ff12c 3298 }
ce973b14 3299
702ff12c
MR		 3300 /* Errors and other events */
3301 if (ucce & UCCE_OTHER) {
3bc53427 3302 if (ucce & UCC_GETH_UCCE_BSY)
09f75cd7 3303 dev->stats.rx_errors++;
3bc53427 3304 if (ucce & UCC_GETH_UCCE_TXE)
09f75cd7 3305 dev->stats.tx_errors++;
ce973b14 3306 }
ce973b14
LY		 3307
3308 return IRQ_HANDLED;
3309}
3310
26d29ea7
AV		 3311#ifdef CONFIG_NET_POLL_CONTROLLER
3312/*
3313 * Polling 'interrupt' - used by things like netconsole to send skbs
3314 * without having to re-enable interrupts. It's not called while
3315 * the interrupt routine is executing.
3316 */
3317static void ucc_netpoll(struct net_device *dev)
3318{
3319 struct ucc_geth_private *ugeth = netdev_priv(dev);
3320 int irq = ugeth->ug_info->uf_info.irq;
3321
3322 disable_irq(irq);
3323 ucc_geth_irq_handler(irq, dev);
3324 enable_irq(irq);
3325}
3326#endif /* CONFIG_NET_POLL_CONTROLLER */
3327
3d6593e9
KH		 3328static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3329{
3330 struct ucc_geth_private *ugeth = netdev_priv(dev);
3331 struct sockaddr *addr = p;
3332
3333 if (!is_valid_ether_addr(addr->sa_data))
3334 return -EADDRNOTAVAIL;
3335
3336 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3337
3338 /*
3339 * If device is not running, we will set mac addr register
3340 * when opening the device.
3341 */
3342 if (!netif_running(dev))
3343 return 0;
3344
3345 spin_lock_irq(&ugeth->lock);
3346 init_mac_station_addr_regs(dev->dev_addr[0],
3347 dev->dev_addr[1],
3348 dev->dev_addr[2],
3349 dev->dev_addr[3],
3350 dev->dev_addr[4],
3351 dev->dev_addr[5],
3352 &ugeth->ug_regs->macstnaddr1,
3353 &ugeth->ug_regs->macstnaddr2);
3354 spin_unlock_irq(&ugeth->lock);
3355
3356 return 0;
3357}
3358
ce973b14
LY		 3359/* Called when something needs to use the ethernet device */
3360/* Returns 0 for success. */
3361static int ucc_geth_open(struct net_device *dev)
3362{
18a8e864 3363 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14
LY		 3364 int err;
3365
b39d66a8 3366 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 3367
3368 /* Test station address */
3369 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
890de95e
LY		 3370 if (netif_msg_ifup(ugeth))
3371 ugeth_err("%s: Multicast address used for station address"
b39d66a8 3372 " - is this what you wanted?", __func__);
ce973b14
LY		 3373 return -EINVAL;
3374 }
3375
79675900
AV		 3376 err = init_phy(dev);
3377 if (err) {
3378 if (netif_msg_ifup(ugeth))
3379 ugeth_err("%s: Cannot initialize PHY, aborting.",
3380 dev->name);
3381 return err;
3382 }
3383
728de4c9
KP		 3384 err = ucc_struct_init(ugeth);
3385 if (err) {
890de95e
LY		 3386 if (netif_msg_ifup(ugeth))
3387 ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
3e73fc9a 3388 goto out_err_stop;
728de4c9
KP		 3389 }
3390
bea3348e 3391 napi_enable(&ugeth->napi);
1a342d22 3392
ce973b14
LY		 3393 err = ucc_geth_startup(ugeth);
3394 if (err) {
890de95e
LY		 3395 if (netif_msg_ifup(ugeth))
3396 ugeth_err("%s: Cannot configure net device, aborting.",
3397 dev->name);
bea3348e 3398 goto out_err;
ce973b14
LY		 3399 }
3400
3401 err = adjust_enet_interface(ugeth);
3402 if (err) {
890de95e
LY		 3403 if (netif_msg_ifup(ugeth))
3404 ugeth_err("%s: Cannot configure net device, aborting.",
3405 dev->name);
bea3348e 3406 goto out_err;
ce973b14
LY		 3407 }
3408
3409 /* Set MACSTNADDR1, MACSTNADDR2 */
3410 /* For more details see the hardware spec. */
3411 init_mac_station_addr_regs(dev->dev_addr[0],
3412 dev->dev_addr[1],
3413 dev->dev_addr[2],
3414 dev->dev_addr[3],
3415 dev->dev_addr[4],
3416 dev->dev_addr[5],
3417 &ugeth->ug_regs->macstnaddr1,
3418 &ugeth->ug_regs->macstnaddr2);
3419
728de4c9
KP		 3420 phy_start(ugeth->phydev);
3421
67c2fb8f 3422 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
ce973b14 3423 if (err) {
890de95e 3424 if (netif_msg_ifup(ugeth))
67c2fb8f 3425 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
bea3348e 3426 goto out_err;
ce973b14 3427 }
ce973b14 3428
67c2fb8f
AV		 3429 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3430 0, "UCC Geth", dev);
ce973b14 3431 if (err) {
890de95e 3432 if (netif_msg_ifup(ugeth))
67c2fb8f
AV		 3433 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3434 dev->name);
bea3348e 3435 goto out_err;
ce973b14
LY		 3436 }
3437
3438 netif_start_queue(dev);
3439
3440 return err;
bea3348e
SH		 3441
3442out_err:
bea3348e 3443 napi_disable(&ugeth->napi);
3e73fc9a 3444out_err_stop:
ba574696 3445 ucc_geth_stop(ugeth);
bea3348e 3446 return err;
ce973b14
LY		 3447}
3448
3449/* Stops the kernel queue, and halts the controller */
3450static int ucc_geth_close(struct net_device *dev)
3451{
18a8e864 3452 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14 3453
b39d66a8 3454 ugeth_vdbg("%s: IN", __func__);
ce973b14 3455
bea3348e 3456 napi_disable(&ugeth->napi);
bea3348e 3457
ce973b14
LY		 3458 ucc_geth_stop(ugeth);
3459
da1aa63e 3460 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
67c2fb8f 3461
ce973b14
LY		 3462 netif_stop_queue(dev);
3463
3464 return 0;
3465}
3466
fdb614c2
AV		 3467/* Reopen device. This will reset the MAC and PHY. */
3468static void ucc_geth_timeout_work(struct work_struct *work)
3469{
3470 struct ucc_geth_private *ugeth;
3471 struct net_device *dev;
3472
3473 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
da1aa63e 3474 dev = ugeth->ndev;
fdb614c2
AV		 3475
3476 ugeth_vdbg("%s: IN", __func__);
3477
3478 dev->stats.tx_errors++;
3479
3480 ugeth_dump_regs(ugeth);
3481
3482 if (dev->flags & IFF_UP) {
3483 /*
3484 * Must reset MAC *and* PHY. This is done by reopening
3485 * the device.
3486 */
3487 ucc_geth_close(dev);
3488 ucc_geth_open(dev);
3489 }
3490
3491 netif_tx_schedule_all(dev);
3492}
3493
3494/*
3495 * ucc_geth_timeout gets called when a packet has not been
3496 * transmitted after a set amount of time.
3497 */
3498static void ucc_geth_timeout(struct net_device *dev)
3499{
3500 struct ucc_geth_private *ugeth = netdev_priv(dev);
3501
3502 netif_carrier_off(dev);
3503 schedule_work(&ugeth->timeout_work);
3504}
3505
4e19b5c1 3506static phy_interface_t to_phy_interface(const char *phy_connection_type)
728de4c9 3507{
4e19b5c1 3508 if (strcasecmp(phy_connection_type, "mii") == 0)
728de4c9 3509 return PHY_INTERFACE_MODE_MII;
4e19b5c1 3510 if (strcasecmp(phy_connection_type, "gmii") == 0)
728de4c9 3511 return PHY_INTERFACE_MODE_GMII;
4e19b5c1 3512 if (strcasecmp(phy_connection_type, "tbi") == 0)
728de4c9 3513 return PHY_INTERFACE_MODE_TBI;
4e19b5c1 3514 if (strcasecmp(phy_connection_type, "rmii") == 0)
728de4c9 3515 return PHY_INTERFACE_MODE_RMII;
4e19b5c1 3516 if (strcasecmp(phy_connection_type, "rgmii") == 0)
728de4c9 3517 return PHY_INTERFACE_MODE_RGMII;
4e19b5c1 3518 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
728de4c9 3519 return PHY_INTERFACE_MODE_RGMII_ID;
bd0ceaab
KP		 3520 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3521 return PHY_INTERFACE_MODE_RGMII_TXID;
3522 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3523 return PHY_INTERFACE_MODE_RGMII_RXID;
4e19b5c1 3524 if (strcasecmp(phy_connection_type, "rtbi") == 0)
728de4c9
KP		 3525 return PHY_INTERFACE_MODE_RTBI;
3526
3527 return PHY_INTERFACE_MODE_MII;
3528}
3529
a9dbae78
JT		 3530static const struct net_device_ops ucc_geth_netdev_ops = {
3531 .ndo_open = ucc_geth_open,
3532 .ndo_stop = ucc_geth_close,
3533 .ndo_start_xmit = ucc_geth_start_xmit,
3534 .ndo_validate_addr = eth_validate_addr,
3d6593e9 3535 .ndo_set_mac_address = ucc_geth_set_mac_addr,
a9dbae78
JT		 3536 .ndo_change_mtu = eth_change_mtu,
3537 .ndo_set_multicast_list = ucc_geth_set_multi,
3538 .ndo_tx_timeout = ucc_geth_timeout,
3539#ifdef CONFIG_NET_POLL_CONTROLLER
3540 .ndo_poll_controller = ucc_netpoll,
3541#endif
3542};
3543
18a8e864 3544static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
ce973b14 3545{
18a8e864
LY		 3546 struct device *device = &ofdev->dev;
3547 struct device_node *np = ofdev->node;
ce973b14
LY		 3548 struct net_device *dev = NULL;
3549 struct ucc_geth_private *ugeth = NULL;
3550 struct ucc_geth_info *ug_info;
18a8e864
LY		 3551 struct resource res;
3552 struct device_node *phy;
728de4c9 3553 int err, ucc_num, max_speed = 0;
3d137fdd 3554 const u32 *fixed_link;
18a8e864 3555 const unsigned int *prop;
9fb1e350 3556 const char *sprop;
9b4c7a4e 3557 const void *mac_addr;
728de4c9
KP		 3558 phy_interface_t phy_interface;
3559 static const int enet_to_speed[] = {
3560 SPEED_10, SPEED_10, SPEED_10,
3561 SPEED_100, SPEED_100, SPEED_100,
3562 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3563 };
3564 static const phy_interface_t enet_to_phy_interface[] = {
3565 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3566 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3567 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3568 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3569 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3570 };
ce973b14 3571
b39d66a8 3572 ugeth_vdbg("%s: IN", __func__);
ce973b14 3573
56626f33
AV		 3574 prop = of_get_property(np, "cell-index", NULL);
3575 if (!prop) {
3576 prop = of_get_property(np, "device-id", NULL);
3577 if (!prop)
3578 return -ENODEV;
3579 }
3580
18a8e864
LY		 3581 ucc_num = *prop - 1;
3582 if ((ucc_num < 0) || (ucc_num > 7))
3583 return -ENODEV;
3584
3585 ug_info = &ugeth_info[ucc_num];
890de95e
LY		 3586 if (ug_info == NULL) {
3587 if (netif_msg_probe(&debug))
3588 ugeth_err("%s: [%d] Missing additional data!",
b39d66a8 3589 __func__, ucc_num);
890de95e
LY		 3590 return -ENODEV;
3591 }
3592
18a8e864 3593 ug_info->uf_info.ucc_num = ucc_num;
728de4c9 3594
9fb1e350
TT		 3595 sprop = of_get_property(np, "rx-clock-name", NULL);
3596 if (sprop) {
3597 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3598 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3599 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3600 printk(KERN_ERR
3601 "ucc_geth: invalid rx-clock-name property\n");
3602 return -EINVAL;
3603 }
3604 } else {
3605 prop = of_get_property(np, "rx-clock", NULL);
3606 if (!prop) {
3607 /* If both rx-clock-name and rx-clock are missing,
3608 we want to tell people to use rx-clock-name. */
3609 printk(KERN_ERR
3610 "ucc_geth: missing rx-clock-name property\n");
3611 return -EINVAL;
3612 }
3613 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3614 printk(KERN_ERR
3615 "ucc_geth: invalid rx-clock propperty\n");
3616 return -EINVAL;
3617 }
3618 ug_info->uf_info.rx_clock = *prop;
3619 }
3620
3621 sprop = of_get_property(np, "tx-clock-name", NULL);
3622 if (sprop) {
3623 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3624 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3625 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3626 printk(KERN_ERR
3627 "ucc_geth: invalid tx-clock-name property\n");
3628 return -EINVAL;
3629 }
3630 } else {
e410553f 3631 prop = of_get_property(np, "tx-clock", NULL);
9fb1e350
TT		 3632 if (!prop) {
3633 printk(KERN_ERR
3634 "ucc_geth: mising tx-clock-name property\n");
3635 return -EINVAL;
3636 }
3637 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3638 printk(KERN_ERR
3639 "ucc_geth: invalid tx-clock property\n");
3640 return -EINVAL;
3641 }
3642 ug_info->uf_info.tx_clock = *prop;
3643 }
3644
18a8e864
LY		 3645 err = of_address_to_resource(np, 0, &res);
3646 if (err)
3647 return -EINVAL;
3648
3649 ug_info->uf_info.regs = res.start;
3650 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3d137fdd
JT		 3651 fixed_link = of_get_property(np, "fixed-link", NULL);
3652 if (fixed_link) {
3d137fdd
JT		 3653 phy = NULL;
3654 } else {
0b9da337 3655 phy = of_parse_phandle(np, "phy-handle", 0);
3d137fdd
JT		 3656 if (phy == NULL)
3657 return -ENODEV;
3d137fdd 3658 }
0b9da337 3659 ug_info->phy_node = phy;
728de4c9
KP		 3660
3661 /* get the phy interface type, or default to MII */
4e19b5c1 3662 prop = of_get_property(np, "phy-connection-type", NULL);
728de4c9
KP		 3663 if (!prop) {
3664 /* handle interface property present in old trees */
40cd3a45 3665 prop = of_get_property(phy, "interface", NULL);
4e19b5c1 3666 if (prop != NULL) {
728de4c9 3667 phy_interface = enet_to_phy_interface[*prop];
4e19b5c1
KP		 3668 max_speed = enet_to_speed[*prop];
3669 } else
728de4c9
KP		 3670 phy_interface = PHY_INTERFACE_MODE_MII;
3671 } else {
3672 phy_interface = to_phy_interface((const char *)prop);
3673 }
3674
4e19b5c1
KP		 3675 /* get speed, or derive from PHY interface */
3676 if (max_speed == 0)
728de4c9
KP		 3677 switch (phy_interface) {
3678 case PHY_INTERFACE_MODE_GMII:
3679 case PHY_INTERFACE_MODE_RGMII:
3680 case PHY_INTERFACE_MODE_RGMII_ID:
bd0ceaab
KP		 3681 case PHY_INTERFACE_MODE_RGMII_RXID:
3682 case PHY_INTERFACE_MODE_RGMII_TXID:
728de4c9
KP		 3683 case PHY_INTERFACE_MODE_TBI:
3684 case PHY_INTERFACE_MODE_RTBI:
3685 max_speed = SPEED_1000;
3686 break;
3687 default:
3688 max_speed = SPEED_100;
3689 break;
3690 }
728de4c9
KP		 3691
3692 if (max_speed == SPEED_1000) {
4e19b5c1 3693 /* configure muram FIFOs for gigabit operation */
728de4c9
KP		 3694 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3695 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3696 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3697 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3698 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3699 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
ffea31ed
JT		 3700 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3701 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
728de4c9
KP		 3702 }
3703
890de95e
LY		 3704 if (netif_msg_probe(&debug))
3705 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3706 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3707 ug_info->uf_info.irq);
ce973b14 3708
ce973b14
LY		 3709 /* Create an ethernet device instance */
3710 dev = alloc_etherdev(sizeof(*ugeth));
3711
3712 if (dev == NULL)
3713 return -ENOMEM;
3714
3715 ugeth = netdev_priv(dev);
3716 spin_lock_init(&ugeth->lock);
3717
80a9fad8
AV		 3718 /* Create CQs for hash tables */
3719 INIT_LIST_HEAD(&ugeth->group_hash_q);
3720 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3721
ce973b14
LY		 3722 dev_set_drvdata(device, dev);
3723
3724 /* Set the dev->base_addr to the gfar reg region */
3725 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3726
ce973b14
LY		 3727 SET_NETDEV_DEV(dev, device);
3728
3729 /* Fill in the dev structure */
ac421852 3730 uec_set_ethtool_ops(dev);
a9dbae78 3731 dev->netdev_ops = &ucc_geth_netdev_ops;
ce973b14 3732 dev->watchdog_timeo = TX_TIMEOUT;
1762a29a 3733 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
0cededf3 3734 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
ce973b14 3735 dev->mtu = 1500;
ce973b14 3736
890de95e 3737 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
728de4c9
KP		 3738 ugeth->phy_interface = phy_interface;
3739 ugeth->max_speed = max_speed;
3740
ce973b14
LY		 3741 err = register_netdev(dev);
3742 if (err) {
890de95e
LY		 3743 if (netif_msg_probe(ugeth))
3744 ugeth_err("%s: Cannot register net device, aborting.",
3745 dev->name);
ce973b14
LY		 3746 free_netdev(dev);
3747 return err;
3748 }
3749
e9eb70c9 3750 mac_addr = of_get_mac_address(np);
9b4c7a4e
LY		 3751 if (mac_addr)
3752 memcpy(dev->dev_addr, mac_addr, 6);
ce973b14 3753
728de4c9 3754 ugeth->ug_info = ug_info;
da1aa63e
AV		 3755 ugeth->dev = device;
3756 ugeth->ndev = dev;
b1c4a9dd 3757 ugeth->node = np;
728de4c9 3758
ce973b14
LY		 3759 return 0;
3760}
3761
18a8e864 3762static int ucc_geth_remove(struct of_device* ofdev)
ce973b14 3763{
18a8e864 3764 struct device *device = &ofdev->dev;
ce973b14
LY		 3765 struct net_device *dev = dev_get_drvdata(device);
3766 struct ucc_geth_private *ugeth = netdev_priv(dev);
3767
80a9fad8 3768 unregister_netdev(dev);
ce973b14 3769 free_netdev(dev);
80a9fad8
AV		 3770 ucc_geth_memclean(ugeth);
3771 dev_set_drvdata(device, NULL);
ce973b14
LY		 3772
3773 return 0;
3774}
3775
18a8e864
LY		 3776static struct of_device_id ucc_geth_match[] = {
3777 {
3778 .type = "network",
3779 .compatible = "ucc_geth",
3780 },
3781 {},
3782};
3783
3784MODULE_DEVICE_TABLE(of, ucc_geth_match);
3785
3786static struct of_platform_driver ucc_geth_driver = {
3787 .name = DRV_NAME,
3788 .match_table = ucc_geth_match,
3789 .probe = ucc_geth_probe,
3790 .remove = ucc_geth_remove,
ce973b14
LY		 3791};
3792
3793static int __init ucc_geth_init(void)
3794{
728de4c9
KP		 3795 int i, ret;
3796
890de95e
LY		 3797 if (netif_msg_drv(&debug))
3798 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
ce973b14
LY		 3799 for (i = 0; i < 8; i++)
3800 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3801 sizeof(ugeth_primary_info));
3802
728de4c9
KP		 3803 ret = of_register_platform_driver(&ucc_geth_driver);
3804
728de4c9 3805 return ret;
ce973b14
LY		 3806}
3807
3808static void __exit ucc_geth_exit(void)
3809{
a4f0c2ca 3810 of_unregister_platform_driver(&ucc_geth_driver);
ce973b14
LY		 3811}
3812
3813module_init(ucc_geth_init);
3814module_exit(ucc_geth_exit);
3815
3816MODULE_AUTHOR("Freescale Semiconductor, Inc");
3817MODULE_DESCRIPTION(DRV_DESC);
c2bcf00b 3818MODULE_VERSION(DRV_VERSION);
ce973b14 3819MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)