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ucc_geth: Fix interrupt coalescing size and alignment
[linux-2.6-block.git] / drivers / net / ucc_geth.c
CommitLineData
ce973b14
LY		 1/*
2 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
18a8e864 5 * Li Yang <leoli@freescale.com>
ce973b14
LY		 6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
ce973b14
LY		 10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/slab.h>
19#include <linux/stddef.h>
20#include <linux/interrupt.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/spinlock.h>
25#include <linux/mm.h>
26#include <linux/ethtool.h>
27#include <linux/delay.h>
28#include <linux/dma-mapping.h>
29#include <linux/fsl_devices.h>
30#include <linux/ethtool.h>
ce973b14 31#include <linux/mii.h>
728de4c9 32#include <linux/phy.h>
df19b6b0 33#include <linux/workqueue.h>
ce973b14 34
a4f0c2ca 35#include <asm/of_platform.h>
ce973b14
LY		 36#include <asm/uaccess.h>
37#include <asm/irq.h>
38#include <asm/io.h>
39#include <asm/immap_qe.h>
40#include <asm/qe.h>
41#include <asm/ucc.h>
42#include <asm/ucc_fast.h>
43
44#include "ucc_geth.h"
728de4c9 45#include "ucc_geth_mii.h"
ce973b14
LY		 46
47#undef DEBUG
48
d5b20697 49#define DRV_DESC "QE UCC Gigabit Ethernet Controller version:Sept 11, 2006"
ce973b14
LY		 50#define DRV_NAME "ucc_geth"
51
52#define ugeth_printk(level, format, arg...) \
53 printk(level format "\n", ## arg)
54
55#define ugeth_dbg(format, arg...) \
56 ugeth_printk(KERN_DEBUG , format , ## arg)
57#define ugeth_err(format, arg...) \
58 ugeth_printk(KERN_ERR , format , ## arg)
59#define ugeth_info(format, arg...) \
60 ugeth_printk(KERN_INFO , format , ## arg)
61#define ugeth_warn(format, arg...) \
62 ugeth_printk(KERN_WARNING , format , ## arg)
63
64#ifdef UGETH_VERBOSE_DEBUG
65#define ugeth_vdbg ugeth_dbg
66#else
67#define ugeth_vdbg(fmt, args...) do { } while (0)
68#endif /* UGETH_VERBOSE_DEBUG */
69
70static DEFINE_SPINLOCK(ugeth_lock);
71
18a8e864 72static struct ucc_geth_info ugeth_primary_info = {
ce973b14
LY		 73 .uf_info = {
74 .bd_mem_part = MEM_PART_SYSTEM,
75 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
76 .max_rx_buf_length = 1536,
728de4c9 77 /* adjusted at startup if max-speed 1000 */
ce973b14
LY		 78 .urfs = UCC_GETH_URFS_INIT,
79 .urfet = UCC_GETH_URFET_INIT,
80 .urfset = UCC_GETH_URFSET_INIT,
81 .utfs = UCC_GETH_UTFS_INIT,
82 .utfet = UCC_GETH_UTFET_INIT,
83 .utftt = UCC_GETH_UTFTT_INIT,
ce973b14
LY		 84 .ufpt = 256,
85 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
86 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
87 .tenc = UCC_FAST_TX_ENCODING_NRZ,
88 .renc = UCC_FAST_RX_ENCODING_NRZ,
89 .tcrc = UCC_FAST_16_BIT_CRC,
90 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
91 },
92 .numQueuesTx = 1,
93 .numQueuesRx = 1,
94 .extendedFilteringChainPointer = ((uint32_t) NULL),
95 .typeorlen = 3072 /*1536 */ ,
96 .nonBackToBackIfgPart1 = 0x40,
97 .nonBackToBackIfgPart2 = 0x60,
98 .miminumInterFrameGapEnforcement = 0x50,
99 .backToBackInterFrameGap = 0x60,
100 .mblinterval = 128,
101 .nortsrbytetime = 5,
102 .fracsiz = 1,
103 .strictpriorityq = 0xff,
104 .altBebTruncation = 0xa,
105 .excessDefer = 1,
106 .maxRetransmission = 0xf,
107 .collisionWindow = 0x37,
108 .receiveFlowControl = 1,
109 .maxGroupAddrInHash = 4,
110 .maxIndAddrInHash = 4,
111 .prel = 7,
112 .maxFrameLength = 1518,
113 .minFrameLength = 64,
114 .maxD1Length = 1520,
115 .maxD2Length = 1520,
116 .vlantype = 0x8100,
117 .ecamptr = ((uint32_t) NULL),
118 .eventRegMask = UCCE_OTHER,
119 .pausePeriod = 0xf000,
120 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
121 .bdRingLenTx = {
122 TX_BD_RING_LEN,
123 TX_BD_RING_LEN,
124 TX_BD_RING_LEN,
125 TX_BD_RING_LEN,
126 TX_BD_RING_LEN,
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN},
130
131 .bdRingLenRx = {
132 RX_BD_RING_LEN,
133 RX_BD_RING_LEN,
134 RX_BD_RING_LEN,
135 RX_BD_RING_LEN,
136 RX_BD_RING_LEN,
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN},
140
141 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
142 .largestexternallookupkeysize =
143 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
144 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_NONE,
145 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
146 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
147 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
148 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
149 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
150 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_4,
151 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_4,
152 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
153 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
154};
155
18a8e864 156static struct ucc_geth_info ugeth_info[8];
ce973b14
LY		 157
158#ifdef DEBUG
159static void mem_disp(u8 *addr, int size)
160{
161 u8 *i;
162 int size16Aling = (size >> 4) << 4;
163 int size4Aling = (size >> 2) << 2;
164 int notAlign = 0;
165 if (size % 16)
166 notAlign = 1;
167
168 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
169 printk("0x%08x: %08x %08x %08x %08x\r\n",
170 (u32) i,
171 *((u32 *) (i)),
172 *((u32 *) (i + 4)),
173 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
174 if (notAlign == 1)
175 printk("0x%08x: ", (u32) i);
176 for (; (u32) i < (u32) addr + size4Aling; i += 4)
177 printk("%08x ", *((u32 *) (i)));
178 for (; (u32) i < (u32) addr + size; i++)
179 printk("%02x", *((u8 *) (i)));
180 if (notAlign == 1)
181 printk("\r\n");
182}
183#endif /* DEBUG */
184
185#ifdef CONFIG_UGETH_FILTERING
186static void enqueue(struct list_head *node, struct list_head *lh)
187{
188 unsigned long flags;
189
1083cfe1 190 spin_lock_irqsave(&ugeth_lock, flags);
ce973b14 191 list_add_tail(node, lh);
1083cfe1 192 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 193}
194#endif /* CONFIG_UGETH_FILTERING */
195
196static struct list_head *dequeue(struct list_head *lh)
197{
198 unsigned long flags;
199
1083cfe1 200 spin_lock_irqsave(&ugeth_lock, flags);
ce973b14
LY		 201 if (!list_empty(lh)) {
202 struct list_head *node = lh->next;
203 list_del(node);
1083cfe1 204 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 205 return node;
206 } else {
1083cfe1 207 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 208 return NULL;
209 }
210}
211
18a8e864 212static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, u8 *bd)
ce973b14
LY		 213{
214 struct sk_buff *skb = NULL;
215
216 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
217 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
218
219 if (skb == NULL)
220 return NULL;
221
222 /* We need the data buffer to be aligned properly. We will reserve
223 * as many bytes as needed to align the data properly
224 */
225 skb_reserve(skb,
226 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
227 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
228 1)));
229
230 skb->dev = ugeth->dev;
231
18a8e864 232 out_be32(&((struct qe_bd *)bd)->buf,
ce973b14
LY		 233 dma_map_single(NULL,
234 skb->data,
235 ugeth->ug_info->uf_info.max_rx_buf_length +
236 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
237 DMA_FROM_DEVICE));
238
18a8e864 239 out_be32((u32 *)bd, (R_E | R_I | (in_be32((u32 *)bd) & R_W)));
ce973b14
LY		 240
241 return skb;
242}
243
18a8e864 244static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
ce973b14
LY		 245{
246 u8 *bd;
247 u32 bd_status;
248 struct sk_buff *skb;
249 int i;
250
251 bd = ugeth->p_rx_bd_ring[rxQ];
252 i = 0;
253
254 do {
18a8e864 255 bd_status = in_be32((u32*)bd);
ce973b14
LY		 256 skb = get_new_skb(ugeth, bd);
257
258 if (!skb) /* If can not allocate data buffer,
259 abort. Cleanup will be elsewhere */
260 return -ENOMEM;
261
262 ugeth->rx_skbuff[rxQ][i] = skb;
263
264 /* advance the BD pointer */
18a8e864 265 bd += sizeof(struct qe_bd);
ce973b14
LY		 266 i++;
267 } while (!(bd_status & R_W));
268
269 return 0;
270}
271
18a8e864 272static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
ce973b14
LY		 273 volatile u32 *p_start,
274 u8 num_entries,
275 u32 thread_size,
276 u32 thread_alignment,
18a8e864 277 enum qe_risc_allocation risc,
ce973b14
LY		 278 int skip_page_for_first_entry)
279{
280 u32 init_enet_offset;
281 u8 i;
282 int snum;
283
284 for (i = 0; i < num_entries; i++) {
285 if ((snum = qe_get_snum()) < 0) {
286 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
287 return snum;
288 }
289 if ((i == 0) && skip_page_for_first_entry)
290 /* First entry of Rx does not have page */
291 init_enet_offset = 0;
292 else {
293 init_enet_offset =
294 qe_muram_alloc(thread_size, thread_alignment);
295 if (IS_MURAM_ERR(init_enet_offset)) {
296 ugeth_err
297 ("fill_init_enet_entries: Can not allocate DPRAM memory.");
298 qe_put_snum((u8) snum);
299 return -ENOMEM;
300 }
301 }
302 *(p_start++) =
303 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
304 | risc;
305 }
306
307 return 0;
308}
309
18a8e864 310static int return_init_enet_entries(struct ucc_geth_private *ugeth,
ce973b14
LY		 311 volatile u32 *p_start,
312 u8 num_entries,
18a8e864 313 enum qe_risc_allocation risc,
ce973b14
LY		 314 int skip_page_for_first_entry)
315{
316 u32 init_enet_offset;
317 u8 i;
318 int snum;
319
320 for (i = 0; i < num_entries; i++) {
321 /* Check that this entry was actually valid --
322 needed in case failed in allocations */
323 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
324 snum =
325 (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
326 ENET_INIT_PARAM_SNUM_SHIFT;
327 qe_put_snum((u8) snum);
328 if (!((i == 0) && skip_page_for_first_entry)) {
329 /* First entry of Rx does not have page */
330 init_enet_offset =
331 (in_be32(p_start) &
332 ENET_INIT_PARAM_PTR_MASK);
333 qe_muram_free(init_enet_offset);
334 }
335 *(p_start++) = 0; /* Just for cosmetics */
336 }
337 }
338
339 return 0;
340}
341
342#ifdef DEBUG
18a8e864 343static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
ce973b14
LY		 344 volatile u32 *p_start,
345 u8 num_entries,
346 u32 thread_size,
18a8e864 347 enum qe_risc_allocation risc,
ce973b14
LY		 348 int skip_page_for_first_entry)
349{
350 u32 init_enet_offset;
351 u8 i;
352 int snum;
353
354 for (i = 0; i < num_entries; i++) {
355 /* Check that this entry was actually valid --
356 needed in case failed in allocations */
357 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
358 snum =
359 (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
360 ENET_INIT_PARAM_SNUM_SHIFT;
361 qe_put_snum((u8) snum);
362 if (!((i == 0) && skip_page_for_first_entry)) {
363 /* First entry of Rx does not have page */
364 init_enet_offset =
365 (in_be32(p_start) &
366 ENET_INIT_PARAM_PTR_MASK);
367 ugeth_info("Init enet entry %d:", i);
368 ugeth_info("Base address: 0x%08x",
369 (u32)
370 qe_muram_addr(init_enet_offset));
371 mem_disp(qe_muram_addr(init_enet_offset),
372 thread_size);
373 }
374 p_start++;
375 }
376 }
377
378 return 0;
379}
380#endif
381
382#ifdef CONFIG_UGETH_FILTERING
18a8e864 383static struct enet_addr_container *get_enet_addr_container(void)
ce973b14 384{
18a8e864 385 struct enet_addr_container *enet_addr_cont;
ce973b14
LY		 386
387 /* allocate memory */
18a8e864 388 enet_addr_cont = kmalloc(sizeof(struct enet_addr_container), GFP_KERNEL);
ce973b14 389 if (!enet_addr_cont) {
18a8e864 390 ugeth_err("%s: No memory for enet_addr_container object.",
ce973b14
LY		 391 __FUNCTION__);
392 return NULL;
393 }
394
395 return enet_addr_cont;
396}
397#endif /* CONFIG_UGETH_FILTERING */
398
18a8e864 399static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
ce973b14
LY		 400{
401 kfree(enet_addr_cont);
402}
403
df19b6b0 404static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
18a8e864
LY		 405{
406 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
407 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
408 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
409}
410
ce973b14 411#ifdef CONFIG_UGETH_FILTERING
18a8e864
LY		 412static int hw_add_addr_in_paddr(struct ucc_geth_private *ugeth,
413 u8 *p_enet_addr, u8 paddr_num)
ce973b14 414{
18a8e864 415 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
ce973b14
LY		 416
417 if (!(paddr_num < NUM_OF_PADDRS)) {
18a8e864 418 ugeth_warn("%s: Illegal paddr_num.", __FUNCTION__);
ce973b14
LY		 419 return -EINVAL;
420 }
421
422 p_82xx_addr_filt =
18a8e864 423 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 424 addressfiltering;
425
426 /* Ethernet frames are defined in Little Endian mode, */
427 /* therefore to insert the address we reverse the bytes. */
18a8e864 428 set_mac_addr(&p_82xx_addr_filt->paddr[paddr_num].h, p_enet_addr);
ce973b14
LY		 429 return 0;
430}
431#endif /* CONFIG_UGETH_FILTERING */
432
18a8e864 433static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
ce973b14 434{
18a8e864 435 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
ce973b14
LY		 436
437 if (!(paddr_num < NUM_OF_PADDRS)) {
438 ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
439 return -EINVAL;
440 }
441
442 p_82xx_addr_filt =
18a8e864 443 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 444 addressfiltering;
445
446 /* Writing address ff.ff.ff.ff.ff.ff disables address
447 recognition for this register */
448 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
449 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
450 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
451
452 return 0;
453}
454
18a8e864
LY		 455static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
456 u8 *p_enet_addr)
ce973b14 457{
18a8e864 458 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
ce973b14
LY		 459 u32 cecr_subblock;
460
461 p_82xx_addr_filt =
18a8e864 462 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 463 addressfiltering;
464
465 cecr_subblock =
466 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
467
468 /* Ethernet frames are defined in Little Endian mode,
469 therefor to insert */
470 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
18a8e864
LY		 471
472 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
ce973b14
LY		 473
474 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
18a8e864 475 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 476}
477
478#ifdef CONFIG_UGETH_MAGIC_PACKET
18a8e864 479static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
ce973b14 480{
18a8e864
LY		 481 struct ucc_fast_private *uccf;
482 struct ucc_geth *ug_regs;
ce973b14
LY		 483 u32 maccfg2, uccm;
484
485 uccf = ugeth->uccf;
486 ug_regs = ugeth->ug_regs;
487
488 /* Enable interrupts for magic packet detection */
489 uccm = in_be32(uccf->p_uccm);
490 uccm |= UCCE_MPD;
491 out_be32(uccf->p_uccm, uccm);
492
493 /* Enable magic packet detection */
494 maccfg2 = in_be32(&ug_regs->maccfg2);
495 maccfg2 |= MACCFG2_MPE;
496 out_be32(&ug_regs->maccfg2, maccfg2);
497}
498
18a8e864 499static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
ce973b14 500{
18a8e864
LY		 501 struct ucc_fast_private *uccf;
502 struct ucc_geth *ug_regs;
ce973b14
LY		 503 u32 maccfg2, uccm;
504
505 uccf = ugeth->uccf;
506 ug_regs = ugeth->ug_regs;
507
508 /* Disable interrupts for magic packet detection */
509 uccm = in_be32(uccf->p_uccm);
510 uccm &= ~UCCE_MPD;
511 out_be32(uccf->p_uccm, uccm);
512
513 /* Disable magic packet detection */
514 maccfg2 = in_be32(&ug_regs->maccfg2);
515 maccfg2 &= ~MACCFG2_MPE;
516 out_be32(&ug_regs->maccfg2, maccfg2);
517}
518#endif /* MAGIC_PACKET */
519
18a8e864 520static inline int compare_addr(u8 **addr1, u8 **addr2)
ce973b14
LY		 521{
522 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
523}
524
525#ifdef DEBUG
18a8e864
LY		 526static void get_statistics(struct ucc_geth_private *ugeth,
527 struct ucc_geth_tx_firmware_statistics *
ce973b14 528 tx_firmware_statistics,
18a8e864 529 struct ucc_geth_rx_firmware_statistics *
ce973b14 530 rx_firmware_statistics,
18a8e864 531 struct ucc_geth_hardware_statistics *hardware_statistics)
ce973b14 532{
18a8e864
LY		 533 struct ucc_fast *uf_regs;
534 struct ucc_geth *ug_regs;
535 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
536 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
ce973b14
LY		 537
538 ug_regs = ugeth->ug_regs;
18a8e864 539 uf_regs = (struct ucc_fast *) ug_regs;
ce973b14
LY		 540 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
541 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
542
543 /* Tx firmware only if user handed pointer and driver actually
544 gathers Tx firmware statistics */
545 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
546 tx_firmware_statistics->sicoltx =
547 in_be32(&p_tx_fw_statistics_pram->sicoltx);
548 tx_firmware_statistics->mulcoltx =
549 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
550 tx_firmware_statistics->latecoltxfr =
551 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
552 tx_firmware_statistics->frabortduecol =
553 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
554 tx_firmware_statistics->frlostinmactxer =
555 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
556 tx_firmware_statistics->carriersenseertx =
557 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
558 tx_firmware_statistics->frtxok =
559 in_be32(&p_tx_fw_statistics_pram->frtxok);
560 tx_firmware_statistics->txfrexcessivedefer =
561 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
562 tx_firmware_statistics->txpkts256 =
563 in_be32(&p_tx_fw_statistics_pram->txpkts256);
564 tx_firmware_statistics->txpkts512 =
565 in_be32(&p_tx_fw_statistics_pram->txpkts512);
566 tx_firmware_statistics->txpkts1024 =
567 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
568 tx_firmware_statistics->txpktsjumbo =
569 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
570 }
571
572 /* Rx firmware only if user handed pointer and driver actually
573 * gathers Rx firmware statistics */
574 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
575 int i;
576 rx_firmware_statistics->frrxfcser =
577 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
578 rx_firmware_statistics->fraligner =
579 in_be32(&p_rx_fw_statistics_pram->fraligner);
580 rx_firmware_statistics->inrangelenrxer =
581 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
582 rx_firmware_statistics->outrangelenrxer =
583 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
584 rx_firmware_statistics->frtoolong =
585 in_be32(&p_rx_fw_statistics_pram->frtoolong);
586 rx_firmware_statistics->runt =
587 in_be32(&p_rx_fw_statistics_pram->runt);
588 rx_firmware_statistics->verylongevent =
589 in_be32(&p_rx_fw_statistics_pram->verylongevent);
590 rx_firmware_statistics->symbolerror =
591 in_be32(&p_rx_fw_statistics_pram->symbolerror);
592 rx_firmware_statistics->dropbsy =
593 in_be32(&p_rx_fw_statistics_pram->dropbsy);
594 for (i = 0; i < 0x8; i++)
595 rx_firmware_statistics->res0[i] =
596 p_rx_fw_statistics_pram->res0[i];
597 rx_firmware_statistics->mismatchdrop =
598 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
599 rx_firmware_statistics->underpkts =
600 in_be32(&p_rx_fw_statistics_pram->underpkts);
601 rx_firmware_statistics->pkts256 =
602 in_be32(&p_rx_fw_statistics_pram->pkts256);
603 rx_firmware_statistics->pkts512 =
604 in_be32(&p_rx_fw_statistics_pram->pkts512);
605 rx_firmware_statistics->pkts1024 =
606 in_be32(&p_rx_fw_statistics_pram->pkts1024);
607 rx_firmware_statistics->pktsjumbo =
608 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
609 rx_firmware_statistics->frlossinmacer =
610 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
611 rx_firmware_statistics->pausefr =
612 in_be32(&p_rx_fw_statistics_pram->pausefr);
613 for (i = 0; i < 0x4; i++)
614 rx_firmware_statistics->res1[i] =
615 p_rx_fw_statistics_pram->res1[i];
616 rx_firmware_statistics->removevlan =
617 in_be32(&p_rx_fw_statistics_pram->removevlan);
618 rx_firmware_statistics->replacevlan =
619 in_be32(&p_rx_fw_statistics_pram->replacevlan);
620 rx_firmware_statistics->insertvlan =
621 in_be32(&p_rx_fw_statistics_pram->insertvlan);
622 }
623
624 /* Hardware only if user handed pointer and driver actually
625 gathers hardware statistics */
626 if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) {
627 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
628 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
629 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
630 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
631 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
632 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
633 hardware_statistics->txok = in_be32(&ug_regs->txok);
634 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
635 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
636 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
637 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
638 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
639 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
640 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
641 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
642 }
643}
644
18a8e864 645static void dump_bds(struct ucc_geth_private *ugeth)
ce973b14
LY		 646{
647 int i;
648 int length;
649
650 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
651 if (ugeth->p_tx_bd_ring[i]) {
652 length =
653 (ugeth->ug_info->bdRingLenTx[i] *
18a8e864 654 sizeof(struct qe_bd));
ce973b14
LY		 655 ugeth_info("TX BDs[%d]", i);
656 mem_disp(ugeth->p_tx_bd_ring[i], length);
657 }
658 }
659 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
660 if (ugeth->p_rx_bd_ring[i]) {
661 length =
662 (ugeth->ug_info->bdRingLenRx[i] *
18a8e864 663 sizeof(struct qe_bd));
ce973b14
LY		 664 ugeth_info("RX BDs[%d]", i);
665 mem_disp(ugeth->p_rx_bd_ring[i], length);
666 }
667 }
668}
669
18a8e864 670static void dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 671{
672 int i;
673
674 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
675 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
676
677 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
678 (u32) & ugeth->ug_regs->maccfg1,
679 in_be32(&ugeth->ug_regs->maccfg1));
680 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
681 (u32) & ugeth->ug_regs->maccfg2,
682 in_be32(&ugeth->ug_regs->maccfg2));
683 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
684 (u32) & ugeth->ug_regs->ipgifg,
685 in_be32(&ugeth->ug_regs->ipgifg));
686 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
687 (u32) & ugeth->ug_regs->hafdup,
688 in_be32(&ugeth->ug_regs->hafdup));
ce973b14
LY		 689 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
690 (u32) & ugeth->ug_regs->ifctl,
691 in_be32(&ugeth->ug_regs->ifctl));
692 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
693 (u32) & ugeth->ug_regs->ifstat,
694 in_be32(&ugeth->ug_regs->ifstat));
695 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
696 (u32) & ugeth->ug_regs->macstnaddr1,
697 in_be32(&ugeth->ug_regs->macstnaddr1));
698 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
699 (u32) & ugeth->ug_regs->macstnaddr2,
700 in_be32(&ugeth->ug_regs->macstnaddr2));
701 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
702 (u32) & ugeth->ug_regs->uempr,
703 in_be32(&ugeth->ug_regs->uempr));
704 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
705 (u32) & ugeth->ug_regs->utbipar,
706 in_be32(&ugeth->ug_regs->utbipar));
707 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
708 (u32) & ugeth->ug_regs->uescr,
709 in_be16(&ugeth->ug_regs->uescr));
710 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
711 (u32) & ugeth->ug_regs->tx64,
712 in_be32(&ugeth->ug_regs->tx64));
713 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
714 (u32) & ugeth->ug_regs->tx127,
715 in_be32(&ugeth->ug_regs->tx127));
716 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
717 (u32) & ugeth->ug_regs->tx255,
718 in_be32(&ugeth->ug_regs->tx255));
719 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
720 (u32) & ugeth->ug_regs->rx64,
721 in_be32(&ugeth->ug_regs->rx64));
722 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
723 (u32) & ugeth->ug_regs->rx127,
724 in_be32(&ugeth->ug_regs->rx127));
725 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
726 (u32) & ugeth->ug_regs->rx255,
727 in_be32(&ugeth->ug_regs->rx255));
728 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
729 (u32) & ugeth->ug_regs->txok,
730 in_be32(&ugeth->ug_regs->txok));
731 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
732 (u32) & ugeth->ug_regs->txcf,
733 in_be16(&ugeth->ug_regs->txcf));
734 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
735 (u32) & ugeth->ug_regs->tmca,
736 in_be32(&ugeth->ug_regs->tmca));
737 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
738 (u32) & ugeth->ug_regs->tbca,
739 in_be32(&ugeth->ug_regs->tbca));
740 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
741 (u32) & ugeth->ug_regs->rxfok,
742 in_be32(&ugeth->ug_regs->rxfok));
743 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
744 (u32) & ugeth->ug_regs->rxbok,
745 in_be32(&ugeth->ug_regs->rxbok));
746 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
747 (u32) & ugeth->ug_regs->rbyt,
748 in_be32(&ugeth->ug_regs->rbyt));
749 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
750 (u32) & ugeth->ug_regs->rmca,
751 in_be32(&ugeth->ug_regs->rmca));
752 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
753 (u32) & ugeth->ug_regs->rbca,
754 in_be32(&ugeth->ug_regs->rbca));
755 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
756 (u32) & ugeth->ug_regs->scar,
757 in_be32(&ugeth->ug_regs->scar));
758 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
759 (u32) & ugeth->ug_regs->scam,
760 in_be32(&ugeth->ug_regs->scam));
761
762 if (ugeth->p_thread_data_tx) {
763 int numThreadsTxNumerical;
764 switch (ugeth->ug_info->numThreadsTx) {
765 case UCC_GETH_NUM_OF_THREADS_1:
766 numThreadsTxNumerical = 1;
767 break;
768 case UCC_GETH_NUM_OF_THREADS_2:
769 numThreadsTxNumerical = 2;
770 break;
771 case UCC_GETH_NUM_OF_THREADS_4:
772 numThreadsTxNumerical = 4;
773 break;
774 case UCC_GETH_NUM_OF_THREADS_6:
775 numThreadsTxNumerical = 6;
776 break;
777 case UCC_GETH_NUM_OF_THREADS_8:
778 numThreadsTxNumerical = 8;
779 break;
780 default:
781 numThreadsTxNumerical = 0;
782 break;
783 }
784
785 ugeth_info("Thread data TXs:");
786 ugeth_info("Base address: 0x%08x",
787 (u32) ugeth->p_thread_data_tx);
788 for (i = 0; i < numThreadsTxNumerical; i++) {
789 ugeth_info("Thread data TX[%d]:", i);
790 ugeth_info("Base address: 0x%08x",
791 (u32) & ugeth->p_thread_data_tx[i]);
792 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
18a8e864 793 sizeof(struct ucc_geth_thread_data_tx));
ce973b14
LY		 794 }
795 }
796 if (ugeth->p_thread_data_rx) {
797 int numThreadsRxNumerical;
798 switch (ugeth->ug_info->numThreadsRx) {
799 case UCC_GETH_NUM_OF_THREADS_1:
800 numThreadsRxNumerical = 1;
801 break;
802 case UCC_GETH_NUM_OF_THREADS_2:
803 numThreadsRxNumerical = 2;
804 break;
805 case UCC_GETH_NUM_OF_THREADS_4:
806 numThreadsRxNumerical = 4;
807 break;
808 case UCC_GETH_NUM_OF_THREADS_6:
809 numThreadsRxNumerical = 6;
810 break;
811 case UCC_GETH_NUM_OF_THREADS_8:
812 numThreadsRxNumerical = 8;
813 break;
814 default:
815 numThreadsRxNumerical = 0;
816 break;
817 }
818
819 ugeth_info("Thread data RX:");
820 ugeth_info("Base address: 0x%08x",
821 (u32) ugeth->p_thread_data_rx);
822 for (i = 0; i < numThreadsRxNumerical; i++) {
823 ugeth_info("Thread data RX[%d]:", i);
824 ugeth_info("Base address: 0x%08x",
825 (u32) & ugeth->p_thread_data_rx[i]);
826 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
18a8e864 827 sizeof(struct ucc_geth_thread_data_rx));
ce973b14
LY		 828 }
829 }
830 if (ugeth->p_exf_glbl_param) {
831 ugeth_info("EXF global param:");
832 ugeth_info("Base address: 0x%08x",
833 (u32) ugeth->p_exf_glbl_param);
834 mem_disp((u8 *) ugeth->p_exf_glbl_param,
835 sizeof(*ugeth->p_exf_glbl_param));
836 }
837 if (ugeth->p_tx_glbl_pram) {
838 ugeth_info("TX global param:");
839 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
840 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
841 (u32) & ugeth->p_tx_glbl_pram->temoder,
842 in_be16(&ugeth->p_tx_glbl_pram->temoder));
843 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
844 (u32) & ugeth->p_tx_glbl_pram->sqptr,
845 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
846 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
847 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
848 in_be32(&ugeth->p_tx_glbl_pram->
849 schedulerbasepointer));
850 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
851 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
852 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
853 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
854 (u32) & ugeth->p_tx_glbl_pram->tstate,
855 in_be32(&ugeth->p_tx_glbl_pram->tstate));
856 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
857 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
858 ugeth->p_tx_glbl_pram->iphoffset[0]);
859 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
860 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
861 ugeth->p_tx_glbl_pram->iphoffset[1]);
862 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
863 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
864 ugeth->p_tx_glbl_pram->iphoffset[2]);
865 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
866 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
867 ugeth->p_tx_glbl_pram->iphoffset[3]);
868 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
869 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
870 ugeth->p_tx_glbl_pram->iphoffset[4]);
871 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
872 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
873 ugeth->p_tx_glbl_pram->iphoffset[5]);
874 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
875 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
876 ugeth->p_tx_glbl_pram->iphoffset[6]);
877 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
878 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
879 ugeth->p_tx_glbl_pram->iphoffset[7]);
880 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
881 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
882 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
883 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
884 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
885 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
886 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
887 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
888 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
889 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
890 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
891 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
892 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
893 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
894 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
895 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
896 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
897 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
898 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
899 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
900 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
901 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
902 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
903 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
904 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
905 (u32) & ugeth->p_tx_glbl_pram->tqptr,
906 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
907 }
908 if (ugeth->p_rx_glbl_pram) {
909 ugeth_info("RX global param:");
910 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
911 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
912 (u32) & ugeth->p_rx_glbl_pram->remoder,
913 in_be32(&ugeth->p_rx_glbl_pram->remoder));
914 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
915 (u32) & ugeth->p_rx_glbl_pram->rqptr,
916 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
917 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
918 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
919 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
920 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
921 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
922 ugeth->p_rx_glbl_pram->rxgstpack);
923 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
924 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
925 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
926 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
927 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
928 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
929 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
930 (u32) & ugeth->p_rx_glbl_pram->rstate,
931 ugeth->p_rx_glbl_pram->rstate);
932 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
933 (u32) & ugeth->p_rx_glbl_pram->mrblr,
934 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
935 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
936 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
937 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
938 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
939 (u32) & ugeth->p_rx_glbl_pram->mflr,
940 in_be16(&ugeth->p_rx_glbl_pram->mflr));
941 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
942 (u32) & ugeth->p_rx_glbl_pram->minflr,
943 in_be16(&ugeth->p_rx_glbl_pram->minflr));
944 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
945 (u32) & ugeth->p_rx_glbl_pram->maxd1,
946 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
947 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
948 (u32) & ugeth->p_rx_glbl_pram->maxd2,
949 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
950 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
951 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
952 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
953 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
954 (u32) & ugeth->p_rx_glbl_pram->l2qt,
955 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
956 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
957 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
958 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
959 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
960 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
961 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
962 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
963 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
964 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
965 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
966 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
967 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
968 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
969 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
970 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
971 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
972 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
973 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
974 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
975 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
976 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
977 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
978 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
979 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
980 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
981 (u32) & ugeth->p_rx_glbl_pram->vlantype,
982 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
983 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
984 (u32) & ugeth->p_rx_glbl_pram->vlantci,
985 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
986 for (i = 0; i < 64; i++)
987 ugeth_info
988 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
989 i,
990 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
991 ugeth->p_rx_glbl_pram->addressfiltering[i]);
992 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
993 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
994 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
995 }
996 if (ugeth->p_send_q_mem_reg) {
997 ugeth_info("Send Q memory registers:");
998 ugeth_info("Base address: 0x%08x",
999 (u32) ugeth->p_send_q_mem_reg);
1000 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1001 ugeth_info("SQQD[%d]:", i);
1002 ugeth_info("Base address: 0x%08x",
1003 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
1004 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
18a8e864 1005 sizeof(struct ucc_geth_send_queue_qd));
ce973b14
LY		 1006 }
1007 }
1008 if (ugeth->p_scheduler) {
1009 ugeth_info("Scheduler:");
1010 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
1011 mem_disp((u8 *) ugeth->p_scheduler,
1012 sizeof(*ugeth->p_scheduler));
1013 }
1014 if (ugeth->p_tx_fw_statistics_pram) {
1015 ugeth_info("TX FW statistics pram:");
1016 ugeth_info("Base address: 0x%08x",
1017 (u32) ugeth->p_tx_fw_statistics_pram);
1018 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
1019 sizeof(*ugeth->p_tx_fw_statistics_pram));
1020 }
1021 if (ugeth->p_rx_fw_statistics_pram) {
1022 ugeth_info("RX FW statistics pram:");
1023 ugeth_info("Base address: 0x%08x",
1024 (u32) ugeth->p_rx_fw_statistics_pram);
1025 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
1026 sizeof(*ugeth->p_rx_fw_statistics_pram));
1027 }
1028 if (ugeth->p_rx_irq_coalescing_tbl) {
1029 ugeth_info("RX IRQ coalescing tables:");
1030 ugeth_info("Base address: 0x%08x",
1031 (u32) ugeth->p_rx_irq_coalescing_tbl);
1032 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1033 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
1034 ugeth_info("Base address: 0x%08x",
1035 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1036 coalescingentry[i]);
1037 ugeth_info
1038 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
1039 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1040 coalescingentry[i].interruptcoalescingmaxvalue,
1041 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1042 coalescingentry[i].
1043 interruptcoalescingmaxvalue));
1044 ugeth_info
1045 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1046 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1047 coalescingentry[i].interruptcoalescingcounter,
1048 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1049 coalescingentry[i].
1050 interruptcoalescingcounter));
1051 }
1052 }
1053 if (ugeth->p_rx_bd_qs_tbl) {
1054 ugeth_info("RX BD QS tables:");
1055 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1056 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1057 ugeth_info("RX BD QS table[%d]:", i);
1058 ugeth_info("Base address: 0x%08x",
1059 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1060 ugeth_info
1061 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1062 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1063 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1064 ugeth_info
1065 ("bdptr : addr - 0x%08x, val - 0x%08x",
1066 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1067 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1068 ugeth_info
1069 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1070 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1071 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1072 externalbdbaseptr));
1073 ugeth_info
1074 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1075 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1076 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1077 ugeth_info("ucode RX Prefetched BDs:");
1078 ugeth_info("Base address: 0x%08x",
1079 (u32)
1080 qe_muram_addr(in_be32
1081 (&ugeth->p_rx_bd_qs_tbl[i].
1082 bdbaseptr)));
1083 mem_disp((u8 *)
1084 qe_muram_addr(in_be32
1085 (&ugeth->p_rx_bd_qs_tbl[i].
1086 bdbaseptr)),
18a8e864 1087 sizeof(struct ucc_geth_rx_prefetched_bds));
ce973b14
LY		 1088 }
1089 }
1090 if (ugeth->p_init_enet_param_shadow) {
1091 int size;
1092 ugeth_info("Init enet param shadow:");
1093 ugeth_info("Base address: 0x%08x",
1094 (u32) ugeth->p_init_enet_param_shadow);
1095 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1096 sizeof(*ugeth->p_init_enet_param_shadow));
1097
18a8e864 1098 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 1099 if (ugeth->ug_info->rxExtendedFiltering) {
1100 size +=
1101 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1102 if (ugeth->ug_info->largestexternallookupkeysize ==
1103 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1104 size +=
1105 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1106 if (ugeth->ug_info->largestexternallookupkeysize ==
1107 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1108 size +=
1109 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1110 }
1111
1112 dump_init_enet_entries(ugeth,
1113 &(ugeth->p_init_enet_param_shadow->
1114 txthread[0]),
1115 ENET_INIT_PARAM_MAX_ENTRIES_TX,
18a8e864 1116 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 1117 ugeth->ug_info->riscTx, 0);
1118 dump_init_enet_entries(ugeth,
1119 &(ugeth->p_init_enet_param_shadow->
1120 rxthread[0]),
1121 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1122 ugeth->ug_info->riscRx, 1);
1123 }
1124}
1125#endif /* DEBUG */
1126
1127static void init_default_reg_vals(volatile u32 *upsmr_register,
1128 volatile u32 *maccfg1_register,
1129 volatile u32 *maccfg2_register)
1130{
1131 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1132 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1133 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1134}
1135
1136static int init_half_duplex_params(int alt_beb,
1137 int back_pressure_no_backoff,
1138 int no_backoff,
1139 int excess_defer,
1140 u8 alt_beb_truncation,
1141 u8 max_retransmissions,
1142 u8 collision_window,
1143 volatile u32 *hafdup_register)
1144{
1145 u32 value = 0;
1146
1147 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1148 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1149 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1150 return -EINVAL;
1151
1152 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1153
1154 if (alt_beb)
1155 value |= HALFDUP_ALT_BEB;
1156 if (back_pressure_no_backoff)
1157 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1158 if (no_backoff)
1159 value |= HALFDUP_NO_BACKOFF;
1160 if (excess_defer)
1161 value |= HALFDUP_EXCESSIVE_DEFER;
1162
1163 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1164
1165 value |= collision_window;
1166
1167 out_be32(hafdup_register, value);
1168 return 0;
1169}
1170
1171static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1172 u8 non_btb_ipg,
1173 u8 min_ifg,
1174 u8 btb_ipg,
1175 volatile u32 *ipgifg_register)
1176{
1177 u32 value = 0;
1178
1179 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1180 IPG part 2 */
1181 if (non_btb_cs_ipg > non_btb_ipg)
1182 return -EINVAL;
1183
1184 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1185 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1186 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1187 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1188 return -EINVAL;
1189
1190 value |=
1191 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1192 IPGIFG_NBTB_CS_IPG_MASK);
1193 value |=
1194 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1195 IPGIFG_NBTB_IPG_MASK);
1196 value |=
1197 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1198 IPGIFG_MIN_IFG_MASK);
1199 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1200
1201 out_be32(ipgifg_register, value);
1202 return 0;
1203}
1204
1205static int init_flow_control_params(u32 automatic_flow_control_mode,
1206 int rx_flow_control_enable,
1207 int tx_flow_control_enable,
1208 u16 pause_period,
1209 u16 extension_field,
1210 volatile u32 *upsmr_register,
1211 volatile u32 *uempr_register,
1212 volatile u32 *maccfg1_register)
1213{
1214 u32 value = 0;
1215
1216 /* Set UEMPR register */
1217 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1218 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1219 out_be32(uempr_register, value);
1220
1221 /* Set UPSMR register */
1222 value = in_be32(upsmr_register);
1223 value |= automatic_flow_control_mode;
1224 out_be32(upsmr_register, value);
1225
1226 value = in_be32(maccfg1_register);
1227 if (rx_flow_control_enable)
1228 value |= MACCFG1_FLOW_RX;
1229 if (tx_flow_control_enable)
1230 value |= MACCFG1_FLOW_TX;
1231 out_be32(maccfg1_register, value);
1232
1233 return 0;
1234}
1235
1236static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1237 int auto_zero_hardware_statistics,
1238 volatile u32 *upsmr_register,
1239 volatile u16 *uescr_register)
1240{
1241 u32 upsmr_value = 0;
1242 u16 uescr_value = 0;
1243 /* Enable hardware statistics gathering if requested */
1244 if (enable_hardware_statistics) {
1245 upsmr_value = in_be32(upsmr_register);
1246 upsmr_value |= UPSMR_HSE;
1247 out_be32(upsmr_register, upsmr_value);
1248 }
1249
1250 /* Clear hardware statistics counters */
1251 uescr_value = in_be16(uescr_register);
1252 uescr_value |= UESCR_CLRCNT;
1253 /* Automatically zero hardware statistics counters on read,
1254 if requested */
1255 if (auto_zero_hardware_statistics)
1256 uescr_value |= UESCR_AUTOZ;
1257 out_be16(uescr_register, uescr_value);
1258
1259 return 0;
1260}
1261
1262static int init_firmware_statistics_gathering_mode(int
1263 enable_tx_firmware_statistics,
1264 int enable_rx_firmware_statistics,
1265 volatile u32 *tx_rmon_base_ptr,
1266 u32 tx_firmware_statistics_structure_address,
1267 volatile u32 *rx_rmon_base_ptr,
1268 u32 rx_firmware_statistics_structure_address,
1269 volatile u16 *temoder_register,
1270 volatile u32 *remoder_register)
1271{
1272 /* Note: this function does not check if */
1273 /* the parameters it receives are NULL */
1274 u16 temoder_value;
1275 u32 remoder_value;
1276
1277 if (enable_tx_firmware_statistics) {
1278 out_be32(tx_rmon_base_ptr,
1279 tx_firmware_statistics_structure_address);
1280 temoder_value = in_be16(temoder_register);
1281 temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
1282 out_be16(temoder_register, temoder_value);
1283 }
1284
1285 if (enable_rx_firmware_statistics) {
1286 out_be32(rx_rmon_base_ptr,
1287 rx_firmware_statistics_structure_address);
1288 remoder_value = in_be32(remoder_register);
1289 remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
1290 out_be32(remoder_register, remoder_value);
1291 }
1292
1293 return 0;
1294}
1295
1296static int init_mac_station_addr_regs(u8 address_byte_0,
1297 u8 address_byte_1,
1298 u8 address_byte_2,
1299 u8 address_byte_3,
1300 u8 address_byte_4,
1301 u8 address_byte_5,
1302 volatile u32 *macstnaddr1_register,
1303 volatile u32 *macstnaddr2_register)
1304{
1305 u32 value = 0;
1306
1307 /* Example: for a station address of 0x12345678ABCD, */
1308 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1309
1310 /* MACSTNADDR1 Register: */
1311
1312 /* 0 7 8 15 */
1313 /* station address byte 5 station address byte 4 */
1314 /* 16 23 24 31 */
1315 /* station address byte 3 station address byte 2 */
1316 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1317 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1318 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1319 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1320
1321 out_be32(macstnaddr1_register, value);
1322
1323 /* MACSTNADDR2 Register: */
1324
1325 /* 0 7 8 15 */
1326 /* station address byte 1 station address byte 0 */
1327 /* 16 23 24 31 */
1328 /* reserved reserved */
1329 value = 0;
1330 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1331 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1332
1333 out_be32(macstnaddr2_register, value);
1334
1335 return 0;
1336}
1337
ce973b14
LY		 1338static int init_check_frame_length_mode(int length_check,
1339 volatile u32 *maccfg2_register)
1340{
1341 u32 value = 0;
1342
1343 value = in_be32(maccfg2_register);
1344
1345 if (length_check)
1346 value |= MACCFG2_LC;
1347 else
1348 value &= ~MACCFG2_LC;
1349
1350 out_be32(maccfg2_register, value);
1351 return 0;
1352}
1353
1354static int init_preamble_length(u8 preamble_length,
1355 volatile u32 *maccfg2_register)
1356{
1357 u32 value = 0;
1358
1359 if ((preamble_length < 3) || (preamble_length > 7))
1360 return -EINVAL;
1361
1362 value = in_be32(maccfg2_register);
1363 value &= ~MACCFG2_PREL_MASK;
1364 value |= (preamble_length << MACCFG2_PREL_SHIFT);
1365 out_be32(maccfg2_register, value);
1366 return 0;
1367}
1368
ce973b14
LY		 1369static int init_rx_parameters(int reject_broadcast,
1370 int receive_short_frames,
1371 int promiscuous, volatile u32 *upsmr_register)
1372{
1373 u32 value = 0;
1374
1375 value = in_be32(upsmr_register);
1376
1377 if (reject_broadcast)
1378 value |= UPSMR_BRO;
1379 else
1380 value &= ~UPSMR_BRO;
1381
1382 if (receive_short_frames)
1383 value |= UPSMR_RSH;
1384 else
1385 value &= ~UPSMR_RSH;
1386
1387 if (promiscuous)
1388 value |= UPSMR_PRO;
1389 else
1390 value &= ~UPSMR_PRO;
1391
1392 out_be32(upsmr_register, value);
1393
1394 return 0;
1395}
1396
1397static int init_max_rx_buff_len(u16 max_rx_buf_len,
1398 volatile u16 *mrblr_register)
1399{
1400 /* max_rx_buf_len value must be a multiple of 128 */
1401 if ((max_rx_buf_len == 0)
1402 || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1403 return -EINVAL;
1404
1405 out_be16(mrblr_register, max_rx_buf_len);
1406 return 0;
1407}
1408
1409static int init_min_frame_len(u16 min_frame_length,
1410 volatile u16 *minflr_register,
1411 volatile u16 *mrblr_register)
1412{
1413 u16 mrblr_value = 0;
1414
1415 mrblr_value = in_be16(mrblr_register);
1416 if (min_frame_length >= (mrblr_value - 4))
1417 return -EINVAL;
1418
1419 out_be16(minflr_register, min_frame_length);
1420 return 0;
1421}
1422
18a8e864 1423static int adjust_enet_interface(struct ucc_geth_private *ugeth)
ce973b14 1424{
18a8e864
LY		 1425 struct ucc_geth_info *ug_info;
1426 struct ucc_geth *ug_regs;
1427 struct ucc_fast *uf_regs;
728de4c9
KP		 1428 int ret_val;
1429 u32 upsmr, maccfg2, tbiBaseAddress;
ce973b14
LY		 1430 u16 value;
1431
1432 ugeth_vdbg("%s: IN", __FUNCTION__);
1433
1434 ug_info = ugeth->ug_info;
1435 ug_regs = ugeth->ug_regs;
1436 uf_regs = ugeth->uccf->uf_regs;
1437
ce973b14
LY		 1438 /* Set MACCFG2 */
1439 maccfg2 = in_be32(&ug_regs->maccfg2);
1440 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
728de4c9
KP		 1441 if ((ugeth->max_speed == SPEED_10) ||
1442 (ugeth->max_speed == SPEED_100))
ce973b14 1443 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
728de4c9 1444 else if (ugeth->max_speed == SPEED_1000)
ce973b14
LY		 1445 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1446 maccfg2 |= ug_info->padAndCrc;
1447 out_be32(&ug_regs->maccfg2, maccfg2);
1448
1449 /* Set UPSMR */
1450 upsmr = in_be32(&uf_regs->upsmr);
1451 upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM);
728de4c9
KP		 1452 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1453 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1454 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1455 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
ce973b14 1456 upsmr |= UPSMR_RPM;
728de4c9
KP		 1457 switch (ugeth->max_speed) {
1458 case SPEED_10:
1459 upsmr |= UPSMR_R10M;
1460 /* FALLTHROUGH */
1461 case SPEED_100:
1462 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1463 upsmr |= UPSMR_RMM;
1464 }
1465 }
1466 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1467 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
ce973b14 1468 upsmr |= UPSMR_TBIM;
728de4c9 1469 }
ce973b14
LY		 1470 out_be32(&uf_regs->upsmr, upsmr);
1471
ce973b14
LY		 1472 /* Disable autonegotiation in tbi mode, because by default it
1473 comes up in autonegotiation mode. */
1474 /* Note that this depends on proper setting in utbipar register. */
728de4c9
KP		 1475 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1476 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
ce973b14
LY		 1477 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1478 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1479 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
728de4c9
KP		 1480 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1481 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
ce973b14 1482 value &= ~0x1000; /* Turn off autonegotiation */
728de4c9
KP		 1483 ugeth->phydev->bus->write(ugeth->phydev->bus,
1484 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
ce973b14
LY		 1485 }
1486
1487 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1488
1489 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1490 if (ret_val != 0) {
1491 ugeth_err
1492 ("%s: Preamble length must be between 3 and 7 inclusive.",
1493 __FUNCTION__);
1494 return ret_val;
1495 }
1496
1497 return 0;
1498}
1499
1500/* Called every time the controller might need to be made
1501 * aware of new link state. The PHY code conveys this
1502 * information through variables in the ugeth structure, and this
1503 * function converts those variables into the appropriate
1504 * register values, and can bring down the device if needed.
1505 */
728de4c9 1506
ce973b14
LY		 1507static void adjust_link(struct net_device *dev)
1508{
18a8e864
LY		 1509 struct ucc_geth_private *ugeth = netdev_priv(dev);
1510 struct ucc_geth *ug_regs;
728de4c9
KP		 1511 struct ucc_fast *uf_regs;
1512 struct phy_device *phydev = ugeth->phydev;
1513 unsigned long flags;
1514 int new_state = 0;
ce973b14
LY		 1515
1516 ug_regs = ugeth->ug_regs;
728de4c9 1517 uf_regs = ugeth->uccf->uf_regs;
ce973b14 1518
728de4c9
KP		 1519 spin_lock_irqsave(&ugeth->lock, flags);
1520
1521 if (phydev->link) {
1522 u32 tempval = in_be32(&ug_regs->maccfg2);
1523 u32 upsmr = in_be32(&uf_regs->upsmr);
ce973b14
LY		 1524 /* Now we make sure that we can be in full duplex mode.
1525 * If not, we operate in half-duplex mode. */
728de4c9
KP		 1526 if (phydev->duplex != ugeth->oldduplex) {
1527 new_state = 1;
1528 if (!(phydev->duplex))
ce973b14 1529 tempval &= ~(MACCFG2_FDX);
728de4c9 1530 else
ce973b14 1531 tempval |= MACCFG2_FDX;
728de4c9 1532 ugeth->oldduplex = phydev->duplex;
ce973b14
LY		 1533 }
1534
728de4c9
KP		 1535 if (phydev->speed != ugeth->oldspeed) {
1536 new_state = 1;
1537 switch (phydev->speed) {
1538 case SPEED_1000:
1539 tempval = ((tempval &
1540 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1541 MACCFG2_INTERFACE_MODE_BYTE);
a1862a53 1542 break;
728de4c9
KP		 1543 case SPEED_100:
1544 case SPEED_10:
1545 tempval = ((tempval &
1546 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1547 MACCFG2_INTERFACE_MODE_NIBBLE);
1548 /* if reduced mode, re-set UPSMR.R10M */
1549 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1550 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1551 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1552 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1553 if (phydev->speed == SPEED_10)
1554 upsmr |= UPSMR_R10M;
1555 else
1556 upsmr &= ~(UPSMR_R10M);
1557 }
ce973b14
LY		 1558 break;
1559 default:
728de4c9
KP		 1560 if (netif_msg_link(ugeth))
1561 ugeth_warn(
1562 "%s: Ack! Speed (%d) is not 10/100/1000!",
1563 dev->name, phydev->speed);
ce973b14
LY		 1564 break;
1565 }
728de4c9 1566 ugeth->oldspeed = phydev->speed;
ce973b14
LY		 1567 }
1568
728de4c9
KP		 1569 out_be32(&ug_regs->maccfg2, tempval);
1570 out_be32(&uf_regs->upsmr, upsmr);
1571
ce973b14 1572 if (!ugeth->oldlink) {
728de4c9 1573 new_state = 1;
ce973b14 1574 ugeth->oldlink = 1;
ce973b14
LY		 1575 netif_schedule(dev);
1576 }
728de4c9
KP		 1577 } else if (ugeth->oldlink) {
1578 new_state = 1;
ce973b14
LY		 1579 ugeth->oldlink = 0;
1580 ugeth->oldspeed = 0;
1581 ugeth->oldduplex = -1;
ce973b14 1582 }
728de4c9
KP		 1583
1584 if (new_state && netif_msg_link(ugeth))
1585 phy_print_status(phydev);
1586
1587 spin_unlock_irqrestore(&ugeth->lock, flags);
ce973b14
LY		 1588}
1589
1590/* Configure the PHY for dev.
1591 * returns 0 if success. -1 if failure
1592 */
1593static int init_phy(struct net_device *dev)
1594{
728de4c9
KP		 1595 struct ucc_geth_private *priv = netdev_priv(dev);
1596 struct phy_device *phydev;
1597 char phy_id[BUS_ID_SIZE];
ce973b14 1598
728de4c9
KP		 1599 priv->oldlink = 0;
1600 priv->oldspeed = 0;
1601 priv->oldduplex = -1;
ce973b14 1602
728de4c9
KP		 1603 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->ug_info->mdio_bus,
1604 priv->ug_info->phy_address);
ce973b14 1605
728de4c9 1606 phydev = phy_connect(dev, phy_id, &adjust_link, 0, priv->phy_interface);
ce973b14 1607
728de4c9
KP		 1608 if (IS_ERR(phydev)) {
1609 printk("%s: Could not attach to PHY\n", dev->name);
1610 return PTR_ERR(phydev);
ce973b14
LY		 1611 }
1612
728de4c9 1613 phydev->supported &= (ADVERTISED_10baseT_Half |
ce973b14
LY		 1614 ADVERTISED_10baseT_Full |
1615 ADVERTISED_100baseT_Half |
728de4c9 1616 ADVERTISED_100baseT_Full);
ce973b14 1617
728de4c9
KP		 1618 if (priv->max_speed == SPEED_1000)
1619 phydev->supported |= ADVERTISED_1000baseT_Full;
ce973b14 1620
728de4c9 1621 phydev->advertising = phydev->supported;
68dc44af 1622
728de4c9 1623 priv->phydev = phydev;
ce973b14
LY		 1624
1625 return 0;
ce973b14
LY		 1626}
1627
728de4c9 1628
ce973b14 1629#ifdef CONFIG_UGETH_TX_ON_DEMOND
18a8e864 1630static int ugeth_transmit_on_demand(struct ucc_geth_private *ugeth)
ce973b14 1631{
18a8e864 1632 struct ucc_fastransmit_on_demand(ugeth->uccf);
ce973b14
LY		 1633
1634 return 0;
1635}
1636#endif
1637
18a8e864 1638static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
ce973b14 1639{
18a8e864 1640 struct ucc_fast_private *uccf;
ce973b14
LY		 1641 u32 cecr_subblock;
1642 u32 temp;
1643
1644 uccf = ugeth->uccf;
1645
1646 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1647 temp = in_be32(uccf->p_uccm);
1648 temp &= ~UCCE_GRA;
1649 out_be32(uccf->p_uccm, temp);
1650 out_be32(uccf->p_ucce, UCCE_GRA); /* clear by writing 1 */
1651
1652 /* Issue host command */
1653 cecr_subblock =
1654 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1655 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
18a8e864 1656 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 1657
1658 /* Wait for command to complete */
1659 do {
1660 temp = in_be32(uccf->p_ucce);
1661 } while (!(temp & UCCE_GRA));
1662
1663 uccf->stopped_tx = 1;
1664
1665 return 0;
1666}
1667
18a8e864 1668static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
ce973b14 1669{
18a8e864 1670 struct ucc_fast_private *uccf;
ce973b14
LY		 1671 u32 cecr_subblock;
1672 u8 temp;
1673
1674 uccf = ugeth->uccf;
1675
1676 /* Clear acknowledge bit */
1677 temp = ugeth->p_rx_glbl_pram->rxgstpack;
1678 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1679 ugeth->p_rx_glbl_pram->rxgstpack = temp;
1680
1681 /* Keep issuing command and checking acknowledge bit until
1682 it is asserted, according to spec */
1683 do {
1684 /* Issue host command */
1685 cecr_subblock =
1686 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1687 ucc_num);
1688 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
18a8e864 1689 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 1690
1691 temp = ugeth->p_rx_glbl_pram->rxgstpack;
1692 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX));
1693
1694 uccf->stopped_rx = 1;
1695
1696 return 0;
1697}
1698
18a8e864 1699static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
ce973b14 1700{
18a8e864 1701 struct ucc_fast_private *uccf;
ce973b14
LY		 1702 u32 cecr_subblock;
1703
1704 uccf = ugeth->uccf;
1705
1706 cecr_subblock =
1707 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 1708 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 1709 uccf->stopped_tx = 0;
1710
1711 return 0;
1712}
1713
18a8e864 1714static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
ce973b14 1715{
18a8e864 1716 struct ucc_fast_private *uccf;
ce973b14
LY		 1717 u32 cecr_subblock;
1718
1719 uccf = ugeth->uccf;
1720
1721 cecr_subblock =
1722 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 1723 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 1724 0);
1725 uccf->stopped_rx = 0;
1726
1727 return 0;
1728}
1729
18a8e864 1730static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
ce973b14 1731{
18a8e864 1732 struct ucc_fast_private *uccf;
ce973b14
LY		 1733 int enabled_tx, enabled_rx;
1734
1735 uccf = ugeth->uccf;
1736
1737 /* check if the UCC number is in range. */
1738 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1739 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
1740 return -EINVAL;
1741 }
1742
1743 enabled_tx = uccf->enabled_tx;
1744 enabled_rx = uccf->enabled_rx;
1745
1746 /* Get Tx and Rx going again, in case this channel was actively
1747 disabled. */
1748 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1749 ugeth_restart_tx(ugeth);
1750 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1751 ugeth_restart_rx(ugeth);
1752
1753 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1754
1755 return 0;
1756
1757}
1758
18a8e864 1759static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
ce973b14 1760{
18a8e864 1761 struct ucc_fast_private *uccf;
ce973b14
LY		 1762
1763 uccf = ugeth->uccf;
1764
1765 /* check if the UCC number is in range. */
1766 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1767 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
1768 return -EINVAL;
1769 }
1770
1771 /* Stop any transmissions */
1772 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1773 ugeth_graceful_stop_tx(ugeth);
1774
1775 /* Stop any receptions */
1776 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1777 ugeth_graceful_stop_rx(ugeth);
1778
1779 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1780
1781 return 0;
1782}
1783
18a8e864 1784static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 1785{
1786#ifdef DEBUG
1787 ucc_fast_dump_regs(ugeth->uccf);
1788 dump_regs(ugeth);
1789 dump_bds(ugeth);
1790#endif
1791}
1792
1793#ifdef CONFIG_UGETH_FILTERING
18a8e864 1794static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params *
ce973b14 1795 p_UccGethTadParams,
18a8e864 1796 struct qe_fltr_tad *qe_fltr_tad)
ce973b14
LY		 1797{
1798 u16 temp;
1799
1800 /* Zero serialized TAD */
1801 memset(qe_fltr_tad, 0, QE_FLTR_TAD_SIZE);
1802
1803 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_V; /* Must have this */
1804 if (p_UccGethTadParams->rx_non_dynamic_extended_features_mode ||
1805 (p_UccGethTadParams->vtag_op != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
1806 || (p_UccGethTadParams->vnontag_op !=
1807 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP)
1808 )
1809 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_EF;
1810 if (p_UccGethTadParams->reject_frame)
1811 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_REJ;
1812 temp =
1813 (u16) (((u16) p_UccGethTadParams->
1814 vtag_op) << UCC_GETH_TAD_VTAG_OP_SHIFT);
1815 qe_fltr_tad->serialized[0] |= (u8) (temp >> 8); /* upper bits */
1816
1817 qe_fltr_tad->serialized[1] |= (u8) (temp & 0x00ff); /* lower bits */
1818 if (p_UccGethTadParams->vnontag_op ==
1819 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT)
1820 qe_fltr_tad->serialized[1] |= UCC_GETH_TAD_V_NON_VTAG_OP;
1821 qe_fltr_tad->serialized[1] |=
1822 p_UccGethTadParams->rqos << UCC_GETH_TAD_RQOS_SHIFT;
1823
1824 qe_fltr_tad->serialized[2] |=
1825 p_UccGethTadParams->vpri << UCC_GETH_TAD_V_PRIORITY_SHIFT;
1826 /* upper bits */
1827 qe_fltr_tad->serialized[2] |= (u8) (p_UccGethTadParams->vid >> 8);
1828 /* lower bits */
1829 qe_fltr_tad->serialized[3] |= (u8) (p_UccGethTadParams->vid & 0x00ff);
1830
1831 return 0;
1832}
1833
18a8e864
LY		 1834static struct enet_addr_container_t
1835 *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private *ugeth,
1836 struct enet_addr *p_enet_addr)
ce973b14 1837{
18a8e864 1838 struct enet_addr_container *enet_addr_cont;
ce973b14
LY		 1839 struct list_head *p_lh;
1840 u16 i, num;
1841 int32_t j;
1842 u8 *p_counter;
1843
1844 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1845 p_lh = &ugeth->group_hash_q;
1846 p_counter = &(ugeth->numGroupAddrInHash);
1847 } else {
1848 p_lh = &ugeth->ind_hash_q;
1849 p_counter = &(ugeth->numIndAddrInHash);
1850 }
1851
1852 if (!p_lh)
1853 return NULL;
1854
1855 num = *p_counter;
1856
1857 for (i = 0; i < num; i++) {
1858 enet_addr_cont =
18a8e864 1859 (struct enet_addr_container *)
ce973b14
LY		 1860 ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
1861 for (j = ENET_NUM_OCTETS_PER_ADDRESS - 1; j >= 0; j--) {
1862 if ((*p_enet_addr)[j] != (enet_addr_cont->address)[j])
1863 break;
1864 if (j == 0)
1865 return enet_addr_cont; /* Found */
1866 }
1867 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1868 }
1869 return NULL;
1870}
1871
18a8e864
LY		 1872static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private *ugeth,
1873 struct enet_addr *p_enet_addr)
ce973b14 1874{
18a8e864
LY		 1875 enum ucc_geth_enet_address_recognition_location location;
1876 struct enet_addr_container *enet_addr_cont;
ce973b14
LY		 1877 struct list_head *p_lh;
1878 u8 i;
1879 u32 limit;
1880 u8 *p_counter;
1881
1882 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1883 p_lh = &ugeth->group_hash_q;
1884 limit = ugeth->ug_info->maxGroupAddrInHash;
1885 location =
1886 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH;
1887 p_counter = &(ugeth->numGroupAddrInHash);
1888 } else {
1889 p_lh = &ugeth->ind_hash_q;
1890 limit = ugeth->ug_info->maxIndAddrInHash;
1891 location =
1892 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH;
1893 p_counter = &(ugeth->numIndAddrInHash);
1894 }
1895
1896 if ((enet_addr_cont =
1897 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr))) {
1898 list_add(p_lh, &enet_addr_cont->node); /* Put it back */
1899 return 0;
1900 }
1901 if ((!p_lh) || (!(*p_counter < limit)))
1902 return -EBUSY;
1903 if (!(enet_addr_cont = get_enet_addr_container()))
1904 return -ENOMEM;
1905 for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
1906 (enet_addr_cont->address)[i] = (*p_enet_addr)[i];
1907 enet_addr_cont->location = location;
1908 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1909 ++(*p_counter);
1910
18a8e864 1911 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
ce973b14
LY		 1912 return 0;
1913}
1914
18a8e864
LY		 1915static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private *ugeth,
1916 struct enet_addr *p_enet_addr)
ce973b14 1917{
18a8e864
LY		 1918 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
1919 struct enet_addr_container *enet_addr_cont;
1920 struct ucc_fast_private *uccf;
1921 enum comm_dir comm_dir;
ce973b14
LY		 1922 u16 i, num;
1923 struct list_head *p_lh;
1924 u32 *addr_h, *addr_l;
1925 u8 *p_counter;
1926
1927 uccf = ugeth->uccf;
1928
1929 p_82xx_addr_filt =
18a8e864 1930 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 1931 addressfiltering;
1932
1933 if (!
1934 (enet_addr_cont =
1935 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr)))
1936 return -ENOENT;
1937
1938 /* It's been found and removed from the CQ. */
1939 /* Now destroy its container */
1940 put_enet_addr_container(enet_addr_cont);
1941
1942 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1943 addr_h = &(p_82xx_addr_filt->gaddr_h);
1944 addr_l = &(p_82xx_addr_filt->gaddr_l);
1945 p_lh = &ugeth->group_hash_q;
1946 p_counter = &(ugeth->numGroupAddrInHash);
1947 } else {
1948 addr_h = &(p_82xx_addr_filt->iaddr_h);
1949 addr_l = &(p_82xx_addr_filt->iaddr_l);
1950 p_lh = &ugeth->ind_hash_q;
1951 p_counter = &(ugeth->numIndAddrInHash);
1952 }
1953
1954 comm_dir = 0;
1955 if (uccf->enabled_tx)
1956 comm_dir |= COMM_DIR_TX;
1957 if (uccf->enabled_rx)
1958 comm_dir |= COMM_DIR_RX;
1959 if (comm_dir)
1960 ugeth_disable(ugeth, comm_dir);
1961
1962 /* Clear the hash table. */
1963 out_be32(addr_h, 0x00000000);
1964 out_be32(addr_l, 0x00000000);
1965
1966 /* Add all remaining CQ elements back into hash */
1967 num = --(*p_counter);
1968 for (i = 0; i < num; i++) {
1969 enet_addr_cont =
18a8e864 1970 (struct enet_addr_container *)
ce973b14 1971 ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
18a8e864 1972 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
ce973b14
LY		 1973 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1974 }
1975
1976 if (comm_dir)
1977 ugeth_enable(ugeth, comm_dir);
1978
1979 return 0;
1980}
1981#endif /* CONFIG_UGETH_FILTERING */
1982
18a8e864 1983static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
ce973b14 1984 ugeth,
18a8e864 1985 enum enet_addr_type
ce973b14
LY		 1986 enet_addr_type)
1987{
18a8e864
LY		 1988 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
1989 struct ucc_fast_private *uccf;
1990 enum comm_dir comm_dir;
ce973b14
LY		 1991 struct list_head *p_lh;
1992 u16 i, num;
1993 u32 *addr_h, *addr_l;
1994 u8 *p_counter;
1995
1996 uccf = ugeth->uccf;
1997
1998 p_82xx_addr_filt =
18a8e864 1999 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 2000 addressfiltering;
2001
2002 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
2003 addr_h = &(p_82xx_addr_filt->gaddr_h);
2004 addr_l = &(p_82xx_addr_filt->gaddr_l);
2005 p_lh = &ugeth->group_hash_q;
2006 p_counter = &(ugeth->numGroupAddrInHash);
2007 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
2008 addr_h = &(p_82xx_addr_filt->iaddr_h);
2009 addr_l = &(p_82xx_addr_filt->iaddr_l);
2010 p_lh = &ugeth->ind_hash_q;
2011 p_counter = &(ugeth->numIndAddrInHash);
2012 } else
2013 return -EINVAL;
2014
2015 comm_dir = 0;
2016 if (uccf->enabled_tx)
2017 comm_dir |= COMM_DIR_TX;
2018 if (uccf->enabled_rx)
2019 comm_dir |= COMM_DIR_RX;
2020 if (comm_dir)
2021 ugeth_disable(ugeth, comm_dir);
2022
2023 /* Clear the hash table. */
2024 out_be32(addr_h, 0x00000000);
2025 out_be32(addr_l, 0x00000000);
2026
2027 if (!p_lh)
2028 return 0;
2029
2030 num = *p_counter;
2031
2032 /* Delete all remaining CQ elements */
2033 for (i = 0; i < num; i++)
2034 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
2035
2036 *p_counter = 0;
2037
2038 if (comm_dir)
2039 ugeth_enable(ugeth, comm_dir);
2040
2041 return 0;
2042}
2043
2044#ifdef CONFIG_UGETH_FILTERING
18a8e864
LY		 2045static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private *ugeth,
2046 struct enet_addr *p_enet_addr,
ce973b14
LY		 2047 u8 paddr_num)
2048{
2049 int i;
2050
2051 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR)
2052 ugeth_warn
2053 ("%s: multicast address added to paddr will have no "
2054 "effect - is this what you wanted?",
2055 __FUNCTION__);
2056
2057 ugeth->indAddrRegUsed[paddr_num] = 1; /* mark this paddr as used */
2058 /* store address in our database */
2059 for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
2060 ugeth->paddr[paddr_num][i] = (*p_enet_addr)[i];
2061 /* put in hardware */
2062 return hw_add_addr_in_paddr(ugeth, p_enet_addr, paddr_num);
2063}
2064#endif /* CONFIG_UGETH_FILTERING */
2065
18a8e864 2066static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
ce973b14
LY		 2067 u8 paddr_num)
2068{
2069 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
2070 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
2071}
2072
18a8e864 2073static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
ce973b14
LY		 2074{
2075 u16 i, j;
2076 u8 *bd;
2077
2078 if (!ugeth)
2079 return;
2080
2081 if (ugeth->uccf)
2082 ucc_fast_free(ugeth->uccf);
2083
2084 if (ugeth->p_thread_data_tx) {
2085 qe_muram_free(ugeth->thread_dat_tx_offset);
2086 ugeth->p_thread_data_tx = NULL;
2087 }
2088 if (ugeth->p_thread_data_rx) {
2089 qe_muram_free(ugeth->thread_dat_rx_offset);
2090 ugeth->p_thread_data_rx = NULL;
2091 }
2092 if (ugeth->p_exf_glbl_param) {
2093 qe_muram_free(ugeth->exf_glbl_param_offset);
2094 ugeth->p_exf_glbl_param = NULL;
2095 }
2096 if (ugeth->p_rx_glbl_pram) {
2097 qe_muram_free(ugeth->rx_glbl_pram_offset);
2098 ugeth->p_rx_glbl_pram = NULL;
2099 }
2100 if (ugeth->p_tx_glbl_pram) {
2101 qe_muram_free(ugeth->tx_glbl_pram_offset);
2102 ugeth->p_tx_glbl_pram = NULL;
2103 }
2104 if (ugeth->p_send_q_mem_reg) {
2105 qe_muram_free(ugeth->send_q_mem_reg_offset);
2106 ugeth->p_send_q_mem_reg = NULL;
2107 }
2108 if (ugeth->p_scheduler) {
2109 qe_muram_free(ugeth->scheduler_offset);
2110 ugeth->p_scheduler = NULL;
2111 }
2112 if (ugeth->p_tx_fw_statistics_pram) {
2113 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
2114 ugeth->p_tx_fw_statistics_pram = NULL;
2115 }
2116 if (ugeth->p_rx_fw_statistics_pram) {
2117 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
2118 ugeth->p_rx_fw_statistics_pram = NULL;
2119 }
2120 if (ugeth->p_rx_irq_coalescing_tbl) {
2121 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
2122 ugeth->p_rx_irq_coalescing_tbl = NULL;
2123 }
2124 if (ugeth->p_rx_bd_qs_tbl) {
2125 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
2126 ugeth->p_rx_bd_qs_tbl = NULL;
2127 }
2128 if (ugeth->p_init_enet_param_shadow) {
2129 return_init_enet_entries(ugeth,
2130 &(ugeth->p_init_enet_param_shadow->
2131 rxthread[0]),
2132 ENET_INIT_PARAM_MAX_ENTRIES_RX,
2133 ugeth->ug_info->riscRx, 1);
2134 return_init_enet_entries(ugeth,
2135 &(ugeth->p_init_enet_param_shadow->
2136 txthread[0]),
2137 ENET_INIT_PARAM_MAX_ENTRIES_TX,
2138 ugeth->ug_info->riscTx, 0);
2139 kfree(ugeth->p_init_enet_param_shadow);
2140 ugeth->p_init_enet_param_shadow = NULL;
2141 }
2142 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
2143 bd = ugeth->p_tx_bd_ring[i];
2144 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
2145 if (ugeth->tx_skbuff[i][j]) {
2146 dma_unmap_single(NULL,
18a8e864
LY		 2147 ((qe_bd_t *)bd)->buf,
2148 (in_be32((u32 *)bd) &
ce973b14
LY		 2149 BD_LENGTH_MASK),
2150 DMA_TO_DEVICE);
2151 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
2152 ugeth->tx_skbuff[i][j] = NULL;
2153 }
2154 }
2155
2156 kfree(ugeth->tx_skbuff[i]);
2157
2158 if (ugeth->p_tx_bd_ring[i]) {
2159 if (ugeth->ug_info->uf_info.bd_mem_part ==
2160 MEM_PART_SYSTEM)
2161 kfree((void *)ugeth->tx_bd_ring_offset[i]);
2162 else if (ugeth->ug_info->uf_info.bd_mem_part ==
2163 MEM_PART_MURAM)
2164 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
2165 ugeth->p_tx_bd_ring[i] = NULL;
2166 }
2167 }
2168 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
2169 if (ugeth->p_rx_bd_ring[i]) {
2170 /* Return existing data buffers in ring */
2171 bd = ugeth->p_rx_bd_ring[i];
2172 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
2173 if (ugeth->rx_skbuff[i][j]) {
18a8e864
LY		 2174 dma_unmap_single(NULL,
2175 ((struct qe_bd *)bd)->buf,
2176 ugeth->ug_info->
2177 uf_info.max_rx_buf_length +
2178 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
2179 DMA_FROM_DEVICE);
2180 dev_kfree_skb_any(
2181 ugeth->rx_skbuff[i][j]);
ce973b14
LY		 2182 ugeth->rx_skbuff[i][j] = NULL;
2183 }
18a8e864 2184 bd += sizeof(struct qe_bd);
ce973b14
LY		 2185 }
2186
2187 kfree(ugeth->rx_skbuff[i]);
2188
2189 if (ugeth->ug_info->uf_info.bd_mem_part ==
2190 MEM_PART_SYSTEM)
2191 kfree((void *)ugeth->rx_bd_ring_offset[i]);
2192 else if (ugeth->ug_info->uf_info.bd_mem_part ==
2193 MEM_PART_MURAM)
2194 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
2195 ugeth->p_rx_bd_ring[i] = NULL;
2196 }
2197 }
2198 while (!list_empty(&ugeth->group_hash_q))
2199 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2200 (dequeue(&ugeth->group_hash_q)));
2201 while (!list_empty(&ugeth->ind_hash_q))
2202 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2203 (dequeue(&ugeth->ind_hash_q)));
2204
2205}
2206
2207static void ucc_geth_set_multi(struct net_device *dev)
2208{
18a8e864 2209 struct ucc_geth_private *ugeth;
ce973b14 2210 struct dev_mc_list *dmi;
18a8e864
LY		 2211 struct ucc_fast *uf_regs;
2212 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2213 u8 tempaddr[6];
ce973b14
LY		 2214 u8 *mcptr, *tdptr;
2215 int i, j;
2216
2217 ugeth = netdev_priv(dev);
2218
2219 uf_regs = ugeth->uccf->uf_regs;
2220
2221 if (dev->flags & IFF_PROMISC) {
2222
ce973b14
LY		 2223 uf_regs->upsmr |= UPSMR_PRO;
2224
2225 } else {
2226
2227 uf_regs->upsmr &= ~UPSMR_PRO;
2228
2229 p_82xx_addr_filt =
18a8e864 2230 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
ce973b14
LY		 2231 p_rx_glbl_pram->addressfiltering;
2232
2233 if (dev->flags & IFF_ALLMULTI) {
2234 /* Catch all multicast addresses, so set the
2235 * filter to all 1's.
2236 */
2237 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2238 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2239 } else {
2240 /* Clear filter and add the addresses in the list.
2241 */
2242 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2243 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2244
2245 dmi = dev->mc_list;
2246
2247 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2248
2249 /* Only support group multicast for now.
2250 */
2251 if (!(dmi->dmi_addr[0] & 1))
2252 continue;
2253
2254 /* The address in dmi_addr is LSB first,
2255 * and taddr is MSB first. We have to
2256 * copy bytes MSB first from dmi_addr.
2257 */
2258 mcptr = (u8 *) dmi->dmi_addr + 5;
18a8e864 2259 tdptr = (u8 *) tempaddr;
ce973b14
LY		 2260 for (j = 0; j < 6; j++)
2261 *tdptr++ = *mcptr--;
2262
2263 /* Ask CPM to run CRC and set bit in
2264 * filter mask.
2265 */
18a8e864 2266 hw_add_addr_in_hash(ugeth, tempaddr);
ce973b14
LY		 2267 }
2268 }
2269 }
2270}
2271
18a8e864 2272static void ucc_geth_stop(struct ucc_geth_private *ugeth)
ce973b14 2273{
18a8e864 2274 struct ucc_geth *ug_regs = ugeth->ug_regs;
728de4c9 2275 struct phy_device *phydev = ugeth->phydev;
ce973b14
LY		 2276 u32 tempval;
2277
2278 ugeth_vdbg("%s: IN", __FUNCTION__);
2279
2280 /* Disable the controller */
2281 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2282
2283 /* Tell the kernel the link is down */
728de4c9 2284 phy_stop(phydev);
ce973b14
LY		 2285
2286 /* Mask all interrupts */
2287 out_be32(ugeth->uccf->p_ucce, 0x00000000);
2288
2289 /* Clear all interrupts */
2290 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2291
2292 /* Disable Rx and Tx */
2293 tempval = in_be32(&ug_regs->maccfg1);
2294 tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2295 out_be32(&ug_regs->maccfg1, tempval);
2296
ce973b14
LY		 2297 free_irq(ugeth->ug_info->uf_info.irq, ugeth->dev);
2298
ce973b14
LY		 2299 ucc_geth_memclean(ugeth);
2300}
2301
728de4c9 2302static int ucc_struct_init(struct ucc_geth_private *ugeth)
ce973b14 2303{
18a8e864
LY		 2304 struct ucc_geth_info *ug_info;
2305 struct ucc_fast_info *uf_info;
728de4c9 2306 int i;
ce973b14
LY		 2307
2308 ug_info = ugeth->ug_info;
2309 uf_info = &ug_info->uf_info;
2310
2311 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2312 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2313 ugeth_err("%s: Bad memory partition value.", __FUNCTION__);
2314 return -EINVAL;
2315 }
2316
2317 /* Rx BD lengths */
2318 for (i = 0; i < ug_info->numQueuesRx; i++) {
2319 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2320 (ug_info->bdRingLenRx[i] %
2321 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2322 ugeth_err
2323 ("%s: Rx BD ring length must be multiple of 4,"
2324 " no smaller than 8.", __FUNCTION__);
2325 return -EINVAL;
2326 }
2327 }
2328
2329 /* Tx BD lengths */
2330 for (i = 0; i < ug_info->numQueuesTx; i++) {
2331 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2332 ugeth_err
2333 ("%s: Tx BD ring length must be no smaller than 2.",
2334 __FUNCTION__);
2335 return -EINVAL;
2336 }
2337 }
2338
2339 /* mrblr */
2340 if ((uf_info->max_rx_buf_length == 0) ||
2341 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2342 ugeth_err
2343 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2344 __FUNCTION__);
2345 return -EINVAL;
2346 }
2347
2348 /* num Tx queues */
2349 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2350 ugeth_err("%s: number of tx queues too large.", __FUNCTION__);
2351 return -EINVAL;
2352 }
2353
2354 /* num Rx queues */
2355 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2356 ugeth_err("%s: number of rx queues too large.", __FUNCTION__);
2357 return -EINVAL;
2358 }
2359
2360 /* l2qt */
2361 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2362 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2363 ugeth_err
2364 ("%s: VLAN priority table entry must not be"
2365 " larger than number of Rx queues.",
2366 __FUNCTION__);
2367 return -EINVAL;
2368 }
2369 }
2370
2371 /* l3qt */
2372 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2373 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2374 ugeth_err
2375 ("%s: IP priority table entry must not be"
2376 " larger than number of Rx queues.",
2377 __FUNCTION__);
2378 return -EINVAL;
2379 }
2380 }
2381
2382 if (ug_info->cam && !ug_info->ecamptr) {
2383 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2384 __FUNCTION__);
2385 return -EINVAL;
2386 }
2387
2388 if ((ug_info->numStationAddresses !=
2389 UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2390 && ug_info->rxExtendedFiltering) {
2391 ugeth_err("%s: Number of station addresses greater than 1 "
2392 "not allowed in extended parsing mode.",
2393 __FUNCTION__);
2394 return -EINVAL;
2395 }
2396
2397 /* Generate uccm_mask for receive */
2398 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2399 for (i = 0; i < ug_info->numQueuesRx; i++)
2400 uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i);
2401
2402 for (i = 0; i < ug_info->numQueuesTx; i++)
2403 uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i);
2404 /* Initialize the general fast UCC block. */
728de4c9 2405 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
ce973b14
LY		 2406 ugeth_err("%s: Failed to init uccf.", __FUNCTION__);
2407 ucc_geth_memclean(ugeth);
2408 return -ENOMEM;
2409 }
728de4c9
KP		 2410
2411 ugeth->ug_regs = (struct ucc_geth *) ioremap(uf_info->regs, sizeof(struct ucc_geth));
2412
2413 return 0;
2414}
2415
2416static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2417{
2418 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2419 struct ucc_geth_init_pram *p_init_enet_pram;
2420 struct ucc_fast_private *uccf;
2421 struct ucc_geth_info *ug_info;
2422 struct ucc_fast_info *uf_info;
2423 struct ucc_fast *uf_regs;
2424 struct ucc_geth *ug_regs;
2425 int ret_val = -EINVAL;
2426 u32 remoder = UCC_GETH_REMODER_INIT;
2427 u32 init_enet_pram_offset, cecr_subblock, command, maccfg1;
2428 u32 ifstat, i, j, size, l2qt, l3qt, length;
2429 u16 temoder = UCC_GETH_TEMODER_INIT;
2430 u16 test;
2431 u8 function_code = 0;
2432 u8 *bd, *endOfRing;
2433 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2434
2435 ugeth_vdbg("%s: IN", __FUNCTION__);
2436 uccf = ugeth->uccf;
2437 ug_info = ugeth->ug_info;
2438 uf_info = &ug_info->uf_info;
2439 uf_regs = uccf->uf_regs;
2440 ug_regs = ugeth->ug_regs;
ce973b14
LY		 2441
2442 switch (ug_info->numThreadsRx) {
2443 case UCC_GETH_NUM_OF_THREADS_1:
2444 numThreadsRxNumerical = 1;
2445 break;
2446 case UCC_GETH_NUM_OF_THREADS_2:
2447 numThreadsRxNumerical = 2;
2448 break;
2449 case UCC_GETH_NUM_OF_THREADS_4:
2450 numThreadsRxNumerical = 4;
2451 break;
2452 case UCC_GETH_NUM_OF_THREADS_6:
2453 numThreadsRxNumerical = 6;
2454 break;
2455 case UCC_GETH_NUM_OF_THREADS_8:
2456 numThreadsRxNumerical = 8;
2457 break;
2458 default:
2459 ugeth_err("%s: Bad number of Rx threads value.", __FUNCTION__);
2460 ucc_geth_memclean(ugeth);
2461 return -EINVAL;
2462 break;
2463 }
2464
2465 switch (ug_info->numThreadsTx) {
2466 case UCC_GETH_NUM_OF_THREADS_1:
2467 numThreadsTxNumerical = 1;
2468 break;
2469 case UCC_GETH_NUM_OF_THREADS_2:
2470 numThreadsTxNumerical = 2;
2471 break;
2472 case UCC_GETH_NUM_OF_THREADS_4:
2473 numThreadsTxNumerical = 4;
2474 break;
2475 case UCC_GETH_NUM_OF_THREADS_6:
2476 numThreadsTxNumerical = 6;
2477 break;
2478 case UCC_GETH_NUM_OF_THREADS_8:
2479 numThreadsTxNumerical = 8;
2480 break;
2481 default:
2482 ugeth_err("%s: Bad number of Tx threads value.", __FUNCTION__);
2483 ucc_geth_memclean(ugeth);
2484 return -EINVAL;
2485 break;
2486 }
2487
2488 /* Calculate rx_extended_features */
2489 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2490 ug_info->ipAddressAlignment ||
2491 (ug_info->numStationAddresses !=
2492 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2493
2494 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2495 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2496 || (ug_info->vlanOperationNonTagged !=
2497 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2498
ce973b14
LY		 2499 init_default_reg_vals(&uf_regs->upsmr,
2500 &ug_regs->maccfg1, &ug_regs->maccfg2);
2501
2502 /* Set UPSMR */
2503 /* For more details see the hardware spec. */
2504 init_rx_parameters(ug_info->bro,
2505 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2506
2507 /* We're going to ignore other registers for now, */
2508 /* except as needed to get up and running */
2509
2510 /* Set MACCFG1 */
2511 /* For more details see the hardware spec. */
2512 init_flow_control_params(ug_info->aufc,
2513 ug_info->receiveFlowControl,
2514 1,
2515 ug_info->pausePeriod,
2516 ug_info->extensionField,
2517 &uf_regs->upsmr,
2518 &ug_regs->uempr, &ug_regs->maccfg1);
2519
2520 maccfg1 = in_be32(&ug_regs->maccfg1);
2521 maccfg1 |= MACCFG1_ENABLE_RX;
2522 maccfg1 |= MACCFG1_ENABLE_TX;
2523 out_be32(&ug_regs->maccfg1, maccfg1);
2524
2525 /* Set IPGIFG */
2526 /* For more details see the hardware spec. */
2527 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2528 ug_info->nonBackToBackIfgPart2,
2529 ug_info->
2530 miminumInterFrameGapEnforcement,
2531 ug_info->backToBackInterFrameGap,
2532 &ug_regs->ipgifg);
2533 if (ret_val != 0) {
2534 ugeth_err("%s: IPGIFG initialization parameter too large.",
2535 __FUNCTION__);
2536 ucc_geth_memclean(ugeth);
2537 return ret_val;
2538 }
2539
2540 /* Set HAFDUP */
2541 /* For more details see the hardware spec. */
2542 ret_val = init_half_duplex_params(ug_info->altBeb,
2543 ug_info->backPressureNoBackoff,
2544 ug_info->noBackoff,
2545 ug_info->excessDefer,
2546 ug_info->altBebTruncation,
2547 ug_info->maxRetransmission,
2548 ug_info->collisionWindow,
2549 &ug_regs->hafdup);
2550 if (ret_val != 0) {
2551 ugeth_err("%s: Half Duplex initialization parameter too large.",
2552 __FUNCTION__);
2553 ucc_geth_memclean(ugeth);
2554 return ret_val;
2555 }
2556
2557 /* Set IFSTAT */
2558 /* For more details see the hardware spec. */
2559 /* Read only - resets upon read */
2560 ifstat = in_be32(&ug_regs->ifstat);
2561
2562 /* Clear UEMPR */
2563 /* For more details see the hardware spec. */
2564 out_be32(&ug_regs->uempr, 0);
2565
2566 /* Set UESCR */
2567 /* For more details see the hardware spec. */
2568 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2569 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2570 0, &uf_regs->upsmr, &ug_regs->uescr);
2571
2572 /* Allocate Tx bds */
2573 for (j = 0; j < ug_info->numQueuesTx; j++) {
2574 /* Allocate in multiple of
2575 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2576 according to spec */
18a8e864 2577 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
ce973b14
LY		 2578 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2579 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
18a8e864 2580 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
ce973b14
LY		 2581 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2582 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2583 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2584 u32 align = 4;
2585 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2586 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2587 ugeth->tx_bd_ring_offset[j] =
04b588d7
AD		 2588 kmalloc((u32) (length + align), GFP_KERNEL);
2589
ce973b14
LY		 2590 if (ugeth->tx_bd_ring_offset[j] != 0)
2591 ugeth->p_tx_bd_ring[j] =
2592 (void*)((ugeth->tx_bd_ring_offset[j] +
2593 align) & ~(align - 1));
2594 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2595 ugeth->tx_bd_ring_offset[j] =
2596 qe_muram_alloc(length,
2597 UCC_GETH_TX_BD_RING_ALIGNMENT);
2598 if (!IS_MURAM_ERR(ugeth->tx_bd_ring_offset[j]))
2599 ugeth->p_tx_bd_ring[j] =
2600 (u8 *) qe_muram_addr(ugeth->
2601 tx_bd_ring_offset[j]);
2602 }
2603 if (!ugeth->p_tx_bd_ring[j]) {
2604 ugeth_err
2605 ("%s: Can not allocate memory for Tx bd rings.",
2606 __FUNCTION__);
2607 ucc_geth_memclean(ugeth);
2608 return -ENOMEM;
2609 }
2610 /* Zero unused end of bd ring, according to spec */
2611 memset(ugeth->p_tx_bd_ring[j] +
18a8e864
LY		 2612 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd), 0,
2613 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
ce973b14
LY		 2614 }
2615
2616 /* Allocate Rx bds */
2617 for (j = 0; j < ug_info->numQueuesRx; j++) {
18a8e864 2618 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
ce973b14
LY		 2619 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2620 u32 align = 4;
2621 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2622 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2623 ugeth->rx_bd_ring_offset[j] =
04b588d7 2624 kmalloc((u32) (length + align), GFP_KERNEL);
ce973b14
LY		 2625 if (ugeth->rx_bd_ring_offset[j] != 0)
2626 ugeth->p_rx_bd_ring[j] =
2627 (void*)((ugeth->rx_bd_ring_offset[j] +
2628 align) & ~(align - 1));
2629 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2630 ugeth->rx_bd_ring_offset[j] =
2631 qe_muram_alloc(length,
2632 UCC_GETH_RX_BD_RING_ALIGNMENT);
2633 if (!IS_MURAM_ERR(ugeth->rx_bd_ring_offset[j]))
2634 ugeth->p_rx_bd_ring[j] =
2635 (u8 *) qe_muram_addr(ugeth->
2636 rx_bd_ring_offset[j]);
2637 }
2638 if (!ugeth->p_rx_bd_ring[j]) {
2639 ugeth_err
2640 ("%s: Can not allocate memory for Rx bd rings.",
2641 __FUNCTION__);
2642 ucc_geth_memclean(ugeth);
2643 return -ENOMEM;
2644 }
2645 }
2646
2647 /* Init Tx bds */
2648 for (j = 0; j < ug_info->numQueuesTx; j++) {
2649 /* Setup the skbuff rings */
04b588d7
AD		 2650 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2651 ugeth->ug_info->bdRingLenTx[j],
2652 GFP_KERNEL);
ce973b14
LY		 2653
2654 if (ugeth->tx_skbuff[j] == NULL) {
2655 ugeth_err("%s: Could not allocate tx_skbuff",
2656 __FUNCTION__);
2657 ucc_geth_memclean(ugeth);
2658 return -ENOMEM;
2659 }
2660
2661 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2662 ugeth->tx_skbuff[j][i] = NULL;
2663
2664 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2665 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2666 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
18a8e864
LY		 2667 /* clear bd buffer */
2668 out_be32(&((struct qe_bd *)bd)->buf, 0);
2669 /* set bd status and length */
2670 out_be32((u32 *)bd, 0);
2671 bd += sizeof(struct qe_bd);
ce973b14 2672 }
18a8e864
LY		 2673 bd -= sizeof(struct qe_bd);
2674 /* set bd status and length */
2675 out_be32((u32 *)bd, T_W); /* for last BD set Wrap bit */
ce973b14
LY		 2676 }
2677
2678 /* Init Rx bds */
2679 for (j = 0; j < ug_info->numQueuesRx; j++) {
2680 /* Setup the skbuff rings */
04b588d7
AD		 2681 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2682 ugeth->ug_info->bdRingLenRx[j],
2683 GFP_KERNEL);
ce973b14
LY		 2684
2685 if (ugeth->rx_skbuff[j] == NULL) {
2686 ugeth_err("%s: Could not allocate rx_skbuff",
2687 __FUNCTION__);
2688 ucc_geth_memclean(ugeth);
2689 return -ENOMEM;
2690 }
2691
2692 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2693 ugeth->rx_skbuff[j][i] = NULL;
2694
2695 ugeth->skb_currx[j] = 0;
2696 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2697 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
18a8e864
LY		 2698 /* set bd status and length */
2699 out_be32((u32 *)bd, R_I);
2700 /* clear bd buffer */
2701 out_be32(&((struct qe_bd *)bd)->buf, 0);
2702 bd += sizeof(struct qe_bd);
ce973b14 2703 }
18a8e864
LY		 2704 bd -= sizeof(struct qe_bd);
2705 /* set bd status and length */
2706 out_be32((u32 *)bd, R_W); /* for last BD set Wrap bit */
ce973b14
LY		 2707 }
2708
2709 /*
2710 * Global PRAM
2711 */
2712 /* Tx global PRAM */
2713 /* Allocate global tx parameter RAM page */
2714 ugeth->tx_glbl_pram_offset =
18a8e864 2715 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
ce973b14
LY		 2716 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2717 if (IS_MURAM_ERR(ugeth->tx_glbl_pram_offset)) {
2718 ugeth_err
2719 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2720 __FUNCTION__);
2721 ucc_geth_memclean(ugeth);
2722 return -ENOMEM;
2723 }
2724 ugeth->p_tx_glbl_pram =
18a8e864 2725 (struct ucc_geth_tx_global_pram *) qe_muram_addr(ugeth->
ce973b14
LY		 2726 tx_glbl_pram_offset);
2727 /* Zero out p_tx_glbl_pram */
18a8e864 2728 memset(ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
ce973b14
LY		 2729
2730 /* Fill global PRAM */
2731
2732 /* TQPTR */
2733 /* Size varies with number of Tx threads */
2734 ugeth->thread_dat_tx_offset =
2735 qe_muram_alloc(numThreadsTxNumerical *
18a8e864 2736 sizeof(struct ucc_geth_thread_data_tx) +
ce973b14
LY		 2737 32 * (numThreadsTxNumerical == 1),
2738 UCC_GETH_THREAD_DATA_ALIGNMENT);
2739 if (IS_MURAM_ERR(ugeth->thread_dat_tx_offset)) {
2740 ugeth_err
2741 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2742 __FUNCTION__);
2743 ucc_geth_memclean(ugeth);
2744 return -ENOMEM;
2745 }
2746
2747 ugeth->p_thread_data_tx =
18a8e864 2748 (struct ucc_geth_thread_data_tx *) qe_muram_addr(ugeth->
ce973b14
LY		 2749 thread_dat_tx_offset);
2750 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2751
2752 /* vtagtable */
2753 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2754 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2755 ug_info->vtagtable[i]);
2756
2757 /* iphoffset */
2758 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2759 ugeth->p_tx_glbl_pram->iphoffset[i] = ug_info->iphoffset[i];
2760
2761 /* SQPTR */
2762 /* Size varies with number of Tx queues */
2763 ugeth->send_q_mem_reg_offset =
2764 qe_muram_alloc(ug_info->numQueuesTx *
18a8e864 2765 sizeof(struct ucc_geth_send_queue_qd),
ce973b14
LY		 2766 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2767 if (IS_MURAM_ERR(ugeth->send_q_mem_reg_offset)) {
2768 ugeth_err
2769 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2770 __FUNCTION__);
2771 ucc_geth_memclean(ugeth);
2772 return -ENOMEM;
2773 }
2774
2775 ugeth->p_send_q_mem_reg =
18a8e864 2776 (struct ucc_geth_send_queue_mem_region *) qe_muram_addr(ugeth->
ce973b14
LY		 2777 send_q_mem_reg_offset);
2778 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2779
2780 /* Setup the table */
2781 /* Assume BD rings are already established */
2782 for (i = 0; i < ug_info->numQueuesTx; i++) {
2783 endOfRing =
2784 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
18a8e864 2785 1) * sizeof(struct qe_bd);
ce973b14
LY		 2786 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2787 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2788 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2789 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2790 last_bd_completed_address,
2791 (u32) virt_to_phys(endOfRing));
2792 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2793 MEM_PART_MURAM) {
2794 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2795 (u32) immrbar_virt_to_phys(ugeth->
2796 p_tx_bd_ring[i]));
2797 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2798 last_bd_completed_address,
2799 (u32) immrbar_virt_to_phys(endOfRing));
2800 }
2801 }
2802
2803 /* schedulerbasepointer */
2804
2805 if (ug_info->numQueuesTx > 1) {
2806 /* scheduler exists only if more than 1 tx queue */
2807 ugeth->scheduler_offset =
18a8e864 2808 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
ce973b14
LY		 2809 UCC_GETH_SCHEDULER_ALIGNMENT);
2810 if (IS_MURAM_ERR(ugeth->scheduler_offset)) {
2811 ugeth_err
2812 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2813 __FUNCTION__);
2814 ucc_geth_memclean(ugeth);
2815 return -ENOMEM;
2816 }
2817
2818 ugeth->p_scheduler =
18a8e864 2819 (struct ucc_geth_scheduler *) qe_muram_addr(ugeth->
ce973b14
LY		 2820 scheduler_offset);
2821 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2822 ugeth->scheduler_offset);
2823 /* Zero out p_scheduler */
18a8e864 2824 memset(ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
ce973b14
LY		 2825
2826 /* Set values in scheduler */
2827 out_be32(&ugeth->p_scheduler->mblinterval,
2828 ug_info->mblinterval);
2829 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2830 ug_info->nortsrbytetime);
2831 ugeth->p_scheduler->fracsiz = ug_info->fracsiz;
2832 ugeth->p_scheduler->strictpriorityq = ug_info->strictpriorityq;
2833 ugeth->p_scheduler->txasap = ug_info->txasap;
2834 ugeth->p_scheduler->extrabw = ug_info->extrabw;
2835 for (i = 0; i < NUM_TX_QUEUES; i++)
2836 ugeth->p_scheduler->weightfactor[i] =
2837 ug_info->weightfactor[i];
2838
2839 /* Set pointers to cpucount registers in scheduler */
2840 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2841 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2842 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2843 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2844 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2845 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2846 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2847 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2848 }
2849
2850 /* schedulerbasepointer */
2851 /* TxRMON_PTR (statistics) */
2852 if (ug_info->
2853 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2854 ugeth->tx_fw_statistics_pram_offset =
2855 qe_muram_alloc(sizeof
18a8e864 2856 (struct ucc_geth_tx_firmware_statistics_pram),
ce973b14
LY		 2857 UCC_GETH_TX_STATISTICS_ALIGNMENT);
2858 if (IS_MURAM_ERR(ugeth->tx_fw_statistics_pram_offset)) {
2859 ugeth_err
2860 ("%s: Can not allocate DPRAM memory for"
2861 " p_tx_fw_statistics_pram.", __FUNCTION__);
2862 ucc_geth_memclean(ugeth);
2863 return -ENOMEM;
2864 }
2865 ugeth->p_tx_fw_statistics_pram =
18a8e864 2866 (struct ucc_geth_tx_firmware_statistics_pram *)
ce973b14
LY		 2867 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2868 /* Zero out p_tx_fw_statistics_pram */
2869 memset(ugeth->p_tx_fw_statistics_pram,
18a8e864 2870 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
ce973b14
LY		 2871 }
2872
2873 /* temoder */
2874 /* Already has speed set */
2875
2876 if (ug_info->numQueuesTx > 1)
2877 temoder |= TEMODER_SCHEDULER_ENABLE;
2878 if (ug_info->ipCheckSumGenerate)
2879 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2880 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2881 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2882
2883 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2884
2885 /* Function code register value to be used later */
2886 function_code = QE_BMR_BYTE_ORDER_BO_MOT | UCC_FAST_FUNCTION_CODE_GBL;
2887 /* Required for QE */
2888
2889 /* function code register */
2890 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2891
2892 /* Rx global PRAM */
2893 /* Allocate global rx parameter RAM page */
2894 ugeth->rx_glbl_pram_offset =
18a8e864 2895 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
ce973b14
LY		 2896 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2897 if (IS_MURAM_ERR(ugeth->rx_glbl_pram_offset)) {
2898 ugeth_err
2899 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2900 __FUNCTION__);
2901 ucc_geth_memclean(ugeth);
2902 return -ENOMEM;
2903 }
2904 ugeth->p_rx_glbl_pram =
18a8e864 2905 (struct ucc_geth_rx_global_pram *) qe_muram_addr(ugeth->
ce973b14
LY		 2906 rx_glbl_pram_offset);
2907 /* Zero out p_rx_glbl_pram */
18a8e864 2908 memset(ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
ce973b14
LY		 2909
2910 /* Fill global PRAM */
2911
2912 /* RQPTR */
2913 /* Size varies with number of Rx threads */
2914 ugeth->thread_dat_rx_offset =
2915 qe_muram_alloc(numThreadsRxNumerical *
18a8e864 2916 sizeof(struct ucc_geth_thread_data_rx),
ce973b14
LY		 2917 UCC_GETH_THREAD_DATA_ALIGNMENT);
2918 if (IS_MURAM_ERR(ugeth->thread_dat_rx_offset)) {
2919 ugeth_err
2920 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2921 __FUNCTION__);
2922 ucc_geth_memclean(ugeth);
2923 return -ENOMEM;
2924 }
2925
2926 ugeth->p_thread_data_rx =
18a8e864 2927 (struct ucc_geth_thread_data_rx *) qe_muram_addr(ugeth->
ce973b14
LY		 2928 thread_dat_rx_offset);
2929 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2930
2931 /* typeorlen */
2932 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2933
2934 /* rxrmonbaseptr (statistics) */
2935 if (ug_info->
2936 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2937 ugeth->rx_fw_statistics_pram_offset =
2938 qe_muram_alloc(sizeof
18a8e864 2939 (struct ucc_geth_rx_firmware_statistics_pram),
ce973b14
LY		 2940 UCC_GETH_RX_STATISTICS_ALIGNMENT);
2941 if (IS_MURAM_ERR(ugeth->rx_fw_statistics_pram_offset)) {
2942 ugeth_err
2943 ("%s: Can not allocate DPRAM memory for"
2944 " p_rx_fw_statistics_pram.", __FUNCTION__);
2945 ucc_geth_memclean(ugeth);
2946 return -ENOMEM;
2947 }
2948 ugeth->p_rx_fw_statistics_pram =
18a8e864 2949 (struct ucc_geth_rx_firmware_statistics_pram *)
ce973b14
LY		 2950 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2951 /* Zero out p_rx_fw_statistics_pram */
2952 memset(ugeth->p_rx_fw_statistics_pram, 0,
18a8e864 2953 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
ce973b14
LY		 2954 }
2955
2956 /* intCoalescingPtr */
2957
2958 /* Size varies with number of Rx queues */
2959 ugeth->rx_irq_coalescing_tbl_offset =
2960 qe_muram_alloc(ug_info->numQueuesRx *
7563907e
MB		 2961 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2962 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
ce973b14
LY		 2963 if (IS_MURAM_ERR(ugeth->rx_irq_coalescing_tbl_offset)) {
2964 ugeth_err
2965 ("%s: Can not allocate DPRAM memory for"
2966 " p_rx_irq_coalescing_tbl.", __FUNCTION__);
2967 ucc_geth_memclean(ugeth);
2968 return -ENOMEM;
2969 }
2970
2971 ugeth->p_rx_irq_coalescing_tbl =
18a8e864 2972 (struct ucc_geth_rx_interrupt_coalescing_table *)
ce973b14
LY		 2973 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2974 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2975 ugeth->rx_irq_coalescing_tbl_offset);
2976
2977 /* Fill interrupt coalescing table */
2978 for (i = 0; i < ug_info->numQueuesRx; i++) {
2979 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2980 interruptcoalescingmaxvalue,
2981 ug_info->interruptcoalescingmaxvalue[i]);
2982 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2983 interruptcoalescingcounter,
2984 ug_info->interruptcoalescingmaxvalue[i]);
2985 }
2986
2987 /* MRBLR */
2988 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2989 &ugeth->p_rx_glbl_pram->mrblr);
2990 /* MFLR */
2991 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2992 /* MINFLR */
2993 init_min_frame_len(ug_info->minFrameLength,
2994 &ugeth->p_rx_glbl_pram->minflr,
2995 &ugeth->p_rx_glbl_pram->mrblr);
2996 /* MAXD1 */
2997 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2998 /* MAXD2 */
2999 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
3000
3001 /* l2qt */
3002 l2qt = 0;
3003 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
3004 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
3005 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
3006
3007 /* l3qt */
3008 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
3009 l3qt = 0;
3010 for (i = 0; i < 8; i++)
3011 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
18a8e864 3012 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
ce973b14
LY		 3013 }
3014
3015 /* vlantype */
3016 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
3017
3018 /* vlantci */
3019 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
3020
3021 /* ecamptr */
3022 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
3023
3024 /* RBDQPTR */
3025 /* Size varies with number of Rx queues */
3026 ugeth->rx_bd_qs_tbl_offset =
3027 qe_muram_alloc(ug_info->numQueuesRx *
18a8e864
LY		 3028 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3029 sizeof(struct ucc_geth_rx_prefetched_bds)),
ce973b14
LY		 3030 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
3031 if (IS_MURAM_ERR(ugeth->rx_bd_qs_tbl_offset)) {
3032 ugeth_err
3033 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
3034 __FUNCTION__);
3035 ucc_geth_memclean(ugeth);
3036 return -ENOMEM;
3037 }
3038
3039 ugeth->p_rx_bd_qs_tbl =
18a8e864 3040 (struct ucc_geth_rx_bd_queues_entry *) qe_muram_addr(ugeth->
ce973b14
LY		 3041 rx_bd_qs_tbl_offset);
3042 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
3043 /* Zero out p_rx_bd_qs_tbl */
3044 memset(ugeth->p_rx_bd_qs_tbl,
3045 0,
18a8e864
LY		 3046 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3047 sizeof(struct ucc_geth_rx_prefetched_bds)));
ce973b14
LY		 3048
3049 /* Setup the table */
3050 /* Assume BD rings are already established */
3051 for (i = 0; i < ug_info->numQueuesRx; i++) {
3052 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
3053 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3054 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
3055 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
3056 MEM_PART_MURAM) {
3057 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3058 (u32) immrbar_virt_to_phys(ugeth->
3059 p_rx_bd_ring[i]));
3060 }
3061 /* rest of fields handled by QE */
3062 }
3063
3064 /* remoder */
3065 /* Already has speed set */
3066
3067 if (ugeth->rx_extended_features)
3068 remoder |= REMODER_RX_EXTENDED_FEATURES;
3069 if (ug_info->rxExtendedFiltering)
3070 remoder |= REMODER_RX_EXTENDED_FILTERING;
3071 if (ug_info->dynamicMaxFrameLength)
3072 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
3073 if (ug_info->dynamicMinFrameLength)
3074 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
3075 remoder |=
3076 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
3077 remoder |=
3078 ug_info->
3079 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
3080 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
3081 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
3082 if (ug_info->ipCheckSumCheck)
3083 remoder |= REMODER_IP_CHECKSUM_CHECK;
3084 if (ug_info->ipAddressAlignment)
3085 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
3086 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
3087
3088 /* Note that this function must be called */
3089 /* ONLY AFTER p_tx_fw_statistics_pram */
3090 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
3091 init_firmware_statistics_gathering_mode((ug_info->
3092 statisticsMode &
3093 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
3094 (ug_info->statisticsMode &
3095 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
3096 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
3097 ugeth->tx_fw_statistics_pram_offset,
3098 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
3099 ugeth->rx_fw_statistics_pram_offset,
3100 &ugeth->p_tx_glbl_pram->temoder,
3101 &ugeth->p_rx_glbl_pram->remoder);
3102
3103 /* function code register */
3104 ugeth->p_rx_glbl_pram->rstate = function_code;
3105
3106 /* initialize extended filtering */
3107 if (ug_info->rxExtendedFiltering) {
3108 if (!ug_info->extendedFilteringChainPointer) {
3109 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
3110 __FUNCTION__);
3111 ucc_geth_memclean(ugeth);
3112 return -EINVAL;
3113 }
3114
3115 /* Allocate memory for extended filtering Mode Global
3116 Parameters */
3117 ugeth->exf_glbl_param_offset =
18a8e864 3118 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
ce973b14
LY		 3119 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
3120 if (IS_MURAM_ERR(ugeth->exf_glbl_param_offset)) {
3121 ugeth_err
3122 ("%s: Can not allocate DPRAM memory for"
3123 " p_exf_glbl_param.", __FUNCTION__);
3124 ucc_geth_memclean(ugeth);
3125 return -ENOMEM;
3126 }
3127
3128 ugeth->p_exf_glbl_param =
18a8e864 3129 (struct ucc_geth_exf_global_pram *) qe_muram_addr(ugeth->
ce973b14
LY		 3130 exf_glbl_param_offset);
3131 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
3132 ugeth->exf_glbl_param_offset);
3133 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
3134 (u32) ug_info->extendedFilteringChainPointer);
3135
3136 } else { /* initialize 82xx style address filtering */
3137
3138 /* Init individual address recognition registers to disabled */
3139
3140 for (j = 0; j < NUM_OF_PADDRS; j++)
3141 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
3142
3143 /* Create CQs for hash tables */
3144 if (ug_info->maxGroupAddrInHash > 0) {
3145 INIT_LIST_HEAD(&ugeth->group_hash_q);
3146 }
3147 if (ug_info->maxIndAddrInHash > 0) {
3148 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3149 }
3150 p_82xx_addr_filt =
18a8e864 3151 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
ce973b14
LY		 3152 p_rx_glbl_pram->addressfiltering;
3153
3154 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3155 ENET_ADDR_TYPE_GROUP);
3156 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3157 ENET_ADDR_TYPE_INDIVIDUAL);
3158 }
3159
3160 /*
3161 * Initialize UCC at QE level
3162 */
3163
3164 command = QE_INIT_TX_RX;
3165
3166 /* Allocate shadow InitEnet command parameter structure.
3167 * This is needed because after the InitEnet command is executed,
3168 * the structure in DPRAM is released, because DPRAM is a premium
3169 * resource.
3170 * This shadow structure keeps a copy of what was done so that the
3171 * allocated resources can be released when the channel is freed.
3172 */
3173 if (!(ugeth->p_init_enet_param_shadow =
04b588d7 3174 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
ce973b14
LY		 3175 ugeth_err
3176 ("%s: Can not allocate memory for"
3177 " p_UccInitEnetParamShadows.", __FUNCTION__);
3178 ucc_geth_memclean(ugeth);
3179 return -ENOMEM;
3180 }
3181 /* Zero out *p_init_enet_param_shadow */
3182 memset((char *)ugeth->p_init_enet_param_shadow,
18a8e864 3183 0, sizeof(struct ucc_geth_init_pram));
ce973b14
LY		 3184
3185 /* Fill shadow InitEnet command parameter structure */
3186
3187 ugeth->p_init_enet_param_shadow->resinit1 =
3188 ENET_INIT_PARAM_MAGIC_RES_INIT1;
3189 ugeth->p_init_enet_param_shadow->resinit2 =
3190 ENET_INIT_PARAM_MAGIC_RES_INIT2;
3191 ugeth->p_init_enet_param_shadow->resinit3 =
3192 ENET_INIT_PARAM_MAGIC_RES_INIT3;
3193 ugeth->p_init_enet_param_shadow->resinit4 =
3194 ENET_INIT_PARAM_MAGIC_RES_INIT4;
3195 ugeth->p_init_enet_param_shadow->resinit5 =
3196 ENET_INIT_PARAM_MAGIC_RES_INIT5;
3197 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3198 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
3199 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3200 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
3201
3202 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3203 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
3204 if ((ug_info->largestexternallookupkeysize !=
3205 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
3206 && (ug_info->largestexternallookupkeysize !=
3207 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3208 && (ug_info->largestexternallookupkeysize !=
3209 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
3210 ugeth_err("%s: Invalid largest External Lookup Key Size.",
3211 __FUNCTION__);
3212 ucc_geth_memclean(ugeth);
3213 return -EINVAL;
3214 }
3215 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3216 ug_info->largestexternallookupkeysize;
18a8e864 3217 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 3218 if (ug_info->rxExtendedFiltering) {
3219 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3220 if (ug_info->largestexternallookupkeysize ==
3221 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3222 size +=
3223 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3224 if (ug_info->largestexternallookupkeysize ==
3225 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3226 size +=
3227 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3228 }
3229
3230 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3231 p_init_enet_param_shadow->rxthread[0]),
3232 (u8) (numThreadsRxNumerical + 1)
3233 /* Rx needs one extra for terminator */
3234 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3235 ug_info->riscRx, 1)) != 0) {
3236 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3237 __FUNCTION__);
3238 ucc_geth_memclean(ugeth);
3239 return ret_val;
3240 }
3241
3242 ugeth->p_init_enet_param_shadow->txglobal =
3243 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3244 if ((ret_val =
3245 fill_init_enet_entries(ugeth,
3246 &(ugeth->p_init_enet_param_shadow->
3247 txthread[0]), numThreadsTxNumerical,
18a8e864 3248 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 3249 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3250 ug_info->riscTx, 0)) != 0) {
3251 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3252 __FUNCTION__);
3253 ucc_geth_memclean(ugeth);
3254 return ret_val;
3255 }
3256
3257 /* Load Rx bds with buffers */
3258 for (i = 0; i < ug_info->numQueuesRx; i++) {
3259 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3260 ugeth_err("%s: Can not fill Rx bds with buffers.",
3261 __FUNCTION__);
3262 ucc_geth_memclean(ugeth);
3263 return ret_val;
3264 }
3265 }
3266
3267 /* Allocate InitEnet command parameter structure */
18a8e864 3268 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
ce973b14
LY		 3269 if (IS_MURAM_ERR(init_enet_pram_offset)) {
3270 ugeth_err
3271 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3272 __FUNCTION__);
3273 ucc_geth_memclean(ugeth);
3274 return -ENOMEM;
3275 }
3276 p_init_enet_pram =
18a8e864 3277 (struct ucc_geth_init_pram *) qe_muram_addr(init_enet_pram_offset);
ce973b14
LY		 3278
3279 /* Copy shadow InitEnet command parameter structure into PRAM */
3280 p_init_enet_pram->resinit1 = ugeth->p_init_enet_param_shadow->resinit1;
3281 p_init_enet_pram->resinit2 = ugeth->p_init_enet_param_shadow->resinit2;
3282 p_init_enet_pram->resinit3 = ugeth->p_init_enet_param_shadow->resinit3;
3283 p_init_enet_pram->resinit4 = ugeth->p_init_enet_param_shadow->resinit4;
3284 out_be16(&p_init_enet_pram->resinit5,
3285 ugeth->p_init_enet_param_shadow->resinit5);
3286 p_init_enet_pram->largestexternallookupkeysize =
3287 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize;
3288 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3289 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3290 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3291 out_be32(&p_init_enet_pram->rxthread[i],
3292 ugeth->p_init_enet_param_shadow->rxthread[i]);
3293 out_be32(&p_init_enet_pram->txglobal,
3294 ugeth->p_init_enet_param_shadow->txglobal);
3295 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3296 out_be32(&p_init_enet_pram->txthread[i],
3297 ugeth->p_init_enet_param_shadow->txthread[i]);
3298
3299 /* Issue QE command */
3300 cecr_subblock =
3301 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 3302 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 3303 init_enet_pram_offset);
3304
3305 /* Free InitEnet command parameter */
3306 qe_muram_free(init_enet_pram_offset);
3307
3308 return 0;
3309}
3310
3311/* returns a net_device_stats structure pointer */
3312static struct net_device_stats *ucc_geth_get_stats(struct net_device *dev)
3313{
18a8e864 3314 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14
LY		 3315
3316 return &(ugeth->stats);
3317}
3318
3319/* ucc_geth_timeout gets called when a packet has not been
3320 * transmitted after a set amount of time.
3321 * For now, assume that clearing out all the structures, and
3322 * starting over will fix the problem. */
3323static void ucc_geth_timeout(struct net_device *dev)
3324{
18a8e864 3325 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14
LY		 3326
3327 ugeth_vdbg("%s: IN", __FUNCTION__);
3328
3329 ugeth->stats.tx_errors++;
3330
3331 ugeth_dump_regs(ugeth);
3332
3333 if (dev->flags & IFF_UP) {
3334 ucc_geth_stop(ugeth);
3335 ucc_geth_startup(ugeth);
3336 }
3337
3338 netif_schedule(dev);
3339}
3340
3341/* This is called by the kernel when a frame is ready for transmission. */
3342/* It is pointed to by the dev->hard_start_xmit function pointer */
3343static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3344{
18a8e864 3345 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14
LY		 3346 u8 *bd; /* BD pointer */
3347 u32 bd_status;
3348 u8 txQ = 0;
3349
3350 ugeth_vdbg("%s: IN", __FUNCTION__);
3351
3352 spin_lock_irq(&ugeth->lock);
3353
3354 ugeth->stats.tx_bytes += skb->len;
3355
3356 /* Start from the next BD that should be filled */
3357 bd = ugeth->txBd[txQ];
18a8e864 3358 bd_status = in_be32((u32 *)bd);
ce973b14
LY		 3359 /* Save the skb pointer so we can free it later */
3360 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3361
3362 /* Update the current skb pointer (wrapping if this was the last) */
3363 ugeth->skb_curtx[txQ] =
3364 (ugeth->skb_curtx[txQ] +
3365 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3366
3367 /* set up the buffer descriptor */
18a8e864 3368 out_be32(&((struct qe_bd *)bd)->buf,
ce973b14
LY		 3369 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE));
3370
18a8e864 3371 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
ce973b14
LY		 3372
3373 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3374
18a8e864
LY		 3375 /* set bd status and length */
3376 out_be32((u32 *)bd, bd_status);
ce973b14
LY		 3377
3378 dev->trans_start = jiffies;
3379
3380 /* Move to next BD in the ring */
3381 if (!(bd_status & T_W))
a394f013 3382 bd += sizeof(struct qe_bd);
ce973b14 3383 else
a394f013 3384 bd = ugeth->p_tx_bd_ring[txQ];
ce973b14
LY		 3385
3386 /* If the next BD still needs to be cleaned up, then the bds
3387 are full. We need to tell the kernel to stop sending us stuff. */
3388 if (bd == ugeth->confBd[txQ]) {
3389 if (!netif_queue_stopped(dev))
3390 netif_stop_queue(dev);
3391 }
3392
a394f013
LY		 3393 ugeth->txBd[txQ] = bd;
3394
ce973b14
LY		 3395 if (ugeth->p_scheduler) {
3396 ugeth->cpucount[txQ]++;
3397 /* Indicate to QE that there are more Tx bds ready for
3398 transmission */
3399 /* This is done by writing a running counter of the bd
3400 count to the scheduler PRAM. */
3401 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3402 }
3403
3404 spin_unlock_irq(&ugeth->lock);
3405
6f6881b8 3406 return 0;
ce973b14
LY		 3407}
3408
18a8e864 3409static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
ce973b14
LY		 3410{
3411 struct sk_buff *skb;
3412 u8 *bd;
3413 u16 length, howmany = 0;
3414 u32 bd_status;
3415 u8 *bdBuffer;
3416
3417 ugeth_vdbg("%s: IN", __FUNCTION__);
3418
ce973b14
LY		 3419 /* collect received buffers */
3420 bd = ugeth->rxBd[rxQ];
3421
18a8e864 3422 bd_status = in_be32((u32 *)bd);
ce973b14
LY		 3423
3424 /* while there are received buffers and BD is full (~R_E) */
3425 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
18a8e864 3426 bdBuffer = (u8 *) in_be32(&((struct qe_bd *)bd)->buf);
ce973b14
LY		 3427 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3428 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3429
3430 /* determine whether buffer is first, last, first and last
3431 (single buffer frame) or middle (not first and not last) */
3432 if (!skb ||
3433 (!(bd_status & (R_F | R_L))) ||
3434 (bd_status & R_ERRORS_FATAL)) {
3435 ugeth_vdbg("%s, %d: ERROR!!! skb - 0x%08x",
3436 __FUNCTION__, __LINE__, (u32) skb);
3437 if (skb)
3438 dev_kfree_skb_any(skb);
3439
3440 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3441 ugeth->stats.rx_dropped++;
3442 } else {
3443 ugeth->stats.rx_packets++;
3444 howmany++;
3445
3446 /* Prep the skb for the packet */
3447 skb_put(skb, length);
3448
3449 /* Tell the skb what kind of packet this is */
3450 skb->protocol = eth_type_trans(skb, ugeth->dev);
3451
3452 ugeth->stats.rx_bytes += length;
3453 /* Send the packet up the stack */
3454#ifdef CONFIG_UGETH_NAPI
3455 netif_receive_skb(skb);
3456#else
3457 netif_rx(skb);
3458#endif /* CONFIG_UGETH_NAPI */
3459 }
3460
3461 ugeth->dev->last_rx = jiffies;
3462
3463 skb = get_new_skb(ugeth, bd);
3464 if (!skb) {
3465 ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__);
ce973b14
LY		 3466 ugeth->stats.rx_dropped++;
3467 break;
3468 }
3469
3470 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3471
3472 /* update to point at the next skb */
3473 ugeth->skb_currx[rxQ] =
3474 (ugeth->skb_currx[rxQ] +
3475 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3476
3477 if (bd_status & R_W)
3478 bd = ugeth->p_rx_bd_ring[rxQ];
3479 else
18a8e864 3480 bd += sizeof(struct qe_bd);
ce973b14 3481
18a8e864 3482 bd_status = in_be32((u32 *)bd);
ce973b14
LY		 3483 }
3484
3485 ugeth->rxBd[rxQ] = bd;
ce973b14
LY		 3486 return howmany;
3487}
3488
3489static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3490{
3491 /* Start from the next BD that should be filled */
18a8e864 3492 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14
LY		 3493 u8 *bd; /* BD pointer */
3494 u32 bd_status;
3495
3496 bd = ugeth->confBd[txQ];
18a8e864 3497 bd_status = in_be32((u32 *)bd);
ce973b14
LY		 3498
3499 /* Normal processing. */
3500 while ((bd_status & T_R) == 0) {
3501 /* BD contains already transmitted buffer. */
3502 /* Handle the transmitted buffer and release */
3503 /* the BD to be used with the current frame */
3504
a394f013 3505 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
ce973b14
LY		 3506 break;
3507
3508 ugeth->stats.tx_packets++;
3509
3510 /* Free the sk buffer associated with this TxBD */
3511 dev_kfree_skb_irq(ugeth->
3512 tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3513 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3514 ugeth->skb_dirtytx[txQ] =
3515 (ugeth->skb_dirtytx[txQ] +
3516 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3517
3518 /* We freed a buffer, so now we can restart transmission */
3519 if (netif_queue_stopped(dev))
3520 netif_wake_queue(dev);
3521
3522 /* Advance the confirmation BD pointer */
3523 if (!(bd_status & T_W))
a394f013 3524 bd += sizeof(struct qe_bd);
ce973b14 3525 else
a394f013
LY		 3526 bd = ugeth->p_tx_bd_ring[txQ];
3527 bd_status = in_be32((u32 *)bd);
ce973b14 3528 }
a394f013 3529 ugeth->confBd[txQ] = bd;
ce973b14
LY		 3530 return 0;
3531}
3532
3533#ifdef CONFIG_UGETH_NAPI
3534static int ucc_geth_poll(struct net_device *dev, int *budget)
3535{
18a8e864 3536 struct ucc_geth_private *ugeth = netdev_priv(dev);
702ff12c
MR		 3537 struct ucc_geth_info *ug_info;
3538 struct ucc_fast_private *uccf;
ce973b14 3539 int howmany;
702ff12c
MR		 3540 u8 i;
3541 int rx_work_limit;
3542 register u32 uccm;
ce973b14 3543
702ff12c
MR		 3544 ug_info = ugeth->ug_info;
3545
3546 rx_work_limit = *budget;
ce973b14
LY		 3547 if (rx_work_limit > dev->quota)
3548 rx_work_limit = dev->quota;
3549
702ff12c
MR		 3550 howmany = 0;
3551
3552 for (i = 0; i < ug_info->numQueuesRx; i++) {
3553 howmany += ucc_geth_rx(ugeth, i, rx_work_limit);
3554 }
ce973b14
LY		 3555
3556 dev->quota -= howmany;
3557 rx_work_limit -= howmany;
3558 *budget -= howmany;
3559
702ff12c 3560 if (rx_work_limit > 0) {
ce973b14 3561 netif_rx_complete(dev);
702ff12c
MR		 3562 uccf = ugeth->uccf;
3563 uccm = in_be32(uccf->p_uccm);
3564 uccm |= UCCE_RX_EVENTS;
3565 out_be32(uccf->p_uccm, uccm);
3566 }
ce973b14 3567
702ff12c 3568 return (rx_work_limit > 0) ? 0 : 1;
ce973b14
LY		 3569}
3570#endif /* CONFIG_UGETH_NAPI */
3571
7d12e780 3572static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
ce973b14
LY		 3573{
3574 struct net_device *dev = (struct net_device *)info;
18a8e864
LY		 3575 struct ucc_geth_private *ugeth = netdev_priv(dev);
3576 struct ucc_fast_private *uccf;
3577 struct ucc_geth_info *ug_info;
702ff12c
MR		 3578 register u32 ucce;
3579 register u32 uccm;
3580#ifndef CONFIG_UGETH_NAPI
3581 register u32 rx_mask;
3582#endif
3583 register u32 tx_mask;
3584 u8 i;
ce973b14
LY		 3585
3586 ugeth_vdbg("%s: IN", __FUNCTION__);
3587
3588 if (!ugeth)
3589 return IRQ_NONE;
3590
3591 uccf = ugeth->uccf;
3592 ug_info = ugeth->ug_info;
3593
702ff12c
MR		 3594 /* read and clear events */
3595 ucce = (u32) in_be32(uccf->p_ucce);
3596 uccm = (u32) in_be32(uccf->p_uccm);
3597 ucce &= uccm;
3598 out_be32(uccf->p_ucce, ucce);
ce973b14 3599
702ff12c
MR		 3600 /* check for receive events that require processing */
3601 if (ucce & UCCE_RX_EVENTS) {
3602#ifdef CONFIG_UGETH_NAPI
3603 if (netif_rx_schedule_prep(dev)) {
3604 uccm &= ~UCCE_RX_EVENTS;
3605 out_be32(uccf->p_uccm, uccm);
3606 __netif_rx_schedule(dev);
3607 }
3608#else
3609 rx_mask = UCCE_RXBF_SINGLE_MASK;
ce973b14 3610 for (i = 0; i < ug_info->numQueuesRx; i++) {
702ff12c
MR		 3611 if (ucce & rx_mask)
3612 ucc_geth_rx(ugeth, i, (int)ugeth->ug_info->bdRingLenRx[i]);
3613 ucce &= ~rx_mask;
3614 rx_mask <<= 1;
ce973b14 3615 }
702ff12c
MR		 3616#endif /* CONFIG_UGETH_NAPI */
3617 }
ce973b14 3618
702ff12c
MR		 3619 /* Tx event processing */
3620 if (ucce & UCCE_TX_EVENTS) {
3621 spin_lock(&ugeth->lock);
3622 tx_mask = UCCE_TXBF_SINGLE_MASK;
ce973b14
LY		 3623 for (i = 0; i < ug_info->numQueuesTx; i++) {
3624 if (ucce & tx_mask)
3625 ucc_geth_tx(dev, i);
3626 ucce &= ~tx_mask;
3627 tx_mask <<= 1;
3628 }
702ff12c
MR		 3629 spin_unlock(&ugeth->lock);
3630 }
ce973b14 3631
702ff12c
MR		 3632 /* Errors and other events */
3633 if (ucce & UCCE_OTHER) {
ce973b14 3634 if (ucce & UCCE_BSY) {
ce973b14 3635 ugeth->stats.rx_errors++;
ce973b14 3636 }
702ff12c
MR		 3637 if (ucce & UCCE_TXE) {
3638 ugeth->stats.tx_errors++;
ce973b14
LY		 3639 }
3640 }
ce973b14
LY		 3641
3642 return IRQ_HANDLED;
3643}
3644
ce973b14
LY		 3645/* Called when something needs to use the ethernet device */
3646/* Returns 0 for success. */
3647static int ucc_geth_open(struct net_device *dev)
3648{
18a8e864 3649 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14
LY		 3650 int err;
3651
3652 ugeth_vdbg("%s: IN", __FUNCTION__);
3653
3654 /* Test station address */
3655 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3656 ugeth_err("%s: Multicast address used for station address"
3657 " - is this what you wanted?", __FUNCTION__);
3658 return -EINVAL;
3659 }
3660
728de4c9
KP		 3661 err = ucc_struct_init(ugeth);
3662 if (err) {
3663 ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
3664 return err;
3665 }
3666
ce973b14
LY		 3667 err = ucc_geth_startup(ugeth);
3668 if (err) {
3669 ugeth_err("%s: Cannot configure net device, aborting.",
3670 dev->name);
3671 return err;
3672 }
3673
3674 err = adjust_enet_interface(ugeth);
3675 if (err) {
3676 ugeth_err("%s: Cannot configure net device, aborting.",
3677 dev->name);
3678 return err;
3679 }
3680
3681 /* Set MACSTNADDR1, MACSTNADDR2 */
3682 /* For more details see the hardware spec. */
3683 init_mac_station_addr_regs(dev->dev_addr[0],
3684 dev->dev_addr[1],
3685 dev->dev_addr[2],
3686 dev->dev_addr[3],
3687 dev->dev_addr[4],
3688 dev->dev_addr[5],
3689 &ugeth->ug_regs->macstnaddr1,
3690 &ugeth->ug_regs->macstnaddr2);
3691
3692 err = init_phy(dev);
3693 if (err) {
728de4c9 3694 ugeth_err("%s: Cannot initialize PHY, aborting.", dev->name);
ce973b14
LY		 3695 return err;
3696 }
728de4c9
KP		 3697
3698 phy_start(ugeth->phydev);
3699
ce973b14
LY		 3700 err =
3701 request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 0,
3702 "UCC Geth", dev);
3703 if (err) {
3704 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3705 dev->name);
3706 ucc_geth_stop(ugeth);
3707 return err;
3708 }
ce973b14 3709
ce973b14
LY		 3710 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3711 if (err) {
3712 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3713 ucc_geth_stop(ugeth);
3714 return err;
3715 }
3716
3717 netif_start_queue(dev);
3718
3719 return err;
3720}
3721
3722/* Stops the kernel queue, and halts the controller */
3723static int ucc_geth_close(struct net_device *dev)
3724{
18a8e864 3725 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14
LY		 3726
3727 ugeth_vdbg("%s: IN", __FUNCTION__);
3728
3729 ucc_geth_stop(ugeth);
3730
728de4c9
KP		 3731 phy_disconnect(ugeth->phydev);
3732 ugeth->phydev = NULL;
ce973b14
LY		 3733
3734 netif_stop_queue(dev);
3735
3736 return 0;
3737}
3738
7282d491 3739const struct ethtool_ops ucc_geth_ethtool_ops = { };
ce973b14 3740
728de4c9
KP		 3741static phy_interface_t to_phy_interface(const char *interface_type)
3742{
3743 if (strcasecmp(interface_type, "mii") == 0)
3744 return PHY_INTERFACE_MODE_MII;
3745 if (strcasecmp(interface_type, "gmii") == 0)
3746 return PHY_INTERFACE_MODE_GMII;
3747 if (strcasecmp(interface_type, "tbi") == 0)
3748 return PHY_INTERFACE_MODE_TBI;
3749 if (strcasecmp(interface_type, "rmii") == 0)
3750 return PHY_INTERFACE_MODE_RMII;
3751 if (strcasecmp(interface_type, "rgmii") == 0)
3752 return PHY_INTERFACE_MODE_RGMII;
3753 if (strcasecmp(interface_type, "rgmii-id") == 0)
3754 return PHY_INTERFACE_MODE_RGMII_ID;
3755 if (strcasecmp(interface_type, "rtbi") == 0)
3756 return PHY_INTERFACE_MODE_RTBI;
3757
3758 return PHY_INTERFACE_MODE_MII;
3759}
3760
18a8e864 3761static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
ce973b14 3762{
18a8e864
LY		 3763 struct device *device = &ofdev->dev;
3764 struct device_node *np = ofdev->node;
728de4c9 3765 struct device_node *mdio;
ce973b14
LY		 3766 struct net_device *dev = NULL;
3767 struct ucc_geth_private *ugeth = NULL;
3768 struct ucc_geth_info *ug_info;
18a8e864
LY		 3769 struct resource res;
3770 struct device_node *phy;
728de4c9 3771 int err, ucc_num, max_speed = 0;
18a8e864
LY		 3772 const phandle *ph;
3773 const unsigned int *prop;
9b4c7a4e 3774 const void *mac_addr;
728de4c9
KP		 3775 phy_interface_t phy_interface;
3776 static const int enet_to_speed[] = {
3777 SPEED_10, SPEED_10, SPEED_10,
3778 SPEED_100, SPEED_100, SPEED_100,
3779 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3780 };
3781 static const phy_interface_t enet_to_phy_interface[] = {
3782 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3783 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3784 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3785 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3786 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3787 };
ce973b14
LY		 3788
3789 ugeth_vdbg("%s: IN", __FUNCTION__);
3790
18a8e864
LY		 3791 prop = get_property(np, "device-id", NULL);
3792 ucc_num = *prop - 1;
3793 if ((ucc_num < 0) || (ucc_num > 7))
3794 return -ENODEV;
3795
3796 ug_info = &ugeth_info[ucc_num];
3797 ug_info->uf_info.ucc_num = ucc_num;
728de4c9 3798
18a8e864
LY		 3799 prop = get_property(np, "rx-clock", NULL);
3800 ug_info->uf_info.rx_clock = *prop;
3801 prop = get_property(np, "tx-clock", NULL);
3802 ug_info->uf_info.tx_clock = *prop;
3803 err = of_address_to_resource(np, 0, &res);
3804 if (err)
3805 return -EINVAL;
3806
3807 ug_info->uf_info.regs = res.start;
3808 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3809
3810 ph = get_property(np, "phy-handle", NULL);
3811 phy = of_find_node_by_phandle(*ph);
ce973b14 3812
18a8e864
LY		 3813 if (phy == NULL)
3814 return -ENODEV;
3815
728de4c9 3816 /* set the PHY address */
18a8e864 3817 prop = get_property(phy, "reg", NULL);
728de4c9
KP		 3818 if (prop == NULL)
3819 return -1;
18a8e864 3820 ug_info->phy_address = *prop;
728de4c9
KP		 3821
3822 /* get the phy interface type, or default to MII */
3823 prop = get_property(np, "interface-type", NULL);
3824 if (!prop) {
3825 /* handle interface property present in old trees */
3826 prop = get_property(phy, "interface", NULL);
3827 if (prop != NULL)
3828 phy_interface = enet_to_phy_interface[*prop];
3829 else
3830 phy_interface = PHY_INTERFACE_MODE_MII;
3831 } else {
3832 phy_interface = to_phy_interface((const char *)prop);
3833 }
3834
3835 /* get speed, or derive from interface */
3836 prop = get_property(np, "max-speed", NULL);
3837 if (!prop) {
3838 /* handle interface property present in old trees */
3839 prop = get_property(phy, "interface", NULL);
3840 if (prop != NULL)
3841 max_speed = enet_to_speed[*prop];
3842 } else {
3843 max_speed = *prop;
3844 }
3845 if (!max_speed) {
3846 switch (phy_interface) {
3847 case PHY_INTERFACE_MODE_GMII:
3848 case PHY_INTERFACE_MODE_RGMII:
3849 case PHY_INTERFACE_MODE_RGMII_ID:
3850 case PHY_INTERFACE_MODE_TBI:
3851 case PHY_INTERFACE_MODE_RTBI:
3852 max_speed = SPEED_1000;
3853 break;
3854 default:
3855 max_speed = SPEED_100;
3856 break;
3857 }
3858 }
3859
3860 if (max_speed == SPEED_1000) {
3861 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3862 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3863 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3864 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3865 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3866 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3867 }
3868
3869 /* Set the bus id */
3870 mdio = of_get_parent(phy);
3871
3872 if (mdio == NULL)
3873 return -1;
3874
3875 err = of_address_to_resource(mdio, 0, &res);
3876 of_node_put(mdio);
3877
3878 if (err)
3879 return -1;
3880
3881 ug_info->mdio_bus = res.start;
ce973b14
LY		 3882
3883 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3884 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3885 ug_info->uf_info.irq);
3886
3887 if (ug_info == NULL) {
3888 ugeth_err("%s: [%d] Missing additional data!", __FUNCTION__,
18a8e864 3889 ucc_num);
ce973b14
LY		 3890 return -ENODEV;
3891 }
3892
ce973b14
LY		 3893 /* Create an ethernet device instance */
3894 dev = alloc_etherdev(sizeof(*ugeth));
3895
3896 if (dev == NULL)
3897 return -ENOMEM;
3898
3899 ugeth = netdev_priv(dev);
3900 spin_lock_init(&ugeth->lock);
3901
3902 dev_set_drvdata(device, dev);
3903
3904 /* Set the dev->base_addr to the gfar reg region */
3905 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3906
3907 SET_MODULE_OWNER(dev);
3908 SET_NETDEV_DEV(dev, device);
3909
3910 /* Fill in the dev structure */
3911 dev->open = ucc_geth_open;
3912 dev->hard_start_xmit = ucc_geth_start_xmit;
3913 dev->tx_timeout = ucc_geth_timeout;
3914 dev->watchdog_timeo = TX_TIMEOUT;
3915#ifdef CONFIG_UGETH_NAPI
3916 dev->poll = ucc_geth_poll;
3917 dev->weight = UCC_GETH_DEV_WEIGHT;
3918#endif /* CONFIG_UGETH_NAPI */
3919 dev->stop = ucc_geth_close;
3920 dev->get_stats = ucc_geth_get_stats;
3921// dev->change_mtu = ucc_geth_change_mtu;
3922 dev->mtu = 1500;
3923 dev->set_multicast_list = ucc_geth_set_multi;
3924 dev->ethtool_ops = &ucc_geth_ethtool_ops;
3925
728de4c9
KP		 3926 ugeth->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
3927 ugeth->phy_interface = phy_interface;
3928 ugeth->max_speed = max_speed;
3929
ce973b14
LY		 3930 err = register_netdev(dev);
3931 if (err) {
3932 ugeth_err("%s: Cannot register net device, aborting.",
3933 dev->name);
3934 free_netdev(dev);
3935 return err;
3936 }
3937
e9eb70c9 3938 mac_addr = of_get_mac_address(np);
9b4c7a4e
LY		 3939 if (mac_addr)
3940 memcpy(dev->dev_addr, mac_addr, 6);
ce973b14 3941
728de4c9
KP		 3942 ugeth->ug_info = ug_info;
3943 ugeth->dev = dev;
3944
ce973b14
LY		 3945 return 0;
3946}
3947
18a8e864 3948static int ucc_geth_remove(struct of_device* ofdev)
ce973b14 3949{
18a8e864 3950 struct device *device = &ofdev->dev;
ce973b14
LY		 3951 struct net_device *dev = dev_get_drvdata(device);
3952 struct ucc_geth_private *ugeth = netdev_priv(dev);
3953
3954 dev_set_drvdata(device, NULL);
3955 ucc_geth_memclean(ugeth);
3956 free_netdev(dev);
3957
3958 return 0;
3959}
3960
18a8e864
LY		 3961static struct of_device_id ucc_geth_match[] = {
3962 {
3963 .type = "network",
3964 .compatible = "ucc_geth",
3965 },
3966 {},
3967};
3968
3969MODULE_DEVICE_TABLE(of, ucc_geth_match);
3970
3971static struct of_platform_driver ucc_geth_driver = {
3972 .name = DRV_NAME,
3973 .match_table = ucc_geth_match,
3974 .probe = ucc_geth_probe,
3975 .remove = ucc_geth_remove,
ce973b14
LY		 3976};
3977
3978static int __init ucc_geth_init(void)
3979{
728de4c9
KP		 3980 int i, ret;
3981
3982 ret = uec_mdio_init();
3983
3984 if (ret)
3985 return ret;
18a8e864 3986
ce973b14
LY		 3987 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
3988 for (i = 0; i < 8; i++)
3989 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3990 sizeof(ugeth_primary_info));
3991
728de4c9
KP		 3992 ret = of_register_platform_driver(&ucc_geth_driver);
3993
3994 if (ret)
3995 uec_mdio_exit();
3996
3997 return ret;
ce973b14
LY		 3998}
3999
4000static void __exit ucc_geth_exit(void)
4001{
a4f0c2ca 4002 of_unregister_platform_driver(&ucc_geth_driver);
728de4c9 4003 uec_mdio_exit();
ce973b14
LY		 4004}
4005
4006module_init(ucc_geth_init);
4007module_exit(ucc_geth_exit);
4008
4009MODULE_AUTHOR("Freescale Semiconductor, Inc");
4010MODULE_DESCRIPTION(DRV_DESC);
4011MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)